1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 300 13 14 /** 15 * dump_phy_type - helper function that prints PHY type strings 16 * @hw: pointer to the HW structure 17 * @phy: 64 bit PHY type to decipher 18 * @i: bit index within phy 19 * @phy_string: string corresponding to bit i in phy 20 * @prefix: prefix string to differentiate multiple dumps 21 */ 22 static void 23 dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string, 24 const char *prefix) 25 { 26 if (phy & BIT_ULL(i)) 27 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i, 28 phy_string); 29 } 30 31 /** 32 * ice_dump_phy_type_low - helper function to dump phy_type_low 33 * @hw: pointer to the HW structure 34 * @low: 64 bit value for phy_type_low 35 * @prefix: prefix string to differentiate multiple dumps 36 */ 37 static void 38 ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix) 39 { 40 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, 41 (unsigned long long)low); 42 43 dump_phy_type(hw, low, 0, "100BASE_TX", prefix); 44 dump_phy_type(hw, low, 1, "100M_SGMII", prefix); 45 dump_phy_type(hw, low, 2, "1000BASE_T", prefix); 46 dump_phy_type(hw, low, 3, "1000BASE_SX", prefix); 47 dump_phy_type(hw, low, 4, "1000BASE_LX", prefix); 48 dump_phy_type(hw, low, 5, "1000BASE_KX", prefix); 49 dump_phy_type(hw, low, 6, "1G_SGMII", prefix); 50 dump_phy_type(hw, low, 7, "2500BASE_T", prefix); 51 dump_phy_type(hw, low, 8, "2500BASE_X", prefix); 52 dump_phy_type(hw, low, 9, "2500BASE_KX", prefix); 53 dump_phy_type(hw, low, 10, "5GBASE_T", prefix); 54 dump_phy_type(hw, low, 11, "5GBASE_KR", prefix); 55 dump_phy_type(hw, low, 12, "10GBASE_T", prefix); 56 dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix); 57 dump_phy_type(hw, low, 14, "10GBASE_SR", prefix); 58 dump_phy_type(hw, low, 15, "10GBASE_LR", prefix); 59 dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix); 60 dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix); 61 dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix); 62 dump_phy_type(hw, low, 19, "25GBASE_T", prefix); 63 dump_phy_type(hw, low, 20, "25GBASE_CR", prefix); 64 dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix); 65 dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix); 66 dump_phy_type(hw, low, 23, "25GBASE_SR", prefix); 67 dump_phy_type(hw, low, 24, "25GBASE_LR", prefix); 68 dump_phy_type(hw, low, 25, "25GBASE_KR", prefix); 69 dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix); 70 dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix); 71 dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix); 72 dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix); 73 dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix); 74 dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix); 75 dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix); 76 dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix); 77 dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix); 78 dump_phy_type(hw, low, 35, "40G_XLAUI", prefix); 79 dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix); 80 dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix); 81 dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix); 82 dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix); 83 dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix); 84 dump_phy_type(hw, low, 41, "50G_LAUI2", prefix); 85 dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix); 86 dump_phy_type(hw, low, 43, "50G_AUI2", prefix); 87 dump_phy_type(hw, low, 44, "50GBASE_CP", prefix); 88 dump_phy_type(hw, low, 45, "50GBASE_SR", prefix); 89 dump_phy_type(hw, low, 46, "50GBASE_FR", prefix); 90 dump_phy_type(hw, low, 47, "50GBASE_LR", prefix); 91 dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix); 92 dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix); 93 dump_phy_type(hw, low, 50, "50G_AUI1", prefix); 94 dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix); 95 dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix); 96 dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix); 97 dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix); 98 dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix); 99 dump_phy_type(hw, low, 56, "100G_CAUI4", prefix); 100 dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix); 101 dump_phy_type(hw, low, 58, "100G_AUI4", prefix); 102 dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix); 103 dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix); 104 dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix); 105 dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix); 106 dump_phy_type(hw, low, 63, "100GBASE_DR", prefix); 107 } 108 109 /** 110 * ice_dump_phy_type_high - helper function to dump phy_type_high 111 * @hw: pointer to the HW structure 112 * @high: 64 bit value for phy_type_high 113 * @prefix: prefix string to differentiate multiple dumps 114 */ 115 static void 116 ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix) 117 { 118 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, 119 (unsigned long long)high); 120 121 dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix); 122 dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix); 123 dump_phy_type(hw, high, 2, "100G_CAUI2", prefix); 124 dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix); 125 dump_phy_type(hw, high, 4, "100G_AUI2", prefix); 126 } 127 128 /** 129 * ice_set_mac_type - Sets MAC type 130 * @hw: pointer to the HW structure 131 * 132 * This function sets the MAC type of the adapter based on the 133 * vendor ID and device ID stored in the HW structure. 134 */ 135 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 136 { 137 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 138 139 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 140 return ICE_ERR_DEVICE_NOT_SUPPORTED; 141 142 switch (hw->device_id) { 143 case ICE_DEV_ID_E810C_BACKPLANE: 144 case ICE_DEV_ID_E810C_QSFP: 145 case ICE_DEV_ID_E810C_SFP: 146 case ICE_DEV_ID_E810_XXV_BACKPLANE: 147 case ICE_DEV_ID_E810_XXV_QSFP: 148 case ICE_DEV_ID_E810_XXV_SFP: 149 hw->mac_type = ICE_MAC_E810; 150 break; 151 case ICE_DEV_ID_E822C_10G_BASE_T: 152 case ICE_DEV_ID_E822C_BACKPLANE: 153 case ICE_DEV_ID_E822C_QSFP: 154 case ICE_DEV_ID_E822C_SFP: 155 case ICE_DEV_ID_E822C_SGMII: 156 case ICE_DEV_ID_E822L_10G_BASE_T: 157 case ICE_DEV_ID_E822L_BACKPLANE: 158 case ICE_DEV_ID_E822L_SFP: 159 case ICE_DEV_ID_E822L_SGMII: 160 case ICE_DEV_ID_E823L_10G_BASE_T: 161 case ICE_DEV_ID_E823L_1GBE: 162 case ICE_DEV_ID_E823L_BACKPLANE: 163 case ICE_DEV_ID_E823L_QSFP: 164 case ICE_DEV_ID_E823L_SFP: 165 case ICE_DEV_ID_E823C_10G_BASE_T: 166 case ICE_DEV_ID_E823C_BACKPLANE: 167 case ICE_DEV_ID_E823C_QSFP: 168 case ICE_DEV_ID_E823C_SFP: 169 case ICE_DEV_ID_E823C_SGMII: 170 hw->mac_type = ICE_MAC_GENERIC; 171 break; 172 default: 173 hw->mac_type = ICE_MAC_UNKNOWN; 174 break; 175 } 176 177 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 178 return ICE_SUCCESS; 179 } 180 181 /** 182 * ice_is_generic_mac 183 * @hw: pointer to the hardware structure 184 * 185 * returns true if mac_type is ICE_MAC_GENERIC, false if not 186 */ 187 bool ice_is_generic_mac(struct ice_hw *hw) 188 { 189 return hw->mac_type == ICE_MAC_GENERIC; 190 } 191 192 /** 193 * ice_is_e810 194 * @hw: pointer to the hardware structure 195 * 196 * returns true if the device is E810 based, false if not. 197 */ 198 bool ice_is_e810(struct ice_hw *hw) 199 { 200 return hw->mac_type == ICE_MAC_E810; 201 } 202 203 /** 204 * ice_is_e810t 205 * @hw: pointer to the hardware structure 206 * 207 * returns true if the device is E810T based, false if not. 208 */ 209 bool ice_is_e810t(struct ice_hw *hw) 210 { 211 return (hw->device_id == ICE_DEV_ID_E810C_SFP && 212 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T); 213 } 214 215 /** 216 * ice_clear_pf_cfg - Clear PF configuration 217 * @hw: pointer to the hardware structure 218 * 219 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 220 * configuration, flow director filters, etc.). 221 */ 222 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 223 { 224 struct ice_aq_desc desc; 225 226 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 227 228 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 229 } 230 231 /** 232 * ice_aq_manage_mac_read - manage MAC address read command 233 * @hw: pointer to the HW struct 234 * @buf: a virtual buffer to hold the manage MAC read response 235 * @buf_size: Size of the virtual buffer 236 * @cd: pointer to command details structure or NULL 237 * 238 * This function is used to return per PF station MAC address (0x0107). 239 * NOTE: Upon successful completion of this command, MAC address information 240 * is returned in user specified buffer. Please interpret user specified 241 * buffer as "manage_mac_read" response. 242 * Response such as various MAC addresses are stored in HW struct (port.mac) 243 * ice_discover_dev_caps is expected to be called before this function is 244 * called. 245 */ 246 static enum ice_status 247 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 248 struct ice_sq_cd *cd) 249 { 250 struct ice_aqc_manage_mac_read_resp *resp; 251 struct ice_aqc_manage_mac_read *cmd; 252 struct ice_aq_desc desc; 253 enum ice_status status; 254 u16 flags; 255 u8 i; 256 257 cmd = &desc.params.mac_read; 258 259 if (buf_size < sizeof(*resp)) 260 return ICE_ERR_BUF_TOO_SHORT; 261 262 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 263 264 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 265 if (status) 266 return status; 267 268 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 269 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 270 271 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 272 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 273 return ICE_ERR_CFG; 274 } 275 276 /* A single port can report up to two (LAN and WoL) addresses */ 277 for (i = 0; i < cmd->num_addr; i++) 278 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 279 ice_memcpy(hw->port_info->mac.lan_addr, 280 resp[i].mac_addr, ETH_ALEN, 281 ICE_DMA_TO_NONDMA); 282 ice_memcpy(hw->port_info->mac.perm_addr, 283 resp[i].mac_addr, 284 ETH_ALEN, ICE_DMA_TO_NONDMA); 285 break; 286 } 287 return ICE_SUCCESS; 288 } 289 290 /** 291 * ice_aq_get_phy_caps - returns PHY capabilities 292 * @pi: port information structure 293 * @qual_mods: report qualified modules 294 * @report_mode: report mode capabilities 295 * @pcaps: structure for PHY capabilities to be filled 296 * @cd: pointer to command details structure or NULL 297 * 298 * Returns the various PHY capabilities supported on the Port (0x0600) 299 */ 300 enum ice_status 301 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 302 struct ice_aqc_get_phy_caps_data *pcaps, 303 struct ice_sq_cd *cd) 304 { 305 struct ice_aqc_get_phy_caps *cmd; 306 u16 pcaps_size = sizeof(*pcaps); 307 struct ice_aq_desc desc; 308 enum ice_status status; 309 const char *prefix; 310 struct ice_hw *hw; 311 312 cmd = &desc.params.get_phy; 313 314 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 315 return ICE_ERR_PARAM; 316 hw = pi->hw; 317 318 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 319 !ice_fw_supports_report_dflt_cfg(hw)) 320 return ICE_ERR_PARAM; 321 322 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 323 324 if (qual_mods) 325 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 326 327 cmd->param0 |= CPU_TO_LE16(report_mode); 328 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 329 330 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 331 332 if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) 333 prefix = "phy_caps_media"; 334 else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA) 335 prefix = "phy_caps_no_media"; 336 else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG) 337 prefix = "phy_caps_active"; 338 else if (report_mode == ICE_AQC_REPORT_DFLT_CFG) 339 prefix = "phy_caps_default"; 340 else 341 prefix = "phy_caps_invalid"; 342 343 ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix); 344 ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix); 345 346 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 347 prefix, report_mode); 348 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 349 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 350 pcaps->low_power_ctrl_an); 351 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 352 pcaps->eee_cap); 353 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 354 pcaps->eeer_value); 355 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 356 pcaps->link_fec_options); 357 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 358 prefix, pcaps->module_compliance_enforcement); 359 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 360 prefix, pcaps->extended_compliance_code); 361 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 362 pcaps->module_type[0]); 363 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 364 pcaps->module_type[1]); 365 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 366 pcaps->module_type[2]); 367 368 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 369 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 370 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 371 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 372 sizeof(pi->phy.link_info.module_type), 373 ICE_NONDMA_TO_NONDMA); 374 } 375 376 return status; 377 } 378 379 /** 380 * ice_aq_get_link_topo_handle - get link topology node return status 381 * @pi: port information structure 382 * @node_type: requested node type 383 * @cd: pointer to command details structure or NULL 384 * 385 * Get link topology node return status for specified node type (0x06E0) 386 * 387 * Node type cage can be used to determine if cage is present. If AQC 388 * returns error (ENOENT), then no cage present. If no cage present, then 389 * connection type is backplane or BASE-T. 390 */ 391 static enum ice_status 392 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 393 struct ice_sq_cd *cd) 394 { 395 struct ice_aqc_get_link_topo *cmd; 396 struct ice_aq_desc desc; 397 398 cmd = &desc.params.get_link_topo; 399 400 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 401 402 cmd->addr.topo_params.node_type_ctx = 403 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 404 ICE_AQC_LINK_TOPO_NODE_CTX_S); 405 406 /* set node type */ 407 cmd->addr.topo_params.node_type_ctx |= 408 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 409 410 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 411 } 412 413 /** 414 * ice_is_media_cage_present 415 * @pi: port information structure 416 * 417 * Returns true if media cage is present, else false. If no cage, then 418 * media type is backplane or BASE-T. 419 */ 420 static bool ice_is_media_cage_present(struct ice_port_info *pi) 421 { 422 /* Node type cage can be used to determine if cage is present. If AQC 423 * returns error (ENOENT), then no cage present. If no cage present then 424 * connection type is backplane or BASE-T. 425 */ 426 return !ice_aq_get_link_topo_handle(pi, 427 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 428 NULL); 429 } 430 431 /** 432 * ice_get_media_type - Gets media type 433 * @pi: port information structure 434 */ 435 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 436 { 437 struct ice_link_status *hw_link_info; 438 439 if (!pi) 440 return ICE_MEDIA_UNKNOWN; 441 442 hw_link_info = &pi->phy.link_info; 443 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 444 /* If more than one media type is selected, report unknown */ 445 return ICE_MEDIA_UNKNOWN; 446 447 if (hw_link_info->phy_type_low) { 448 /* 1G SGMII is a special case where some DA cable PHYs 449 * may show this as an option when it really shouldn't 450 * be since SGMII is meant to be between a MAC and a PHY 451 * in a backplane. Try to detect this case and handle it 452 */ 453 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 454 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 455 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 456 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 457 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 458 return ICE_MEDIA_DA; 459 460 switch (hw_link_info->phy_type_low) { 461 case ICE_PHY_TYPE_LOW_1000BASE_SX: 462 case ICE_PHY_TYPE_LOW_1000BASE_LX: 463 case ICE_PHY_TYPE_LOW_10GBASE_SR: 464 case ICE_PHY_TYPE_LOW_10GBASE_LR: 465 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 466 case ICE_PHY_TYPE_LOW_25GBASE_SR: 467 case ICE_PHY_TYPE_LOW_25GBASE_LR: 468 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 469 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 470 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 471 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 472 case ICE_PHY_TYPE_LOW_50GBASE_SR: 473 case ICE_PHY_TYPE_LOW_50GBASE_FR: 474 case ICE_PHY_TYPE_LOW_50GBASE_LR: 475 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 476 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 477 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 478 case ICE_PHY_TYPE_LOW_100GBASE_DR: 479 return ICE_MEDIA_FIBER; 480 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 481 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 482 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 483 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 484 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 485 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 486 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 487 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 488 return ICE_MEDIA_FIBER; 489 case ICE_PHY_TYPE_LOW_100BASE_TX: 490 case ICE_PHY_TYPE_LOW_1000BASE_T: 491 case ICE_PHY_TYPE_LOW_2500BASE_T: 492 case ICE_PHY_TYPE_LOW_5GBASE_T: 493 case ICE_PHY_TYPE_LOW_10GBASE_T: 494 case ICE_PHY_TYPE_LOW_25GBASE_T: 495 return ICE_MEDIA_BASET; 496 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 497 case ICE_PHY_TYPE_LOW_25GBASE_CR: 498 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 499 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 500 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 501 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 502 case ICE_PHY_TYPE_LOW_50GBASE_CP: 503 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 504 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 505 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 506 return ICE_MEDIA_DA; 507 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 508 case ICE_PHY_TYPE_LOW_40G_XLAUI: 509 case ICE_PHY_TYPE_LOW_50G_LAUI2: 510 case ICE_PHY_TYPE_LOW_50G_AUI2: 511 case ICE_PHY_TYPE_LOW_50G_AUI1: 512 case ICE_PHY_TYPE_LOW_100G_AUI4: 513 case ICE_PHY_TYPE_LOW_100G_CAUI4: 514 if (ice_is_media_cage_present(pi)) 515 return ICE_MEDIA_AUI; 516 /* fall-through */ 517 case ICE_PHY_TYPE_LOW_1000BASE_KX: 518 case ICE_PHY_TYPE_LOW_2500BASE_KX: 519 case ICE_PHY_TYPE_LOW_2500BASE_X: 520 case ICE_PHY_TYPE_LOW_5GBASE_KR: 521 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 522 case ICE_PHY_TYPE_LOW_25GBASE_KR: 523 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 524 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 525 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 526 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 527 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 528 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 529 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 530 return ICE_MEDIA_BACKPLANE; 531 } 532 } else { 533 switch (hw_link_info->phy_type_high) { 534 case ICE_PHY_TYPE_HIGH_100G_AUI2: 535 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 536 if (ice_is_media_cage_present(pi)) 537 return ICE_MEDIA_AUI; 538 /* fall-through */ 539 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 540 return ICE_MEDIA_BACKPLANE; 541 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 542 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 543 return ICE_MEDIA_FIBER; 544 } 545 } 546 return ICE_MEDIA_UNKNOWN; 547 } 548 549 /** 550 * ice_aq_get_link_info 551 * @pi: port information structure 552 * @ena_lse: enable/disable LinkStatusEvent reporting 553 * @link: pointer to link status structure - optional 554 * @cd: pointer to command details structure or NULL 555 * 556 * Get Link Status (0x607). Returns the link status of the adapter. 557 */ 558 enum ice_status 559 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 560 struct ice_link_status *link, struct ice_sq_cd *cd) 561 { 562 struct ice_aqc_get_link_status_data link_data = { 0 }; 563 struct ice_aqc_get_link_status *resp; 564 struct ice_link_status *li_old, *li; 565 enum ice_media_type *hw_media_type; 566 struct ice_fc_info *hw_fc_info; 567 bool tx_pause, rx_pause; 568 struct ice_aq_desc desc; 569 enum ice_status status; 570 struct ice_hw *hw; 571 u16 cmd_flags; 572 573 if (!pi) 574 return ICE_ERR_PARAM; 575 hw = pi->hw; 576 li_old = &pi->phy.link_info_old; 577 hw_media_type = &pi->phy.media_type; 578 li = &pi->phy.link_info; 579 hw_fc_info = &pi->fc; 580 581 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 582 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 583 resp = &desc.params.get_link_status; 584 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 585 resp->lport_num = pi->lport; 586 587 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 588 589 if (status != ICE_SUCCESS) 590 return status; 591 592 /* save off old link status information */ 593 *li_old = *li; 594 595 /* update current link status information */ 596 li->link_speed = LE16_TO_CPU(link_data.link_speed); 597 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 598 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 599 *hw_media_type = ice_get_media_type(pi); 600 li->link_info = link_data.link_info; 601 li->link_cfg_err = link_data.link_cfg_err; 602 li->an_info = link_data.an_info; 603 li->ext_info = link_data.ext_info; 604 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 605 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 606 li->topo_media_conflict = link_data.topo_media_conflict; 607 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 608 ICE_AQ_CFG_PACING_TYPE_M); 609 610 /* update fc info */ 611 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 612 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 613 if (tx_pause && rx_pause) 614 hw_fc_info->current_mode = ICE_FC_FULL; 615 else if (tx_pause) 616 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 617 else if (rx_pause) 618 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 619 else 620 hw_fc_info->current_mode = ICE_FC_NONE; 621 622 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 623 624 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 625 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 626 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 627 (unsigned long long)li->phy_type_low); 628 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 629 (unsigned long long)li->phy_type_high); 630 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 631 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 632 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 633 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 634 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 635 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 636 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 637 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 638 li->max_frame_size); 639 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 640 641 /* save link status information */ 642 if (link) 643 *link = *li; 644 645 /* flag cleared so calling functions don't call AQ again */ 646 pi->phy.get_link_info = false; 647 648 return ICE_SUCCESS; 649 } 650 651 /** 652 * ice_fill_tx_timer_and_fc_thresh 653 * @hw: pointer to the HW struct 654 * @cmd: pointer to MAC cfg structure 655 * 656 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 657 * descriptor 658 */ 659 static void 660 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 661 struct ice_aqc_set_mac_cfg *cmd) 662 { 663 u16 fc_thres_val, tx_timer_val; 664 u32 val; 665 666 /* We read back the transmit timer and fc threshold value of 667 * LFC. Thus, we will use index = 668 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 669 * 670 * Also, because we are opearating on transmit timer and fc 671 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 672 */ 673 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 674 675 /* Retrieve the transmit timer */ 676 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 677 tx_timer_val = val & 678 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 679 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 680 681 /* Retrieve the fc threshold */ 682 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 683 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 684 685 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 686 } 687 688 /** 689 * ice_aq_set_mac_cfg 690 * @hw: pointer to the HW struct 691 * @max_frame_size: Maximum Frame Size to be supported 692 * @cd: pointer to command details structure or NULL 693 * 694 * Set MAC configuration (0x0603) 695 */ 696 enum ice_status 697 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 698 { 699 struct ice_aqc_set_mac_cfg *cmd; 700 struct ice_aq_desc desc; 701 702 cmd = &desc.params.set_mac_cfg; 703 704 if (max_frame_size == 0) 705 return ICE_ERR_PARAM; 706 707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 708 709 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 710 711 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 712 713 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 714 } 715 716 /** 717 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 718 * @hw: pointer to the HW struct 719 */ 720 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 721 { 722 struct ice_switch_info *sw; 723 enum ice_status status; 724 725 hw->switch_info = (struct ice_switch_info *) 726 ice_malloc(hw, sizeof(*hw->switch_info)); 727 728 sw = hw->switch_info; 729 730 if (!sw) 731 return ICE_ERR_NO_MEMORY; 732 733 INIT_LIST_HEAD(&sw->vsi_list_map_head); 734 sw->prof_res_bm_init = 0; 735 736 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 737 if (status) { 738 ice_free(hw, hw->switch_info); 739 return status; 740 } 741 return ICE_SUCCESS; 742 } 743 744 /** 745 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 746 * @hw: pointer to the HW struct 747 * @sw: pointer to switch info struct for which function clears filters 748 */ 749 static void 750 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 751 { 752 struct ice_vsi_list_map_info *v_pos_map; 753 struct ice_vsi_list_map_info *v_tmp_map; 754 struct ice_sw_recipe *recps; 755 u8 i; 756 757 if (!sw) 758 return; 759 760 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 761 ice_vsi_list_map_info, list_entry) { 762 LIST_DEL(&v_pos_map->list_entry); 763 ice_free(hw, v_pos_map); 764 } 765 recps = sw->recp_list; 766 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 767 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 768 769 recps[i].root_rid = i; 770 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 771 &recps[i].rg_list, ice_recp_grp_entry, 772 l_entry) { 773 LIST_DEL(&rg_entry->l_entry); 774 ice_free(hw, rg_entry); 775 } 776 777 if (recps[i].adv_rule) { 778 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 779 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 780 781 ice_destroy_lock(&recps[i].filt_rule_lock); 782 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 783 &recps[i].filt_rules, 784 ice_adv_fltr_mgmt_list_entry, 785 list_entry) { 786 LIST_DEL(&lst_itr->list_entry); 787 ice_free(hw, lst_itr->lkups); 788 ice_free(hw, lst_itr); 789 } 790 } else { 791 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 792 793 ice_destroy_lock(&recps[i].filt_rule_lock); 794 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 795 &recps[i].filt_rules, 796 ice_fltr_mgmt_list_entry, 797 list_entry) { 798 LIST_DEL(&lst_itr->list_entry); 799 ice_free(hw, lst_itr); 800 } 801 } 802 if (recps[i].root_buf) 803 ice_free(hw, recps[i].root_buf); 804 } 805 ice_rm_sw_replay_rule_info(hw, sw); 806 ice_free(hw, sw->recp_list); 807 ice_free(hw, sw); 808 } 809 810 /** 811 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 812 * @hw: pointer to the HW struct 813 */ 814 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 815 { 816 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 817 } 818 819 /** 820 * ice_get_itr_intrl_gran 821 * @hw: pointer to the HW struct 822 * 823 * Determines the ITR/INTRL granularities based on the maximum aggregate 824 * bandwidth according to the device's configuration during power-on. 825 */ 826 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 827 { 828 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 829 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 830 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 831 832 switch (max_agg_bw) { 833 case ICE_MAX_AGG_BW_200G: 834 case ICE_MAX_AGG_BW_100G: 835 case ICE_MAX_AGG_BW_50G: 836 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 837 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 838 break; 839 case ICE_MAX_AGG_BW_25G: 840 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 841 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 842 break; 843 } 844 } 845 846 /** 847 * ice_print_rollback_msg - print FW rollback message 848 * @hw: pointer to the hardware structure 849 */ 850 void ice_print_rollback_msg(struct ice_hw *hw) 851 { 852 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 853 struct ice_orom_info *orom; 854 struct ice_nvm_info *nvm; 855 856 orom = &hw->flash.orom; 857 nvm = &hw->flash.nvm; 858 859 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 860 nvm->major, nvm->minor, nvm->eetrack, orom->major, 861 orom->build, orom->patch); 862 ice_warn(hw, 863 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 864 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 865 } 866 867 /** 868 * ice_set_umac_shared 869 * @hw: pointer to the hw struct 870 * 871 * Set boolean flag to allow unicast MAC sharing 872 */ 873 void ice_set_umac_shared(struct ice_hw *hw) 874 { 875 hw->umac_shared = true; 876 } 877 878 /** 879 * ice_init_hw - main hardware initialization routine 880 * @hw: pointer to the hardware structure 881 */ 882 enum ice_status ice_init_hw(struct ice_hw *hw) 883 { 884 struct ice_aqc_get_phy_caps_data *pcaps; 885 enum ice_status status; 886 u16 mac_buf_len; 887 void *mac_buf; 888 889 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 890 891 /* Set MAC type based on DeviceID */ 892 status = ice_set_mac_type(hw); 893 if (status) 894 return status; 895 896 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 897 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 898 PF_FUNC_RID_FUNCTION_NUMBER_S; 899 900 status = ice_reset(hw, ICE_RESET_PFR); 901 if (status) 902 return status; 903 904 ice_get_itr_intrl_gran(hw); 905 906 status = ice_create_all_ctrlq(hw); 907 if (status) 908 goto err_unroll_cqinit; 909 910 status = ice_init_nvm(hw); 911 if (status) 912 goto err_unroll_cqinit; 913 914 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 915 ice_print_rollback_msg(hw); 916 917 status = ice_clear_pf_cfg(hw); 918 if (status) 919 goto err_unroll_cqinit; 920 921 /* Set bit to enable Flow Director filters */ 922 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 923 INIT_LIST_HEAD(&hw->fdir_list_head); 924 925 ice_clear_pxe_mode(hw); 926 927 status = ice_get_caps(hw); 928 if (status) 929 goto err_unroll_cqinit; 930 931 hw->port_info = (struct ice_port_info *) 932 ice_malloc(hw, sizeof(*hw->port_info)); 933 if (!hw->port_info) { 934 status = ICE_ERR_NO_MEMORY; 935 goto err_unroll_cqinit; 936 } 937 938 /* set the back pointer to HW */ 939 hw->port_info->hw = hw; 940 941 /* Initialize port_info struct with switch configuration data */ 942 status = ice_get_initial_sw_cfg(hw); 943 if (status) 944 goto err_unroll_alloc; 945 946 hw->evb_veb = true; 947 /* Query the allocated resources for Tx scheduler */ 948 status = ice_sched_query_res_alloc(hw); 949 if (status) { 950 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 951 goto err_unroll_alloc; 952 } 953 ice_sched_get_psm_clk_freq(hw); 954 955 /* Initialize port_info struct with scheduler data */ 956 status = ice_sched_init_port(hw->port_info); 957 if (status) 958 goto err_unroll_sched; 959 pcaps = (struct ice_aqc_get_phy_caps_data *) 960 ice_malloc(hw, sizeof(*pcaps)); 961 if (!pcaps) { 962 status = ICE_ERR_NO_MEMORY; 963 goto err_unroll_sched; 964 } 965 966 /* Initialize port_info struct with PHY capabilities */ 967 status = ice_aq_get_phy_caps(hw->port_info, false, 968 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); 969 ice_free(hw, pcaps); 970 if (status) 971 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", 972 status); 973 974 /* Initialize port_info struct with link information */ 975 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 976 if (status) 977 goto err_unroll_sched; 978 /* need a valid SW entry point to build a Tx tree */ 979 if (!hw->sw_entry_point_layer) { 980 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 981 status = ICE_ERR_CFG; 982 goto err_unroll_sched; 983 } 984 INIT_LIST_HEAD(&hw->agg_list); 985 /* Initialize max burst size */ 986 if (!hw->max_burst_size) 987 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 988 status = ice_init_fltr_mgmt_struct(hw); 989 if (status) 990 goto err_unroll_sched; 991 992 /* Get MAC information */ 993 /* A single port can report up to two (LAN and WoL) addresses */ 994 mac_buf = ice_calloc(hw, 2, 995 sizeof(struct ice_aqc_manage_mac_read_resp)); 996 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 997 998 if (!mac_buf) { 999 status = ICE_ERR_NO_MEMORY; 1000 goto err_unroll_fltr_mgmt_struct; 1001 } 1002 1003 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1004 ice_free(hw, mac_buf); 1005 1006 if (status) 1007 goto err_unroll_fltr_mgmt_struct; 1008 1009 /* enable jumbo frame support at MAC level */ 1010 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1011 if (status) 1012 goto err_unroll_fltr_mgmt_struct; 1013 1014 /* Obtain counter base index which would be used by flow director */ 1015 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1016 if (status) 1017 goto err_unroll_fltr_mgmt_struct; 1018 status = ice_init_hw_tbls(hw); 1019 if (status) 1020 goto err_unroll_fltr_mgmt_struct; 1021 ice_init_lock(&hw->tnl_lock); 1022 1023 return ICE_SUCCESS; 1024 1025 err_unroll_fltr_mgmt_struct: 1026 ice_cleanup_fltr_mgmt_struct(hw); 1027 err_unroll_sched: 1028 ice_sched_cleanup_all(hw); 1029 err_unroll_alloc: 1030 ice_free(hw, hw->port_info); 1031 hw->port_info = NULL; 1032 err_unroll_cqinit: 1033 ice_destroy_all_ctrlq(hw); 1034 return status; 1035 } 1036 1037 /** 1038 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1039 * @hw: pointer to the hardware structure 1040 * 1041 * This should be called only during nominal operation, not as a result of 1042 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1043 * applicable initializations if it fails for any reason. 1044 */ 1045 void ice_deinit_hw(struct ice_hw *hw) 1046 { 1047 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1048 ice_cleanup_fltr_mgmt_struct(hw); 1049 1050 ice_sched_cleanup_all(hw); 1051 ice_sched_clear_agg(hw); 1052 ice_free_seg(hw); 1053 ice_free_hw_tbls(hw); 1054 ice_destroy_lock(&hw->tnl_lock); 1055 1056 if (hw->port_info) { 1057 ice_free(hw, hw->port_info); 1058 hw->port_info = NULL; 1059 } 1060 1061 ice_destroy_all_ctrlq(hw); 1062 1063 /* Clear VSI contexts if not already cleared */ 1064 ice_clear_all_vsi_ctx(hw); 1065 } 1066 1067 /** 1068 * ice_check_reset - Check to see if a global reset is complete 1069 * @hw: pointer to the hardware structure 1070 */ 1071 enum ice_status ice_check_reset(struct ice_hw *hw) 1072 { 1073 u32 cnt, reg = 0, grst_timeout, uld_mask; 1074 1075 /* Poll for Device Active state in case a recent CORER, GLOBR, 1076 * or EMPR has occurred. The grst delay value is in 100ms units. 1077 * Add 1sec for outstanding AQ commands that can take a long time. 1078 */ 1079 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1080 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1081 1082 for (cnt = 0; cnt < grst_timeout; cnt++) { 1083 ice_msec_delay(100, true); 1084 reg = rd32(hw, GLGEN_RSTAT); 1085 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1086 break; 1087 } 1088 1089 if (cnt == grst_timeout) { 1090 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1091 return ICE_ERR_RESET_FAILED; 1092 } 1093 1094 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1095 GLNVM_ULD_PCIER_DONE_1_M |\ 1096 GLNVM_ULD_CORER_DONE_M |\ 1097 GLNVM_ULD_GLOBR_DONE_M |\ 1098 GLNVM_ULD_POR_DONE_M |\ 1099 GLNVM_ULD_POR_DONE_1_M |\ 1100 GLNVM_ULD_PCIER_DONE_2_M) 1101 1102 uld_mask = ICE_RESET_DONE_MASK; 1103 1104 /* Device is Active; check Global Reset processes are done */ 1105 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1106 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1107 if (reg == uld_mask) { 1108 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1109 break; 1110 } 1111 ice_msec_delay(10, true); 1112 } 1113 1114 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1115 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1116 reg); 1117 return ICE_ERR_RESET_FAILED; 1118 } 1119 1120 return ICE_SUCCESS; 1121 } 1122 1123 /** 1124 * ice_pf_reset - Reset the PF 1125 * @hw: pointer to the hardware structure 1126 * 1127 * If a global reset has been triggered, this function checks 1128 * for its completion and then issues the PF reset 1129 */ 1130 static enum ice_status ice_pf_reset(struct ice_hw *hw) 1131 { 1132 u32 cnt, reg; 1133 1134 /* If at function entry a global reset was already in progress, i.e. 1135 * state is not 'device active' or any of the reset done bits are not 1136 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1137 * global reset is done. 1138 */ 1139 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1140 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1141 /* poll on global reset currently in progress until done */ 1142 if (ice_check_reset(hw)) 1143 return ICE_ERR_RESET_FAILED; 1144 1145 return ICE_SUCCESS; 1146 } 1147 1148 /* Reset the PF */ 1149 reg = rd32(hw, PFGEN_CTRL); 1150 1151 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1152 1153 /* Wait for the PFR to complete. The wait time is the global config lock 1154 * timeout plus the PFR timeout which will account for a possible reset 1155 * that is occurring during a download package operation. 1156 */ 1157 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1158 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1159 reg = rd32(hw, PFGEN_CTRL); 1160 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1161 break; 1162 1163 ice_msec_delay(1, true); 1164 } 1165 1166 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1167 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1168 return ICE_ERR_RESET_FAILED; 1169 } 1170 1171 return ICE_SUCCESS; 1172 } 1173 1174 /** 1175 * ice_reset - Perform different types of reset 1176 * @hw: pointer to the hardware structure 1177 * @req: reset request 1178 * 1179 * This function triggers a reset as specified by the req parameter. 1180 * 1181 * Note: 1182 * If anything other than a PF reset is triggered, PXE mode is restored. 1183 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1184 * interface has been restored in the rebuild flow. 1185 */ 1186 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1187 { 1188 u32 val = 0; 1189 1190 switch (req) { 1191 case ICE_RESET_PFR: 1192 return ice_pf_reset(hw); 1193 case ICE_RESET_CORER: 1194 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1195 val = GLGEN_RTRIG_CORER_M; 1196 break; 1197 case ICE_RESET_GLOBR: 1198 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1199 val = GLGEN_RTRIG_GLOBR_M; 1200 break; 1201 default: 1202 return ICE_ERR_PARAM; 1203 } 1204 1205 val |= rd32(hw, GLGEN_RTRIG); 1206 wr32(hw, GLGEN_RTRIG, val); 1207 ice_flush(hw); 1208 1209 /* wait for the FW to be ready */ 1210 return ice_check_reset(hw); 1211 } 1212 1213 /** 1214 * ice_copy_rxq_ctx_to_hw 1215 * @hw: pointer to the hardware structure 1216 * @ice_rxq_ctx: pointer to the rxq context 1217 * @rxq_index: the index of the Rx queue 1218 * 1219 * Copies rxq context from dense structure to HW register space 1220 */ 1221 static enum ice_status 1222 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1223 { 1224 u8 i; 1225 1226 if (!ice_rxq_ctx) 1227 return ICE_ERR_BAD_PTR; 1228 1229 if (rxq_index > QRX_CTRL_MAX_INDEX) 1230 return ICE_ERR_PARAM; 1231 1232 /* Copy each dword separately to HW */ 1233 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1234 wr32(hw, QRX_CONTEXT(i, rxq_index), 1235 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1236 1237 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1238 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1239 } 1240 1241 return ICE_SUCCESS; 1242 } 1243 1244 /* LAN Rx Queue Context */ 1245 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1246 /* Field Width LSB */ 1247 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1248 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1249 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1250 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1251 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1252 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1253 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1254 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1255 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1256 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1257 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1258 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1259 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1260 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1261 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1262 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1263 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1264 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1265 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1266 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1267 { 0 } 1268 }; 1269 1270 /** 1271 * ice_write_rxq_ctx 1272 * @hw: pointer to the hardware structure 1273 * @rlan_ctx: pointer to the rxq context 1274 * @rxq_index: the index of the Rx queue 1275 * 1276 * Converts rxq context from sparse to dense structure and then writes 1277 * it to HW register space and enables the hardware to prefetch descriptors 1278 * instead of only fetching them on demand 1279 */ 1280 enum ice_status 1281 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1282 u32 rxq_index) 1283 { 1284 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1285 1286 if (!rlan_ctx) 1287 return ICE_ERR_BAD_PTR; 1288 1289 rlan_ctx->prefena = 1; 1290 1291 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1292 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1293 } 1294 1295 /** 1296 * ice_clear_rxq_ctx 1297 * @hw: pointer to the hardware structure 1298 * @rxq_index: the index of the Rx queue to clear 1299 * 1300 * Clears rxq context in HW register space 1301 */ 1302 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1303 { 1304 u8 i; 1305 1306 if (rxq_index > QRX_CTRL_MAX_INDEX) 1307 return ICE_ERR_PARAM; 1308 1309 /* Clear each dword register separately */ 1310 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1311 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1312 1313 return ICE_SUCCESS; 1314 } 1315 1316 /* LAN Tx Queue Context */ 1317 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1318 /* Field Width LSB */ 1319 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1320 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1321 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1322 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1323 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1324 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1325 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1326 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1327 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1328 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1329 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1330 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1331 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1332 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1333 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1334 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1335 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1336 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1337 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1338 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1339 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1340 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1341 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1342 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1343 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1344 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1345 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1346 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1347 { 0 } 1348 }; 1349 1350 /** 1351 * ice_copy_tx_cmpltnq_ctx_to_hw 1352 * @hw: pointer to the hardware structure 1353 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1354 * @tx_cmpltnq_index: the index of the completion queue 1355 * 1356 * Copies Tx completion queue context from dense structure to HW register space 1357 */ 1358 static enum ice_status 1359 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1360 u32 tx_cmpltnq_index) 1361 { 1362 u8 i; 1363 1364 if (!ice_tx_cmpltnq_ctx) 1365 return ICE_ERR_BAD_PTR; 1366 1367 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1368 return ICE_ERR_PARAM; 1369 1370 /* Copy each dword separately to HW */ 1371 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1372 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1373 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1374 1375 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1376 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1377 } 1378 1379 return ICE_SUCCESS; 1380 } 1381 1382 /* LAN Tx Completion Queue Context */ 1383 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1384 /* Field Width LSB */ 1385 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1386 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1387 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1388 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1389 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1390 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1391 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1392 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1393 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1394 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1395 { 0 } 1396 }; 1397 1398 /** 1399 * ice_write_tx_cmpltnq_ctx 1400 * @hw: pointer to the hardware structure 1401 * @tx_cmpltnq_ctx: pointer to the completion queue context 1402 * @tx_cmpltnq_index: the index of the completion queue 1403 * 1404 * Converts completion queue context from sparse to dense structure and then 1405 * writes it to HW register space 1406 */ 1407 enum ice_status 1408 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1409 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1410 u32 tx_cmpltnq_index) 1411 { 1412 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1413 1414 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1415 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1416 } 1417 1418 /** 1419 * ice_clear_tx_cmpltnq_ctx 1420 * @hw: pointer to the hardware structure 1421 * @tx_cmpltnq_index: the index of the completion queue to clear 1422 * 1423 * Clears Tx completion queue context in HW register space 1424 */ 1425 enum ice_status 1426 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1427 { 1428 u8 i; 1429 1430 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1431 return ICE_ERR_PARAM; 1432 1433 /* Clear each dword register separately */ 1434 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1435 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1436 1437 return ICE_SUCCESS; 1438 } 1439 1440 /** 1441 * ice_copy_tx_drbell_q_ctx_to_hw 1442 * @hw: pointer to the hardware structure 1443 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1444 * @tx_drbell_q_index: the index of the doorbell queue 1445 * 1446 * Copies doorbell queue context from dense structure to HW register space 1447 */ 1448 static enum ice_status 1449 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1450 u32 tx_drbell_q_index) 1451 { 1452 u8 i; 1453 1454 if (!ice_tx_drbell_q_ctx) 1455 return ICE_ERR_BAD_PTR; 1456 1457 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1458 return ICE_ERR_PARAM; 1459 1460 /* Copy each dword separately to HW */ 1461 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1462 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1463 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1464 1465 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1466 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1467 } 1468 1469 return ICE_SUCCESS; 1470 } 1471 1472 /* LAN Tx Doorbell Queue Context info */ 1473 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1474 /* Field Width LSB */ 1475 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1476 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1477 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1478 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1479 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1480 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1481 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1482 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1483 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1484 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1485 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1486 { 0 } 1487 }; 1488 1489 /** 1490 * ice_write_tx_drbell_q_ctx 1491 * @hw: pointer to the hardware structure 1492 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1493 * @tx_drbell_q_index: the index of the doorbell queue 1494 * 1495 * Converts doorbell queue context from sparse to dense structure and then 1496 * writes it to HW register space 1497 */ 1498 enum ice_status 1499 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1500 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1501 u32 tx_drbell_q_index) 1502 { 1503 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1504 1505 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 1506 ice_tx_drbell_q_ctx_info); 1507 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1508 } 1509 1510 /** 1511 * ice_clear_tx_drbell_q_ctx 1512 * @hw: pointer to the hardware structure 1513 * @tx_drbell_q_index: the index of the doorbell queue to clear 1514 * 1515 * Clears doorbell queue context in HW register space 1516 */ 1517 enum ice_status 1518 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1519 { 1520 u8 i; 1521 1522 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1523 return ICE_ERR_PARAM; 1524 1525 /* Clear each dword register separately */ 1526 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1527 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1528 1529 return ICE_SUCCESS; 1530 } 1531 1532 /* Sideband Queue command wrappers */ 1533 1534 /** 1535 * ice_get_sbq - returns the right control queue to use for sideband 1536 * @hw: pointer to the hardware structure 1537 */ 1538 static struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw) 1539 { 1540 if (!ice_is_generic_mac(hw)) 1541 return &hw->adminq; 1542 return &hw->sbq; 1543 } 1544 1545 /** 1546 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1547 * @hw: pointer to the HW struct 1548 * @desc: descriptor describing the command 1549 * @buf: buffer to use for indirect commands (NULL for direct commands) 1550 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1551 * @cd: pointer to command details structure 1552 */ 1553 static enum ice_status 1554 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1555 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1556 { 1557 return ice_sq_send_cmd(hw, ice_get_sbq(hw), (struct ice_aq_desc *)desc, 1558 buf, buf_size, cd); 1559 } 1560 1561 /** 1562 * ice_sbq_send_cmd_nolock - send Sideband Queue command to Sideband Queue 1563 * but do not lock sq_lock 1564 * @hw: pointer to the HW struct 1565 * @desc: descriptor describing the command 1566 * @buf: buffer to use for indirect commands (NULL for direct commands) 1567 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1568 * @cd: pointer to command details structure 1569 */ 1570 static enum ice_status 1571 ice_sbq_send_cmd_nolock(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1572 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1573 { 1574 return ice_sq_send_cmd_nolock(hw, ice_get_sbq(hw), 1575 (struct ice_aq_desc *)desc, buf, 1576 buf_size, cd); 1577 } 1578 1579 /** 1580 * ice_sbq_rw_reg_lp - Fill Sideband Queue command, with lock parameter 1581 * @hw: pointer to the HW struct 1582 * @in: message info to be filled in descriptor 1583 * @lock: true to lock the sq_lock (the usual case); false if the sq_lock has 1584 * already been locked at a higher level 1585 */ 1586 enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw, 1587 struct ice_sbq_msg_input *in, bool lock) 1588 { 1589 struct ice_sbq_cmd_desc desc = {0}; 1590 struct ice_sbq_msg_req msg = {0}; 1591 enum ice_status status; 1592 u16 msg_len; 1593 1594 msg_len = sizeof(msg); 1595 1596 msg.dest_dev = in->dest_dev; 1597 msg.opcode = in->opcode; 1598 msg.flags = ICE_SBQ_MSG_FLAGS; 1599 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1600 msg.msg_addr_low = CPU_TO_LE16(in->msg_addr_low); 1601 msg.msg_addr_high = CPU_TO_LE32(in->msg_addr_high); 1602 1603 if (in->opcode) 1604 msg.data = CPU_TO_LE32(in->data); 1605 else 1606 /* data read comes back in completion, so shorten the struct by 1607 * sizeof(msg.data) 1608 */ 1609 msg_len -= sizeof(msg.data); 1610 1611 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 1612 desc.opcode = CPU_TO_LE16(ice_sbq_opc_neigh_dev_req); 1613 desc.param0.cmd_len = CPU_TO_LE16(msg_len); 1614 if (lock) 1615 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1616 else 1617 status = ice_sbq_send_cmd_nolock(hw, &desc, &msg, msg_len, 1618 NULL); 1619 if (!status && !in->opcode) 1620 in->data = LE32_TO_CPU 1621 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1622 return status; 1623 } 1624 1625 /** 1626 * ice_sbq_rw_reg - Fill Sideband Queue command 1627 * @hw: pointer to the HW struct 1628 * @in: message info to be filled in descriptor 1629 */ 1630 enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1631 { 1632 return ice_sbq_rw_reg_lp(hw, in, true); 1633 } 1634 1635 /** 1636 * ice_sbq_lock - Lock the sideband queue's sq_lock 1637 * @hw: pointer to the HW struct 1638 */ 1639 void ice_sbq_lock(struct ice_hw *hw) 1640 { 1641 ice_acquire_lock(&ice_get_sbq(hw)->sq_lock); 1642 } 1643 1644 /** 1645 * ice_sbq_unlock - Unlock the sideband queue's sq_lock 1646 * @hw: pointer to the HW struct 1647 */ 1648 void ice_sbq_unlock(struct ice_hw *hw) 1649 { 1650 ice_release_lock(&ice_get_sbq(hw)->sq_lock); 1651 } 1652 1653 /* FW Admin Queue command wrappers */ 1654 1655 /** 1656 * ice_should_retry_sq_send_cmd 1657 * @opcode: AQ opcode 1658 * 1659 * Decide if we should retry the send command routine for the ATQ, depending 1660 * on the opcode. 1661 */ 1662 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1663 { 1664 switch (opcode) { 1665 case ice_aqc_opc_get_link_topo: 1666 case ice_aqc_opc_lldp_stop: 1667 case ice_aqc_opc_lldp_start: 1668 case ice_aqc_opc_lldp_filter_ctrl: 1669 return true; 1670 } 1671 1672 return false; 1673 } 1674 1675 /** 1676 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1677 * @hw: pointer to the HW struct 1678 * @cq: pointer to the specific Control queue 1679 * @desc: prefilled descriptor describing the command 1680 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1681 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1682 * @cd: pointer to command details structure 1683 * 1684 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1685 * Queue if the EBUSY AQ error is returned. 1686 */ 1687 static enum ice_status 1688 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1689 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1690 struct ice_sq_cd *cd) 1691 { 1692 struct ice_aq_desc desc_cpy; 1693 enum ice_status status; 1694 bool is_cmd_for_retry; 1695 u8 *buf_cpy = NULL; 1696 u8 idx = 0; 1697 u16 opcode; 1698 1699 opcode = LE16_TO_CPU(desc->opcode); 1700 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1701 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); 1702 1703 if (is_cmd_for_retry) { 1704 if (buf) { 1705 buf_cpy = (u8 *)ice_malloc(hw, buf_size); 1706 if (!buf_cpy) 1707 return ICE_ERR_NO_MEMORY; 1708 } 1709 1710 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), 1711 ICE_NONDMA_TO_NONDMA); 1712 } 1713 1714 do { 1715 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1716 1717 if (!is_cmd_for_retry || status == ICE_SUCCESS || 1718 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1719 break; 1720 1721 if (buf_cpy) 1722 ice_memcpy(buf, buf_cpy, buf_size, 1723 ICE_NONDMA_TO_NONDMA); 1724 1725 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), 1726 ICE_NONDMA_TO_NONDMA); 1727 1728 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); 1729 1730 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1731 1732 if (buf_cpy) 1733 ice_free(hw, buf_cpy); 1734 1735 return status; 1736 } 1737 1738 /** 1739 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1740 * @hw: pointer to the HW struct 1741 * @desc: descriptor describing the command 1742 * @buf: buffer to use for indirect commands (NULL for direct commands) 1743 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1744 * @cd: pointer to command details structure 1745 * 1746 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1747 */ 1748 enum ice_status 1749 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1750 u16 buf_size, struct ice_sq_cd *cd) 1751 { 1752 if (hw->aq_send_cmd_fn) { 1753 enum ice_status status = ICE_ERR_NOT_READY; 1754 u16 retval = ICE_AQ_RC_OK; 1755 1756 ice_acquire_lock(&hw->adminq.sq_lock); 1757 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc, 1758 buf, buf_size)) { 1759 retval = LE16_TO_CPU(desc->retval); 1760 /* strip off FW internal code */ 1761 if (retval) 1762 retval &= 0xff; 1763 if (retval == ICE_AQ_RC_OK) 1764 status = ICE_SUCCESS; 1765 else 1766 status = ICE_ERR_AQ_ERROR; 1767 } 1768 1769 hw->adminq.sq_last_status = (enum ice_aq_err)retval; 1770 ice_release_lock(&hw->adminq.sq_lock); 1771 1772 return status; 1773 } 1774 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1775 } 1776 1777 /** 1778 * ice_aq_get_fw_ver 1779 * @hw: pointer to the HW struct 1780 * @cd: pointer to command details structure or NULL 1781 * 1782 * Get the firmware version (0x0001) from the admin queue commands 1783 */ 1784 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1785 { 1786 struct ice_aqc_get_ver *resp; 1787 struct ice_aq_desc desc; 1788 enum ice_status status; 1789 1790 resp = &desc.params.get_ver; 1791 1792 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1793 1794 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1795 1796 if (!status) { 1797 hw->fw_branch = resp->fw_branch; 1798 hw->fw_maj_ver = resp->fw_major; 1799 hw->fw_min_ver = resp->fw_minor; 1800 hw->fw_patch = resp->fw_patch; 1801 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1802 hw->api_branch = resp->api_branch; 1803 hw->api_maj_ver = resp->api_major; 1804 hw->api_min_ver = resp->api_minor; 1805 hw->api_patch = resp->api_patch; 1806 } 1807 1808 return status; 1809 } 1810 1811 /** 1812 * ice_aq_send_driver_ver 1813 * @hw: pointer to the HW struct 1814 * @dv: driver's major, minor version 1815 * @cd: pointer to command details structure or NULL 1816 * 1817 * Send the driver version (0x0002) to the firmware 1818 */ 1819 enum ice_status 1820 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1821 struct ice_sq_cd *cd) 1822 { 1823 struct ice_aqc_driver_ver *cmd; 1824 struct ice_aq_desc desc; 1825 u16 len; 1826 1827 cmd = &desc.params.driver_ver; 1828 1829 if (!dv) 1830 return ICE_ERR_PARAM; 1831 1832 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1833 1834 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1835 cmd->major_ver = dv->major_ver; 1836 cmd->minor_ver = dv->minor_ver; 1837 cmd->build_ver = dv->build_ver; 1838 cmd->subbuild_ver = dv->subbuild_ver; 1839 1840 len = 0; 1841 while (len < sizeof(dv->driver_string) && 1842 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1843 len++; 1844 1845 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1846 } 1847 1848 /** 1849 * ice_aq_q_shutdown 1850 * @hw: pointer to the HW struct 1851 * @unloading: is the driver unloading itself 1852 * 1853 * Tell the Firmware that we're shutting down the AdminQ and whether 1854 * or not the driver is unloading as well (0x0003). 1855 */ 1856 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1857 { 1858 struct ice_aqc_q_shutdown *cmd; 1859 struct ice_aq_desc desc; 1860 1861 cmd = &desc.params.q_shutdown; 1862 1863 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1864 1865 if (unloading) 1866 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1867 1868 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1869 } 1870 1871 /** 1872 * ice_aq_req_res 1873 * @hw: pointer to the HW struct 1874 * @res: resource ID 1875 * @access: access type 1876 * @sdp_number: resource number 1877 * @timeout: the maximum time in ms that the driver may hold the resource 1878 * @cd: pointer to command details structure or NULL 1879 * 1880 * Requests common resource using the admin queue commands (0x0008). 1881 * When attempting to acquire the Global Config Lock, the driver can 1882 * learn of three states: 1883 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1884 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1885 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1886 * successfully downloaded the package; the driver does 1887 * not have to download the package and can continue 1888 * loading 1889 * 1890 * Note that if the caller is in an acquire lock, perform action, release lock 1891 * phase of operation, it is possible that the FW may detect a timeout and issue 1892 * a CORER. In this case, the driver will receive a CORER interrupt and will 1893 * have to determine its cause. The calling thread that is handling this flow 1894 * will likely get an error propagated back to it indicating the Download 1895 * Package, Update Package or the Release Resource AQ commands timed out. 1896 */ 1897 static enum ice_status 1898 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1899 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1900 struct ice_sq_cd *cd) 1901 { 1902 struct ice_aqc_req_res *cmd_resp; 1903 struct ice_aq_desc desc; 1904 enum ice_status status; 1905 1906 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1907 1908 cmd_resp = &desc.params.res_owner; 1909 1910 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1911 1912 cmd_resp->res_id = CPU_TO_LE16(res); 1913 cmd_resp->access_type = CPU_TO_LE16(access); 1914 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1915 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1916 *timeout = 0; 1917 1918 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1919 1920 /* The completion specifies the maximum time in ms that the driver 1921 * may hold the resource in the Timeout field. 1922 */ 1923 1924 /* Global config lock response utilizes an additional status field. 1925 * 1926 * If the Global config lock resource is held by some other driver, the 1927 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1928 * and the timeout field indicates the maximum time the current owner 1929 * of the resource has to free it. 1930 */ 1931 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1932 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1933 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1934 return ICE_SUCCESS; 1935 } else if (LE16_TO_CPU(cmd_resp->status) == 1936 ICE_AQ_RES_GLBL_IN_PROG) { 1937 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1938 return ICE_ERR_AQ_ERROR; 1939 } else if (LE16_TO_CPU(cmd_resp->status) == 1940 ICE_AQ_RES_GLBL_DONE) { 1941 return ICE_ERR_AQ_NO_WORK; 1942 } 1943 1944 /* invalid FW response, force a timeout immediately */ 1945 *timeout = 0; 1946 return ICE_ERR_AQ_ERROR; 1947 } 1948 1949 /* If the resource is held by some other driver, the command completes 1950 * with a busy return value and the timeout field indicates the maximum 1951 * time the current owner of the resource has to free it. 1952 */ 1953 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1954 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1955 1956 return status; 1957 } 1958 1959 /** 1960 * ice_aq_release_res 1961 * @hw: pointer to the HW struct 1962 * @res: resource ID 1963 * @sdp_number: resource number 1964 * @cd: pointer to command details structure or NULL 1965 * 1966 * release common resource using the admin queue commands (0x0009) 1967 */ 1968 static enum ice_status 1969 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1970 struct ice_sq_cd *cd) 1971 { 1972 struct ice_aqc_req_res *cmd; 1973 struct ice_aq_desc desc; 1974 1975 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1976 1977 cmd = &desc.params.res_owner; 1978 1979 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1980 1981 cmd->res_id = CPU_TO_LE16(res); 1982 cmd->res_number = CPU_TO_LE32(sdp_number); 1983 1984 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1985 } 1986 1987 /** 1988 * ice_acquire_res 1989 * @hw: pointer to the HW structure 1990 * @res: resource ID 1991 * @access: access type (read or write) 1992 * @timeout: timeout in milliseconds 1993 * 1994 * This function will attempt to acquire the ownership of a resource. 1995 */ 1996 enum ice_status 1997 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1998 enum ice_aq_res_access_type access, u32 timeout) 1999 { 2000 #define ICE_RES_POLLING_DELAY_MS 10 2001 u32 delay = ICE_RES_POLLING_DELAY_MS; 2002 u32 time_left = timeout; 2003 enum ice_status status; 2004 2005 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 2006 2007 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2008 2009 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 2010 * previously acquired the resource and performed any necessary updates; 2011 * in this case the caller does not obtain the resource and has no 2012 * further work to do. 2013 */ 2014 if (status == ICE_ERR_AQ_NO_WORK) 2015 goto ice_acquire_res_exit; 2016 2017 if (status) 2018 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2019 2020 /* If necessary, poll until the current lock owner timeouts */ 2021 timeout = time_left; 2022 while (status && timeout && time_left) { 2023 ice_msec_delay(delay, true); 2024 timeout = (timeout > delay) ? timeout - delay : 0; 2025 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2026 2027 if (status == ICE_ERR_AQ_NO_WORK) 2028 /* lock free, but no work to do */ 2029 break; 2030 2031 if (!status) 2032 /* lock acquired */ 2033 break; 2034 } 2035 if (status && status != ICE_ERR_AQ_NO_WORK) 2036 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2037 2038 ice_acquire_res_exit: 2039 if (status == ICE_ERR_AQ_NO_WORK) { 2040 if (access == ICE_RES_WRITE) 2041 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2042 else 2043 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 2044 } 2045 return status; 2046 } 2047 2048 /** 2049 * ice_release_res 2050 * @hw: pointer to the HW structure 2051 * @res: resource ID 2052 * 2053 * This function will release a resource using the proper Admin Command. 2054 */ 2055 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2056 { 2057 enum ice_status status; 2058 u32 total_delay = 0; 2059 2060 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 2061 2062 status = ice_aq_release_res(hw, res, 0, NULL); 2063 2064 /* there are some rare cases when trying to release the resource 2065 * results in an admin queue timeout, so handle them correctly 2066 */ 2067 while ((status == ICE_ERR_AQ_TIMEOUT) && 2068 (total_delay < hw->adminq.sq_cmd_timeout)) { 2069 ice_msec_delay(1, true); 2070 status = ice_aq_release_res(hw, res, 0, NULL); 2071 total_delay++; 2072 } 2073 } 2074 2075 /** 2076 * ice_aq_alloc_free_res - command to allocate/free resources 2077 * @hw: pointer to the HW struct 2078 * @num_entries: number of resource entries in buffer 2079 * @buf: Indirect buffer to hold data parameters and response 2080 * @buf_size: size of buffer for indirect commands 2081 * @opc: pass in the command opcode 2082 * @cd: pointer to command details structure or NULL 2083 * 2084 * Helper function to allocate/free resources using the admin queue commands 2085 */ 2086 enum ice_status 2087 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 2088 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2089 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2090 { 2091 struct ice_aqc_alloc_free_res_cmd *cmd; 2092 struct ice_aq_desc desc; 2093 2094 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 2095 2096 cmd = &desc.params.sw_res_ctrl; 2097 2098 if (!buf) 2099 return ICE_ERR_PARAM; 2100 2101 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) 2102 return ICE_ERR_PARAM; 2103 2104 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2105 2106 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2107 2108 cmd->num_entries = CPU_TO_LE16(num_entries); 2109 2110 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2111 } 2112 2113 /** 2114 * ice_alloc_hw_res - allocate resource 2115 * @hw: pointer to the HW struct 2116 * @type: type of resource 2117 * @num: number of resources to allocate 2118 * @btm: allocate from bottom 2119 * @res: pointer to array that will receive the resources 2120 */ 2121 enum ice_status 2122 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2123 { 2124 struct ice_aqc_alloc_free_res_elem *buf; 2125 enum ice_status status; 2126 u16 buf_len; 2127 2128 buf_len = ice_struct_size(buf, elem, num); 2129 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 2130 if (!buf) 2131 return ICE_ERR_NO_MEMORY; 2132 2133 /* Prepare buffer to allocate resource. */ 2134 buf->num_elems = CPU_TO_LE16(num); 2135 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2136 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2137 if (btm) 2138 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2139 2140 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 2141 ice_aqc_opc_alloc_res, NULL); 2142 if (status) 2143 goto ice_alloc_res_exit; 2144 2145 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num, 2146 ICE_NONDMA_TO_NONDMA); 2147 2148 ice_alloc_res_exit: 2149 ice_free(hw, buf); 2150 return status; 2151 } 2152 2153 /** 2154 * ice_free_hw_res - free allocated HW resource 2155 * @hw: pointer to the HW struct 2156 * @type: type of resource to free 2157 * @num: number of resources 2158 * @res: pointer to array that contains the resources to free 2159 */ 2160 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2161 { 2162 struct ice_aqc_alloc_free_res_elem *buf; 2163 enum ice_status status; 2164 u16 buf_len; 2165 2166 buf_len = ice_struct_size(buf, elem, num); 2167 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 2168 if (!buf) 2169 return ICE_ERR_NO_MEMORY; 2170 2171 /* Prepare buffer to free resource. */ 2172 buf->num_elems = CPU_TO_LE16(num); 2173 buf->res_type = CPU_TO_LE16(type); 2174 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num, 2175 ICE_NONDMA_TO_NONDMA); 2176 2177 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 2178 ice_aqc_opc_free_res, NULL); 2179 if (status) 2180 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2181 2182 ice_free(hw, buf); 2183 return status; 2184 } 2185 2186 /** 2187 * ice_get_num_per_func - determine number of resources per PF 2188 * @hw: pointer to the HW structure 2189 * @max: value to be evenly split between each PF 2190 * 2191 * Determine the number of valid functions by going through the bitmap returned 2192 * from parsing capabilities and use this to calculate the number of resources 2193 * per PF based on the max value passed in. 2194 */ 2195 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2196 { 2197 u8 funcs; 2198 2199 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2200 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 2201 ICE_CAPS_VALID_FUNCS_M); 2202 2203 if (!funcs) 2204 return 0; 2205 2206 return max / funcs; 2207 } 2208 2209 /** 2210 * ice_parse_common_caps - parse common device/function capabilities 2211 * @hw: pointer to the HW struct 2212 * @caps: pointer to common capabilities structure 2213 * @elem: the capability element to parse 2214 * @prefix: message prefix for tracing capabilities 2215 * 2216 * Given a capability element, extract relevant details into the common 2217 * capability structure. 2218 * 2219 * Returns: true if the capability matches one of the common capability ids, 2220 * false otherwise. 2221 */ 2222 static bool 2223 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2224 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2225 { 2226 u32 logical_id = LE32_TO_CPU(elem->logical_id); 2227 u32 phys_id = LE32_TO_CPU(elem->phys_id); 2228 u32 number = LE32_TO_CPU(elem->number); 2229 u16 cap = LE16_TO_CPU(elem->cap); 2230 bool found = true; 2231 2232 switch (cap) { 2233 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2234 caps->valid_functions = number; 2235 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2236 caps->valid_functions); 2237 break; 2238 case ICE_AQC_CAPS_DCB: 2239 caps->dcb = (number == 1); 2240 caps->active_tc_bitmap = logical_id; 2241 caps->maxtc = phys_id; 2242 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2243 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2244 caps->active_tc_bitmap); 2245 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2246 break; 2247 case ICE_AQC_CAPS_RSS: 2248 caps->rss_table_size = number; 2249 caps->rss_table_entry_width = logical_id; 2250 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2251 caps->rss_table_size); 2252 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2253 caps->rss_table_entry_width); 2254 break; 2255 case ICE_AQC_CAPS_RXQS: 2256 caps->num_rxq = number; 2257 caps->rxq_first_id = phys_id; 2258 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2259 caps->num_rxq); 2260 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2261 caps->rxq_first_id); 2262 break; 2263 case ICE_AQC_CAPS_TXQS: 2264 caps->num_txq = number; 2265 caps->txq_first_id = phys_id; 2266 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2267 caps->num_txq); 2268 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2269 caps->txq_first_id); 2270 break; 2271 case ICE_AQC_CAPS_MSIX: 2272 caps->num_msix_vectors = number; 2273 caps->msix_vector_first_id = phys_id; 2274 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2275 caps->num_msix_vectors); 2276 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2277 caps->msix_vector_first_id); 2278 break; 2279 case ICE_AQC_CAPS_NVM_MGMT: 2280 caps->sec_rev_disabled = 2281 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? 2282 true : false; 2283 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, 2284 caps->sec_rev_disabled); 2285 caps->update_disabled = 2286 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? 2287 true : false; 2288 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, 2289 caps->update_disabled); 2290 caps->nvm_unified_update = 2291 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2292 true : false; 2293 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2294 caps->nvm_unified_update); 2295 break; 2296 case ICE_AQC_CAPS_MAX_MTU: 2297 caps->max_mtu = number; 2298 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2299 prefix, caps->max_mtu); 2300 break; 2301 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2302 caps->pcie_reset_avoidance = (number > 0); 2303 ice_debug(hw, ICE_DBG_INIT, 2304 "%s: pcie_reset_avoidance = %d\n", prefix, 2305 caps->pcie_reset_avoidance); 2306 break; 2307 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2308 caps->reset_restrict_support = (number == 1); 2309 ice_debug(hw, ICE_DBG_INIT, 2310 "%s: reset_restrict_support = %d\n", prefix, 2311 caps->reset_restrict_support); 2312 break; 2313 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0: 2314 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1: 2315 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2: 2316 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3: 2317 { 2318 u8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0; 2319 2320 caps->ext_topo_dev_img_ver_high[index] = number; 2321 caps->ext_topo_dev_img_ver_low[index] = logical_id; 2322 caps->ext_topo_dev_img_part_num[index] = 2323 (phys_id & ICE_EXT_TOPO_DEV_IMG_PART_NUM_M) >> 2324 ICE_EXT_TOPO_DEV_IMG_PART_NUM_S; 2325 caps->ext_topo_dev_img_load_en[index] = 2326 (phys_id & ICE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0; 2327 caps->ext_topo_dev_img_prog_en[index] = 2328 (phys_id & ICE_EXT_TOPO_DEV_IMG_PROG_EN) != 0; 2329 ice_debug(hw, ICE_DBG_INIT, 2330 "%s: ext_topo_dev_img_ver_high[%d] = %d\n", 2331 prefix, index, 2332 caps->ext_topo_dev_img_ver_high[index]); 2333 ice_debug(hw, ICE_DBG_INIT, 2334 "%s: ext_topo_dev_img_ver_low[%d] = %d\n", 2335 prefix, index, 2336 caps->ext_topo_dev_img_ver_low[index]); 2337 ice_debug(hw, ICE_DBG_INIT, 2338 "%s: ext_topo_dev_img_part_num[%d] = %d\n", 2339 prefix, index, 2340 caps->ext_topo_dev_img_part_num[index]); 2341 ice_debug(hw, ICE_DBG_INIT, 2342 "%s: ext_topo_dev_img_load_en[%d] = %d\n", 2343 prefix, index, 2344 caps->ext_topo_dev_img_load_en[index]); 2345 ice_debug(hw, ICE_DBG_INIT, 2346 "%s: ext_topo_dev_img_prog_en[%d] = %d\n", 2347 prefix, index, 2348 caps->ext_topo_dev_img_prog_en[index]); 2349 break; 2350 } 2351 default: 2352 /* Not one of the recognized common capabilities */ 2353 found = false; 2354 } 2355 2356 return found; 2357 } 2358 2359 /** 2360 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2361 * @hw: pointer to the HW structure 2362 * @caps: pointer to capabilities structure to fix 2363 * 2364 * Re-calculate the capabilities that are dependent on the number of physical 2365 * ports; i.e. some features are not supported or function differently on 2366 * devices with more than 4 ports. 2367 */ 2368 static void 2369 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2370 { 2371 /* This assumes device capabilities are always scanned before function 2372 * capabilities during the initialization flow. 2373 */ 2374 if (hw->dev_caps.num_funcs > 4) { 2375 /* Max 4 TCs per port */ 2376 caps->maxtc = 4; 2377 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2378 caps->maxtc); 2379 } 2380 } 2381 2382 /** 2383 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2384 * @hw: pointer to the HW struct 2385 * @func_p: pointer to function capabilities structure 2386 * @cap: pointer to the capability element to parse 2387 * 2388 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2389 */ 2390 static void 2391 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2392 struct ice_aqc_list_caps_elem *cap) 2393 { 2394 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2395 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2396 LE32_TO_CPU(cap->number)); 2397 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2398 func_p->guar_num_vsi); 2399 } 2400 2401 /** 2402 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2403 * @hw: pointer to the HW struct 2404 * @func_p: pointer to function capabilities structure 2405 * @cap: pointer to the capability element to parse 2406 * 2407 * Extract function capabilities for ICE_AQC_CAPS_1588. 2408 */ 2409 static void 2410 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2411 struct ice_aqc_list_caps_elem *cap) 2412 { 2413 struct ice_ts_func_info *info = &func_p->ts_func_info; 2414 u32 number = LE32_TO_CPU(cap->number); 2415 2416 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2417 func_p->common_cap.ieee_1588 = info->ena; 2418 2419 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2420 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2421 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2422 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2423 2424 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2425 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2426 2427 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2428 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2429 } else { 2430 /* Unknown clock frequency, so assume a (probably incorrect) 2431 * default to avoid out-of-bounds look ups of frequency 2432 * related information. 2433 */ 2434 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2435 info->clk_freq); 2436 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2437 } 2438 2439 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2440 func_p->common_cap.ieee_1588); 2441 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2442 info->src_tmr_owned); 2443 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2444 info->tmr_ena); 2445 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2446 info->tmr_index_owned); 2447 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2448 info->tmr_index_assoc); 2449 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2450 info->clk_freq); 2451 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2452 info->clk_src); 2453 } 2454 2455 /** 2456 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2457 * @hw: pointer to the HW struct 2458 * @func_p: pointer to function capabilities structure 2459 * 2460 * Extract function capabilities for ICE_AQC_CAPS_FD. 2461 */ 2462 static void 2463 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2464 { 2465 u32 reg_val, val; 2466 2467 if (hw->dcf_enabled) 2468 return; 2469 reg_val = rd32(hw, GLQF_FD_SIZE); 2470 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2471 GLQF_FD_SIZE_FD_GSIZE_S; 2472 func_p->fd_fltr_guar = 2473 ice_get_num_per_func(hw, val); 2474 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2475 GLQF_FD_SIZE_FD_BSIZE_S; 2476 func_p->fd_fltr_best_effort = val; 2477 2478 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2479 func_p->fd_fltr_guar); 2480 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2481 func_p->fd_fltr_best_effort); 2482 } 2483 2484 /** 2485 * ice_parse_func_caps - Parse function capabilities 2486 * @hw: pointer to the HW struct 2487 * @func_p: pointer to function capabilities structure 2488 * @buf: buffer containing the function capability records 2489 * @cap_count: the number of capabilities 2490 * 2491 * Helper function to parse function (0x000A) capabilities list. For 2492 * capabilities shared between device and function, this relies on 2493 * ice_parse_common_caps. 2494 * 2495 * Loop through the list of provided capabilities and extract the relevant 2496 * data into the function capabilities structured. 2497 */ 2498 static void 2499 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2500 void *buf, u32 cap_count) 2501 { 2502 struct ice_aqc_list_caps_elem *cap_resp; 2503 u32 i; 2504 2505 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2506 2507 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 2508 2509 for (i = 0; i < cap_count; i++) { 2510 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2511 bool found; 2512 2513 found = ice_parse_common_caps(hw, &func_p->common_cap, 2514 &cap_resp[i], "func caps"); 2515 2516 switch (cap) { 2517 case ICE_AQC_CAPS_VSI: 2518 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2519 break; 2520 case ICE_AQC_CAPS_1588: 2521 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2522 break; 2523 case ICE_AQC_CAPS_FD: 2524 ice_parse_fdir_func_caps(hw, func_p); 2525 break; 2526 default: 2527 /* Don't list common capabilities as unknown */ 2528 if (!found) 2529 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2530 i, cap); 2531 break; 2532 } 2533 } 2534 2535 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2536 } 2537 2538 /** 2539 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2540 * @hw: pointer to the HW struct 2541 * @dev_p: pointer to device capabilities structure 2542 * @cap: capability element to parse 2543 * 2544 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2545 */ 2546 static void 2547 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2548 struct ice_aqc_list_caps_elem *cap) 2549 { 2550 u32 number = LE32_TO_CPU(cap->number); 2551 2552 dev_p->num_funcs = ice_hweight32(number); 2553 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2554 dev_p->num_funcs); 2555 } 2556 2557 /** 2558 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2559 * @hw: pointer to the HW struct 2560 * @dev_p: pointer to device capabilities structure 2561 * @cap: capability element to parse 2562 * 2563 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2564 */ 2565 static void 2566 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2567 struct ice_aqc_list_caps_elem *cap) 2568 { 2569 u32 number = LE32_TO_CPU(cap->number); 2570 2571 dev_p->num_vsi_allocd_to_host = number; 2572 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2573 dev_p->num_vsi_allocd_to_host); 2574 } 2575 2576 /** 2577 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2578 * @hw: pointer to the HW struct 2579 * @dev_p: pointer to device capabilities structure 2580 * @cap: capability element to parse 2581 * 2582 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2583 */ 2584 static void 2585 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2586 struct ice_aqc_list_caps_elem *cap) 2587 { 2588 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2589 u32 logical_id = LE32_TO_CPU(cap->logical_id); 2590 u32 phys_id = LE32_TO_CPU(cap->phys_id); 2591 u32 number = LE32_TO_CPU(cap->number); 2592 2593 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2594 dev_p->common_cap.ieee_1588 = info->ena; 2595 2596 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2597 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2598 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2599 2600 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2601 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2602 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2603 2604 info->ena_ports = logical_id; 2605 info->tmr_own_map = phys_id; 2606 2607 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2608 dev_p->common_cap.ieee_1588); 2609 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2610 info->tmr0_owner); 2611 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2612 info->tmr0_owned); 2613 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2614 info->tmr0_ena); 2615 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2616 info->tmr1_owner); 2617 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2618 info->tmr1_owned); 2619 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2620 info->tmr1_ena); 2621 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2622 info->ena_ports); 2623 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2624 info->tmr_own_map); 2625 } 2626 2627 /** 2628 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2629 * @hw: pointer to the HW struct 2630 * @dev_p: pointer to device capabilities structure 2631 * @cap: capability element to parse 2632 * 2633 * Parse ICE_AQC_CAPS_FD for device capabilities. 2634 */ 2635 static void 2636 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2637 struct ice_aqc_list_caps_elem *cap) 2638 { 2639 u32 number = LE32_TO_CPU(cap->number); 2640 2641 dev_p->num_flow_director_fltr = number; 2642 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2643 dev_p->num_flow_director_fltr); 2644 } 2645 2646 /** 2647 * ice_parse_dev_caps - Parse device capabilities 2648 * @hw: pointer to the HW struct 2649 * @dev_p: pointer to device capabilities structure 2650 * @buf: buffer containing the device capability records 2651 * @cap_count: the number of capabilities 2652 * 2653 * Helper device to parse device (0x000B) capabilities list. For 2654 * capabilities shared between device and function, this relies on 2655 * ice_parse_common_caps. 2656 * 2657 * Loop through the list of provided capabilities and extract the relevant 2658 * data into the device capabilities structured. 2659 */ 2660 static void 2661 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2662 void *buf, u32 cap_count) 2663 { 2664 struct ice_aqc_list_caps_elem *cap_resp; 2665 u32 i; 2666 2667 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2668 2669 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 2670 2671 for (i = 0; i < cap_count; i++) { 2672 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2673 bool found; 2674 2675 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2676 &cap_resp[i], "dev caps"); 2677 2678 switch (cap) { 2679 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2680 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2681 break; 2682 case ICE_AQC_CAPS_VSI: 2683 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2684 break; 2685 case ICE_AQC_CAPS_1588: 2686 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2687 break; 2688 case ICE_AQC_CAPS_FD: 2689 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2690 break; 2691 default: 2692 /* Don't list common capabilities as unknown */ 2693 if (!found) 2694 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2695 i, cap); 2696 break; 2697 } 2698 } 2699 2700 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2701 } 2702 2703 /** 2704 * ice_aq_list_caps - query function/device capabilities 2705 * @hw: pointer to the HW struct 2706 * @buf: a buffer to hold the capabilities 2707 * @buf_size: size of the buffer 2708 * @cap_count: if not NULL, set to the number of capabilities reported 2709 * @opc: capabilities type to discover, device or function 2710 * @cd: pointer to command details structure or NULL 2711 * 2712 * Get the function (0x000A) or device (0x000B) capabilities description from 2713 * firmware and store it in the buffer. 2714 * 2715 * If the cap_count pointer is not NULL, then it is set to the number of 2716 * capabilities firmware will report. Note that if the buffer size is too 2717 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2718 * cap_count will still be updated in this case. It is recommended that the 2719 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2720 * firmware could return) to avoid this. 2721 */ 2722 static enum ice_status 2723 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2724 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2725 { 2726 struct ice_aqc_list_caps *cmd; 2727 struct ice_aq_desc desc; 2728 enum ice_status status; 2729 2730 cmd = &desc.params.get_cap; 2731 2732 if (opc != ice_aqc_opc_list_func_caps && 2733 opc != ice_aqc_opc_list_dev_caps) 2734 return ICE_ERR_PARAM; 2735 2736 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2737 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2738 2739 if (cap_count) 2740 *cap_count = LE32_TO_CPU(cmd->count); 2741 2742 return status; 2743 } 2744 2745 /** 2746 * ice_discover_dev_caps - Read and extract device capabilities 2747 * @hw: pointer to the hardware structure 2748 * @dev_caps: pointer to device capabilities structure 2749 * 2750 * Read the device capabilities and extract them into the dev_caps structure 2751 * for later use. 2752 */ 2753 static enum ice_status 2754 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2755 { 2756 enum ice_status status; 2757 u32 cap_count = 0; 2758 void *cbuf; 2759 2760 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2761 if (!cbuf) 2762 return ICE_ERR_NO_MEMORY; 2763 2764 /* Although the driver doesn't know the number of capabilities the 2765 * device will return, we can simply send a 4KB buffer, the maximum 2766 * possible size that firmware can return. 2767 */ 2768 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2769 2770 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2771 ice_aqc_opc_list_dev_caps, NULL); 2772 if (!status) 2773 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2774 ice_free(hw, cbuf); 2775 2776 return status; 2777 } 2778 2779 /** 2780 * ice_discover_func_caps - Read and extract function capabilities 2781 * @hw: pointer to the hardware structure 2782 * @func_caps: pointer to function capabilities structure 2783 * 2784 * Read the function capabilities and extract them into the func_caps structure 2785 * for later use. 2786 */ 2787 static enum ice_status 2788 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2789 { 2790 enum ice_status status; 2791 u32 cap_count = 0; 2792 void *cbuf; 2793 2794 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2795 if (!cbuf) 2796 return ICE_ERR_NO_MEMORY; 2797 2798 /* Although the driver doesn't know the number of capabilities the 2799 * device will return, we can simply send a 4KB buffer, the maximum 2800 * possible size that firmware can return. 2801 */ 2802 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2803 2804 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2805 ice_aqc_opc_list_func_caps, NULL); 2806 if (!status) 2807 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2808 ice_free(hw, cbuf); 2809 2810 return status; 2811 } 2812 2813 /** 2814 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2815 * @hw: pointer to the hardware structure 2816 */ 2817 void ice_set_safe_mode_caps(struct ice_hw *hw) 2818 { 2819 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2820 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2821 struct ice_hw_common_caps cached_caps; 2822 u32 num_funcs; 2823 2824 /* cache some func_caps values that should be restored after memset */ 2825 cached_caps = func_caps->common_cap; 2826 2827 /* unset func capabilities */ 2828 memset(func_caps, 0, sizeof(*func_caps)); 2829 2830 #define ICE_RESTORE_FUNC_CAP(name) \ 2831 func_caps->common_cap.name = cached_caps.name 2832 2833 /* restore cached values */ 2834 ICE_RESTORE_FUNC_CAP(valid_functions); 2835 ICE_RESTORE_FUNC_CAP(txq_first_id); 2836 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2837 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2838 ICE_RESTORE_FUNC_CAP(max_mtu); 2839 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2840 2841 /* one Tx and one Rx queue in safe mode */ 2842 func_caps->common_cap.num_rxq = 1; 2843 func_caps->common_cap.num_txq = 1; 2844 2845 /* two MSIX vectors, one for traffic and one for misc causes */ 2846 func_caps->common_cap.num_msix_vectors = 2; 2847 func_caps->guar_num_vsi = 1; 2848 2849 /* cache some dev_caps values that should be restored after memset */ 2850 cached_caps = dev_caps->common_cap; 2851 num_funcs = dev_caps->num_funcs; 2852 2853 /* unset dev capabilities */ 2854 memset(dev_caps, 0, sizeof(*dev_caps)); 2855 2856 #define ICE_RESTORE_DEV_CAP(name) \ 2857 dev_caps->common_cap.name = cached_caps.name 2858 2859 /* restore cached values */ 2860 ICE_RESTORE_DEV_CAP(valid_functions); 2861 ICE_RESTORE_DEV_CAP(txq_first_id); 2862 ICE_RESTORE_DEV_CAP(rxq_first_id); 2863 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2864 ICE_RESTORE_DEV_CAP(max_mtu); 2865 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2866 dev_caps->num_funcs = num_funcs; 2867 2868 /* one Tx and one Rx queue per function in safe mode */ 2869 dev_caps->common_cap.num_rxq = num_funcs; 2870 dev_caps->common_cap.num_txq = num_funcs; 2871 2872 /* two MSIX vectors per function */ 2873 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2874 } 2875 2876 /** 2877 * ice_get_caps - get info about the HW 2878 * @hw: pointer to the hardware structure 2879 */ 2880 enum ice_status ice_get_caps(struct ice_hw *hw) 2881 { 2882 enum ice_status status; 2883 2884 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2885 if (status) 2886 return status; 2887 2888 return ice_discover_func_caps(hw, &hw->func_caps); 2889 } 2890 2891 /** 2892 * ice_aq_manage_mac_write - manage MAC address write command 2893 * @hw: pointer to the HW struct 2894 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2895 * @flags: flags to control write behavior 2896 * @cd: pointer to command details structure or NULL 2897 * 2898 * This function is used to write MAC address to the NVM (0x0108). 2899 */ 2900 enum ice_status 2901 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2902 struct ice_sq_cd *cd) 2903 { 2904 struct ice_aqc_manage_mac_write *cmd; 2905 struct ice_aq_desc desc; 2906 2907 cmd = &desc.params.mac_write; 2908 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2909 2910 cmd->flags = flags; 2911 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 2912 2913 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2914 } 2915 2916 /** 2917 * ice_aq_clear_pxe_mode 2918 * @hw: pointer to the HW struct 2919 * 2920 * Tell the firmware that the driver is taking over from PXE (0x0110). 2921 */ 2922 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2923 { 2924 struct ice_aq_desc desc; 2925 2926 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2927 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2928 2929 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2930 } 2931 2932 /** 2933 * ice_clear_pxe_mode - clear pxe operations mode 2934 * @hw: pointer to the HW struct 2935 * 2936 * Make sure all PXE mode settings are cleared, including things 2937 * like descriptor fetch/write-back mode. 2938 */ 2939 void ice_clear_pxe_mode(struct ice_hw *hw) 2940 { 2941 if (ice_check_sq_alive(hw, &hw->adminq)) 2942 ice_aq_clear_pxe_mode(hw); 2943 } 2944 2945 /** 2946 * ice_aq_set_port_params - set physical port parameters. 2947 * @pi: pointer to the port info struct 2948 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 2949 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 2950 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 2951 * @double_vlan: if set double VLAN is enabled 2952 * @cd: pointer to command details structure or NULL 2953 * 2954 * Set Physical port parameters (0x0203) 2955 */ 2956 enum ice_status 2957 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 2958 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 2959 struct ice_sq_cd *cd) 2960 2961 { 2962 struct ice_aqc_set_port_params *cmd; 2963 struct ice_hw *hw = pi->hw; 2964 struct ice_aq_desc desc; 2965 u16 cmd_flags = 0; 2966 2967 cmd = &desc.params.set_port_params; 2968 2969 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2970 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 2971 if (save_bad_pac) 2972 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; 2973 if (pad_short_pac) 2974 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; 2975 if (double_vlan) 2976 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2977 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 2978 2979 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2980 } 2981 2982 /** 2983 * ice_get_link_speed_based_on_phy_type - returns link speed 2984 * @phy_type_low: lower part of phy_type 2985 * @phy_type_high: higher part of phy_type 2986 * 2987 * This helper function will convert an entry in PHY type structure 2988 * [phy_type_low, phy_type_high] to its corresponding link speed. 2989 * Note: In the structure of [phy_type_low, phy_type_high], there should 2990 * be one bit set, as this function will convert one PHY type to its 2991 * speed. 2992 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2993 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2994 */ 2995 static u16 2996 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2997 { 2998 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2999 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3000 3001 switch (phy_type_low) { 3002 case ICE_PHY_TYPE_LOW_100BASE_TX: 3003 case ICE_PHY_TYPE_LOW_100M_SGMII: 3004 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3005 break; 3006 case ICE_PHY_TYPE_LOW_1000BASE_T: 3007 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3008 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3009 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3010 case ICE_PHY_TYPE_LOW_1G_SGMII: 3011 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3012 break; 3013 case ICE_PHY_TYPE_LOW_2500BASE_T: 3014 case ICE_PHY_TYPE_LOW_2500BASE_X: 3015 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3016 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3017 break; 3018 case ICE_PHY_TYPE_LOW_5GBASE_T: 3019 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3020 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3021 break; 3022 case ICE_PHY_TYPE_LOW_10GBASE_T: 3023 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3024 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3025 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3026 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3027 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3028 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3029 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3030 break; 3031 case ICE_PHY_TYPE_LOW_25GBASE_T: 3032 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3033 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3034 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3035 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3036 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3037 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3038 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3039 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3040 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3041 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3042 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3043 break; 3044 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3045 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3046 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3047 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3048 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3049 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3050 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3051 break; 3052 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3053 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3054 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3055 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3056 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3057 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3058 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3059 case ICE_PHY_TYPE_LOW_50G_AUI2: 3060 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3061 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3062 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3063 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3064 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3065 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3066 case ICE_PHY_TYPE_LOW_50G_AUI1: 3067 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3068 break; 3069 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3070 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3071 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3072 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3073 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3074 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3075 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3076 case ICE_PHY_TYPE_LOW_100G_AUI4: 3077 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3078 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3079 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3080 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3081 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3082 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3083 break; 3084 default: 3085 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3086 break; 3087 } 3088 3089 switch (phy_type_high) { 3090 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3091 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3092 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3093 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3094 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3095 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3096 break; 3097 default: 3098 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3099 break; 3100 } 3101 3102 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3103 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3104 return ICE_AQ_LINK_SPEED_UNKNOWN; 3105 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3106 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3107 return ICE_AQ_LINK_SPEED_UNKNOWN; 3108 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3109 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3110 return speed_phy_type_low; 3111 else 3112 return speed_phy_type_high; 3113 } 3114 3115 /** 3116 * ice_update_phy_type 3117 * @phy_type_low: pointer to the lower part of phy_type 3118 * @phy_type_high: pointer to the higher part of phy_type 3119 * @link_speeds_bitmap: targeted link speeds bitmap 3120 * 3121 * Note: For the link_speeds_bitmap structure, you can check it at 3122 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3123 * link_speeds_bitmap include multiple speeds. 3124 * 3125 * Each entry in this [phy_type_low, phy_type_high] structure will 3126 * present a certain link speed. This helper function will turn on bits 3127 * in [phy_type_low, phy_type_high] structure based on the value of 3128 * link_speeds_bitmap input parameter. 3129 */ 3130 void 3131 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3132 u16 link_speeds_bitmap) 3133 { 3134 u64 pt_high; 3135 u64 pt_low; 3136 int index; 3137 u16 speed; 3138 3139 /* We first check with low part of phy_type */ 3140 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3141 pt_low = BIT_ULL(index); 3142 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3143 3144 if (link_speeds_bitmap & speed) 3145 *phy_type_low |= BIT_ULL(index); 3146 } 3147 3148 /* We then check with high part of phy_type */ 3149 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3150 pt_high = BIT_ULL(index); 3151 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3152 3153 if (link_speeds_bitmap & speed) 3154 *phy_type_high |= BIT_ULL(index); 3155 } 3156 } 3157 3158 /** 3159 * ice_aq_set_phy_cfg 3160 * @hw: pointer to the HW struct 3161 * @pi: port info structure of the interested logical port 3162 * @cfg: structure with PHY configuration data to be set 3163 * @cd: pointer to command details structure or NULL 3164 * 3165 * Set the various PHY configuration parameters supported on the Port. 3166 * One or more of the Set PHY config parameters may be ignored in an MFP 3167 * mode as the PF may not have the privilege to set some of the PHY Config 3168 * parameters. This status will be indicated by the command response (0x0601). 3169 */ 3170 enum ice_status 3171 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3172 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3173 { 3174 struct ice_aq_desc desc; 3175 enum ice_status status; 3176 3177 if (!cfg) 3178 return ICE_ERR_PARAM; 3179 3180 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3181 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3182 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3183 cfg->caps); 3184 3185 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3186 } 3187 3188 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3189 desc.params.set_phy.lport_num = pi->lport; 3190 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3191 3192 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3193 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3194 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 3195 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3196 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 3197 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3198 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3199 cfg->low_power_ctrl_an); 3200 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3201 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3202 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3203 cfg->link_fec_opt); 3204 3205 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3206 3207 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3208 status = ICE_SUCCESS; 3209 3210 if (!status) 3211 pi->phy.curr_user_phy_cfg = *cfg; 3212 3213 return status; 3214 } 3215 3216 /** 3217 * ice_update_link_info - update status of the HW network link 3218 * @pi: port info structure of the interested logical port 3219 */ 3220 enum ice_status ice_update_link_info(struct ice_port_info *pi) 3221 { 3222 struct ice_link_status *li; 3223 enum ice_status status; 3224 3225 if (!pi) 3226 return ICE_ERR_PARAM; 3227 3228 li = &pi->phy.link_info; 3229 3230 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3231 if (status) 3232 return status; 3233 3234 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3235 struct ice_aqc_get_phy_caps_data *pcaps; 3236 struct ice_hw *hw; 3237 3238 hw = pi->hw; 3239 pcaps = (struct ice_aqc_get_phy_caps_data *) 3240 ice_malloc(hw, sizeof(*pcaps)); 3241 if (!pcaps) 3242 return ICE_ERR_NO_MEMORY; 3243 3244 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3245 pcaps, NULL); 3246 3247 if (status == ICE_SUCCESS) 3248 ice_memcpy(li->module_type, &pcaps->module_type, 3249 sizeof(li->module_type), 3250 ICE_NONDMA_TO_NONDMA); 3251 3252 ice_free(hw, pcaps); 3253 } 3254 3255 return status; 3256 } 3257 3258 /** 3259 * ice_cache_phy_user_req 3260 * @pi: port information structure 3261 * @cache_data: PHY logging data 3262 * @cache_mode: PHY logging mode 3263 * 3264 * Log the user request on (FC, FEC, SPEED) for later user. 3265 */ 3266 static void 3267 ice_cache_phy_user_req(struct ice_port_info *pi, 3268 struct ice_phy_cache_mode_data cache_data, 3269 enum ice_phy_cache_mode cache_mode) 3270 { 3271 if (!pi) 3272 return; 3273 3274 switch (cache_mode) { 3275 case ICE_FC_MODE: 3276 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3277 break; 3278 case ICE_SPEED_MODE: 3279 pi->phy.curr_user_speed_req = 3280 cache_data.data.curr_user_speed_req; 3281 break; 3282 case ICE_FEC_MODE: 3283 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3284 break; 3285 default: 3286 break; 3287 } 3288 } 3289 3290 /** 3291 * ice_caps_to_fc_mode 3292 * @caps: PHY capabilities 3293 * 3294 * Convert PHY FC capabilities to ice FC mode 3295 */ 3296 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3297 { 3298 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3299 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3300 return ICE_FC_FULL; 3301 3302 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3303 return ICE_FC_TX_PAUSE; 3304 3305 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3306 return ICE_FC_RX_PAUSE; 3307 3308 return ICE_FC_NONE; 3309 } 3310 3311 /** 3312 * ice_caps_to_fec_mode 3313 * @caps: PHY capabilities 3314 * @fec_options: Link FEC options 3315 * 3316 * Convert PHY FEC capabilities to ice FEC mode 3317 */ 3318 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3319 { 3320 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3321 return ICE_FEC_AUTO; 3322 3323 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3324 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3325 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3326 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3327 return ICE_FEC_BASER; 3328 3329 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3330 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3331 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3332 return ICE_FEC_RS; 3333 3334 return ICE_FEC_NONE; 3335 } 3336 3337 /** 3338 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3339 * @pi: port information structure 3340 * @cfg: PHY configuration data to set FC mode 3341 * @req_mode: FC mode to configure 3342 */ 3343 static enum ice_status 3344 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3345 enum ice_fc_mode req_mode) 3346 { 3347 struct ice_phy_cache_mode_data cache_data; 3348 u8 pause_mask = 0x0; 3349 3350 if (!pi || !cfg) 3351 return ICE_ERR_BAD_PTR; 3352 3353 switch (req_mode) { 3354 case ICE_FC_AUTO: 3355 { 3356 struct ice_aqc_get_phy_caps_data *pcaps; 3357 enum ice_status status; 3358 3359 pcaps = (struct ice_aqc_get_phy_caps_data *) 3360 ice_malloc(pi->hw, sizeof(*pcaps)); 3361 if (!pcaps) 3362 return ICE_ERR_NO_MEMORY; 3363 3364 /* Query the value of FC that both the NIC and attached media 3365 * can do. 3366 */ 3367 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3368 pcaps, NULL); 3369 if (status) { 3370 ice_free(pi->hw, pcaps); 3371 return status; 3372 } 3373 3374 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3375 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3376 3377 ice_free(pi->hw, pcaps); 3378 break; 3379 } 3380 case ICE_FC_FULL: 3381 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3382 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3383 break; 3384 case ICE_FC_RX_PAUSE: 3385 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3386 break; 3387 case ICE_FC_TX_PAUSE: 3388 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3389 break; 3390 default: 3391 break; 3392 } 3393 3394 /* clear the old pause settings */ 3395 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3396 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3397 3398 /* set the new capabilities */ 3399 cfg->caps |= pause_mask; 3400 3401 /* Cache user FC request */ 3402 cache_data.data.curr_user_fc_req = req_mode; 3403 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3404 3405 return ICE_SUCCESS; 3406 } 3407 3408 /** 3409 * ice_set_fc 3410 * @pi: port information structure 3411 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3412 * @ena_auto_link_update: enable automatic link update 3413 * 3414 * Set the requested flow control mode. 3415 */ 3416 enum ice_status 3417 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3418 { 3419 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3420 struct ice_aqc_get_phy_caps_data *pcaps; 3421 enum ice_status status; 3422 struct ice_hw *hw; 3423 3424 if (!pi || !aq_failures) 3425 return ICE_ERR_BAD_PTR; 3426 3427 *aq_failures = 0; 3428 hw = pi->hw; 3429 3430 pcaps = (struct ice_aqc_get_phy_caps_data *) 3431 ice_malloc(hw, sizeof(*pcaps)); 3432 if (!pcaps) 3433 return ICE_ERR_NO_MEMORY; 3434 3435 /* Get the current PHY config */ 3436 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3437 pcaps, NULL); 3438 3439 if (status) { 3440 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3441 goto out; 3442 } 3443 3444 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3445 3446 /* Configure the set PHY data */ 3447 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3448 if (status) { 3449 if (status != ICE_ERR_BAD_PTR) 3450 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3451 3452 goto out; 3453 } 3454 3455 /* If the capabilities have changed, then set the new config */ 3456 if (cfg.caps != pcaps->caps) { 3457 int retry_count, retry_max = 10; 3458 3459 /* Auto restart link so settings take effect */ 3460 if (ena_auto_link_update) 3461 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3462 3463 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3464 if (status) { 3465 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3466 goto out; 3467 } 3468 3469 /* Update the link info 3470 * It sometimes takes a really long time for link to 3471 * come back from the atomic reset. Thus, we wait a 3472 * little bit. 3473 */ 3474 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3475 status = ice_update_link_info(pi); 3476 3477 if (status == ICE_SUCCESS) 3478 break; 3479 3480 ice_msec_delay(100, true); 3481 } 3482 3483 if (status) 3484 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3485 } 3486 3487 out: 3488 ice_free(hw, pcaps); 3489 return status; 3490 } 3491 3492 /** 3493 * ice_phy_caps_equals_cfg 3494 * @phy_caps: PHY capabilities 3495 * @phy_cfg: PHY configuration 3496 * 3497 * Helper function to determine if PHY capabilities matches PHY 3498 * configuration 3499 */ 3500 bool 3501 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3502 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3503 { 3504 u8 caps_mask, cfg_mask; 3505 3506 if (!phy_caps || !phy_cfg) 3507 return false; 3508 3509 /* These bits are not common between capabilities and configuration. 3510 * Do not use them to determine equality. 3511 */ 3512 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3513 ICE_AQC_PHY_EN_MOD_QUAL); 3514 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3515 3516 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3517 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3518 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3519 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3520 phy_caps->eee_cap != phy_cfg->eee_cap || 3521 phy_caps->eeer_value != phy_cfg->eeer_value || 3522 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3523 return false; 3524 3525 return true; 3526 } 3527 3528 /** 3529 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3530 * @pi: port information structure 3531 * @caps: PHY ability structure to copy data from 3532 * @cfg: PHY configuration structure to copy data to 3533 * 3534 * Helper function to copy AQC PHY get ability data to PHY set configuration 3535 * data structure 3536 */ 3537 void 3538 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3539 struct ice_aqc_get_phy_caps_data *caps, 3540 struct ice_aqc_set_phy_cfg_data *cfg) 3541 { 3542 if (!pi || !caps || !cfg) 3543 return; 3544 3545 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 3546 cfg->phy_type_low = caps->phy_type_low; 3547 cfg->phy_type_high = caps->phy_type_high; 3548 cfg->caps = caps->caps; 3549 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3550 cfg->eee_cap = caps->eee_cap; 3551 cfg->eeer_value = caps->eeer_value; 3552 cfg->link_fec_opt = caps->link_fec_options; 3553 cfg->module_compliance_enforcement = 3554 caps->module_compliance_enforcement; 3555 } 3556 3557 /** 3558 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3559 * @pi: port information structure 3560 * @cfg: PHY configuration data to set FEC mode 3561 * @fec: FEC mode to configure 3562 */ 3563 enum ice_status 3564 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3565 enum ice_fec_mode fec) 3566 { 3567 struct ice_aqc_get_phy_caps_data *pcaps; 3568 enum ice_status status = ICE_SUCCESS; 3569 struct ice_hw *hw; 3570 3571 if (!pi || !cfg) 3572 return ICE_ERR_BAD_PTR; 3573 3574 hw = pi->hw; 3575 3576 pcaps = (struct ice_aqc_get_phy_caps_data *) 3577 ice_malloc(hw, sizeof(*pcaps)); 3578 if (!pcaps) 3579 return ICE_ERR_NO_MEMORY; 3580 3581 status = ice_aq_get_phy_caps(pi, false, 3582 (ice_fw_supports_report_dflt_cfg(hw) ? 3583 ICE_AQC_REPORT_DFLT_CFG : 3584 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3585 3586 if (status) 3587 goto out; 3588 3589 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 3590 cfg->link_fec_opt = pcaps->link_fec_options; 3591 3592 switch (fec) { 3593 case ICE_FEC_BASER: 3594 /* Clear RS bits, and AND BASE-R ability 3595 * bits and OR request bits. 3596 */ 3597 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3598 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3599 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3600 ICE_AQC_PHY_FEC_25G_KR_REQ; 3601 break; 3602 case ICE_FEC_RS: 3603 /* Clear BASE-R bits, and AND RS ability 3604 * bits and OR request bits. 3605 */ 3606 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3607 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3608 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3609 break; 3610 case ICE_FEC_NONE: 3611 /* Clear all FEC option bits. */ 3612 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3613 break; 3614 case ICE_FEC_AUTO: 3615 /* AND auto FEC bit, and all caps bits. */ 3616 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3617 cfg->link_fec_opt |= pcaps->link_fec_options; 3618 break; 3619 default: 3620 status = ICE_ERR_PARAM; 3621 break; 3622 } 3623 3624 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && 3625 !ice_fw_supports_report_dflt_cfg(pi->hw)) { 3626 struct ice_link_default_override_tlv tlv; 3627 3628 if (ice_get_link_default_override(&tlv, pi)) 3629 goto out; 3630 3631 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3632 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3633 cfg->link_fec_opt = tlv.fec_options; 3634 } 3635 3636 out: 3637 ice_free(hw, pcaps); 3638 3639 return status; 3640 } 3641 3642 /** 3643 * ice_get_link_status - get status of the HW network link 3644 * @pi: port information structure 3645 * @link_up: pointer to bool (true/false = linkup/linkdown) 3646 * 3647 * Variable link_up is true if link is up, false if link is down. 3648 * The variable link_up is invalid if status is non zero. As a 3649 * result of this call, link status reporting becomes enabled 3650 */ 3651 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3652 { 3653 struct ice_phy_info *phy_info; 3654 enum ice_status status = ICE_SUCCESS; 3655 3656 if (!pi || !link_up) 3657 return ICE_ERR_PARAM; 3658 3659 phy_info = &pi->phy; 3660 3661 if (phy_info->get_link_info) { 3662 status = ice_update_link_info(pi); 3663 3664 if (status) 3665 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3666 status); 3667 } 3668 3669 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3670 3671 return status; 3672 } 3673 3674 /** 3675 * ice_aq_set_link_restart_an 3676 * @pi: pointer to the port information structure 3677 * @ena_link: if true: enable link, if false: disable link 3678 * @cd: pointer to command details structure or NULL 3679 * 3680 * Sets up the link and restarts the Auto-Negotiation over the link. 3681 */ 3682 enum ice_status 3683 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3684 struct ice_sq_cd *cd) 3685 { 3686 struct ice_aqc_restart_an *cmd; 3687 struct ice_aq_desc desc; 3688 3689 cmd = &desc.params.restart_an; 3690 3691 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3692 3693 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3694 cmd->lport_num = pi->lport; 3695 if (ena_link) 3696 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3697 else 3698 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3699 3700 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3701 } 3702 3703 /** 3704 * ice_aq_set_event_mask 3705 * @hw: pointer to the HW struct 3706 * @port_num: port number of the physical function 3707 * @mask: event mask to be set 3708 * @cd: pointer to command details structure or NULL 3709 * 3710 * Set event mask (0x0613) 3711 */ 3712 enum ice_status 3713 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3714 struct ice_sq_cd *cd) 3715 { 3716 struct ice_aqc_set_event_mask *cmd; 3717 struct ice_aq_desc desc; 3718 3719 cmd = &desc.params.set_event_mask; 3720 3721 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3722 3723 cmd->lport_num = port_num; 3724 3725 cmd->event_mask = CPU_TO_LE16(mask); 3726 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3727 } 3728 3729 /** 3730 * ice_aq_set_mac_loopback 3731 * @hw: pointer to the HW struct 3732 * @ena_lpbk: Enable or Disable loopback 3733 * @cd: pointer to command details structure or NULL 3734 * 3735 * Enable/disable loopback on a given port 3736 */ 3737 enum ice_status 3738 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3739 { 3740 struct ice_aqc_set_mac_lb *cmd; 3741 struct ice_aq_desc desc; 3742 3743 cmd = &desc.params.set_mac_lb; 3744 3745 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3746 if (ena_lpbk) 3747 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3748 3749 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3750 } 3751 3752 /** 3753 * ice_aq_set_port_id_led 3754 * @pi: pointer to the port information 3755 * @is_orig_mode: is this LED set to original mode (by the net-list) 3756 * @cd: pointer to command details structure or NULL 3757 * 3758 * Set LED value for the given port (0x06e9) 3759 */ 3760 enum ice_status 3761 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3762 struct ice_sq_cd *cd) 3763 { 3764 struct ice_aqc_set_port_id_led *cmd; 3765 struct ice_hw *hw = pi->hw; 3766 struct ice_aq_desc desc; 3767 3768 cmd = &desc.params.set_port_id_led; 3769 3770 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3771 3772 if (is_orig_mode) 3773 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3774 else 3775 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3776 3777 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3778 } 3779 3780 /** 3781 * ice_aq_sff_eeprom 3782 * @hw: pointer to the HW struct 3783 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3784 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3785 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3786 * @page: QSFP page 3787 * @set_page: set or ignore the page 3788 * @data: pointer to data buffer to be read/written to the I2C device. 3789 * @length: 1-16 for read, 1 for write. 3790 * @write: 0 read, 1 for write. 3791 * @cd: pointer to command details structure or NULL 3792 * 3793 * Read/Write SFF EEPROM (0x06EE) 3794 */ 3795 enum ice_status 3796 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3797 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3798 bool write, struct ice_sq_cd *cd) 3799 { 3800 struct ice_aqc_sff_eeprom *cmd; 3801 struct ice_aq_desc desc; 3802 enum ice_status status; 3803 3804 if (!data || (mem_addr & 0xff00)) 3805 return ICE_ERR_PARAM; 3806 3807 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3808 cmd = &desc.params.read_write_sff_param; 3809 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 3810 cmd->lport_num = (u8)(lport & 0xff); 3811 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3812 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 3813 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3814 ((set_page << 3815 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3816 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3817 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 3818 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3819 if (write) 3820 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 3821 3822 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3823 return status; 3824 } 3825 3826 /** 3827 * ice_aq_prog_topo_dev_nvm 3828 * @hw: pointer to the hardware structure 3829 * @topo_params: pointer to structure storing topology parameters for a device 3830 * @cd: pointer to command details structure or NULL 3831 * 3832 * Program Topology Device NVM (0x06F2) 3833 * 3834 */ 3835 enum ice_status 3836 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, 3837 struct ice_aqc_link_topo_params *topo_params, 3838 struct ice_sq_cd *cd) 3839 { 3840 struct ice_aqc_prog_topo_dev_nvm *cmd; 3841 struct ice_aq_desc desc; 3842 3843 cmd = &desc.params.prog_topo_dev_nvm; 3844 3845 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_prog_topo_dev_nvm); 3846 3847 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), 3848 ICE_NONDMA_TO_NONDMA); 3849 3850 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3851 } 3852 3853 /** 3854 * ice_aq_read_topo_dev_nvm 3855 * @hw: pointer to the hardware structure 3856 * @topo_params: pointer to structure storing topology parameters for a device 3857 * @start_address: byte offset in the topology device NVM 3858 * @data: pointer to data buffer 3859 * @data_size: number of bytes to be read from the topology device NVM 3860 * @cd: pointer to command details structure or NULL 3861 * Read Topology Device NVM (0x06F3) 3862 * 3863 */ 3864 enum ice_status 3865 ice_aq_read_topo_dev_nvm(struct ice_hw *hw, 3866 struct ice_aqc_link_topo_params *topo_params, 3867 u32 start_address, u8 *data, u8 data_size, 3868 struct ice_sq_cd *cd) 3869 { 3870 struct ice_aqc_read_topo_dev_nvm *cmd; 3871 struct ice_aq_desc desc; 3872 enum ice_status status; 3873 3874 if (!data || data_size == 0 || 3875 data_size > ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE) 3876 return ICE_ERR_PARAM; 3877 3878 cmd = &desc.params.read_topo_dev_nvm; 3879 3880 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm); 3881 3882 desc.datalen = data_size; 3883 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), 3884 ICE_NONDMA_TO_NONDMA); 3885 cmd->start_address = CPU_TO_LE32(start_address); 3886 3887 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3888 if (status) 3889 return status; 3890 3891 ice_memcpy(data, cmd->data_read, data_size, ICE_NONDMA_TO_NONDMA); 3892 3893 return ICE_SUCCESS; 3894 } 3895 3896 /** 3897 * __ice_aq_get_set_rss_lut 3898 * @hw: pointer to the hardware structure 3899 * @params: RSS LUT parameters 3900 * @set: set true to set the table, false to get the table 3901 * 3902 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3903 */ 3904 static enum ice_status 3905 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3906 { 3907 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3908 struct ice_aqc_get_set_rss_lut *cmd_resp; 3909 struct ice_aq_desc desc; 3910 enum ice_status status; 3911 u8 *lut; 3912 3913 if (!params) 3914 return ICE_ERR_PARAM; 3915 3916 vsi_handle = params->vsi_handle; 3917 lut = params->lut; 3918 3919 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3920 return ICE_ERR_PARAM; 3921 3922 lut_size = params->lut_size; 3923 lut_type = params->lut_type; 3924 glob_lut_idx = params->global_lut_id; 3925 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3926 3927 cmd_resp = &desc.params.get_set_rss_lut; 3928 3929 if (set) { 3930 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3931 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3932 } else { 3933 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3934 } 3935 3936 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3937 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3938 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3939 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3940 3941 switch (lut_type) { 3942 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3943 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3944 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3945 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3946 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3947 break; 3948 default: 3949 status = ICE_ERR_PARAM; 3950 goto ice_aq_get_set_rss_lut_exit; 3951 } 3952 3953 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3954 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3955 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3956 3957 if (!set) 3958 goto ice_aq_get_set_rss_lut_send; 3959 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3960 if (!set) 3961 goto ice_aq_get_set_rss_lut_send; 3962 } else { 3963 goto ice_aq_get_set_rss_lut_send; 3964 } 3965 3966 /* LUT size is only valid for Global and PF table types */ 3967 switch (lut_size) { 3968 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3969 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 3970 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3971 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3972 break; 3973 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3974 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3975 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3976 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3977 break; 3978 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3979 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3980 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3981 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3982 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3983 break; 3984 } 3985 /* fall-through */ 3986 default: 3987 status = ICE_ERR_PARAM; 3988 goto ice_aq_get_set_rss_lut_exit; 3989 } 3990 3991 ice_aq_get_set_rss_lut_send: 3992 cmd_resp->flags = CPU_TO_LE16(flags); 3993 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3994 3995 ice_aq_get_set_rss_lut_exit: 3996 return status; 3997 } 3998 3999 /** 4000 * ice_aq_get_rss_lut 4001 * @hw: pointer to the hardware structure 4002 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4003 * 4004 * get the RSS lookup table, PF or VSI type 4005 */ 4006 enum ice_status 4007 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4008 { 4009 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4010 } 4011 4012 /** 4013 * ice_aq_set_rss_lut 4014 * @hw: pointer to the hardware structure 4015 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4016 * 4017 * set the RSS lookup table, PF or VSI type 4018 */ 4019 enum ice_status 4020 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4021 { 4022 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4023 } 4024 4025 /** 4026 * __ice_aq_get_set_rss_key 4027 * @hw: pointer to the HW struct 4028 * @vsi_id: VSI FW index 4029 * @key: pointer to key info struct 4030 * @set: set true to set the key, false to get the key 4031 * 4032 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4033 */ 4034 static enum 4035 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4036 struct ice_aqc_get_set_rss_keys *key, 4037 bool set) 4038 { 4039 struct ice_aqc_get_set_rss_key *cmd_resp; 4040 u16 key_size = sizeof(*key); 4041 struct ice_aq_desc desc; 4042 4043 cmd_resp = &desc.params.get_set_rss_key; 4044 4045 if (set) { 4046 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4047 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 4048 } else { 4049 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4050 } 4051 4052 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 4053 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 4054 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 4055 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 4056 4057 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4058 } 4059 4060 /** 4061 * ice_aq_get_rss_key 4062 * @hw: pointer to the HW struct 4063 * @vsi_handle: software VSI handle 4064 * @key: pointer to key info struct 4065 * 4066 * get the RSS key per VSI 4067 */ 4068 enum ice_status 4069 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4070 struct ice_aqc_get_set_rss_keys *key) 4071 { 4072 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4073 return ICE_ERR_PARAM; 4074 4075 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4076 key, false); 4077 } 4078 4079 /** 4080 * ice_aq_set_rss_key 4081 * @hw: pointer to the HW struct 4082 * @vsi_handle: software VSI handle 4083 * @keys: pointer to key info struct 4084 * 4085 * set the RSS key per VSI 4086 */ 4087 enum ice_status 4088 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4089 struct ice_aqc_get_set_rss_keys *keys) 4090 { 4091 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4092 return ICE_ERR_PARAM; 4093 4094 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4095 keys, true); 4096 } 4097 4098 /** 4099 * ice_aq_add_lan_txq 4100 * @hw: pointer to the hardware structure 4101 * @num_qgrps: Number of added queue groups 4102 * @qg_list: list of queue groups to be added 4103 * @buf_size: size of buffer for indirect command 4104 * @cd: pointer to command details structure or NULL 4105 * 4106 * Add Tx LAN queue (0x0C30) 4107 * 4108 * NOTE: 4109 * Prior to calling add Tx LAN queue: 4110 * Initialize the following as part of the Tx queue context: 4111 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4112 * Cache profile and Packet shaper profile. 4113 * 4114 * After add Tx LAN queue AQ command is completed: 4115 * Interrupts should be associated with specific queues, 4116 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4117 * flow. 4118 */ 4119 enum ice_status 4120 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4121 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4122 struct ice_sq_cd *cd) 4123 { 4124 struct ice_aqc_add_tx_qgrp *list; 4125 struct ice_aqc_add_txqs *cmd; 4126 struct ice_aq_desc desc; 4127 u16 i, sum_size = 0; 4128 4129 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 4130 4131 cmd = &desc.params.add_txqs; 4132 4133 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4134 4135 if (!qg_list) 4136 return ICE_ERR_PARAM; 4137 4138 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4139 return ICE_ERR_PARAM; 4140 4141 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4142 sum_size += ice_struct_size(list, txqs, list->num_txqs); 4143 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4144 list->num_txqs); 4145 } 4146 4147 if (buf_size != sum_size) 4148 return ICE_ERR_PARAM; 4149 4150 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 4151 4152 cmd->num_qgrps = num_qgrps; 4153 4154 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4155 } 4156 4157 /** 4158 * ice_aq_dis_lan_txq 4159 * @hw: pointer to the hardware structure 4160 * @num_qgrps: number of groups in the list 4161 * @qg_list: the list of groups to disable 4162 * @buf_size: the total size of the qg_list buffer in bytes 4163 * @rst_src: if called due to reset, specifies the reset source 4164 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4165 * @cd: pointer to command details structure or NULL 4166 * 4167 * Disable LAN Tx queue (0x0C31) 4168 */ 4169 static enum ice_status 4170 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4171 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4172 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4173 struct ice_sq_cd *cd) 4174 { 4175 struct ice_aqc_dis_txq_item *item; 4176 struct ice_aqc_dis_txqs *cmd; 4177 struct ice_aq_desc desc; 4178 enum ice_status status; 4179 u16 i, sz = 0; 4180 4181 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 4182 cmd = &desc.params.dis_txqs; 4183 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4184 4185 /* qg_list can be NULL only in VM/VF reset flow */ 4186 if (!qg_list && !rst_src) 4187 return ICE_ERR_PARAM; 4188 4189 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4190 return ICE_ERR_PARAM; 4191 4192 cmd->num_entries = num_qgrps; 4193 4194 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4195 ICE_AQC_Q_DIS_TIMEOUT_M); 4196 4197 switch (rst_src) { 4198 case ICE_VM_RESET: 4199 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4200 cmd->vmvf_and_timeout |= 4201 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4202 break; 4203 case ICE_NO_RESET: 4204 default: 4205 break; 4206 } 4207 4208 /* flush pipe on time out */ 4209 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4210 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4211 if (!qg_list) 4212 goto do_aq; 4213 4214 /* set RD bit to indicate that command buffer is provided by the driver 4215 * and it needs to be read by the firmware 4216 */ 4217 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 4218 4219 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4220 u16 item_size = ice_struct_size(item, q_id, item->num_qs); 4221 4222 /* If the num of queues is even, add 2 bytes of padding */ 4223 if ((item->num_qs % 2) == 0) 4224 item_size += 2; 4225 4226 sz += item_size; 4227 4228 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4229 } 4230 4231 if (buf_size != sz) 4232 return ICE_ERR_PARAM; 4233 4234 do_aq: 4235 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4236 if (status) { 4237 if (!qg_list) 4238 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4239 vmvf_num, hw->adminq.sq_last_status); 4240 else 4241 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4242 LE16_TO_CPU(qg_list[0].q_id[0]), 4243 hw->adminq.sq_last_status); 4244 } 4245 return status; 4246 } 4247 4248 /** 4249 * ice_aq_move_recfg_lan_txq 4250 * @hw: pointer to the hardware structure 4251 * @num_qs: number of queues to move/reconfigure 4252 * @is_move: true if this operation involves node movement 4253 * @is_tc_change: true if this operation involves a TC change 4254 * @subseq_call: true if this operation is a subsequent call 4255 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 4256 * @timeout: timeout in units of 100 usec (valid values 0-50) 4257 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 4258 * @buf: struct containing src/dest TEID and per-queue info 4259 * @buf_size: size of buffer for indirect command 4260 * @txqs_moved: out param, number of queues successfully moved 4261 * @cd: pointer to command details structure or NULL 4262 * 4263 * Move / Reconfigure Tx LAN queues (0x0C32) 4264 */ 4265 enum ice_status 4266 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 4267 bool is_tc_change, bool subseq_call, bool flush_pipe, 4268 u8 timeout, u32 *blocked_cgds, 4269 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 4270 u8 *txqs_moved, struct ice_sq_cd *cd) 4271 { 4272 struct ice_aqc_move_txqs *cmd; 4273 struct ice_aq_desc desc; 4274 enum ice_status status; 4275 4276 cmd = &desc.params.move_txqs; 4277 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 4278 4279 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 4280 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 4281 return ICE_ERR_PARAM; 4282 4283 if (is_tc_change && !flush_pipe && !blocked_cgds) 4284 return ICE_ERR_PARAM; 4285 4286 if (!is_move && !is_tc_change) 4287 return ICE_ERR_PARAM; 4288 4289 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 4290 4291 if (is_move) 4292 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 4293 4294 if (is_tc_change) 4295 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 4296 4297 if (subseq_call) 4298 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 4299 4300 if (flush_pipe) 4301 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 4302 4303 cmd->num_qs = num_qs; 4304 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 4305 ICE_AQC_Q_CMD_TIMEOUT_M); 4306 4307 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4308 4309 if (!status && txqs_moved) 4310 *txqs_moved = cmd->num_qs; 4311 4312 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 4313 is_tc_change && !flush_pipe) 4314 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 4315 4316 return status; 4317 } 4318 4319 /* End of FW Admin Queue command wrappers */ 4320 4321 /** 4322 * ice_write_byte - write a byte to a packed context structure 4323 * @src_ctx: the context structure to read from 4324 * @dest_ctx: the context to be written to 4325 * @ce_info: a description of the struct to be filled 4326 */ 4327 static void 4328 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4329 { 4330 u8 src_byte, dest_byte, mask; 4331 u8 *from, *dest; 4332 u16 shift_width; 4333 4334 /* copy from the next struct field */ 4335 from = src_ctx + ce_info->offset; 4336 4337 /* prepare the bits and mask */ 4338 shift_width = ce_info->lsb % 8; 4339 mask = (u8)(BIT(ce_info->width) - 1); 4340 4341 src_byte = *from; 4342 src_byte &= mask; 4343 4344 /* shift to correct alignment */ 4345 mask <<= shift_width; 4346 src_byte <<= shift_width; 4347 4348 /* get the current bits from the target bit string */ 4349 dest = dest_ctx + (ce_info->lsb / 8); 4350 4351 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4352 4353 dest_byte &= ~mask; /* get the bits not changing */ 4354 dest_byte |= src_byte; /* add in the new bits */ 4355 4356 /* put it all back */ 4357 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4358 } 4359 4360 /** 4361 * ice_write_word - write a word to a packed context structure 4362 * @src_ctx: the context structure to read from 4363 * @dest_ctx: the context to be written to 4364 * @ce_info: a description of the struct to be filled 4365 */ 4366 static void 4367 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4368 { 4369 u16 src_word, mask; 4370 __le16 dest_word; 4371 u8 *from, *dest; 4372 u16 shift_width; 4373 4374 /* copy from the next struct field */ 4375 from = src_ctx + ce_info->offset; 4376 4377 /* prepare the bits and mask */ 4378 shift_width = ce_info->lsb % 8; 4379 mask = BIT(ce_info->width) - 1; 4380 4381 /* don't swizzle the bits until after the mask because the mask bits 4382 * will be in a different bit position on big endian machines 4383 */ 4384 src_word = *(u16 *)from; 4385 src_word &= mask; 4386 4387 /* shift to correct alignment */ 4388 mask <<= shift_width; 4389 src_word <<= shift_width; 4390 4391 /* get the current bits from the target bit string */ 4392 dest = dest_ctx + (ce_info->lsb / 8); 4393 4394 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 4395 4396 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 4397 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 4398 4399 /* put it all back */ 4400 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4401 } 4402 4403 /** 4404 * ice_write_dword - write a dword to a packed context structure 4405 * @src_ctx: the context structure to read from 4406 * @dest_ctx: the context to be written to 4407 * @ce_info: a description of the struct to be filled 4408 */ 4409 static void 4410 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4411 { 4412 u32 src_dword, mask; 4413 __le32 dest_dword; 4414 u8 *from, *dest; 4415 u16 shift_width; 4416 4417 /* copy from the next struct field */ 4418 from = src_ctx + ce_info->offset; 4419 4420 /* prepare the bits and mask */ 4421 shift_width = ce_info->lsb % 8; 4422 4423 /* if the field width is exactly 32 on an x86 machine, then the shift 4424 * operation will not work because the SHL instructions count is masked 4425 * to 5 bits so the shift will do nothing 4426 */ 4427 if (ce_info->width < 32) 4428 mask = BIT(ce_info->width) - 1; 4429 else 4430 mask = (u32)~0; 4431 4432 /* don't swizzle the bits until after the mask because the mask bits 4433 * will be in a different bit position on big endian machines 4434 */ 4435 src_dword = *(u32 *)from; 4436 src_dword &= mask; 4437 4438 /* shift to correct alignment */ 4439 mask <<= shift_width; 4440 src_dword <<= shift_width; 4441 4442 /* get the current bits from the target bit string */ 4443 dest = dest_ctx + (ce_info->lsb / 8); 4444 4445 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 4446 4447 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 4448 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 4449 4450 /* put it all back */ 4451 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4452 } 4453 4454 /** 4455 * ice_write_qword - write a qword to a packed context structure 4456 * @src_ctx: the context structure to read from 4457 * @dest_ctx: the context to be written to 4458 * @ce_info: a description of the struct to be filled 4459 */ 4460 static void 4461 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4462 { 4463 u64 src_qword, mask; 4464 __le64 dest_qword; 4465 u8 *from, *dest; 4466 u16 shift_width; 4467 4468 /* copy from the next struct field */ 4469 from = src_ctx + ce_info->offset; 4470 4471 /* prepare the bits and mask */ 4472 shift_width = ce_info->lsb % 8; 4473 4474 /* if the field width is exactly 64 on an x86 machine, then the shift 4475 * operation will not work because the SHL instructions count is masked 4476 * to 6 bits so the shift will do nothing 4477 */ 4478 if (ce_info->width < 64) 4479 mask = BIT_ULL(ce_info->width) - 1; 4480 else 4481 mask = (u64)~0; 4482 4483 /* don't swizzle the bits until after the mask because the mask bits 4484 * will be in a different bit position on big endian machines 4485 */ 4486 src_qword = *(u64 *)from; 4487 src_qword &= mask; 4488 4489 /* shift to correct alignment */ 4490 mask <<= shift_width; 4491 src_qword <<= shift_width; 4492 4493 /* get the current bits from the target bit string */ 4494 dest = dest_ctx + (ce_info->lsb / 8); 4495 4496 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 4497 4498 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 4499 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 4500 4501 /* put it all back */ 4502 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4503 } 4504 4505 /** 4506 * ice_set_ctx - set context bits in packed structure 4507 * @hw: pointer to the hardware structure 4508 * @src_ctx: pointer to a generic non-packed context structure 4509 * @dest_ctx: pointer to memory for the packed structure 4510 * @ce_info: a description of the structure to be transformed 4511 */ 4512 enum ice_status 4513 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4514 const struct ice_ctx_ele *ce_info) 4515 { 4516 int f; 4517 4518 for (f = 0; ce_info[f].width; f++) { 4519 /* We have to deal with each element of the FW response 4520 * using the correct size so that we are correct regardless 4521 * of the endianness of the machine. 4522 */ 4523 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4524 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4525 f, ce_info[f].width, ce_info[f].size_of); 4526 continue; 4527 } 4528 switch (ce_info[f].size_of) { 4529 case sizeof(u8): 4530 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4531 break; 4532 case sizeof(u16): 4533 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4534 break; 4535 case sizeof(u32): 4536 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4537 break; 4538 case sizeof(u64): 4539 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4540 break; 4541 default: 4542 return ICE_ERR_INVAL_SIZE; 4543 } 4544 } 4545 4546 return ICE_SUCCESS; 4547 } 4548 4549 /** 4550 * ice_aq_get_internal_data 4551 * @hw: pointer to the hardware structure 4552 * @cluster_id: specific cluster to dump 4553 * @table_id: table ID within cluster 4554 * @start: index of line in the block to read 4555 * @buf: dump buffer 4556 * @buf_size: dump buffer size 4557 * @ret_buf_size: return buffer size (returned by FW) 4558 * @ret_next_table: next block to read (returned by FW) 4559 * @ret_next_index: next index to read (returned by FW) 4560 * @cd: pointer to command details structure 4561 * 4562 * Get internal FW/HW data (0xFF08) for debug purposes. 4563 */ 4564 enum ice_status 4565 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, 4566 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, 4567 u16 *ret_next_table, u32 *ret_next_index, 4568 struct ice_sq_cd *cd) 4569 { 4570 struct ice_aqc_debug_dump_internals *cmd; 4571 struct ice_aq_desc desc; 4572 enum ice_status status; 4573 4574 cmd = &desc.params.debug_dump; 4575 4576 if (buf_size == 0 || !buf) 4577 return ICE_ERR_PARAM; 4578 4579 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals); 4580 4581 cmd->cluster_id = cluster_id; 4582 cmd->table_id = CPU_TO_LE16(table_id); 4583 cmd->idx = CPU_TO_LE32(start); 4584 4585 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4586 4587 if (!status) { 4588 if (ret_buf_size) 4589 *ret_buf_size = LE16_TO_CPU(desc.datalen); 4590 if (ret_next_table) 4591 *ret_next_table = LE16_TO_CPU(cmd->table_id); 4592 if (ret_next_index) 4593 *ret_next_index = LE32_TO_CPU(cmd->idx); 4594 } 4595 4596 return status; 4597 } 4598 4599 /** 4600 * ice_read_byte - read context byte into struct 4601 * @src_ctx: the context structure to read from 4602 * @dest_ctx: the context to be written to 4603 * @ce_info: a description of the struct to be filled 4604 */ 4605 static void 4606 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4607 { 4608 u8 dest_byte, mask; 4609 u8 *src, *target; 4610 u16 shift_width; 4611 4612 /* prepare the bits and mask */ 4613 shift_width = ce_info->lsb % 8; 4614 mask = (u8)(BIT(ce_info->width) - 1); 4615 4616 /* shift to correct alignment */ 4617 mask <<= shift_width; 4618 4619 /* get the current bits from the src bit string */ 4620 src = src_ctx + (ce_info->lsb / 8); 4621 4622 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4623 4624 dest_byte &= ~(mask); 4625 4626 dest_byte >>= shift_width; 4627 4628 /* get the address from the struct field */ 4629 target = dest_ctx + ce_info->offset; 4630 4631 /* put it back in the struct */ 4632 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4633 } 4634 4635 /** 4636 * ice_read_word - read context word into struct 4637 * @src_ctx: the context structure to read from 4638 * @dest_ctx: the context to be written to 4639 * @ce_info: a description of the struct to be filled 4640 */ 4641 static void 4642 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4643 { 4644 u16 dest_word, mask; 4645 u8 *src, *target; 4646 __le16 src_word; 4647 u16 shift_width; 4648 4649 /* prepare the bits and mask */ 4650 shift_width = ce_info->lsb % 8; 4651 mask = BIT(ce_info->width) - 1; 4652 4653 /* shift to correct alignment */ 4654 mask <<= shift_width; 4655 4656 /* get the current bits from the src bit string */ 4657 src = src_ctx + (ce_info->lsb / 8); 4658 4659 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 4660 4661 /* the data in the memory is stored as little endian so mask it 4662 * correctly 4663 */ 4664 src_word &= ~(CPU_TO_LE16(mask)); 4665 4666 /* get the data back into host order before shifting */ 4667 dest_word = LE16_TO_CPU(src_word); 4668 4669 dest_word >>= shift_width; 4670 4671 /* get the address from the struct field */ 4672 target = dest_ctx + ce_info->offset; 4673 4674 /* put it back in the struct */ 4675 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4676 } 4677 4678 /** 4679 * ice_read_dword - read context dword into struct 4680 * @src_ctx: the context structure to read from 4681 * @dest_ctx: the context to be written to 4682 * @ce_info: a description of the struct to be filled 4683 */ 4684 static void 4685 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4686 { 4687 u32 dest_dword, mask; 4688 __le32 src_dword; 4689 u8 *src, *target; 4690 u16 shift_width; 4691 4692 /* prepare the bits and mask */ 4693 shift_width = ce_info->lsb % 8; 4694 4695 /* if the field width is exactly 32 on an x86 machine, then the shift 4696 * operation will not work because the SHL instructions count is masked 4697 * to 5 bits so the shift will do nothing 4698 */ 4699 if (ce_info->width < 32) 4700 mask = BIT(ce_info->width) - 1; 4701 else 4702 mask = (u32)~0; 4703 4704 /* shift to correct alignment */ 4705 mask <<= shift_width; 4706 4707 /* get the current bits from the src bit string */ 4708 src = src_ctx + (ce_info->lsb / 8); 4709 4710 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 4711 4712 /* the data in the memory is stored as little endian so mask it 4713 * correctly 4714 */ 4715 src_dword &= ~(CPU_TO_LE32(mask)); 4716 4717 /* get the data back into host order before shifting */ 4718 dest_dword = LE32_TO_CPU(src_dword); 4719 4720 dest_dword >>= shift_width; 4721 4722 /* get the address from the struct field */ 4723 target = dest_ctx + ce_info->offset; 4724 4725 /* put it back in the struct */ 4726 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4727 } 4728 4729 /** 4730 * ice_read_qword - read context qword into struct 4731 * @src_ctx: the context structure to read from 4732 * @dest_ctx: the context to be written to 4733 * @ce_info: a description of the struct to be filled 4734 */ 4735 static void 4736 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4737 { 4738 u64 dest_qword, mask; 4739 __le64 src_qword; 4740 u8 *src, *target; 4741 u16 shift_width; 4742 4743 /* prepare the bits and mask */ 4744 shift_width = ce_info->lsb % 8; 4745 4746 /* if the field width is exactly 64 on an x86 machine, then the shift 4747 * operation will not work because the SHL instructions count is masked 4748 * to 6 bits so the shift will do nothing 4749 */ 4750 if (ce_info->width < 64) 4751 mask = BIT_ULL(ce_info->width) - 1; 4752 else 4753 mask = (u64)~0; 4754 4755 /* shift to correct alignment */ 4756 mask <<= shift_width; 4757 4758 /* get the current bits from the src bit string */ 4759 src = src_ctx + (ce_info->lsb / 8); 4760 4761 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 4762 4763 /* the data in the memory is stored as little endian so mask it 4764 * correctly 4765 */ 4766 src_qword &= ~(CPU_TO_LE64(mask)); 4767 4768 /* get the data back into host order before shifting */ 4769 dest_qword = LE64_TO_CPU(src_qword); 4770 4771 dest_qword >>= shift_width; 4772 4773 /* get the address from the struct field */ 4774 target = dest_ctx + ce_info->offset; 4775 4776 /* put it back in the struct */ 4777 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4778 } 4779 4780 /** 4781 * ice_get_ctx - extract context bits from a packed structure 4782 * @src_ctx: pointer to a generic packed context structure 4783 * @dest_ctx: pointer to a generic non-packed context structure 4784 * @ce_info: a description of the structure to be read from 4785 */ 4786 enum ice_status 4787 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4788 { 4789 int f; 4790 4791 for (f = 0; ce_info[f].width; f++) { 4792 switch (ce_info[f].size_of) { 4793 case 1: 4794 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 4795 break; 4796 case 2: 4797 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 4798 break; 4799 case 4: 4800 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 4801 break; 4802 case 8: 4803 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 4804 break; 4805 default: 4806 /* nothing to do, just keep going */ 4807 break; 4808 } 4809 } 4810 4811 return ICE_SUCCESS; 4812 } 4813 4814 /** 4815 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4816 * @hw: pointer to the HW struct 4817 * @vsi_handle: software VSI handle 4818 * @tc: TC number 4819 * @q_handle: software queue handle 4820 */ 4821 struct ice_q_ctx * 4822 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4823 { 4824 struct ice_vsi_ctx *vsi; 4825 struct ice_q_ctx *q_ctx; 4826 4827 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4828 if (!vsi) 4829 return NULL; 4830 if (q_handle >= vsi->num_lan_q_entries[tc]) 4831 return NULL; 4832 if (!vsi->lan_q_ctx[tc]) 4833 return NULL; 4834 q_ctx = vsi->lan_q_ctx[tc]; 4835 return &q_ctx[q_handle]; 4836 } 4837 4838 /** 4839 * ice_ena_vsi_txq 4840 * @pi: port information structure 4841 * @vsi_handle: software VSI handle 4842 * @tc: TC number 4843 * @q_handle: software queue handle 4844 * @num_qgrps: Number of added queue groups 4845 * @buf: list of queue groups to be added 4846 * @buf_size: size of buffer for indirect command 4847 * @cd: pointer to command details structure or NULL 4848 * 4849 * This function adds one LAN queue 4850 */ 4851 enum ice_status 4852 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4853 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4854 struct ice_sq_cd *cd) 4855 { 4856 struct ice_aqc_txsched_elem_data node = { 0 }; 4857 struct ice_sched_node *parent; 4858 struct ice_q_ctx *q_ctx; 4859 enum ice_status status; 4860 struct ice_hw *hw; 4861 4862 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4863 return ICE_ERR_CFG; 4864 4865 if (num_qgrps > 1 || buf->num_txqs > 1) 4866 return ICE_ERR_MAX_LIMIT; 4867 4868 hw = pi->hw; 4869 4870 if (!ice_is_vsi_valid(hw, vsi_handle)) 4871 return ICE_ERR_PARAM; 4872 4873 ice_acquire_lock(&pi->sched_lock); 4874 4875 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4876 if (!q_ctx) { 4877 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4878 q_handle); 4879 status = ICE_ERR_PARAM; 4880 goto ena_txq_exit; 4881 } 4882 4883 /* find a parent node */ 4884 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4885 ICE_SCHED_NODE_OWNER_LAN); 4886 if (!parent) { 4887 status = ICE_ERR_PARAM; 4888 goto ena_txq_exit; 4889 } 4890 4891 buf->parent_teid = parent->info.node_teid; 4892 node.parent_teid = parent->info.node_teid; 4893 /* Mark that the values in the "generic" section as valid. The default 4894 * value in the "generic" section is zero. This means that : 4895 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4896 * - 0 priority among siblings, indicated by Bit 1-3. 4897 * - WFQ, indicated by Bit 4. 4898 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4899 * Bit 5-6. 4900 * - Bit 7 is reserved. 4901 * Without setting the generic section as valid in valid_sections, the 4902 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4903 */ 4904 buf->txqs[0].info.valid_sections = 4905 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4906 ICE_AQC_ELEM_VALID_EIR; 4907 buf->txqs[0].info.generic = 0; 4908 buf->txqs[0].info.cir_bw.bw_profile_idx = 4909 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4910 buf->txqs[0].info.cir_bw.bw_alloc = 4911 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4912 buf->txqs[0].info.eir_bw.bw_profile_idx = 4913 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4914 buf->txqs[0].info.eir_bw.bw_alloc = 4915 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4916 4917 /* add the LAN queue */ 4918 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4919 if (status != ICE_SUCCESS) { 4920 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4921 LE16_TO_CPU(buf->txqs[0].txq_id), 4922 hw->adminq.sq_last_status); 4923 goto ena_txq_exit; 4924 } 4925 4926 node.node_teid = buf->txqs[0].q_teid; 4927 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4928 q_ctx->q_handle = q_handle; 4929 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 4930 4931 /* add a leaf node into scheduler tree queue layer */ 4932 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4933 if (!status) 4934 status = ice_sched_replay_q_bw(pi, q_ctx); 4935 4936 ena_txq_exit: 4937 ice_release_lock(&pi->sched_lock); 4938 return status; 4939 } 4940 4941 /** 4942 * ice_dis_vsi_txq 4943 * @pi: port information structure 4944 * @vsi_handle: software VSI handle 4945 * @tc: TC number 4946 * @num_queues: number of queues 4947 * @q_handles: pointer to software queue handle array 4948 * @q_ids: pointer to the q_id array 4949 * @q_teids: pointer to queue node teids 4950 * @rst_src: if called due to reset, specifies the reset source 4951 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4952 * @cd: pointer to command details structure or NULL 4953 * 4954 * This function removes queues and their corresponding nodes in SW DB 4955 */ 4956 enum ice_status 4957 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4958 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4959 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4960 struct ice_sq_cd *cd) 4961 { 4962 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4963 struct ice_aqc_dis_txq_item *qg_list; 4964 struct ice_q_ctx *q_ctx; 4965 struct ice_hw *hw; 4966 u16 i, buf_size; 4967 4968 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4969 return ICE_ERR_CFG; 4970 4971 hw = pi->hw; 4972 4973 if (!num_queues) { 4974 /* if queue is disabled already yet the disable queue command 4975 * has to be sent to complete the VF reset, then call 4976 * ice_aq_dis_lan_txq without any queue information 4977 */ 4978 if (rst_src) 4979 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4980 vmvf_num, NULL); 4981 return ICE_ERR_CFG; 4982 } 4983 4984 buf_size = ice_struct_size(qg_list, q_id, 1); 4985 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size); 4986 if (!qg_list) 4987 return ICE_ERR_NO_MEMORY; 4988 4989 ice_acquire_lock(&pi->sched_lock); 4990 4991 for (i = 0; i < num_queues; i++) { 4992 struct ice_sched_node *node; 4993 4994 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4995 if (!node) 4996 continue; 4997 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4998 if (!q_ctx) { 4999 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5000 q_handles[i]); 5001 continue; 5002 } 5003 if (q_ctx->q_handle != q_handles[i]) { 5004 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5005 q_ctx->q_handle, q_handles[i]); 5006 continue; 5007 } 5008 qg_list->parent_teid = node->info.parent_teid; 5009 qg_list->num_qs = 1; 5010 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]); 5011 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5012 vmvf_num, cd); 5013 5014 if (status != ICE_SUCCESS) 5015 break; 5016 ice_free_sched_node(pi, node); 5017 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5018 } 5019 ice_release_lock(&pi->sched_lock); 5020 ice_free(hw, qg_list); 5021 return status; 5022 } 5023 5024 /** 5025 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5026 * @pi: port information structure 5027 * @vsi_handle: software VSI handle 5028 * @tc_bitmap: TC bitmap 5029 * @maxqs: max queues array per TC 5030 * @owner: LAN or RDMA 5031 * 5032 * This function adds/updates the VSI queues per TC. 5033 */ 5034 static enum ice_status 5035 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5036 u16 *maxqs, u8 owner) 5037 { 5038 enum ice_status status = ICE_SUCCESS; 5039 u8 i; 5040 5041 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5042 return ICE_ERR_CFG; 5043 5044 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5045 return ICE_ERR_PARAM; 5046 5047 ice_acquire_lock(&pi->sched_lock); 5048 5049 ice_for_each_traffic_class(i) { 5050 /* configuration is possible only if TC node is present */ 5051 if (!ice_sched_get_tc_node(pi, i)) 5052 continue; 5053 5054 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5055 ice_is_tc_ena(tc_bitmap, i)); 5056 if (status) 5057 break; 5058 } 5059 5060 ice_release_lock(&pi->sched_lock); 5061 return status; 5062 } 5063 5064 /** 5065 * ice_cfg_vsi_lan - configure VSI LAN queues 5066 * @pi: port information structure 5067 * @vsi_handle: software VSI handle 5068 * @tc_bitmap: TC bitmap 5069 * @max_lanqs: max LAN queues array per TC 5070 * 5071 * This function adds/updates the VSI LAN queues per TC. 5072 */ 5073 enum ice_status 5074 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5075 u16 *max_lanqs) 5076 { 5077 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5078 ICE_SCHED_NODE_OWNER_LAN); 5079 } 5080 5081 /** 5082 * ice_is_main_vsi - checks whether the VSI is main VSI 5083 * @hw: pointer to the HW struct 5084 * @vsi_handle: VSI handle 5085 * 5086 * Checks whether the VSI is the main VSI (the first PF VSI created on 5087 * given PF). 5088 */ 5089 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 5090 { 5091 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 5092 } 5093 5094 /** 5095 * ice_replay_pre_init - replay pre initialization 5096 * @hw: pointer to the HW struct 5097 * @sw: pointer to switch info struct for which function initializes filters 5098 * 5099 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5100 */ 5101 enum ice_status 5102 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 5103 { 5104 enum ice_status status; 5105 u8 i; 5106 5107 /* Delete old entries from replay filter list head if there is any */ 5108 ice_rm_sw_replay_rule_info(hw, sw); 5109 /* In start of replay, move entries into replay_rules list, it 5110 * will allow adding rules entries back to filt_rules list, 5111 * which is operational list. 5112 */ 5113 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5114 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 5115 &sw->recp_list[i].filt_replay_rules); 5116 ice_sched_replay_agg_vsi_preinit(hw); 5117 5118 status = ice_sched_replay_root_node_bw(hw->port_info); 5119 if (status) 5120 return status; 5121 5122 return ice_sched_replay_tc_node_bw(hw->port_info); 5123 } 5124 5125 /** 5126 * ice_replay_vsi - replay VSI configuration 5127 * @hw: pointer to the HW struct 5128 * @vsi_handle: driver VSI handle 5129 * 5130 * Restore all VSI configuration after reset. It is required to call this 5131 * function with main VSI first. 5132 */ 5133 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5134 { 5135 struct ice_switch_info *sw = hw->switch_info; 5136 struct ice_port_info *pi = hw->port_info; 5137 enum ice_status status; 5138 5139 if (!ice_is_vsi_valid(hw, vsi_handle)) 5140 return ICE_ERR_PARAM; 5141 5142 /* Replay pre-initialization if there is any */ 5143 if (ice_is_main_vsi(hw, vsi_handle)) { 5144 status = ice_replay_pre_init(hw, sw); 5145 if (status) 5146 return status; 5147 } 5148 /* Replay per VSI all RSS configurations */ 5149 status = ice_replay_rss_cfg(hw, vsi_handle); 5150 if (status) 5151 return status; 5152 /* Replay per VSI all filters */ 5153 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 5154 if (!status) 5155 status = ice_replay_vsi_agg(hw, vsi_handle); 5156 return status; 5157 } 5158 5159 /** 5160 * ice_replay_post - post replay configuration cleanup 5161 * @hw: pointer to the HW struct 5162 * 5163 * Post replay cleanup. 5164 */ 5165 void ice_replay_post(struct ice_hw *hw) 5166 { 5167 /* Delete old entries from replay filter list head */ 5168 ice_rm_all_sw_replay_rule_info(hw); 5169 ice_sched_replay_agg(hw); 5170 } 5171 5172 /** 5173 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5174 * @hw: ptr to the hardware info 5175 * @reg: offset of 64 bit HW register to read from 5176 * @prev_stat_loaded: bool to specify if previous stats are loaded 5177 * @prev_stat: ptr to previous loaded stat value 5178 * @cur_stat: ptr to current stat value 5179 */ 5180 void 5181 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5182 u64 *prev_stat, u64 *cur_stat) 5183 { 5184 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5185 5186 /* device stats are not reset at PFR, they likely will not be zeroed 5187 * when the driver starts. Thus, save the value from the first read 5188 * without adding to the statistic value so that we report stats which 5189 * count up from zero. 5190 */ 5191 if (!prev_stat_loaded) { 5192 *prev_stat = new_data; 5193 return; 5194 } 5195 5196 /* Calculate the difference between the new and old values, and then 5197 * add it to the software stat value. 5198 */ 5199 if (new_data >= *prev_stat) 5200 *cur_stat += new_data - *prev_stat; 5201 else 5202 /* to manage the potential roll-over */ 5203 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5204 5205 /* Update the previously stored value to prepare for next read */ 5206 *prev_stat = new_data; 5207 } 5208 5209 /** 5210 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5211 * @hw: ptr to the hardware info 5212 * @reg: offset of HW register to read from 5213 * @prev_stat_loaded: bool to specify if previous stats are loaded 5214 * @prev_stat: ptr to previous loaded stat value 5215 * @cur_stat: ptr to current stat value 5216 */ 5217 void 5218 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5219 u64 *prev_stat, u64 *cur_stat) 5220 { 5221 u32 new_data; 5222 5223 new_data = rd32(hw, reg); 5224 5225 /* device stats are not reset at PFR, they likely will not be zeroed 5226 * when the driver starts. Thus, save the value from the first read 5227 * without adding to the statistic value so that we report stats which 5228 * count up from zero. 5229 */ 5230 if (!prev_stat_loaded) { 5231 *prev_stat = new_data; 5232 return; 5233 } 5234 5235 /* Calculate the difference between the new and old values, and then 5236 * add it to the software stat value. 5237 */ 5238 if (new_data >= *prev_stat) 5239 *cur_stat += new_data - *prev_stat; 5240 else 5241 /* to manage the potential roll-over */ 5242 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5243 5244 /* Update the previously stored value to prepare for next read */ 5245 *prev_stat = new_data; 5246 } 5247 5248 /** 5249 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 5250 * @hw: ptr to the hardware info 5251 * @vsi_handle: VSI handle 5252 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 5253 * @cur_stats: ptr to current stats structure 5254 * 5255 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 5256 * thus cannot be read using the normal ice_stat_update32 function. 5257 * 5258 * Read the GLV_REPC register associated with the given VSI, and update the 5259 * rx_no_desc and rx_error values in the ice_eth_stats structure. 5260 * 5261 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 5262 * cleared each time it's read. 5263 * 5264 * Note that the GLV_RDPC register also counts the causes that would trigger 5265 * GLV_REPC. However, it does not give the finer grained detail about why the 5266 * packets are being dropped. The GLV_REPC values can be used to distinguish 5267 * whether Rx packets are dropped due to errors or due to no available 5268 * descriptors. 5269 */ 5270 void 5271 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 5272 struct ice_eth_stats *cur_stats) 5273 { 5274 u16 vsi_num, no_desc, error_cnt; 5275 u32 repc; 5276 5277 if (!ice_is_vsi_valid(hw, vsi_handle)) 5278 return; 5279 5280 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 5281 5282 /* If we haven't loaded stats yet, just clear the current value */ 5283 if (!prev_stat_loaded) { 5284 wr32(hw, GLV_REPC(vsi_num), 0); 5285 return; 5286 } 5287 5288 repc = rd32(hw, GLV_REPC(vsi_num)); 5289 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 5290 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 5291 5292 /* Clear the count by writing to the stats register */ 5293 wr32(hw, GLV_REPC(vsi_num), 0); 5294 5295 cur_stats->rx_no_desc += no_desc; 5296 cur_stats->rx_errors += error_cnt; 5297 } 5298 5299 /** 5300 * ice_sched_query_elem - query element information from HW 5301 * @hw: pointer to the HW struct 5302 * @node_teid: node TEID to be queried 5303 * @buf: buffer to element information 5304 * 5305 * This function queries HW element information 5306 */ 5307 enum ice_status 5308 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5309 struct ice_aqc_txsched_elem_data *buf) 5310 { 5311 u16 buf_size, num_elem_ret = 0; 5312 enum ice_status status; 5313 5314 buf_size = sizeof(*buf); 5315 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 5316 buf->node_teid = CPU_TO_LE32(node_teid); 5317 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5318 NULL); 5319 if (status != ICE_SUCCESS || num_elem_ret != 1) 5320 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5321 return status; 5322 } 5323 5324 /** 5325 * ice_get_fw_mode - returns FW mode 5326 * @hw: pointer to the HW struct 5327 */ 5328 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 5329 { 5330 #define ICE_FW_MODE_DBG_M BIT(0) 5331 #define ICE_FW_MODE_REC_M BIT(1) 5332 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 5333 u32 fw_mode; 5334 5335 /* check the current FW mode */ 5336 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 5337 5338 if (fw_mode & ICE_FW_MODE_DBG_M) 5339 return ICE_FW_MODE_DBG; 5340 else if (fw_mode & ICE_FW_MODE_REC_M) 5341 return ICE_FW_MODE_REC; 5342 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 5343 return ICE_FW_MODE_ROLLBACK; 5344 else 5345 return ICE_FW_MODE_NORMAL; 5346 } 5347 5348 /** 5349 * ice_aq_read_i2c 5350 * @hw: pointer to the hw struct 5351 * @topo_addr: topology address for a device to communicate with 5352 * @bus_addr: 7-bit I2C bus address 5353 * @addr: I2C memory address (I2C offset) with up to 16 bits 5354 * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size, 5355 * bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes) 5356 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5357 * @cd: pointer to command details structure or NULL 5358 * 5359 * Read I2C (0x06E2) 5360 */ 5361 enum ice_status 5362 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5363 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5364 struct ice_sq_cd *cd) 5365 { 5366 struct ice_aq_desc desc = { 0 }; 5367 struct ice_aqc_i2c *cmd; 5368 enum ice_status status; 5369 u8 data_size; 5370 5371 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5372 cmd = &desc.params.read_write_i2c; 5373 5374 if (!data) 5375 return ICE_ERR_PARAM; 5376 5377 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S; 5378 5379 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr); 5380 cmd->topo_addr = topo_addr; 5381 cmd->i2c_params = params; 5382 cmd->i2c_addr = addr; 5383 5384 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5385 if (!status) { 5386 struct ice_aqc_read_i2c_resp *resp; 5387 u8 i; 5388 5389 resp = &desc.params.read_i2c_resp; 5390 for (i = 0; i < data_size; i++) { 5391 *data = resp->i2c_data[i]; 5392 data++; 5393 } 5394 } 5395 5396 return status; 5397 } 5398 5399 /** 5400 * ice_aq_write_i2c 5401 * @hw: pointer to the hw struct 5402 * @topo_addr: topology address for a device to communicate with 5403 * @bus_addr: 7-bit I2C bus address 5404 * @addr: I2C memory address (I2C offset) with up to 16 bits 5405 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5406 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5407 * @cd: pointer to command details structure or NULL 5408 * 5409 * Write I2C (0x06E3) 5410 */ 5411 enum ice_status 5412 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5413 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5414 struct ice_sq_cd *cd) 5415 { 5416 struct ice_aq_desc desc = { 0 }; 5417 struct ice_aqc_i2c *cmd; 5418 u8 i, data_size; 5419 5420 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5421 cmd = &desc.params.read_write_i2c; 5422 5423 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S; 5424 5425 /* data_size limited to 4 */ 5426 if (data_size > 4) 5427 return ICE_ERR_PARAM; 5428 5429 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr); 5430 cmd->topo_addr = topo_addr; 5431 cmd->i2c_params = params; 5432 cmd->i2c_addr = addr; 5433 5434 for (i = 0; i < data_size; i++) { 5435 cmd->i2c_data[i] = *data; 5436 data++; 5437 } 5438 5439 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5440 } 5441 5442 /** 5443 * ice_aq_set_gpio 5444 * @hw: pointer to the hw struct 5445 * @gpio_ctrl_handle: GPIO controller node handle 5446 * @pin_idx: IO Number of the GPIO that needs to be set 5447 * @value: SW provide IO value to set in the LSB 5448 * @cd: pointer to command details structure or NULL 5449 * 5450 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5451 */ 5452 enum ice_status 5453 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5454 struct ice_sq_cd *cd) 5455 { 5456 struct ice_aqc_gpio *cmd; 5457 struct ice_aq_desc desc; 5458 5459 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5460 cmd = &desc.params.read_write_gpio; 5461 cmd->gpio_ctrl_handle = gpio_ctrl_handle; 5462 cmd->gpio_num = pin_idx; 5463 cmd->gpio_val = value ? 1 : 0; 5464 5465 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5466 } 5467 5468 /** 5469 * ice_aq_get_gpio 5470 * @hw: pointer to the hw struct 5471 * @gpio_ctrl_handle: GPIO controller node handle 5472 * @pin_idx: IO Number of the GPIO that needs to be set 5473 * @value: IO value read 5474 * @cd: pointer to command details structure or NULL 5475 * 5476 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5477 * the topology 5478 */ 5479 enum ice_status 5480 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5481 bool *value, struct ice_sq_cd *cd) 5482 { 5483 struct ice_aqc_gpio *cmd; 5484 struct ice_aq_desc desc; 5485 enum ice_status status; 5486 5487 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5488 cmd = &desc.params.read_write_gpio; 5489 cmd->gpio_ctrl_handle = gpio_ctrl_handle; 5490 cmd->gpio_num = pin_idx; 5491 5492 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5493 if (status) 5494 return status; 5495 5496 *value = !!cmd->gpio_val; 5497 return ICE_SUCCESS; 5498 } 5499 5500 /** 5501 * ice_fw_supports_link_override 5502 * @hw: pointer to the hardware structure 5503 * 5504 * Checks if the firmware supports link override 5505 */ 5506 bool ice_fw_supports_link_override(struct ice_hw *hw) 5507 { 5508 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 5509 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 5510 return true; 5511 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 5512 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 5513 return true; 5514 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 5515 return true; 5516 } 5517 5518 return false; 5519 } 5520 5521 /** 5522 * ice_get_link_default_override 5523 * @ldo: pointer to the link default override struct 5524 * @pi: pointer to the port info struct 5525 * 5526 * Gets the link default override for a port 5527 */ 5528 enum ice_status 5529 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5530 struct ice_port_info *pi) 5531 { 5532 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5533 struct ice_hw *hw = pi->hw; 5534 enum ice_status status; 5535 5536 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5537 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5538 if (status) { 5539 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5540 return status; 5541 } 5542 5543 /* Each port has its own config; calculate for our port */ 5544 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5545 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5546 5547 /* link options first */ 5548 status = ice_read_sr_word(hw, tlv_start, &buf); 5549 if (status) { 5550 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5551 return status; 5552 } 5553 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5554 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5555 ICE_LINK_OVERRIDE_PHY_CFG_S; 5556 5557 /* link PHY config */ 5558 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5559 status = ice_read_sr_word(hw, offset, &buf); 5560 if (status) { 5561 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5562 return status; 5563 } 5564 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5565 5566 /* PHY types low */ 5567 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5568 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5569 status = ice_read_sr_word(hw, (offset + i), &buf); 5570 if (status) { 5571 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5572 return status; 5573 } 5574 /* shift 16 bits at a time to fill 64 bits */ 5575 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5576 } 5577 5578 /* PHY types high */ 5579 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5580 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5581 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5582 status = ice_read_sr_word(hw, (offset + i), &buf); 5583 if (status) { 5584 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5585 return status; 5586 } 5587 /* shift 16 bits at a time to fill 64 bits */ 5588 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5589 } 5590 5591 return status; 5592 } 5593 5594 /** 5595 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5596 * @caps: get PHY capability data 5597 */ 5598 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5599 { 5600 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5601 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5602 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5603 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5604 return true; 5605 5606 return false; 5607 } 5608 5609 /** 5610 * ice_aq_set_lldp_mib - Set the LLDP MIB 5611 * @hw: pointer to the HW struct 5612 * @mib_type: Local, Remote or both Local and Remote MIBs 5613 * @buf: pointer to the caller-supplied buffer to store the MIB block 5614 * @buf_size: size of the buffer (in bytes) 5615 * @cd: pointer to command details structure or NULL 5616 * 5617 * Set the LLDP MIB. (0x0A08) 5618 */ 5619 enum ice_status 5620 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5621 struct ice_sq_cd *cd) 5622 { 5623 struct ice_aqc_lldp_set_local_mib *cmd; 5624 struct ice_aq_desc desc; 5625 5626 cmd = &desc.params.lldp_set_mib; 5627 5628 if (buf_size == 0 || !buf) 5629 return ICE_ERR_PARAM; 5630 5631 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5632 5633 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD); 5634 desc.datalen = CPU_TO_LE16(buf_size); 5635 5636 cmd->type = mib_type; 5637 cmd->length = CPU_TO_LE16(buf_size); 5638 5639 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5640 } 5641 5642 /** 5643 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5644 * @hw: pointer to HW struct 5645 */ 5646 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5647 { 5648 if (hw->mac_type != ICE_MAC_E810) 5649 return false; 5650 5651 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 5652 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 5653 return true; 5654 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 5655 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 5656 return true; 5657 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 5658 return true; 5659 } 5660 return false; 5661 } 5662 5663 /** 5664 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5665 * @hw: pointer to HW struct 5666 * @vsi_num: absolute HW index for VSI 5667 * @add: boolean for if adding or removing a filter 5668 */ 5669 enum ice_status 5670 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5671 { 5672 struct ice_aqc_lldp_filter_ctrl *cmd; 5673 struct ice_aq_desc desc; 5674 5675 cmd = &desc.params.lldp_filter_ctrl; 5676 5677 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5678 5679 if (add) 5680 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5681 else 5682 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5683 5684 cmd->vsi_num = CPU_TO_LE16(vsi_num); 5685 5686 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5687 } 5688 5689 /** 5690 * ice_fw_supports_report_dflt_cfg 5691 * @hw: pointer to the hardware structure 5692 * 5693 * Checks if the firmware supports report default configuration 5694 */ 5695 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5696 { 5697 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5698 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 5699 return true; 5700 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 5701 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 5702 return true; 5703 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5704 return true; 5705 } 5706 return false; 5707 } 5708