1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 300 13 14 /** 15 * ice_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the MAC type of the adapter based on the 19 * vendor ID and device ID stored in the HW structure. 20 */ 21 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 22 { 23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 24 25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 26 return ICE_ERR_DEVICE_NOT_SUPPORTED; 27 28 switch (hw->device_id) { 29 case ICE_DEV_ID_E810C_BACKPLANE: 30 case ICE_DEV_ID_E810C_QSFP: 31 case ICE_DEV_ID_E810C_SFP: 32 case ICE_DEV_ID_E810_XXV_BACKPLANE: 33 case ICE_DEV_ID_E810_XXV_QSFP: 34 case ICE_DEV_ID_E810_XXV_SFP: 35 hw->mac_type = ICE_MAC_E810; 36 break; 37 case ICE_DEV_ID_E822C_10G_BASE_T: 38 case ICE_DEV_ID_E822C_BACKPLANE: 39 case ICE_DEV_ID_E822C_QSFP: 40 case ICE_DEV_ID_E822C_SFP: 41 case ICE_DEV_ID_E822C_SGMII: 42 case ICE_DEV_ID_E822L_10G_BASE_T: 43 case ICE_DEV_ID_E822L_BACKPLANE: 44 case ICE_DEV_ID_E822L_SFP: 45 case ICE_DEV_ID_E822L_SGMII: 46 case ICE_DEV_ID_E823L_10G_BASE_T: 47 case ICE_DEV_ID_E823L_1GBE: 48 case ICE_DEV_ID_E823L_BACKPLANE: 49 case ICE_DEV_ID_E823L_QSFP: 50 case ICE_DEV_ID_E823L_SFP: 51 case ICE_DEV_ID_E823C_10G_BASE_T: 52 case ICE_DEV_ID_E823C_BACKPLANE: 53 case ICE_DEV_ID_E823C_QSFP: 54 case ICE_DEV_ID_E823C_SFP: 55 case ICE_DEV_ID_E823C_SGMII: 56 hw->mac_type = ICE_MAC_GENERIC; 57 break; 58 default: 59 hw->mac_type = ICE_MAC_UNKNOWN; 60 break; 61 } 62 63 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 64 return ICE_SUCCESS; 65 } 66 67 /** 68 * ice_clear_pf_cfg - Clear PF configuration 69 * @hw: pointer to the hardware structure 70 * 71 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 72 * configuration, flow director filters, etc.). 73 */ 74 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 75 { 76 struct ice_aq_desc desc; 77 78 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 79 80 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 81 } 82 83 /** 84 * ice_aq_manage_mac_read - manage MAC address read command 85 * @hw: pointer to the HW struct 86 * @buf: a virtual buffer to hold the manage MAC read response 87 * @buf_size: Size of the virtual buffer 88 * @cd: pointer to command details structure or NULL 89 * 90 * This function is used to return per PF station MAC address (0x0107). 91 * NOTE: Upon successful completion of this command, MAC address information 92 * is returned in user specified buffer. Please interpret user specified 93 * buffer as "manage_mac_read" response. 94 * Response such as various MAC addresses are stored in HW struct (port.mac) 95 * ice_discover_dev_caps is expected to be called before this function is 96 * called. 97 */ 98 static enum ice_status 99 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 100 struct ice_sq_cd *cd) 101 { 102 struct ice_aqc_manage_mac_read_resp *resp; 103 struct ice_aqc_manage_mac_read *cmd; 104 struct ice_aq_desc desc; 105 enum ice_status status; 106 u16 flags; 107 u8 i; 108 109 cmd = &desc.params.mac_read; 110 111 if (buf_size < sizeof(*resp)) 112 return ICE_ERR_BUF_TOO_SHORT; 113 114 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 115 116 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 117 if (status) 118 return status; 119 120 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 121 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 122 123 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 124 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 125 return ICE_ERR_CFG; 126 } 127 128 /* A single port can report up to two (LAN and WoL) addresses */ 129 for (i = 0; i < cmd->num_addr; i++) 130 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 131 ice_memcpy(hw->port_info->mac.lan_addr, 132 resp[i].mac_addr, ETH_ALEN, 133 ICE_DMA_TO_NONDMA); 134 ice_memcpy(hw->port_info->mac.perm_addr, 135 resp[i].mac_addr, 136 ETH_ALEN, ICE_DMA_TO_NONDMA); 137 break; 138 } 139 return ICE_SUCCESS; 140 } 141 142 /** 143 * ice_aq_get_phy_caps - returns PHY capabilities 144 * @pi: port information structure 145 * @qual_mods: report qualified modules 146 * @report_mode: report mode capabilities 147 * @pcaps: structure for PHY capabilities to be filled 148 * @cd: pointer to command details structure or NULL 149 * 150 * Returns the various PHY capabilities supported on the Port (0x0600) 151 */ 152 enum ice_status 153 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 154 struct ice_aqc_get_phy_caps_data *pcaps, 155 struct ice_sq_cd *cd) 156 { 157 struct ice_aqc_get_phy_caps *cmd; 158 u16 pcaps_size = sizeof(*pcaps); 159 struct ice_aq_desc desc; 160 enum ice_status status; 161 struct ice_hw *hw; 162 163 cmd = &desc.params.get_phy; 164 165 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 166 return ICE_ERR_PARAM; 167 hw = pi->hw; 168 169 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 170 !ice_fw_supports_report_dflt_cfg(hw)) 171 return ICE_ERR_PARAM; 172 173 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 174 175 if (qual_mods) 176 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 177 178 cmd->param0 |= CPU_TO_LE16(report_mode); 179 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 180 181 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 182 report_mode); 183 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 184 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); 185 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 186 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); 187 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 188 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 189 pcaps->low_power_ctrl_an); 190 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 191 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 192 pcaps->eeer_value); 193 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 194 pcaps->link_fec_options); 195 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 196 pcaps->module_compliance_enforcement); 197 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 198 pcaps->extended_compliance_code); 199 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 200 pcaps->module_type[0]); 201 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 202 pcaps->module_type[1]); 203 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 204 pcaps->module_type[2]); 205 206 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 207 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 208 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 209 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 210 sizeof(pi->phy.link_info.module_type), 211 ICE_NONDMA_TO_NONDMA); 212 } 213 214 return status; 215 } 216 217 /** 218 * ice_aq_get_link_topo_handle - get link topology node return status 219 * @pi: port information structure 220 * @node_type: requested node type 221 * @cd: pointer to command details structure or NULL 222 * 223 * Get link topology node return status for specified node type (0x06E0) 224 * 225 * Node type cage can be used to determine if cage is present. If AQC 226 * returns error (ENOENT), then no cage present. If no cage present, then 227 * connection type is backplane or BASE-T. 228 */ 229 static enum ice_status 230 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 231 struct ice_sq_cd *cd) 232 { 233 struct ice_aqc_get_link_topo *cmd; 234 struct ice_aq_desc desc; 235 236 cmd = &desc.params.get_link_topo; 237 238 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 239 240 cmd->addr.topo_params.node_type_ctx = 241 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 242 ICE_AQC_LINK_TOPO_NODE_CTX_S); 243 244 /* set node type */ 245 cmd->addr.topo_params.node_type_ctx |= 246 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 247 248 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 249 } 250 251 /** 252 * ice_is_media_cage_present 253 * @pi: port information structure 254 * 255 * Returns true if media cage is present, else false. If no cage, then 256 * media type is backplane or BASE-T. 257 */ 258 static bool ice_is_media_cage_present(struct ice_port_info *pi) 259 { 260 /* Node type cage can be used to determine if cage is present. If AQC 261 * returns error (ENOENT), then no cage present. If no cage present then 262 * connection type is backplane or BASE-T. 263 */ 264 return !ice_aq_get_link_topo_handle(pi, 265 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 266 NULL); 267 } 268 269 /** 270 * ice_get_media_type - Gets media type 271 * @pi: port information structure 272 */ 273 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 274 { 275 struct ice_link_status *hw_link_info; 276 277 if (!pi) 278 return ICE_MEDIA_UNKNOWN; 279 280 hw_link_info = &pi->phy.link_info; 281 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 282 /* If more than one media type is selected, report unknown */ 283 return ICE_MEDIA_UNKNOWN; 284 285 if (hw_link_info->phy_type_low) { 286 /* 1G SGMII is a special case where some DA cable PHYs 287 * may show this as an option when it really shouldn't 288 * be since SGMII is meant to be between a MAC and a PHY 289 * in a backplane. Try to detect this case and handle it 290 */ 291 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 292 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 293 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 294 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 295 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 296 return ICE_MEDIA_DA; 297 298 switch (hw_link_info->phy_type_low) { 299 case ICE_PHY_TYPE_LOW_1000BASE_SX: 300 case ICE_PHY_TYPE_LOW_1000BASE_LX: 301 case ICE_PHY_TYPE_LOW_10GBASE_SR: 302 case ICE_PHY_TYPE_LOW_10GBASE_LR: 303 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 304 case ICE_PHY_TYPE_LOW_25GBASE_SR: 305 case ICE_PHY_TYPE_LOW_25GBASE_LR: 306 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 307 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 308 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 309 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 310 case ICE_PHY_TYPE_LOW_50GBASE_SR: 311 case ICE_PHY_TYPE_LOW_50GBASE_FR: 312 case ICE_PHY_TYPE_LOW_50GBASE_LR: 313 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 314 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 315 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 316 case ICE_PHY_TYPE_LOW_100GBASE_DR: 317 return ICE_MEDIA_FIBER; 318 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 319 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 320 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 321 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 322 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 323 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 324 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 325 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 326 return ICE_MEDIA_FIBER; 327 case ICE_PHY_TYPE_LOW_100BASE_TX: 328 case ICE_PHY_TYPE_LOW_1000BASE_T: 329 case ICE_PHY_TYPE_LOW_2500BASE_T: 330 case ICE_PHY_TYPE_LOW_5GBASE_T: 331 case ICE_PHY_TYPE_LOW_10GBASE_T: 332 case ICE_PHY_TYPE_LOW_25GBASE_T: 333 return ICE_MEDIA_BASET; 334 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 335 case ICE_PHY_TYPE_LOW_25GBASE_CR: 336 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 337 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 338 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 339 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 340 case ICE_PHY_TYPE_LOW_50GBASE_CP: 341 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 342 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 343 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 344 return ICE_MEDIA_DA; 345 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 346 case ICE_PHY_TYPE_LOW_40G_XLAUI: 347 case ICE_PHY_TYPE_LOW_50G_LAUI2: 348 case ICE_PHY_TYPE_LOW_50G_AUI2: 349 case ICE_PHY_TYPE_LOW_50G_AUI1: 350 case ICE_PHY_TYPE_LOW_100G_AUI4: 351 case ICE_PHY_TYPE_LOW_100G_CAUI4: 352 if (ice_is_media_cage_present(pi)) 353 return ICE_MEDIA_AUI; 354 /* fall-through */ 355 case ICE_PHY_TYPE_LOW_1000BASE_KX: 356 case ICE_PHY_TYPE_LOW_2500BASE_KX: 357 case ICE_PHY_TYPE_LOW_2500BASE_X: 358 case ICE_PHY_TYPE_LOW_5GBASE_KR: 359 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 360 case ICE_PHY_TYPE_LOW_25GBASE_KR: 361 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 362 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 363 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 364 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 365 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 366 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 367 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 368 return ICE_MEDIA_BACKPLANE; 369 } 370 } else { 371 switch (hw_link_info->phy_type_high) { 372 case ICE_PHY_TYPE_HIGH_100G_AUI2: 373 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 374 if (ice_is_media_cage_present(pi)) 375 return ICE_MEDIA_AUI; 376 /* fall-through */ 377 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 378 return ICE_MEDIA_BACKPLANE; 379 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 380 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 381 return ICE_MEDIA_FIBER; 382 } 383 } 384 return ICE_MEDIA_UNKNOWN; 385 } 386 387 /** 388 * ice_aq_get_link_info 389 * @pi: port information structure 390 * @ena_lse: enable/disable LinkStatusEvent reporting 391 * @link: pointer to link status structure - optional 392 * @cd: pointer to command details structure or NULL 393 * 394 * Get Link Status (0x607). Returns the link status of the adapter. 395 */ 396 enum ice_status 397 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 398 struct ice_link_status *link, struct ice_sq_cd *cd) 399 { 400 struct ice_aqc_get_link_status_data link_data = { 0 }; 401 struct ice_aqc_get_link_status *resp; 402 struct ice_link_status *li_old, *li; 403 enum ice_media_type *hw_media_type; 404 struct ice_fc_info *hw_fc_info; 405 bool tx_pause, rx_pause; 406 struct ice_aq_desc desc; 407 enum ice_status status; 408 struct ice_hw *hw; 409 u16 cmd_flags; 410 411 if (!pi) 412 return ICE_ERR_PARAM; 413 hw = pi->hw; 414 li_old = &pi->phy.link_info_old; 415 hw_media_type = &pi->phy.media_type; 416 li = &pi->phy.link_info; 417 hw_fc_info = &pi->fc; 418 419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 420 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 421 resp = &desc.params.get_link_status; 422 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 423 resp->lport_num = pi->lport; 424 425 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 426 427 if (status != ICE_SUCCESS) 428 return status; 429 430 /* save off old link status information */ 431 *li_old = *li; 432 433 /* update current link status information */ 434 li->link_speed = LE16_TO_CPU(link_data.link_speed); 435 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 436 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 437 *hw_media_type = ice_get_media_type(pi); 438 li->link_info = link_data.link_info; 439 li->link_cfg_err = link_data.link_cfg_err; 440 li->an_info = link_data.an_info; 441 li->ext_info = link_data.ext_info; 442 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 443 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 444 li->topo_media_conflict = link_data.topo_media_conflict; 445 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 446 ICE_AQ_CFG_PACING_TYPE_M); 447 448 /* update fc info */ 449 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 450 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 451 if (tx_pause && rx_pause) 452 hw_fc_info->current_mode = ICE_FC_FULL; 453 else if (tx_pause) 454 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 455 else if (rx_pause) 456 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 457 else 458 hw_fc_info->current_mode = ICE_FC_NONE; 459 460 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 461 462 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 463 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 464 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 465 (unsigned long long)li->phy_type_low); 466 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 467 (unsigned long long)li->phy_type_high); 468 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 469 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 470 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 471 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 472 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 473 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 474 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 475 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 476 li->max_frame_size); 477 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 478 479 /* save link status information */ 480 if (link) 481 *link = *li; 482 483 /* flag cleared so calling functions don't call AQ again */ 484 pi->phy.get_link_info = false; 485 486 return ICE_SUCCESS; 487 } 488 489 /** 490 * ice_fill_tx_timer_and_fc_thresh 491 * @hw: pointer to the HW struct 492 * @cmd: pointer to MAC cfg structure 493 * 494 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 495 * descriptor 496 */ 497 static void 498 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 499 struct ice_aqc_set_mac_cfg *cmd) 500 { 501 u16 fc_thres_val, tx_timer_val; 502 u32 val; 503 504 /* We read back the transmit timer and fc threshold value of 505 * LFC. Thus, we will use index = 506 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 507 * 508 * Also, because we are opearating on transmit timer and fc 509 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 510 */ 511 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 512 513 /* Retrieve the transmit timer */ 514 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 515 tx_timer_val = val & 516 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 517 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 518 519 /* Retrieve the fc threshold */ 520 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 521 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 522 523 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 524 } 525 526 /** 527 * ice_aq_set_mac_cfg 528 * @hw: pointer to the HW struct 529 * @max_frame_size: Maximum Frame Size to be supported 530 * @cd: pointer to command details structure or NULL 531 * 532 * Set MAC configuration (0x0603) 533 */ 534 enum ice_status 535 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 536 { 537 struct ice_aqc_set_mac_cfg *cmd; 538 struct ice_aq_desc desc; 539 540 cmd = &desc.params.set_mac_cfg; 541 542 if (max_frame_size == 0) 543 return ICE_ERR_PARAM; 544 545 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 546 547 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 548 549 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 550 551 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 552 } 553 554 /** 555 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 556 * @hw: pointer to the HW struct 557 */ 558 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 559 { 560 struct ice_switch_info *sw; 561 enum ice_status status; 562 563 hw->switch_info = (struct ice_switch_info *) 564 ice_malloc(hw, sizeof(*hw->switch_info)); 565 566 sw = hw->switch_info; 567 568 if (!sw) 569 return ICE_ERR_NO_MEMORY; 570 571 INIT_LIST_HEAD(&sw->vsi_list_map_head); 572 sw->prof_res_bm_init = 0; 573 574 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 575 if (status) { 576 ice_free(hw, hw->switch_info); 577 return status; 578 } 579 return ICE_SUCCESS; 580 } 581 582 /** 583 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 584 * @hw: pointer to the HW struct 585 * @sw: pointer to switch info struct for which function clears filters 586 */ 587 static void 588 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 589 { 590 struct ice_vsi_list_map_info *v_pos_map; 591 struct ice_vsi_list_map_info *v_tmp_map; 592 struct ice_sw_recipe *recps; 593 u8 i; 594 595 if (!sw) 596 return; 597 598 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 599 ice_vsi_list_map_info, list_entry) { 600 LIST_DEL(&v_pos_map->list_entry); 601 ice_free(hw, v_pos_map); 602 } 603 recps = sw->recp_list; 604 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 605 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 606 607 recps[i].root_rid = i; 608 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 609 &recps[i].rg_list, ice_recp_grp_entry, 610 l_entry) { 611 LIST_DEL(&rg_entry->l_entry); 612 ice_free(hw, rg_entry); 613 } 614 615 if (recps[i].adv_rule) { 616 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 617 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 618 619 ice_destroy_lock(&recps[i].filt_rule_lock); 620 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 621 &recps[i].filt_rules, 622 ice_adv_fltr_mgmt_list_entry, 623 list_entry) { 624 LIST_DEL(&lst_itr->list_entry); 625 ice_free(hw, lst_itr->lkups); 626 ice_free(hw, lst_itr); 627 } 628 } else { 629 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 630 631 ice_destroy_lock(&recps[i].filt_rule_lock); 632 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 633 &recps[i].filt_rules, 634 ice_fltr_mgmt_list_entry, 635 list_entry) { 636 LIST_DEL(&lst_itr->list_entry); 637 ice_free(hw, lst_itr); 638 } 639 } 640 if (recps[i].root_buf) 641 ice_free(hw, recps[i].root_buf); 642 } 643 ice_rm_sw_replay_rule_info(hw, sw); 644 ice_free(hw, sw->recp_list); 645 ice_free(hw, sw); 646 } 647 648 /** 649 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 650 * @hw: pointer to the HW struct 651 */ 652 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 653 { 654 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 655 } 656 657 /** 658 * ice_get_itr_intrl_gran 659 * @hw: pointer to the HW struct 660 * 661 * Determines the ITR/INTRL granularities based on the maximum aggregate 662 * bandwidth according to the device's configuration during power-on. 663 */ 664 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 665 { 666 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 667 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 668 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 669 670 switch (max_agg_bw) { 671 case ICE_MAX_AGG_BW_200G: 672 case ICE_MAX_AGG_BW_100G: 673 case ICE_MAX_AGG_BW_50G: 674 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 675 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 676 break; 677 case ICE_MAX_AGG_BW_25G: 678 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 679 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 680 break; 681 } 682 } 683 684 /** 685 * ice_print_rollback_msg - print FW rollback message 686 * @hw: pointer to the hardware structure 687 */ 688 void ice_print_rollback_msg(struct ice_hw *hw) 689 { 690 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 691 struct ice_orom_info *orom; 692 struct ice_nvm_info *nvm; 693 694 orom = &hw->flash.orom; 695 nvm = &hw->flash.nvm; 696 697 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 698 nvm->major, nvm->minor, nvm->eetrack, orom->major, 699 orom->build, orom->patch); 700 ice_warn(hw, 701 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 702 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 703 } 704 705 /** 706 * ice_init_hw - main hardware initialization routine 707 * @hw: pointer to the hardware structure 708 */ 709 enum ice_status ice_init_hw(struct ice_hw *hw) 710 { 711 struct ice_aqc_get_phy_caps_data *pcaps; 712 enum ice_status status; 713 u16 mac_buf_len; 714 void *mac_buf; 715 716 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 717 718 /* Set MAC type based on DeviceID */ 719 status = ice_set_mac_type(hw); 720 if (status) 721 return status; 722 723 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 724 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 725 PF_FUNC_RID_FUNCTION_NUMBER_S; 726 727 status = ice_reset(hw, ICE_RESET_PFR); 728 if (status) 729 return status; 730 731 ice_get_itr_intrl_gran(hw); 732 733 status = ice_create_all_ctrlq(hw); 734 if (status) 735 goto err_unroll_cqinit; 736 737 status = ice_init_nvm(hw); 738 if (status) 739 goto err_unroll_cqinit; 740 741 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 742 ice_print_rollback_msg(hw); 743 744 status = ice_clear_pf_cfg(hw); 745 if (status) 746 goto err_unroll_cqinit; 747 748 /* Set bit to enable Flow Director filters */ 749 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 750 INIT_LIST_HEAD(&hw->fdir_list_head); 751 752 ice_clear_pxe_mode(hw); 753 754 status = ice_get_caps(hw); 755 if (status) 756 goto err_unroll_cqinit; 757 758 hw->port_info = (struct ice_port_info *) 759 ice_malloc(hw, sizeof(*hw->port_info)); 760 if (!hw->port_info) { 761 status = ICE_ERR_NO_MEMORY; 762 goto err_unroll_cqinit; 763 } 764 765 /* set the back pointer to HW */ 766 hw->port_info->hw = hw; 767 768 /* Initialize port_info struct with switch configuration data */ 769 status = ice_get_initial_sw_cfg(hw); 770 if (status) 771 goto err_unroll_alloc; 772 773 hw->evb_veb = true; 774 /* Query the allocated resources for Tx scheduler */ 775 status = ice_sched_query_res_alloc(hw); 776 if (status) { 777 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 778 goto err_unroll_alloc; 779 } 780 ice_sched_get_psm_clk_freq(hw); 781 782 /* Initialize port_info struct with scheduler data */ 783 status = ice_sched_init_port(hw->port_info); 784 if (status) 785 goto err_unroll_sched; 786 pcaps = (struct ice_aqc_get_phy_caps_data *) 787 ice_malloc(hw, sizeof(*pcaps)); 788 if (!pcaps) { 789 status = ICE_ERR_NO_MEMORY; 790 goto err_unroll_sched; 791 } 792 793 /* Initialize port_info struct with PHY capabilities */ 794 status = ice_aq_get_phy_caps(hw->port_info, false, 795 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); 796 ice_free(hw, pcaps); 797 if (status) 798 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", 799 status); 800 801 /* Initialize port_info struct with link information */ 802 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 803 if (status) 804 goto err_unroll_sched; 805 /* need a valid SW entry point to build a Tx tree */ 806 if (!hw->sw_entry_point_layer) { 807 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 808 status = ICE_ERR_CFG; 809 goto err_unroll_sched; 810 } 811 INIT_LIST_HEAD(&hw->agg_list); 812 /* Initialize max burst size */ 813 if (!hw->max_burst_size) 814 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 815 status = ice_init_fltr_mgmt_struct(hw); 816 if (status) 817 goto err_unroll_sched; 818 819 /* Get MAC information */ 820 /* A single port can report up to two (LAN and WoL) addresses */ 821 mac_buf = ice_calloc(hw, 2, 822 sizeof(struct ice_aqc_manage_mac_read_resp)); 823 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 824 825 if (!mac_buf) { 826 status = ICE_ERR_NO_MEMORY; 827 goto err_unroll_fltr_mgmt_struct; 828 } 829 830 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 831 ice_free(hw, mac_buf); 832 833 if (status) 834 goto err_unroll_fltr_mgmt_struct; 835 /* enable jumbo frame support at MAC level */ 836 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 837 if (status) 838 goto err_unroll_fltr_mgmt_struct; 839 /* Obtain counter base index which would be used by flow director */ 840 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 841 if (status) 842 goto err_unroll_fltr_mgmt_struct; 843 status = ice_init_hw_tbls(hw); 844 if (status) 845 goto err_unroll_fltr_mgmt_struct; 846 ice_init_lock(&hw->tnl_lock); 847 848 return ICE_SUCCESS; 849 850 err_unroll_fltr_mgmt_struct: 851 ice_cleanup_fltr_mgmt_struct(hw); 852 err_unroll_sched: 853 ice_sched_cleanup_all(hw); 854 err_unroll_alloc: 855 ice_free(hw, hw->port_info); 856 hw->port_info = NULL; 857 err_unroll_cqinit: 858 ice_destroy_all_ctrlq(hw); 859 return status; 860 } 861 862 /** 863 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 864 * @hw: pointer to the hardware structure 865 * 866 * This should be called only during nominal operation, not as a result of 867 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 868 * applicable initializations if it fails for any reason. 869 */ 870 void ice_deinit_hw(struct ice_hw *hw) 871 { 872 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 873 ice_cleanup_fltr_mgmt_struct(hw); 874 875 ice_sched_cleanup_all(hw); 876 ice_sched_clear_agg(hw); 877 ice_free_seg(hw); 878 ice_free_hw_tbls(hw); 879 ice_destroy_lock(&hw->tnl_lock); 880 881 if (hw->port_info) { 882 ice_free(hw, hw->port_info); 883 hw->port_info = NULL; 884 } 885 886 ice_destroy_all_ctrlq(hw); 887 888 /* Clear VSI contexts if not already cleared */ 889 ice_clear_all_vsi_ctx(hw); 890 } 891 892 /** 893 * ice_check_reset - Check to see if a global reset is complete 894 * @hw: pointer to the hardware structure 895 */ 896 enum ice_status ice_check_reset(struct ice_hw *hw) 897 { 898 u32 cnt, reg = 0, grst_timeout, uld_mask; 899 900 /* Poll for Device Active state in case a recent CORER, GLOBR, 901 * or EMPR has occurred. The grst delay value is in 100ms units. 902 * Add 1sec for outstanding AQ commands that can take a long time. 903 */ 904 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 905 GLGEN_RSTCTL_GRSTDEL_S) + 10; 906 907 for (cnt = 0; cnt < grst_timeout; cnt++) { 908 ice_msec_delay(100, true); 909 reg = rd32(hw, GLGEN_RSTAT); 910 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 911 break; 912 } 913 914 if (cnt == grst_timeout) { 915 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 916 return ICE_ERR_RESET_FAILED; 917 } 918 919 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 920 GLNVM_ULD_PCIER_DONE_1_M |\ 921 GLNVM_ULD_CORER_DONE_M |\ 922 GLNVM_ULD_GLOBR_DONE_M |\ 923 GLNVM_ULD_POR_DONE_M |\ 924 GLNVM_ULD_POR_DONE_1_M |\ 925 GLNVM_ULD_PCIER_DONE_2_M) 926 927 uld_mask = ICE_RESET_DONE_MASK; 928 929 /* Device is Active; check Global Reset processes are done */ 930 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 931 reg = rd32(hw, GLNVM_ULD) & uld_mask; 932 if (reg == uld_mask) { 933 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 934 break; 935 } 936 ice_msec_delay(10, true); 937 } 938 939 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 940 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 941 reg); 942 return ICE_ERR_RESET_FAILED; 943 } 944 945 return ICE_SUCCESS; 946 } 947 948 /** 949 * ice_pf_reset - Reset the PF 950 * @hw: pointer to the hardware structure 951 * 952 * If a global reset has been triggered, this function checks 953 * for its completion and then issues the PF reset 954 */ 955 static enum ice_status ice_pf_reset(struct ice_hw *hw) 956 { 957 u32 cnt, reg; 958 959 /* If at function entry a global reset was already in progress, i.e. 960 * state is not 'device active' or any of the reset done bits are not 961 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 962 * global reset is done. 963 */ 964 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 965 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 966 /* poll on global reset currently in progress until done */ 967 if (ice_check_reset(hw)) 968 return ICE_ERR_RESET_FAILED; 969 970 return ICE_SUCCESS; 971 } 972 973 /* Reset the PF */ 974 reg = rd32(hw, PFGEN_CTRL); 975 976 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 977 978 /* Wait for the PFR to complete. The wait time is the global config lock 979 * timeout plus the PFR timeout which will account for a possible reset 980 * that is occurring during a download package operation. 981 */ 982 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 983 ICE_PF_RESET_WAIT_COUNT; cnt++) { 984 reg = rd32(hw, PFGEN_CTRL); 985 if (!(reg & PFGEN_CTRL_PFSWR_M)) 986 break; 987 988 ice_msec_delay(1, true); 989 } 990 991 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 992 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 993 return ICE_ERR_RESET_FAILED; 994 } 995 996 return ICE_SUCCESS; 997 } 998 999 /** 1000 * ice_reset - Perform different types of reset 1001 * @hw: pointer to the hardware structure 1002 * @req: reset request 1003 * 1004 * This function triggers a reset as specified by the req parameter. 1005 * 1006 * Note: 1007 * If anything other than a PF reset is triggered, PXE mode is restored. 1008 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1009 * interface has been restored in the rebuild flow. 1010 */ 1011 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1012 { 1013 u32 val = 0; 1014 1015 switch (req) { 1016 case ICE_RESET_PFR: 1017 return ice_pf_reset(hw); 1018 case ICE_RESET_CORER: 1019 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1020 val = GLGEN_RTRIG_CORER_M; 1021 break; 1022 case ICE_RESET_GLOBR: 1023 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1024 val = GLGEN_RTRIG_GLOBR_M; 1025 break; 1026 default: 1027 return ICE_ERR_PARAM; 1028 } 1029 1030 val |= rd32(hw, GLGEN_RTRIG); 1031 wr32(hw, GLGEN_RTRIG, val); 1032 ice_flush(hw); 1033 1034 /* wait for the FW to be ready */ 1035 return ice_check_reset(hw); 1036 } 1037 1038 /** 1039 * ice_copy_rxq_ctx_to_hw 1040 * @hw: pointer to the hardware structure 1041 * @ice_rxq_ctx: pointer to the rxq context 1042 * @rxq_index: the index of the Rx queue 1043 * 1044 * Copies rxq context from dense structure to HW register space 1045 */ 1046 static enum ice_status 1047 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1048 { 1049 u8 i; 1050 1051 if (!ice_rxq_ctx) 1052 return ICE_ERR_BAD_PTR; 1053 1054 if (rxq_index > QRX_CTRL_MAX_INDEX) 1055 return ICE_ERR_PARAM; 1056 1057 /* Copy each dword separately to HW */ 1058 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1059 wr32(hw, QRX_CONTEXT(i, rxq_index), 1060 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1061 1062 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1063 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1064 } 1065 1066 return ICE_SUCCESS; 1067 } 1068 1069 /* LAN Rx Queue Context */ 1070 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1071 /* Field Width LSB */ 1072 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1073 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1074 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1075 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1076 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1077 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1078 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1079 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1080 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1081 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1082 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1083 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1084 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1085 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1086 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1087 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1088 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1089 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1090 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1091 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1092 { 0 } 1093 }; 1094 1095 /** 1096 * ice_write_rxq_ctx 1097 * @hw: pointer to the hardware structure 1098 * @rlan_ctx: pointer to the rxq context 1099 * @rxq_index: the index of the Rx queue 1100 * 1101 * Converts rxq context from sparse to dense structure and then writes 1102 * it to HW register space and enables the hardware to prefetch descriptors 1103 * instead of only fetching them on demand 1104 */ 1105 enum ice_status 1106 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1107 u32 rxq_index) 1108 { 1109 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1110 1111 if (!rlan_ctx) 1112 return ICE_ERR_BAD_PTR; 1113 1114 rlan_ctx->prefena = 1; 1115 1116 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1117 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1118 } 1119 1120 /** 1121 * ice_clear_rxq_ctx 1122 * @hw: pointer to the hardware structure 1123 * @rxq_index: the index of the Rx queue to clear 1124 * 1125 * Clears rxq context in HW register space 1126 */ 1127 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1128 { 1129 u8 i; 1130 1131 if (rxq_index > QRX_CTRL_MAX_INDEX) 1132 return ICE_ERR_PARAM; 1133 1134 /* Clear each dword register separately */ 1135 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1136 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1137 1138 return ICE_SUCCESS; 1139 } 1140 1141 /* LAN Tx Queue Context */ 1142 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1143 /* Field Width LSB */ 1144 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1145 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1146 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1147 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1148 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1149 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1150 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1151 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1152 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1153 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1154 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1155 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1156 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1157 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1158 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1159 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1160 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1161 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1162 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1163 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1164 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1165 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1166 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1167 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1168 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1169 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1170 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1171 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1172 { 0 } 1173 }; 1174 1175 /** 1176 * ice_copy_tx_cmpltnq_ctx_to_hw 1177 * @hw: pointer to the hardware structure 1178 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1179 * @tx_cmpltnq_index: the index of the completion queue 1180 * 1181 * Copies Tx completion queue context from dense structure to HW register space 1182 */ 1183 static enum ice_status 1184 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1185 u32 tx_cmpltnq_index) 1186 { 1187 u8 i; 1188 1189 if (!ice_tx_cmpltnq_ctx) 1190 return ICE_ERR_BAD_PTR; 1191 1192 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1193 return ICE_ERR_PARAM; 1194 1195 /* Copy each dword separately to HW */ 1196 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1197 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1198 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1199 1200 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1201 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1202 } 1203 1204 return ICE_SUCCESS; 1205 } 1206 1207 /* LAN Tx Completion Queue Context */ 1208 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1209 /* Field Width LSB */ 1210 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1211 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1212 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1213 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1214 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1215 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1216 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1217 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1218 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1219 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1220 { 0 } 1221 }; 1222 1223 /** 1224 * ice_write_tx_cmpltnq_ctx 1225 * @hw: pointer to the hardware structure 1226 * @tx_cmpltnq_ctx: pointer to the completion queue context 1227 * @tx_cmpltnq_index: the index of the completion queue 1228 * 1229 * Converts completion queue context from sparse to dense structure and then 1230 * writes it to HW register space 1231 */ 1232 enum ice_status 1233 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1234 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1235 u32 tx_cmpltnq_index) 1236 { 1237 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1238 1239 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1240 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1241 } 1242 1243 /** 1244 * ice_clear_tx_cmpltnq_ctx 1245 * @hw: pointer to the hardware structure 1246 * @tx_cmpltnq_index: the index of the completion queue to clear 1247 * 1248 * Clears Tx completion queue context in HW register space 1249 */ 1250 enum ice_status 1251 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1252 { 1253 u8 i; 1254 1255 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1256 return ICE_ERR_PARAM; 1257 1258 /* Clear each dword register separately */ 1259 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1260 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1261 1262 return ICE_SUCCESS; 1263 } 1264 1265 /** 1266 * ice_copy_tx_drbell_q_ctx_to_hw 1267 * @hw: pointer to the hardware structure 1268 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1269 * @tx_drbell_q_index: the index of the doorbell queue 1270 * 1271 * Copies doorbell queue context from dense structure to HW register space 1272 */ 1273 static enum ice_status 1274 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1275 u32 tx_drbell_q_index) 1276 { 1277 u8 i; 1278 1279 if (!ice_tx_drbell_q_ctx) 1280 return ICE_ERR_BAD_PTR; 1281 1282 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1283 return ICE_ERR_PARAM; 1284 1285 /* Copy each dword separately to HW */ 1286 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1287 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1288 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1289 1290 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1291 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1292 } 1293 1294 return ICE_SUCCESS; 1295 } 1296 1297 /* LAN Tx Doorbell Queue Context info */ 1298 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1299 /* Field Width LSB */ 1300 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1301 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1302 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1303 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1304 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1305 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1306 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1307 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1308 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1309 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1310 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1311 { 0 } 1312 }; 1313 1314 /** 1315 * ice_write_tx_drbell_q_ctx 1316 * @hw: pointer to the hardware structure 1317 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1318 * @tx_drbell_q_index: the index of the doorbell queue 1319 * 1320 * Converts doorbell queue context from sparse to dense structure and then 1321 * writes it to HW register space 1322 */ 1323 enum ice_status 1324 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1325 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1326 u32 tx_drbell_q_index) 1327 { 1328 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1329 1330 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 1331 ice_tx_drbell_q_ctx_info); 1332 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1333 } 1334 1335 /** 1336 * ice_clear_tx_drbell_q_ctx 1337 * @hw: pointer to the hardware structure 1338 * @tx_drbell_q_index: the index of the doorbell queue to clear 1339 * 1340 * Clears doorbell queue context in HW register space 1341 */ 1342 enum ice_status 1343 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1344 { 1345 u8 i; 1346 1347 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1348 return ICE_ERR_PARAM; 1349 1350 /* Clear each dword register separately */ 1351 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1352 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1353 1354 return ICE_SUCCESS; 1355 } 1356 1357 /* FW Admin Queue command wrappers */ 1358 1359 /** 1360 * ice_should_retry_sq_send_cmd 1361 * @opcode: AQ opcode 1362 * 1363 * Decide if we should retry the send command routine for the ATQ, depending 1364 * on the opcode. 1365 */ 1366 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1367 { 1368 switch (opcode) { 1369 case ice_aqc_opc_get_link_topo: 1370 case ice_aqc_opc_lldp_stop: 1371 case ice_aqc_opc_lldp_start: 1372 case ice_aqc_opc_lldp_filter_ctrl: 1373 return true; 1374 } 1375 1376 return false; 1377 } 1378 1379 /** 1380 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1381 * @hw: pointer to the HW struct 1382 * @cq: pointer to the specific Control queue 1383 * @desc: prefilled descriptor describing the command 1384 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1385 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1386 * @cd: pointer to command details structure 1387 * 1388 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1389 * Queue if the EBUSY AQ error is returned. 1390 */ 1391 static enum ice_status 1392 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1393 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1394 struct ice_sq_cd *cd) 1395 { 1396 struct ice_aq_desc desc_cpy; 1397 enum ice_status status; 1398 bool is_cmd_for_retry; 1399 u8 *buf_cpy = NULL; 1400 u8 idx = 0; 1401 u16 opcode; 1402 1403 opcode = LE16_TO_CPU(desc->opcode); 1404 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1405 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); 1406 1407 if (is_cmd_for_retry) { 1408 if (buf) { 1409 buf_cpy = (u8 *)ice_malloc(hw, buf_size); 1410 if (!buf_cpy) 1411 return ICE_ERR_NO_MEMORY; 1412 } 1413 1414 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), 1415 ICE_NONDMA_TO_NONDMA); 1416 } 1417 1418 do { 1419 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1420 1421 if (!is_cmd_for_retry || status == ICE_SUCCESS || 1422 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1423 break; 1424 1425 if (buf_cpy) 1426 ice_memcpy(buf, buf_cpy, buf_size, 1427 ICE_NONDMA_TO_NONDMA); 1428 1429 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), 1430 ICE_NONDMA_TO_NONDMA); 1431 1432 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); 1433 1434 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1435 1436 if (buf_cpy) 1437 ice_free(hw, buf_cpy); 1438 1439 return status; 1440 } 1441 1442 /** 1443 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1444 * @hw: pointer to the HW struct 1445 * @desc: descriptor describing the command 1446 * @buf: buffer to use for indirect commands (NULL for direct commands) 1447 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1448 * @cd: pointer to command details structure 1449 * 1450 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1451 */ 1452 enum ice_status 1453 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1454 u16 buf_size, struct ice_sq_cd *cd) 1455 { 1456 if (hw->aq_send_cmd_fn) { 1457 enum ice_status status = ICE_ERR_NOT_READY; 1458 u16 retval = ICE_AQ_RC_OK; 1459 1460 ice_acquire_lock(&hw->adminq.sq_lock); 1461 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc, 1462 buf, buf_size)) { 1463 retval = LE16_TO_CPU(desc->retval); 1464 /* strip off FW internal code */ 1465 if (retval) 1466 retval &= 0xff; 1467 if (retval == ICE_AQ_RC_OK) 1468 status = ICE_SUCCESS; 1469 else 1470 status = ICE_ERR_AQ_ERROR; 1471 } 1472 1473 hw->adminq.sq_last_status = (enum ice_aq_err)retval; 1474 ice_release_lock(&hw->adminq.sq_lock); 1475 1476 return status; 1477 } 1478 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1479 } 1480 1481 /** 1482 * ice_aq_get_fw_ver 1483 * @hw: pointer to the HW struct 1484 * @cd: pointer to command details structure or NULL 1485 * 1486 * Get the firmware version (0x0001) from the admin queue commands 1487 */ 1488 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1489 { 1490 struct ice_aqc_get_ver *resp; 1491 struct ice_aq_desc desc; 1492 enum ice_status status; 1493 1494 resp = &desc.params.get_ver; 1495 1496 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1497 1498 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1499 1500 if (!status) { 1501 hw->fw_branch = resp->fw_branch; 1502 hw->fw_maj_ver = resp->fw_major; 1503 hw->fw_min_ver = resp->fw_minor; 1504 hw->fw_patch = resp->fw_patch; 1505 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1506 hw->api_branch = resp->api_branch; 1507 hw->api_maj_ver = resp->api_major; 1508 hw->api_min_ver = resp->api_minor; 1509 hw->api_patch = resp->api_patch; 1510 } 1511 1512 return status; 1513 } 1514 1515 /** 1516 * ice_aq_send_driver_ver 1517 * @hw: pointer to the HW struct 1518 * @dv: driver's major, minor version 1519 * @cd: pointer to command details structure or NULL 1520 * 1521 * Send the driver version (0x0002) to the firmware 1522 */ 1523 enum ice_status 1524 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1525 struct ice_sq_cd *cd) 1526 { 1527 struct ice_aqc_driver_ver *cmd; 1528 struct ice_aq_desc desc; 1529 u16 len; 1530 1531 cmd = &desc.params.driver_ver; 1532 1533 if (!dv) 1534 return ICE_ERR_PARAM; 1535 1536 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1537 1538 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1539 cmd->major_ver = dv->major_ver; 1540 cmd->minor_ver = dv->minor_ver; 1541 cmd->build_ver = dv->build_ver; 1542 cmd->subbuild_ver = dv->subbuild_ver; 1543 1544 len = 0; 1545 while (len < sizeof(dv->driver_string) && 1546 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1547 len++; 1548 1549 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1550 } 1551 1552 /** 1553 * ice_aq_q_shutdown 1554 * @hw: pointer to the HW struct 1555 * @unloading: is the driver unloading itself 1556 * 1557 * Tell the Firmware that we're shutting down the AdminQ and whether 1558 * or not the driver is unloading as well (0x0003). 1559 */ 1560 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1561 { 1562 struct ice_aqc_q_shutdown *cmd; 1563 struct ice_aq_desc desc; 1564 1565 cmd = &desc.params.q_shutdown; 1566 1567 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1568 1569 if (unloading) 1570 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1571 1572 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1573 } 1574 1575 /** 1576 * ice_aq_req_res 1577 * @hw: pointer to the HW struct 1578 * @res: resource ID 1579 * @access: access type 1580 * @sdp_number: resource number 1581 * @timeout: the maximum time in ms that the driver may hold the resource 1582 * @cd: pointer to command details structure or NULL 1583 * 1584 * Requests common resource using the admin queue commands (0x0008). 1585 * When attempting to acquire the Global Config Lock, the driver can 1586 * learn of three states: 1587 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1588 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1589 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1590 * successfully downloaded the package; the driver does 1591 * not have to download the package and can continue 1592 * loading 1593 * 1594 * Note that if the caller is in an acquire lock, perform action, release lock 1595 * phase of operation, it is possible that the FW may detect a timeout and issue 1596 * a CORER. In this case, the driver will receive a CORER interrupt and will 1597 * have to determine its cause. The calling thread that is handling this flow 1598 * will likely get an error propagated back to it indicating the Download 1599 * Package, Update Package or the Release Resource AQ commands timed out. 1600 */ 1601 static enum ice_status 1602 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1603 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1604 struct ice_sq_cd *cd) 1605 { 1606 struct ice_aqc_req_res *cmd_resp; 1607 struct ice_aq_desc desc; 1608 enum ice_status status; 1609 1610 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1611 1612 cmd_resp = &desc.params.res_owner; 1613 1614 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1615 1616 cmd_resp->res_id = CPU_TO_LE16(res); 1617 cmd_resp->access_type = CPU_TO_LE16(access); 1618 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1619 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1620 *timeout = 0; 1621 1622 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1623 1624 /* The completion specifies the maximum time in ms that the driver 1625 * may hold the resource in the Timeout field. 1626 */ 1627 1628 /* Global config lock response utilizes an additional status field. 1629 * 1630 * If the Global config lock resource is held by some other driver, the 1631 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1632 * and the timeout field indicates the maximum time the current owner 1633 * of the resource has to free it. 1634 */ 1635 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1636 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1637 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1638 return ICE_SUCCESS; 1639 } else if (LE16_TO_CPU(cmd_resp->status) == 1640 ICE_AQ_RES_GLBL_IN_PROG) { 1641 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1642 return ICE_ERR_AQ_ERROR; 1643 } else if (LE16_TO_CPU(cmd_resp->status) == 1644 ICE_AQ_RES_GLBL_DONE) { 1645 return ICE_ERR_AQ_NO_WORK; 1646 } 1647 1648 /* invalid FW response, force a timeout immediately */ 1649 *timeout = 0; 1650 return ICE_ERR_AQ_ERROR; 1651 } 1652 1653 /* If the resource is held by some other driver, the command completes 1654 * with a busy return value and the timeout field indicates the maximum 1655 * time the current owner of the resource has to free it. 1656 */ 1657 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1658 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1659 1660 return status; 1661 } 1662 1663 /** 1664 * ice_aq_release_res 1665 * @hw: pointer to the HW struct 1666 * @res: resource ID 1667 * @sdp_number: resource number 1668 * @cd: pointer to command details structure or NULL 1669 * 1670 * release common resource using the admin queue commands (0x0009) 1671 */ 1672 static enum ice_status 1673 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1674 struct ice_sq_cd *cd) 1675 { 1676 struct ice_aqc_req_res *cmd; 1677 struct ice_aq_desc desc; 1678 1679 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1680 1681 cmd = &desc.params.res_owner; 1682 1683 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1684 1685 cmd->res_id = CPU_TO_LE16(res); 1686 cmd->res_number = CPU_TO_LE32(sdp_number); 1687 1688 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1689 } 1690 1691 /** 1692 * ice_acquire_res 1693 * @hw: pointer to the HW structure 1694 * @res: resource ID 1695 * @access: access type (read or write) 1696 * @timeout: timeout in milliseconds 1697 * 1698 * This function will attempt to acquire the ownership of a resource. 1699 */ 1700 enum ice_status 1701 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1702 enum ice_aq_res_access_type access, u32 timeout) 1703 { 1704 #define ICE_RES_POLLING_DELAY_MS 10 1705 u32 delay = ICE_RES_POLLING_DELAY_MS; 1706 u32 time_left = timeout; 1707 enum ice_status status; 1708 1709 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1710 1711 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1712 1713 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1714 * previously acquired the resource and performed any necessary updates; 1715 * in this case the caller does not obtain the resource and has no 1716 * further work to do. 1717 */ 1718 if (status == ICE_ERR_AQ_NO_WORK) 1719 goto ice_acquire_res_exit; 1720 1721 if (status) 1722 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1723 1724 /* If necessary, poll until the current lock owner timeouts */ 1725 timeout = time_left; 1726 while (status && timeout && time_left) { 1727 ice_msec_delay(delay, true); 1728 timeout = (timeout > delay) ? timeout - delay : 0; 1729 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1730 1731 if (status == ICE_ERR_AQ_NO_WORK) 1732 /* lock free, but no work to do */ 1733 break; 1734 1735 if (!status) 1736 /* lock acquired */ 1737 break; 1738 } 1739 if (status && status != ICE_ERR_AQ_NO_WORK) 1740 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1741 1742 ice_acquire_res_exit: 1743 if (status == ICE_ERR_AQ_NO_WORK) { 1744 if (access == ICE_RES_WRITE) 1745 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1746 else 1747 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1748 } 1749 return status; 1750 } 1751 1752 /** 1753 * ice_release_res 1754 * @hw: pointer to the HW structure 1755 * @res: resource ID 1756 * 1757 * This function will release a resource using the proper Admin Command. 1758 */ 1759 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1760 { 1761 enum ice_status status; 1762 u32 total_delay = 0; 1763 1764 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1765 1766 status = ice_aq_release_res(hw, res, 0, NULL); 1767 1768 /* there are some rare cases when trying to release the resource 1769 * results in an admin queue timeout, so handle them correctly 1770 */ 1771 while ((status == ICE_ERR_AQ_TIMEOUT) && 1772 (total_delay < hw->adminq.sq_cmd_timeout)) { 1773 ice_msec_delay(1, true); 1774 status = ice_aq_release_res(hw, res, 0, NULL); 1775 total_delay++; 1776 } 1777 } 1778 1779 /** 1780 * ice_aq_alloc_free_res - command to allocate/free resources 1781 * @hw: pointer to the HW struct 1782 * @num_entries: number of resource entries in buffer 1783 * @buf: Indirect buffer to hold data parameters and response 1784 * @buf_size: size of buffer for indirect commands 1785 * @opc: pass in the command opcode 1786 * @cd: pointer to command details structure or NULL 1787 * 1788 * Helper function to allocate/free resources using the admin queue commands 1789 */ 1790 enum ice_status 1791 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1792 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1793 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1794 { 1795 struct ice_aqc_alloc_free_res_cmd *cmd; 1796 struct ice_aq_desc desc; 1797 1798 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1799 1800 cmd = &desc.params.sw_res_ctrl; 1801 1802 if (!buf) 1803 return ICE_ERR_PARAM; 1804 1805 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) 1806 return ICE_ERR_PARAM; 1807 1808 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1809 1810 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1811 1812 cmd->num_entries = CPU_TO_LE16(num_entries); 1813 1814 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1815 } 1816 1817 /** 1818 * ice_alloc_hw_res - allocate resource 1819 * @hw: pointer to the HW struct 1820 * @type: type of resource 1821 * @num: number of resources to allocate 1822 * @btm: allocate from bottom 1823 * @res: pointer to array that will receive the resources 1824 */ 1825 enum ice_status 1826 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1827 { 1828 struct ice_aqc_alloc_free_res_elem *buf; 1829 enum ice_status status; 1830 u16 buf_len; 1831 1832 buf_len = ice_struct_size(buf, elem, num); 1833 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1834 if (!buf) 1835 return ICE_ERR_NO_MEMORY; 1836 1837 /* Prepare buffer to allocate resource. */ 1838 buf->num_elems = CPU_TO_LE16(num); 1839 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1840 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1841 if (btm) 1842 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1843 1844 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1845 ice_aqc_opc_alloc_res, NULL); 1846 if (status) 1847 goto ice_alloc_res_exit; 1848 1849 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num, 1850 ICE_NONDMA_TO_NONDMA); 1851 1852 ice_alloc_res_exit: 1853 ice_free(hw, buf); 1854 return status; 1855 } 1856 1857 /** 1858 * ice_free_hw_res - free allocated HW resource 1859 * @hw: pointer to the HW struct 1860 * @type: type of resource to free 1861 * @num: number of resources 1862 * @res: pointer to array that contains the resources to free 1863 */ 1864 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1865 { 1866 struct ice_aqc_alloc_free_res_elem *buf; 1867 enum ice_status status; 1868 u16 buf_len; 1869 1870 buf_len = ice_struct_size(buf, elem, num); 1871 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1872 if (!buf) 1873 return ICE_ERR_NO_MEMORY; 1874 1875 /* Prepare buffer to free resource. */ 1876 buf->num_elems = CPU_TO_LE16(num); 1877 buf->res_type = CPU_TO_LE16(type); 1878 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num, 1879 ICE_NONDMA_TO_NONDMA); 1880 1881 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1882 ice_aqc_opc_free_res, NULL); 1883 if (status) 1884 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1885 1886 ice_free(hw, buf); 1887 return status; 1888 } 1889 1890 /** 1891 * ice_get_num_per_func - determine number of resources per PF 1892 * @hw: pointer to the HW structure 1893 * @max: value to be evenly split between each PF 1894 * 1895 * Determine the number of valid functions by going through the bitmap returned 1896 * from parsing capabilities and use this to calculate the number of resources 1897 * per PF based on the max value passed in. 1898 */ 1899 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1900 { 1901 u8 funcs; 1902 1903 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1904 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 1905 ICE_CAPS_VALID_FUNCS_M); 1906 1907 if (!funcs) 1908 return 0; 1909 1910 return max / funcs; 1911 } 1912 1913 /** 1914 * ice_parse_common_caps - parse common device/function capabilities 1915 * @hw: pointer to the HW struct 1916 * @caps: pointer to common capabilities structure 1917 * @elem: the capability element to parse 1918 * @prefix: message prefix for tracing capabilities 1919 * 1920 * Given a capability element, extract relevant details into the common 1921 * capability structure. 1922 * 1923 * Returns: true if the capability matches one of the common capability ids, 1924 * false otherwise. 1925 */ 1926 static bool 1927 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1928 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1929 { 1930 u32 logical_id = LE32_TO_CPU(elem->logical_id); 1931 u32 phys_id = LE32_TO_CPU(elem->phys_id); 1932 u32 number = LE32_TO_CPU(elem->number); 1933 u16 cap = LE16_TO_CPU(elem->cap); 1934 bool found = true; 1935 1936 switch (cap) { 1937 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1938 caps->valid_functions = number; 1939 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1940 caps->valid_functions); 1941 break; 1942 case ICE_AQC_CAPS_DCB: 1943 caps->dcb = (number == 1); 1944 caps->active_tc_bitmap = logical_id; 1945 caps->maxtc = phys_id; 1946 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 1947 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1948 caps->active_tc_bitmap); 1949 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1950 break; 1951 case ICE_AQC_CAPS_RSS: 1952 caps->rss_table_size = number; 1953 caps->rss_table_entry_width = logical_id; 1954 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 1955 caps->rss_table_size); 1956 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 1957 caps->rss_table_entry_width); 1958 break; 1959 case ICE_AQC_CAPS_RXQS: 1960 caps->num_rxq = number; 1961 caps->rxq_first_id = phys_id; 1962 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1963 caps->num_rxq); 1964 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 1965 caps->rxq_first_id); 1966 break; 1967 case ICE_AQC_CAPS_TXQS: 1968 caps->num_txq = number; 1969 caps->txq_first_id = phys_id; 1970 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1971 caps->num_txq); 1972 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 1973 caps->txq_first_id); 1974 break; 1975 case ICE_AQC_CAPS_MSIX: 1976 caps->num_msix_vectors = number; 1977 caps->msix_vector_first_id = phys_id; 1978 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 1979 caps->num_msix_vectors); 1980 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 1981 caps->msix_vector_first_id); 1982 break; 1983 case ICE_AQC_CAPS_NVM_MGMT: 1984 caps->sec_rev_disabled = 1985 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? 1986 true : false; 1987 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, 1988 caps->sec_rev_disabled); 1989 caps->update_disabled = 1990 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? 1991 true : false; 1992 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, 1993 caps->update_disabled); 1994 caps->nvm_unified_update = 1995 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1996 true : false; 1997 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1998 caps->nvm_unified_update); 1999 break; 2000 case ICE_AQC_CAPS_MAX_MTU: 2001 caps->max_mtu = number; 2002 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2003 prefix, caps->max_mtu); 2004 break; 2005 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0: 2006 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1: 2007 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2: 2008 case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3: 2009 { 2010 u8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0; 2011 2012 caps->ext_topo_dev_img_ver_high[index] = number; 2013 caps->ext_topo_dev_img_ver_low[index] = logical_id; 2014 caps->ext_topo_dev_img_part_num[index] = 2015 (phys_id & ICE_EXT_TOPO_DEV_IMG_PART_NUM_M) >> 2016 ICE_EXT_TOPO_DEV_IMG_PART_NUM_S; 2017 caps->ext_topo_dev_img_load_en[index] = 2018 (phys_id & ICE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0; 2019 caps->ext_topo_dev_img_prog_en[index] = 2020 (phys_id & ICE_EXT_TOPO_DEV_IMG_PROG_EN) != 0; 2021 ice_debug(hw, ICE_DBG_INIT, 2022 "%s: ext_topo_dev_img_ver_high[%d] = %d\n", 2023 prefix, index, 2024 caps->ext_topo_dev_img_ver_high[index]); 2025 ice_debug(hw, ICE_DBG_INIT, 2026 "%s: ext_topo_dev_img_ver_low[%d] = %d\n", 2027 prefix, index, 2028 caps->ext_topo_dev_img_ver_low[index]); 2029 ice_debug(hw, ICE_DBG_INIT, 2030 "%s: ext_topo_dev_img_part_num[%d] = %d\n", 2031 prefix, index, 2032 caps->ext_topo_dev_img_part_num[index]); 2033 ice_debug(hw, ICE_DBG_INIT, 2034 "%s: ext_topo_dev_img_load_en[%d] = %d\n", 2035 prefix, index, 2036 caps->ext_topo_dev_img_load_en[index]); 2037 ice_debug(hw, ICE_DBG_INIT, 2038 "%s: ext_topo_dev_img_prog_en[%d] = %d\n", 2039 prefix, index, 2040 caps->ext_topo_dev_img_prog_en[index]); 2041 break; 2042 } 2043 default: 2044 /* Not one of the recognized common capabilities */ 2045 found = false; 2046 } 2047 2048 return found; 2049 } 2050 2051 /** 2052 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2053 * @hw: pointer to the HW structure 2054 * @caps: pointer to capabilities structure to fix 2055 * 2056 * Re-calculate the capabilities that are dependent on the number of physical 2057 * ports; i.e. some features are not supported or function differently on 2058 * devices with more than 4 ports. 2059 */ 2060 static void 2061 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2062 { 2063 /* This assumes device capabilities are always scanned before function 2064 * capabilities during the initialization flow. 2065 */ 2066 if (hw->dev_caps.num_funcs > 4) { 2067 /* Max 4 TCs per port */ 2068 caps->maxtc = 4; 2069 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2070 caps->maxtc); 2071 } 2072 } 2073 2074 /** 2075 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2076 * @hw: pointer to the HW struct 2077 * @func_p: pointer to function capabilities structure 2078 * @cap: pointer to the capability element to parse 2079 * 2080 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2081 */ 2082 static void 2083 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2084 struct ice_aqc_list_caps_elem *cap) 2085 { 2086 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2087 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2088 LE32_TO_CPU(cap->number)); 2089 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2090 func_p->guar_num_vsi); 2091 } 2092 2093 /** 2094 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2095 * @hw: pointer to the HW struct 2096 * @func_p: pointer to function capabilities structure 2097 * 2098 * Extract function capabilities for ICE_AQC_CAPS_FD. 2099 */ 2100 static void 2101 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2102 { 2103 u32 reg_val, val; 2104 2105 if (hw->dcf_enabled) 2106 return; 2107 reg_val = rd32(hw, GLQF_FD_SIZE); 2108 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2109 GLQF_FD_SIZE_FD_GSIZE_S; 2110 func_p->fd_fltr_guar = 2111 ice_get_num_per_func(hw, val); 2112 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2113 GLQF_FD_SIZE_FD_BSIZE_S; 2114 func_p->fd_fltr_best_effort = val; 2115 2116 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2117 func_p->fd_fltr_guar); 2118 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2119 func_p->fd_fltr_best_effort); 2120 } 2121 2122 /** 2123 * ice_parse_func_caps - Parse function capabilities 2124 * @hw: pointer to the HW struct 2125 * @func_p: pointer to function capabilities structure 2126 * @buf: buffer containing the function capability records 2127 * @cap_count: the number of capabilities 2128 * 2129 * Helper function to parse function (0x000A) capabilities list. For 2130 * capabilities shared between device and function, this relies on 2131 * ice_parse_common_caps. 2132 * 2133 * Loop through the list of provided capabilities and extract the relevant 2134 * data into the function capabilities structured. 2135 */ 2136 static void 2137 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2138 void *buf, u32 cap_count) 2139 { 2140 struct ice_aqc_list_caps_elem *cap_resp; 2141 u32 i; 2142 2143 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2144 2145 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 2146 2147 for (i = 0; i < cap_count; i++) { 2148 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2149 bool found; 2150 2151 found = ice_parse_common_caps(hw, &func_p->common_cap, 2152 &cap_resp[i], "func caps"); 2153 2154 switch (cap) { 2155 case ICE_AQC_CAPS_VSI: 2156 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2157 break; 2158 case ICE_AQC_CAPS_FD: 2159 ice_parse_fdir_func_caps(hw, func_p); 2160 break; 2161 default: 2162 /* Don't list common capabilities as unknown */ 2163 if (!found) 2164 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2165 i, cap); 2166 break; 2167 } 2168 } 2169 2170 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2171 } 2172 2173 /** 2174 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2175 * @hw: pointer to the HW struct 2176 * @dev_p: pointer to device capabilities structure 2177 * @cap: capability element to parse 2178 * 2179 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2180 */ 2181 static void 2182 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2183 struct ice_aqc_list_caps_elem *cap) 2184 { 2185 u32 number = LE32_TO_CPU(cap->number); 2186 2187 dev_p->num_funcs = ice_hweight32(number); 2188 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2189 dev_p->num_funcs); 2190 } 2191 2192 /** 2193 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2194 * @hw: pointer to the HW struct 2195 * @dev_p: pointer to device capabilities structure 2196 * @cap: capability element to parse 2197 * 2198 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2199 */ 2200 static void 2201 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2202 struct ice_aqc_list_caps_elem *cap) 2203 { 2204 u32 number = LE32_TO_CPU(cap->number); 2205 2206 dev_p->num_vsi_allocd_to_host = number; 2207 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2208 dev_p->num_vsi_allocd_to_host); 2209 } 2210 2211 /** 2212 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2213 * @hw: pointer to the HW struct 2214 * @dev_p: pointer to device capabilities structure 2215 * @cap: capability element to parse 2216 * 2217 * Parse ICE_AQC_CAPS_FD for device capabilities. 2218 */ 2219 static void 2220 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2221 struct ice_aqc_list_caps_elem *cap) 2222 { 2223 u32 number = LE32_TO_CPU(cap->number); 2224 2225 dev_p->num_flow_director_fltr = number; 2226 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2227 dev_p->num_flow_director_fltr); 2228 } 2229 2230 /** 2231 * ice_parse_dev_caps - Parse device capabilities 2232 * @hw: pointer to the HW struct 2233 * @dev_p: pointer to device capabilities structure 2234 * @buf: buffer containing the device capability records 2235 * @cap_count: the number of capabilities 2236 * 2237 * Helper device to parse device (0x000B) capabilities list. For 2238 * capabilities shared between device and function, this relies on 2239 * ice_parse_common_caps. 2240 * 2241 * Loop through the list of provided capabilities and extract the relevant 2242 * data into the device capabilities structured. 2243 */ 2244 static void 2245 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2246 void *buf, u32 cap_count) 2247 { 2248 struct ice_aqc_list_caps_elem *cap_resp; 2249 u32 i; 2250 2251 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2252 2253 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 2254 2255 for (i = 0; i < cap_count; i++) { 2256 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2257 bool found; 2258 2259 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2260 &cap_resp[i], "dev caps"); 2261 2262 switch (cap) { 2263 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2264 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2265 break; 2266 case ICE_AQC_CAPS_VSI: 2267 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2268 break; 2269 case ICE_AQC_CAPS_FD: 2270 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2271 break; 2272 default: 2273 /* Don't list common capabilities as unknown */ 2274 if (!found) 2275 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2276 i, cap); 2277 break; 2278 } 2279 } 2280 2281 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2282 } 2283 2284 /** 2285 * ice_aq_list_caps - query function/device capabilities 2286 * @hw: pointer to the HW struct 2287 * @buf: a buffer to hold the capabilities 2288 * @buf_size: size of the buffer 2289 * @cap_count: if not NULL, set to the number of capabilities reported 2290 * @opc: capabilities type to discover, device or function 2291 * @cd: pointer to command details structure or NULL 2292 * 2293 * Get the function (0x000A) or device (0x000B) capabilities description from 2294 * firmware and store it in the buffer. 2295 * 2296 * If the cap_count pointer is not NULL, then it is set to the number of 2297 * capabilities firmware will report. Note that if the buffer size is too 2298 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2299 * cap_count will still be updated in this case. It is recommended that the 2300 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2301 * firmware could return) to avoid this. 2302 */ 2303 static enum ice_status 2304 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2305 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2306 { 2307 struct ice_aqc_list_caps *cmd; 2308 struct ice_aq_desc desc; 2309 enum ice_status status; 2310 2311 cmd = &desc.params.get_cap; 2312 2313 if (opc != ice_aqc_opc_list_func_caps && 2314 opc != ice_aqc_opc_list_dev_caps) 2315 return ICE_ERR_PARAM; 2316 2317 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2318 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2319 2320 if (cap_count) 2321 *cap_count = LE32_TO_CPU(cmd->count); 2322 2323 return status; 2324 } 2325 2326 /** 2327 * ice_discover_dev_caps - Read and extract device capabilities 2328 * @hw: pointer to the hardware structure 2329 * @dev_caps: pointer to device capabilities structure 2330 * 2331 * Read the device capabilities and extract them into the dev_caps structure 2332 * for later use. 2333 */ 2334 static enum ice_status 2335 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2336 { 2337 enum ice_status status; 2338 u32 cap_count = 0; 2339 void *cbuf; 2340 2341 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2342 if (!cbuf) 2343 return ICE_ERR_NO_MEMORY; 2344 2345 /* Although the driver doesn't know the number of capabilities the 2346 * device will return, we can simply send a 4KB buffer, the maximum 2347 * possible size that firmware can return. 2348 */ 2349 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2350 2351 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2352 ice_aqc_opc_list_dev_caps, NULL); 2353 if (!status) 2354 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2355 ice_free(hw, cbuf); 2356 2357 return status; 2358 } 2359 2360 /** 2361 * ice_discover_func_caps - Read and extract function capabilities 2362 * @hw: pointer to the hardware structure 2363 * @func_caps: pointer to function capabilities structure 2364 * 2365 * Read the function capabilities and extract them into the func_caps structure 2366 * for later use. 2367 */ 2368 static enum ice_status 2369 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2370 { 2371 enum ice_status status; 2372 u32 cap_count = 0; 2373 void *cbuf; 2374 2375 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2376 if (!cbuf) 2377 return ICE_ERR_NO_MEMORY; 2378 2379 /* Although the driver doesn't know the number of capabilities the 2380 * device will return, we can simply send a 4KB buffer, the maximum 2381 * possible size that firmware can return. 2382 */ 2383 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2384 2385 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2386 ice_aqc_opc_list_func_caps, NULL); 2387 if (!status) 2388 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2389 ice_free(hw, cbuf); 2390 2391 return status; 2392 } 2393 2394 /** 2395 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2396 * @hw: pointer to the hardware structure 2397 */ 2398 void ice_set_safe_mode_caps(struct ice_hw *hw) 2399 { 2400 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2401 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2402 struct ice_hw_common_caps cached_caps; 2403 u32 num_funcs; 2404 2405 /* cache some func_caps values that should be restored after memset */ 2406 cached_caps = func_caps->common_cap; 2407 2408 /* unset func capabilities */ 2409 memset(func_caps, 0, sizeof(*func_caps)); 2410 2411 #define ICE_RESTORE_FUNC_CAP(name) \ 2412 func_caps->common_cap.name = cached_caps.name 2413 2414 /* restore cached values */ 2415 ICE_RESTORE_FUNC_CAP(valid_functions); 2416 ICE_RESTORE_FUNC_CAP(txq_first_id); 2417 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2418 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2419 ICE_RESTORE_FUNC_CAP(max_mtu); 2420 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2421 2422 /* one Tx and one Rx queue in safe mode */ 2423 func_caps->common_cap.num_rxq = 1; 2424 func_caps->common_cap.num_txq = 1; 2425 2426 /* two MSIX vectors, one for traffic and one for misc causes */ 2427 func_caps->common_cap.num_msix_vectors = 2; 2428 func_caps->guar_num_vsi = 1; 2429 2430 /* cache some dev_caps values that should be restored after memset */ 2431 cached_caps = dev_caps->common_cap; 2432 num_funcs = dev_caps->num_funcs; 2433 2434 /* unset dev capabilities */ 2435 memset(dev_caps, 0, sizeof(*dev_caps)); 2436 2437 #define ICE_RESTORE_DEV_CAP(name) \ 2438 dev_caps->common_cap.name = cached_caps.name 2439 2440 /* restore cached values */ 2441 ICE_RESTORE_DEV_CAP(valid_functions); 2442 ICE_RESTORE_DEV_CAP(txq_first_id); 2443 ICE_RESTORE_DEV_CAP(rxq_first_id); 2444 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2445 ICE_RESTORE_DEV_CAP(max_mtu); 2446 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2447 dev_caps->num_funcs = num_funcs; 2448 2449 /* one Tx and one Rx queue per function in safe mode */ 2450 dev_caps->common_cap.num_rxq = num_funcs; 2451 dev_caps->common_cap.num_txq = num_funcs; 2452 2453 /* two MSIX vectors per function */ 2454 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2455 } 2456 2457 /** 2458 * ice_get_caps - get info about the HW 2459 * @hw: pointer to the hardware structure 2460 */ 2461 enum ice_status ice_get_caps(struct ice_hw *hw) 2462 { 2463 enum ice_status status; 2464 2465 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2466 if (status) 2467 return status; 2468 2469 return ice_discover_func_caps(hw, &hw->func_caps); 2470 } 2471 2472 /** 2473 * ice_aq_manage_mac_write - manage MAC address write command 2474 * @hw: pointer to the HW struct 2475 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2476 * @flags: flags to control write behavior 2477 * @cd: pointer to command details structure or NULL 2478 * 2479 * This function is used to write MAC address to the NVM (0x0108). 2480 */ 2481 enum ice_status 2482 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2483 struct ice_sq_cd *cd) 2484 { 2485 struct ice_aqc_manage_mac_write *cmd; 2486 struct ice_aq_desc desc; 2487 2488 cmd = &desc.params.mac_write; 2489 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2490 2491 cmd->flags = flags; 2492 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 2493 2494 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2495 } 2496 2497 /** 2498 * ice_aq_clear_pxe_mode 2499 * @hw: pointer to the HW struct 2500 * 2501 * Tell the firmware that the driver is taking over from PXE (0x0110). 2502 */ 2503 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2504 { 2505 struct ice_aq_desc desc; 2506 2507 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2508 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2509 2510 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2511 } 2512 2513 /** 2514 * ice_clear_pxe_mode - clear pxe operations mode 2515 * @hw: pointer to the HW struct 2516 * 2517 * Make sure all PXE mode settings are cleared, including things 2518 * like descriptor fetch/write-back mode. 2519 */ 2520 void ice_clear_pxe_mode(struct ice_hw *hw) 2521 { 2522 if (ice_check_sq_alive(hw, &hw->adminq)) 2523 ice_aq_clear_pxe_mode(hw); 2524 } 2525 2526 /** 2527 * ice_aq_set_port_params - set physical port parameters. 2528 * @pi: pointer to the port info struct 2529 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 2530 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 2531 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 2532 * @double_vlan: if set double VLAN is enabled 2533 * @cd: pointer to command details structure or NULL 2534 * 2535 * Set Physical port parameters (0x0203) 2536 */ 2537 enum ice_status 2538 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 2539 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 2540 struct ice_sq_cd *cd) 2541 2542 { 2543 struct ice_aqc_set_port_params *cmd; 2544 struct ice_hw *hw = pi->hw; 2545 struct ice_aq_desc desc; 2546 u16 cmd_flags = 0; 2547 2548 cmd = &desc.params.set_port_params; 2549 2550 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2551 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 2552 if (save_bad_pac) 2553 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; 2554 if (pad_short_pac) 2555 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; 2556 if (double_vlan) 2557 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2558 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 2559 2560 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2561 } 2562 2563 /** 2564 * ice_get_link_speed_based_on_phy_type - returns link speed 2565 * @phy_type_low: lower part of phy_type 2566 * @phy_type_high: higher part of phy_type 2567 * 2568 * This helper function will convert an entry in PHY type structure 2569 * [phy_type_low, phy_type_high] to its corresponding link speed. 2570 * Note: In the structure of [phy_type_low, phy_type_high], there should 2571 * be one bit set, as this function will convert one PHY type to its 2572 * speed. 2573 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2574 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2575 */ 2576 static u16 2577 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2578 { 2579 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2580 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2581 2582 switch (phy_type_low) { 2583 case ICE_PHY_TYPE_LOW_100BASE_TX: 2584 case ICE_PHY_TYPE_LOW_100M_SGMII: 2585 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2586 break; 2587 case ICE_PHY_TYPE_LOW_1000BASE_T: 2588 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2589 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2590 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2591 case ICE_PHY_TYPE_LOW_1G_SGMII: 2592 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2593 break; 2594 case ICE_PHY_TYPE_LOW_2500BASE_T: 2595 case ICE_PHY_TYPE_LOW_2500BASE_X: 2596 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2597 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2598 break; 2599 case ICE_PHY_TYPE_LOW_5GBASE_T: 2600 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2601 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2602 break; 2603 case ICE_PHY_TYPE_LOW_10GBASE_T: 2604 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2605 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2606 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2607 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2608 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2609 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2610 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2611 break; 2612 case ICE_PHY_TYPE_LOW_25GBASE_T: 2613 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2614 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2615 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2616 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2617 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2618 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2619 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2620 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2621 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2622 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2623 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2624 break; 2625 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2626 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2627 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2628 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2629 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2630 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2631 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2632 break; 2633 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2634 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2635 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2636 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2637 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2638 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2639 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2640 case ICE_PHY_TYPE_LOW_50G_AUI2: 2641 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2642 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2643 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2644 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2645 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2646 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2647 case ICE_PHY_TYPE_LOW_50G_AUI1: 2648 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2649 break; 2650 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2651 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2652 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2653 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2654 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2655 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2656 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2657 case ICE_PHY_TYPE_LOW_100G_AUI4: 2658 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2659 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2660 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2661 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2662 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2663 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2664 break; 2665 default: 2666 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2667 break; 2668 } 2669 2670 switch (phy_type_high) { 2671 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2672 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2673 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2674 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2675 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2676 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2677 break; 2678 default: 2679 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2680 break; 2681 } 2682 2683 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2684 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2685 return ICE_AQ_LINK_SPEED_UNKNOWN; 2686 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2687 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2688 return ICE_AQ_LINK_SPEED_UNKNOWN; 2689 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2690 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2691 return speed_phy_type_low; 2692 else 2693 return speed_phy_type_high; 2694 } 2695 2696 /** 2697 * ice_update_phy_type 2698 * @phy_type_low: pointer to the lower part of phy_type 2699 * @phy_type_high: pointer to the higher part of phy_type 2700 * @link_speeds_bitmap: targeted link speeds bitmap 2701 * 2702 * Note: For the link_speeds_bitmap structure, you can check it at 2703 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2704 * link_speeds_bitmap include multiple speeds. 2705 * 2706 * Each entry in this [phy_type_low, phy_type_high] structure will 2707 * present a certain link speed. This helper function will turn on bits 2708 * in [phy_type_low, phy_type_high] structure based on the value of 2709 * link_speeds_bitmap input parameter. 2710 */ 2711 void 2712 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2713 u16 link_speeds_bitmap) 2714 { 2715 u64 pt_high; 2716 u64 pt_low; 2717 int index; 2718 u16 speed; 2719 2720 /* We first check with low part of phy_type */ 2721 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2722 pt_low = BIT_ULL(index); 2723 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2724 2725 if (link_speeds_bitmap & speed) 2726 *phy_type_low |= BIT_ULL(index); 2727 } 2728 2729 /* We then check with high part of phy_type */ 2730 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2731 pt_high = BIT_ULL(index); 2732 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2733 2734 if (link_speeds_bitmap & speed) 2735 *phy_type_high |= BIT_ULL(index); 2736 } 2737 } 2738 2739 /** 2740 * ice_aq_set_phy_cfg 2741 * @hw: pointer to the HW struct 2742 * @pi: port info structure of the interested logical port 2743 * @cfg: structure with PHY configuration data to be set 2744 * @cd: pointer to command details structure or NULL 2745 * 2746 * Set the various PHY configuration parameters supported on the Port. 2747 * One or more of the Set PHY config parameters may be ignored in an MFP 2748 * mode as the PF may not have the privilege to set some of the PHY Config 2749 * parameters. This status will be indicated by the command response (0x0601). 2750 */ 2751 enum ice_status 2752 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2753 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2754 { 2755 struct ice_aq_desc desc; 2756 enum ice_status status; 2757 2758 if (!cfg) 2759 return ICE_ERR_PARAM; 2760 2761 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2762 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2763 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2764 cfg->caps); 2765 2766 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2767 } 2768 2769 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2770 desc.params.set_phy.lport_num = pi->lport; 2771 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2772 2773 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2774 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2775 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 2776 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2777 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 2778 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2779 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2780 cfg->low_power_ctrl_an); 2781 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2782 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2783 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2784 cfg->link_fec_opt); 2785 2786 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2787 2788 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2789 status = ICE_SUCCESS; 2790 2791 if (!status) 2792 pi->phy.curr_user_phy_cfg = *cfg; 2793 2794 return status; 2795 } 2796 2797 /** 2798 * ice_update_link_info - update status of the HW network link 2799 * @pi: port info structure of the interested logical port 2800 */ 2801 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2802 { 2803 struct ice_link_status *li; 2804 enum ice_status status; 2805 2806 if (!pi) 2807 return ICE_ERR_PARAM; 2808 2809 li = &pi->phy.link_info; 2810 2811 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2812 if (status) 2813 return status; 2814 2815 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2816 struct ice_aqc_get_phy_caps_data *pcaps; 2817 struct ice_hw *hw; 2818 2819 hw = pi->hw; 2820 pcaps = (struct ice_aqc_get_phy_caps_data *) 2821 ice_malloc(hw, sizeof(*pcaps)); 2822 if (!pcaps) 2823 return ICE_ERR_NO_MEMORY; 2824 2825 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2826 pcaps, NULL); 2827 2828 if (status == ICE_SUCCESS) 2829 ice_memcpy(li->module_type, &pcaps->module_type, 2830 sizeof(li->module_type), 2831 ICE_NONDMA_TO_NONDMA); 2832 2833 ice_free(hw, pcaps); 2834 } 2835 2836 return status; 2837 } 2838 2839 /** 2840 * ice_cache_phy_user_req 2841 * @pi: port information structure 2842 * @cache_data: PHY logging data 2843 * @cache_mode: PHY logging mode 2844 * 2845 * Log the user request on (FC, FEC, SPEED) for later user. 2846 */ 2847 static void 2848 ice_cache_phy_user_req(struct ice_port_info *pi, 2849 struct ice_phy_cache_mode_data cache_data, 2850 enum ice_phy_cache_mode cache_mode) 2851 { 2852 if (!pi) 2853 return; 2854 2855 switch (cache_mode) { 2856 case ICE_FC_MODE: 2857 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2858 break; 2859 case ICE_SPEED_MODE: 2860 pi->phy.curr_user_speed_req = 2861 cache_data.data.curr_user_speed_req; 2862 break; 2863 case ICE_FEC_MODE: 2864 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2865 break; 2866 default: 2867 break; 2868 } 2869 } 2870 2871 /** 2872 * ice_caps_to_fc_mode 2873 * @caps: PHY capabilities 2874 * 2875 * Convert PHY FC capabilities to ice FC mode 2876 */ 2877 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2878 { 2879 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2880 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2881 return ICE_FC_FULL; 2882 2883 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2884 return ICE_FC_TX_PAUSE; 2885 2886 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2887 return ICE_FC_RX_PAUSE; 2888 2889 return ICE_FC_NONE; 2890 } 2891 2892 /** 2893 * ice_caps_to_fec_mode 2894 * @caps: PHY capabilities 2895 * @fec_options: Link FEC options 2896 * 2897 * Convert PHY FEC capabilities to ice FEC mode 2898 */ 2899 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2900 { 2901 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2902 return ICE_FEC_AUTO; 2903 2904 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2905 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2906 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2907 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2908 return ICE_FEC_BASER; 2909 2910 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2911 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2912 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2913 return ICE_FEC_RS; 2914 2915 return ICE_FEC_NONE; 2916 } 2917 2918 /** 2919 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2920 * @pi: port information structure 2921 * @cfg: PHY configuration data to set FC mode 2922 * @req_mode: FC mode to configure 2923 */ 2924 static enum ice_status 2925 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2926 enum ice_fc_mode req_mode) 2927 { 2928 struct ice_phy_cache_mode_data cache_data; 2929 u8 pause_mask = 0x0; 2930 2931 if (!pi || !cfg) 2932 return ICE_ERR_BAD_PTR; 2933 2934 switch (req_mode) { 2935 case ICE_FC_AUTO: 2936 { 2937 struct ice_aqc_get_phy_caps_data *pcaps; 2938 enum ice_status status; 2939 2940 pcaps = (struct ice_aqc_get_phy_caps_data *) 2941 ice_malloc(pi->hw, sizeof(*pcaps)); 2942 if (!pcaps) 2943 return ICE_ERR_NO_MEMORY; 2944 2945 /* Query the value of FC that both the NIC and attached media 2946 * can do. 2947 */ 2948 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2949 pcaps, NULL); 2950 if (status) { 2951 ice_free(pi->hw, pcaps); 2952 return status; 2953 } 2954 2955 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2956 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2957 2958 ice_free(pi->hw, pcaps); 2959 break; 2960 } 2961 case ICE_FC_FULL: 2962 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2963 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2964 break; 2965 case ICE_FC_RX_PAUSE: 2966 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2967 break; 2968 case ICE_FC_TX_PAUSE: 2969 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2970 break; 2971 default: 2972 break; 2973 } 2974 2975 /* clear the old pause settings */ 2976 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2977 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2978 2979 /* set the new capabilities */ 2980 cfg->caps |= pause_mask; 2981 2982 /* Cache user FC request */ 2983 cache_data.data.curr_user_fc_req = req_mode; 2984 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2985 2986 return ICE_SUCCESS; 2987 } 2988 2989 /** 2990 * ice_set_fc 2991 * @pi: port information structure 2992 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2993 * @ena_auto_link_update: enable automatic link update 2994 * 2995 * Set the requested flow control mode. 2996 */ 2997 enum ice_status 2998 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2999 { 3000 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3001 struct ice_aqc_get_phy_caps_data *pcaps; 3002 enum ice_status status; 3003 struct ice_hw *hw; 3004 3005 if (!pi || !aq_failures) 3006 return ICE_ERR_BAD_PTR; 3007 3008 *aq_failures = 0; 3009 hw = pi->hw; 3010 3011 pcaps = (struct ice_aqc_get_phy_caps_data *) 3012 ice_malloc(hw, sizeof(*pcaps)); 3013 if (!pcaps) 3014 return ICE_ERR_NO_MEMORY; 3015 3016 /* Get the current PHY config */ 3017 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3018 pcaps, NULL); 3019 3020 if (status) { 3021 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3022 goto out; 3023 } 3024 3025 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3026 3027 /* Configure the set PHY data */ 3028 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3029 if (status) { 3030 if (status != ICE_ERR_BAD_PTR) 3031 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3032 3033 goto out; 3034 } 3035 3036 /* If the capabilities have changed, then set the new config */ 3037 if (cfg.caps != pcaps->caps) { 3038 int retry_count, retry_max = 10; 3039 3040 /* Auto restart link so settings take effect */ 3041 if (ena_auto_link_update) 3042 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3043 3044 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3045 if (status) { 3046 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3047 goto out; 3048 } 3049 3050 /* Update the link info 3051 * It sometimes takes a really long time for link to 3052 * come back from the atomic reset. Thus, we wait a 3053 * little bit. 3054 */ 3055 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3056 status = ice_update_link_info(pi); 3057 3058 if (status == ICE_SUCCESS) 3059 break; 3060 3061 ice_msec_delay(100, true); 3062 } 3063 3064 if (status) 3065 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3066 } 3067 3068 out: 3069 ice_free(hw, pcaps); 3070 return status; 3071 } 3072 3073 /** 3074 * ice_phy_caps_equals_cfg 3075 * @phy_caps: PHY capabilities 3076 * @phy_cfg: PHY configuration 3077 * 3078 * Helper function to determine if PHY capabilities matches PHY 3079 * configuration 3080 */ 3081 bool 3082 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3083 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3084 { 3085 u8 caps_mask, cfg_mask; 3086 3087 if (!phy_caps || !phy_cfg) 3088 return false; 3089 3090 /* These bits are not common between capabilities and configuration. 3091 * Do not use them to determine equality. 3092 */ 3093 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3094 ICE_AQC_PHY_EN_MOD_QUAL); 3095 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3096 3097 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3098 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3099 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3100 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3101 phy_caps->eee_cap != phy_cfg->eee_cap || 3102 phy_caps->eeer_value != phy_cfg->eeer_value || 3103 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3104 return false; 3105 3106 return true; 3107 } 3108 3109 /** 3110 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3111 * @pi: port information structure 3112 * @caps: PHY ability structure to copy date from 3113 * @cfg: PHY configuration structure to copy data to 3114 * 3115 * Helper function to copy AQC PHY get ability data to PHY set configuration 3116 * data structure 3117 */ 3118 void 3119 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3120 struct ice_aqc_get_phy_caps_data *caps, 3121 struct ice_aqc_set_phy_cfg_data *cfg) 3122 { 3123 if (!pi || !caps || !cfg) 3124 return; 3125 3126 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 3127 cfg->phy_type_low = caps->phy_type_low; 3128 cfg->phy_type_high = caps->phy_type_high; 3129 cfg->caps = caps->caps; 3130 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3131 cfg->eee_cap = caps->eee_cap; 3132 cfg->eeer_value = caps->eeer_value; 3133 cfg->link_fec_opt = caps->link_fec_options; 3134 cfg->module_compliance_enforcement = 3135 caps->module_compliance_enforcement; 3136 } 3137 3138 /** 3139 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3140 * @pi: port information structure 3141 * @cfg: PHY configuration data to set FEC mode 3142 * @fec: FEC mode to configure 3143 */ 3144 enum ice_status 3145 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3146 enum ice_fec_mode fec) 3147 { 3148 struct ice_aqc_get_phy_caps_data *pcaps; 3149 enum ice_status status = ICE_SUCCESS; 3150 struct ice_hw *hw; 3151 3152 if (!pi || !cfg) 3153 return ICE_ERR_BAD_PTR; 3154 3155 hw = pi->hw; 3156 3157 pcaps = (struct ice_aqc_get_phy_caps_data *) 3158 ice_malloc(hw, sizeof(*pcaps)); 3159 if (!pcaps) 3160 return ICE_ERR_NO_MEMORY; 3161 3162 status = ice_aq_get_phy_caps(pi, false, 3163 (ice_fw_supports_report_dflt_cfg(hw) ? 3164 ICE_AQC_REPORT_DFLT_CFG : 3165 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3166 3167 if (status) 3168 goto out; 3169 3170 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 3171 cfg->link_fec_opt = pcaps->link_fec_options; 3172 3173 switch (fec) { 3174 case ICE_FEC_BASER: 3175 /* Clear RS bits, and AND BASE-R ability 3176 * bits and OR request bits. 3177 */ 3178 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3179 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3180 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3181 ICE_AQC_PHY_FEC_25G_KR_REQ; 3182 break; 3183 case ICE_FEC_RS: 3184 /* Clear BASE-R bits, and AND RS ability 3185 * bits and OR request bits. 3186 */ 3187 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3188 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3189 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3190 break; 3191 case ICE_FEC_NONE: 3192 /* Clear all FEC option bits. */ 3193 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3194 break; 3195 case ICE_FEC_AUTO: 3196 /* AND auto FEC bit, and all caps bits. */ 3197 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3198 cfg->link_fec_opt |= pcaps->link_fec_options; 3199 break; 3200 default: 3201 status = ICE_ERR_PARAM; 3202 break; 3203 } 3204 3205 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && 3206 !ice_fw_supports_report_dflt_cfg(pi->hw)) { 3207 struct ice_link_default_override_tlv tlv; 3208 3209 if (ice_get_link_default_override(&tlv, pi)) 3210 goto out; 3211 3212 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3213 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3214 cfg->link_fec_opt = tlv.fec_options; 3215 } 3216 3217 out: 3218 ice_free(hw, pcaps); 3219 3220 return status; 3221 } 3222 3223 /** 3224 * ice_get_link_status - get status of the HW network link 3225 * @pi: port information structure 3226 * @link_up: pointer to bool (true/false = linkup/linkdown) 3227 * 3228 * Variable link_up is true if link is up, false if link is down. 3229 * The variable link_up is invalid if status is non zero. As a 3230 * result of this call, link status reporting becomes enabled 3231 */ 3232 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3233 { 3234 struct ice_phy_info *phy_info; 3235 enum ice_status status = ICE_SUCCESS; 3236 3237 if (!pi || !link_up) 3238 return ICE_ERR_PARAM; 3239 3240 phy_info = &pi->phy; 3241 3242 if (phy_info->get_link_info) { 3243 status = ice_update_link_info(pi); 3244 3245 if (status) 3246 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3247 status); 3248 } 3249 3250 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3251 3252 return status; 3253 } 3254 3255 /** 3256 * ice_aq_set_link_restart_an 3257 * @pi: pointer to the port information structure 3258 * @ena_link: if true: enable link, if false: disable link 3259 * @cd: pointer to command details structure or NULL 3260 * 3261 * Sets up the link and restarts the Auto-Negotiation over the link. 3262 */ 3263 enum ice_status 3264 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3265 struct ice_sq_cd *cd) 3266 { 3267 struct ice_aqc_restart_an *cmd; 3268 struct ice_aq_desc desc; 3269 3270 cmd = &desc.params.restart_an; 3271 3272 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3273 3274 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3275 cmd->lport_num = pi->lport; 3276 if (ena_link) 3277 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3278 else 3279 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3280 3281 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3282 } 3283 3284 /** 3285 * ice_aq_set_event_mask 3286 * @hw: pointer to the HW struct 3287 * @port_num: port number of the physical function 3288 * @mask: event mask to be set 3289 * @cd: pointer to command details structure or NULL 3290 * 3291 * Set event mask (0x0613) 3292 */ 3293 enum ice_status 3294 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3295 struct ice_sq_cd *cd) 3296 { 3297 struct ice_aqc_set_event_mask *cmd; 3298 struct ice_aq_desc desc; 3299 3300 cmd = &desc.params.set_event_mask; 3301 3302 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3303 3304 cmd->lport_num = port_num; 3305 3306 cmd->event_mask = CPU_TO_LE16(mask); 3307 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3308 } 3309 3310 /** 3311 * ice_aq_set_mac_loopback 3312 * @hw: pointer to the HW struct 3313 * @ena_lpbk: Enable or Disable loopback 3314 * @cd: pointer to command details structure or NULL 3315 * 3316 * Enable/disable loopback on a given port 3317 */ 3318 enum ice_status 3319 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3320 { 3321 struct ice_aqc_set_mac_lb *cmd; 3322 struct ice_aq_desc desc; 3323 3324 cmd = &desc.params.set_mac_lb; 3325 3326 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3327 if (ena_lpbk) 3328 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3329 3330 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3331 } 3332 3333 /** 3334 * ice_aq_set_port_id_led 3335 * @pi: pointer to the port information 3336 * @is_orig_mode: is this LED set to original mode (by the net-list) 3337 * @cd: pointer to command details structure or NULL 3338 * 3339 * Set LED value for the given port (0x06e9) 3340 */ 3341 enum ice_status 3342 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3343 struct ice_sq_cd *cd) 3344 { 3345 struct ice_aqc_set_port_id_led *cmd; 3346 struct ice_hw *hw = pi->hw; 3347 struct ice_aq_desc desc; 3348 3349 cmd = &desc.params.set_port_id_led; 3350 3351 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3352 3353 if (is_orig_mode) 3354 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3355 else 3356 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3357 3358 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3359 } 3360 3361 /** 3362 * ice_aq_sff_eeprom 3363 * @hw: pointer to the HW struct 3364 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3365 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3366 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3367 * @page: QSFP page 3368 * @set_page: set or ignore the page 3369 * @data: pointer to data buffer to be read/written to the I2C device. 3370 * @length: 1-16 for read, 1 for write. 3371 * @write: 0 read, 1 for write. 3372 * @cd: pointer to command details structure or NULL 3373 * 3374 * Read/Write SFF EEPROM (0x06EE) 3375 */ 3376 enum ice_status 3377 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3378 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3379 bool write, struct ice_sq_cd *cd) 3380 { 3381 struct ice_aqc_sff_eeprom *cmd; 3382 struct ice_aq_desc desc; 3383 enum ice_status status; 3384 3385 if (!data || (mem_addr & 0xff00)) 3386 return ICE_ERR_PARAM; 3387 3388 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3389 cmd = &desc.params.read_write_sff_param; 3390 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 3391 cmd->lport_num = (u8)(lport & 0xff); 3392 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3393 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 3394 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3395 ((set_page << 3396 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3397 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3398 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 3399 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3400 if (write) 3401 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 3402 3403 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3404 return status; 3405 } 3406 3407 /** 3408 * ice_aq_prog_topo_dev_nvm 3409 * @hw: pointer to the hardware structure 3410 * @topo_params: pointer to structure storing topology parameters for a device 3411 * @cd: pointer to command details structure or NULL 3412 * 3413 * Program Topology Device NVM (0x06F2) 3414 * 3415 */ 3416 enum ice_status 3417 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, 3418 struct ice_aqc_link_topo_params *topo_params, 3419 struct ice_sq_cd *cd) 3420 { 3421 struct ice_aqc_prog_topo_dev_nvm *cmd; 3422 struct ice_aq_desc desc; 3423 3424 cmd = &desc.params.prog_topo_dev_nvm; 3425 3426 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_prog_topo_dev_nvm); 3427 3428 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), 3429 ICE_NONDMA_TO_NONDMA); 3430 3431 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3432 } 3433 3434 /** 3435 * ice_aq_read_topo_dev_nvm 3436 * @hw: pointer to the hardware structure 3437 * @topo_params: pointer to structure storing topology parameters for a device 3438 * @start_address: byte offset in the topology device NVM 3439 * @data: pointer to data buffer 3440 * @data_size: number of bytes to be read from the topology device NVM 3441 * @cd: pointer to command details structure or NULL 3442 * Read Topology Device NVM (0x06F3) 3443 * 3444 */ 3445 enum ice_status 3446 ice_aq_read_topo_dev_nvm(struct ice_hw *hw, 3447 struct ice_aqc_link_topo_params *topo_params, 3448 u32 start_address, u8 *data, u8 data_size, 3449 struct ice_sq_cd *cd) 3450 { 3451 struct ice_aqc_read_topo_dev_nvm *cmd; 3452 struct ice_aq_desc desc; 3453 enum ice_status status; 3454 3455 if (!data || data_size == 0 || 3456 data_size > ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE) 3457 return ICE_ERR_PARAM; 3458 3459 cmd = &desc.params.read_topo_dev_nvm; 3460 3461 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm); 3462 3463 desc.datalen = data_size; 3464 ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), 3465 ICE_NONDMA_TO_NONDMA); 3466 cmd->start_address = CPU_TO_LE32(start_address); 3467 3468 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3469 if (status) 3470 return status; 3471 3472 ice_memcpy(data, cmd->data_read, data_size, ICE_NONDMA_TO_NONDMA); 3473 3474 return ICE_SUCCESS; 3475 } 3476 3477 /** 3478 * __ice_aq_get_set_rss_lut 3479 * @hw: pointer to the hardware structure 3480 * @params: RSS LUT parameters 3481 * @set: set true to set the table, false to get the table 3482 * 3483 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3484 */ 3485 static enum ice_status 3486 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3487 { 3488 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3489 struct ice_aqc_get_set_rss_lut *cmd_resp; 3490 struct ice_aq_desc desc; 3491 enum ice_status status; 3492 u8 *lut; 3493 3494 if (!params) 3495 return ICE_ERR_PARAM; 3496 3497 vsi_handle = params->vsi_handle; 3498 lut = params->lut; 3499 3500 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3501 return ICE_ERR_PARAM; 3502 3503 lut_size = params->lut_size; 3504 lut_type = params->lut_type; 3505 glob_lut_idx = params->global_lut_id; 3506 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3507 3508 cmd_resp = &desc.params.get_set_rss_lut; 3509 3510 if (set) { 3511 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3512 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3513 } else { 3514 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3515 } 3516 3517 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3518 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3519 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3520 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3521 3522 switch (lut_type) { 3523 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3524 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3525 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3526 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3527 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3528 break; 3529 default: 3530 status = ICE_ERR_PARAM; 3531 goto ice_aq_get_set_rss_lut_exit; 3532 } 3533 3534 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3535 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3536 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3537 3538 if (!set) 3539 goto ice_aq_get_set_rss_lut_send; 3540 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3541 if (!set) 3542 goto ice_aq_get_set_rss_lut_send; 3543 } else { 3544 goto ice_aq_get_set_rss_lut_send; 3545 } 3546 3547 /* LUT size is only valid for Global and PF table types */ 3548 switch (lut_size) { 3549 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3550 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 3551 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3552 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3553 break; 3554 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3555 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3556 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3557 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3558 break; 3559 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3560 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3561 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3562 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3563 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3564 break; 3565 } 3566 /* fall-through */ 3567 default: 3568 status = ICE_ERR_PARAM; 3569 goto ice_aq_get_set_rss_lut_exit; 3570 } 3571 3572 ice_aq_get_set_rss_lut_send: 3573 cmd_resp->flags = CPU_TO_LE16(flags); 3574 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3575 3576 ice_aq_get_set_rss_lut_exit: 3577 return status; 3578 } 3579 3580 /** 3581 * ice_aq_get_rss_lut 3582 * @hw: pointer to the hardware structure 3583 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3584 * 3585 * get the RSS lookup table, PF or VSI type 3586 */ 3587 enum ice_status 3588 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3589 { 3590 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3591 } 3592 3593 /** 3594 * ice_aq_set_rss_lut 3595 * @hw: pointer to the hardware structure 3596 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3597 * 3598 * set the RSS lookup table, PF or VSI type 3599 */ 3600 enum ice_status 3601 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3602 { 3603 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3604 } 3605 3606 /** 3607 * __ice_aq_get_set_rss_key 3608 * @hw: pointer to the HW struct 3609 * @vsi_id: VSI FW index 3610 * @key: pointer to key info struct 3611 * @set: set true to set the key, false to get the key 3612 * 3613 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3614 */ 3615 static enum 3616 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3617 struct ice_aqc_get_set_rss_keys *key, 3618 bool set) 3619 { 3620 struct ice_aqc_get_set_rss_key *cmd_resp; 3621 u16 key_size = sizeof(*key); 3622 struct ice_aq_desc desc; 3623 3624 cmd_resp = &desc.params.get_set_rss_key; 3625 3626 if (set) { 3627 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3628 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3629 } else { 3630 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3631 } 3632 3633 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3634 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3635 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3636 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3637 3638 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3639 } 3640 3641 /** 3642 * ice_aq_get_rss_key 3643 * @hw: pointer to the HW struct 3644 * @vsi_handle: software VSI handle 3645 * @key: pointer to key info struct 3646 * 3647 * get the RSS key per VSI 3648 */ 3649 enum ice_status 3650 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3651 struct ice_aqc_get_set_rss_keys *key) 3652 { 3653 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3654 return ICE_ERR_PARAM; 3655 3656 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3657 key, false); 3658 } 3659 3660 /** 3661 * ice_aq_set_rss_key 3662 * @hw: pointer to the HW struct 3663 * @vsi_handle: software VSI handle 3664 * @keys: pointer to key info struct 3665 * 3666 * set the RSS key per VSI 3667 */ 3668 enum ice_status 3669 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3670 struct ice_aqc_get_set_rss_keys *keys) 3671 { 3672 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3673 return ICE_ERR_PARAM; 3674 3675 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3676 keys, true); 3677 } 3678 3679 /** 3680 * ice_aq_add_lan_txq 3681 * @hw: pointer to the hardware structure 3682 * @num_qgrps: Number of added queue groups 3683 * @qg_list: list of queue groups to be added 3684 * @buf_size: size of buffer for indirect command 3685 * @cd: pointer to command details structure or NULL 3686 * 3687 * Add Tx LAN queue (0x0C30) 3688 * 3689 * NOTE: 3690 * Prior to calling add Tx LAN queue: 3691 * Initialize the following as part of the Tx queue context: 3692 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3693 * Cache profile and Packet shaper profile. 3694 * 3695 * After add Tx LAN queue AQ command is completed: 3696 * Interrupts should be associated with specific queues, 3697 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3698 * flow. 3699 */ 3700 enum ice_status 3701 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3702 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3703 struct ice_sq_cd *cd) 3704 { 3705 struct ice_aqc_add_tx_qgrp *list; 3706 struct ice_aqc_add_txqs *cmd; 3707 struct ice_aq_desc desc; 3708 u16 i, sum_size = 0; 3709 3710 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3711 3712 cmd = &desc.params.add_txqs; 3713 3714 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3715 3716 if (!qg_list) 3717 return ICE_ERR_PARAM; 3718 3719 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3720 return ICE_ERR_PARAM; 3721 3722 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3723 sum_size += ice_struct_size(list, txqs, list->num_txqs); 3724 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3725 list->num_txqs); 3726 } 3727 3728 if (buf_size != sum_size) 3729 return ICE_ERR_PARAM; 3730 3731 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3732 3733 cmd->num_qgrps = num_qgrps; 3734 3735 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3736 } 3737 3738 /** 3739 * ice_aq_dis_lan_txq 3740 * @hw: pointer to the hardware structure 3741 * @num_qgrps: number of groups in the list 3742 * @qg_list: the list of groups to disable 3743 * @buf_size: the total size of the qg_list buffer in bytes 3744 * @rst_src: if called due to reset, specifies the reset source 3745 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3746 * @cd: pointer to command details structure or NULL 3747 * 3748 * Disable LAN Tx queue (0x0C31) 3749 */ 3750 static enum ice_status 3751 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3752 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3753 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3754 struct ice_sq_cd *cd) 3755 { 3756 struct ice_aqc_dis_txq_item *item; 3757 struct ice_aqc_dis_txqs *cmd; 3758 struct ice_aq_desc desc; 3759 enum ice_status status; 3760 u16 i, sz = 0; 3761 3762 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3763 cmd = &desc.params.dis_txqs; 3764 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3765 3766 /* qg_list can be NULL only in VM/VF reset flow */ 3767 if (!qg_list && !rst_src) 3768 return ICE_ERR_PARAM; 3769 3770 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3771 return ICE_ERR_PARAM; 3772 3773 cmd->num_entries = num_qgrps; 3774 3775 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3776 ICE_AQC_Q_DIS_TIMEOUT_M); 3777 3778 switch (rst_src) { 3779 case ICE_VM_RESET: 3780 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3781 cmd->vmvf_and_timeout |= 3782 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3783 break; 3784 case ICE_NO_RESET: 3785 default: 3786 break; 3787 } 3788 3789 /* flush pipe on time out */ 3790 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3791 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3792 if (!qg_list) 3793 goto do_aq; 3794 3795 /* set RD bit to indicate that command buffer is provided by the driver 3796 * and it needs to be read by the firmware 3797 */ 3798 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3799 3800 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3801 u16 item_size = ice_struct_size(item, q_id, item->num_qs); 3802 3803 /* If the num of queues is even, add 2 bytes of padding */ 3804 if ((item->num_qs % 2) == 0) 3805 item_size += 2; 3806 3807 sz += item_size; 3808 3809 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3810 } 3811 3812 if (buf_size != sz) 3813 return ICE_ERR_PARAM; 3814 3815 do_aq: 3816 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3817 if (status) { 3818 if (!qg_list) 3819 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3820 vmvf_num, hw->adminq.sq_last_status); 3821 else 3822 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3823 LE16_TO_CPU(qg_list[0].q_id[0]), 3824 hw->adminq.sq_last_status); 3825 } 3826 return status; 3827 } 3828 3829 /** 3830 * ice_aq_move_recfg_lan_txq 3831 * @hw: pointer to the hardware structure 3832 * @num_qs: number of queues to move/reconfigure 3833 * @is_move: true if this operation involves node movement 3834 * @is_tc_change: true if this operation involves a TC change 3835 * @subseq_call: true if this operation is a subsequent call 3836 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 3837 * @timeout: timeout in units of 100 usec (valid values 0-50) 3838 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 3839 * @buf: struct containing src/dest TEID and per-queue info 3840 * @buf_size: size of buffer for indirect command 3841 * @txqs_moved: out param, number of queues successfully moved 3842 * @cd: pointer to command details structure or NULL 3843 * 3844 * Move / Reconfigure Tx LAN queues (0x0C32) 3845 */ 3846 enum ice_status 3847 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 3848 bool is_tc_change, bool subseq_call, bool flush_pipe, 3849 u8 timeout, u32 *blocked_cgds, 3850 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 3851 u8 *txqs_moved, struct ice_sq_cd *cd) 3852 { 3853 struct ice_aqc_move_txqs *cmd; 3854 struct ice_aq_desc desc; 3855 enum ice_status status; 3856 3857 cmd = &desc.params.move_txqs; 3858 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 3859 3860 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 3861 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 3862 return ICE_ERR_PARAM; 3863 3864 if (is_tc_change && !flush_pipe && !blocked_cgds) 3865 return ICE_ERR_PARAM; 3866 3867 if (!is_move && !is_tc_change) 3868 return ICE_ERR_PARAM; 3869 3870 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3871 3872 if (is_move) 3873 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 3874 3875 if (is_tc_change) 3876 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 3877 3878 if (subseq_call) 3879 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 3880 3881 if (flush_pipe) 3882 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 3883 3884 cmd->num_qs = num_qs; 3885 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 3886 ICE_AQC_Q_CMD_TIMEOUT_M); 3887 3888 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3889 3890 if (!status && txqs_moved) 3891 *txqs_moved = cmd->num_qs; 3892 3893 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 3894 is_tc_change && !flush_pipe) 3895 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 3896 3897 return status; 3898 } 3899 3900 /* End of FW Admin Queue command wrappers */ 3901 3902 /** 3903 * ice_write_byte - write a byte to a packed context structure 3904 * @src_ctx: the context structure to read from 3905 * @dest_ctx: the context to be written to 3906 * @ce_info: a description of the struct to be filled 3907 */ 3908 static void 3909 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3910 { 3911 u8 src_byte, dest_byte, mask; 3912 u8 *from, *dest; 3913 u16 shift_width; 3914 3915 /* copy from the next struct field */ 3916 from = src_ctx + ce_info->offset; 3917 3918 /* prepare the bits and mask */ 3919 shift_width = ce_info->lsb % 8; 3920 mask = (u8)(BIT(ce_info->width) - 1); 3921 3922 src_byte = *from; 3923 src_byte &= mask; 3924 3925 /* shift to correct alignment */ 3926 mask <<= shift_width; 3927 src_byte <<= shift_width; 3928 3929 /* get the current bits from the target bit string */ 3930 dest = dest_ctx + (ce_info->lsb / 8); 3931 3932 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3933 3934 dest_byte &= ~mask; /* get the bits not changing */ 3935 dest_byte |= src_byte; /* add in the new bits */ 3936 3937 /* put it all back */ 3938 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3939 } 3940 3941 /** 3942 * ice_write_word - write a word to a packed context structure 3943 * @src_ctx: the context structure to read from 3944 * @dest_ctx: the context to be written to 3945 * @ce_info: a description of the struct to be filled 3946 */ 3947 static void 3948 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3949 { 3950 u16 src_word, mask; 3951 __le16 dest_word; 3952 u8 *from, *dest; 3953 u16 shift_width; 3954 3955 /* copy from the next struct field */ 3956 from = src_ctx + ce_info->offset; 3957 3958 /* prepare the bits and mask */ 3959 shift_width = ce_info->lsb % 8; 3960 mask = BIT(ce_info->width) - 1; 3961 3962 /* don't swizzle the bits until after the mask because the mask bits 3963 * will be in a different bit position on big endian machines 3964 */ 3965 src_word = *(u16 *)from; 3966 src_word &= mask; 3967 3968 /* shift to correct alignment */ 3969 mask <<= shift_width; 3970 src_word <<= shift_width; 3971 3972 /* get the current bits from the target bit string */ 3973 dest = dest_ctx + (ce_info->lsb / 8); 3974 3975 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 3976 3977 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 3978 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 3979 3980 /* put it all back */ 3981 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3982 } 3983 3984 /** 3985 * ice_write_dword - write a dword to a packed context structure 3986 * @src_ctx: the context structure to read from 3987 * @dest_ctx: the context to be written to 3988 * @ce_info: a description of the struct to be filled 3989 */ 3990 static void 3991 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3992 { 3993 u32 src_dword, mask; 3994 __le32 dest_dword; 3995 u8 *from, *dest; 3996 u16 shift_width; 3997 3998 /* copy from the next struct field */ 3999 from = src_ctx + ce_info->offset; 4000 4001 /* prepare the bits and mask */ 4002 shift_width = ce_info->lsb % 8; 4003 4004 /* if the field width is exactly 32 on an x86 machine, then the shift 4005 * operation will not work because the SHL instructions count is masked 4006 * to 5 bits so the shift will do nothing 4007 */ 4008 if (ce_info->width < 32) 4009 mask = BIT(ce_info->width) - 1; 4010 else 4011 mask = (u32)~0; 4012 4013 /* don't swizzle the bits until after the mask because the mask bits 4014 * will be in a different bit position on big endian machines 4015 */ 4016 src_dword = *(u32 *)from; 4017 src_dword &= mask; 4018 4019 /* shift to correct alignment */ 4020 mask <<= shift_width; 4021 src_dword <<= shift_width; 4022 4023 /* get the current bits from the target bit string */ 4024 dest = dest_ctx + (ce_info->lsb / 8); 4025 4026 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 4027 4028 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 4029 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 4030 4031 /* put it all back */ 4032 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4033 } 4034 4035 /** 4036 * ice_write_qword - write a qword to a packed context structure 4037 * @src_ctx: the context structure to read from 4038 * @dest_ctx: the context to be written to 4039 * @ce_info: a description of the struct to be filled 4040 */ 4041 static void 4042 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4043 { 4044 u64 src_qword, mask; 4045 __le64 dest_qword; 4046 u8 *from, *dest; 4047 u16 shift_width; 4048 4049 /* copy from the next struct field */ 4050 from = src_ctx + ce_info->offset; 4051 4052 /* prepare the bits and mask */ 4053 shift_width = ce_info->lsb % 8; 4054 4055 /* if the field width is exactly 64 on an x86 machine, then the shift 4056 * operation will not work because the SHL instructions count is masked 4057 * to 6 bits so the shift will do nothing 4058 */ 4059 if (ce_info->width < 64) 4060 mask = BIT_ULL(ce_info->width) - 1; 4061 else 4062 mask = (u64)~0; 4063 4064 /* don't swizzle the bits until after the mask because the mask bits 4065 * will be in a different bit position on big endian machines 4066 */ 4067 src_qword = *(u64 *)from; 4068 src_qword &= mask; 4069 4070 /* shift to correct alignment */ 4071 mask <<= shift_width; 4072 src_qword <<= shift_width; 4073 4074 /* get the current bits from the target bit string */ 4075 dest = dest_ctx + (ce_info->lsb / 8); 4076 4077 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 4078 4079 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 4080 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 4081 4082 /* put it all back */ 4083 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4084 } 4085 4086 /** 4087 * ice_set_ctx - set context bits in packed structure 4088 * @hw: pointer to the hardware structure 4089 * @src_ctx: pointer to a generic non-packed context structure 4090 * @dest_ctx: pointer to memory for the packed structure 4091 * @ce_info: a description of the structure to be transformed 4092 */ 4093 enum ice_status 4094 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4095 const struct ice_ctx_ele *ce_info) 4096 { 4097 int f; 4098 4099 for (f = 0; ce_info[f].width; f++) { 4100 /* We have to deal with each element of the FW response 4101 * using the correct size so that we are correct regardless 4102 * of the endianness of the machine. 4103 */ 4104 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4105 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4106 f, ce_info[f].width, ce_info[f].size_of); 4107 continue; 4108 } 4109 switch (ce_info[f].size_of) { 4110 case sizeof(u8): 4111 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4112 break; 4113 case sizeof(u16): 4114 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4115 break; 4116 case sizeof(u32): 4117 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4118 break; 4119 case sizeof(u64): 4120 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4121 break; 4122 default: 4123 return ICE_ERR_INVAL_SIZE; 4124 } 4125 } 4126 4127 return ICE_SUCCESS; 4128 } 4129 4130 /** 4131 * ice_read_byte - read context byte into struct 4132 * @src_ctx: the context structure to read from 4133 * @dest_ctx: the context to be written to 4134 * @ce_info: a description of the struct to be filled 4135 */ 4136 static void 4137 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4138 { 4139 u8 dest_byte, mask; 4140 u8 *src, *target; 4141 u16 shift_width; 4142 4143 /* prepare the bits and mask */ 4144 shift_width = ce_info->lsb % 8; 4145 mask = (u8)(BIT(ce_info->width) - 1); 4146 4147 /* shift to correct alignment */ 4148 mask <<= shift_width; 4149 4150 /* get the current bits from the src bit string */ 4151 src = src_ctx + (ce_info->lsb / 8); 4152 4153 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4154 4155 dest_byte &= ~(mask); 4156 4157 dest_byte >>= shift_width; 4158 4159 /* get the address from the struct field */ 4160 target = dest_ctx + ce_info->offset; 4161 4162 /* put it back in the struct */ 4163 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4164 } 4165 4166 /** 4167 * ice_read_word - read context word into struct 4168 * @src_ctx: the context structure to read from 4169 * @dest_ctx: the context to be written to 4170 * @ce_info: a description of the struct to be filled 4171 */ 4172 static void 4173 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4174 { 4175 u16 dest_word, mask; 4176 u8 *src, *target; 4177 __le16 src_word; 4178 u16 shift_width; 4179 4180 /* prepare the bits and mask */ 4181 shift_width = ce_info->lsb % 8; 4182 mask = BIT(ce_info->width) - 1; 4183 4184 /* shift to correct alignment */ 4185 mask <<= shift_width; 4186 4187 /* get the current bits from the src bit string */ 4188 src = src_ctx + (ce_info->lsb / 8); 4189 4190 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 4191 4192 /* the data in the memory is stored as little endian so mask it 4193 * correctly 4194 */ 4195 src_word &= ~(CPU_TO_LE16(mask)); 4196 4197 /* get the data back into host order before shifting */ 4198 dest_word = LE16_TO_CPU(src_word); 4199 4200 dest_word >>= shift_width; 4201 4202 /* get the address from the struct field */ 4203 target = dest_ctx + ce_info->offset; 4204 4205 /* put it back in the struct */ 4206 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4207 } 4208 4209 /** 4210 * ice_read_dword - read context dword into struct 4211 * @src_ctx: the context structure to read from 4212 * @dest_ctx: the context to be written to 4213 * @ce_info: a description of the struct to be filled 4214 */ 4215 static void 4216 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4217 { 4218 u32 dest_dword, mask; 4219 __le32 src_dword; 4220 u8 *src, *target; 4221 u16 shift_width; 4222 4223 /* prepare the bits and mask */ 4224 shift_width = ce_info->lsb % 8; 4225 4226 /* if the field width is exactly 32 on an x86 machine, then the shift 4227 * operation will not work because the SHL instructions count is masked 4228 * to 5 bits so the shift will do nothing 4229 */ 4230 if (ce_info->width < 32) 4231 mask = BIT(ce_info->width) - 1; 4232 else 4233 mask = (u32)~0; 4234 4235 /* shift to correct alignment */ 4236 mask <<= shift_width; 4237 4238 /* get the current bits from the src bit string */ 4239 src = src_ctx + (ce_info->lsb / 8); 4240 4241 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 4242 4243 /* the data in the memory is stored as little endian so mask it 4244 * correctly 4245 */ 4246 src_dword &= ~(CPU_TO_LE32(mask)); 4247 4248 /* get the data back into host order before shifting */ 4249 dest_dword = LE32_TO_CPU(src_dword); 4250 4251 dest_dword >>= shift_width; 4252 4253 /* get the address from the struct field */ 4254 target = dest_ctx + ce_info->offset; 4255 4256 /* put it back in the struct */ 4257 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4258 } 4259 4260 /** 4261 * ice_read_qword - read context qword into struct 4262 * @src_ctx: the context structure to read from 4263 * @dest_ctx: the context to be written to 4264 * @ce_info: a description of the struct to be filled 4265 */ 4266 static void 4267 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4268 { 4269 u64 dest_qword, mask; 4270 __le64 src_qword; 4271 u8 *src, *target; 4272 u16 shift_width; 4273 4274 /* prepare the bits and mask */ 4275 shift_width = ce_info->lsb % 8; 4276 4277 /* if the field width is exactly 64 on an x86 machine, then the shift 4278 * operation will not work because the SHL instructions count is masked 4279 * to 6 bits so the shift will do nothing 4280 */ 4281 if (ce_info->width < 64) 4282 mask = BIT_ULL(ce_info->width) - 1; 4283 else 4284 mask = (u64)~0; 4285 4286 /* shift to correct alignment */ 4287 mask <<= shift_width; 4288 4289 /* get the current bits from the src bit string */ 4290 src = src_ctx + (ce_info->lsb / 8); 4291 4292 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 4293 4294 /* the data in the memory is stored as little endian so mask it 4295 * correctly 4296 */ 4297 src_qword &= ~(CPU_TO_LE64(mask)); 4298 4299 /* get the data back into host order before shifting */ 4300 dest_qword = LE64_TO_CPU(src_qword); 4301 4302 dest_qword >>= shift_width; 4303 4304 /* get the address from the struct field */ 4305 target = dest_ctx + ce_info->offset; 4306 4307 /* put it back in the struct */ 4308 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4309 } 4310 4311 /** 4312 * ice_get_ctx - extract context bits from a packed structure 4313 * @src_ctx: pointer to a generic packed context structure 4314 * @dest_ctx: pointer to a generic non-packed context structure 4315 * @ce_info: a description of the structure to be read from 4316 */ 4317 enum ice_status 4318 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4319 { 4320 int f; 4321 4322 for (f = 0; ce_info[f].width; f++) { 4323 switch (ce_info[f].size_of) { 4324 case 1: 4325 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 4326 break; 4327 case 2: 4328 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 4329 break; 4330 case 4: 4331 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 4332 break; 4333 case 8: 4334 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 4335 break; 4336 default: 4337 /* nothing to do, just keep going */ 4338 break; 4339 } 4340 } 4341 4342 return ICE_SUCCESS; 4343 } 4344 4345 /** 4346 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4347 * @hw: pointer to the HW struct 4348 * @vsi_handle: software VSI handle 4349 * @tc: TC number 4350 * @q_handle: software queue handle 4351 */ 4352 struct ice_q_ctx * 4353 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4354 { 4355 struct ice_vsi_ctx *vsi; 4356 struct ice_q_ctx *q_ctx; 4357 4358 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4359 if (!vsi) 4360 return NULL; 4361 if (q_handle >= vsi->num_lan_q_entries[tc]) 4362 return NULL; 4363 if (!vsi->lan_q_ctx[tc]) 4364 return NULL; 4365 q_ctx = vsi->lan_q_ctx[tc]; 4366 return &q_ctx[q_handle]; 4367 } 4368 4369 /** 4370 * ice_ena_vsi_txq 4371 * @pi: port information structure 4372 * @vsi_handle: software VSI handle 4373 * @tc: TC number 4374 * @q_handle: software queue handle 4375 * @num_qgrps: Number of added queue groups 4376 * @buf: list of queue groups to be added 4377 * @buf_size: size of buffer for indirect command 4378 * @cd: pointer to command details structure or NULL 4379 * 4380 * This function adds one LAN queue 4381 */ 4382 enum ice_status 4383 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4384 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4385 struct ice_sq_cd *cd) 4386 { 4387 struct ice_aqc_txsched_elem_data node = { 0 }; 4388 struct ice_sched_node *parent; 4389 struct ice_q_ctx *q_ctx; 4390 enum ice_status status; 4391 struct ice_hw *hw; 4392 4393 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4394 return ICE_ERR_CFG; 4395 4396 if (num_qgrps > 1 || buf->num_txqs > 1) 4397 return ICE_ERR_MAX_LIMIT; 4398 4399 hw = pi->hw; 4400 4401 if (!ice_is_vsi_valid(hw, vsi_handle)) 4402 return ICE_ERR_PARAM; 4403 4404 ice_acquire_lock(&pi->sched_lock); 4405 4406 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4407 if (!q_ctx) { 4408 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4409 q_handle); 4410 status = ICE_ERR_PARAM; 4411 goto ena_txq_exit; 4412 } 4413 4414 /* find a parent node */ 4415 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4416 ICE_SCHED_NODE_OWNER_LAN); 4417 if (!parent) { 4418 status = ICE_ERR_PARAM; 4419 goto ena_txq_exit; 4420 } 4421 4422 buf->parent_teid = parent->info.node_teid; 4423 node.parent_teid = parent->info.node_teid; 4424 /* Mark that the values in the "generic" section as valid. The default 4425 * value in the "generic" section is zero. This means that : 4426 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4427 * - 0 priority among siblings, indicated by Bit 1-3. 4428 * - WFQ, indicated by Bit 4. 4429 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4430 * Bit 5-6. 4431 * - Bit 7 is reserved. 4432 * Without setting the generic section as valid in valid_sections, the 4433 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4434 */ 4435 buf->txqs[0].info.valid_sections = 4436 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4437 ICE_AQC_ELEM_VALID_EIR; 4438 buf->txqs[0].info.generic = 0; 4439 buf->txqs[0].info.cir_bw.bw_profile_idx = 4440 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4441 buf->txqs[0].info.cir_bw.bw_alloc = 4442 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4443 buf->txqs[0].info.eir_bw.bw_profile_idx = 4444 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4445 buf->txqs[0].info.eir_bw.bw_alloc = 4446 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4447 4448 /* add the LAN queue */ 4449 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4450 if (status != ICE_SUCCESS) { 4451 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4452 LE16_TO_CPU(buf->txqs[0].txq_id), 4453 hw->adminq.sq_last_status); 4454 goto ena_txq_exit; 4455 } 4456 4457 node.node_teid = buf->txqs[0].q_teid; 4458 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4459 q_ctx->q_handle = q_handle; 4460 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 4461 4462 /* add a leaf node into scheduler tree queue layer */ 4463 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4464 if (!status) 4465 status = ice_sched_replay_q_bw(pi, q_ctx); 4466 4467 ena_txq_exit: 4468 ice_release_lock(&pi->sched_lock); 4469 return status; 4470 } 4471 4472 /** 4473 * ice_dis_vsi_txq 4474 * @pi: port information structure 4475 * @vsi_handle: software VSI handle 4476 * @tc: TC number 4477 * @num_queues: number of queues 4478 * @q_handles: pointer to software queue handle array 4479 * @q_ids: pointer to the q_id array 4480 * @q_teids: pointer to queue node teids 4481 * @rst_src: if called due to reset, specifies the reset source 4482 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4483 * @cd: pointer to command details structure or NULL 4484 * 4485 * This function removes queues and their corresponding nodes in SW DB 4486 */ 4487 enum ice_status 4488 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4489 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4490 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4491 struct ice_sq_cd *cd) 4492 { 4493 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4494 struct ice_aqc_dis_txq_item *qg_list; 4495 struct ice_q_ctx *q_ctx; 4496 struct ice_hw *hw; 4497 u16 i, buf_size; 4498 4499 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4500 return ICE_ERR_CFG; 4501 4502 hw = pi->hw; 4503 4504 if (!num_queues) { 4505 /* if queue is disabled already yet the disable queue command 4506 * has to be sent to complete the VF reset, then call 4507 * ice_aq_dis_lan_txq without any queue information 4508 */ 4509 if (rst_src) 4510 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4511 vmvf_num, NULL); 4512 return ICE_ERR_CFG; 4513 } 4514 4515 buf_size = ice_struct_size(qg_list, q_id, 1); 4516 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size); 4517 if (!qg_list) 4518 return ICE_ERR_NO_MEMORY; 4519 4520 ice_acquire_lock(&pi->sched_lock); 4521 4522 for (i = 0; i < num_queues; i++) { 4523 struct ice_sched_node *node; 4524 4525 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4526 if (!node) 4527 continue; 4528 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4529 if (!q_ctx) { 4530 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4531 q_handles[i]); 4532 continue; 4533 } 4534 if (q_ctx->q_handle != q_handles[i]) { 4535 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4536 q_ctx->q_handle, q_handles[i]); 4537 continue; 4538 } 4539 qg_list->parent_teid = node->info.parent_teid; 4540 qg_list->num_qs = 1; 4541 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]); 4542 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4543 vmvf_num, cd); 4544 4545 if (status != ICE_SUCCESS) 4546 break; 4547 ice_free_sched_node(pi, node); 4548 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4549 } 4550 ice_release_lock(&pi->sched_lock); 4551 ice_free(hw, qg_list); 4552 return status; 4553 } 4554 4555 /** 4556 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4557 * @pi: port information structure 4558 * @vsi_handle: software VSI handle 4559 * @tc_bitmap: TC bitmap 4560 * @maxqs: max queues array per TC 4561 * @owner: LAN or RDMA 4562 * 4563 * This function adds/updates the VSI queues per TC. 4564 */ 4565 static enum ice_status 4566 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4567 u16 *maxqs, u8 owner) 4568 { 4569 enum ice_status status = ICE_SUCCESS; 4570 u8 i; 4571 4572 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4573 return ICE_ERR_CFG; 4574 4575 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4576 return ICE_ERR_PARAM; 4577 4578 ice_acquire_lock(&pi->sched_lock); 4579 4580 ice_for_each_traffic_class(i) { 4581 /* configuration is possible only if TC node is present */ 4582 if (!ice_sched_get_tc_node(pi, i)) 4583 continue; 4584 4585 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4586 ice_is_tc_ena(tc_bitmap, i)); 4587 if (status) 4588 break; 4589 } 4590 4591 ice_release_lock(&pi->sched_lock); 4592 return status; 4593 } 4594 4595 /** 4596 * ice_cfg_vsi_lan - configure VSI LAN queues 4597 * @pi: port information structure 4598 * @vsi_handle: software VSI handle 4599 * @tc_bitmap: TC bitmap 4600 * @max_lanqs: max LAN queues array per TC 4601 * 4602 * This function adds/updates the VSI LAN queues per TC. 4603 */ 4604 enum ice_status 4605 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4606 u16 *max_lanqs) 4607 { 4608 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4609 ICE_SCHED_NODE_OWNER_LAN); 4610 } 4611 4612 /** 4613 * ice_is_main_vsi - checks whether the VSI is main VSI 4614 * @hw: pointer to the HW struct 4615 * @vsi_handle: VSI handle 4616 * 4617 * Checks whether the VSI is the main VSI (the first PF VSI created on 4618 * given PF). 4619 */ 4620 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 4621 { 4622 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 4623 } 4624 4625 /** 4626 * ice_replay_pre_init - replay pre initialization 4627 * @hw: pointer to the HW struct 4628 * @sw: pointer to switch info struct for which function initializes filters 4629 * 4630 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4631 */ 4632 static enum ice_status 4633 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 4634 { 4635 enum ice_status status; 4636 u8 i; 4637 4638 /* Delete old entries from replay filter list head if there is any */ 4639 ice_rm_sw_replay_rule_info(hw, sw); 4640 /* In start of replay, move entries into replay_rules list, it 4641 * will allow adding rules entries back to filt_rules list, 4642 * which is operational list. 4643 */ 4644 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4645 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 4646 &sw->recp_list[i].filt_replay_rules); 4647 ice_sched_replay_agg_vsi_preinit(hw); 4648 4649 status = ice_sched_replay_root_node_bw(hw->port_info); 4650 if (status) 4651 return status; 4652 4653 return ice_sched_replay_tc_node_bw(hw->port_info); 4654 } 4655 4656 /** 4657 * ice_replay_vsi - replay VSI configuration 4658 * @hw: pointer to the HW struct 4659 * @vsi_handle: driver VSI handle 4660 * 4661 * Restore all VSI configuration after reset. It is required to call this 4662 * function with main VSI first. 4663 */ 4664 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4665 { 4666 struct ice_switch_info *sw = hw->switch_info; 4667 struct ice_port_info *pi = hw->port_info; 4668 enum ice_status status; 4669 4670 if (!ice_is_vsi_valid(hw, vsi_handle)) 4671 return ICE_ERR_PARAM; 4672 4673 /* Replay pre-initialization if there is any */ 4674 if (ice_is_main_vsi(hw, vsi_handle)) { 4675 status = ice_replay_pre_init(hw, sw); 4676 if (status) 4677 return status; 4678 } 4679 /* Replay per VSI all RSS configurations */ 4680 status = ice_replay_rss_cfg(hw, vsi_handle); 4681 if (status) 4682 return status; 4683 /* Replay per VSI all filters */ 4684 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 4685 if (!status) 4686 status = ice_replay_vsi_agg(hw, vsi_handle); 4687 return status; 4688 } 4689 4690 /** 4691 * ice_replay_post - post replay configuration cleanup 4692 * @hw: pointer to the HW struct 4693 * 4694 * Post replay cleanup. 4695 */ 4696 void ice_replay_post(struct ice_hw *hw) 4697 { 4698 /* Delete old entries from replay filter list head */ 4699 ice_rm_all_sw_replay_rule_info(hw); 4700 ice_sched_replay_agg(hw); 4701 } 4702 4703 /** 4704 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4705 * @hw: ptr to the hardware info 4706 * @reg: offset of 64 bit HW register to read from 4707 * @prev_stat_loaded: bool to specify if previous stats are loaded 4708 * @prev_stat: ptr to previous loaded stat value 4709 * @cur_stat: ptr to current stat value 4710 */ 4711 void 4712 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4713 u64 *prev_stat, u64 *cur_stat) 4714 { 4715 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4716 4717 /* device stats are not reset at PFR, they likely will not be zeroed 4718 * when the driver starts. Thus, save the value from the first read 4719 * without adding to the statistic value so that we report stats which 4720 * count up from zero. 4721 */ 4722 if (!prev_stat_loaded) { 4723 *prev_stat = new_data; 4724 return; 4725 } 4726 4727 /* Calculate the difference between the new and old values, and then 4728 * add it to the software stat value. 4729 */ 4730 if (new_data >= *prev_stat) 4731 *cur_stat += new_data - *prev_stat; 4732 else 4733 /* to manage the potential roll-over */ 4734 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4735 4736 /* Update the previously stored value to prepare for next read */ 4737 *prev_stat = new_data; 4738 } 4739 4740 /** 4741 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4742 * @hw: ptr to the hardware info 4743 * @reg: offset of HW register to read from 4744 * @prev_stat_loaded: bool to specify if previous stats are loaded 4745 * @prev_stat: ptr to previous loaded stat value 4746 * @cur_stat: ptr to current stat value 4747 */ 4748 void 4749 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4750 u64 *prev_stat, u64 *cur_stat) 4751 { 4752 u32 new_data; 4753 4754 new_data = rd32(hw, reg); 4755 4756 /* device stats are not reset at PFR, they likely will not be zeroed 4757 * when the driver starts. Thus, save the value from the first read 4758 * without adding to the statistic value so that we report stats which 4759 * count up from zero. 4760 */ 4761 if (!prev_stat_loaded) { 4762 *prev_stat = new_data; 4763 return; 4764 } 4765 4766 /* Calculate the difference between the new and old values, and then 4767 * add it to the software stat value. 4768 */ 4769 if (new_data >= *prev_stat) 4770 *cur_stat += new_data - *prev_stat; 4771 else 4772 /* to manage the potential roll-over */ 4773 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4774 4775 /* Update the previously stored value to prepare for next read */ 4776 *prev_stat = new_data; 4777 } 4778 4779 /** 4780 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 4781 * @hw: ptr to the hardware info 4782 * @vsi_handle: VSI handle 4783 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 4784 * @cur_stats: ptr to current stats structure 4785 * 4786 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 4787 * thus cannot be read using the normal ice_stat_update32 function. 4788 * 4789 * Read the GLV_REPC register associated with the given VSI, and update the 4790 * rx_no_desc and rx_error values in the ice_eth_stats structure. 4791 * 4792 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 4793 * cleared each time it's read. 4794 * 4795 * Note that the GLV_RDPC register also counts the causes that would trigger 4796 * GLV_REPC. However, it does not give the finer grained detail about why the 4797 * packets are being dropped. The GLV_REPC values can be used to distinguish 4798 * whether Rx packets are dropped due to errors or due to no available 4799 * descriptors. 4800 */ 4801 void 4802 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 4803 struct ice_eth_stats *cur_stats) 4804 { 4805 u16 vsi_num, no_desc, error_cnt; 4806 u32 repc; 4807 4808 if (!ice_is_vsi_valid(hw, vsi_handle)) 4809 return; 4810 4811 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 4812 4813 /* If we haven't loaded stats yet, just clear the current value */ 4814 if (!prev_stat_loaded) { 4815 wr32(hw, GLV_REPC(vsi_num), 0); 4816 return; 4817 } 4818 4819 repc = rd32(hw, GLV_REPC(vsi_num)); 4820 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 4821 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 4822 4823 /* Clear the count by writing to the stats register */ 4824 wr32(hw, GLV_REPC(vsi_num), 0); 4825 4826 cur_stats->rx_no_desc += no_desc; 4827 cur_stats->rx_errors += error_cnt; 4828 } 4829 4830 /** 4831 * ice_sched_query_elem - query element information from HW 4832 * @hw: pointer to the HW struct 4833 * @node_teid: node TEID to be queried 4834 * @buf: buffer to element information 4835 * 4836 * This function queries HW element information 4837 */ 4838 enum ice_status 4839 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4840 struct ice_aqc_txsched_elem_data *buf) 4841 { 4842 u16 buf_size, num_elem_ret = 0; 4843 enum ice_status status; 4844 4845 buf_size = sizeof(*buf); 4846 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 4847 buf->node_teid = CPU_TO_LE32(node_teid); 4848 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4849 NULL); 4850 if (status != ICE_SUCCESS || num_elem_ret != 1) 4851 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4852 return status; 4853 } 4854 4855 /** 4856 * ice_get_fw_mode - returns FW mode 4857 * @hw: pointer to the HW struct 4858 */ 4859 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 4860 { 4861 #define ICE_FW_MODE_DBG_M BIT(0) 4862 #define ICE_FW_MODE_REC_M BIT(1) 4863 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 4864 u32 fw_mode; 4865 4866 /* check the current FW mode */ 4867 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 4868 4869 if (fw_mode & ICE_FW_MODE_DBG_M) 4870 return ICE_FW_MODE_DBG; 4871 else if (fw_mode & ICE_FW_MODE_REC_M) 4872 return ICE_FW_MODE_REC; 4873 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 4874 return ICE_FW_MODE_ROLLBACK; 4875 else 4876 return ICE_FW_MODE_NORMAL; 4877 } 4878 4879 /** 4880 * ice_aq_read_i2c 4881 * @hw: pointer to the hw struct 4882 * @topo_addr: topology address for a device to communicate with 4883 * @bus_addr: 7-bit I2C bus address 4884 * @addr: I2C memory address (I2C offset) with up to 16 bits 4885 * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size, 4886 * bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes) 4887 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 4888 * @cd: pointer to command details structure or NULL 4889 * 4890 * Read I2C (0x06E2) 4891 */ 4892 enum ice_status 4893 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 4894 u16 bus_addr, __le16 addr, u8 params, u8 *data, 4895 struct ice_sq_cd *cd) 4896 { 4897 struct ice_aq_desc desc = { 0 }; 4898 struct ice_aqc_i2c *cmd; 4899 enum ice_status status; 4900 u8 data_size; 4901 4902 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 4903 cmd = &desc.params.read_write_i2c; 4904 4905 if (!data) 4906 return ICE_ERR_PARAM; 4907 4908 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S; 4909 4910 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr); 4911 cmd->topo_addr = topo_addr; 4912 cmd->i2c_params = params; 4913 cmd->i2c_addr = addr; 4914 4915 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4916 if (!status) { 4917 struct ice_aqc_read_i2c_resp *resp; 4918 u8 i; 4919 4920 resp = &desc.params.read_i2c_resp; 4921 for (i = 0; i < data_size; i++) { 4922 *data = resp->i2c_data[i]; 4923 data++; 4924 } 4925 } 4926 4927 return status; 4928 } 4929 4930 /** 4931 * ice_aq_write_i2c 4932 * @hw: pointer to the hw struct 4933 * @topo_addr: topology address for a device to communicate with 4934 * @bus_addr: 7-bit I2C bus address 4935 * @addr: I2C memory address (I2C offset) with up to 16 bits 4936 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 4937 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 4938 * @cd: pointer to command details structure or NULL 4939 * 4940 * Write I2C (0x06E3) 4941 */ 4942 enum ice_status 4943 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 4944 u16 bus_addr, __le16 addr, u8 params, u8 *data, 4945 struct ice_sq_cd *cd) 4946 { 4947 struct ice_aq_desc desc = { 0 }; 4948 struct ice_aqc_i2c *cmd; 4949 u8 i, data_size; 4950 4951 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 4952 cmd = &desc.params.read_write_i2c; 4953 4954 data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S; 4955 4956 /* data_size limited to 4 */ 4957 if (data_size > 4) 4958 return ICE_ERR_PARAM; 4959 4960 cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr); 4961 cmd->topo_addr = topo_addr; 4962 cmd->i2c_params = params; 4963 cmd->i2c_addr = addr; 4964 4965 for (i = 0; i < data_size; i++) { 4966 cmd->i2c_data[i] = *data; 4967 data++; 4968 } 4969 4970 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4971 } 4972 4973 /** 4974 * ice_aq_set_gpio 4975 * @hw: pointer to the hw struct 4976 * @gpio_ctrl_handle: GPIO controller node handle 4977 * @pin_idx: IO Number of the GPIO that needs to be set 4978 * @value: SW provide IO value to set in the LSB 4979 * @cd: pointer to command details structure or NULL 4980 * 4981 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 4982 */ 4983 enum ice_status 4984 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 4985 struct ice_sq_cd *cd) 4986 { 4987 struct ice_aqc_gpio *cmd; 4988 struct ice_aq_desc desc; 4989 4990 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 4991 cmd = &desc.params.read_write_gpio; 4992 cmd->gpio_ctrl_handle = gpio_ctrl_handle; 4993 cmd->gpio_num = pin_idx; 4994 cmd->gpio_val = value ? 1 : 0; 4995 4996 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4997 } 4998 4999 /** 5000 * ice_aq_get_gpio 5001 * @hw: pointer to the hw struct 5002 * @gpio_ctrl_handle: GPIO controller node handle 5003 * @pin_idx: IO Number of the GPIO that needs to be set 5004 * @value: IO value read 5005 * @cd: pointer to command details structure or NULL 5006 * 5007 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5008 * the topology 5009 */ 5010 enum ice_status 5011 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5012 bool *value, struct ice_sq_cd *cd) 5013 { 5014 struct ice_aqc_gpio *cmd; 5015 struct ice_aq_desc desc; 5016 enum ice_status status; 5017 5018 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5019 cmd = &desc.params.read_write_gpio; 5020 cmd->gpio_ctrl_handle = gpio_ctrl_handle; 5021 cmd->gpio_num = pin_idx; 5022 5023 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5024 if (status) 5025 return status; 5026 5027 *value = !!cmd->gpio_val; 5028 return ICE_SUCCESS; 5029 } 5030 5031 /** 5032 * ice_fw_supports_link_override 5033 * @hw: pointer to the hardware structure 5034 * 5035 * Checks if the firmware supports link override 5036 */ 5037 bool ice_fw_supports_link_override(struct ice_hw *hw) 5038 { 5039 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 5040 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 5041 return true; 5042 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 5043 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 5044 return true; 5045 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 5046 return true; 5047 } 5048 5049 return false; 5050 } 5051 5052 /** 5053 * ice_get_link_default_override 5054 * @ldo: pointer to the link default override struct 5055 * @pi: pointer to the port info struct 5056 * 5057 * Gets the link default override for a port 5058 */ 5059 enum ice_status 5060 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5061 struct ice_port_info *pi) 5062 { 5063 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5064 struct ice_hw *hw = pi->hw; 5065 enum ice_status status; 5066 5067 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5068 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5069 if (status) { 5070 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5071 return status; 5072 } 5073 5074 /* Each port has its own config; calculate for our port */ 5075 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5076 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5077 5078 /* link options first */ 5079 status = ice_read_sr_word(hw, tlv_start, &buf); 5080 if (status) { 5081 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5082 return status; 5083 } 5084 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5085 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5086 ICE_LINK_OVERRIDE_PHY_CFG_S; 5087 5088 /* link PHY config */ 5089 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5090 status = ice_read_sr_word(hw, offset, &buf); 5091 if (status) { 5092 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5093 return status; 5094 } 5095 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5096 5097 /* PHY types low */ 5098 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5099 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5100 status = ice_read_sr_word(hw, (offset + i), &buf); 5101 if (status) { 5102 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5103 return status; 5104 } 5105 /* shift 16 bits at a time to fill 64 bits */ 5106 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5107 } 5108 5109 /* PHY types high */ 5110 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5111 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5112 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5113 status = ice_read_sr_word(hw, (offset + i), &buf); 5114 if (status) { 5115 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5116 return status; 5117 } 5118 /* shift 16 bits at a time to fill 64 bits */ 5119 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5120 } 5121 5122 return status; 5123 } 5124 5125 /** 5126 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5127 * @caps: get PHY capability data 5128 */ 5129 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5130 { 5131 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5132 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5133 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5134 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5135 return true; 5136 5137 return false; 5138 } 5139 5140 /** 5141 * ice_aq_set_lldp_mib - Set the LLDP MIB 5142 * @hw: pointer to the HW struct 5143 * @mib_type: Local, Remote or both Local and Remote MIBs 5144 * @buf: pointer to the caller-supplied buffer to store the MIB block 5145 * @buf_size: size of the buffer (in bytes) 5146 * @cd: pointer to command details structure or NULL 5147 * 5148 * Set the LLDP MIB. (0x0A08) 5149 */ 5150 enum ice_status 5151 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5152 struct ice_sq_cd *cd) 5153 { 5154 struct ice_aqc_lldp_set_local_mib *cmd; 5155 struct ice_aq_desc desc; 5156 5157 cmd = &desc.params.lldp_set_mib; 5158 5159 if (buf_size == 0 || !buf) 5160 return ICE_ERR_PARAM; 5161 5162 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5163 5164 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD); 5165 desc.datalen = CPU_TO_LE16(buf_size); 5166 5167 cmd->type = mib_type; 5168 cmd->length = CPU_TO_LE16(buf_size); 5169 5170 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5171 } 5172 5173 /** 5174 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5175 * @hw: pointer to HW struct 5176 */ 5177 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5178 { 5179 if (hw->mac_type != ICE_MAC_E810) 5180 return false; 5181 5182 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 5183 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 5184 return true; 5185 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 5186 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 5187 return true; 5188 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 5189 return true; 5190 } 5191 return false; 5192 } 5193 5194 /** 5195 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5196 * @hw: pointer to HW struct 5197 * @vsi_num: absolute HW index for VSI 5198 * @add: boolean for if adding or removing a filter 5199 */ 5200 enum ice_status 5201 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5202 { 5203 struct ice_aqc_lldp_filter_ctrl *cmd; 5204 struct ice_aq_desc desc; 5205 5206 cmd = &desc.params.lldp_filter_ctrl; 5207 5208 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5209 5210 if (add) 5211 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5212 else 5213 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5214 5215 cmd->vsi_num = CPU_TO_LE16(vsi_num); 5216 5217 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5218 } 5219 5220 /** 5221 * ice_fw_supports_report_dflt_cfg 5222 * @hw: pointer to the hardware structure 5223 * 5224 * Checks if the firmware supports report default configuration 5225 */ 5226 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5227 { 5228 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5229 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 5230 return true; 5231 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 5232 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 5233 return true; 5234 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5235 return true; 5236 } 5237 return false; 5238 } 5239