1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 300 13 14 /** 15 * ice_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the MAC type of the adapter based on the 19 * vendor ID and device ID stored in the HW structure. 20 */ 21 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 22 { 23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 24 25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 26 return ICE_ERR_DEVICE_NOT_SUPPORTED; 27 28 switch (hw->device_id) { 29 case ICE_DEV_ID_E810C_BACKPLANE: 30 case ICE_DEV_ID_E810C_QSFP: 31 case ICE_DEV_ID_E810C_SFP: 32 case ICE_DEV_ID_E810_XXV_BACKPLANE: 33 case ICE_DEV_ID_E810_XXV_QSFP: 34 case ICE_DEV_ID_E810_XXV_SFP: 35 hw->mac_type = ICE_MAC_E810; 36 break; 37 case ICE_DEV_ID_E822C_10G_BASE_T: 38 case ICE_DEV_ID_E822C_BACKPLANE: 39 case ICE_DEV_ID_E822C_QSFP: 40 case ICE_DEV_ID_E822C_SFP: 41 case ICE_DEV_ID_E822C_SGMII: 42 case ICE_DEV_ID_E822L_10G_BASE_T: 43 case ICE_DEV_ID_E822L_BACKPLANE: 44 case ICE_DEV_ID_E822L_SFP: 45 case ICE_DEV_ID_E822L_SGMII: 46 case ICE_DEV_ID_E823L_10G_BASE_T: 47 case ICE_DEV_ID_E823L_1GBE: 48 case ICE_DEV_ID_E823L_BACKPLANE: 49 case ICE_DEV_ID_E823L_QSFP: 50 case ICE_DEV_ID_E823L_SFP: 51 hw->mac_type = ICE_MAC_GENERIC; 52 break; 53 default: 54 hw->mac_type = ICE_MAC_UNKNOWN; 55 break; 56 } 57 58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 59 return ICE_SUCCESS; 60 } 61 62 /** 63 * ice_clear_pf_cfg - Clear PF configuration 64 * @hw: pointer to the hardware structure 65 * 66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 67 * configuration, flow director filters, etc.). 68 */ 69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 70 { 71 struct ice_aq_desc desc; 72 73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 74 75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 76 } 77 78 /** 79 * ice_aq_manage_mac_read - manage MAC address read command 80 * @hw: pointer to the HW struct 81 * @buf: a virtual buffer to hold the manage MAC read response 82 * @buf_size: Size of the virtual buffer 83 * @cd: pointer to command details structure or NULL 84 * 85 * This function is used to return per PF station MAC address (0x0107). 86 * NOTE: Upon successful completion of this command, MAC address information 87 * is returned in user specified buffer. Please interpret user specified 88 * buffer as "manage_mac_read" response. 89 * Response such as various MAC addresses are stored in HW struct (port.mac) 90 * ice_discover_dev_caps is expected to be called before this function is 91 * called. 92 */ 93 static enum ice_status 94 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 95 struct ice_sq_cd *cd) 96 { 97 struct ice_aqc_manage_mac_read_resp *resp; 98 struct ice_aqc_manage_mac_read *cmd; 99 struct ice_aq_desc desc; 100 enum ice_status status; 101 u16 flags; 102 u8 i; 103 104 cmd = &desc.params.mac_read; 105 106 if (buf_size < sizeof(*resp)) 107 return ICE_ERR_BUF_TOO_SHORT; 108 109 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 110 111 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 112 if (status) 113 return status; 114 115 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 116 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 117 118 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 119 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 120 return ICE_ERR_CFG; 121 } 122 123 /* A single port can report up to two (LAN and WoL) addresses */ 124 for (i = 0; i < cmd->num_addr; i++) 125 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 126 ice_memcpy(hw->port_info->mac.lan_addr, 127 resp[i].mac_addr, ETH_ALEN, 128 ICE_DMA_TO_NONDMA); 129 ice_memcpy(hw->port_info->mac.perm_addr, 130 resp[i].mac_addr, 131 ETH_ALEN, ICE_DMA_TO_NONDMA); 132 break; 133 } 134 return ICE_SUCCESS; 135 } 136 137 /** 138 * ice_aq_get_phy_caps - returns PHY capabilities 139 * @pi: port information structure 140 * @qual_mods: report qualified modules 141 * @report_mode: report mode capabilities 142 * @pcaps: structure for PHY capabilities to be filled 143 * @cd: pointer to command details structure or NULL 144 * 145 * Returns the various PHY capabilities supported on the Port (0x0600) 146 */ 147 enum ice_status 148 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 149 struct ice_aqc_get_phy_caps_data *pcaps, 150 struct ice_sq_cd *cd) 151 { 152 struct ice_aqc_get_phy_caps *cmd; 153 u16 pcaps_size = sizeof(*pcaps); 154 struct ice_aq_desc desc; 155 enum ice_status status; 156 struct ice_hw *hw; 157 158 cmd = &desc.params.get_phy; 159 160 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 161 return ICE_ERR_PARAM; 162 hw = pi->hw; 163 164 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 165 !ice_fw_supports_report_dflt_cfg(hw)) 166 return ICE_ERR_PARAM; 167 168 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 169 170 if (qual_mods) 171 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 172 173 cmd->param0 |= CPU_TO_LE16(report_mode); 174 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 175 176 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 177 report_mode); 178 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 179 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); 180 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 181 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); 182 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 183 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 184 pcaps->low_power_ctrl_an); 185 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 186 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 187 pcaps->eeer_value); 188 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 189 pcaps->link_fec_options); 190 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 191 pcaps->module_compliance_enforcement); 192 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 193 pcaps->extended_compliance_code); 194 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 195 pcaps->module_type[0]); 196 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 197 pcaps->module_type[1]); 198 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 199 pcaps->module_type[2]); 200 201 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 202 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 203 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 204 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 205 sizeof(pi->phy.link_info.module_type), 206 ICE_NONDMA_TO_NONDMA); 207 } 208 209 return status; 210 } 211 212 /** 213 * ice_aq_get_link_topo_handle - get link topology node return status 214 * @pi: port information structure 215 * @node_type: requested node type 216 * @cd: pointer to command details structure or NULL 217 * 218 * Get link topology node return status for specified node type (0x06E0) 219 * 220 * Node type cage can be used to determine if cage is present. If AQC 221 * returns error (ENOENT), then no cage present. If no cage present, then 222 * connection type is backplane or BASE-T. 223 */ 224 static enum ice_status 225 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 226 struct ice_sq_cd *cd) 227 { 228 struct ice_aqc_get_link_topo *cmd; 229 struct ice_aq_desc desc; 230 231 cmd = &desc.params.get_link_topo; 232 233 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 234 235 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 236 ICE_AQC_LINK_TOPO_NODE_CTX_S); 237 238 /* set node type */ 239 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 240 241 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 242 } 243 244 /** 245 * ice_is_media_cage_present 246 * @pi: port information structure 247 * 248 * Returns true if media cage is present, else false. If no cage, then 249 * media type is backplane or BASE-T. 250 */ 251 static bool ice_is_media_cage_present(struct ice_port_info *pi) 252 { 253 /* Node type cage can be used to determine if cage is present. If AQC 254 * returns error (ENOENT), then no cage present. If no cage present then 255 * connection type is backplane or BASE-T. 256 */ 257 return !ice_aq_get_link_topo_handle(pi, 258 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 259 NULL); 260 } 261 262 /** 263 * ice_get_media_type - Gets media type 264 * @pi: port information structure 265 */ 266 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 267 { 268 struct ice_link_status *hw_link_info; 269 270 if (!pi) 271 return ICE_MEDIA_UNKNOWN; 272 273 hw_link_info = &pi->phy.link_info; 274 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 275 /* If more than one media type is selected, report unknown */ 276 return ICE_MEDIA_UNKNOWN; 277 278 if (hw_link_info->phy_type_low) { 279 /* 1G SGMII is a special case where some DA cable PHYs 280 * may show this as an option when it really shouldn't 281 * be since SGMII is meant to be between a MAC and a PHY 282 * in a backplane. Try to detect this case and handle it 283 */ 284 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 285 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 286 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 287 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 288 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 289 return ICE_MEDIA_DA; 290 291 switch (hw_link_info->phy_type_low) { 292 case ICE_PHY_TYPE_LOW_1000BASE_SX: 293 case ICE_PHY_TYPE_LOW_1000BASE_LX: 294 case ICE_PHY_TYPE_LOW_10GBASE_SR: 295 case ICE_PHY_TYPE_LOW_10GBASE_LR: 296 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 297 case ICE_PHY_TYPE_LOW_25GBASE_SR: 298 case ICE_PHY_TYPE_LOW_25GBASE_LR: 299 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 300 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 301 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 302 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 303 case ICE_PHY_TYPE_LOW_50GBASE_SR: 304 case ICE_PHY_TYPE_LOW_50GBASE_FR: 305 case ICE_PHY_TYPE_LOW_50GBASE_LR: 306 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 307 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 308 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 309 case ICE_PHY_TYPE_LOW_100GBASE_DR: 310 return ICE_MEDIA_FIBER; 311 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 312 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 313 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 314 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 315 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 316 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 317 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 318 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 319 return ICE_MEDIA_FIBER; 320 case ICE_PHY_TYPE_LOW_100BASE_TX: 321 case ICE_PHY_TYPE_LOW_1000BASE_T: 322 case ICE_PHY_TYPE_LOW_2500BASE_T: 323 case ICE_PHY_TYPE_LOW_5GBASE_T: 324 case ICE_PHY_TYPE_LOW_10GBASE_T: 325 case ICE_PHY_TYPE_LOW_25GBASE_T: 326 return ICE_MEDIA_BASET; 327 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 328 case ICE_PHY_TYPE_LOW_25GBASE_CR: 329 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 330 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 331 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 332 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 333 case ICE_PHY_TYPE_LOW_50GBASE_CP: 334 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 335 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 336 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 337 return ICE_MEDIA_DA; 338 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 339 case ICE_PHY_TYPE_LOW_40G_XLAUI: 340 case ICE_PHY_TYPE_LOW_50G_LAUI2: 341 case ICE_PHY_TYPE_LOW_50G_AUI2: 342 case ICE_PHY_TYPE_LOW_50G_AUI1: 343 case ICE_PHY_TYPE_LOW_100G_AUI4: 344 case ICE_PHY_TYPE_LOW_100G_CAUI4: 345 if (ice_is_media_cage_present(pi)) 346 return ICE_MEDIA_AUI; 347 /* fall-through */ 348 case ICE_PHY_TYPE_LOW_1000BASE_KX: 349 case ICE_PHY_TYPE_LOW_2500BASE_KX: 350 case ICE_PHY_TYPE_LOW_2500BASE_X: 351 case ICE_PHY_TYPE_LOW_5GBASE_KR: 352 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 353 case ICE_PHY_TYPE_LOW_25GBASE_KR: 354 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 355 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 356 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 357 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 358 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 359 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 360 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 361 return ICE_MEDIA_BACKPLANE; 362 } 363 } else { 364 switch (hw_link_info->phy_type_high) { 365 case ICE_PHY_TYPE_HIGH_100G_AUI2: 366 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 367 if (ice_is_media_cage_present(pi)) 368 return ICE_MEDIA_AUI; 369 /* fall-through */ 370 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 371 return ICE_MEDIA_BACKPLANE; 372 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 373 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 374 return ICE_MEDIA_FIBER; 375 } 376 } 377 return ICE_MEDIA_UNKNOWN; 378 } 379 380 /** 381 * ice_aq_get_link_info 382 * @pi: port information structure 383 * @ena_lse: enable/disable LinkStatusEvent reporting 384 * @link: pointer to link status structure - optional 385 * @cd: pointer to command details structure or NULL 386 * 387 * Get Link Status (0x607). Returns the link status of the adapter. 388 */ 389 enum ice_status 390 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 391 struct ice_link_status *link, struct ice_sq_cd *cd) 392 { 393 struct ice_aqc_get_link_status_data link_data = { 0 }; 394 struct ice_aqc_get_link_status *resp; 395 struct ice_link_status *li_old, *li; 396 enum ice_media_type *hw_media_type; 397 struct ice_fc_info *hw_fc_info; 398 bool tx_pause, rx_pause; 399 struct ice_aq_desc desc; 400 enum ice_status status; 401 struct ice_hw *hw; 402 u16 cmd_flags; 403 404 if (!pi) 405 return ICE_ERR_PARAM; 406 hw = pi->hw; 407 li_old = &pi->phy.link_info_old; 408 hw_media_type = &pi->phy.media_type; 409 li = &pi->phy.link_info; 410 hw_fc_info = &pi->fc; 411 412 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 413 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 414 resp = &desc.params.get_link_status; 415 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 416 resp->lport_num = pi->lport; 417 418 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 419 420 if (status != ICE_SUCCESS) 421 return status; 422 423 /* save off old link status information */ 424 *li_old = *li; 425 426 /* update current link status information */ 427 li->link_speed = LE16_TO_CPU(link_data.link_speed); 428 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 429 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 430 *hw_media_type = ice_get_media_type(pi); 431 li->link_info = link_data.link_info; 432 li->an_info = link_data.an_info; 433 li->ext_info = link_data.ext_info; 434 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 435 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 436 li->topo_media_conflict = link_data.topo_media_conflict; 437 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 438 ICE_AQ_CFG_PACING_TYPE_M); 439 440 /* update fc info */ 441 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 442 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 443 if (tx_pause && rx_pause) 444 hw_fc_info->current_mode = ICE_FC_FULL; 445 else if (tx_pause) 446 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 447 else if (rx_pause) 448 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 449 else 450 hw_fc_info->current_mode = ICE_FC_NONE; 451 452 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 453 454 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 455 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 456 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 457 (unsigned long long)li->phy_type_low); 458 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 459 (unsigned long long)li->phy_type_high); 460 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 461 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 462 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 463 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 464 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 465 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 466 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 467 li->max_frame_size); 468 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 469 470 /* save link status information */ 471 if (link) 472 *link = *li; 473 474 /* flag cleared so calling functions don't call AQ again */ 475 pi->phy.get_link_info = false; 476 477 return ICE_SUCCESS; 478 } 479 480 /** 481 * ice_fill_tx_timer_and_fc_thresh 482 * @hw: pointer to the HW struct 483 * @cmd: pointer to MAC cfg structure 484 * 485 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 486 * descriptor 487 */ 488 static void 489 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 490 struct ice_aqc_set_mac_cfg *cmd) 491 { 492 u16 fc_thres_val, tx_timer_val; 493 u32 val; 494 495 /* We read back the transmit timer and fc threshold value of 496 * LFC. Thus, we will use index = 497 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 498 * 499 * Also, because we are opearating on transmit timer and fc 500 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 501 */ 502 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 503 504 /* Retrieve the transmit timer */ 505 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 506 tx_timer_val = val & 507 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 508 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 509 510 /* Retrieve the fc threshold */ 511 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 512 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 513 514 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 515 } 516 517 /** 518 * ice_aq_set_mac_cfg 519 * @hw: pointer to the HW struct 520 * @max_frame_size: Maximum Frame Size to be supported 521 * @cd: pointer to command details structure or NULL 522 * 523 * Set MAC configuration (0x0603) 524 */ 525 enum ice_status 526 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 527 { 528 struct ice_aqc_set_mac_cfg *cmd; 529 struct ice_aq_desc desc; 530 531 cmd = &desc.params.set_mac_cfg; 532 533 if (max_frame_size == 0) 534 return ICE_ERR_PARAM; 535 536 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 537 538 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 539 540 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 541 542 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 543 } 544 545 /** 546 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 547 * @hw: pointer to the HW struct 548 */ 549 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 550 { 551 struct ice_switch_info *sw; 552 enum ice_status status; 553 554 hw->switch_info = (struct ice_switch_info *) 555 ice_malloc(hw, sizeof(*hw->switch_info)); 556 557 sw = hw->switch_info; 558 559 if (!sw) 560 return ICE_ERR_NO_MEMORY; 561 562 INIT_LIST_HEAD(&sw->vsi_list_map_head); 563 sw->prof_res_bm_init = 0; 564 565 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 566 if (status) { 567 ice_free(hw, hw->switch_info); 568 return status; 569 } 570 return ICE_SUCCESS; 571 } 572 573 /** 574 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 575 * @hw: pointer to the HW struct 576 * @sw: pointer to switch info struct for which function clears filters 577 */ 578 static void 579 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 580 { 581 struct ice_vsi_list_map_info *v_pos_map; 582 struct ice_vsi_list_map_info *v_tmp_map; 583 struct ice_sw_recipe *recps; 584 u8 i; 585 586 if (!sw) 587 return; 588 589 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 590 ice_vsi_list_map_info, list_entry) { 591 LIST_DEL(&v_pos_map->list_entry); 592 ice_free(hw, v_pos_map); 593 } 594 recps = sw->recp_list; 595 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 596 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 597 598 recps[i].root_rid = i; 599 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 600 &recps[i].rg_list, ice_recp_grp_entry, 601 l_entry) { 602 LIST_DEL(&rg_entry->l_entry); 603 ice_free(hw, rg_entry); 604 } 605 606 if (recps[i].adv_rule) { 607 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 608 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 609 610 ice_destroy_lock(&recps[i].filt_rule_lock); 611 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 612 &recps[i].filt_rules, 613 ice_adv_fltr_mgmt_list_entry, 614 list_entry) { 615 LIST_DEL(&lst_itr->list_entry); 616 ice_free(hw, lst_itr->lkups); 617 ice_free(hw, lst_itr); 618 } 619 } else { 620 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 621 622 ice_destroy_lock(&recps[i].filt_rule_lock); 623 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 624 &recps[i].filt_rules, 625 ice_fltr_mgmt_list_entry, 626 list_entry) { 627 LIST_DEL(&lst_itr->list_entry); 628 ice_free(hw, lst_itr); 629 } 630 } 631 if (recps[i].root_buf) 632 ice_free(hw, recps[i].root_buf); 633 } 634 ice_rm_sw_replay_rule_info(hw, sw); 635 ice_free(hw, sw->recp_list); 636 ice_free(hw, sw); 637 } 638 639 /** 640 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks 641 * @hw: pointer to the HW struct 642 */ 643 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 644 { 645 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 646 } 647 648 /** 649 * ice_get_itr_intrl_gran 650 * @hw: pointer to the HW struct 651 * 652 * Determines the ITR/INTRL granularities based on the maximum aggregate 653 * bandwidth according to the device's configuration during power-on. 654 */ 655 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 656 { 657 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 658 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 659 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 660 661 switch (max_agg_bw) { 662 case ICE_MAX_AGG_BW_200G: 663 case ICE_MAX_AGG_BW_100G: 664 case ICE_MAX_AGG_BW_50G: 665 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 666 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 667 break; 668 case ICE_MAX_AGG_BW_25G: 669 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 670 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 671 break; 672 } 673 } 674 675 /** 676 * ice_print_rollback_msg - print FW rollback message 677 * @hw: pointer to the hardware structure 678 */ 679 void ice_print_rollback_msg(struct ice_hw *hw) 680 { 681 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 682 struct ice_orom_info *orom; 683 struct ice_nvm_info *nvm; 684 685 orom = &hw->flash.orom; 686 nvm = &hw->flash.nvm; 687 688 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 689 nvm->major, nvm->minor, nvm->eetrack, orom->major, 690 orom->build, orom->patch); 691 ice_warn(hw, 692 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 693 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 694 } 695 696 /** 697 * ice_init_hw - main hardware initialization routine 698 * @hw: pointer to the hardware structure 699 */ 700 enum ice_status ice_init_hw(struct ice_hw *hw) 701 { 702 struct ice_aqc_get_phy_caps_data *pcaps; 703 enum ice_status status; 704 u16 mac_buf_len; 705 void *mac_buf; 706 707 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 708 709 /* Set MAC type based on DeviceID */ 710 status = ice_set_mac_type(hw); 711 if (status) 712 return status; 713 714 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 715 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 716 PF_FUNC_RID_FUNCTION_NUMBER_S; 717 718 status = ice_reset(hw, ICE_RESET_PFR); 719 if (status) 720 return status; 721 722 ice_get_itr_intrl_gran(hw); 723 724 status = ice_create_all_ctrlq(hw); 725 if (status) 726 goto err_unroll_cqinit; 727 728 status = ice_init_nvm(hw); 729 if (status) 730 goto err_unroll_cqinit; 731 732 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 733 ice_print_rollback_msg(hw); 734 735 status = ice_clear_pf_cfg(hw); 736 if (status) 737 goto err_unroll_cqinit; 738 739 /* Set bit to enable Flow Director filters */ 740 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 741 INIT_LIST_HEAD(&hw->fdir_list_head); 742 743 ice_clear_pxe_mode(hw); 744 745 status = ice_get_caps(hw); 746 if (status) 747 goto err_unroll_cqinit; 748 749 hw->port_info = (struct ice_port_info *) 750 ice_malloc(hw, sizeof(*hw->port_info)); 751 if (!hw->port_info) { 752 status = ICE_ERR_NO_MEMORY; 753 goto err_unroll_cqinit; 754 } 755 756 /* set the back pointer to HW */ 757 hw->port_info->hw = hw; 758 759 /* Initialize port_info struct with switch configuration data */ 760 status = ice_get_initial_sw_cfg(hw); 761 if (status) 762 goto err_unroll_alloc; 763 764 hw->evb_veb = true; 765 /* Query the allocated resources for Tx scheduler */ 766 status = ice_sched_query_res_alloc(hw); 767 if (status) { 768 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 769 goto err_unroll_alloc; 770 } 771 ice_sched_get_psm_clk_freq(hw); 772 773 /* Initialize port_info struct with scheduler data */ 774 status = ice_sched_init_port(hw->port_info); 775 if (status) 776 goto err_unroll_sched; 777 pcaps = (struct ice_aqc_get_phy_caps_data *) 778 ice_malloc(hw, sizeof(*pcaps)); 779 if (!pcaps) { 780 status = ICE_ERR_NO_MEMORY; 781 goto err_unroll_sched; 782 } 783 784 /* Initialize port_info struct with PHY capabilities */ 785 status = ice_aq_get_phy_caps(hw->port_info, false, 786 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); 787 ice_free(hw, pcaps); 788 if (status) 789 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", 790 status); 791 792 /* Initialize port_info struct with link information */ 793 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 794 if (status) 795 goto err_unroll_sched; 796 /* need a valid SW entry point to build a Tx tree */ 797 if (!hw->sw_entry_point_layer) { 798 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 799 status = ICE_ERR_CFG; 800 goto err_unroll_sched; 801 } 802 INIT_LIST_HEAD(&hw->agg_list); 803 /* Initialize max burst size */ 804 if (!hw->max_burst_size) 805 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 806 status = ice_init_fltr_mgmt_struct(hw); 807 if (status) 808 goto err_unroll_sched; 809 810 /* Get MAC information */ 811 /* A single port can report up to two (LAN and WoL) addresses */ 812 mac_buf = ice_calloc(hw, 2, 813 sizeof(struct ice_aqc_manage_mac_read_resp)); 814 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 815 816 if (!mac_buf) { 817 status = ICE_ERR_NO_MEMORY; 818 goto err_unroll_fltr_mgmt_struct; 819 } 820 821 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 822 ice_free(hw, mac_buf); 823 824 if (status) 825 goto err_unroll_fltr_mgmt_struct; 826 /* enable jumbo frame support at MAC level */ 827 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 828 if (status) 829 goto err_unroll_fltr_mgmt_struct; 830 /* Obtain counter base index which would be used by flow director */ 831 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 832 if (status) 833 goto err_unroll_fltr_mgmt_struct; 834 status = ice_init_hw_tbls(hw); 835 if (status) 836 goto err_unroll_fltr_mgmt_struct; 837 ice_init_lock(&hw->tnl_lock); 838 839 return ICE_SUCCESS; 840 841 err_unroll_fltr_mgmt_struct: 842 ice_cleanup_fltr_mgmt_struct(hw); 843 err_unroll_sched: 844 ice_sched_cleanup_all(hw); 845 err_unroll_alloc: 846 ice_free(hw, hw->port_info); 847 hw->port_info = NULL; 848 err_unroll_cqinit: 849 ice_destroy_all_ctrlq(hw); 850 return status; 851 } 852 853 /** 854 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 855 * @hw: pointer to the hardware structure 856 * 857 * This should be called only during nominal operation, not as a result of 858 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 859 * applicable initializations if it fails for any reason. 860 */ 861 void ice_deinit_hw(struct ice_hw *hw) 862 { 863 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 864 ice_cleanup_fltr_mgmt_struct(hw); 865 866 ice_sched_cleanup_all(hw); 867 ice_sched_clear_agg(hw); 868 ice_free_seg(hw); 869 ice_free_hw_tbls(hw); 870 ice_destroy_lock(&hw->tnl_lock); 871 872 if (hw->port_info) { 873 ice_free(hw, hw->port_info); 874 hw->port_info = NULL; 875 } 876 877 ice_destroy_all_ctrlq(hw); 878 879 /* Clear VSI contexts if not already cleared */ 880 ice_clear_all_vsi_ctx(hw); 881 } 882 883 /** 884 * ice_check_reset - Check to see if a global reset is complete 885 * @hw: pointer to the hardware structure 886 */ 887 enum ice_status ice_check_reset(struct ice_hw *hw) 888 { 889 u32 cnt, reg = 0, grst_timeout, uld_mask; 890 891 /* Poll for Device Active state in case a recent CORER, GLOBR, 892 * or EMPR has occurred. The grst delay value is in 100ms units. 893 * Add 1sec for outstanding AQ commands that can take a long time. 894 */ 895 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 896 GLGEN_RSTCTL_GRSTDEL_S) + 10; 897 898 for (cnt = 0; cnt < grst_timeout; cnt++) { 899 ice_msec_delay(100, true); 900 reg = rd32(hw, GLGEN_RSTAT); 901 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 902 break; 903 } 904 905 if (cnt == grst_timeout) { 906 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 907 return ICE_ERR_RESET_FAILED; 908 } 909 910 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 911 GLNVM_ULD_PCIER_DONE_1_M |\ 912 GLNVM_ULD_CORER_DONE_M |\ 913 GLNVM_ULD_GLOBR_DONE_M |\ 914 GLNVM_ULD_POR_DONE_M |\ 915 GLNVM_ULD_POR_DONE_1_M |\ 916 GLNVM_ULD_PCIER_DONE_2_M) 917 918 uld_mask = ICE_RESET_DONE_MASK; 919 920 /* Device is Active; check Global Reset processes are done */ 921 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 922 reg = rd32(hw, GLNVM_ULD) & uld_mask; 923 if (reg == uld_mask) { 924 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 925 break; 926 } 927 ice_msec_delay(10, true); 928 } 929 930 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 931 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 932 reg); 933 return ICE_ERR_RESET_FAILED; 934 } 935 936 return ICE_SUCCESS; 937 } 938 939 /** 940 * ice_pf_reset - Reset the PF 941 * @hw: pointer to the hardware structure 942 * 943 * If a global reset has been triggered, this function checks 944 * for its completion and then issues the PF reset 945 */ 946 static enum ice_status ice_pf_reset(struct ice_hw *hw) 947 { 948 u32 cnt, reg; 949 950 /* If at function entry a global reset was already in progress, i.e. 951 * state is not 'device active' or any of the reset done bits are not 952 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 953 * global reset is done. 954 */ 955 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 956 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 957 /* poll on global reset currently in progress until done */ 958 if (ice_check_reset(hw)) 959 return ICE_ERR_RESET_FAILED; 960 961 return ICE_SUCCESS; 962 } 963 964 /* Reset the PF */ 965 reg = rd32(hw, PFGEN_CTRL); 966 967 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 968 969 /* Wait for the PFR to complete. The wait time is the global config lock 970 * timeout plus the PFR timeout which will account for a possible reset 971 * that is occurring during a download package operation. 972 */ 973 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 974 ICE_PF_RESET_WAIT_COUNT; cnt++) { 975 reg = rd32(hw, PFGEN_CTRL); 976 if (!(reg & PFGEN_CTRL_PFSWR_M)) 977 break; 978 979 ice_msec_delay(1, true); 980 } 981 982 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 983 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 984 return ICE_ERR_RESET_FAILED; 985 } 986 987 return ICE_SUCCESS; 988 } 989 990 /** 991 * ice_reset - Perform different types of reset 992 * @hw: pointer to the hardware structure 993 * @req: reset request 994 * 995 * This function triggers a reset as specified by the req parameter. 996 * 997 * Note: 998 * If anything other than a PF reset is triggered, PXE mode is restored. 999 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1000 * interface has been restored in the rebuild flow. 1001 */ 1002 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1003 { 1004 u32 val = 0; 1005 1006 switch (req) { 1007 case ICE_RESET_PFR: 1008 return ice_pf_reset(hw); 1009 case ICE_RESET_CORER: 1010 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1011 val = GLGEN_RTRIG_CORER_M; 1012 break; 1013 case ICE_RESET_GLOBR: 1014 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1015 val = GLGEN_RTRIG_GLOBR_M; 1016 break; 1017 default: 1018 return ICE_ERR_PARAM; 1019 } 1020 1021 val |= rd32(hw, GLGEN_RTRIG); 1022 wr32(hw, GLGEN_RTRIG, val); 1023 ice_flush(hw); 1024 1025 /* wait for the FW to be ready */ 1026 return ice_check_reset(hw); 1027 } 1028 1029 /** 1030 * ice_copy_rxq_ctx_to_hw 1031 * @hw: pointer to the hardware structure 1032 * @ice_rxq_ctx: pointer to the rxq context 1033 * @rxq_index: the index of the Rx queue 1034 * 1035 * Copies rxq context from dense structure to HW register space 1036 */ 1037 static enum ice_status 1038 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1039 { 1040 u8 i; 1041 1042 if (!ice_rxq_ctx) 1043 return ICE_ERR_BAD_PTR; 1044 1045 if (rxq_index > QRX_CTRL_MAX_INDEX) 1046 return ICE_ERR_PARAM; 1047 1048 /* Copy each dword separately to HW */ 1049 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1050 wr32(hw, QRX_CONTEXT(i, rxq_index), 1051 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1052 1053 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1054 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1055 } 1056 1057 return ICE_SUCCESS; 1058 } 1059 1060 /* LAN Rx Queue Context */ 1061 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1062 /* Field Width LSB */ 1063 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1064 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1065 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1066 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1067 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1068 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1069 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1070 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1071 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1072 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1073 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1074 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1075 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1076 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1077 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1078 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1079 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1080 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1081 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1082 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1083 { 0 } 1084 }; 1085 1086 /** 1087 * ice_write_rxq_ctx 1088 * @hw: pointer to the hardware structure 1089 * @rlan_ctx: pointer to the rxq context 1090 * @rxq_index: the index of the Rx queue 1091 * 1092 * Converts rxq context from sparse to dense structure and then writes 1093 * it to HW register space and enables the hardware to prefetch descriptors 1094 * instead of only fetching them on demand 1095 */ 1096 enum ice_status 1097 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1098 u32 rxq_index) 1099 { 1100 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1101 1102 if (!rlan_ctx) 1103 return ICE_ERR_BAD_PTR; 1104 1105 rlan_ctx->prefena = 1; 1106 1107 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1108 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1109 } 1110 1111 /** 1112 * ice_clear_rxq_ctx 1113 * @hw: pointer to the hardware structure 1114 * @rxq_index: the index of the Rx queue to clear 1115 * 1116 * Clears rxq context in HW register space 1117 */ 1118 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1119 { 1120 u8 i; 1121 1122 if (rxq_index > QRX_CTRL_MAX_INDEX) 1123 return ICE_ERR_PARAM; 1124 1125 /* Clear each dword register separately */ 1126 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1127 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1128 1129 return ICE_SUCCESS; 1130 } 1131 1132 /* LAN Tx Queue Context */ 1133 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1134 /* Field Width LSB */ 1135 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1136 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1137 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1138 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1139 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1140 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1141 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1142 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1143 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1144 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1145 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1146 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1147 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1148 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1149 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1150 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1151 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1152 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1153 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1154 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1155 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1156 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1157 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1158 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1159 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1160 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1161 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1162 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1163 { 0 } 1164 }; 1165 1166 /** 1167 * ice_copy_tx_cmpltnq_ctx_to_hw 1168 * @hw: pointer to the hardware structure 1169 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1170 * @tx_cmpltnq_index: the index of the completion queue 1171 * 1172 * Copies Tx completion queue context from dense structure to HW register space 1173 */ 1174 static enum ice_status 1175 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1176 u32 tx_cmpltnq_index) 1177 { 1178 u8 i; 1179 1180 if (!ice_tx_cmpltnq_ctx) 1181 return ICE_ERR_BAD_PTR; 1182 1183 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1184 return ICE_ERR_PARAM; 1185 1186 /* Copy each dword separately to HW */ 1187 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1188 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1189 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1190 1191 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1192 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1193 } 1194 1195 return ICE_SUCCESS; 1196 } 1197 1198 /* LAN Tx Completion Queue Context */ 1199 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1200 /* Field Width LSB */ 1201 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1202 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1203 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1204 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1205 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1206 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1207 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1208 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1209 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1210 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1211 { 0 } 1212 }; 1213 1214 /** 1215 * ice_write_tx_cmpltnq_ctx 1216 * @hw: pointer to the hardware structure 1217 * @tx_cmpltnq_ctx: pointer to the completion queue context 1218 * @tx_cmpltnq_index: the index of the completion queue 1219 * 1220 * Converts completion queue context from sparse to dense structure and then 1221 * writes it to HW register space 1222 */ 1223 enum ice_status 1224 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1225 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1226 u32 tx_cmpltnq_index) 1227 { 1228 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1229 1230 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1231 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1232 } 1233 1234 /** 1235 * ice_clear_tx_cmpltnq_ctx 1236 * @hw: pointer to the hardware structure 1237 * @tx_cmpltnq_index: the index of the completion queue to clear 1238 * 1239 * Clears Tx completion queue context in HW register space 1240 */ 1241 enum ice_status 1242 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1243 { 1244 u8 i; 1245 1246 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1247 return ICE_ERR_PARAM; 1248 1249 /* Clear each dword register separately */ 1250 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1251 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1252 1253 return ICE_SUCCESS; 1254 } 1255 1256 /** 1257 * ice_copy_tx_drbell_q_ctx_to_hw 1258 * @hw: pointer to the hardware structure 1259 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1260 * @tx_drbell_q_index: the index of the doorbell queue 1261 * 1262 * Copies doorbell queue context from dense structure to HW register space 1263 */ 1264 static enum ice_status 1265 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1266 u32 tx_drbell_q_index) 1267 { 1268 u8 i; 1269 1270 if (!ice_tx_drbell_q_ctx) 1271 return ICE_ERR_BAD_PTR; 1272 1273 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1274 return ICE_ERR_PARAM; 1275 1276 /* Copy each dword separately to HW */ 1277 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1278 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1279 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1280 1281 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1282 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1283 } 1284 1285 return ICE_SUCCESS; 1286 } 1287 1288 /* LAN Tx Doorbell Queue Context info */ 1289 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1290 /* Field Width LSB */ 1291 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1292 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1293 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1294 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1295 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1296 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1297 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1298 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1299 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1300 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1301 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1302 { 0 } 1303 }; 1304 1305 /** 1306 * ice_write_tx_drbell_q_ctx 1307 * @hw: pointer to the hardware structure 1308 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1309 * @tx_drbell_q_index: the index of the doorbell queue 1310 * 1311 * Converts doorbell queue context from sparse to dense structure and then 1312 * writes it to HW register space 1313 */ 1314 enum ice_status 1315 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1316 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1317 u32 tx_drbell_q_index) 1318 { 1319 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1320 1321 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 1322 ice_tx_drbell_q_ctx_info); 1323 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1324 } 1325 1326 /** 1327 * ice_clear_tx_drbell_q_ctx 1328 * @hw: pointer to the hardware structure 1329 * @tx_drbell_q_index: the index of the doorbell queue to clear 1330 * 1331 * Clears doorbell queue context in HW register space 1332 */ 1333 enum ice_status 1334 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1335 { 1336 u8 i; 1337 1338 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1339 return ICE_ERR_PARAM; 1340 1341 /* Clear each dword register separately */ 1342 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1343 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1344 1345 return ICE_SUCCESS; 1346 } 1347 1348 /* FW Admin Queue command wrappers */ 1349 1350 /** 1351 * ice_should_retry_sq_send_cmd 1352 * @opcode: AQ opcode 1353 * 1354 * Decide if we should retry the send command routine for the ATQ, depending 1355 * on the opcode. 1356 */ 1357 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1358 { 1359 switch (opcode) { 1360 case ice_aqc_opc_get_link_topo: 1361 case ice_aqc_opc_lldp_stop: 1362 case ice_aqc_opc_lldp_start: 1363 case ice_aqc_opc_lldp_filter_ctrl: 1364 return true; 1365 } 1366 1367 return false; 1368 } 1369 1370 /** 1371 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1372 * @hw: pointer to the HW struct 1373 * @cq: pointer to the specific Control queue 1374 * @desc: prefilled descriptor describing the command 1375 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1376 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1377 * @cd: pointer to command details structure 1378 * 1379 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1380 * Queue if the EBUSY AQ error is returned. 1381 */ 1382 static enum ice_status 1383 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1384 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1385 struct ice_sq_cd *cd) 1386 { 1387 struct ice_aq_desc desc_cpy; 1388 enum ice_status status; 1389 bool is_cmd_for_retry; 1390 u8 *buf_cpy = NULL; 1391 u8 idx = 0; 1392 u16 opcode; 1393 1394 opcode = LE16_TO_CPU(desc->opcode); 1395 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1396 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); 1397 1398 if (is_cmd_for_retry) { 1399 if (buf) { 1400 buf_cpy = (u8 *)ice_malloc(hw, buf_size); 1401 if (!buf_cpy) 1402 return ICE_ERR_NO_MEMORY; 1403 } 1404 1405 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), 1406 ICE_NONDMA_TO_NONDMA); 1407 } 1408 1409 do { 1410 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1411 1412 if (!is_cmd_for_retry || status == ICE_SUCCESS || 1413 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1414 break; 1415 1416 if (buf_cpy) 1417 ice_memcpy(buf, buf_cpy, buf_size, 1418 ICE_NONDMA_TO_NONDMA); 1419 1420 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), 1421 ICE_NONDMA_TO_NONDMA); 1422 1423 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); 1424 1425 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1426 1427 if (buf_cpy) 1428 ice_free(hw, buf_cpy); 1429 1430 return status; 1431 } 1432 1433 /** 1434 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1435 * @hw: pointer to the HW struct 1436 * @desc: descriptor describing the command 1437 * @buf: buffer to use for indirect commands (NULL for direct commands) 1438 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1439 * @cd: pointer to command details structure 1440 * 1441 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1442 */ 1443 enum ice_status 1444 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1445 u16 buf_size, struct ice_sq_cd *cd) 1446 { 1447 if (hw->aq_send_cmd_fn) { 1448 enum ice_status status = ICE_ERR_NOT_READY; 1449 u16 retval = ICE_AQ_RC_OK; 1450 1451 ice_acquire_lock(&hw->adminq.sq_lock); 1452 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc, 1453 buf, buf_size)) { 1454 retval = LE16_TO_CPU(desc->retval); 1455 /* strip off FW internal code */ 1456 if (retval) 1457 retval &= 0xff; 1458 if (retval == ICE_AQ_RC_OK) 1459 status = ICE_SUCCESS; 1460 else 1461 status = ICE_ERR_AQ_ERROR; 1462 } 1463 1464 hw->adminq.sq_last_status = (enum ice_aq_err)retval; 1465 ice_release_lock(&hw->adminq.sq_lock); 1466 1467 return status; 1468 } 1469 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1470 } 1471 1472 /** 1473 * ice_aq_get_fw_ver 1474 * @hw: pointer to the HW struct 1475 * @cd: pointer to command details structure or NULL 1476 * 1477 * Get the firmware version (0x0001) from the admin queue commands 1478 */ 1479 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1480 { 1481 struct ice_aqc_get_ver *resp; 1482 struct ice_aq_desc desc; 1483 enum ice_status status; 1484 1485 resp = &desc.params.get_ver; 1486 1487 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1488 1489 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1490 1491 if (!status) { 1492 hw->fw_branch = resp->fw_branch; 1493 hw->fw_maj_ver = resp->fw_major; 1494 hw->fw_min_ver = resp->fw_minor; 1495 hw->fw_patch = resp->fw_patch; 1496 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1497 hw->api_branch = resp->api_branch; 1498 hw->api_maj_ver = resp->api_major; 1499 hw->api_min_ver = resp->api_minor; 1500 hw->api_patch = resp->api_patch; 1501 } 1502 1503 return status; 1504 } 1505 1506 /** 1507 * ice_aq_send_driver_ver 1508 * @hw: pointer to the HW struct 1509 * @dv: driver's major, minor version 1510 * @cd: pointer to command details structure or NULL 1511 * 1512 * Send the driver version (0x0002) to the firmware 1513 */ 1514 enum ice_status 1515 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1516 struct ice_sq_cd *cd) 1517 { 1518 struct ice_aqc_driver_ver *cmd; 1519 struct ice_aq_desc desc; 1520 u16 len; 1521 1522 cmd = &desc.params.driver_ver; 1523 1524 if (!dv) 1525 return ICE_ERR_PARAM; 1526 1527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1528 1529 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1530 cmd->major_ver = dv->major_ver; 1531 cmd->minor_ver = dv->minor_ver; 1532 cmd->build_ver = dv->build_ver; 1533 cmd->subbuild_ver = dv->subbuild_ver; 1534 1535 len = 0; 1536 while (len < sizeof(dv->driver_string) && 1537 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1538 len++; 1539 1540 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1541 } 1542 1543 /** 1544 * ice_aq_q_shutdown 1545 * @hw: pointer to the HW struct 1546 * @unloading: is the driver unloading itself 1547 * 1548 * Tell the Firmware that we're shutting down the AdminQ and whether 1549 * or not the driver is unloading as well (0x0003). 1550 */ 1551 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1552 { 1553 struct ice_aqc_q_shutdown *cmd; 1554 struct ice_aq_desc desc; 1555 1556 cmd = &desc.params.q_shutdown; 1557 1558 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1559 1560 if (unloading) 1561 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1562 1563 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1564 } 1565 1566 /** 1567 * ice_aq_req_res 1568 * @hw: pointer to the HW struct 1569 * @res: resource ID 1570 * @access: access type 1571 * @sdp_number: resource number 1572 * @timeout: the maximum time in ms that the driver may hold the resource 1573 * @cd: pointer to command details structure or NULL 1574 * 1575 * Requests common resource using the admin queue commands (0x0008). 1576 * When attempting to acquire the Global Config Lock, the driver can 1577 * learn of three states: 1578 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1579 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1580 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1581 * successfully downloaded the package; the driver does 1582 * not have to download the package and can continue 1583 * loading 1584 * 1585 * Note that if the caller is in an acquire lock, perform action, release lock 1586 * phase of operation, it is possible that the FW may detect a timeout and issue 1587 * a CORER. In this case, the driver will receive a CORER interrupt and will 1588 * have to determine its cause. The calling thread that is handling this flow 1589 * will likely get an error propagated back to it indicating the Download 1590 * Package, Update Package or the Release Resource AQ commands timed out. 1591 */ 1592 static enum ice_status 1593 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1594 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1595 struct ice_sq_cd *cd) 1596 { 1597 struct ice_aqc_req_res *cmd_resp; 1598 struct ice_aq_desc desc; 1599 enum ice_status status; 1600 1601 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1602 1603 cmd_resp = &desc.params.res_owner; 1604 1605 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1606 1607 cmd_resp->res_id = CPU_TO_LE16(res); 1608 cmd_resp->access_type = CPU_TO_LE16(access); 1609 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1610 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1611 *timeout = 0; 1612 1613 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1614 1615 /* The completion specifies the maximum time in ms that the driver 1616 * may hold the resource in the Timeout field. 1617 */ 1618 1619 /* Global config lock response utilizes an additional status field. 1620 * 1621 * If the Global config lock resource is held by some other driver, the 1622 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1623 * and the timeout field indicates the maximum time the current owner 1624 * of the resource has to free it. 1625 */ 1626 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1627 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1628 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1629 return ICE_SUCCESS; 1630 } else if (LE16_TO_CPU(cmd_resp->status) == 1631 ICE_AQ_RES_GLBL_IN_PROG) { 1632 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1633 return ICE_ERR_AQ_ERROR; 1634 } else if (LE16_TO_CPU(cmd_resp->status) == 1635 ICE_AQ_RES_GLBL_DONE) { 1636 return ICE_ERR_AQ_NO_WORK; 1637 } 1638 1639 /* invalid FW response, force a timeout immediately */ 1640 *timeout = 0; 1641 return ICE_ERR_AQ_ERROR; 1642 } 1643 1644 /* If the resource is held by some other driver, the command completes 1645 * with a busy return value and the timeout field indicates the maximum 1646 * time the current owner of the resource has to free it. 1647 */ 1648 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1649 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1650 1651 return status; 1652 } 1653 1654 /** 1655 * ice_aq_release_res 1656 * @hw: pointer to the HW struct 1657 * @res: resource ID 1658 * @sdp_number: resource number 1659 * @cd: pointer to command details structure or NULL 1660 * 1661 * release common resource using the admin queue commands (0x0009) 1662 */ 1663 static enum ice_status 1664 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1665 struct ice_sq_cd *cd) 1666 { 1667 struct ice_aqc_req_res *cmd; 1668 struct ice_aq_desc desc; 1669 1670 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1671 1672 cmd = &desc.params.res_owner; 1673 1674 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1675 1676 cmd->res_id = CPU_TO_LE16(res); 1677 cmd->res_number = CPU_TO_LE32(sdp_number); 1678 1679 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1680 } 1681 1682 /** 1683 * ice_acquire_res 1684 * @hw: pointer to the HW structure 1685 * @res: resource ID 1686 * @access: access type (read or write) 1687 * @timeout: timeout in milliseconds 1688 * 1689 * This function will attempt to acquire the ownership of a resource. 1690 */ 1691 enum ice_status 1692 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1693 enum ice_aq_res_access_type access, u32 timeout) 1694 { 1695 #define ICE_RES_POLLING_DELAY_MS 10 1696 u32 delay = ICE_RES_POLLING_DELAY_MS; 1697 u32 time_left = timeout; 1698 enum ice_status status; 1699 1700 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1701 1702 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1703 1704 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1705 * previously acquired the resource and performed any necessary updates; 1706 * in this case the caller does not obtain the resource and has no 1707 * further work to do. 1708 */ 1709 if (status == ICE_ERR_AQ_NO_WORK) 1710 goto ice_acquire_res_exit; 1711 1712 if (status) 1713 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1714 1715 /* If necessary, poll until the current lock owner timeouts */ 1716 timeout = time_left; 1717 while (status && timeout && time_left) { 1718 ice_msec_delay(delay, true); 1719 timeout = (timeout > delay) ? timeout - delay : 0; 1720 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1721 1722 if (status == ICE_ERR_AQ_NO_WORK) 1723 /* lock free, but no work to do */ 1724 break; 1725 1726 if (!status) 1727 /* lock acquired */ 1728 break; 1729 } 1730 if (status && status != ICE_ERR_AQ_NO_WORK) 1731 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1732 1733 ice_acquire_res_exit: 1734 if (status == ICE_ERR_AQ_NO_WORK) { 1735 if (access == ICE_RES_WRITE) 1736 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1737 else 1738 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1739 } 1740 return status; 1741 } 1742 1743 /** 1744 * ice_release_res 1745 * @hw: pointer to the HW structure 1746 * @res: resource ID 1747 * 1748 * This function will release a resource using the proper Admin Command. 1749 */ 1750 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1751 { 1752 enum ice_status status; 1753 u32 total_delay = 0; 1754 1755 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1756 1757 status = ice_aq_release_res(hw, res, 0, NULL); 1758 1759 /* there are some rare cases when trying to release the resource 1760 * results in an admin queue timeout, so handle them correctly 1761 */ 1762 while ((status == ICE_ERR_AQ_TIMEOUT) && 1763 (total_delay < hw->adminq.sq_cmd_timeout)) { 1764 ice_msec_delay(1, true); 1765 status = ice_aq_release_res(hw, res, 0, NULL); 1766 total_delay++; 1767 } 1768 } 1769 1770 /** 1771 * ice_aq_alloc_free_res - command to allocate/free resources 1772 * @hw: pointer to the HW struct 1773 * @num_entries: number of resource entries in buffer 1774 * @buf: Indirect buffer to hold data parameters and response 1775 * @buf_size: size of buffer for indirect commands 1776 * @opc: pass in the command opcode 1777 * @cd: pointer to command details structure or NULL 1778 * 1779 * Helper function to allocate/free resources using the admin queue commands 1780 */ 1781 enum ice_status 1782 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1783 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1784 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1785 { 1786 struct ice_aqc_alloc_free_res_cmd *cmd; 1787 struct ice_aq_desc desc; 1788 1789 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1790 1791 cmd = &desc.params.sw_res_ctrl; 1792 1793 if (!buf) 1794 return ICE_ERR_PARAM; 1795 1796 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) 1797 return ICE_ERR_PARAM; 1798 1799 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1800 1801 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1802 1803 cmd->num_entries = CPU_TO_LE16(num_entries); 1804 1805 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1806 } 1807 1808 /** 1809 * ice_alloc_hw_res - allocate resource 1810 * @hw: pointer to the HW struct 1811 * @type: type of resource 1812 * @num: number of resources to allocate 1813 * @btm: allocate from bottom 1814 * @res: pointer to array that will receive the resources 1815 */ 1816 enum ice_status 1817 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1818 { 1819 struct ice_aqc_alloc_free_res_elem *buf; 1820 enum ice_status status; 1821 u16 buf_len; 1822 1823 buf_len = ice_struct_size(buf, elem, num); 1824 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1825 if (!buf) 1826 return ICE_ERR_NO_MEMORY; 1827 1828 /* Prepare buffer to allocate resource. */ 1829 buf->num_elems = CPU_TO_LE16(num); 1830 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1831 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1832 if (btm) 1833 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1834 1835 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1836 ice_aqc_opc_alloc_res, NULL); 1837 if (status) 1838 goto ice_alloc_res_exit; 1839 1840 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num, 1841 ICE_NONDMA_TO_NONDMA); 1842 1843 ice_alloc_res_exit: 1844 ice_free(hw, buf); 1845 return status; 1846 } 1847 1848 /** 1849 * ice_free_hw_res - free allocated HW resource 1850 * @hw: pointer to the HW struct 1851 * @type: type of resource to free 1852 * @num: number of resources 1853 * @res: pointer to array that contains the resources to free 1854 */ 1855 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1856 { 1857 struct ice_aqc_alloc_free_res_elem *buf; 1858 enum ice_status status; 1859 u16 buf_len; 1860 1861 buf_len = ice_struct_size(buf, elem, num); 1862 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1863 if (!buf) 1864 return ICE_ERR_NO_MEMORY; 1865 1866 /* Prepare buffer to free resource. */ 1867 buf->num_elems = CPU_TO_LE16(num); 1868 buf->res_type = CPU_TO_LE16(type); 1869 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num, 1870 ICE_NONDMA_TO_NONDMA); 1871 1872 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1873 ice_aqc_opc_free_res, NULL); 1874 if (status) 1875 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1876 1877 ice_free(hw, buf); 1878 return status; 1879 } 1880 1881 /** 1882 * ice_get_num_per_func - determine number of resources per PF 1883 * @hw: pointer to the HW structure 1884 * @max: value to be evenly split between each PF 1885 * 1886 * Determine the number of valid functions by going through the bitmap returned 1887 * from parsing capabilities and use this to calculate the number of resources 1888 * per PF based on the max value passed in. 1889 */ 1890 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1891 { 1892 u8 funcs; 1893 1894 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1895 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 1896 ICE_CAPS_VALID_FUNCS_M); 1897 1898 if (!funcs) 1899 return 0; 1900 1901 return max / funcs; 1902 } 1903 1904 /** 1905 * ice_parse_common_caps - parse common device/function capabilities 1906 * @hw: pointer to the HW struct 1907 * @caps: pointer to common capabilities structure 1908 * @elem: the capability element to parse 1909 * @prefix: message prefix for tracing capabilities 1910 * 1911 * Given a capability element, extract relevant details into the common 1912 * capability structure. 1913 * 1914 * Returns: true if the capability matches one of the common capability ids, 1915 * false otherwise. 1916 */ 1917 static bool 1918 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1919 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1920 { 1921 u32 logical_id = LE32_TO_CPU(elem->logical_id); 1922 u32 phys_id = LE32_TO_CPU(elem->phys_id); 1923 u32 number = LE32_TO_CPU(elem->number); 1924 u16 cap = LE16_TO_CPU(elem->cap); 1925 bool found = true; 1926 1927 switch (cap) { 1928 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1929 caps->valid_functions = number; 1930 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1931 caps->valid_functions); 1932 break; 1933 case ICE_AQC_CAPS_DCB: 1934 caps->dcb = (number == 1); 1935 caps->active_tc_bitmap = logical_id; 1936 caps->maxtc = phys_id; 1937 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 1938 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1939 caps->active_tc_bitmap); 1940 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1941 break; 1942 case ICE_AQC_CAPS_RSS: 1943 caps->rss_table_size = number; 1944 caps->rss_table_entry_width = logical_id; 1945 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 1946 caps->rss_table_size); 1947 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 1948 caps->rss_table_entry_width); 1949 break; 1950 case ICE_AQC_CAPS_RXQS: 1951 caps->num_rxq = number; 1952 caps->rxq_first_id = phys_id; 1953 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1954 caps->num_rxq); 1955 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 1956 caps->rxq_first_id); 1957 break; 1958 case ICE_AQC_CAPS_TXQS: 1959 caps->num_txq = number; 1960 caps->txq_first_id = phys_id; 1961 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1962 caps->num_txq); 1963 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 1964 caps->txq_first_id); 1965 break; 1966 case ICE_AQC_CAPS_MSIX: 1967 caps->num_msix_vectors = number; 1968 caps->msix_vector_first_id = phys_id; 1969 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 1970 caps->num_msix_vectors); 1971 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 1972 caps->msix_vector_first_id); 1973 break; 1974 case ICE_AQC_CAPS_NVM_MGMT: 1975 caps->sec_rev_disabled = 1976 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? 1977 true : false; 1978 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, 1979 caps->sec_rev_disabled); 1980 caps->update_disabled = 1981 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? 1982 true : false; 1983 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, 1984 caps->update_disabled); 1985 caps->nvm_unified_update = 1986 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1987 true : false; 1988 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1989 caps->nvm_unified_update); 1990 break; 1991 case ICE_AQC_CAPS_MAX_MTU: 1992 caps->max_mtu = number; 1993 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1994 prefix, caps->max_mtu); 1995 break; 1996 default: 1997 /* Not one of the recognized common capabilities */ 1998 found = false; 1999 } 2000 2001 return found; 2002 } 2003 2004 /** 2005 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2006 * @hw: pointer to the HW structure 2007 * @caps: pointer to capabilities structure to fix 2008 * 2009 * Re-calculate the capabilities that are dependent on the number of physical 2010 * ports; i.e. some features are not supported or function differently on 2011 * devices with more than 4 ports. 2012 */ 2013 static void 2014 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2015 { 2016 /* This assumes device capabilities are always scanned before function 2017 * capabilities during the initialization flow. 2018 */ 2019 if (hw->dev_caps.num_funcs > 4) { 2020 /* Max 4 TCs per port */ 2021 caps->maxtc = 4; 2022 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2023 caps->maxtc); 2024 } 2025 } 2026 2027 /** 2028 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2029 * @hw: pointer to the HW struct 2030 * @func_p: pointer to function capabilities structure 2031 * @cap: pointer to the capability element to parse 2032 * 2033 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2034 */ 2035 static void 2036 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2037 struct ice_aqc_list_caps_elem *cap) 2038 { 2039 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2040 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2041 LE32_TO_CPU(cap->number)); 2042 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2043 func_p->guar_num_vsi); 2044 } 2045 2046 /** 2047 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2048 * @hw: pointer to the HW struct 2049 * @func_p: pointer to function capabilities structure 2050 * 2051 * Extract function capabilities for ICE_AQC_CAPS_FD. 2052 */ 2053 static void 2054 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2055 { 2056 u32 reg_val, val; 2057 2058 if (hw->dcf_enabled) 2059 return; 2060 reg_val = rd32(hw, GLQF_FD_SIZE); 2061 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2062 GLQF_FD_SIZE_FD_GSIZE_S; 2063 func_p->fd_fltr_guar = 2064 ice_get_num_per_func(hw, val); 2065 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2066 GLQF_FD_SIZE_FD_BSIZE_S; 2067 func_p->fd_fltr_best_effort = val; 2068 2069 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2070 func_p->fd_fltr_guar); 2071 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2072 func_p->fd_fltr_best_effort); 2073 } 2074 2075 /** 2076 * ice_parse_func_caps - Parse function capabilities 2077 * @hw: pointer to the HW struct 2078 * @func_p: pointer to function capabilities structure 2079 * @buf: buffer containing the function capability records 2080 * @cap_count: the number of capabilities 2081 * 2082 * Helper function to parse function (0x000A) capabilities list. For 2083 * capabilities shared between device and function, this relies on 2084 * ice_parse_common_caps. 2085 * 2086 * Loop through the list of provided capabilities and extract the relevant 2087 * data into the function capabilities structured. 2088 */ 2089 static void 2090 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2091 void *buf, u32 cap_count) 2092 { 2093 struct ice_aqc_list_caps_elem *cap_resp; 2094 u32 i; 2095 2096 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2097 2098 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 2099 2100 for (i = 0; i < cap_count; i++) { 2101 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2102 bool found; 2103 2104 found = ice_parse_common_caps(hw, &func_p->common_cap, 2105 &cap_resp[i], "func caps"); 2106 2107 switch (cap) { 2108 case ICE_AQC_CAPS_VSI: 2109 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2110 break; 2111 case ICE_AQC_CAPS_FD: 2112 ice_parse_fdir_func_caps(hw, func_p); 2113 break; 2114 default: 2115 /* Don't list common capabilities as unknown */ 2116 if (!found) 2117 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2118 i, cap); 2119 break; 2120 } 2121 } 2122 2123 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2124 } 2125 2126 /** 2127 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2128 * @hw: pointer to the HW struct 2129 * @dev_p: pointer to device capabilities structure 2130 * @cap: capability element to parse 2131 * 2132 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2133 */ 2134 static void 2135 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2136 struct ice_aqc_list_caps_elem *cap) 2137 { 2138 u32 number = LE32_TO_CPU(cap->number); 2139 2140 dev_p->num_funcs = ice_hweight32(number); 2141 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2142 dev_p->num_funcs); 2143 } 2144 2145 /** 2146 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2147 * @hw: pointer to the HW struct 2148 * @dev_p: pointer to device capabilities structure 2149 * @cap: capability element to parse 2150 * 2151 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2152 */ 2153 static void 2154 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2155 struct ice_aqc_list_caps_elem *cap) 2156 { 2157 u32 number = LE32_TO_CPU(cap->number); 2158 2159 dev_p->num_vsi_allocd_to_host = number; 2160 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2161 dev_p->num_vsi_allocd_to_host); 2162 } 2163 2164 /** 2165 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2166 * @hw: pointer to the HW struct 2167 * @dev_p: pointer to device capabilities structure 2168 * @cap: capability element to parse 2169 * 2170 * Parse ICE_AQC_CAPS_FD for device capabilities. 2171 */ 2172 static void 2173 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2174 struct ice_aqc_list_caps_elem *cap) 2175 { 2176 u32 number = LE32_TO_CPU(cap->number); 2177 2178 dev_p->num_flow_director_fltr = number; 2179 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2180 dev_p->num_flow_director_fltr); 2181 } 2182 2183 /** 2184 * ice_parse_dev_caps - Parse device capabilities 2185 * @hw: pointer to the HW struct 2186 * @dev_p: pointer to device capabilities structure 2187 * @buf: buffer containing the device capability records 2188 * @cap_count: the number of capabilities 2189 * 2190 * Helper device to parse device (0x000B) capabilities list. For 2191 * capabilities shared between device and function, this relies on 2192 * ice_parse_common_caps. 2193 * 2194 * Loop through the list of provided capabilities and extract the relevant 2195 * data into the device capabilities structured. 2196 */ 2197 static void 2198 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2199 void *buf, u32 cap_count) 2200 { 2201 struct ice_aqc_list_caps_elem *cap_resp; 2202 u32 i; 2203 2204 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2205 2206 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 2207 2208 for (i = 0; i < cap_count; i++) { 2209 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2210 bool found; 2211 2212 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2213 &cap_resp[i], "dev caps"); 2214 2215 switch (cap) { 2216 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2217 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2218 break; 2219 case ICE_AQC_CAPS_VSI: 2220 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2221 break; 2222 case ICE_AQC_CAPS_FD: 2223 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2224 break; 2225 default: 2226 /* Don't list common capabilities as unknown */ 2227 if (!found) 2228 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2229 i, cap); 2230 break; 2231 } 2232 } 2233 2234 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2235 } 2236 2237 /** 2238 * ice_aq_list_caps - query function/device capabilities 2239 * @hw: pointer to the HW struct 2240 * @buf: a buffer to hold the capabilities 2241 * @buf_size: size of the buffer 2242 * @cap_count: if not NULL, set to the number of capabilities reported 2243 * @opc: capabilities type to discover, device or function 2244 * @cd: pointer to command details structure or NULL 2245 * 2246 * Get the function (0x000A) or device (0x000B) capabilities description from 2247 * firmware and store it in the buffer. 2248 * 2249 * If the cap_count pointer is not NULL, then it is set to the number of 2250 * capabilities firmware will report. Note that if the buffer size is too 2251 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2252 * cap_count will still be updated in this case. It is recommended that the 2253 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2254 * firmware could return) to avoid this. 2255 */ 2256 static enum ice_status 2257 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2258 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2259 { 2260 struct ice_aqc_list_caps *cmd; 2261 struct ice_aq_desc desc; 2262 enum ice_status status; 2263 2264 cmd = &desc.params.get_cap; 2265 2266 if (opc != ice_aqc_opc_list_func_caps && 2267 opc != ice_aqc_opc_list_dev_caps) 2268 return ICE_ERR_PARAM; 2269 2270 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2271 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2272 2273 if (cap_count) 2274 *cap_count = LE32_TO_CPU(cmd->count); 2275 2276 return status; 2277 } 2278 2279 /** 2280 * ice_discover_dev_caps - Read and extract device capabilities 2281 * @hw: pointer to the hardware structure 2282 * @dev_caps: pointer to device capabilities structure 2283 * 2284 * Read the device capabilities and extract them into the dev_caps structure 2285 * for later use. 2286 */ 2287 static enum ice_status 2288 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2289 { 2290 enum ice_status status; 2291 u32 cap_count = 0; 2292 void *cbuf; 2293 2294 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2295 if (!cbuf) 2296 return ICE_ERR_NO_MEMORY; 2297 2298 /* Although the driver doesn't know the number of capabilities the 2299 * device will return, we can simply send a 4KB buffer, the maximum 2300 * possible size that firmware can return. 2301 */ 2302 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2303 2304 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2305 ice_aqc_opc_list_dev_caps, NULL); 2306 if (!status) 2307 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2308 ice_free(hw, cbuf); 2309 2310 return status; 2311 } 2312 2313 /** 2314 * ice_discover_func_caps - Read and extract function capabilities 2315 * @hw: pointer to the hardware structure 2316 * @func_caps: pointer to function capabilities structure 2317 * 2318 * Read the function capabilities and extract them into the func_caps structure 2319 * for later use. 2320 */ 2321 static enum ice_status 2322 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2323 { 2324 enum ice_status status; 2325 u32 cap_count = 0; 2326 void *cbuf; 2327 2328 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2329 if (!cbuf) 2330 return ICE_ERR_NO_MEMORY; 2331 2332 /* Although the driver doesn't know the number of capabilities the 2333 * device will return, we can simply send a 4KB buffer, the maximum 2334 * possible size that firmware can return. 2335 */ 2336 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2337 2338 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2339 ice_aqc_opc_list_func_caps, NULL); 2340 if (!status) 2341 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2342 ice_free(hw, cbuf); 2343 2344 return status; 2345 } 2346 2347 /** 2348 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2349 * @hw: pointer to the hardware structure 2350 */ 2351 void ice_set_safe_mode_caps(struct ice_hw *hw) 2352 { 2353 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2354 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2355 struct ice_hw_common_caps cached_caps; 2356 u32 num_funcs; 2357 2358 /* cache some func_caps values that should be restored after memset */ 2359 cached_caps = func_caps->common_cap; 2360 2361 /* unset func capabilities */ 2362 memset(func_caps, 0, sizeof(*func_caps)); 2363 2364 #define ICE_RESTORE_FUNC_CAP(name) \ 2365 func_caps->common_cap.name = cached_caps.name 2366 2367 /* restore cached values */ 2368 ICE_RESTORE_FUNC_CAP(valid_functions); 2369 ICE_RESTORE_FUNC_CAP(txq_first_id); 2370 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2371 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2372 ICE_RESTORE_FUNC_CAP(max_mtu); 2373 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2374 2375 /* one Tx and one Rx queue in safe mode */ 2376 func_caps->common_cap.num_rxq = 1; 2377 func_caps->common_cap.num_txq = 1; 2378 2379 /* two MSIX vectors, one for traffic and one for misc causes */ 2380 func_caps->common_cap.num_msix_vectors = 2; 2381 func_caps->guar_num_vsi = 1; 2382 2383 /* cache some dev_caps values that should be restored after memset */ 2384 cached_caps = dev_caps->common_cap; 2385 num_funcs = dev_caps->num_funcs; 2386 2387 /* unset dev capabilities */ 2388 memset(dev_caps, 0, sizeof(*dev_caps)); 2389 2390 #define ICE_RESTORE_DEV_CAP(name) \ 2391 dev_caps->common_cap.name = cached_caps.name 2392 2393 /* restore cached values */ 2394 ICE_RESTORE_DEV_CAP(valid_functions); 2395 ICE_RESTORE_DEV_CAP(txq_first_id); 2396 ICE_RESTORE_DEV_CAP(rxq_first_id); 2397 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2398 ICE_RESTORE_DEV_CAP(max_mtu); 2399 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2400 dev_caps->num_funcs = num_funcs; 2401 2402 /* one Tx and one Rx queue per function in safe mode */ 2403 dev_caps->common_cap.num_rxq = num_funcs; 2404 dev_caps->common_cap.num_txq = num_funcs; 2405 2406 /* two MSIX vectors per function */ 2407 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2408 } 2409 2410 /** 2411 * ice_get_caps - get info about the HW 2412 * @hw: pointer to the hardware structure 2413 */ 2414 enum ice_status ice_get_caps(struct ice_hw *hw) 2415 { 2416 enum ice_status status; 2417 2418 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2419 if (status) 2420 return status; 2421 2422 return ice_discover_func_caps(hw, &hw->func_caps); 2423 } 2424 2425 /** 2426 * ice_aq_manage_mac_write - manage MAC address write command 2427 * @hw: pointer to the HW struct 2428 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2429 * @flags: flags to control write behavior 2430 * @cd: pointer to command details structure or NULL 2431 * 2432 * This function is used to write MAC address to the NVM (0x0108). 2433 */ 2434 enum ice_status 2435 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2436 struct ice_sq_cd *cd) 2437 { 2438 struct ice_aqc_manage_mac_write *cmd; 2439 struct ice_aq_desc desc; 2440 2441 cmd = &desc.params.mac_write; 2442 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2443 2444 cmd->flags = flags; 2445 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 2446 2447 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2448 } 2449 2450 /** 2451 * ice_aq_clear_pxe_mode 2452 * @hw: pointer to the HW struct 2453 * 2454 * Tell the firmware that the driver is taking over from PXE (0x0110). 2455 */ 2456 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2457 { 2458 struct ice_aq_desc desc; 2459 2460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2461 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2462 2463 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2464 } 2465 2466 /** 2467 * ice_clear_pxe_mode - clear pxe operations mode 2468 * @hw: pointer to the HW struct 2469 * 2470 * Make sure all PXE mode settings are cleared, including things 2471 * like descriptor fetch/write-back mode. 2472 */ 2473 void ice_clear_pxe_mode(struct ice_hw *hw) 2474 { 2475 if (ice_check_sq_alive(hw, &hw->adminq)) 2476 ice_aq_clear_pxe_mode(hw); 2477 } 2478 2479 /** 2480 * ice_aq_set_port_params - set physical port parameters. 2481 * @pi: pointer to the port info struct 2482 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 2483 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 2484 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 2485 * @double_vlan: if set double VLAN is enabled 2486 * @cd: pointer to command details structure or NULL 2487 * 2488 * Set Physical port parameters (0x0203) 2489 */ 2490 enum ice_status 2491 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 2492 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 2493 struct ice_sq_cd *cd) 2494 2495 { 2496 struct ice_aqc_set_port_params *cmd; 2497 struct ice_hw *hw = pi->hw; 2498 struct ice_aq_desc desc; 2499 u16 cmd_flags = 0; 2500 2501 cmd = &desc.params.set_port_params; 2502 2503 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2504 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 2505 if (save_bad_pac) 2506 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; 2507 if (pad_short_pac) 2508 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; 2509 if (double_vlan) 2510 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2511 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 2512 2513 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2514 } 2515 2516 /** 2517 * ice_get_link_speed_based_on_phy_type - returns link speed 2518 * @phy_type_low: lower part of phy_type 2519 * @phy_type_high: higher part of phy_type 2520 * 2521 * This helper function will convert an entry in PHY type structure 2522 * [phy_type_low, phy_type_high] to its corresponding link speed. 2523 * Note: In the structure of [phy_type_low, phy_type_high], there should 2524 * be one bit set, as this function will convert one PHY type to its 2525 * speed. 2526 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2527 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2528 */ 2529 static u16 2530 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2531 { 2532 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2533 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2534 2535 switch (phy_type_low) { 2536 case ICE_PHY_TYPE_LOW_100BASE_TX: 2537 case ICE_PHY_TYPE_LOW_100M_SGMII: 2538 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2539 break; 2540 case ICE_PHY_TYPE_LOW_1000BASE_T: 2541 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2542 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2543 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2544 case ICE_PHY_TYPE_LOW_1G_SGMII: 2545 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2546 break; 2547 case ICE_PHY_TYPE_LOW_2500BASE_T: 2548 case ICE_PHY_TYPE_LOW_2500BASE_X: 2549 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2550 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2551 break; 2552 case ICE_PHY_TYPE_LOW_5GBASE_T: 2553 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2554 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2555 break; 2556 case ICE_PHY_TYPE_LOW_10GBASE_T: 2557 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2558 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2559 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2560 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2561 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2562 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2563 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2564 break; 2565 case ICE_PHY_TYPE_LOW_25GBASE_T: 2566 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2567 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2568 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2569 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2570 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2571 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2572 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2573 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2574 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2575 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2576 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2577 break; 2578 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2579 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2580 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2581 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2582 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2583 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2584 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2585 break; 2586 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2587 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2588 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2589 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2590 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2591 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2592 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2593 case ICE_PHY_TYPE_LOW_50G_AUI2: 2594 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2595 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2596 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2597 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2598 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2599 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2600 case ICE_PHY_TYPE_LOW_50G_AUI1: 2601 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2602 break; 2603 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2604 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2605 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2606 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2607 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2608 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2609 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2610 case ICE_PHY_TYPE_LOW_100G_AUI4: 2611 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2612 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2613 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2614 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2615 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2616 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2617 break; 2618 default: 2619 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2620 break; 2621 } 2622 2623 switch (phy_type_high) { 2624 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2625 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2626 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2627 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2628 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2629 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2630 break; 2631 default: 2632 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2633 break; 2634 } 2635 2636 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2637 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2638 return ICE_AQ_LINK_SPEED_UNKNOWN; 2639 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2640 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2641 return ICE_AQ_LINK_SPEED_UNKNOWN; 2642 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2643 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2644 return speed_phy_type_low; 2645 else 2646 return speed_phy_type_high; 2647 } 2648 2649 /** 2650 * ice_update_phy_type 2651 * @phy_type_low: pointer to the lower part of phy_type 2652 * @phy_type_high: pointer to the higher part of phy_type 2653 * @link_speeds_bitmap: targeted link speeds bitmap 2654 * 2655 * Note: For the link_speeds_bitmap structure, you can check it at 2656 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2657 * link_speeds_bitmap include multiple speeds. 2658 * 2659 * Each entry in this [phy_type_low, phy_type_high] structure will 2660 * present a certain link speed. This helper function will turn on bits 2661 * in [phy_type_low, phy_type_high] structure based on the value of 2662 * link_speeds_bitmap input parameter. 2663 */ 2664 void 2665 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2666 u16 link_speeds_bitmap) 2667 { 2668 u64 pt_high; 2669 u64 pt_low; 2670 int index; 2671 u16 speed; 2672 2673 /* We first check with low part of phy_type */ 2674 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2675 pt_low = BIT_ULL(index); 2676 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2677 2678 if (link_speeds_bitmap & speed) 2679 *phy_type_low |= BIT_ULL(index); 2680 } 2681 2682 /* We then check with high part of phy_type */ 2683 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2684 pt_high = BIT_ULL(index); 2685 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2686 2687 if (link_speeds_bitmap & speed) 2688 *phy_type_high |= BIT_ULL(index); 2689 } 2690 } 2691 2692 /** 2693 * ice_aq_set_phy_cfg 2694 * @hw: pointer to the HW struct 2695 * @pi: port info structure of the interested logical port 2696 * @cfg: structure with PHY configuration data to be set 2697 * @cd: pointer to command details structure or NULL 2698 * 2699 * Set the various PHY configuration parameters supported on the Port. 2700 * One or more of the Set PHY config parameters may be ignored in an MFP 2701 * mode as the PF may not have the privilege to set some of the PHY Config 2702 * parameters. This status will be indicated by the command response (0x0601). 2703 */ 2704 enum ice_status 2705 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2706 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2707 { 2708 struct ice_aq_desc desc; 2709 enum ice_status status; 2710 2711 if (!cfg) 2712 return ICE_ERR_PARAM; 2713 2714 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2715 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2716 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2717 cfg->caps); 2718 2719 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2720 } 2721 2722 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2723 desc.params.set_phy.lport_num = pi->lport; 2724 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2725 2726 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2727 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2728 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 2729 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2730 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 2731 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2732 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2733 cfg->low_power_ctrl_an); 2734 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2735 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2736 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2737 cfg->link_fec_opt); 2738 2739 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2740 2741 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2742 status = ICE_SUCCESS; 2743 2744 if (!status) 2745 pi->phy.curr_user_phy_cfg = *cfg; 2746 2747 return status; 2748 } 2749 2750 /** 2751 * ice_update_link_info - update status of the HW network link 2752 * @pi: port info structure of the interested logical port 2753 */ 2754 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2755 { 2756 struct ice_link_status *li; 2757 enum ice_status status; 2758 2759 if (!pi) 2760 return ICE_ERR_PARAM; 2761 2762 li = &pi->phy.link_info; 2763 2764 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2765 if (status) 2766 return status; 2767 2768 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2769 struct ice_aqc_get_phy_caps_data *pcaps; 2770 struct ice_hw *hw; 2771 2772 hw = pi->hw; 2773 pcaps = (struct ice_aqc_get_phy_caps_data *) 2774 ice_malloc(hw, sizeof(*pcaps)); 2775 if (!pcaps) 2776 return ICE_ERR_NO_MEMORY; 2777 2778 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2779 pcaps, NULL); 2780 2781 if (status == ICE_SUCCESS) 2782 ice_memcpy(li->module_type, &pcaps->module_type, 2783 sizeof(li->module_type), 2784 ICE_NONDMA_TO_NONDMA); 2785 2786 ice_free(hw, pcaps); 2787 } 2788 2789 return status; 2790 } 2791 2792 /** 2793 * ice_cache_phy_user_req 2794 * @pi: port information structure 2795 * @cache_data: PHY logging data 2796 * @cache_mode: PHY logging mode 2797 * 2798 * Log the user request on (FC, FEC, SPEED) for later user. 2799 */ 2800 static void 2801 ice_cache_phy_user_req(struct ice_port_info *pi, 2802 struct ice_phy_cache_mode_data cache_data, 2803 enum ice_phy_cache_mode cache_mode) 2804 { 2805 if (!pi) 2806 return; 2807 2808 switch (cache_mode) { 2809 case ICE_FC_MODE: 2810 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2811 break; 2812 case ICE_SPEED_MODE: 2813 pi->phy.curr_user_speed_req = 2814 cache_data.data.curr_user_speed_req; 2815 break; 2816 case ICE_FEC_MODE: 2817 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2818 break; 2819 default: 2820 break; 2821 } 2822 } 2823 2824 /** 2825 * ice_caps_to_fc_mode 2826 * @caps: PHY capabilities 2827 * 2828 * Convert PHY FC capabilities to ice FC mode 2829 */ 2830 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2831 { 2832 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2833 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2834 return ICE_FC_FULL; 2835 2836 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2837 return ICE_FC_TX_PAUSE; 2838 2839 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2840 return ICE_FC_RX_PAUSE; 2841 2842 return ICE_FC_NONE; 2843 } 2844 2845 /** 2846 * ice_caps_to_fec_mode 2847 * @caps: PHY capabilities 2848 * @fec_options: Link FEC options 2849 * 2850 * Convert PHY FEC capabilities to ice FEC mode 2851 */ 2852 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2853 { 2854 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2855 return ICE_FEC_AUTO; 2856 2857 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2858 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2859 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2860 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2861 return ICE_FEC_BASER; 2862 2863 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2864 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2865 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2866 return ICE_FEC_RS; 2867 2868 return ICE_FEC_NONE; 2869 } 2870 2871 /** 2872 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2873 * @pi: port information structure 2874 * @cfg: PHY configuration data to set FC mode 2875 * @req_mode: FC mode to configure 2876 */ 2877 static enum ice_status 2878 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2879 enum ice_fc_mode req_mode) 2880 { 2881 struct ice_phy_cache_mode_data cache_data; 2882 u8 pause_mask = 0x0; 2883 2884 if (!pi || !cfg) 2885 return ICE_ERR_BAD_PTR; 2886 2887 switch (req_mode) { 2888 case ICE_FC_AUTO: 2889 { 2890 struct ice_aqc_get_phy_caps_data *pcaps; 2891 enum ice_status status; 2892 2893 pcaps = (struct ice_aqc_get_phy_caps_data *) 2894 ice_malloc(pi->hw, sizeof(*pcaps)); 2895 if (!pcaps) 2896 return ICE_ERR_NO_MEMORY; 2897 2898 /* Query the value of FC that both the NIC and attached media 2899 * can do. 2900 */ 2901 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2902 pcaps, NULL); 2903 if (status) { 2904 ice_free(pi->hw, pcaps); 2905 return status; 2906 } 2907 2908 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2909 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2910 2911 ice_free(pi->hw, pcaps); 2912 break; 2913 } 2914 case ICE_FC_FULL: 2915 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2916 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2917 break; 2918 case ICE_FC_RX_PAUSE: 2919 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2920 break; 2921 case ICE_FC_TX_PAUSE: 2922 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2923 break; 2924 default: 2925 break; 2926 } 2927 2928 /* clear the old pause settings */ 2929 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2930 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2931 2932 /* set the new capabilities */ 2933 cfg->caps |= pause_mask; 2934 2935 /* Cache user FC request */ 2936 cache_data.data.curr_user_fc_req = req_mode; 2937 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2938 2939 return ICE_SUCCESS; 2940 } 2941 2942 /** 2943 * ice_set_fc 2944 * @pi: port information structure 2945 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2946 * @ena_auto_link_update: enable automatic link update 2947 * 2948 * Set the requested flow control mode. 2949 */ 2950 enum ice_status 2951 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2952 { 2953 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2954 struct ice_aqc_get_phy_caps_data *pcaps; 2955 enum ice_status status; 2956 struct ice_hw *hw; 2957 2958 if (!pi || !aq_failures) 2959 return ICE_ERR_BAD_PTR; 2960 2961 *aq_failures = 0; 2962 hw = pi->hw; 2963 2964 pcaps = (struct ice_aqc_get_phy_caps_data *) 2965 ice_malloc(hw, sizeof(*pcaps)); 2966 if (!pcaps) 2967 return ICE_ERR_NO_MEMORY; 2968 2969 /* Get the current PHY config */ 2970 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 2971 pcaps, NULL); 2972 2973 if (status) { 2974 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2975 goto out; 2976 } 2977 2978 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2979 2980 /* Configure the set PHY data */ 2981 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2982 if (status) { 2983 if (status != ICE_ERR_BAD_PTR) 2984 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2985 2986 goto out; 2987 } 2988 2989 /* If the capabilities have changed, then set the new config */ 2990 if (cfg.caps != pcaps->caps) { 2991 int retry_count, retry_max = 10; 2992 2993 /* Auto restart link so settings take effect */ 2994 if (ena_auto_link_update) 2995 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2996 2997 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2998 if (status) { 2999 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3000 goto out; 3001 } 3002 3003 /* Update the link info 3004 * It sometimes takes a really long time for link to 3005 * come back from the atomic reset. Thus, we wait a 3006 * little bit. 3007 */ 3008 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3009 status = ice_update_link_info(pi); 3010 3011 if (status == ICE_SUCCESS) 3012 break; 3013 3014 ice_msec_delay(100, true); 3015 } 3016 3017 if (status) 3018 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3019 } 3020 3021 out: 3022 ice_free(hw, pcaps); 3023 return status; 3024 } 3025 3026 /** 3027 * ice_phy_caps_equals_cfg 3028 * @phy_caps: PHY capabilities 3029 * @phy_cfg: PHY configuration 3030 * 3031 * Helper function to determine if PHY capabilities matches PHY 3032 * configuration 3033 */ 3034 bool 3035 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3036 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3037 { 3038 u8 caps_mask, cfg_mask; 3039 3040 if (!phy_caps || !phy_cfg) 3041 return false; 3042 3043 /* These bits are not common between capabilities and configuration. 3044 * Do not use them to determine equality. 3045 */ 3046 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3047 ICE_AQC_PHY_EN_MOD_QUAL); 3048 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3049 3050 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3051 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3052 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3053 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3054 phy_caps->eee_cap != phy_cfg->eee_cap || 3055 phy_caps->eeer_value != phy_cfg->eeer_value || 3056 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3057 return false; 3058 3059 return true; 3060 } 3061 3062 /** 3063 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3064 * @pi: port information structure 3065 * @caps: PHY ability structure to copy date from 3066 * @cfg: PHY configuration structure to copy data to 3067 * 3068 * Helper function to copy AQC PHY get ability data to PHY set configuration 3069 * data structure 3070 */ 3071 void 3072 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3073 struct ice_aqc_get_phy_caps_data *caps, 3074 struct ice_aqc_set_phy_cfg_data *cfg) 3075 { 3076 if (!pi || !caps || !cfg) 3077 return; 3078 3079 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 3080 cfg->phy_type_low = caps->phy_type_low; 3081 cfg->phy_type_high = caps->phy_type_high; 3082 cfg->caps = caps->caps; 3083 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3084 cfg->eee_cap = caps->eee_cap; 3085 cfg->eeer_value = caps->eeer_value; 3086 cfg->link_fec_opt = caps->link_fec_options; 3087 cfg->module_compliance_enforcement = 3088 caps->module_compliance_enforcement; 3089 } 3090 3091 /** 3092 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3093 * @pi: port information structure 3094 * @cfg: PHY configuration data to set FEC mode 3095 * @fec: FEC mode to configure 3096 */ 3097 enum ice_status 3098 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3099 enum ice_fec_mode fec) 3100 { 3101 struct ice_aqc_get_phy_caps_data *pcaps; 3102 enum ice_status status = ICE_SUCCESS; 3103 struct ice_hw *hw; 3104 3105 if (!pi || !cfg) 3106 return ICE_ERR_BAD_PTR; 3107 3108 hw = pi->hw; 3109 3110 pcaps = (struct ice_aqc_get_phy_caps_data *) 3111 ice_malloc(hw, sizeof(*pcaps)); 3112 if (!pcaps) 3113 return ICE_ERR_NO_MEMORY; 3114 3115 status = ice_aq_get_phy_caps(pi, false, 3116 (ice_fw_supports_report_dflt_cfg(hw) ? 3117 ICE_AQC_REPORT_DFLT_CFG : 3118 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3119 3120 if (status) 3121 goto out; 3122 3123 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 3124 cfg->link_fec_opt = pcaps->link_fec_options; 3125 3126 switch (fec) { 3127 case ICE_FEC_BASER: 3128 /* Clear RS bits, and AND BASE-R ability 3129 * bits and OR request bits. 3130 */ 3131 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3132 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3133 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3134 ICE_AQC_PHY_FEC_25G_KR_REQ; 3135 break; 3136 case ICE_FEC_RS: 3137 /* Clear BASE-R bits, and AND RS ability 3138 * bits and OR request bits. 3139 */ 3140 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3141 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3142 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3143 break; 3144 case ICE_FEC_NONE: 3145 /* Clear all FEC option bits. */ 3146 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3147 break; 3148 case ICE_FEC_AUTO: 3149 /* AND auto FEC bit, and all caps bits. */ 3150 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3151 cfg->link_fec_opt |= pcaps->link_fec_options; 3152 break; 3153 default: 3154 status = ICE_ERR_PARAM; 3155 break; 3156 } 3157 3158 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && 3159 !ice_fw_supports_report_dflt_cfg(pi->hw)) { 3160 struct ice_link_default_override_tlv tlv; 3161 3162 if (ice_get_link_default_override(&tlv, pi)) 3163 goto out; 3164 3165 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3166 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3167 cfg->link_fec_opt = tlv.fec_options; 3168 } 3169 3170 out: 3171 ice_free(hw, pcaps); 3172 3173 return status; 3174 } 3175 3176 /** 3177 * ice_get_link_status - get status of the HW network link 3178 * @pi: port information structure 3179 * @link_up: pointer to bool (true/false = linkup/linkdown) 3180 * 3181 * Variable link_up is true if link is up, false if link is down. 3182 * The variable link_up is invalid if status is non zero. As a 3183 * result of this call, link status reporting becomes enabled 3184 */ 3185 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3186 { 3187 struct ice_phy_info *phy_info; 3188 enum ice_status status = ICE_SUCCESS; 3189 3190 if (!pi || !link_up) 3191 return ICE_ERR_PARAM; 3192 3193 phy_info = &pi->phy; 3194 3195 if (phy_info->get_link_info) { 3196 status = ice_update_link_info(pi); 3197 3198 if (status) 3199 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3200 status); 3201 } 3202 3203 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3204 3205 return status; 3206 } 3207 3208 /** 3209 * ice_aq_set_link_restart_an 3210 * @pi: pointer to the port information structure 3211 * @ena_link: if true: enable link, if false: disable link 3212 * @cd: pointer to command details structure or NULL 3213 * 3214 * Sets up the link and restarts the Auto-Negotiation over the link. 3215 */ 3216 enum ice_status 3217 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3218 struct ice_sq_cd *cd) 3219 { 3220 struct ice_aqc_restart_an *cmd; 3221 struct ice_aq_desc desc; 3222 3223 cmd = &desc.params.restart_an; 3224 3225 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3226 3227 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3228 cmd->lport_num = pi->lport; 3229 if (ena_link) 3230 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3231 else 3232 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3233 3234 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3235 } 3236 3237 /** 3238 * ice_aq_set_event_mask 3239 * @hw: pointer to the HW struct 3240 * @port_num: port number of the physical function 3241 * @mask: event mask to be set 3242 * @cd: pointer to command details structure or NULL 3243 * 3244 * Set event mask (0x0613) 3245 */ 3246 enum ice_status 3247 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3248 struct ice_sq_cd *cd) 3249 { 3250 struct ice_aqc_set_event_mask *cmd; 3251 struct ice_aq_desc desc; 3252 3253 cmd = &desc.params.set_event_mask; 3254 3255 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3256 3257 cmd->lport_num = port_num; 3258 3259 cmd->event_mask = CPU_TO_LE16(mask); 3260 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3261 } 3262 3263 /** 3264 * ice_aq_set_mac_loopback 3265 * @hw: pointer to the HW struct 3266 * @ena_lpbk: Enable or Disable loopback 3267 * @cd: pointer to command details structure or NULL 3268 * 3269 * Enable/disable loopback on a given port 3270 */ 3271 enum ice_status 3272 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3273 { 3274 struct ice_aqc_set_mac_lb *cmd; 3275 struct ice_aq_desc desc; 3276 3277 cmd = &desc.params.set_mac_lb; 3278 3279 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3280 if (ena_lpbk) 3281 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3282 3283 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3284 } 3285 3286 /** 3287 * ice_aq_set_port_id_led 3288 * @pi: pointer to the port information 3289 * @is_orig_mode: is this LED set to original mode (by the net-list) 3290 * @cd: pointer to command details structure or NULL 3291 * 3292 * Set LED value for the given port (0x06e9) 3293 */ 3294 enum ice_status 3295 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3296 struct ice_sq_cd *cd) 3297 { 3298 struct ice_aqc_set_port_id_led *cmd; 3299 struct ice_hw *hw = pi->hw; 3300 struct ice_aq_desc desc; 3301 3302 cmd = &desc.params.set_port_id_led; 3303 3304 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3305 3306 if (is_orig_mode) 3307 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3308 else 3309 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3310 3311 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3312 } 3313 3314 /** 3315 * ice_aq_sff_eeprom 3316 * @hw: pointer to the HW struct 3317 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3318 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3319 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3320 * @page: QSFP page 3321 * @set_page: set or ignore the page 3322 * @data: pointer to data buffer to be read/written to the I2C device. 3323 * @length: 1-16 for read, 1 for write. 3324 * @write: 0 read, 1 for write. 3325 * @cd: pointer to command details structure or NULL 3326 * 3327 * Read/Write SFF EEPROM (0x06EE) 3328 */ 3329 enum ice_status 3330 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3331 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3332 bool write, struct ice_sq_cd *cd) 3333 { 3334 struct ice_aqc_sff_eeprom *cmd; 3335 struct ice_aq_desc desc; 3336 enum ice_status status; 3337 3338 if (!data || (mem_addr & 0xff00)) 3339 return ICE_ERR_PARAM; 3340 3341 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3342 cmd = &desc.params.read_write_sff_param; 3343 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 3344 cmd->lport_num = (u8)(lport & 0xff); 3345 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3346 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 3347 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3348 ((set_page << 3349 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3350 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3351 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 3352 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3353 if (write) 3354 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 3355 3356 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3357 return status; 3358 } 3359 3360 /** 3361 * __ice_aq_get_set_rss_lut 3362 * @hw: pointer to the hardware structure 3363 * @params: RSS LUT parameters 3364 * @set: set true to set the table, false to get the table 3365 * 3366 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3367 */ 3368 static enum ice_status 3369 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3370 { 3371 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3372 struct ice_aqc_get_set_rss_lut *cmd_resp; 3373 struct ice_aq_desc desc; 3374 enum ice_status status; 3375 u8 *lut; 3376 3377 if (!params) 3378 return ICE_ERR_PARAM; 3379 3380 vsi_handle = params->vsi_handle; 3381 lut = params->lut; 3382 3383 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3384 return ICE_ERR_PARAM; 3385 3386 lut_size = params->lut_size; 3387 lut_type = params->lut_type; 3388 glob_lut_idx = params->global_lut_id; 3389 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3390 3391 cmd_resp = &desc.params.get_set_rss_lut; 3392 3393 if (set) { 3394 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3395 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3396 } else { 3397 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3398 } 3399 3400 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3401 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3402 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3403 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3404 3405 switch (lut_type) { 3406 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3407 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3408 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3409 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3410 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3411 break; 3412 default: 3413 status = ICE_ERR_PARAM; 3414 goto ice_aq_get_set_rss_lut_exit; 3415 } 3416 3417 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3418 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3419 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3420 3421 if (!set) 3422 goto ice_aq_get_set_rss_lut_send; 3423 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3424 if (!set) 3425 goto ice_aq_get_set_rss_lut_send; 3426 } else { 3427 goto ice_aq_get_set_rss_lut_send; 3428 } 3429 3430 /* LUT size is only valid for Global and PF table types */ 3431 switch (lut_size) { 3432 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3433 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 3434 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3435 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3436 break; 3437 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3438 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3439 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3440 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3441 break; 3442 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3443 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3444 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3445 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3446 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3447 break; 3448 } 3449 /* fall-through */ 3450 default: 3451 status = ICE_ERR_PARAM; 3452 goto ice_aq_get_set_rss_lut_exit; 3453 } 3454 3455 ice_aq_get_set_rss_lut_send: 3456 cmd_resp->flags = CPU_TO_LE16(flags); 3457 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3458 3459 ice_aq_get_set_rss_lut_exit: 3460 return status; 3461 } 3462 3463 /** 3464 * ice_aq_get_rss_lut 3465 * @hw: pointer to the hardware structure 3466 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3467 * 3468 * get the RSS lookup table, PF or VSI type 3469 */ 3470 enum ice_status 3471 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3472 { 3473 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3474 } 3475 3476 /** 3477 * ice_aq_set_rss_lut 3478 * @hw: pointer to the hardware structure 3479 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3480 * 3481 * set the RSS lookup table, PF or VSI type 3482 */ 3483 enum ice_status 3484 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3485 { 3486 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3487 } 3488 3489 /** 3490 * __ice_aq_get_set_rss_key 3491 * @hw: pointer to the HW struct 3492 * @vsi_id: VSI FW index 3493 * @key: pointer to key info struct 3494 * @set: set true to set the key, false to get the key 3495 * 3496 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3497 */ 3498 static enum 3499 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3500 struct ice_aqc_get_set_rss_keys *key, 3501 bool set) 3502 { 3503 struct ice_aqc_get_set_rss_key *cmd_resp; 3504 u16 key_size = sizeof(*key); 3505 struct ice_aq_desc desc; 3506 3507 cmd_resp = &desc.params.get_set_rss_key; 3508 3509 if (set) { 3510 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3511 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3512 } else { 3513 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3514 } 3515 3516 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3517 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3518 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3519 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3520 3521 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3522 } 3523 3524 /** 3525 * ice_aq_get_rss_key 3526 * @hw: pointer to the HW struct 3527 * @vsi_handle: software VSI handle 3528 * @key: pointer to key info struct 3529 * 3530 * get the RSS key per VSI 3531 */ 3532 enum ice_status 3533 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3534 struct ice_aqc_get_set_rss_keys *key) 3535 { 3536 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3537 return ICE_ERR_PARAM; 3538 3539 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3540 key, false); 3541 } 3542 3543 /** 3544 * ice_aq_set_rss_key 3545 * @hw: pointer to the HW struct 3546 * @vsi_handle: software VSI handle 3547 * @keys: pointer to key info struct 3548 * 3549 * set the RSS key per VSI 3550 */ 3551 enum ice_status 3552 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3553 struct ice_aqc_get_set_rss_keys *keys) 3554 { 3555 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3556 return ICE_ERR_PARAM; 3557 3558 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3559 keys, true); 3560 } 3561 3562 /** 3563 * ice_aq_add_lan_txq 3564 * @hw: pointer to the hardware structure 3565 * @num_qgrps: Number of added queue groups 3566 * @qg_list: list of queue groups to be added 3567 * @buf_size: size of buffer for indirect command 3568 * @cd: pointer to command details structure or NULL 3569 * 3570 * Add Tx LAN queue (0x0C30) 3571 * 3572 * NOTE: 3573 * Prior to calling add Tx LAN queue: 3574 * Initialize the following as part of the Tx queue context: 3575 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3576 * Cache profile and Packet shaper profile. 3577 * 3578 * After add Tx LAN queue AQ command is completed: 3579 * Interrupts should be associated with specific queues, 3580 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3581 * flow. 3582 */ 3583 enum ice_status 3584 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3585 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3586 struct ice_sq_cd *cd) 3587 { 3588 struct ice_aqc_add_tx_qgrp *list; 3589 struct ice_aqc_add_txqs *cmd; 3590 struct ice_aq_desc desc; 3591 u16 i, sum_size = 0; 3592 3593 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3594 3595 cmd = &desc.params.add_txqs; 3596 3597 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3598 3599 if (!qg_list) 3600 return ICE_ERR_PARAM; 3601 3602 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3603 return ICE_ERR_PARAM; 3604 3605 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3606 sum_size += ice_struct_size(list, txqs, list->num_txqs); 3607 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3608 list->num_txqs); 3609 } 3610 3611 if (buf_size != sum_size) 3612 return ICE_ERR_PARAM; 3613 3614 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3615 3616 cmd->num_qgrps = num_qgrps; 3617 3618 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3619 } 3620 3621 /** 3622 * ice_aq_dis_lan_txq 3623 * @hw: pointer to the hardware structure 3624 * @num_qgrps: number of groups in the list 3625 * @qg_list: the list of groups to disable 3626 * @buf_size: the total size of the qg_list buffer in bytes 3627 * @rst_src: if called due to reset, specifies the reset source 3628 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3629 * @cd: pointer to command details structure or NULL 3630 * 3631 * Disable LAN Tx queue (0x0C31) 3632 */ 3633 static enum ice_status 3634 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3635 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3636 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3637 struct ice_sq_cd *cd) 3638 { 3639 struct ice_aqc_dis_txq_item *item; 3640 struct ice_aqc_dis_txqs *cmd; 3641 struct ice_aq_desc desc; 3642 enum ice_status status; 3643 u16 i, sz = 0; 3644 3645 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3646 cmd = &desc.params.dis_txqs; 3647 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3648 3649 /* qg_list can be NULL only in VM/VF reset flow */ 3650 if (!qg_list && !rst_src) 3651 return ICE_ERR_PARAM; 3652 3653 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3654 return ICE_ERR_PARAM; 3655 3656 cmd->num_entries = num_qgrps; 3657 3658 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3659 ICE_AQC_Q_DIS_TIMEOUT_M); 3660 3661 switch (rst_src) { 3662 case ICE_VM_RESET: 3663 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3664 cmd->vmvf_and_timeout |= 3665 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3666 break; 3667 case ICE_NO_RESET: 3668 default: 3669 break; 3670 } 3671 3672 /* flush pipe on time out */ 3673 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3674 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3675 if (!qg_list) 3676 goto do_aq; 3677 3678 /* set RD bit to indicate that command buffer is provided by the driver 3679 * and it needs to be read by the firmware 3680 */ 3681 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3682 3683 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3684 u16 item_size = ice_struct_size(item, q_id, item->num_qs); 3685 3686 /* If the num of queues is even, add 2 bytes of padding */ 3687 if ((item->num_qs % 2) == 0) 3688 item_size += 2; 3689 3690 sz += item_size; 3691 3692 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3693 } 3694 3695 if (buf_size != sz) 3696 return ICE_ERR_PARAM; 3697 3698 do_aq: 3699 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3700 if (status) { 3701 if (!qg_list) 3702 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3703 vmvf_num, hw->adminq.sq_last_status); 3704 else 3705 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3706 LE16_TO_CPU(qg_list[0].q_id[0]), 3707 hw->adminq.sq_last_status); 3708 } 3709 return status; 3710 } 3711 3712 /** 3713 * ice_aq_move_recfg_lan_txq 3714 * @hw: pointer to the hardware structure 3715 * @num_qs: number of queues to move/reconfigure 3716 * @is_move: true if this operation involves node movement 3717 * @is_tc_change: true if this operation involves a TC change 3718 * @subseq_call: true if this operation is a subsequent call 3719 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 3720 * @timeout: timeout in units of 100 usec (valid values 0-50) 3721 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 3722 * @buf: struct containing src/dest TEID and per-queue info 3723 * @buf_size: size of buffer for indirect command 3724 * @txqs_moved: out param, number of queues successfully moved 3725 * @cd: pointer to command details structure or NULL 3726 * 3727 * Move / Reconfigure Tx LAN queues (0x0C32) 3728 */ 3729 enum ice_status 3730 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 3731 bool is_tc_change, bool subseq_call, bool flush_pipe, 3732 u8 timeout, u32 *blocked_cgds, 3733 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 3734 u8 *txqs_moved, struct ice_sq_cd *cd) 3735 { 3736 struct ice_aqc_move_txqs *cmd; 3737 struct ice_aq_desc desc; 3738 enum ice_status status; 3739 3740 cmd = &desc.params.move_txqs; 3741 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 3742 3743 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 3744 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 3745 return ICE_ERR_PARAM; 3746 3747 if (is_tc_change && !flush_pipe && !blocked_cgds) 3748 return ICE_ERR_PARAM; 3749 3750 if (!is_move && !is_tc_change) 3751 return ICE_ERR_PARAM; 3752 3753 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3754 3755 if (is_move) 3756 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 3757 3758 if (is_tc_change) 3759 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 3760 3761 if (subseq_call) 3762 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 3763 3764 if (flush_pipe) 3765 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 3766 3767 cmd->num_qs = num_qs; 3768 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 3769 ICE_AQC_Q_CMD_TIMEOUT_M); 3770 3771 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3772 3773 if (!status && txqs_moved) 3774 *txqs_moved = cmd->num_qs; 3775 3776 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 3777 is_tc_change && !flush_pipe) 3778 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 3779 3780 return status; 3781 } 3782 3783 /* End of FW Admin Queue command wrappers */ 3784 3785 /** 3786 * ice_write_byte - write a byte to a packed context structure 3787 * @src_ctx: the context structure to read from 3788 * @dest_ctx: the context to be written to 3789 * @ce_info: a description of the struct to be filled 3790 */ 3791 static void 3792 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3793 { 3794 u8 src_byte, dest_byte, mask; 3795 u8 *from, *dest; 3796 u16 shift_width; 3797 3798 /* copy from the next struct field */ 3799 from = src_ctx + ce_info->offset; 3800 3801 /* prepare the bits and mask */ 3802 shift_width = ce_info->lsb % 8; 3803 mask = (u8)(BIT(ce_info->width) - 1); 3804 3805 src_byte = *from; 3806 src_byte &= mask; 3807 3808 /* shift to correct alignment */ 3809 mask <<= shift_width; 3810 src_byte <<= shift_width; 3811 3812 /* get the current bits from the target bit string */ 3813 dest = dest_ctx + (ce_info->lsb / 8); 3814 3815 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3816 3817 dest_byte &= ~mask; /* get the bits not changing */ 3818 dest_byte |= src_byte; /* add in the new bits */ 3819 3820 /* put it all back */ 3821 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3822 } 3823 3824 /** 3825 * ice_write_word - write a word to a packed context structure 3826 * @src_ctx: the context structure to read from 3827 * @dest_ctx: the context to be written to 3828 * @ce_info: a description of the struct to be filled 3829 */ 3830 static void 3831 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3832 { 3833 u16 src_word, mask; 3834 __le16 dest_word; 3835 u8 *from, *dest; 3836 u16 shift_width; 3837 3838 /* copy from the next struct field */ 3839 from = src_ctx + ce_info->offset; 3840 3841 /* prepare the bits and mask */ 3842 shift_width = ce_info->lsb % 8; 3843 mask = BIT(ce_info->width) - 1; 3844 3845 /* don't swizzle the bits until after the mask because the mask bits 3846 * will be in a different bit position on big endian machines 3847 */ 3848 src_word = *(u16 *)from; 3849 src_word &= mask; 3850 3851 /* shift to correct alignment */ 3852 mask <<= shift_width; 3853 src_word <<= shift_width; 3854 3855 /* get the current bits from the target bit string */ 3856 dest = dest_ctx + (ce_info->lsb / 8); 3857 3858 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 3859 3860 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 3861 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 3862 3863 /* put it all back */ 3864 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3865 } 3866 3867 /** 3868 * ice_write_dword - write a dword to a packed context structure 3869 * @src_ctx: the context structure to read from 3870 * @dest_ctx: the context to be written to 3871 * @ce_info: a description of the struct to be filled 3872 */ 3873 static void 3874 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3875 { 3876 u32 src_dword, mask; 3877 __le32 dest_dword; 3878 u8 *from, *dest; 3879 u16 shift_width; 3880 3881 /* copy from the next struct field */ 3882 from = src_ctx + ce_info->offset; 3883 3884 /* prepare the bits and mask */ 3885 shift_width = ce_info->lsb % 8; 3886 3887 /* if the field width is exactly 32 on an x86 machine, then the shift 3888 * operation will not work because the SHL instructions count is masked 3889 * to 5 bits so the shift will do nothing 3890 */ 3891 if (ce_info->width < 32) 3892 mask = BIT(ce_info->width) - 1; 3893 else 3894 mask = (u32)~0; 3895 3896 /* don't swizzle the bits until after the mask because the mask bits 3897 * will be in a different bit position on big endian machines 3898 */ 3899 src_dword = *(u32 *)from; 3900 src_dword &= mask; 3901 3902 /* shift to correct alignment */ 3903 mask <<= shift_width; 3904 src_dword <<= shift_width; 3905 3906 /* get the current bits from the target bit string */ 3907 dest = dest_ctx + (ce_info->lsb / 8); 3908 3909 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 3910 3911 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 3912 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 3913 3914 /* put it all back */ 3915 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3916 } 3917 3918 /** 3919 * ice_write_qword - write a qword to a packed context structure 3920 * @src_ctx: the context structure to read from 3921 * @dest_ctx: the context to be written to 3922 * @ce_info: a description of the struct to be filled 3923 */ 3924 static void 3925 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3926 { 3927 u64 src_qword, mask; 3928 __le64 dest_qword; 3929 u8 *from, *dest; 3930 u16 shift_width; 3931 3932 /* copy from the next struct field */ 3933 from = src_ctx + ce_info->offset; 3934 3935 /* prepare the bits and mask */ 3936 shift_width = ce_info->lsb % 8; 3937 3938 /* if the field width is exactly 64 on an x86 machine, then the shift 3939 * operation will not work because the SHL instructions count is masked 3940 * to 6 bits so the shift will do nothing 3941 */ 3942 if (ce_info->width < 64) 3943 mask = BIT_ULL(ce_info->width) - 1; 3944 else 3945 mask = (u64)~0; 3946 3947 /* don't swizzle the bits until after the mask because the mask bits 3948 * will be in a different bit position on big endian machines 3949 */ 3950 src_qword = *(u64 *)from; 3951 src_qword &= mask; 3952 3953 /* shift to correct alignment */ 3954 mask <<= shift_width; 3955 src_qword <<= shift_width; 3956 3957 /* get the current bits from the target bit string */ 3958 dest = dest_ctx + (ce_info->lsb / 8); 3959 3960 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 3961 3962 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 3963 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 3964 3965 /* put it all back */ 3966 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3967 } 3968 3969 /** 3970 * ice_set_ctx - set context bits in packed structure 3971 * @hw: pointer to the hardware structure 3972 * @src_ctx: pointer to a generic non-packed context structure 3973 * @dest_ctx: pointer to memory for the packed structure 3974 * @ce_info: a description of the structure to be transformed 3975 */ 3976 enum ice_status 3977 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3978 const struct ice_ctx_ele *ce_info) 3979 { 3980 int f; 3981 3982 for (f = 0; ce_info[f].width; f++) { 3983 /* We have to deal with each element of the FW response 3984 * using the correct size so that we are correct regardless 3985 * of the endianness of the machine. 3986 */ 3987 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3988 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3989 f, ce_info[f].width, ce_info[f].size_of); 3990 continue; 3991 } 3992 switch (ce_info[f].size_of) { 3993 case sizeof(u8): 3994 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3995 break; 3996 case sizeof(u16): 3997 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3998 break; 3999 case sizeof(u32): 4000 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4001 break; 4002 case sizeof(u64): 4003 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4004 break; 4005 default: 4006 return ICE_ERR_INVAL_SIZE; 4007 } 4008 } 4009 4010 return ICE_SUCCESS; 4011 } 4012 4013 /** 4014 * ice_read_byte - read context byte into struct 4015 * @src_ctx: the context structure to read from 4016 * @dest_ctx: the context to be written to 4017 * @ce_info: a description of the struct to be filled 4018 */ 4019 static void 4020 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4021 { 4022 u8 dest_byte, mask; 4023 u8 *src, *target; 4024 u16 shift_width; 4025 4026 /* prepare the bits and mask */ 4027 shift_width = ce_info->lsb % 8; 4028 mask = (u8)(BIT(ce_info->width) - 1); 4029 4030 /* shift to correct alignment */ 4031 mask <<= shift_width; 4032 4033 /* get the current bits from the src bit string */ 4034 src = src_ctx + (ce_info->lsb / 8); 4035 4036 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4037 4038 dest_byte &= ~(mask); 4039 4040 dest_byte >>= shift_width; 4041 4042 /* get the address from the struct field */ 4043 target = dest_ctx + ce_info->offset; 4044 4045 /* put it back in the struct */ 4046 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4047 } 4048 4049 /** 4050 * ice_read_word - read context word into struct 4051 * @src_ctx: the context structure to read from 4052 * @dest_ctx: the context to be written to 4053 * @ce_info: a description of the struct to be filled 4054 */ 4055 static void 4056 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4057 { 4058 u16 dest_word, mask; 4059 u8 *src, *target; 4060 __le16 src_word; 4061 u16 shift_width; 4062 4063 /* prepare the bits and mask */ 4064 shift_width = ce_info->lsb % 8; 4065 mask = BIT(ce_info->width) - 1; 4066 4067 /* shift to correct alignment */ 4068 mask <<= shift_width; 4069 4070 /* get the current bits from the src bit string */ 4071 src = src_ctx + (ce_info->lsb / 8); 4072 4073 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 4074 4075 /* the data in the memory is stored as little endian so mask it 4076 * correctly 4077 */ 4078 src_word &= ~(CPU_TO_LE16(mask)); 4079 4080 /* get the data back into host order before shifting */ 4081 dest_word = LE16_TO_CPU(src_word); 4082 4083 dest_word >>= shift_width; 4084 4085 /* get the address from the struct field */ 4086 target = dest_ctx + ce_info->offset; 4087 4088 /* put it back in the struct */ 4089 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4090 } 4091 4092 /** 4093 * ice_read_dword - read context dword into struct 4094 * @src_ctx: the context structure to read from 4095 * @dest_ctx: the context to be written to 4096 * @ce_info: a description of the struct to be filled 4097 */ 4098 static void 4099 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4100 { 4101 u32 dest_dword, mask; 4102 __le32 src_dword; 4103 u8 *src, *target; 4104 u16 shift_width; 4105 4106 /* prepare the bits and mask */ 4107 shift_width = ce_info->lsb % 8; 4108 4109 /* if the field width is exactly 32 on an x86 machine, then the shift 4110 * operation will not work because the SHL instructions count is masked 4111 * to 5 bits so the shift will do nothing 4112 */ 4113 if (ce_info->width < 32) 4114 mask = BIT(ce_info->width) - 1; 4115 else 4116 mask = (u32)~0; 4117 4118 /* shift to correct alignment */ 4119 mask <<= shift_width; 4120 4121 /* get the current bits from the src bit string */ 4122 src = src_ctx + (ce_info->lsb / 8); 4123 4124 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 4125 4126 /* the data in the memory is stored as little endian so mask it 4127 * correctly 4128 */ 4129 src_dword &= ~(CPU_TO_LE32(mask)); 4130 4131 /* get the data back into host order before shifting */ 4132 dest_dword = LE32_TO_CPU(src_dword); 4133 4134 dest_dword >>= shift_width; 4135 4136 /* get the address from the struct field */ 4137 target = dest_ctx + ce_info->offset; 4138 4139 /* put it back in the struct */ 4140 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4141 } 4142 4143 /** 4144 * ice_read_qword - read context qword into struct 4145 * @src_ctx: the context structure to read from 4146 * @dest_ctx: the context to be written to 4147 * @ce_info: a description of the struct to be filled 4148 */ 4149 static void 4150 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4151 { 4152 u64 dest_qword, mask; 4153 __le64 src_qword; 4154 u8 *src, *target; 4155 u16 shift_width; 4156 4157 /* prepare the bits and mask */ 4158 shift_width = ce_info->lsb % 8; 4159 4160 /* if the field width is exactly 64 on an x86 machine, then the shift 4161 * operation will not work because the SHL instructions count is masked 4162 * to 6 bits so the shift will do nothing 4163 */ 4164 if (ce_info->width < 64) 4165 mask = BIT_ULL(ce_info->width) - 1; 4166 else 4167 mask = (u64)~0; 4168 4169 /* shift to correct alignment */ 4170 mask <<= shift_width; 4171 4172 /* get the current bits from the src bit string */ 4173 src = src_ctx + (ce_info->lsb / 8); 4174 4175 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 4176 4177 /* the data in the memory is stored as little endian so mask it 4178 * correctly 4179 */ 4180 src_qword &= ~(CPU_TO_LE64(mask)); 4181 4182 /* get the data back into host order before shifting */ 4183 dest_qword = LE64_TO_CPU(src_qword); 4184 4185 dest_qword >>= shift_width; 4186 4187 /* get the address from the struct field */ 4188 target = dest_ctx + ce_info->offset; 4189 4190 /* put it back in the struct */ 4191 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4192 } 4193 4194 /** 4195 * ice_get_ctx - extract context bits from a packed structure 4196 * @src_ctx: pointer to a generic packed context structure 4197 * @dest_ctx: pointer to a generic non-packed context structure 4198 * @ce_info: a description of the structure to be read from 4199 */ 4200 enum ice_status 4201 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4202 { 4203 int f; 4204 4205 for (f = 0; ce_info[f].width; f++) { 4206 switch (ce_info[f].size_of) { 4207 case 1: 4208 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 4209 break; 4210 case 2: 4211 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 4212 break; 4213 case 4: 4214 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 4215 break; 4216 case 8: 4217 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 4218 break; 4219 default: 4220 /* nothing to do, just keep going */ 4221 break; 4222 } 4223 } 4224 4225 return ICE_SUCCESS; 4226 } 4227 4228 /** 4229 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4230 * @hw: pointer to the HW struct 4231 * @vsi_handle: software VSI handle 4232 * @tc: TC number 4233 * @q_handle: software queue handle 4234 */ 4235 struct ice_q_ctx * 4236 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4237 { 4238 struct ice_vsi_ctx *vsi; 4239 struct ice_q_ctx *q_ctx; 4240 4241 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4242 if (!vsi) 4243 return NULL; 4244 if (q_handle >= vsi->num_lan_q_entries[tc]) 4245 return NULL; 4246 if (!vsi->lan_q_ctx[tc]) 4247 return NULL; 4248 q_ctx = vsi->lan_q_ctx[tc]; 4249 return &q_ctx[q_handle]; 4250 } 4251 4252 /** 4253 * ice_ena_vsi_txq 4254 * @pi: port information structure 4255 * @vsi_handle: software VSI handle 4256 * @tc: TC number 4257 * @q_handle: software queue handle 4258 * @num_qgrps: Number of added queue groups 4259 * @buf: list of queue groups to be added 4260 * @buf_size: size of buffer for indirect command 4261 * @cd: pointer to command details structure or NULL 4262 * 4263 * This function adds one LAN queue 4264 */ 4265 enum ice_status 4266 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4267 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4268 struct ice_sq_cd *cd) 4269 { 4270 struct ice_aqc_txsched_elem_data node = { 0 }; 4271 struct ice_sched_node *parent; 4272 struct ice_q_ctx *q_ctx; 4273 enum ice_status status; 4274 struct ice_hw *hw; 4275 4276 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4277 return ICE_ERR_CFG; 4278 4279 if (num_qgrps > 1 || buf->num_txqs > 1) 4280 return ICE_ERR_MAX_LIMIT; 4281 4282 hw = pi->hw; 4283 4284 if (!ice_is_vsi_valid(hw, vsi_handle)) 4285 return ICE_ERR_PARAM; 4286 4287 ice_acquire_lock(&pi->sched_lock); 4288 4289 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4290 if (!q_ctx) { 4291 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4292 q_handle); 4293 status = ICE_ERR_PARAM; 4294 goto ena_txq_exit; 4295 } 4296 4297 /* find a parent node */ 4298 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4299 ICE_SCHED_NODE_OWNER_LAN); 4300 if (!parent) { 4301 status = ICE_ERR_PARAM; 4302 goto ena_txq_exit; 4303 } 4304 4305 buf->parent_teid = parent->info.node_teid; 4306 node.parent_teid = parent->info.node_teid; 4307 /* Mark that the values in the "generic" section as valid. The default 4308 * value in the "generic" section is zero. This means that : 4309 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4310 * - 0 priority among siblings, indicated by Bit 1-3. 4311 * - WFQ, indicated by Bit 4. 4312 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4313 * Bit 5-6. 4314 * - Bit 7 is reserved. 4315 * Without setting the generic section as valid in valid_sections, the 4316 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4317 */ 4318 buf->txqs[0].info.valid_sections = 4319 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4320 ICE_AQC_ELEM_VALID_EIR; 4321 buf->txqs[0].info.generic = 0; 4322 buf->txqs[0].info.cir_bw.bw_profile_idx = 4323 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4324 buf->txqs[0].info.cir_bw.bw_alloc = 4325 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4326 buf->txqs[0].info.eir_bw.bw_profile_idx = 4327 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4328 buf->txqs[0].info.eir_bw.bw_alloc = 4329 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4330 4331 /* add the LAN queue */ 4332 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4333 if (status != ICE_SUCCESS) { 4334 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4335 LE16_TO_CPU(buf->txqs[0].txq_id), 4336 hw->adminq.sq_last_status); 4337 goto ena_txq_exit; 4338 } 4339 4340 node.node_teid = buf->txqs[0].q_teid; 4341 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4342 q_ctx->q_handle = q_handle; 4343 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 4344 4345 /* add a leaf node into scheduler tree queue layer */ 4346 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4347 if (!status) 4348 status = ice_sched_replay_q_bw(pi, q_ctx); 4349 4350 ena_txq_exit: 4351 ice_release_lock(&pi->sched_lock); 4352 return status; 4353 } 4354 4355 /** 4356 * ice_dis_vsi_txq 4357 * @pi: port information structure 4358 * @vsi_handle: software VSI handle 4359 * @tc: TC number 4360 * @num_queues: number of queues 4361 * @q_handles: pointer to software queue handle array 4362 * @q_ids: pointer to the q_id array 4363 * @q_teids: pointer to queue node teids 4364 * @rst_src: if called due to reset, specifies the reset source 4365 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4366 * @cd: pointer to command details structure or NULL 4367 * 4368 * This function removes queues and their corresponding nodes in SW DB 4369 */ 4370 enum ice_status 4371 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4372 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4373 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4374 struct ice_sq_cd *cd) 4375 { 4376 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4377 struct ice_aqc_dis_txq_item *qg_list; 4378 struct ice_q_ctx *q_ctx; 4379 struct ice_hw *hw; 4380 u16 i, buf_size; 4381 4382 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4383 return ICE_ERR_CFG; 4384 4385 hw = pi->hw; 4386 4387 if (!num_queues) { 4388 /* if queue is disabled already yet the disable queue command 4389 * has to be sent to complete the VF reset, then call 4390 * ice_aq_dis_lan_txq without any queue information 4391 */ 4392 if (rst_src) 4393 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4394 vmvf_num, NULL); 4395 return ICE_ERR_CFG; 4396 } 4397 4398 buf_size = ice_struct_size(qg_list, q_id, 1); 4399 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size); 4400 if (!qg_list) 4401 return ICE_ERR_NO_MEMORY; 4402 4403 ice_acquire_lock(&pi->sched_lock); 4404 4405 for (i = 0; i < num_queues; i++) { 4406 struct ice_sched_node *node; 4407 4408 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4409 if (!node) 4410 continue; 4411 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4412 if (!q_ctx) { 4413 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4414 q_handles[i]); 4415 continue; 4416 } 4417 if (q_ctx->q_handle != q_handles[i]) { 4418 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4419 q_ctx->q_handle, q_handles[i]); 4420 continue; 4421 } 4422 qg_list->parent_teid = node->info.parent_teid; 4423 qg_list->num_qs = 1; 4424 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]); 4425 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4426 vmvf_num, cd); 4427 4428 if (status != ICE_SUCCESS) 4429 break; 4430 ice_free_sched_node(pi, node); 4431 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4432 } 4433 ice_release_lock(&pi->sched_lock); 4434 ice_free(hw, qg_list); 4435 return status; 4436 } 4437 4438 /** 4439 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4440 * @pi: port information structure 4441 * @vsi_handle: software VSI handle 4442 * @tc_bitmap: TC bitmap 4443 * @maxqs: max queues array per TC 4444 * @owner: LAN or RDMA 4445 * 4446 * This function adds/updates the VSI queues per TC. 4447 */ 4448 static enum ice_status 4449 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4450 u16 *maxqs, u8 owner) 4451 { 4452 enum ice_status status = ICE_SUCCESS; 4453 u8 i; 4454 4455 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4456 return ICE_ERR_CFG; 4457 4458 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4459 return ICE_ERR_PARAM; 4460 4461 ice_acquire_lock(&pi->sched_lock); 4462 4463 ice_for_each_traffic_class(i) { 4464 /* configuration is possible only if TC node is present */ 4465 if (!ice_sched_get_tc_node(pi, i)) 4466 continue; 4467 4468 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4469 ice_is_tc_ena(tc_bitmap, i)); 4470 if (status) 4471 break; 4472 } 4473 4474 ice_release_lock(&pi->sched_lock); 4475 return status; 4476 } 4477 4478 /** 4479 * ice_cfg_vsi_lan - configure VSI LAN queues 4480 * @pi: port information structure 4481 * @vsi_handle: software VSI handle 4482 * @tc_bitmap: TC bitmap 4483 * @max_lanqs: max LAN queues array per TC 4484 * 4485 * This function adds/updates the VSI LAN queues per TC. 4486 */ 4487 enum ice_status 4488 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4489 u16 *max_lanqs) 4490 { 4491 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4492 ICE_SCHED_NODE_OWNER_LAN); 4493 } 4494 4495 /** 4496 * ice_is_main_vsi - checks whether the VSI is main VSI 4497 * @hw: pointer to the HW struct 4498 * @vsi_handle: VSI handle 4499 * 4500 * Checks whether the VSI is the main VSI (the first PF VSI created on 4501 * given PF). 4502 */ 4503 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 4504 { 4505 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 4506 } 4507 4508 /** 4509 * ice_replay_pre_init - replay pre initialization 4510 * @hw: pointer to the HW struct 4511 * @sw: pointer to switch info struct for which function initializes filters 4512 * 4513 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4514 */ 4515 static enum ice_status 4516 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 4517 { 4518 enum ice_status status; 4519 u8 i; 4520 4521 /* Delete old entries from replay filter list head if there is any */ 4522 ice_rm_sw_replay_rule_info(hw, sw); 4523 /* In start of replay, move entries into replay_rules list, it 4524 * will allow adding rules entries back to filt_rules list, 4525 * which is operational list. 4526 */ 4527 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4528 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 4529 &sw->recp_list[i].filt_replay_rules); 4530 ice_sched_replay_agg_vsi_preinit(hw); 4531 4532 status = ice_sched_replay_root_node_bw(hw->port_info); 4533 if (status) 4534 return status; 4535 4536 return ice_sched_replay_tc_node_bw(hw->port_info); 4537 } 4538 4539 /** 4540 * ice_replay_vsi - replay VSI configuration 4541 * @hw: pointer to the HW struct 4542 * @vsi_handle: driver VSI handle 4543 * 4544 * Restore all VSI configuration after reset. It is required to call this 4545 * function with main VSI first. 4546 */ 4547 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4548 { 4549 struct ice_switch_info *sw = hw->switch_info; 4550 struct ice_port_info *pi = hw->port_info; 4551 enum ice_status status; 4552 4553 if (!ice_is_vsi_valid(hw, vsi_handle)) 4554 return ICE_ERR_PARAM; 4555 4556 /* Replay pre-initialization if there is any */ 4557 if (ice_is_main_vsi(hw, vsi_handle)) { 4558 status = ice_replay_pre_init(hw, sw); 4559 if (status) 4560 return status; 4561 } 4562 /* Replay per VSI all RSS configurations */ 4563 status = ice_replay_rss_cfg(hw, vsi_handle); 4564 if (status) 4565 return status; 4566 /* Replay per VSI all filters */ 4567 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 4568 if (!status) 4569 status = ice_replay_vsi_agg(hw, vsi_handle); 4570 return status; 4571 } 4572 4573 /** 4574 * ice_replay_post - post replay configuration cleanup 4575 * @hw: pointer to the HW struct 4576 * 4577 * Post replay cleanup. 4578 */ 4579 void ice_replay_post(struct ice_hw *hw) 4580 { 4581 /* Delete old entries from replay filter list head */ 4582 ice_rm_all_sw_replay_rule_info(hw); 4583 ice_sched_replay_agg(hw); 4584 } 4585 4586 /** 4587 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4588 * @hw: ptr to the hardware info 4589 * @reg: offset of 64 bit HW register to read from 4590 * @prev_stat_loaded: bool to specify if previous stats are loaded 4591 * @prev_stat: ptr to previous loaded stat value 4592 * @cur_stat: ptr to current stat value 4593 */ 4594 void 4595 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4596 u64 *prev_stat, u64 *cur_stat) 4597 { 4598 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4599 4600 /* device stats are not reset at PFR, they likely will not be zeroed 4601 * when the driver starts. Thus, save the value from the first read 4602 * without adding to the statistic value so that we report stats which 4603 * count up from zero. 4604 */ 4605 if (!prev_stat_loaded) { 4606 *prev_stat = new_data; 4607 return; 4608 } 4609 4610 /* Calculate the difference between the new and old values, and then 4611 * add it to the software stat value. 4612 */ 4613 if (new_data >= *prev_stat) 4614 *cur_stat += new_data - *prev_stat; 4615 else 4616 /* to manage the potential roll-over */ 4617 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4618 4619 /* Update the previously stored value to prepare for next read */ 4620 *prev_stat = new_data; 4621 } 4622 4623 /** 4624 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4625 * @hw: ptr to the hardware info 4626 * @reg: offset of HW register to read from 4627 * @prev_stat_loaded: bool to specify if previous stats are loaded 4628 * @prev_stat: ptr to previous loaded stat value 4629 * @cur_stat: ptr to current stat value 4630 */ 4631 void 4632 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4633 u64 *prev_stat, u64 *cur_stat) 4634 { 4635 u32 new_data; 4636 4637 new_data = rd32(hw, reg); 4638 4639 /* device stats are not reset at PFR, they likely will not be zeroed 4640 * when the driver starts. Thus, save the value from the first read 4641 * without adding to the statistic value so that we report stats which 4642 * count up from zero. 4643 */ 4644 if (!prev_stat_loaded) { 4645 *prev_stat = new_data; 4646 return; 4647 } 4648 4649 /* Calculate the difference between the new and old values, and then 4650 * add it to the software stat value. 4651 */ 4652 if (new_data >= *prev_stat) 4653 *cur_stat += new_data - *prev_stat; 4654 else 4655 /* to manage the potential roll-over */ 4656 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4657 4658 /* Update the previously stored value to prepare for next read */ 4659 *prev_stat = new_data; 4660 } 4661 4662 /** 4663 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 4664 * @hw: ptr to the hardware info 4665 * @vsi_handle: VSI handle 4666 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 4667 * @cur_stats: ptr to current stats structure 4668 * 4669 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 4670 * thus cannot be read using the normal ice_stat_update32 function. 4671 * 4672 * Read the GLV_REPC register associated with the given VSI, and update the 4673 * rx_no_desc and rx_error values in the ice_eth_stats structure. 4674 * 4675 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 4676 * cleared each time it's read. 4677 * 4678 * Note that the GLV_RDPC register also counts the causes that would trigger 4679 * GLV_REPC. However, it does not give the finer grained detail about why the 4680 * packets are being dropped. The GLV_REPC values can be used to distinguish 4681 * whether Rx packets are dropped due to errors or due to no available 4682 * descriptors. 4683 */ 4684 void 4685 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 4686 struct ice_eth_stats *cur_stats) 4687 { 4688 u16 vsi_num, no_desc, error_cnt; 4689 u32 repc; 4690 4691 if (!ice_is_vsi_valid(hw, vsi_handle)) 4692 return; 4693 4694 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 4695 4696 /* If we haven't loaded stats yet, just clear the current value */ 4697 if (!prev_stat_loaded) { 4698 wr32(hw, GLV_REPC(vsi_num), 0); 4699 return; 4700 } 4701 4702 repc = rd32(hw, GLV_REPC(vsi_num)); 4703 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 4704 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 4705 4706 /* Clear the count by writing to the stats register */ 4707 wr32(hw, GLV_REPC(vsi_num), 0); 4708 4709 cur_stats->rx_no_desc += no_desc; 4710 cur_stats->rx_errors += error_cnt; 4711 } 4712 4713 /** 4714 * ice_sched_query_elem - query element information from HW 4715 * @hw: pointer to the HW struct 4716 * @node_teid: node TEID to be queried 4717 * @buf: buffer to element information 4718 * 4719 * This function queries HW element information 4720 */ 4721 enum ice_status 4722 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4723 struct ice_aqc_txsched_elem_data *buf) 4724 { 4725 u16 buf_size, num_elem_ret = 0; 4726 enum ice_status status; 4727 4728 buf_size = sizeof(*buf); 4729 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 4730 buf->node_teid = CPU_TO_LE32(node_teid); 4731 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4732 NULL); 4733 if (status != ICE_SUCCESS || num_elem_ret != 1) 4734 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4735 return status; 4736 } 4737 4738 /** 4739 * ice_get_fw_mode - returns FW mode 4740 * @hw: pointer to the HW struct 4741 */ 4742 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 4743 { 4744 #define ICE_FW_MODE_DBG_M BIT(0) 4745 #define ICE_FW_MODE_REC_M BIT(1) 4746 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 4747 u32 fw_mode; 4748 4749 /* check the current FW mode */ 4750 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 4751 4752 if (fw_mode & ICE_FW_MODE_DBG_M) 4753 return ICE_FW_MODE_DBG; 4754 else if (fw_mode & ICE_FW_MODE_REC_M) 4755 return ICE_FW_MODE_REC; 4756 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 4757 return ICE_FW_MODE_ROLLBACK; 4758 else 4759 return ICE_FW_MODE_NORMAL; 4760 } 4761 4762 /** 4763 * ice_fw_supports_link_override 4764 * @hw: pointer to the hardware structure 4765 * 4766 * Checks if the firmware supports link override 4767 */ 4768 bool ice_fw_supports_link_override(struct ice_hw *hw) 4769 { 4770 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4771 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4772 return true; 4773 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4774 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4775 return true; 4776 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4777 return true; 4778 } 4779 4780 return false; 4781 } 4782 4783 /** 4784 * ice_get_link_default_override 4785 * @ldo: pointer to the link default override struct 4786 * @pi: pointer to the port info struct 4787 * 4788 * Gets the link default override for a port 4789 */ 4790 enum ice_status 4791 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4792 struct ice_port_info *pi) 4793 { 4794 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4795 struct ice_hw *hw = pi->hw; 4796 enum ice_status status; 4797 4798 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4799 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4800 if (status) { 4801 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4802 return status; 4803 } 4804 4805 /* Each port has its own config; calculate for our port */ 4806 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4807 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4808 4809 /* link options first */ 4810 status = ice_read_sr_word(hw, tlv_start, &buf); 4811 if (status) { 4812 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4813 return status; 4814 } 4815 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4816 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4817 ICE_LINK_OVERRIDE_PHY_CFG_S; 4818 4819 /* link PHY config */ 4820 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4821 status = ice_read_sr_word(hw, offset, &buf); 4822 if (status) { 4823 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4824 return status; 4825 } 4826 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4827 4828 /* PHY types low */ 4829 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4830 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4831 status = ice_read_sr_word(hw, (offset + i), &buf); 4832 if (status) { 4833 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4834 return status; 4835 } 4836 /* shift 16 bits at a time to fill 64 bits */ 4837 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4838 } 4839 4840 /* PHY types high */ 4841 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4842 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4843 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4844 status = ice_read_sr_word(hw, (offset + i), &buf); 4845 if (status) { 4846 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4847 return status; 4848 } 4849 /* shift 16 bits at a time to fill 64 bits */ 4850 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4851 } 4852 4853 return status; 4854 } 4855 4856 /** 4857 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4858 * @caps: get PHY capability data 4859 */ 4860 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4861 { 4862 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4863 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4864 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4865 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4866 return true; 4867 4868 return false; 4869 } 4870 4871 /** 4872 * ice_aq_set_lldp_mib - Set the LLDP MIB 4873 * @hw: pointer to the HW struct 4874 * @mib_type: Local, Remote or both Local and Remote MIBs 4875 * @buf: pointer to the caller-supplied buffer to store the MIB block 4876 * @buf_size: size of the buffer (in bytes) 4877 * @cd: pointer to command details structure or NULL 4878 * 4879 * Set the LLDP MIB. (0x0A08) 4880 */ 4881 enum ice_status 4882 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 4883 struct ice_sq_cd *cd) 4884 { 4885 struct ice_aqc_lldp_set_local_mib *cmd; 4886 struct ice_aq_desc desc; 4887 4888 cmd = &desc.params.lldp_set_mib; 4889 4890 if (buf_size == 0 || !buf) 4891 return ICE_ERR_PARAM; 4892 4893 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 4894 4895 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD); 4896 desc.datalen = CPU_TO_LE16(buf_size); 4897 4898 cmd->type = mib_type; 4899 cmd->length = CPU_TO_LE16(buf_size); 4900 4901 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4902 } 4903 4904 /** 4905 * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl 4906 * @hw: pointer to HW struct 4907 */ 4908 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 4909 { 4910 if (hw->mac_type != ICE_MAC_E810) 4911 return false; 4912 4913 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 4914 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 4915 return true; 4916 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 4917 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 4918 return true; 4919 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 4920 return true; 4921 } 4922 return false; 4923 } 4924 4925 /** 4926 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 4927 * @hw: pointer to HW struct 4928 * @vsi_num: absolute HW index for VSI 4929 * @add: boolean for if adding or removing a filter 4930 */ 4931 enum ice_status 4932 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 4933 { 4934 struct ice_aqc_lldp_filter_ctrl *cmd; 4935 struct ice_aq_desc desc; 4936 4937 cmd = &desc.params.lldp_filter_ctrl; 4938 4939 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 4940 4941 if (add) 4942 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 4943 else 4944 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 4945 4946 cmd->vsi_num = CPU_TO_LE16(vsi_num); 4947 4948 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4949 } 4950 4951 /** 4952 * ice_fw_supports_report_dflt_cfg 4953 * @hw: pointer to the hardware structure 4954 * 4955 * Checks if the firmware supports report default configuration 4956 */ 4957 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 4958 { 4959 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 4960 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 4961 return true; 4962 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 4963 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 4964 return true; 4965 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 4966 return true; 4967 } 4968 return false; 4969 } 4970