1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2019 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 200 13 14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \ 15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \ 16 ((ICE_RX_OPC_MDID << \ 17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \ 18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \ 19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \ 20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M)) 21 22 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \ 23 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \ 24 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \ 25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \ 26 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \ 27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \ 28 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \ 29 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \ 30 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \ 31 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M)) 32 33 34 /** 35 * ice_set_mac_type - Sets MAC type 36 * @hw: pointer to the HW structure 37 * 38 * This function sets the MAC type of the adapter based on the 39 * vendor ID and device ID stored in the HW structure. 40 */ 41 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 42 { 43 enum ice_status status = ICE_SUCCESS; 44 45 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 46 47 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) { 48 switch (hw->device_id) { 49 default: 50 hw->mac_type = ICE_MAC_GENERIC; 51 break; 52 } 53 } else { 54 status = ICE_ERR_DEVICE_NOT_SUPPORTED; 55 } 56 57 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n", 58 hw->mac_type, status); 59 60 return status; 61 } 62 63 64 /** 65 * ice_clear_pf_cfg - Clear PF configuration 66 * @hw: pointer to the hardware structure 67 * 68 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 69 * configuration, flow director filters, etc.). 70 */ 71 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 72 { 73 struct ice_aq_desc desc; 74 75 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 76 77 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 78 } 79 80 /** 81 * ice_aq_manage_mac_read - manage MAC address read command 82 * @hw: pointer to the HW struct 83 * @buf: a virtual buffer to hold the manage MAC read response 84 * @buf_size: Size of the virtual buffer 85 * @cd: pointer to command details structure or NULL 86 * 87 * This function is used to return per PF station MAC address (0x0107). 88 * NOTE: Upon successful completion of this command, MAC address information 89 * is returned in user specified buffer. Please interpret user specified 90 * buffer as "manage_mac_read" response. 91 * Response such as various MAC addresses are stored in HW struct (port.mac) 92 * ice_aq_discover_caps is expected to be called before this function is called. 93 */ 94 static enum ice_status 95 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 96 struct ice_sq_cd *cd) 97 { 98 struct ice_aqc_manage_mac_read_resp *resp; 99 struct ice_aqc_manage_mac_read *cmd; 100 struct ice_aq_desc desc; 101 enum ice_status status; 102 u16 flags; 103 u8 i; 104 105 cmd = &desc.params.mac_read; 106 107 if (buf_size < sizeof(*resp)) 108 return ICE_ERR_BUF_TOO_SHORT; 109 110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 111 112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 113 if (status) 114 return status; 115 116 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 117 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 118 119 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 120 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 121 return ICE_ERR_CFG; 122 } 123 124 /* A single port can report up to two (LAN and WoL) addresses */ 125 for (i = 0; i < cmd->num_addr; i++) 126 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 127 ice_memcpy(hw->port_info->mac.lan_addr, 128 resp[i].mac_addr, ETH_ALEN, 129 ICE_DMA_TO_NONDMA); 130 ice_memcpy(hw->port_info->mac.perm_addr, 131 resp[i].mac_addr, 132 ETH_ALEN, ICE_DMA_TO_NONDMA); 133 break; 134 } 135 136 return ICE_SUCCESS; 137 } 138 139 /** 140 * ice_aq_get_phy_caps - returns PHY capabilities 141 * @pi: port information structure 142 * @qual_mods: report qualified modules 143 * @report_mode: report mode capabilities 144 * @pcaps: structure for PHY capabilities to be filled 145 * @cd: pointer to command details structure or NULL 146 * 147 * Returns the various PHY capabilities supported on the Port (0x0600) 148 */ 149 enum ice_status 150 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 151 struct ice_aqc_get_phy_caps_data *pcaps, 152 struct ice_sq_cd *cd) 153 { 154 struct ice_aqc_get_phy_caps *cmd; 155 u16 pcaps_size = sizeof(*pcaps); 156 struct ice_aq_desc desc; 157 enum ice_status status; 158 159 cmd = &desc.params.get_phy; 160 161 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 162 return ICE_ERR_PARAM; 163 164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 165 166 if (qual_mods) 167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 168 169 cmd->param0 |= CPU_TO_LE16(report_mode); 170 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); 171 172 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 173 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 174 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 175 } 176 177 return status; 178 } 179 180 /** 181 * ice_get_media_type - Gets media type 182 * @pi: port information structure 183 */ 184 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 185 { 186 struct ice_link_status *hw_link_info; 187 188 if (!pi) 189 return ICE_MEDIA_UNKNOWN; 190 191 hw_link_info = &pi->phy.link_info; 192 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 193 /* If more than one media type is selected, report unknown */ 194 return ICE_MEDIA_UNKNOWN; 195 196 if (hw_link_info->phy_type_low) { 197 switch (hw_link_info->phy_type_low) { 198 case ICE_PHY_TYPE_LOW_1000BASE_SX: 199 case ICE_PHY_TYPE_LOW_1000BASE_LX: 200 case ICE_PHY_TYPE_LOW_10GBASE_SR: 201 case ICE_PHY_TYPE_LOW_10GBASE_LR: 202 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 203 case ICE_PHY_TYPE_LOW_25GBASE_SR: 204 case ICE_PHY_TYPE_LOW_25GBASE_LR: 205 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 206 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 207 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 208 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 209 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 210 case ICE_PHY_TYPE_LOW_50GBASE_SR: 211 case ICE_PHY_TYPE_LOW_50GBASE_FR: 212 case ICE_PHY_TYPE_LOW_50GBASE_LR: 213 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 214 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 215 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 216 case ICE_PHY_TYPE_LOW_100GBASE_DR: 217 return ICE_MEDIA_FIBER; 218 case ICE_PHY_TYPE_LOW_100BASE_TX: 219 case ICE_PHY_TYPE_LOW_1000BASE_T: 220 case ICE_PHY_TYPE_LOW_2500BASE_T: 221 case ICE_PHY_TYPE_LOW_5GBASE_T: 222 case ICE_PHY_TYPE_LOW_10GBASE_T: 223 case ICE_PHY_TYPE_LOW_25GBASE_T: 224 return ICE_MEDIA_BASET; 225 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 226 case ICE_PHY_TYPE_LOW_25GBASE_CR: 227 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 228 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 229 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 230 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 231 case ICE_PHY_TYPE_LOW_50GBASE_CP: 232 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 233 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 234 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 235 return ICE_MEDIA_DA; 236 case ICE_PHY_TYPE_LOW_1000BASE_KX: 237 case ICE_PHY_TYPE_LOW_2500BASE_KX: 238 case ICE_PHY_TYPE_LOW_2500BASE_X: 239 case ICE_PHY_TYPE_LOW_5GBASE_KR: 240 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 241 case ICE_PHY_TYPE_LOW_25GBASE_KR: 242 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 243 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 244 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 246 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 247 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 248 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 249 return ICE_MEDIA_BACKPLANE; 250 } 251 } else { 252 switch (hw_link_info->phy_type_high) { 253 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 254 return ICE_MEDIA_BACKPLANE; 255 } 256 } 257 return ICE_MEDIA_UNKNOWN; 258 } 259 260 /** 261 * ice_aq_get_link_info 262 * @pi: port information structure 263 * @ena_lse: enable/disable LinkStatusEvent reporting 264 * @link: pointer to link status structure - optional 265 * @cd: pointer to command details structure or NULL 266 * 267 * Get Link Status (0x607). Returns the link status of the adapter. 268 */ 269 enum ice_status 270 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 271 struct ice_link_status *link, struct ice_sq_cd *cd) 272 { 273 struct ice_aqc_get_link_status_data link_data = { 0 }; 274 struct ice_aqc_get_link_status *resp; 275 struct ice_link_status *li_old, *li; 276 enum ice_media_type *hw_media_type; 277 struct ice_fc_info *hw_fc_info; 278 bool tx_pause, rx_pause; 279 struct ice_aq_desc desc; 280 enum ice_status status; 281 struct ice_hw *hw; 282 u16 cmd_flags; 283 284 if (!pi) 285 return ICE_ERR_PARAM; 286 hw = pi->hw; 287 li_old = &pi->phy.link_info_old; 288 hw_media_type = &pi->phy.media_type; 289 li = &pi->phy.link_info; 290 hw_fc_info = &pi->fc; 291 292 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 293 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 294 resp = &desc.params.get_link_status; 295 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 296 resp->lport_num = pi->lport; 297 298 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 299 300 if (status != ICE_SUCCESS) 301 return status; 302 303 /* save off old link status information */ 304 *li_old = *li; 305 306 /* update current link status information */ 307 li->link_speed = LE16_TO_CPU(link_data.link_speed); 308 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 309 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 310 *hw_media_type = ice_get_media_type(pi); 311 li->link_info = link_data.link_info; 312 li->an_info = link_data.an_info; 313 li->ext_info = link_data.ext_info; 314 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 315 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 316 li->topo_media_conflict = link_data.topo_media_conflict; 317 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 318 ICE_AQ_CFG_PACING_TYPE_M); 319 320 /* update fc info */ 321 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 322 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 323 if (tx_pause && rx_pause) 324 hw_fc_info->current_mode = ICE_FC_FULL; 325 else if (tx_pause) 326 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 327 else if (rx_pause) 328 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 329 else 330 hw_fc_info->current_mode = ICE_FC_NONE; 331 332 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 333 334 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed); 335 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n", 336 (unsigned long long)li->phy_type_low); 337 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n", 338 (unsigned long long)li->phy_type_high); 339 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type); 340 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info); 341 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info); 342 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info); 343 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena); 344 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size); 345 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing); 346 347 /* save link status information */ 348 if (link) 349 *link = *li; 350 351 /* flag cleared so calling functions don't call AQ again */ 352 pi->phy.get_link_info = false; 353 354 return ICE_SUCCESS; 355 } 356 357 /** 358 * ice_init_flex_flags 359 * @hw: pointer to the hardware structure 360 * @prof_id: Rx Descriptor Builder profile ID 361 * 362 * Function to initialize Rx flex flags 363 */ 364 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id) 365 { 366 u8 idx = 0; 367 368 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout: 369 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE 370 * flexiflags1[3:0] - Not used for flag programming 371 * flexiflags2[7:0] - Tunnel and VLAN types 372 * 2 invalid fields in last index 373 */ 374 switch (prof_id) { 375 /* Rx flex flags are currently programmed for the NIC profiles only. 376 * Different flag bit programming configurations can be added per 377 * profile as needed. 378 */ 379 case ICE_RXDID_FLEX_NIC: 380 case ICE_RXDID_FLEX_NIC_2: 381 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG, 382 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI, 383 ICE_FLG_FIN, idx++); 384 /* flex flag 1 is not used for flexi-flag programming, skipping 385 * these four FLG64 bits. 386 */ 387 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST, 388 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++); 389 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI, 390 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100, 391 ICE_FLG_EVLAN_x9100, idx++); 392 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100, 393 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC, 394 ICE_FLG_TNL0, idx++); 395 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2, 396 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx); 397 break; 398 399 default: 400 ice_debug(hw, ICE_DBG_INIT, 401 "Flag programming for profile ID %d not supported\n", 402 prof_id); 403 } 404 } 405 406 /** 407 * ice_init_flex_flds 408 * @hw: pointer to the hardware structure 409 * @prof_id: Rx Descriptor Builder profile ID 410 * 411 * Function to initialize flex descriptors 412 */ 413 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id) 414 { 415 enum ice_flex_mdid mdid; 416 417 switch (prof_id) { 418 case ICE_RXDID_FLEX_NIC: 419 case ICE_RXDID_FLEX_NIC_2: 420 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0); 421 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1); 422 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2); 423 424 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ? 425 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH; 426 427 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3); 428 429 ice_init_flex_flags(hw, prof_id); 430 break; 431 432 default: 433 ice_debug(hw, ICE_DBG_INIT, 434 "Field init for profile ID %d not supported\n", 435 prof_id); 436 } 437 } 438 439 /** 440 * ice_aq_set_mac_cfg 441 * @hw: pointer to the HW struct 442 * @max_frame_size: Maximum Frame Size to be supported 443 * @cd: pointer to command details structure or NULL 444 * 445 * Set MAC configuration (0x0603) 446 */ 447 enum ice_status 448 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 449 { 450 u16 fc_threshold_val, tx_timer_val; 451 struct ice_aqc_set_mac_cfg *cmd; 452 struct ice_aq_desc desc; 453 u32 reg_val; 454 455 cmd = &desc.params.set_mac_cfg; 456 457 if (max_frame_size == 0) 458 return ICE_ERR_PARAM; 459 460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 461 462 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 463 464 /* We read back the transmit timer and fc threshold value of 465 * LFC. Thus, we will use index = 466 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 467 * 468 * Also, because we are opearating on transmit timer and fc 469 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 470 */ 471 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 472 473 /* Retrieve the transmit timer */ 474 reg_val = rd32(hw, 475 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 476 tx_timer_val = reg_val & 477 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 478 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 479 480 /* Retrieve the fc threshold */ 481 reg_val = rd32(hw, 482 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 483 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0); 484 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val); 485 486 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 487 } 488 489 /** 490 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 491 * @hw: pointer to the HW struct 492 */ 493 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 494 { 495 struct ice_switch_info *sw; 496 497 hw->switch_info = (struct ice_switch_info *) 498 ice_malloc(hw, sizeof(*hw->switch_info)); 499 sw = hw->switch_info; 500 501 if (!sw) 502 return ICE_ERR_NO_MEMORY; 503 504 INIT_LIST_HEAD(&sw->vsi_list_map_head); 505 506 return ice_init_def_sw_recp(hw); 507 } 508 509 /** 510 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 511 * @hw: pointer to the HW struct 512 */ 513 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 514 { 515 struct ice_switch_info *sw = hw->switch_info; 516 struct ice_vsi_list_map_info *v_pos_map; 517 struct ice_vsi_list_map_info *v_tmp_map; 518 struct ice_sw_recipe *recps; 519 u8 i; 520 521 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 522 ice_vsi_list_map_info, list_entry) { 523 LIST_DEL(&v_pos_map->list_entry); 524 ice_free(hw, v_pos_map); 525 } 526 recps = hw->switch_info->recp_list; 527 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 528 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 529 530 recps[i].root_rid = i; 531 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 532 &recps[i].rg_list, ice_recp_grp_entry, 533 l_entry) { 534 LIST_DEL(&rg_entry->l_entry); 535 ice_free(hw, rg_entry); 536 } 537 538 if (recps[i].adv_rule) { 539 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 540 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 541 542 ice_destroy_lock(&recps[i].filt_rule_lock); 543 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 544 &recps[i].filt_rules, 545 ice_adv_fltr_mgmt_list_entry, 546 list_entry) { 547 LIST_DEL(&lst_itr->list_entry); 548 ice_free(hw, lst_itr->lkups); 549 ice_free(hw, lst_itr); 550 } 551 } else { 552 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 553 554 ice_destroy_lock(&recps[i].filt_rule_lock); 555 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 556 &recps[i].filt_rules, 557 ice_fltr_mgmt_list_entry, 558 list_entry) { 559 LIST_DEL(&lst_itr->list_entry); 560 ice_free(hw, lst_itr); 561 } 562 } 563 if (recps[i].root_buf) 564 ice_free(hw, recps[i].root_buf); 565 } 566 ice_rm_all_sw_replay_rule_info(hw); 567 ice_free(hw, sw->recp_list); 568 ice_free(hw, sw); 569 } 570 571 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \ 572 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry))) 573 #define ICE_FW_LOG_DESC_SIZE_MAX \ 574 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX) 575 576 /** 577 * ice_get_fw_log_cfg - get FW logging configuration 578 * @hw: pointer to the HW struct 579 */ 580 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 581 { 582 struct ice_aqc_fw_logging_data *config; 583 struct ice_aq_desc desc; 584 enum ice_status status; 585 u16 size; 586 587 size = ICE_FW_LOG_DESC_SIZE_MAX; 588 config = (struct ice_aqc_fw_logging_data *)ice_malloc(hw, size); 589 if (!config) 590 return ICE_ERR_NO_MEMORY; 591 592 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 593 594 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF); 595 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 596 597 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 598 if (!status) { 599 u16 i; 600 601 /* Save fw logging information into the HW structure */ 602 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 603 u16 v, m, flgs; 604 605 v = LE16_TO_CPU(config->entry[i]); 606 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 607 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 608 609 if (m < ICE_AQC_FW_LOG_ID_MAX) 610 hw->fw_log.evnts[m].cur = flgs; 611 } 612 } 613 614 ice_free(hw, config); 615 616 return status; 617 } 618 619 /** 620 * ice_cfg_fw_log - configure FW logging 621 * @hw: pointer to the HW struct 622 * @enable: enable certain FW logging events if true, disable all if false 623 * 624 * This function enables/disables the FW logging via Rx CQ events and a UART 625 * port based on predetermined configurations. FW logging via the Rx CQ can be 626 * enabled/disabled for individual PF's. However, FW logging via the UART can 627 * only be enabled/disabled for all PFs on the same device. 628 * 629 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 630 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 631 * before initializing the device. 632 * 633 * When re/configuring FW logging, callers need to update the "cfg" elements of 634 * the hw->fw_log.evnts array with the desired logging event configurations for 635 * modules of interest. When disabling FW logging completely, the callers can 636 * just pass false in the "enable" parameter. On completion, the function will 637 * update the "cur" element of the hw->fw_log.evnts array with the resulting 638 * logging event configurations of the modules that are being re/configured. FW 639 * logging modules that are not part of a reconfiguration operation retain their 640 * previous states. 641 * 642 * Before resetting the device, it is recommended that the driver disables FW 643 * logging before shutting down the control queue. When disabling FW logging 644 * ("enable" = false), the latest configurations of FW logging events stored in 645 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 646 * a device reset. 647 * 648 * When enabling FW logging to emit log messages via the Rx CQ during the 649 * device's initialization phase, a mechanism alternative to interrupt handlers 650 * needs to be used to extract FW log messages from the Rx CQ periodically and 651 * to prevent the Rx CQ from being full and stalling other types of control 652 * messages from FW to SW. Interrupts are typically disabled during the device's 653 * initialization phase. 654 */ 655 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 656 { 657 struct ice_aqc_fw_logging_data *data = NULL; 658 struct ice_aqc_fw_logging *cmd; 659 enum ice_status status = ICE_SUCCESS; 660 u16 i, chgs = 0, len = 0; 661 struct ice_aq_desc desc; 662 u8 actv_evnts = 0; 663 void *buf = NULL; 664 665 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 666 return ICE_SUCCESS; 667 668 /* Disable FW logging only when the control queue is still responsive */ 669 if (!enable && 670 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 671 return ICE_SUCCESS; 672 673 /* Get current FW log settings */ 674 status = ice_get_fw_log_cfg(hw); 675 if (status) 676 return status; 677 678 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 679 cmd = &desc.params.fw_logging; 680 681 /* Indicate which controls are valid */ 682 if (hw->fw_log.cq_en) 683 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 684 685 if (hw->fw_log.uart_en) 686 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 687 688 if (enable) { 689 /* Fill in an array of entries with FW logging modules and 690 * logging events being reconfigured. 691 */ 692 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 693 u16 val; 694 695 /* Keep track of enabled event types */ 696 actv_evnts |= hw->fw_log.evnts[i].cfg; 697 698 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 699 continue; 700 701 if (!data) { 702 data = (struct ice_aqc_fw_logging_data *) 703 ice_malloc(hw, 704 ICE_FW_LOG_DESC_SIZE_MAX); 705 if (!data) 706 return ICE_ERR_NO_MEMORY; 707 } 708 709 val = i << ICE_AQC_FW_LOG_ID_S; 710 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 711 data->entry[chgs++] = CPU_TO_LE16(val); 712 } 713 714 /* Only enable FW logging if at least one module is specified. 715 * If FW logging is currently enabled but all modules are not 716 * enabled to emit log messages, disable FW logging altogether. 717 */ 718 if (actv_evnts) { 719 /* Leave if there is effectively no change */ 720 if (!chgs) 721 goto out; 722 723 if (hw->fw_log.cq_en) 724 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 725 726 if (hw->fw_log.uart_en) 727 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 728 729 buf = data; 730 len = ICE_FW_LOG_DESC_SIZE(chgs); 731 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 732 } 733 } 734 735 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 736 if (!status) { 737 /* Update the current configuration to reflect events enabled. 738 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 739 * logging mode is enabled for the device. They do not reflect 740 * actual modules being enabled to emit log messages. So, their 741 * values remain unchanged even when all modules are disabled. 742 */ 743 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 744 745 hw->fw_log.actv_evnts = actv_evnts; 746 for (i = 0; i < cnt; i++) { 747 u16 v, m; 748 749 if (!enable) { 750 /* When disabling all FW logging events as part 751 * of device's de-initialization, the original 752 * configurations are retained, and can be used 753 * to reconfigure FW logging later if the device 754 * is re-initialized. 755 */ 756 hw->fw_log.evnts[i].cur = 0; 757 continue; 758 } 759 760 v = LE16_TO_CPU(data->entry[i]); 761 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 762 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 763 } 764 } 765 766 out: 767 if (data) 768 ice_free(hw, data); 769 770 return status; 771 } 772 773 /** 774 * ice_output_fw_log 775 * @hw: pointer to the HW struct 776 * @desc: pointer to the AQ message descriptor 777 * @buf: pointer to the buffer accompanying the AQ message 778 * 779 * Formats a FW Log message and outputs it via the standard driver logs. 780 */ 781 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 782 { 783 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 784 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 785 LE16_TO_CPU(desc->datalen)); 786 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 787 } 788 789 /** 790 * ice_get_itr_intrl_gran - determine int/intrl granularity 791 * @hw: pointer to the HW struct 792 * 793 * Determines the itr/intrl granularities based on the maximum aggregate 794 * bandwidth according to the device's configuration during power-on. 795 */ 796 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 797 { 798 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 799 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 800 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 801 802 switch (max_agg_bw) { 803 case ICE_MAX_AGG_BW_200G: 804 case ICE_MAX_AGG_BW_100G: 805 case ICE_MAX_AGG_BW_50G: 806 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 807 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 808 break; 809 case ICE_MAX_AGG_BW_25G: 810 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 811 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 812 break; 813 } 814 } 815 816 /** 817 * ice_init_hw - main hardware initialization routine 818 * @hw: pointer to the hardware structure 819 */ 820 enum ice_status ice_init_hw(struct ice_hw *hw) 821 { 822 struct ice_aqc_get_phy_caps_data *pcaps; 823 enum ice_status status; 824 u16 mac_buf_len; 825 void *mac_buf; 826 827 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 828 829 830 /* Set MAC type based on DeviceID */ 831 status = ice_set_mac_type(hw); 832 if (status) 833 return status; 834 835 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 836 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 837 PF_FUNC_RID_FUNCTION_NUMBER_S; 838 839 840 status = ice_reset(hw, ICE_RESET_PFR); 841 if (status) 842 return status; 843 844 ice_get_itr_intrl_gran(hw); 845 846 847 status = ice_create_all_ctrlq(hw); 848 if (status) 849 goto err_unroll_cqinit; 850 851 /* Enable FW logging. Not fatal if this fails. */ 852 status = ice_cfg_fw_log(hw, true); 853 if (status) 854 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 855 856 status = ice_clear_pf_cfg(hw); 857 if (status) 858 goto err_unroll_cqinit; 859 860 /* Set bit to enable Flow Director filters */ 861 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 862 INIT_LIST_HEAD(&hw->fdir_list_head); 863 864 ice_clear_pxe_mode(hw); 865 866 status = ice_init_nvm(hw); 867 if (status) 868 goto err_unroll_cqinit; 869 870 status = ice_get_caps(hw); 871 if (status) 872 goto err_unroll_cqinit; 873 874 hw->port_info = (struct ice_port_info *) 875 ice_malloc(hw, sizeof(*hw->port_info)); 876 if (!hw->port_info) { 877 status = ICE_ERR_NO_MEMORY; 878 goto err_unroll_cqinit; 879 } 880 881 /* set the back pointer to HW */ 882 hw->port_info->hw = hw; 883 884 /* Initialize port_info struct with switch configuration data */ 885 status = ice_get_initial_sw_cfg(hw); 886 if (status) 887 goto err_unroll_alloc; 888 889 hw->evb_veb = true; 890 891 /* Query the allocated resources for Tx scheduler */ 892 status = ice_sched_query_res_alloc(hw); 893 if (status) { 894 ice_debug(hw, ICE_DBG_SCHED, 895 "Failed to get scheduler allocated resources\n"); 896 goto err_unroll_alloc; 897 } 898 899 900 /* Initialize port_info struct with scheduler data */ 901 status = ice_sched_init_port(hw->port_info); 902 if (status) 903 goto err_unroll_sched; 904 905 pcaps = (struct ice_aqc_get_phy_caps_data *) 906 ice_malloc(hw, sizeof(*pcaps)); 907 if (!pcaps) { 908 status = ICE_ERR_NO_MEMORY; 909 goto err_unroll_sched; 910 } 911 912 /* Initialize port_info struct with PHY capabilities */ 913 status = ice_aq_get_phy_caps(hw->port_info, false, 914 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 915 ice_free(hw, pcaps); 916 if (status) 917 goto err_unroll_sched; 918 919 /* Initialize port_info struct with link information */ 920 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 921 if (status) 922 goto err_unroll_sched; 923 /* need a valid SW entry point to build a Tx tree */ 924 if (!hw->sw_entry_point_layer) { 925 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 926 status = ICE_ERR_CFG; 927 goto err_unroll_sched; 928 } 929 INIT_LIST_HEAD(&hw->agg_list); 930 /* Initialize max burst size */ 931 if (!hw->max_burst_size) 932 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 933 934 status = ice_init_fltr_mgmt_struct(hw); 935 if (status) 936 goto err_unroll_sched; 937 938 939 /* Get MAC information */ 940 /* A single port can report up to two (LAN and WoL) addresses */ 941 mac_buf = ice_calloc(hw, 2, 942 sizeof(struct ice_aqc_manage_mac_read_resp)); 943 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 944 945 if (!mac_buf) { 946 status = ICE_ERR_NO_MEMORY; 947 goto err_unroll_fltr_mgmt_struct; 948 } 949 950 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 951 ice_free(hw, mac_buf); 952 953 if (status) 954 goto err_unroll_fltr_mgmt_struct; 955 956 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC); 957 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2); 958 /* Obtain counter base index which would be used by flow director */ 959 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 960 if (status) 961 goto err_unroll_fltr_mgmt_struct; 962 status = ice_init_hw_tbls(hw); 963 if (status) 964 goto err_unroll_fltr_mgmt_struct; 965 return ICE_SUCCESS; 966 967 err_unroll_fltr_mgmt_struct: 968 ice_cleanup_fltr_mgmt_struct(hw); 969 err_unroll_sched: 970 ice_sched_cleanup_all(hw); 971 err_unroll_alloc: 972 ice_free(hw, hw->port_info); 973 hw->port_info = NULL; 974 err_unroll_cqinit: 975 ice_destroy_all_ctrlq(hw); 976 return status; 977 } 978 979 /** 980 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 981 * @hw: pointer to the hardware structure 982 * 983 * This should be called only during nominal operation, not as a result of 984 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 985 * applicable initializations if it fails for any reason. 986 */ 987 void ice_deinit_hw(struct ice_hw *hw) 988 { 989 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 990 ice_cleanup_fltr_mgmt_struct(hw); 991 992 ice_sched_cleanup_all(hw); 993 ice_sched_clear_agg(hw); 994 ice_free_seg(hw); 995 ice_free_hw_tbls(hw); 996 997 if (hw->port_info) { 998 ice_free(hw, hw->port_info); 999 hw->port_info = NULL; 1000 } 1001 1002 /* Attempt to disable FW logging before shutting down control queues */ 1003 ice_cfg_fw_log(hw, false); 1004 ice_destroy_all_ctrlq(hw); 1005 1006 /* Clear VSI contexts if not already cleared */ 1007 ice_clear_all_vsi_ctx(hw); 1008 } 1009 1010 /** 1011 * ice_check_reset - Check to see if a global reset is complete 1012 * @hw: pointer to the hardware structure 1013 */ 1014 enum ice_status ice_check_reset(struct ice_hw *hw) 1015 { 1016 u32 cnt, reg = 0, grst_delay; 1017 1018 /* Poll for Device Active state in case a recent CORER, GLOBR, 1019 * or EMPR has occurred. The grst delay value is in 100ms units. 1020 * Add 1sec for outstanding AQ commands that can take a long time. 1021 */ 1022 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1023 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1024 1025 for (cnt = 0; cnt < grst_delay; cnt++) { 1026 ice_msec_delay(100, true); 1027 reg = rd32(hw, GLGEN_RSTAT); 1028 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1029 break; 1030 } 1031 1032 if (cnt == grst_delay) { 1033 ice_debug(hw, ICE_DBG_INIT, 1034 "Global reset polling failed to complete.\n"); 1035 return ICE_ERR_RESET_FAILED; 1036 } 1037 1038 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ 1039 GLNVM_ULD_GLOBR_DONE_M) 1040 1041 /* Device is Active; check Global Reset processes are done */ 1042 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1043 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; 1044 if (reg == ICE_RESET_DONE_MASK) { 1045 ice_debug(hw, ICE_DBG_INIT, 1046 "Global reset processes done. %d\n", cnt); 1047 break; 1048 } 1049 ice_msec_delay(10, true); 1050 } 1051 1052 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1053 ice_debug(hw, ICE_DBG_INIT, 1054 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1055 reg); 1056 return ICE_ERR_RESET_FAILED; 1057 } 1058 1059 return ICE_SUCCESS; 1060 } 1061 1062 /** 1063 * ice_pf_reset - Reset the PF 1064 * @hw: pointer to the hardware structure 1065 * 1066 * If a global reset has been triggered, this function checks 1067 * for its completion and then issues the PF reset 1068 */ 1069 static enum ice_status ice_pf_reset(struct ice_hw *hw) 1070 { 1071 u32 cnt, reg; 1072 1073 /* If at function entry a global reset was already in progress, i.e. 1074 * state is not 'device active' or any of the reset done bits are not 1075 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1076 * global reset is done. 1077 */ 1078 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1079 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1080 /* poll on global reset currently in progress until done */ 1081 if (ice_check_reset(hw)) 1082 return ICE_ERR_RESET_FAILED; 1083 1084 return ICE_SUCCESS; 1085 } 1086 1087 /* Reset the PF */ 1088 reg = rd32(hw, PFGEN_CTRL); 1089 1090 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1091 1092 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1093 reg = rd32(hw, PFGEN_CTRL); 1094 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1095 break; 1096 1097 ice_msec_delay(1, true); 1098 } 1099 1100 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1101 ice_debug(hw, ICE_DBG_INIT, 1102 "PF reset polling failed to complete.\n"); 1103 return ICE_ERR_RESET_FAILED; 1104 } 1105 1106 return ICE_SUCCESS; 1107 } 1108 1109 /** 1110 * ice_reset - Perform different types of reset 1111 * @hw: pointer to the hardware structure 1112 * @req: reset request 1113 * 1114 * This function triggers a reset as specified by the req parameter. 1115 * 1116 * Note: 1117 * If anything other than a PF reset is triggered, PXE mode is restored. 1118 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1119 * interface has been restored in the rebuild flow. 1120 */ 1121 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1122 { 1123 u32 val = 0; 1124 1125 switch (req) { 1126 case ICE_RESET_PFR: 1127 return ice_pf_reset(hw); 1128 case ICE_RESET_CORER: 1129 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1130 val = GLGEN_RTRIG_CORER_M; 1131 break; 1132 case ICE_RESET_GLOBR: 1133 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1134 val = GLGEN_RTRIG_GLOBR_M; 1135 break; 1136 default: 1137 return ICE_ERR_PARAM; 1138 } 1139 1140 val |= rd32(hw, GLGEN_RTRIG); 1141 wr32(hw, GLGEN_RTRIG, val); 1142 ice_flush(hw); 1143 1144 1145 /* wait for the FW to be ready */ 1146 return ice_check_reset(hw); 1147 } 1148 1149 1150 1151 /** 1152 * ice_copy_rxq_ctx_to_hw 1153 * @hw: pointer to the hardware structure 1154 * @ice_rxq_ctx: pointer to the rxq context 1155 * @rxq_index: the index of the Rx queue 1156 * 1157 * Copies rxq context from dense structure to HW register space 1158 */ 1159 static enum ice_status 1160 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1161 { 1162 u8 i; 1163 1164 if (!ice_rxq_ctx) 1165 return ICE_ERR_BAD_PTR; 1166 1167 if (rxq_index > QRX_CTRL_MAX_INDEX) 1168 return ICE_ERR_PARAM; 1169 1170 /* Copy each dword separately to HW */ 1171 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1172 wr32(hw, QRX_CONTEXT(i, rxq_index), 1173 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1174 1175 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1176 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1177 } 1178 1179 return ICE_SUCCESS; 1180 } 1181 1182 /* LAN Rx Queue Context */ 1183 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1184 /* Field Width LSB */ 1185 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1186 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1187 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1188 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1189 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1190 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1191 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1192 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1193 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1194 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1195 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1196 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1197 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1198 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1199 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1200 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1201 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1202 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1203 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1204 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1205 { 0 } 1206 }; 1207 1208 /** 1209 * ice_write_rxq_ctx 1210 * @hw: pointer to the hardware structure 1211 * @rlan_ctx: pointer to the rxq context 1212 * @rxq_index: the index of the Rx queue 1213 * 1214 * Converts rxq context from sparse to dense structure and then writes 1215 * it to HW register space and enables the hardware to prefetch descriptors 1216 * instead of only fetching them on demand 1217 */ 1218 enum ice_status 1219 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1220 u32 rxq_index) 1221 { 1222 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1223 1224 if (!rlan_ctx) 1225 return ICE_ERR_BAD_PTR; 1226 1227 rlan_ctx->prefena = 1; 1228 1229 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1230 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1231 } 1232 1233 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER) 1234 /** 1235 * ice_clear_rxq_ctx 1236 * @hw: pointer to the hardware structure 1237 * @rxq_index: the index of the Rx queue to clear 1238 * 1239 * Clears rxq context in HW register space 1240 */ 1241 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1242 { 1243 u8 i; 1244 1245 if (rxq_index > QRX_CTRL_MAX_INDEX) 1246 return ICE_ERR_PARAM; 1247 1248 /* Clear each dword register separately */ 1249 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1250 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1251 1252 return ICE_SUCCESS; 1253 } 1254 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */ 1255 1256 /* LAN Tx Queue Context */ 1257 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1258 /* Field Width LSB */ 1259 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1260 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1261 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1262 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1263 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1264 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1265 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1266 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1267 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1268 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1269 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1270 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1271 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1272 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1273 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1274 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1275 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1276 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1277 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1278 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1279 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1280 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1281 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1282 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1283 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1284 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1285 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1286 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1287 { 0 } 1288 }; 1289 1290 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER) 1291 /** 1292 * ice_copy_tx_cmpltnq_ctx_to_hw 1293 * @hw: pointer to the hardware structure 1294 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1295 * @tx_cmpltnq_index: the index of the completion queue 1296 * 1297 * Copies Tx completion queue context from dense structure to HW register space 1298 */ 1299 static enum ice_status 1300 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1301 u32 tx_cmpltnq_index) 1302 { 1303 u8 i; 1304 1305 if (!ice_tx_cmpltnq_ctx) 1306 return ICE_ERR_BAD_PTR; 1307 1308 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1309 return ICE_ERR_PARAM; 1310 1311 /* Copy each dword separately to HW */ 1312 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1313 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1314 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1315 1316 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1317 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1318 } 1319 1320 return ICE_SUCCESS; 1321 } 1322 1323 /* LAN Tx Completion Queue Context */ 1324 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1325 /* Field Width LSB */ 1326 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1327 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1328 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1329 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1330 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1331 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1332 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1333 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1334 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1335 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1336 { 0 } 1337 }; 1338 1339 /** 1340 * ice_write_tx_cmpltnq_ctx 1341 * @hw: pointer to the hardware structure 1342 * @tx_cmpltnq_ctx: pointer to the completion queue context 1343 * @tx_cmpltnq_index: the index of the completion queue 1344 * 1345 * Converts completion queue context from sparse to dense structure and then 1346 * writes it to HW register space 1347 */ 1348 enum ice_status 1349 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1350 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1351 u32 tx_cmpltnq_index) 1352 { 1353 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1354 1355 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1356 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1357 } 1358 1359 /** 1360 * ice_clear_tx_cmpltnq_ctx 1361 * @hw: pointer to the hardware structure 1362 * @tx_cmpltnq_index: the index of the completion queue to clear 1363 * 1364 * Clears Tx completion queue context in HW register space 1365 */ 1366 enum ice_status 1367 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1368 { 1369 u8 i; 1370 1371 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1372 return ICE_ERR_PARAM; 1373 1374 /* Clear each dword register separately */ 1375 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1376 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1377 1378 return ICE_SUCCESS; 1379 } 1380 1381 /** 1382 * ice_copy_tx_drbell_q_ctx_to_hw 1383 * @hw: pointer to the hardware structure 1384 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1385 * @tx_drbell_q_index: the index of the doorbell queue 1386 * 1387 * Copies doorbell queue context from dense structure to HW register space 1388 */ 1389 static enum ice_status 1390 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1391 u32 tx_drbell_q_index) 1392 { 1393 u8 i; 1394 1395 if (!ice_tx_drbell_q_ctx) 1396 return ICE_ERR_BAD_PTR; 1397 1398 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1399 return ICE_ERR_PARAM; 1400 1401 /* Copy each dword separately to HW */ 1402 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1403 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1404 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1405 1406 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1407 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1408 } 1409 1410 return ICE_SUCCESS; 1411 } 1412 1413 /* LAN Tx Doorbell Queue Context info */ 1414 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1415 /* Field Width LSB */ 1416 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1417 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1418 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1419 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1420 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1421 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1422 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1423 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1424 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1425 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1426 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1427 { 0 } 1428 }; 1429 1430 /** 1431 * ice_write_tx_drbell_q_ctx 1432 * @hw: pointer to the hardware structure 1433 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1434 * @tx_drbell_q_index: the index of the doorbell queue 1435 * 1436 * Converts doorbell queue context from sparse to dense structure and then 1437 * writes it to HW register space 1438 */ 1439 enum ice_status 1440 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1441 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1442 u32 tx_drbell_q_index) 1443 { 1444 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1445 1446 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info); 1447 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1448 } 1449 1450 /** 1451 * ice_clear_tx_drbell_q_ctx 1452 * @hw: pointer to the hardware structure 1453 * @tx_drbell_q_index: the index of the doorbell queue to clear 1454 * 1455 * Clears doorbell queue context in HW register space 1456 */ 1457 enum ice_status 1458 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1459 { 1460 u8 i; 1461 1462 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1463 return ICE_ERR_PARAM; 1464 1465 /* Clear each dword register separately */ 1466 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1467 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1468 1469 return ICE_SUCCESS; 1470 } 1471 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */ 1472 1473 1474 /* FW Admin Queue command wrappers */ 1475 1476 /** 1477 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1478 * @hw: pointer to the HW struct 1479 * @desc: descriptor describing the command 1480 * @buf: buffer to use for indirect commands (NULL for direct commands) 1481 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1482 * @cd: pointer to command details structure 1483 * 1484 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1485 */ 1486 enum ice_status 1487 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1488 u16 buf_size, struct ice_sq_cd *cd) 1489 { 1490 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1491 } 1492 1493 /** 1494 * ice_aq_get_fw_ver 1495 * @hw: pointer to the HW struct 1496 * @cd: pointer to command details structure or NULL 1497 * 1498 * Get the firmware version (0x0001) from the admin queue commands 1499 */ 1500 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1501 { 1502 struct ice_aqc_get_ver *resp; 1503 struct ice_aq_desc desc; 1504 enum ice_status status; 1505 1506 resp = &desc.params.get_ver; 1507 1508 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1509 1510 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1511 1512 if (!status) { 1513 hw->fw_branch = resp->fw_branch; 1514 hw->fw_maj_ver = resp->fw_major; 1515 hw->fw_min_ver = resp->fw_minor; 1516 hw->fw_patch = resp->fw_patch; 1517 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1518 hw->api_branch = resp->api_branch; 1519 hw->api_maj_ver = resp->api_major; 1520 hw->api_min_ver = resp->api_minor; 1521 hw->api_patch = resp->api_patch; 1522 } 1523 1524 return status; 1525 } 1526 1527 /** 1528 * ice_aq_send_driver_ver 1529 * @hw: pointer to the HW struct 1530 * @dv: driver's major, minor version 1531 * @cd: pointer to command details structure or NULL 1532 * 1533 * Send the driver version (0x0002) to the firmware 1534 */ 1535 enum ice_status 1536 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1537 struct ice_sq_cd *cd) 1538 { 1539 struct ice_aqc_driver_ver *cmd; 1540 struct ice_aq_desc desc; 1541 u16 len; 1542 1543 cmd = &desc.params.driver_ver; 1544 1545 if (!dv) 1546 return ICE_ERR_PARAM; 1547 1548 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1549 1550 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1551 cmd->major_ver = dv->major_ver; 1552 cmd->minor_ver = dv->minor_ver; 1553 cmd->build_ver = dv->build_ver; 1554 cmd->subbuild_ver = dv->subbuild_ver; 1555 1556 len = 0; 1557 while (len < sizeof(dv->driver_string) && 1558 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1559 len++; 1560 1561 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1562 } 1563 1564 /** 1565 * ice_aq_q_shutdown 1566 * @hw: pointer to the HW struct 1567 * @unloading: is the driver unloading itself 1568 * 1569 * Tell the Firmware that we're shutting down the AdminQ and whether 1570 * or not the driver is unloading as well (0x0003). 1571 */ 1572 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1573 { 1574 struct ice_aqc_q_shutdown *cmd; 1575 struct ice_aq_desc desc; 1576 1577 cmd = &desc.params.q_shutdown; 1578 1579 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1580 1581 if (unloading) 1582 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1583 1584 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1585 } 1586 1587 /** 1588 * ice_aq_req_res 1589 * @hw: pointer to the HW struct 1590 * @res: resource ID 1591 * @access: access type 1592 * @sdp_number: resource number 1593 * @timeout: the maximum time in ms that the driver may hold the resource 1594 * @cd: pointer to command details structure or NULL 1595 * 1596 * Requests common resource using the admin queue commands (0x0008). 1597 * When attempting to acquire the Global Config Lock, the driver can 1598 * learn of three states: 1599 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1600 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1601 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1602 * successfully downloaded the package; the driver does 1603 * not have to download the package and can continue 1604 * loading 1605 * 1606 * Note that if the caller is in an acquire lock, perform action, release lock 1607 * phase of operation, it is possible that the FW may detect a timeout and issue 1608 * a CORER. In this case, the driver will receive a CORER interrupt and will 1609 * have to determine its cause. The calling thread that is handling this flow 1610 * will likely get an error propagated back to it indicating the Download 1611 * Package, Update Package or the Release Resource AQ commands timed out. 1612 */ 1613 static enum ice_status 1614 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1615 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1616 struct ice_sq_cd *cd) 1617 { 1618 struct ice_aqc_req_res *cmd_resp; 1619 struct ice_aq_desc desc; 1620 enum ice_status status; 1621 1622 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1623 1624 cmd_resp = &desc.params.res_owner; 1625 1626 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1627 1628 cmd_resp->res_id = CPU_TO_LE16(res); 1629 cmd_resp->access_type = CPU_TO_LE16(access); 1630 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1631 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1632 *timeout = 0; 1633 1634 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1635 1636 /* The completion specifies the maximum time in ms that the driver 1637 * may hold the resource in the Timeout field. 1638 */ 1639 1640 /* Global config lock response utilizes an additional status field. 1641 * 1642 * If the Global config lock resource is held by some other driver, the 1643 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1644 * and the timeout field indicates the maximum time the current owner 1645 * of the resource has to free it. 1646 */ 1647 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1648 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1649 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1650 return ICE_SUCCESS; 1651 } else if (LE16_TO_CPU(cmd_resp->status) == 1652 ICE_AQ_RES_GLBL_IN_PROG) { 1653 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1654 return ICE_ERR_AQ_ERROR; 1655 } else if (LE16_TO_CPU(cmd_resp->status) == 1656 ICE_AQ_RES_GLBL_DONE) { 1657 return ICE_ERR_AQ_NO_WORK; 1658 } 1659 1660 /* invalid FW response, force a timeout immediately */ 1661 *timeout = 0; 1662 return ICE_ERR_AQ_ERROR; 1663 } 1664 1665 /* If the resource is held by some other driver, the command completes 1666 * with a busy return value and the timeout field indicates the maximum 1667 * time the current owner of the resource has to free it. 1668 */ 1669 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1670 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1671 1672 return status; 1673 } 1674 1675 /** 1676 * ice_aq_release_res 1677 * @hw: pointer to the HW struct 1678 * @res: resource ID 1679 * @sdp_number: resource number 1680 * @cd: pointer to command details structure or NULL 1681 * 1682 * release common resource using the admin queue commands (0x0009) 1683 */ 1684 static enum ice_status 1685 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1686 struct ice_sq_cd *cd) 1687 { 1688 struct ice_aqc_req_res *cmd; 1689 struct ice_aq_desc desc; 1690 1691 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1692 1693 cmd = &desc.params.res_owner; 1694 1695 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1696 1697 cmd->res_id = CPU_TO_LE16(res); 1698 cmd->res_number = CPU_TO_LE32(sdp_number); 1699 1700 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1701 } 1702 1703 /** 1704 * ice_acquire_res 1705 * @hw: pointer to the HW structure 1706 * @res: resource ID 1707 * @access: access type (read or write) 1708 * @timeout: timeout in milliseconds 1709 * 1710 * This function will attempt to acquire the ownership of a resource. 1711 */ 1712 enum ice_status 1713 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1714 enum ice_aq_res_access_type access, u32 timeout) 1715 { 1716 #define ICE_RES_POLLING_DELAY_MS 10 1717 u32 delay = ICE_RES_POLLING_DELAY_MS; 1718 u32 time_left = timeout; 1719 enum ice_status status; 1720 1721 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1722 1723 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1724 1725 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1726 * previously acquired the resource and performed any necessary updates; 1727 * in this case the caller does not obtain the resource and has no 1728 * further work to do. 1729 */ 1730 if (status == ICE_ERR_AQ_NO_WORK) 1731 goto ice_acquire_res_exit; 1732 1733 if (status) 1734 ice_debug(hw, ICE_DBG_RES, 1735 "resource %d acquire type %d failed.\n", res, access); 1736 1737 /* If necessary, poll until the current lock owner timeouts */ 1738 timeout = time_left; 1739 while (status && timeout && time_left) { 1740 ice_msec_delay(delay, true); 1741 timeout = (timeout > delay) ? timeout - delay : 0; 1742 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1743 1744 if (status == ICE_ERR_AQ_NO_WORK) 1745 /* lock free, but no work to do */ 1746 break; 1747 1748 if (!status) 1749 /* lock acquired */ 1750 break; 1751 } 1752 if (status && status != ICE_ERR_AQ_NO_WORK) 1753 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1754 1755 ice_acquire_res_exit: 1756 if (status == ICE_ERR_AQ_NO_WORK) { 1757 if (access == ICE_RES_WRITE) 1758 ice_debug(hw, ICE_DBG_RES, 1759 "resource indicates no work to do.\n"); 1760 else 1761 ice_debug(hw, ICE_DBG_RES, 1762 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1763 } 1764 return status; 1765 } 1766 1767 /** 1768 * ice_release_res 1769 * @hw: pointer to the HW structure 1770 * @res: resource ID 1771 * 1772 * This function will release a resource using the proper Admin Command. 1773 */ 1774 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1775 { 1776 enum ice_status status; 1777 u32 total_delay = 0; 1778 1779 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1780 1781 status = ice_aq_release_res(hw, res, 0, NULL); 1782 1783 /* there are some rare cases when trying to release the resource 1784 * results in an admin queue timeout, so handle them correctly 1785 */ 1786 while ((status == ICE_ERR_AQ_TIMEOUT) && 1787 (total_delay < hw->adminq.sq_cmd_timeout)) { 1788 ice_msec_delay(1, true); 1789 status = ice_aq_release_res(hw, res, 0, NULL); 1790 total_delay++; 1791 } 1792 } 1793 1794 /** 1795 * ice_aq_alloc_free_res - command to allocate/free resources 1796 * @hw: pointer to the HW struct 1797 * @num_entries: number of resource entries in buffer 1798 * @buf: Indirect buffer to hold data parameters and response 1799 * @buf_size: size of buffer for indirect commands 1800 * @opc: pass in the command opcode 1801 * @cd: pointer to command details structure or NULL 1802 * 1803 * Helper function to allocate/free resources using the admin queue commands 1804 */ 1805 enum ice_status 1806 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1807 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1808 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1809 { 1810 struct ice_aqc_alloc_free_res_cmd *cmd; 1811 struct ice_aq_desc desc; 1812 1813 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1814 1815 cmd = &desc.params.sw_res_ctrl; 1816 1817 if (!buf) 1818 return ICE_ERR_PARAM; 1819 1820 if (buf_size < (num_entries * sizeof(buf->elem[0]))) 1821 return ICE_ERR_PARAM; 1822 1823 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1824 1825 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1826 1827 cmd->num_entries = CPU_TO_LE16(num_entries); 1828 1829 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1830 } 1831 1832 /** 1833 * ice_alloc_hw_res - allocate resource 1834 * @hw: pointer to the HW struct 1835 * @type: type of resource 1836 * @num: number of resources to allocate 1837 * @btm: allocate from bottom 1838 * @res: pointer to array that will receive the resources 1839 */ 1840 enum ice_status 1841 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1842 { 1843 struct ice_aqc_alloc_free_res_elem *buf; 1844 enum ice_status status; 1845 u16 buf_len; 1846 1847 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1); 1848 buf = (struct ice_aqc_alloc_free_res_elem *) 1849 ice_malloc(hw, buf_len); 1850 if (!buf) 1851 return ICE_ERR_NO_MEMORY; 1852 1853 /* Prepare buffer to allocate resource. */ 1854 buf->num_elems = CPU_TO_LE16(num); 1855 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1856 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1857 if (btm) 1858 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1859 1860 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1861 ice_aqc_opc_alloc_res, NULL); 1862 if (status) 1863 goto ice_alloc_res_exit; 1864 1865 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num, 1866 ICE_NONDMA_TO_NONDMA); 1867 1868 ice_alloc_res_exit: 1869 ice_free(hw, buf); 1870 return status; 1871 } 1872 1873 /** 1874 * ice_free_hw_res - free allocated HW resource 1875 * @hw: pointer to the HW struct 1876 * @type: type of resource to free 1877 * @num: number of resources 1878 * @res: pointer to array that contains the resources to free 1879 */ 1880 enum ice_status 1881 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1882 { 1883 struct ice_aqc_alloc_free_res_elem *buf; 1884 enum ice_status status; 1885 u16 buf_len; 1886 1887 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1); 1888 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1889 if (!buf) 1890 return ICE_ERR_NO_MEMORY; 1891 1892 /* Prepare buffer to free resource. */ 1893 buf->num_elems = CPU_TO_LE16(num); 1894 buf->res_type = CPU_TO_LE16(type); 1895 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num, 1896 ICE_NONDMA_TO_NONDMA); 1897 1898 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1899 ice_aqc_opc_free_res, NULL); 1900 if (status) 1901 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1902 1903 ice_free(hw, buf); 1904 return status; 1905 } 1906 1907 /** 1908 * ice_get_num_per_func - determine number of resources per PF 1909 * @hw: pointer to the HW structure 1910 * @max: value to be evenly split between each PF 1911 * 1912 * Determine the number of valid functions by going through the bitmap returned 1913 * from parsing capabilities and use this to calculate the number of resources 1914 * per PF based on the max value passed in. 1915 */ 1916 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1917 { 1918 u8 funcs; 1919 1920 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1921 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 1922 ICE_CAPS_VALID_FUNCS_M); 1923 1924 if (!funcs) 1925 return 0; 1926 1927 return max / funcs; 1928 } 1929 1930 /** 1931 * ice_parse_caps - parse function/device capabilities 1932 * @hw: pointer to the HW struct 1933 * @buf: pointer to a buffer containing function/device capability records 1934 * @cap_count: number of capability records in the list 1935 * @opc: type of capabilities list to parse 1936 * 1937 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1938 */ 1939 static void 1940 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1941 enum ice_adminq_opc opc) 1942 { 1943 struct ice_aqc_list_caps_elem *cap_resp; 1944 struct ice_hw_func_caps *func_p = NULL; 1945 struct ice_hw_dev_caps *dev_p = NULL; 1946 struct ice_hw_common_caps *caps; 1947 char const *prefix; 1948 u32 i; 1949 1950 if (!buf) 1951 return; 1952 1953 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1954 1955 if (opc == ice_aqc_opc_list_dev_caps) { 1956 dev_p = &hw->dev_caps; 1957 caps = &dev_p->common_cap; 1958 prefix = "dev cap"; 1959 } else if (opc == ice_aqc_opc_list_func_caps) { 1960 func_p = &hw->func_caps; 1961 caps = &func_p->common_cap; 1962 prefix = "func cap"; 1963 } else { 1964 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1965 return; 1966 } 1967 1968 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1969 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id); 1970 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id); 1971 u32 number = LE32_TO_CPU(cap_resp->number); 1972 u16 cap = LE16_TO_CPU(cap_resp->cap); 1973 1974 switch (cap) { 1975 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1976 caps->valid_functions = number; 1977 ice_debug(hw, ICE_DBG_INIT, 1978 "%s: valid functions = %d\n", prefix, 1979 caps->valid_functions); 1980 break; 1981 case ICE_AQC_CAPS_VSI: 1982 if (dev_p) { 1983 dev_p->num_vsi_allocd_to_host = number; 1984 ice_debug(hw, ICE_DBG_INIT, 1985 "%s: num VSI alloc to host = %d\n", 1986 prefix, 1987 dev_p->num_vsi_allocd_to_host); 1988 } else if (func_p) { 1989 func_p->guar_num_vsi = 1990 ice_get_num_per_func(hw, ICE_MAX_VSI); 1991 ice_debug(hw, ICE_DBG_INIT, 1992 "%s: num guaranteed VSI (fw) = %d\n", 1993 prefix, number); 1994 ice_debug(hw, ICE_DBG_INIT, 1995 "%s: num guaranteed VSI = %d\n", 1996 prefix, func_p->guar_num_vsi); 1997 } 1998 break; 1999 case ICE_AQC_CAPS_DCB: 2000 caps->dcb = (number == 1); 2001 caps->active_tc_bitmap = logical_id; 2002 caps->maxtc = phys_id; 2003 ice_debug(hw, ICE_DBG_INIT, 2004 "%s: DCB = %d\n", prefix, caps->dcb); 2005 ice_debug(hw, ICE_DBG_INIT, 2006 "%s: active TC bitmap = %d\n", prefix, 2007 caps->active_tc_bitmap); 2008 ice_debug(hw, ICE_DBG_INIT, 2009 "%s: TC max = %d\n", prefix, caps->maxtc); 2010 break; 2011 case ICE_AQC_CAPS_RSS: 2012 caps->rss_table_size = number; 2013 caps->rss_table_entry_width = logical_id; 2014 ice_debug(hw, ICE_DBG_INIT, 2015 "%s: RSS table size = %d\n", prefix, 2016 caps->rss_table_size); 2017 ice_debug(hw, ICE_DBG_INIT, 2018 "%s: RSS table width = %d\n", prefix, 2019 caps->rss_table_entry_width); 2020 break; 2021 case ICE_AQC_CAPS_RXQS: 2022 caps->num_rxq = number; 2023 caps->rxq_first_id = phys_id; 2024 ice_debug(hw, ICE_DBG_INIT, 2025 "%s: num Rx queues = %d\n", prefix, 2026 caps->num_rxq); 2027 ice_debug(hw, ICE_DBG_INIT, 2028 "%s: Rx first queue ID = %d\n", prefix, 2029 caps->rxq_first_id); 2030 break; 2031 case ICE_AQC_CAPS_TXQS: 2032 caps->num_txq = number; 2033 caps->txq_first_id = phys_id; 2034 ice_debug(hw, ICE_DBG_INIT, 2035 "%s: num Tx queues = %d\n", prefix, 2036 caps->num_txq); 2037 ice_debug(hw, ICE_DBG_INIT, 2038 "%s: Tx first queue ID = %d\n", prefix, 2039 caps->txq_first_id); 2040 break; 2041 case ICE_AQC_CAPS_MSIX: 2042 caps->num_msix_vectors = number; 2043 caps->msix_vector_first_id = phys_id; 2044 ice_debug(hw, ICE_DBG_INIT, 2045 "%s: MSIX vector count = %d\n", prefix, 2046 caps->num_msix_vectors); 2047 ice_debug(hw, ICE_DBG_INIT, 2048 "%s: MSIX first vector index = %d\n", prefix, 2049 caps->msix_vector_first_id); 2050 break; 2051 case ICE_AQC_CAPS_FD: 2052 { 2053 u32 reg_val, val; 2054 2055 if (dev_p) { 2056 dev_p->num_flow_director_fltr = number; 2057 ice_debug(hw, ICE_DBG_INIT, 2058 "%s: num FD filters = %d\n", prefix, 2059 dev_p->num_flow_director_fltr); 2060 } 2061 if (func_p) { 2062 reg_val = rd32(hw, GLQF_FD_SIZE); 2063 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2064 GLQF_FD_SIZE_FD_GSIZE_S; 2065 func_p->fd_fltr_guar = 2066 ice_get_num_per_func(hw, val); 2067 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2068 GLQF_FD_SIZE_FD_BSIZE_S; 2069 func_p->fd_fltr_best_effort = val; 2070 ice_debug(hw, ICE_DBG_INIT, 2071 "%s: num guaranteed FD filters = %d\n", 2072 prefix, func_p->fd_fltr_guar); 2073 ice_debug(hw, ICE_DBG_INIT, 2074 "%s: num best effort FD filters = %d\n", 2075 prefix, func_p->fd_fltr_best_effort); 2076 } 2077 break; 2078 } 2079 case ICE_AQC_CAPS_MAX_MTU: 2080 caps->max_mtu = number; 2081 ice_debug(hw, ICE_DBG_INIT, "%s: max MTU = %d\n", 2082 prefix, caps->max_mtu); 2083 break; 2084 default: 2085 ice_debug(hw, ICE_DBG_INIT, 2086 "%s: unknown capability[%d]: 0x%x\n", prefix, 2087 i, cap); 2088 break; 2089 } 2090 } 2091 2092 /* Re-calculate capabilities that are dependent on the number of 2093 * physical ports; i.e. some features are not supported or function 2094 * differently on devices with more than 4 ports. 2095 */ 2096 if (caps && (ice_hweight32(caps->valid_functions) > 4)) { 2097 /* Max 4 TCs per port */ 2098 caps->maxtc = 4; 2099 ice_debug(hw, ICE_DBG_INIT, 2100 "%s: TC max = %d (based on #ports)\n", prefix, 2101 caps->maxtc); 2102 } 2103 } 2104 2105 /** 2106 * ice_aq_discover_caps - query function/device capabilities 2107 * @hw: pointer to the HW struct 2108 * @buf: a virtual buffer to hold the capabilities 2109 * @buf_size: Size of the virtual buffer 2110 * @cap_count: cap count needed if AQ err==ENOMEM 2111 * @opc: capabilities type to discover - pass in the command opcode 2112 * @cd: pointer to command details structure or NULL 2113 * 2114 * Get the function(0x000a)/device(0x000b) capabilities description from 2115 * the firmware. 2116 */ 2117 static enum ice_status 2118 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2119 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2120 { 2121 struct ice_aqc_list_caps *cmd; 2122 struct ice_aq_desc desc; 2123 enum ice_status status; 2124 2125 cmd = &desc.params.get_cap; 2126 2127 if (opc != ice_aqc_opc_list_func_caps && 2128 opc != ice_aqc_opc_list_dev_caps) 2129 return ICE_ERR_PARAM; 2130 2131 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2132 2133 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2134 if (!status) 2135 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc); 2136 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM) 2137 *cap_count = LE32_TO_CPU(cmd->count); 2138 return status; 2139 } 2140 2141 /** 2142 * ice_discover_caps - get info about the HW 2143 * @hw: pointer to the hardware structure 2144 * @opc: capabilities type to discover - pass in the command opcode 2145 */ 2146 static enum ice_status 2147 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc) 2148 { 2149 enum ice_status status; 2150 u32 cap_count; 2151 u16 cbuf_len; 2152 u8 retries; 2153 2154 /* The driver doesn't know how many capabilities the device will return 2155 * so the buffer size required isn't known ahead of time. The driver 2156 * starts with cbuf_len and if this turns out to be insufficient, the 2157 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs. 2158 * The driver then allocates the buffer based on the count and retries 2159 * the operation. So it follows that the retry count is 2. 2160 */ 2161 #define ICE_GET_CAP_BUF_COUNT 40 2162 #define ICE_GET_CAP_RETRY_COUNT 2 2163 2164 cap_count = ICE_GET_CAP_BUF_COUNT; 2165 retries = ICE_GET_CAP_RETRY_COUNT; 2166 2167 do { 2168 void *cbuf; 2169 2170 cbuf_len = (u16)(cap_count * 2171 sizeof(struct ice_aqc_list_caps_elem)); 2172 cbuf = ice_malloc(hw, cbuf_len); 2173 if (!cbuf) 2174 return ICE_ERR_NO_MEMORY; 2175 2176 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count, 2177 opc, NULL); 2178 ice_free(hw, cbuf); 2179 2180 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) 2181 break; 2182 2183 /* If ENOMEM is returned, try again with bigger buffer */ 2184 } while (--retries); 2185 2186 return status; 2187 } 2188 2189 /** 2190 * ice_get_caps - get info about the HW 2191 * @hw: pointer to the hardware structure 2192 */ 2193 enum ice_status ice_get_caps(struct ice_hw *hw) 2194 { 2195 enum ice_status status; 2196 2197 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps); 2198 if (!status) 2199 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps); 2200 2201 return status; 2202 } 2203 2204 /** 2205 * ice_aq_manage_mac_write - manage MAC address write command 2206 * @hw: pointer to the HW struct 2207 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2208 * @flags: flags to control write behavior 2209 * @cd: pointer to command details structure or NULL 2210 * 2211 * This function is used to write MAC address to the NVM (0x0108). 2212 */ 2213 enum ice_status 2214 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2215 struct ice_sq_cd *cd) 2216 { 2217 struct ice_aqc_manage_mac_write *cmd; 2218 struct ice_aq_desc desc; 2219 2220 cmd = &desc.params.mac_write; 2221 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2222 2223 cmd->flags = flags; 2224 2225 2226 /* Prep values for flags, sah, sal */ 2227 cmd->sah = HTONS(*((const u16 *)mac_addr)); 2228 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2))); 2229 2230 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2231 } 2232 2233 /** 2234 * ice_aq_clear_pxe_mode 2235 * @hw: pointer to the HW struct 2236 * 2237 * Tell the firmware that the driver is taking over from PXE (0x0110). 2238 */ 2239 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2240 { 2241 struct ice_aq_desc desc; 2242 2243 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2244 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2245 2246 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2247 } 2248 2249 /** 2250 * ice_clear_pxe_mode - clear pxe operations mode 2251 * @hw: pointer to the HW struct 2252 * 2253 * Make sure all PXE mode settings are cleared, including things 2254 * like descriptor fetch/write-back mode. 2255 */ 2256 void ice_clear_pxe_mode(struct ice_hw *hw) 2257 { 2258 if (ice_check_sq_alive(hw, &hw->adminq)) 2259 ice_aq_clear_pxe_mode(hw); 2260 } 2261 2262 2263 /** 2264 * ice_get_link_speed_based_on_phy_type - returns link speed 2265 * @phy_type_low: lower part of phy_type 2266 * @phy_type_high: higher part of phy_type 2267 * 2268 * This helper function will convert an entry in PHY type structure 2269 * [phy_type_low, phy_type_high] to its corresponding link speed. 2270 * Note: In the structure of [phy_type_low, phy_type_high], there should 2271 * be one bit set, as this function will convert one PHY type to its 2272 * speed. 2273 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2274 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2275 */ 2276 static u16 2277 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2278 { 2279 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2280 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2281 2282 switch (phy_type_low) { 2283 case ICE_PHY_TYPE_LOW_100BASE_TX: 2284 case ICE_PHY_TYPE_LOW_100M_SGMII: 2285 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2286 break; 2287 case ICE_PHY_TYPE_LOW_1000BASE_T: 2288 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2289 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2290 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2291 case ICE_PHY_TYPE_LOW_1G_SGMII: 2292 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2293 break; 2294 case ICE_PHY_TYPE_LOW_2500BASE_T: 2295 case ICE_PHY_TYPE_LOW_2500BASE_X: 2296 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2297 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2298 break; 2299 case ICE_PHY_TYPE_LOW_5GBASE_T: 2300 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2301 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2302 break; 2303 case ICE_PHY_TYPE_LOW_10GBASE_T: 2304 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2305 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2306 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2307 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2308 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2309 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2310 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2311 break; 2312 case ICE_PHY_TYPE_LOW_25GBASE_T: 2313 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2314 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2315 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2316 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2317 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2318 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2319 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2320 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2321 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2322 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2323 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2324 break; 2325 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2326 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2327 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2328 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2329 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2330 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2331 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2332 break; 2333 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2334 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2335 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2336 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2337 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2338 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2339 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2340 case ICE_PHY_TYPE_LOW_50G_AUI2: 2341 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2342 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2343 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2344 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2345 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2346 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2347 case ICE_PHY_TYPE_LOW_50G_AUI1: 2348 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2349 break; 2350 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2351 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2352 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2353 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2354 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2355 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2356 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2357 case ICE_PHY_TYPE_LOW_100G_AUI4: 2358 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2359 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2360 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2361 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2362 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2363 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2364 break; 2365 default: 2366 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2367 break; 2368 } 2369 2370 switch (phy_type_high) { 2371 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2372 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2373 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2374 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2375 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2376 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2377 break; 2378 default: 2379 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2380 break; 2381 } 2382 2383 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2384 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2385 return ICE_AQ_LINK_SPEED_UNKNOWN; 2386 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2387 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2388 return ICE_AQ_LINK_SPEED_UNKNOWN; 2389 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2390 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2391 return speed_phy_type_low; 2392 else 2393 return speed_phy_type_high; 2394 } 2395 2396 /** 2397 * ice_update_phy_type 2398 * @phy_type_low: pointer to the lower part of phy_type 2399 * @phy_type_high: pointer to the higher part of phy_type 2400 * @link_speeds_bitmap: targeted link speeds bitmap 2401 * 2402 * Note: For the link_speeds_bitmap structure, you can check it at 2403 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2404 * link_speeds_bitmap include multiple speeds. 2405 * 2406 * Each entry in this [phy_type_low, phy_type_high] structure will 2407 * present a certain link speed. This helper function will turn on bits 2408 * in [phy_type_low, phy_type_high] structure based on the value of 2409 * link_speeds_bitmap input parameter. 2410 */ 2411 void 2412 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2413 u16 link_speeds_bitmap) 2414 { 2415 u64 pt_high; 2416 u64 pt_low; 2417 int index; 2418 u16 speed; 2419 2420 /* We first check with low part of phy_type */ 2421 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2422 pt_low = BIT_ULL(index); 2423 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2424 2425 if (link_speeds_bitmap & speed) 2426 *phy_type_low |= BIT_ULL(index); 2427 } 2428 2429 /* We then check with high part of phy_type */ 2430 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2431 pt_high = BIT_ULL(index); 2432 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2433 2434 if (link_speeds_bitmap & speed) 2435 *phy_type_high |= BIT_ULL(index); 2436 } 2437 } 2438 2439 /** 2440 * ice_aq_set_phy_cfg 2441 * @hw: pointer to the HW struct 2442 * @pi: port info structure of the interested logical port 2443 * @cfg: structure with PHY configuration data to be set 2444 * @cd: pointer to command details structure or NULL 2445 * 2446 * Set the various PHY configuration parameters supported on the Port. 2447 * One or more of the Set PHY config parameters may be ignored in an MFP 2448 * mode as the PF may not have the privilege to set some of the PHY Config 2449 * parameters. This status will be indicated by the command response (0x0601). 2450 */ 2451 enum ice_status 2452 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2453 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2454 { 2455 struct ice_aq_desc desc; 2456 enum ice_status status; 2457 2458 if (!cfg) 2459 return ICE_ERR_PARAM; 2460 2461 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2462 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2463 ice_debug(hw, ICE_DBG_PHY, 2464 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2465 cfg->caps); 2466 2467 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2468 } 2469 2470 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2471 desc.params.set_phy.lport_num = pi->lport; 2472 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2473 2474 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n", 2475 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 2476 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n", 2477 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 2478 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps); 2479 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n", 2480 cfg->low_power_ctrl); 2481 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap); 2482 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value); 2483 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt); 2484 2485 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2486 2487 if (!status) 2488 pi->phy.curr_user_phy_cfg = *cfg; 2489 2490 return status; 2491 } 2492 2493 /** 2494 * ice_update_link_info - update status of the HW network link 2495 * @pi: port info structure of the interested logical port 2496 */ 2497 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2498 { 2499 struct ice_link_status *li; 2500 enum ice_status status; 2501 2502 if (!pi) 2503 return ICE_ERR_PARAM; 2504 2505 li = &pi->phy.link_info; 2506 2507 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2508 if (status) 2509 return status; 2510 2511 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2512 struct ice_aqc_get_phy_caps_data *pcaps; 2513 struct ice_hw *hw; 2514 2515 hw = pi->hw; 2516 pcaps = (struct ice_aqc_get_phy_caps_data *) 2517 ice_malloc(hw, sizeof(*pcaps)); 2518 if (!pcaps) 2519 return ICE_ERR_NO_MEMORY; 2520 2521 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2522 pcaps, NULL); 2523 if (status == ICE_SUCCESS) 2524 ice_memcpy(li->module_type, &pcaps->module_type, 2525 sizeof(li->module_type), 2526 ICE_NONDMA_TO_NONDMA); 2527 2528 ice_free(hw, pcaps); 2529 } 2530 2531 return status; 2532 } 2533 2534 /** 2535 * ice_cache_phy_user_req 2536 * @pi: port information structure 2537 * @cache_data: PHY logging data 2538 * @cache_mode: PHY logging mode 2539 * 2540 * Log the user request on (FC, FEC, SPEED) for later user. 2541 */ 2542 static void 2543 ice_cache_phy_user_req(struct ice_port_info *pi, 2544 struct ice_phy_cache_mode_data cache_data, 2545 enum ice_phy_cache_mode cache_mode) 2546 { 2547 if (!pi) 2548 return; 2549 2550 switch (cache_mode) { 2551 case ICE_FC_MODE: 2552 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2553 break; 2554 case ICE_SPEED_MODE: 2555 pi->phy.curr_user_speed_req = 2556 cache_data.data.curr_user_speed_req; 2557 break; 2558 case ICE_FEC_MODE: 2559 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2560 break; 2561 default: 2562 break; 2563 } 2564 } 2565 2566 /** 2567 * ice_set_fc 2568 * @pi: port information structure 2569 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2570 * @ena_auto_link_update: enable automatic link update 2571 * 2572 * Set the requested flow control mode. 2573 */ 2574 enum ice_status 2575 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2576 { 2577 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2578 struct ice_phy_cache_mode_data cache_data; 2579 struct ice_aqc_get_phy_caps_data *pcaps; 2580 enum ice_status status; 2581 u8 pause_mask = 0x0; 2582 struct ice_hw *hw; 2583 2584 if (!pi) 2585 return ICE_ERR_PARAM; 2586 hw = pi->hw; 2587 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; 2588 2589 /* Cache user FC request */ 2590 cache_data.data.curr_user_fc_req = pi->fc.req_mode; 2591 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2592 2593 switch (pi->fc.req_mode) { 2594 case ICE_FC_FULL: 2595 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2596 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2597 break; 2598 case ICE_FC_RX_PAUSE: 2599 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2600 break; 2601 case ICE_FC_TX_PAUSE: 2602 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2603 break; 2604 default: 2605 break; 2606 } 2607 2608 pcaps = (struct ice_aqc_get_phy_caps_data *) 2609 ice_malloc(hw, sizeof(*pcaps)); 2610 if (!pcaps) 2611 return ICE_ERR_NO_MEMORY; 2612 2613 /* Get the current PHY config */ 2614 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2615 NULL); 2616 if (status) { 2617 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2618 goto out; 2619 } 2620 2621 /* clear the old pause settings */ 2622 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2623 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2624 2625 /* set the new capabilities */ 2626 cfg.caps |= pause_mask; 2627 2628 /* If the capabilities have changed, then set the new config */ 2629 if (cfg.caps != pcaps->caps) { 2630 int retry_count, retry_max = 10; 2631 2632 /* Auto restart link so settings take effect */ 2633 if (ena_auto_link_update) 2634 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2635 /* Copy over all the old settings */ 2636 cfg.phy_type_high = pcaps->phy_type_high; 2637 cfg.phy_type_low = pcaps->phy_type_low; 2638 cfg.low_power_ctrl = pcaps->low_power_ctrl; 2639 cfg.eee_cap = pcaps->eee_cap; 2640 cfg.eeer_value = pcaps->eeer_value; 2641 cfg.link_fec_opt = pcaps->link_fec_options; 2642 2643 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2644 if (status) { 2645 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2646 goto out; 2647 } 2648 2649 /* Update the link info 2650 * It sometimes takes a really long time for link to 2651 * come back from the atomic reset. Thus, we wait a 2652 * little bit. 2653 */ 2654 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2655 status = ice_update_link_info(pi); 2656 2657 if (status == ICE_SUCCESS) 2658 break; 2659 2660 ice_msec_delay(100, true); 2661 } 2662 2663 if (status) 2664 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2665 } 2666 2667 out: 2668 ice_free(hw, pcaps); 2669 return status; 2670 } 2671 2672 /** 2673 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2674 * @caps: PHY ability structure to copy date from 2675 * @cfg: PHY configuration structure to copy data to 2676 * 2677 * Helper function to copy AQC PHY get ability data to PHY set configuration 2678 * data structure 2679 */ 2680 void 2681 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps, 2682 struct ice_aqc_set_phy_cfg_data *cfg) 2683 { 2684 if (!caps || !cfg) 2685 return; 2686 2687 cfg->phy_type_low = caps->phy_type_low; 2688 cfg->phy_type_high = caps->phy_type_high; 2689 cfg->caps = caps->caps; 2690 cfg->low_power_ctrl = caps->low_power_ctrl; 2691 cfg->eee_cap = caps->eee_cap; 2692 cfg->eeer_value = caps->eeer_value; 2693 cfg->link_fec_opt = caps->link_fec_options; 2694 } 2695 2696 /** 2697 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 2698 * @cfg: PHY configuration data to set FEC mode 2699 * @fec: FEC mode to configure 2700 * 2701 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC 2702 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps 2703 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling. 2704 */ 2705 void 2706 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec) 2707 { 2708 switch (fec) { 2709 case ICE_FEC_BASER: 2710 /* Clear RS bits, and AND BASE-R ability 2711 * bits and OR request bits. 2712 */ 2713 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2714 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2715 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2716 ICE_AQC_PHY_FEC_25G_KR_REQ; 2717 break; 2718 case ICE_FEC_RS: 2719 /* Clear BASE-R bits, and AND RS ability 2720 * bits and OR request bits. 2721 */ 2722 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2723 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2724 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2725 break; 2726 case ICE_FEC_NONE: 2727 /* Clear all FEC option bits. */ 2728 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2729 break; 2730 case ICE_FEC_AUTO: 2731 /* AND auto FEC bit, and all caps bits. */ 2732 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 2733 break; 2734 } 2735 } 2736 2737 /** 2738 * ice_get_link_status - get status of the HW network link 2739 * @pi: port information structure 2740 * @link_up: pointer to bool (true/false = linkup/linkdown) 2741 * 2742 * Variable link_up is true if link is up, false if link is down. 2743 * The variable link_up is invalid if status is non zero. As a 2744 * result of this call, link status reporting becomes enabled 2745 */ 2746 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 2747 { 2748 struct ice_phy_info *phy_info; 2749 enum ice_status status = ICE_SUCCESS; 2750 2751 if (!pi || !link_up) 2752 return ICE_ERR_PARAM; 2753 2754 phy_info = &pi->phy; 2755 2756 if (phy_info->get_link_info) { 2757 status = ice_update_link_info(pi); 2758 2759 if (status) 2760 ice_debug(pi->hw, ICE_DBG_LINK, 2761 "get link status error, status = %d\n", 2762 status); 2763 } 2764 2765 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 2766 2767 return status; 2768 } 2769 2770 /** 2771 * ice_aq_set_link_restart_an 2772 * @pi: pointer to the port information structure 2773 * @ena_link: if true: enable link, if false: disable link 2774 * @cd: pointer to command details structure or NULL 2775 * 2776 * Sets up the link and restarts the Auto-Negotiation over the link. 2777 */ 2778 enum ice_status 2779 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 2780 struct ice_sq_cd *cd) 2781 { 2782 struct ice_aqc_restart_an *cmd; 2783 struct ice_aq_desc desc; 2784 2785 cmd = &desc.params.restart_an; 2786 2787 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 2788 2789 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 2790 cmd->lport_num = pi->lport; 2791 if (ena_link) 2792 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 2793 else 2794 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 2795 2796 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2797 } 2798 2799 /** 2800 * ice_aq_set_event_mask 2801 * @hw: pointer to the HW struct 2802 * @port_num: port number of the physical function 2803 * @mask: event mask to be set 2804 * @cd: pointer to command details structure or NULL 2805 * 2806 * Set event mask (0x0613) 2807 */ 2808 enum ice_status 2809 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 2810 struct ice_sq_cd *cd) 2811 { 2812 struct ice_aqc_set_event_mask *cmd; 2813 struct ice_aq_desc desc; 2814 2815 cmd = &desc.params.set_event_mask; 2816 2817 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 2818 2819 cmd->lport_num = port_num; 2820 2821 cmd->event_mask = CPU_TO_LE16(mask); 2822 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2823 } 2824 2825 /** 2826 * ice_aq_set_mac_loopback 2827 * @hw: pointer to the HW struct 2828 * @ena_lpbk: Enable or Disable loopback 2829 * @cd: pointer to command details structure or NULL 2830 * 2831 * Enable/disable loopback on a given port 2832 */ 2833 enum ice_status 2834 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 2835 { 2836 struct ice_aqc_set_mac_lb *cmd; 2837 struct ice_aq_desc desc; 2838 2839 cmd = &desc.params.set_mac_lb; 2840 2841 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 2842 if (ena_lpbk) 2843 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 2844 2845 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2846 } 2847 2848 2849 /** 2850 * ice_aq_set_port_id_led 2851 * @pi: pointer to the port information 2852 * @is_orig_mode: is this LED set to original mode (by the net-list) 2853 * @cd: pointer to command details structure or NULL 2854 * 2855 * Set LED value for the given port (0x06e9) 2856 */ 2857 enum ice_status 2858 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 2859 struct ice_sq_cd *cd) 2860 { 2861 struct ice_aqc_set_port_id_led *cmd; 2862 struct ice_hw *hw = pi->hw; 2863 struct ice_aq_desc desc; 2864 2865 cmd = &desc.params.set_port_id_led; 2866 2867 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 2868 2869 2870 if (is_orig_mode) 2871 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 2872 else 2873 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 2874 2875 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2876 } 2877 2878 /** 2879 * __ice_aq_get_set_rss_lut 2880 * @hw: pointer to the hardware structure 2881 * @vsi_id: VSI FW index 2882 * @lut_type: LUT table type 2883 * @lut: pointer to the LUT buffer provided by the caller 2884 * @lut_size: size of the LUT buffer 2885 * @glob_lut_idx: global LUT index 2886 * @set: set true to set the table, false to get the table 2887 * 2888 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 2889 */ 2890 static enum ice_status 2891 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 2892 u16 lut_size, u8 glob_lut_idx, bool set) 2893 { 2894 struct ice_aqc_get_set_rss_lut *cmd_resp; 2895 struct ice_aq_desc desc; 2896 enum ice_status status; 2897 u16 flags = 0; 2898 2899 cmd_resp = &desc.params.get_set_rss_lut; 2900 2901 if (set) { 2902 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 2903 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2904 } else { 2905 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 2906 } 2907 2908 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 2909 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 2910 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 2911 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 2912 2913 switch (lut_type) { 2914 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 2915 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 2916 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 2917 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 2918 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 2919 break; 2920 default: 2921 status = ICE_ERR_PARAM; 2922 goto ice_aq_get_set_rss_lut_exit; 2923 } 2924 2925 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 2926 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 2927 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 2928 2929 if (!set) 2930 goto ice_aq_get_set_rss_lut_send; 2931 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2932 if (!set) 2933 goto ice_aq_get_set_rss_lut_send; 2934 } else { 2935 goto ice_aq_get_set_rss_lut_send; 2936 } 2937 2938 /* LUT size is only valid for Global and PF table types */ 2939 switch (lut_size) { 2940 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 2941 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 2942 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2943 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2944 break; 2945 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 2946 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 2947 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2948 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2949 break; 2950 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 2951 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2952 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 2953 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2954 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2955 break; 2956 } 2957 /* fall-through */ 2958 default: 2959 status = ICE_ERR_PARAM; 2960 goto ice_aq_get_set_rss_lut_exit; 2961 } 2962 2963 ice_aq_get_set_rss_lut_send: 2964 cmd_resp->flags = CPU_TO_LE16(flags); 2965 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 2966 2967 ice_aq_get_set_rss_lut_exit: 2968 return status; 2969 } 2970 2971 /** 2972 * ice_aq_get_rss_lut 2973 * @hw: pointer to the hardware structure 2974 * @vsi_handle: software VSI handle 2975 * @lut_type: LUT table type 2976 * @lut: pointer to the LUT buffer provided by the caller 2977 * @lut_size: size of the LUT buffer 2978 * 2979 * get the RSS lookup table, PF or VSI type 2980 */ 2981 enum ice_status 2982 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2983 u8 *lut, u16 lut_size) 2984 { 2985 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2986 return ICE_ERR_PARAM; 2987 2988 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2989 lut_type, lut, lut_size, 0, false); 2990 } 2991 2992 /** 2993 * ice_aq_set_rss_lut 2994 * @hw: pointer to the hardware structure 2995 * @vsi_handle: software VSI handle 2996 * @lut_type: LUT table type 2997 * @lut: pointer to the LUT buffer provided by the caller 2998 * @lut_size: size of the LUT buffer 2999 * 3000 * set the RSS lookup table, PF or VSI type 3001 */ 3002 enum ice_status 3003 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3004 u8 *lut, u16 lut_size) 3005 { 3006 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3007 return ICE_ERR_PARAM; 3008 3009 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3010 lut_type, lut, lut_size, 0, true); 3011 } 3012 3013 /** 3014 * __ice_aq_get_set_rss_key 3015 * @hw: pointer to the HW struct 3016 * @vsi_id: VSI FW index 3017 * @key: pointer to key info struct 3018 * @set: set true to set the key, false to get the key 3019 * 3020 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3021 */ 3022 static enum 3023 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3024 struct ice_aqc_get_set_rss_keys *key, 3025 bool set) 3026 { 3027 struct ice_aqc_get_set_rss_key *cmd_resp; 3028 u16 key_size = sizeof(*key); 3029 struct ice_aq_desc desc; 3030 3031 cmd_resp = &desc.params.get_set_rss_key; 3032 3033 if (set) { 3034 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3035 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3036 } else { 3037 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3038 } 3039 3040 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3041 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3042 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3043 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3044 3045 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3046 } 3047 3048 /** 3049 * ice_aq_get_rss_key 3050 * @hw: pointer to the HW struct 3051 * @vsi_handle: software VSI handle 3052 * @key: pointer to key info struct 3053 * 3054 * get the RSS key per VSI 3055 */ 3056 enum ice_status 3057 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3058 struct ice_aqc_get_set_rss_keys *key) 3059 { 3060 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3061 return ICE_ERR_PARAM; 3062 3063 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3064 key, false); 3065 } 3066 3067 /** 3068 * ice_aq_set_rss_key 3069 * @hw: pointer to the HW struct 3070 * @vsi_handle: software VSI handle 3071 * @keys: pointer to key info struct 3072 * 3073 * set the RSS key per VSI 3074 */ 3075 enum ice_status 3076 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3077 struct ice_aqc_get_set_rss_keys *keys) 3078 { 3079 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3080 return ICE_ERR_PARAM; 3081 3082 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3083 keys, true); 3084 } 3085 3086 /** 3087 * ice_aq_add_lan_txq 3088 * @hw: pointer to the hardware structure 3089 * @num_qgrps: Number of added queue groups 3090 * @qg_list: list of queue groups to be added 3091 * @buf_size: size of buffer for indirect command 3092 * @cd: pointer to command details structure or NULL 3093 * 3094 * Add Tx LAN queue (0x0C30) 3095 * 3096 * NOTE: 3097 * Prior to calling add Tx LAN queue: 3098 * Initialize the following as part of the Tx queue context: 3099 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3100 * Cache profile and Packet shaper profile. 3101 * 3102 * After add Tx LAN queue AQ command is completed: 3103 * Interrupts should be associated with specific queues, 3104 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3105 * flow. 3106 */ 3107 enum ice_status 3108 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3109 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3110 struct ice_sq_cd *cd) 3111 { 3112 u16 i, sum_header_size, sum_q_size = 0; 3113 struct ice_aqc_add_tx_qgrp *list; 3114 struct ice_aqc_add_txqs *cmd; 3115 struct ice_aq_desc desc; 3116 3117 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3118 3119 cmd = &desc.params.add_txqs; 3120 3121 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3122 3123 if (!qg_list) 3124 return ICE_ERR_PARAM; 3125 3126 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3127 return ICE_ERR_PARAM; 3128 3129 sum_header_size = num_qgrps * 3130 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 3131 3132 list = qg_list; 3133 for (i = 0; i < num_qgrps; i++) { 3134 struct ice_aqc_add_txqs_perq *q = list->txqs; 3135 3136 sum_q_size += list->num_txqs * sizeof(*q); 3137 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 3138 } 3139 3140 if (buf_size != (sum_header_size + sum_q_size)) 3141 return ICE_ERR_PARAM; 3142 3143 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3144 3145 cmd->num_qgrps = num_qgrps; 3146 3147 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3148 } 3149 3150 /** 3151 * ice_aq_dis_lan_txq 3152 * @hw: pointer to the hardware structure 3153 * @num_qgrps: number of groups in the list 3154 * @qg_list: the list of groups to disable 3155 * @buf_size: the total size of the qg_list buffer in bytes 3156 * @rst_src: if called due to reset, specifies the reset source 3157 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3158 * @cd: pointer to command details structure or NULL 3159 * 3160 * Disable LAN Tx queue (0x0C31) 3161 */ 3162 static enum ice_status 3163 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3164 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3165 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3166 struct ice_sq_cd *cd) 3167 { 3168 struct ice_aqc_dis_txqs *cmd; 3169 struct ice_aq_desc desc; 3170 enum ice_status status; 3171 u16 i, sz = 0; 3172 3173 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3174 cmd = &desc.params.dis_txqs; 3175 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3176 3177 /* qg_list can be NULL only in VM/VF reset flow */ 3178 if (!qg_list && !rst_src) 3179 return ICE_ERR_PARAM; 3180 3181 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3182 return ICE_ERR_PARAM; 3183 3184 cmd->num_entries = num_qgrps; 3185 3186 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3187 ICE_AQC_Q_DIS_TIMEOUT_M); 3188 3189 switch (rst_src) { 3190 case ICE_VM_RESET: 3191 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3192 cmd->vmvf_and_timeout |= 3193 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3194 break; 3195 case ICE_NO_RESET: 3196 default: 3197 break; 3198 } 3199 3200 /* flush pipe on time out */ 3201 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3202 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3203 if (!qg_list) 3204 goto do_aq; 3205 3206 /* set RD bit to indicate that command buffer is provided by the driver 3207 * and it needs to be read by the firmware 3208 */ 3209 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3210 3211 for (i = 0; i < num_qgrps; ++i) { 3212 /* Calculate the size taken up by the queue IDs in this group */ 3213 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 3214 3215 /* Add the size of the group header */ 3216 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 3217 3218 /* If the num of queues is even, add 2 bytes of padding */ 3219 if ((qg_list[i].num_qs % 2) == 0) 3220 sz += 2; 3221 } 3222 3223 if (buf_size != sz) 3224 return ICE_ERR_PARAM; 3225 3226 do_aq: 3227 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3228 if (status) { 3229 if (!qg_list) 3230 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3231 vmvf_num, hw->adminq.sq_last_status); 3232 else 3233 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3234 LE16_TO_CPU(qg_list[0].q_id[0]), 3235 hw->adminq.sq_last_status); 3236 } 3237 return status; 3238 } 3239 3240 3241 /* End of FW Admin Queue command wrappers */ 3242 3243 /** 3244 * ice_write_byte - write a byte to a packed context structure 3245 * @src_ctx: the context structure to read from 3246 * @dest_ctx: the context to be written to 3247 * @ce_info: a description of the struct to be filled 3248 */ 3249 static void 3250 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3251 { 3252 u8 src_byte, dest_byte, mask; 3253 u8 *from, *dest; 3254 u16 shift_width; 3255 3256 /* copy from the next struct field */ 3257 from = src_ctx + ce_info->offset; 3258 3259 /* prepare the bits and mask */ 3260 shift_width = ce_info->lsb % 8; 3261 mask = (u8)(BIT(ce_info->width) - 1); 3262 3263 src_byte = *from; 3264 src_byte &= mask; 3265 3266 /* shift to correct alignment */ 3267 mask <<= shift_width; 3268 src_byte <<= shift_width; 3269 3270 /* get the current bits from the target bit string */ 3271 dest = dest_ctx + (ce_info->lsb / 8); 3272 3273 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3274 3275 dest_byte &= ~mask; /* get the bits not changing */ 3276 dest_byte |= src_byte; /* add in the new bits */ 3277 3278 /* put it all back */ 3279 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3280 } 3281 3282 /** 3283 * ice_write_word - write a word to a packed context structure 3284 * @src_ctx: the context structure to read from 3285 * @dest_ctx: the context to be written to 3286 * @ce_info: a description of the struct to be filled 3287 */ 3288 static void 3289 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3290 { 3291 u16 src_word, mask; 3292 __le16 dest_word; 3293 u8 *from, *dest; 3294 u16 shift_width; 3295 3296 /* copy from the next struct field */ 3297 from = src_ctx + ce_info->offset; 3298 3299 /* prepare the bits and mask */ 3300 shift_width = ce_info->lsb % 8; 3301 mask = BIT(ce_info->width) - 1; 3302 3303 /* don't swizzle the bits until after the mask because the mask bits 3304 * will be in a different bit position on big endian machines 3305 */ 3306 src_word = *(u16 *)from; 3307 src_word &= mask; 3308 3309 /* shift to correct alignment */ 3310 mask <<= shift_width; 3311 src_word <<= shift_width; 3312 3313 /* get the current bits from the target bit string */ 3314 dest = dest_ctx + (ce_info->lsb / 8); 3315 3316 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 3317 3318 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 3319 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 3320 3321 /* put it all back */ 3322 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3323 } 3324 3325 /** 3326 * ice_write_dword - write a dword to a packed context structure 3327 * @src_ctx: the context structure to read from 3328 * @dest_ctx: the context to be written to 3329 * @ce_info: a description of the struct to be filled 3330 */ 3331 static void 3332 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3333 { 3334 u32 src_dword, mask; 3335 __le32 dest_dword; 3336 u8 *from, *dest; 3337 u16 shift_width; 3338 3339 /* copy from the next struct field */ 3340 from = src_ctx + ce_info->offset; 3341 3342 /* prepare the bits and mask */ 3343 shift_width = ce_info->lsb % 8; 3344 3345 /* if the field width is exactly 32 on an x86 machine, then the shift 3346 * operation will not work because the SHL instructions count is masked 3347 * to 5 bits so the shift will do nothing 3348 */ 3349 if (ce_info->width < 32) 3350 mask = BIT(ce_info->width) - 1; 3351 else 3352 mask = (u32)~0; 3353 3354 /* don't swizzle the bits until after the mask because the mask bits 3355 * will be in a different bit position on big endian machines 3356 */ 3357 src_dword = *(u32 *)from; 3358 src_dword &= mask; 3359 3360 /* shift to correct alignment */ 3361 mask <<= shift_width; 3362 src_dword <<= shift_width; 3363 3364 /* get the current bits from the target bit string */ 3365 dest = dest_ctx + (ce_info->lsb / 8); 3366 3367 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 3368 3369 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 3370 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 3371 3372 /* put it all back */ 3373 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3374 } 3375 3376 /** 3377 * ice_write_qword - write a qword to a packed context structure 3378 * @src_ctx: the context structure to read from 3379 * @dest_ctx: the context to be written to 3380 * @ce_info: a description of the struct to be filled 3381 */ 3382 static void 3383 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3384 { 3385 u64 src_qword, mask; 3386 __le64 dest_qword; 3387 u8 *from, *dest; 3388 u16 shift_width; 3389 3390 /* copy from the next struct field */ 3391 from = src_ctx + ce_info->offset; 3392 3393 /* prepare the bits and mask */ 3394 shift_width = ce_info->lsb % 8; 3395 3396 /* if the field width is exactly 64 on an x86 machine, then the shift 3397 * operation will not work because the SHL instructions count is masked 3398 * to 6 bits so the shift will do nothing 3399 */ 3400 if (ce_info->width < 64) 3401 mask = BIT_ULL(ce_info->width) - 1; 3402 else 3403 mask = (u64)~0; 3404 3405 /* don't swizzle the bits until after the mask because the mask bits 3406 * will be in a different bit position on big endian machines 3407 */ 3408 src_qword = *(u64 *)from; 3409 src_qword &= mask; 3410 3411 /* shift to correct alignment */ 3412 mask <<= shift_width; 3413 src_qword <<= shift_width; 3414 3415 /* get the current bits from the target bit string */ 3416 dest = dest_ctx + (ce_info->lsb / 8); 3417 3418 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 3419 3420 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 3421 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 3422 3423 /* put it all back */ 3424 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3425 } 3426 3427 /** 3428 * ice_set_ctx - set context bits in packed structure 3429 * @src_ctx: pointer to a generic non-packed context structure 3430 * @dest_ctx: pointer to memory for the packed structure 3431 * @ce_info: a description of the structure to be transformed 3432 */ 3433 enum ice_status 3434 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3435 { 3436 int f; 3437 3438 for (f = 0; ce_info[f].width; f++) { 3439 /* We have to deal with each element of the FW response 3440 * using the correct size so that we are correct regardless 3441 * of the endianness of the machine. 3442 */ 3443 switch (ce_info[f].size_of) { 3444 case sizeof(u8): 3445 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3446 break; 3447 case sizeof(u16): 3448 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3449 break; 3450 case sizeof(u32): 3451 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3452 break; 3453 case sizeof(u64): 3454 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3455 break; 3456 default: 3457 return ICE_ERR_INVAL_SIZE; 3458 } 3459 } 3460 3461 return ICE_SUCCESS; 3462 } 3463 3464 3465 3466 3467 /** 3468 * ice_read_byte - read context byte into struct 3469 * @src_ctx: the context structure to read from 3470 * @dest_ctx: the context to be written to 3471 * @ce_info: a description of the struct to be filled 3472 */ 3473 static void 3474 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3475 { 3476 u8 dest_byte, mask; 3477 u8 *src, *target; 3478 u16 shift_width; 3479 3480 /* prepare the bits and mask */ 3481 shift_width = ce_info->lsb % 8; 3482 mask = (u8)(BIT(ce_info->width) - 1); 3483 3484 /* shift to correct alignment */ 3485 mask <<= shift_width; 3486 3487 /* get the current bits from the src bit string */ 3488 src = src_ctx + (ce_info->lsb / 8); 3489 3490 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3491 3492 dest_byte &= ~(mask); 3493 3494 dest_byte >>= shift_width; 3495 3496 /* get the address from the struct field */ 3497 target = dest_ctx + ce_info->offset; 3498 3499 /* put it back in the struct */ 3500 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3501 } 3502 3503 /** 3504 * ice_read_word - read context word into struct 3505 * @src_ctx: the context structure to read from 3506 * @dest_ctx: the context to be written to 3507 * @ce_info: a description of the struct to be filled 3508 */ 3509 static void 3510 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3511 { 3512 u16 dest_word, mask; 3513 u8 *src, *target; 3514 __le16 src_word; 3515 u16 shift_width; 3516 3517 /* prepare the bits and mask */ 3518 shift_width = ce_info->lsb % 8; 3519 mask = BIT(ce_info->width) - 1; 3520 3521 /* shift to correct alignment */ 3522 mask <<= shift_width; 3523 3524 /* get the current bits from the src bit string */ 3525 src = src_ctx + (ce_info->lsb / 8); 3526 3527 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 3528 3529 /* the data in the memory is stored as little endian so mask it 3530 * correctly 3531 */ 3532 src_word &= ~(CPU_TO_LE16(mask)); 3533 3534 /* get the data back into host order before shifting */ 3535 dest_word = LE16_TO_CPU(src_word); 3536 3537 dest_word >>= shift_width; 3538 3539 /* get the address from the struct field */ 3540 target = dest_ctx + ce_info->offset; 3541 3542 /* put it back in the struct */ 3543 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3544 } 3545 3546 /** 3547 * ice_read_dword - read context dword into struct 3548 * @src_ctx: the context structure to read from 3549 * @dest_ctx: the context to be written to 3550 * @ce_info: a description of the struct to be filled 3551 */ 3552 static void 3553 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3554 { 3555 u32 dest_dword, mask; 3556 __le32 src_dword; 3557 u8 *src, *target; 3558 u16 shift_width; 3559 3560 /* prepare the bits and mask */ 3561 shift_width = ce_info->lsb % 8; 3562 3563 /* if the field width is exactly 32 on an x86 machine, then the shift 3564 * operation will not work because the SHL instructions count is masked 3565 * to 5 bits so the shift will do nothing 3566 */ 3567 if (ce_info->width < 32) 3568 mask = BIT(ce_info->width) - 1; 3569 else 3570 mask = (u32)~0; 3571 3572 /* shift to correct alignment */ 3573 mask <<= shift_width; 3574 3575 /* get the current bits from the src bit string */ 3576 src = src_ctx + (ce_info->lsb / 8); 3577 3578 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 3579 3580 /* the data in the memory is stored as little endian so mask it 3581 * correctly 3582 */ 3583 src_dword &= ~(CPU_TO_LE32(mask)); 3584 3585 /* get the data back into host order before shifting */ 3586 dest_dword = LE32_TO_CPU(src_dword); 3587 3588 dest_dword >>= shift_width; 3589 3590 /* get the address from the struct field */ 3591 target = dest_ctx + ce_info->offset; 3592 3593 /* put it back in the struct */ 3594 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3595 } 3596 3597 /** 3598 * ice_read_qword - read context qword into struct 3599 * @src_ctx: the context structure to read from 3600 * @dest_ctx: the context to be written to 3601 * @ce_info: a description of the struct to be filled 3602 */ 3603 static void 3604 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3605 { 3606 u64 dest_qword, mask; 3607 __le64 src_qword; 3608 u8 *src, *target; 3609 u16 shift_width; 3610 3611 /* prepare the bits and mask */ 3612 shift_width = ce_info->lsb % 8; 3613 3614 /* if the field width is exactly 64 on an x86 machine, then the shift 3615 * operation will not work because the SHL instructions count is masked 3616 * to 6 bits so the shift will do nothing 3617 */ 3618 if (ce_info->width < 64) 3619 mask = BIT_ULL(ce_info->width) - 1; 3620 else 3621 mask = (u64)~0; 3622 3623 /* shift to correct alignment */ 3624 mask <<= shift_width; 3625 3626 /* get the current bits from the src bit string */ 3627 src = src_ctx + (ce_info->lsb / 8); 3628 3629 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 3630 3631 /* the data in the memory is stored as little endian so mask it 3632 * correctly 3633 */ 3634 src_qword &= ~(CPU_TO_LE64(mask)); 3635 3636 /* get the data back into host order before shifting */ 3637 dest_qword = LE64_TO_CPU(src_qword); 3638 3639 dest_qword >>= shift_width; 3640 3641 /* get the address from the struct field */ 3642 target = dest_ctx + ce_info->offset; 3643 3644 /* put it back in the struct */ 3645 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3646 } 3647 3648 /** 3649 * ice_get_ctx - extract context bits from a packed structure 3650 * @src_ctx: pointer to a generic packed context structure 3651 * @dest_ctx: pointer to a generic non-packed context structure 3652 * @ce_info: a description of the structure to be read from 3653 */ 3654 enum ice_status 3655 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3656 { 3657 int f; 3658 3659 for (f = 0; ce_info[f].width; f++) { 3660 switch (ce_info[f].size_of) { 3661 case 1: 3662 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 3663 break; 3664 case 2: 3665 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 3666 break; 3667 case 4: 3668 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 3669 break; 3670 case 8: 3671 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 3672 break; 3673 default: 3674 /* nothing to do, just keep going */ 3675 break; 3676 } 3677 } 3678 3679 return ICE_SUCCESS; 3680 } 3681 3682 /** 3683 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3684 * @hw: pointer to the HW struct 3685 * @vsi_handle: software VSI handle 3686 * @tc: TC number 3687 * @q_handle: software queue handle 3688 */ 3689 struct ice_q_ctx * 3690 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3691 { 3692 struct ice_vsi_ctx *vsi; 3693 struct ice_q_ctx *q_ctx; 3694 3695 vsi = ice_get_vsi_ctx(hw, vsi_handle); 3696 if (!vsi) 3697 return NULL; 3698 if (q_handle >= vsi->num_lan_q_entries[tc]) 3699 return NULL; 3700 if (!vsi->lan_q_ctx[tc]) 3701 return NULL; 3702 q_ctx = vsi->lan_q_ctx[tc]; 3703 return &q_ctx[q_handle]; 3704 } 3705 3706 /** 3707 * ice_ena_vsi_txq 3708 * @pi: port information structure 3709 * @vsi_handle: software VSI handle 3710 * @tc: TC number 3711 * @q_handle: software queue handle 3712 * @num_qgrps: Number of added queue groups 3713 * @buf: list of queue groups to be added 3714 * @buf_size: size of buffer for indirect command 3715 * @cd: pointer to command details structure or NULL 3716 * 3717 * This function adds one LAN queue 3718 */ 3719 enum ice_status 3720 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3721 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3722 struct ice_sq_cd *cd) 3723 { 3724 struct ice_aqc_txsched_elem_data node = { 0 }; 3725 struct ice_sched_node *parent; 3726 struct ice_q_ctx *q_ctx; 3727 enum ice_status status; 3728 struct ice_hw *hw; 3729 3730 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3731 return ICE_ERR_CFG; 3732 3733 if (num_qgrps > 1 || buf->num_txqs > 1) 3734 return ICE_ERR_MAX_LIMIT; 3735 3736 hw = pi->hw; 3737 3738 if (!ice_is_vsi_valid(hw, vsi_handle)) 3739 return ICE_ERR_PARAM; 3740 3741 ice_acquire_lock(&pi->sched_lock); 3742 3743 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3744 if (!q_ctx) { 3745 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3746 q_handle); 3747 status = ICE_ERR_PARAM; 3748 goto ena_txq_exit; 3749 } 3750 3751 /* find a parent node */ 3752 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3753 ICE_SCHED_NODE_OWNER_LAN); 3754 if (!parent) { 3755 status = ICE_ERR_PARAM; 3756 goto ena_txq_exit; 3757 } 3758 3759 buf->parent_teid = parent->info.node_teid; 3760 node.parent_teid = parent->info.node_teid; 3761 /* Mark that the values in the "generic" section as valid. The default 3762 * value in the "generic" section is zero. This means that : 3763 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3764 * - 0 priority among siblings, indicated by Bit 1-3. 3765 * - WFQ, indicated by Bit 4. 3766 * - 0 Adjustment value is used in PSM credit update flow, indicated by 3767 * Bit 5-6. 3768 * - Bit 7 is reserved. 3769 * Without setting the generic section as valid in valid_sections, the 3770 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3771 */ 3772 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 3773 3774 /* add the LAN queue */ 3775 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 3776 if (status != ICE_SUCCESS) { 3777 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 3778 LE16_TO_CPU(buf->txqs[0].txq_id), 3779 hw->adminq.sq_last_status); 3780 goto ena_txq_exit; 3781 } 3782 3783 node.node_teid = buf->txqs[0].q_teid; 3784 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3785 q_ctx->q_handle = q_handle; 3786 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 3787 3788 /* add a leaf node into scheduler tree queue layer */ 3789 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 3790 if (!status) 3791 status = ice_sched_replay_q_bw(pi, q_ctx); 3792 3793 ena_txq_exit: 3794 ice_release_lock(&pi->sched_lock); 3795 return status; 3796 } 3797 3798 /** 3799 * ice_dis_vsi_txq 3800 * @pi: port information structure 3801 * @vsi_handle: software VSI handle 3802 * @tc: TC number 3803 * @num_queues: number of queues 3804 * @q_handles: pointer to software queue handle array 3805 * @q_ids: pointer to the q_id array 3806 * @q_teids: pointer to queue node teids 3807 * @rst_src: if called due to reset, specifies the reset source 3808 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3809 * @cd: pointer to command details structure or NULL 3810 * 3811 * This function removes queues and their corresponding nodes in SW DB 3812 */ 3813 enum ice_status 3814 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3815 u16 *q_handles, u16 *q_ids, u32 *q_teids, 3816 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3817 struct ice_sq_cd *cd) 3818 { 3819 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 3820 struct ice_aqc_dis_txq_item qg_list; 3821 struct ice_q_ctx *q_ctx; 3822 u16 i; 3823 3824 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3825 return ICE_ERR_CFG; 3826 3827 if (!num_queues) { 3828 /* if queue is disabled already yet the disable queue command 3829 * has to be sent to complete the VF reset, then call 3830 * ice_aq_dis_lan_txq without any queue information 3831 */ 3832 if (rst_src) 3833 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, 3834 vmvf_num, NULL); 3835 return ICE_ERR_CFG; 3836 } 3837 3838 ice_acquire_lock(&pi->sched_lock); 3839 3840 for (i = 0; i < num_queues; i++) { 3841 struct ice_sched_node *node; 3842 3843 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3844 if (!node) 3845 continue; 3846 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]); 3847 if (!q_ctx) { 3848 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 3849 q_handles[i]); 3850 continue; 3851 } 3852 if (q_ctx->q_handle != q_handles[i]) { 3853 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 3854 q_ctx->q_handle, q_handles[i]); 3855 continue; 3856 } 3857 qg_list.parent_teid = node->info.parent_teid; 3858 qg_list.num_qs = 1; 3859 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]); 3860 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 3861 sizeof(qg_list), rst_src, vmvf_num, 3862 cd); 3863 3864 if (status != ICE_SUCCESS) 3865 break; 3866 ice_free_sched_node(pi, node); 3867 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 3868 } 3869 ice_release_lock(&pi->sched_lock); 3870 return status; 3871 } 3872 3873 /** 3874 * ice_cfg_vsi_qs - configure the new/existing VSI queues 3875 * @pi: port information structure 3876 * @vsi_handle: software VSI handle 3877 * @tc_bitmap: TC bitmap 3878 * @maxqs: max queues array per TC 3879 * @owner: LAN or RDMA 3880 * 3881 * This function adds/updates the VSI queues per TC. 3882 */ 3883 static enum ice_status 3884 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 3885 u16 *maxqs, u8 owner) 3886 { 3887 enum ice_status status = ICE_SUCCESS; 3888 u8 i; 3889 3890 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3891 return ICE_ERR_CFG; 3892 3893 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3894 return ICE_ERR_PARAM; 3895 3896 ice_acquire_lock(&pi->sched_lock); 3897 3898 ice_for_each_traffic_class(i) { 3899 /* configuration is possible only if TC node is present */ 3900 if (!ice_sched_get_tc_node(pi, i)) 3901 continue; 3902 3903 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 3904 ice_is_tc_ena(tc_bitmap, i)); 3905 if (status) 3906 break; 3907 } 3908 3909 ice_release_lock(&pi->sched_lock); 3910 return status; 3911 } 3912 3913 /** 3914 * ice_cfg_vsi_lan - configure VSI LAN queues 3915 * @pi: port information structure 3916 * @vsi_handle: software VSI handle 3917 * @tc_bitmap: TC bitmap 3918 * @max_lanqs: max LAN queues array per TC 3919 * 3920 * This function adds/updates the VSI LAN queues per TC. 3921 */ 3922 enum ice_status 3923 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 3924 u16 *max_lanqs) 3925 { 3926 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 3927 ICE_SCHED_NODE_OWNER_LAN); 3928 } 3929 3930 3931 3932 /** 3933 * ice_replay_pre_init - replay pre initialization 3934 * @hw: pointer to the HW struct 3935 * 3936 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 3937 */ 3938 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 3939 { 3940 struct ice_switch_info *sw = hw->switch_info; 3941 u8 i; 3942 3943 /* Delete old entries from replay filter list head if there is any */ 3944 ice_rm_all_sw_replay_rule_info(hw); 3945 /* In start of replay, move entries into replay_rules list, it 3946 * will allow adding rules entries back to filt_rules list, 3947 * which is operational list. 3948 */ 3949 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 3950 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 3951 &sw->recp_list[i].filt_replay_rules); 3952 ice_sched_replay_agg_vsi_preinit(hw); 3953 3954 return ice_sched_replay_tc_node_bw(hw); 3955 } 3956 3957 /** 3958 * ice_replay_vsi - replay VSI configuration 3959 * @hw: pointer to the HW struct 3960 * @vsi_handle: driver VSI handle 3961 * 3962 * Restore all VSI configuration after reset. It is required to call this 3963 * function with main VSI first. 3964 */ 3965 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 3966 { 3967 enum ice_status status; 3968 3969 if (!ice_is_vsi_valid(hw, vsi_handle)) 3970 return ICE_ERR_PARAM; 3971 3972 /* Replay pre-initialization if there is any */ 3973 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 3974 status = ice_replay_pre_init(hw); 3975 if (status) 3976 return status; 3977 } 3978 /* Replay per VSI all RSS configurations */ 3979 status = ice_replay_rss_cfg(hw, vsi_handle); 3980 if (status) 3981 return status; 3982 /* Replay per VSI all filters */ 3983 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 3984 if (!status) 3985 status = ice_replay_vsi_agg(hw, vsi_handle); 3986 return status; 3987 } 3988 3989 /** 3990 * ice_replay_post - post replay configuration cleanup 3991 * @hw: pointer to the HW struct 3992 * 3993 * Post replay cleanup. 3994 */ 3995 void ice_replay_post(struct ice_hw *hw) 3996 { 3997 /* Delete old entries from replay filter list head */ 3998 ice_rm_all_sw_replay_rule_info(hw); 3999 ice_sched_replay_agg(hw); 4000 } 4001 4002 /** 4003 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4004 * @hw: ptr to the hardware info 4005 * @reg: offset of 64 bit HW register to read from 4006 * @prev_stat_loaded: bool to specify if previous stats are loaded 4007 * @prev_stat: ptr to previous loaded stat value 4008 * @cur_stat: ptr to current stat value 4009 */ 4010 void 4011 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4012 u64 *prev_stat, u64 *cur_stat) 4013 { 4014 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4015 4016 /* device stats are not reset at PFR, they likely will not be zeroed 4017 * when the driver starts. Thus, save the value from the first read 4018 * without adding to the statistic value so that we report stats which 4019 * count up from zero. 4020 */ 4021 if (!prev_stat_loaded) { 4022 *prev_stat = new_data; 4023 return; 4024 } 4025 4026 /* Calculate the difference between the new and old values, and then 4027 * add it to the software stat value. 4028 */ 4029 if (new_data >= *prev_stat) 4030 *cur_stat += new_data - *prev_stat; 4031 else 4032 /* to manage the potential roll-over */ 4033 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4034 4035 /* Update the previously stored value to prepare for next read */ 4036 *prev_stat = new_data; 4037 } 4038 4039 /** 4040 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4041 * @hw: ptr to the hardware info 4042 * @reg: offset of HW register to read from 4043 * @prev_stat_loaded: bool to specify if previous stats are loaded 4044 * @prev_stat: ptr to previous loaded stat value 4045 * @cur_stat: ptr to current stat value 4046 */ 4047 void 4048 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4049 u64 *prev_stat, u64 *cur_stat) 4050 { 4051 u32 new_data; 4052 4053 new_data = rd32(hw, reg); 4054 4055 /* device stats are not reset at PFR, they likely will not be zeroed 4056 * when the driver starts. Thus, save the value from the first read 4057 * without adding to the statistic value so that we report stats which 4058 * count up from zero. 4059 */ 4060 if (!prev_stat_loaded) { 4061 *prev_stat = new_data; 4062 return; 4063 } 4064 4065 /* Calculate the difference between the new and old values, and then 4066 * add it to the software stat value. 4067 */ 4068 if (new_data >= *prev_stat) 4069 *cur_stat += new_data - *prev_stat; 4070 else 4071 /* to manage the potential roll-over */ 4072 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4073 4074 /* Update the previously stored value to prepare for next read */ 4075 *prev_stat = new_data; 4076 } 4077 4078 4079 /** 4080 * ice_sched_query_elem - query element information from HW 4081 * @hw: pointer to the HW struct 4082 * @node_teid: node TEID to be queried 4083 * @buf: buffer to element information 4084 * 4085 * This function queries HW element information 4086 */ 4087 enum ice_status 4088 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4089 struct ice_aqc_get_elem *buf) 4090 { 4091 u16 buf_size, num_elem_ret = 0; 4092 enum ice_status status; 4093 4094 buf_size = sizeof(*buf); 4095 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 4096 buf->generic[0].node_teid = CPU_TO_LE32(node_teid); 4097 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4098 NULL); 4099 if (status != ICE_SUCCESS || num_elem_ret != 1) 4100 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4101 return status; 4102 } 4103 4104 /** 4105 * ice_is_fw_in_rec_mode 4106 * @hw: pointer to the HW struct 4107 * 4108 * This function returns true if fw is in recovery mode 4109 */ 4110 bool ice_is_fw_in_rec_mode(struct ice_hw *hw) 4111 { 4112 u32 reg; 4113 4114 /* check the current FW mode */ 4115 reg = rd32(hw, GL_MNG_FWSM); 4116 return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG; 4117 } 4118