1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2019 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 200 13 14 /** 15 * ice_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the MAC type of the adapter based on the 19 * vendor ID and device ID stored in the HW structure. 20 */ 21 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 22 { 23 enum ice_status status = ICE_SUCCESS; 24 25 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 26 27 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) { 28 switch (hw->device_id) { 29 default: 30 hw->mac_type = ICE_MAC_GENERIC; 31 break; 32 } 33 } else { 34 status = ICE_ERR_DEVICE_NOT_SUPPORTED; 35 } 36 37 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n", 38 hw->mac_type, status); 39 40 return status; 41 } 42 43 /** 44 * ice_clear_pf_cfg - Clear PF configuration 45 * @hw: pointer to the hardware structure 46 * 47 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 48 * configuration, flow director filters, etc.). 49 */ 50 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 51 { 52 struct ice_aq_desc desc; 53 54 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 55 56 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 57 } 58 59 /** 60 * ice_aq_manage_mac_read - manage MAC address read command 61 * @hw: pointer to the HW struct 62 * @buf: a virtual buffer to hold the manage MAC read response 63 * @buf_size: Size of the virtual buffer 64 * @cd: pointer to command details structure or NULL 65 * 66 * This function is used to return per PF station MAC address (0x0107). 67 * NOTE: Upon successful completion of this command, MAC address information 68 * is returned in user specified buffer. Please interpret user specified 69 * buffer as "manage_mac_read" response. 70 * Response such as various MAC addresses are stored in HW struct (port.mac) 71 * ice_aq_discover_caps is expected to be called before this function is called. 72 */ 73 static enum ice_status 74 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 75 struct ice_sq_cd *cd) 76 { 77 struct ice_aqc_manage_mac_read_resp *resp; 78 struct ice_aqc_manage_mac_read *cmd; 79 struct ice_aq_desc desc; 80 enum ice_status status; 81 u16 flags; 82 u8 i; 83 84 cmd = &desc.params.mac_read; 85 86 if (buf_size < sizeof(*resp)) 87 return ICE_ERR_BUF_TOO_SHORT; 88 89 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 90 91 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 92 if (status) 93 return status; 94 95 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 96 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 97 98 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 99 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 100 return ICE_ERR_CFG; 101 } 102 103 /* A single port can report up to two (LAN and WoL) addresses */ 104 for (i = 0; i < cmd->num_addr; i++) 105 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 106 ice_memcpy(hw->port_info->mac.lan_addr, 107 resp[i].mac_addr, ETH_ALEN, 108 ICE_DMA_TO_NONDMA); 109 ice_memcpy(hw->port_info->mac.perm_addr, 110 resp[i].mac_addr, 111 ETH_ALEN, ICE_DMA_TO_NONDMA); 112 break; 113 } 114 return ICE_SUCCESS; 115 } 116 117 /** 118 * ice_aq_get_phy_caps - returns PHY capabilities 119 * @pi: port information structure 120 * @qual_mods: report qualified modules 121 * @report_mode: report mode capabilities 122 * @pcaps: structure for PHY capabilities to be filled 123 * @cd: pointer to command details structure or NULL 124 * 125 * Returns the various PHY capabilities supported on the Port (0x0600) 126 */ 127 enum ice_status 128 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 129 struct ice_aqc_get_phy_caps_data *pcaps, 130 struct ice_sq_cd *cd) 131 { 132 struct ice_aqc_get_phy_caps *cmd; 133 u16 pcaps_size = sizeof(*pcaps); 134 struct ice_aq_desc desc; 135 enum ice_status status; 136 137 cmd = &desc.params.get_phy; 138 139 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 140 return ICE_ERR_PARAM; 141 142 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 143 144 if (qual_mods) 145 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 146 147 cmd->param0 |= CPU_TO_LE16(report_mode); 148 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); 149 150 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 151 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 152 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 153 } 154 155 return status; 156 } 157 158 /** 159 * ice_aq_get_link_topo_handle - get link topology node return status 160 * @pi: port information structure 161 * @node_type: requested node type 162 * @cd: pointer to command details structure or NULL 163 * 164 * Get link topology node return status for specified node type (0x06E0) 165 * 166 * Node type cage can be used to determine if cage is present. If AQC 167 * returns error (ENOENT), then no cage present. If no cage present, then 168 * connection type is backplane or BASE-T. 169 */ 170 static enum ice_status 171 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 172 struct ice_sq_cd *cd) 173 { 174 struct ice_aqc_get_link_topo *cmd; 175 struct ice_aq_desc desc; 176 177 cmd = &desc.params.get_link_topo; 178 179 if (!cmd) 180 return ICE_ERR_PARAM; 181 182 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 183 184 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 185 ICE_AQC_LINK_TOPO_NODE_CTX_S); 186 187 /* set node type */ 188 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 189 190 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 191 } 192 193 /** 194 * ice_is_media_cage_present 195 * @pi: port information structure 196 * 197 * Returns true if media cage is present, else false. If no cage, then 198 * media type is backplane or BASE-T. 199 */ 200 static bool ice_is_media_cage_present(struct ice_port_info *pi) 201 { 202 /* Node type cage can be used to determine if cage is present. If AQC 203 * returns error (ENOENT), then no cage present. If no cage present then 204 * connection type is backplane or BASE-T. 205 */ 206 return !ice_aq_get_link_topo_handle(pi, 207 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 208 NULL); 209 } 210 211 /** 212 * ice_get_media_type - Gets media type 213 * @pi: port information structure 214 */ 215 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 216 { 217 struct ice_link_status *hw_link_info; 218 219 if (!pi) 220 return ICE_MEDIA_UNKNOWN; 221 222 hw_link_info = &pi->phy.link_info; 223 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 224 /* If more than one media type is selected, report unknown */ 225 return ICE_MEDIA_UNKNOWN; 226 227 if (hw_link_info->phy_type_low) { 228 switch (hw_link_info->phy_type_low) { 229 case ICE_PHY_TYPE_LOW_1000BASE_SX: 230 case ICE_PHY_TYPE_LOW_1000BASE_LX: 231 case ICE_PHY_TYPE_LOW_10GBASE_SR: 232 case ICE_PHY_TYPE_LOW_10GBASE_LR: 233 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 234 case ICE_PHY_TYPE_LOW_25GBASE_SR: 235 case ICE_PHY_TYPE_LOW_25GBASE_LR: 236 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 237 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 238 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 239 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 240 case ICE_PHY_TYPE_LOW_50GBASE_SR: 241 case ICE_PHY_TYPE_LOW_50GBASE_FR: 242 case ICE_PHY_TYPE_LOW_50GBASE_LR: 243 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 244 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 245 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 246 case ICE_PHY_TYPE_LOW_100GBASE_DR: 247 return ICE_MEDIA_FIBER; 248 case ICE_PHY_TYPE_LOW_100BASE_TX: 249 case ICE_PHY_TYPE_LOW_1000BASE_T: 250 case ICE_PHY_TYPE_LOW_2500BASE_T: 251 case ICE_PHY_TYPE_LOW_5GBASE_T: 252 case ICE_PHY_TYPE_LOW_10GBASE_T: 253 case ICE_PHY_TYPE_LOW_25GBASE_T: 254 return ICE_MEDIA_BASET; 255 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 256 case ICE_PHY_TYPE_LOW_25GBASE_CR: 257 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 258 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 259 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 260 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 261 case ICE_PHY_TYPE_LOW_50GBASE_CP: 262 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 263 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 264 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 265 return ICE_MEDIA_DA; 266 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 267 case ICE_PHY_TYPE_LOW_40G_XLAUI: 268 case ICE_PHY_TYPE_LOW_50G_LAUI2: 269 case ICE_PHY_TYPE_LOW_50G_AUI2: 270 case ICE_PHY_TYPE_LOW_50G_AUI1: 271 case ICE_PHY_TYPE_LOW_100G_AUI4: 272 case ICE_PHY_TYPE_LOW_100G_CAUI4: 273 if (ice_is_media_cage_present(pi)) 274 return ICE_MEDIA_DA; 275 /* fall-through */ 276 case ICE_PHY_TYPE_LOW_1000BASE_KX: 277 case ICE_PHY_TYPE_LOW_2500BASE_KX: 278 case ICE_PHY_TYPE_LOW_2500BASE_X: 279 case ICE_PHY_TYPE_LOW_5GBASE_KR: 280 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 281 case ICE_PHY_TYPE_LOW_25GBASE_KR: 282 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 283 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 284 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 285 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 286 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 287 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 288 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 289 return ICE_MEDIA_BACKPLANE; 290 } 291 } else { 292 switch (hw_link_info->phy_type_high) { 293 case ICE_PHY_TYPE_HIGH_100G_AUI2: 294 if (ice_is_media_cage_present(pi)) 295 return ICE_MEDIA_DA; 296 /* fall-through */ 297 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 298 return ICE_MEDIA_BACKPLANE; 299 } 300 } 301 return ICE_MEDIA_UNKNOWN; 302 } 303 304 /** 305 * ice_aq_get_link_info 306 * @pi: port information structure 307 * @ena_lse: enable/disable LinkStatusEvent reporting 308 * @link: pointer to link status structure - optional 309 * @cd: pointer to command details structure or NULL 310 * 311 * Get Link Status (0x607). Returns the link status of the adapter. 312 */ 313 enum ice_status 314 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 315 struct ice_link_status *link, struct ice_sq_cd *cd) 316 { 317 struct ice_aqc_get_link_status_data link_data = { 0 }; 318 struct ice_aqc_get_link_status *resp; 319 struct ice_link_status *li_old, *li; 320 enum ice_media_type *hw_media_type; 321 struct ice_fc_info *hw_fc_info; 322 bool tx_pause, rx_pause; 323 struct ice_aq_desc desc; 324 enum ice_status status; 325 struct ice_hw *hw; 326 u16 cmd_flags; 327 328 if (!pi) 329 return ICE_ERR_PARAM; 330 hw = pi->hw; 331 li_old = &pi->phy.link_info_old; 332 hw_media_type = &pi->phy.media_type; 333 li = &pi->phy.link_info; 334 hw_fc_info = &pi->fc; 335 336 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 337 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 338 resp = &desc.params.get_link_status; 339 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 340 resp->lport_num = pi->lport; 341 342 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 343 344 if (status != ICE_SUCCESS) 345 return status; 346 347 /* save off old link status information */ 348 *li_old = *li; 349 350 /* update current link status information */ 351 li->link_speed = LE16_TO_CPU(link_data.link_speed); 352 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 353 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 354 *hw_media_type = ice_get_media_type(pi); 355 li->link_info = link_data.link_info; 356 li->an_info = link_data.an_info; 357 li->ext_info = link_data.ext_info; 358 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 359 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 360 li->topo_media_conflict = link_data.topo_media_conflict; 361 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 362 ICE_AQ_CFG_PACING_TYPE_M); 363 364 /* update fc info */ 365 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 366 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 367 if (tx_pause && rx_pause) 368 hw_fc_info->current_mode = ICE_FC_FULL; 369 else if (tx_pause) 370 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 371 else if (rx_pause) 372 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 373 else 374 hw_fc_info->current_mode = ICE_FC_NONE; 375 376 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 377 378 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed); 379 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n", 380 (unsigned long long)li->phy_type_low); 381 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n", 382 (unsigned long long)li->phy_type_high); 383 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type); 384 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info); 385 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info); 386 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info); 387 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena); 388 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size); 389 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing); 390 391 /* save link status information */ 392 if (link) 393 *link = *li; 394 395 /* flag cleared so calling functions don't call AQ again */ 396 pi->phy.get_link_info = false; 397 398 return ICE_SUCCESS; 399 } 400 401 /** 402 * ice_aq_set_mac_cfg 403 * @hw: pointer to the HW struct 404 * @max_frame_size: Maximum Frame Size to be supported 405 * @cd: pointer to command details structure or NULL 406 * 407 * Set MAC configuration (0x0603) 408 */ 409 enum ice_status 410 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 411 { 412 u16 fc_threshold_val, tx_timer_val; 413 struct ice_aqc_set_mac_cfg *cmd; 414 struct ice_aq_desc desc; 415 u32 reg_val; 416 417 cmd = &desc.params.set_mac_cfg; 418 419 if (max_frame_size == 0) 420 return ICE_ERR_PARAM; 421 422 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 423 424 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 425 426 /* We read back the transmit timer and fc threshold value of 427 * LFC. Thus, we will use index = 428 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 429 * 430 * Also, because we are opearating on transmit timer and fc 431 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 432 */ 433 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 434 435 /* Retrieve the transmit timer */ 436 reg_val = rd32(hw, 437 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 438 tx_timer_val = reg_val & 439 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 440 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 441 442 /* Retrieve the fc threshold */ 443 reg_val = rd32(hw, 444 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 445 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0); 446 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val); 447 448 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 449 } 450 451 /** 452 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 453 * @hw: pointer to the HW struct 454 */ 455 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 456 { 457 struct ice_switch_info *sw; 458 459 hw->switch_info = (struct ice_switch_info *) 460 ice_malloc(hw, sizeof(*hw->switch_info)); 461 sw = hw->switch_info; 462 463 if (!sw) 464 return ICE_ERR_NO_MEMORY; 465 466 INIT_LIST_HEAD(&sw->vsi_list_map_head); 467 468 return ice_init_def_sw_recp(hw); 469 } 470 471 /** 472 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 473 * @hw: pointer to the HW struct 474 */ 475 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 476 { 477 struct ice_switch_info *sw = hw->switch_info; 478 struct ice_vsi_list_map_info *v_pos_map; 479 struct ice_vsi_list_map_info *v_tmp_map; 480 struct ice_sw_recipe *recps; 481 u8 i; 482 483 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 484 ice_vsi_list_map_info, list_entry) { 485 LIST_DEL(&v_pos_map->list_entry); 486 ice_free(hw, v_pos_map); 487 } 488 recps = hw->switch_info->recp_list; 489 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 490 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 491 492 recps[i].root_rid = i; 493 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 494 &recps[i].rg_list, ice_recp_grp_entry, 495 l_entry) { 496 LIST_DEL(&rg_entry->l_entry); 497 ice_free(hw, rg_entry); 498 } 499 500 if (recps[i].adv_rule) { 501 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 502 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 503 504 ice_destroy_lock(&recps[i].filt_rule_lock); 505 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 506 &recps[i].filt_rules, 507 ice_adv_fltr_mgmt_list_entry, 508 list_entry) { 509 LIST_DEL(&lst_itr->list_entry); 510 ice_free(hw, lst_itr->lkups); 511 ice_free(hw, lst_itr); 512 } 513 } else { 514 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 515 516 ice_destroy_lock(&recps[i].filt_rule_lock); 517 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 518 &recps[i].filt_rules, 519 ice_fltr_mgmt_list_entry, 520 list_entry) { 521 LIST_DEL(&lst_itr->list_entry); 522 ice_free(hw, lst_itr); 523 } 524 } 525 if (recps[i].root_buf) 526 ice_free(hw, recps[i].root_buf); 527 } 528 ice_rm_all_sw_replay_rule_info(hw); 529 ice_free(hw, sw->recp_list); 530 ice_free(hw, sw); 531 } 532 533 /** 534 * ice_get_itr_intrl_gran 535 * @hw: pointer to the HW struct 536 * 537 * Determines the ITR/INTRL granularities based on the maximum aggregate 538 * bandwidth according to the device's configuration during power-on. 539 */ 540 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 541 { 542 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 543 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 544 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 545 546 switch (max_agg_bw) { 547 case ICE_MAX_AGG_BW_200G: 548 case ICE_MAX_AGG_BW_100G: 549 case ICE_MAX_AGG_BW_50G: 550 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 551 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 552 break; 553 case ICE_MAX_AGG_BW_25G: 554 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 555 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 556 break; 557 } 558 } 559 560 /** 561 * ice_get_nvm_version - get cached NVM version data 562 * @hw: pointer to the hardware structure 563 * @oem_ver: 8 bit NVM version 564 * @oem_build: 16 bit NVM build number 565 * @oem_patch: 8 NVM patch number 566 * @ver_hi: high 16 bits of the NVM version 567 * @ver_lo: low 16 bits of the NVM version 568 */ 569 void 570 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build, 571 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo) 572 { 573 struct ice_nvm_info *nvm = &hw->nvm; 574 575 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT); 576 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK); 577 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >> 578 ICE_OEM_VER_BUILD_SHIFT); 579 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT; 580 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT; 581 } 582 583 /** 584 * ice_print_rollback_msg - print FW rollback message 585 * @hw: pointer to the hardware structure 586 */ 587 void ice_print_rollback_msg(struct ice_hw *hw) 588 { 589 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 590 u8 oem_ver, oem_patch, ver_hi, ver_lo; 591 u16 oem_build; 592 593 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi, 594 &ver_lo); 595 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi, 596 ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch); 597 ice_warn(hw, 598 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode", 599 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 600 } 601 602 /** 603 * ice_init_hw - main hardware initialization routine 604 * @hw: pointer to the hardware structure 605 */ 606 enum ice_status ice_init_hw(struct ice_hw *hw) 607 { 608 struct ice_aqc_get_phy_caps_data *pcaps; 609 enum ice_status status; 610 u16 mac_buf_len; 611 void *mac_buf; 612 613 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 614 615 /* Set MAC type based on DeviceID */ 616 status = ice_set_mac_type(hw); 617 if (status) 618 return status; 619 620 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 621 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 622 PF_FUNC_RID_FUNCTION_NUMBER_S; 623 624 status = ice_reset(hw, ICE_RESET_PFR); 625 if (status) 626 return status; 627 628 ice_get_itr_intrl_gran(hw); 629 630 status = ice_create_all_ctrlq(hw); 631 if (status) 632 goto err_unroll_cqinit; 633 634 status = ice_init_nvm(hw); 635 if (status) 636 goto err_unroll_cqinit; 637 638 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 639 ice_print_rollback_msg(hw); 640 641 status = ice_clear_pf_cfg(hw); 642 if (status) 643 goto err_unroll_cqinit; 644 645 /* Set bit to enable Flow Director filters */ 646 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 647 INIT_LIST_HEAD(&hw->fdir_list_head); 648 649 ice_clear_pxe_mode(hw); 650 651 652 status = ice_get_caps(hw); 653 if (status) 654 goto err_unroll_cqinit; 655 656 hw->port_info = (struct ice_port_info *) 657 ice_malloc(hw, sizeof(*hw->port_info)); 658 if (!hw->port_info) { 659 status = ICE_ERR_NO_MEMORY; 660 goto err_unroll_cqinit; 661 } 662 663 /* set the back pointer to HW */ 664 hw->port_info->hw = hw; 665 666 /* Initialize port_info struct with switch configuration data */ 667 status = ice_get_initial_sw_cfg(hw); 668 if (status) 669 goto err_unroll_alloc; 670 671 hw->evb_veb = true; 672 673 /* Query the allocated resources for Tx scheduler */ 674 status = ice_sched_query_res_alloc(hw); 675 if (status) { 676 ice_debug(hw, ICE_DBG_SCHED, 677 "Failed to get scheduler allocated resources\n"); 678 goto err_unroll_alloc; 679 } 680 681 /* Initialize port_info struct with scheduler data */ 682 status = ice_sched_init_port(hw->port_info); 683 if (status) 684 goto err_unroll_sched; 685 686 pcaps = (struct ice_aqc_get_phy_caps_data *) 687 ice_malloc(hw, sizeof(*pcaps)); 688 if (!pcaps) { 689 status = ICE_ERR_NO_MEMORY; 690 goto err_unroll_sched; 691 } 692 693 /* Initialize port_info struct with PHY capabilities */ 694 status = ice_aq_get_phy_caps(hw->port_info, false, 695 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 696 ice_free(hw, pcaps); 697 if (status) 698 goto err_unroll_sched; 699 700 /* Initialize port_info struct with link information */ 701 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 702 if (status) 703 goto err_unroll_sched; 704 /* need a valid SW entry point to build a Tx tree */ 705 if (!hw->sw_entry_point_layer) { 706 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 707 status = ICE_ERR_CFG; 708 goto err_unroll_sched; 709 } 710 INIT_LIST_HEAD(&hw->agg_list); 711 /* Initialize max burst size */ 712 if (!hw->max_burst_size) 713 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 714 715 status = ice_init_fltr_mgmt_struct(hw); 716 if (status) 717 goto err_unroll_sched; 718 719 /* Get MAC information */ 720 /* A single port can report up to two (LAN and WoL) addresses */ 721 mac_buf = ice_calloc(hw, 2, 722 sizeof(struct ice_aqc_manage_mac_read_resp)); 723 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 724 725 if (!mac_buf) { 726 status = ICE_ERR_NO_MEMORY; 727 goto err_unroll_fltr_mgmt_struct; 728 } 729 730 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 731 ice_free(hw, mac_buf); 732 733 if (status) 734 goto err_unroll_fltr_mgmt_struct; 735 /* Obtain counter base index which would be used by flow director */ 736 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 737 if (status) 738 goto err_unroll_fltr_mgmt_struct; 739 status = ice_init_hw_tbls(hw); 740 if (status) 741 goto err_unroll_fltr_mgmt_struct; 742 return ICE_SUCCESS; 743 744 err_unroll_fltr_mgmt_struct: 745 ice_cleanup_fltr_mgmt_struct(hw); 746 err_unroll_sched: 747 ice_sched_cleanup_all(hw); 748 err_unroll_alloc: 749 ice_free(hw, hw->port_info); 750 hw->port_info = NULL; 751 err_unroll_cqinit: 752 ice_destroy_all_ctrlq(hw); 753 return status; 754 } 755 756 /** 757 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 758 * @hw: pointer to the hardware structure 759 * 760 * This should be called only during nominal operation, not as a result of 761 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 762 * applicable initializations if it fails for any reason. 763 */ 764 void ice_deinit_hw(struct ice_hw *hw) 765 { 766 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 767 ice_cleanup_fltr_mgmt_struct(hw); 768 769 ice_sched_cleanup_all(hw); 770 ice_sched_clear_agg(hw); 771 ice_free_seg(hw); 772 ice_free_hw_tbls(hw); 773 774 if (hw->port_info) { 775 ice_free(hw, hw->port_info); 776 hw->port_info = NULL; 777 } 778 779 ice_destroy_all_ctrlq(hw); 780 781 /* Clear VSI contexts if not already cleared */ 782 ice_clear_all_vsi_ctx(hw); 783 } 784 785 /** 786 * ice_check_reset - Check to see if a global reset is complete 787 * @hw: pointer to the hardware structure 788 */ 789 enum ice_status ice_check_reset(struct ice_hw *hw) 790 { 791 u32 cnt, reg = 0, grst_delay; 792 793 /* Poll for Device Active state in case a recent CORER, GLOBR, 794 * or EMPR has occurred. The grst delay value is in 100ms units. 795 * Add 1sec for outstanding AQ commands that can take a long time. 796 */ 797 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 798 GLGEN_RSTCTL_GRSTDEL_S) + 10; 799 800 for (cnt = 0; cnt < grst_delay; cnt++) { 801 ice_msec_delay(100, true); 802 reg = rd32(hw, GLGEN_RSTAT); 803 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 804 break; 805 } 806 807 if (cnt == grst_delay) { 808 ice_debug(hw, ICE_DBG_INIT, 809 "Global reset polling failed to complete.\n"); 810 return ICE_ERR_RESET_FAILED; 811 } 812 813 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ 814 GLNVM_ULD_GLOBR_DONE_M) 815 816 /* Device is Active; check Global Reset processes are done */ 817 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 818 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; 819 if (reg == ICE_RESET_DONE_MASK) { 820 ice_debug(hw, ICE_DBG_INIT, 821 "Global reset processes done. %d\n", cnt); 822 break; 823 } 824 ice_msec_delay(10, true); 825 } 826 827 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 828 ice_debug(hw, ICE_DBG_INIT, 829 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 830 reg); 831 return ICE_ERR_RESET_FAILED; 832 } 833 834 return ICE_SUCCESS; 835 } 836 837 /** 838 * ice_pf_reset - Reset the PF 839 * @hw: pointer to the hardware structure 840 * 841 * If a global reset has been triggered, this function checks 842 * for its completion and then issues the PF reset 843 */ 844 static enum ice_status ice_pf_reset(struct ice_hw *hw) 845 { 846 u32 cnt, reg; 847 848 /* If at function entry a global reset was already in progress, i.e. 849 * state is not 'device active' or any of the reset done bits are not 850 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 851 * global reset is done. 852 */ 853 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 854 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 855 /* poll on global reset currently in progress until done */ 856 if (ice_check_reset(hw)) 857 return ICE_ERR_RESET_FAILED; 858 859 return ICE_SUCCESS; 860 } 861 862 /* Reset the PF */ 863 reg = rd32(hw, PFGEN_CTRL); 864 865 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 866 867 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 868 reg = rd32(hw, PFGEN_CTRL); 869 if (!(reg & PFGEN_CTRL_PFSWR_M)) 870 break; 871 872 ice_msec_delay(1, true); 873 } 874 875 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 876 ice_debug(hw, ICE_DBG_INIT, 877 "PF reset polling failed to complete.\n"); 878 return ICE_ERR_RESET_FAILED; 879 } 880 881 return ICE_SUCCESS; 882 } 883 884 /** 885 * ice_reset - Perform different types of reset 886 * @hw: pointer to the hardware structure 887 * @req: reset request 888 * 889 * This function triggers a reset as specified by the req parameter. 890 * 891 * Note: 892 * If anything other than a PF reset is triggered, PXE mode is restored. 893 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 894 * interface has been restored in the rebuild flow. 895 */ 896 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 897 { 898 u32 val = 0; 899 900 switch (req) { 901 case ICE_RESET_PFR: 902 return ice_pf_reset(hw); 903 case ICE_RESET_CORER: 904 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 905 val = GLGEN_RTRIG_CORER_M; 906 break; 907 case ICE_RESET_GLOBR: 908 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 909 val = GLGEN_RTRIG_GLOBR_M; 910 break; 911 default: 912 return ICE_ERR_PARAM; 913 } 914 915 val |= rd32(hw, GLGEN_RTRIG); 916 wr32(hw, GLGEN_RTRIG, val); 917 ice_flush(hw); 918 919 /* wait for the FW to be ready */ 920 return ice_check_reset(hw); 921 } 922 923 /** 924 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA 925 * @hw: pointer to hardware structure 926 * @module_tlv: pointer to module TLV to return 927 * @module_tlv_len: pointer to module TLV length to return 928 * @module_type: module type requested 929 * 930 * Finds the requested sub module TLV type from the Preserved Field 931 * Area (PFA) and returns the TLV pointer and length. The caller can 932 * use these to read the variable length TLV value. 933 */ 934 enum ice_status 935 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, 936 u16 module_type) 937 { 938 enum ice_status status; 939 u16 pfa_len, pfa_ptr; 940 u16 next_tlv; 941 942 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr); 943 if (status != ICE_SUCCESS) { 944 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n"); 945 return status; 946 } 947 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len); 948 if (status != ICE_SUCCESS) { 949 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n"); 950 return status; 951 } 952 /* Starting with first TLV after PFA length, iterate through the list 953 * of TLVs to find the requested one. 954 */ 955 next_tlv = pfa_ptr + 1; 956 while (next_tlv < pfa_ptr + pfa_len) { 957 u16 tlv_sub_module_type; 958 u16 tlv_len; 959 960 /* Read TLV type */ 961 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type); 962 if (status != ICE_SUCCESS) { 963 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n"); 964 break; 965 } 966 /* Read TLV length */ 967 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len); 968 if (status != ICE_SUCCESS) { 969 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n"); 970 break; 971 } 972 if (tlv_sub_module_type == module_type) { 973 if (tlv_len) { 974 *module_tlv = next_tlv; 975 *module_tlv_len = tlv_len; 976 return ICE_SUCCESS; 977 } 978 return ICE_ERR_INVAL_SIZE; 979 } 980 /* Check next TLV, i.e. current TLV pointer + length + 2 words 981 * (for current TLV's type and length) 982 */ 983 next_tlv = next_tlv + tlv_len + 2; 984 } 985 /* Module does not exist */ 986 return ICE_ERR_DOES_NOT_EXIST; 987 } 988 989 /** 990 * ice_copy_rxq_ctx_to_hw 991 * @hw: pointer to the hardware structure 992 * @ice_rxq_ctx: pointer to the rxq context 993 * @rxq_index: the index of the Rx queue 994 * 995 * Copies rxq context from dense structure to HW register space 996 */ 997 static enum ice_status 998 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 999 { 1000 u8 i; 1001 1002 if (!ice_rxq_ctx) 1003 return ICE_ERR_BAD_PTR; 1004 1005 if (rxq_index > QRX_CTRL_MAX_INDEX) 1006 return ICE_ERR_PARAM; 1007 1008 /* Copy each dword separately to HW */ 1009 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1010 wr32(hw, QRX_CONTEXT(i, rxq_index), 1011 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1012 1013 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1014 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1015 } 1016 1017 return ICE_SUCCESS; 1018 } 1019 1020 /* LAN Rx Queue Context */ 1021 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1022 /* Field Width LSB */ 1023 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1024 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1025 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1026 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1027 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1028 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1029 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1030 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1031 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1032 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1033 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1034 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1035 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1036 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1037 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1038 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1039 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1040 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1041 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1042 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1043 { 0 } 1044 }; 1045 1046 /** 1047 * ice_write_rxq_ctx 1048 * @hw: pointer to the hardware structure 1049 * @rlan_ctx: pointer to the rxq context 1050 * @rxq_index: the index of the Rx queue 1051 * 1052 * Converts rxq context from sparse to dense structure and then writes 1053 * it to HW register space and enables the hardware to prefetch descriptors 1054 * instead of only fetching them on demand 1055 */ 1056 enum ice_status 1057 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1058 u32 rxq_index) 1059 { 1060 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1061 1062 if (!rlan_ctx) 1063 return ICE_ERR_BAD_PTR; 1064 1065 rlan_ctx->prefena = 1; 1066 1067 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1068 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1069 } 1070 1071 /** 1072 * ice_clear_rxq_ctx 1073 * @hw: pointer to the hardware structure 1074 * @rxq_index: the index of the Rx queue to clear 1075 * 1076 * Clears rxq context in HW register space 1077 */ 1078 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1079 { 1080 u8 i; 1081 1082 if (rxq_index > QRX_CTRL_MAX_INDEX) 1083 return ICE_ERR_PARAM; 1084 1085 /* Clear each dword register separately */ 1086 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1087 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1088 1089 return ICE_SUCCESS; 1090 } 1091 1092 /* LAN Tx Queue Context */ 1093 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1094 /* Field Width LSB */ 1095 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1096 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1097 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1098 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1099 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1100 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1101 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1102 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1103 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1104 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1105 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1106 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1107 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1108 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1109 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1110 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1111 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1112 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1113 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1114 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1115 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1116 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1117 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1118 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1119 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1120 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1121 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1122 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1123 { 0 } 1124 }; 1125 1126 /** 1127 * ice_copy_tx_cmpltnq_ctx_to_hw 1128 * @hw: pointer to the hardware structure 1129 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1130 * @tx_cmpltnq_index: the index of the completion queue 1131 * 1132 * Copies Tx completion queue context from dense structure to HW register space 1133 */ 1134 static enum ice_status 1135 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1136 u32 tx_cmpltnq_index) 1137 { 1138 u8 i; 1139 1140 if (!ice_tx_cmpltnq_ctx) 1141 return ICE_ERR_BAD_PTR; 1142 1143 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1144 return ICE_ERR_PARAM; 1145 1146 /* Copy each dword separately to HW */ 1147 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1148 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1149 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1150 1151 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1152 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1153 } 1154 1155 return ICE_SUCCESS; 1156 } 1157 1158 /* LAN Tx Completion Queue Context */ 1159 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1160 /* Field Width LSB */ 1161 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1162 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1163 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1164 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1165 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1166 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1167 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1168 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1169 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1170 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1171 { 0 } 1172 }; 1173 1174 /** 1175 * ice_write_tx_cmpltnq_ctx 1176 * @hw: pointer to the hardware structure 1177 * @tx_cmpltnq_ctx: pointer to the completion queue context 1178 * @tx_cmpltnq_index: the index of the completion queue 1179 * 1180 * Converts completion queue context from sparse to dense structure and then 1181 * writes it to HW register space 1182 */ 1183 enum ice_status 1184 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1185 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1186 u32 tx_cmpltnq_index) 1187 { 1188 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1189 1190 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1191 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1192 } 1193 1194 /** 1195 * ice_clear_tx_cmpltnq_ctx 1196 * @hw: pointer to the hardware structure 1197 * @tx_cmpltnq_index: the index of the completion queue to clear 1198 * 1199 * Clears Tx completion queue context in HW register space 1200 */ 1201 enum ice_status 1202 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1203 { 1204 u8 i; 1205 1206 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1207 return ICE_ERR_PARAM; 1208 1209 /* Clear each dword register separately */ 1210 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1211 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1212 1213 return ICE_SUCCESS; 1214 } 1215 1216 /** 1217 * ice_copy_tx_drbell_q_ctx_to_hw 1218 * @hw: pointer to the hardware structure 1219 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1220 * @tx_drbell_q_index: the index of the doorbell queue 1221 * 1222 * Copies doorbell queue context from dense structure to HW register space 1223 */ 1224 static enum ice_status 1225 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1226 u32 tx_drbell_q_index) 1227 { 1228 u8 i; 1229 1230 if (!ice_tx_drbell_q_ctx) 1231 return ICE_ERR_BAD_PTR; 1232 1233 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1234 return ICE_ERR_PARAM; 1235 1236 /* Copy each dword separately to HW */ 1237 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1238 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1239 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1240 1241 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1242 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1243 } 1244 1245 return ICE_SUCCESS; 1246 } 1247 1248 /* LAN Tx Doorbell Queue Context info */ 1249 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1250 /* Field Width LSB */ 1251 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1252 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1253 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1254 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1255 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1256 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1257 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1258 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1259 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1260 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1261 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1262 { 0 } 1263 }; 1264 1265 /** 1266 * ice_write_tx_drbell_q_ctx 1267 * @hw: pointer to the hardware structure 1268 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1269 * @tx_drbell_q_index: the index of the doorbell queue 1270 * 1271 * Converts doorbell queue context from sparse to dense structure and then 1272 * writes it to HW register space 1273 */ 1274 enum ice_status 1275 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1276 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1277 u32 tx_drbell_q_index) 1278 { 1279 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1280 1281 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info); 1282 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1283 } 1284 1285 /** 1286 * ice_clear_tx_drbell_q_ctx 1287 * @hw: pointer to the hardware structure 1288 * @tx_drbell_q_index: the index of the doorbell queue to clear 1289 * 1290 * Clears doorbell queue context in HW register space 1291 */ 1292 enum ice_status 1293 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1294 { 1295 u8 i; 1296 1297 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1298 return ICE_ERR_PARAM; 1299 1300 /* Clear each dword register separately */ 1301 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1302 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1303 1304 return ICE_SUCCESS; 1305 } 1306 1307 /* FW Admin Queue command wrappers */ 1308 1309 /** 1310 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1311 * @hw: pointer to the HW struct 1312 * @desc: descriptor describing the command 1313 * @buf: buffer to use for indirect commands (NULL for direct commands) 1314 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1315 * @cd: pointer to command details structure 1316 * 1317 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1318 */ 1319 enum ice_status 1320 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1321 u16 buf_size, struct ice_sq_cd *cd) 1322 { 1323 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1324 } 1325 1326 /** 1327 * ice_aq_get_fw_ver 1328 * @hw: pointer to the HW struct 1329 * @cd: pointer to command details structure or NULL 1330 * 1331 * Get the firmware version (0x0001) from the admin queue commands 1332 */ 1333 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1334 { 1335 struct ice_aqc_get_ver *resp; 1336 struct ice_aq_desc desc; 1337 enum ice_status status; 1338 1339 resp = &desc.params.get_ver; 1340 1341 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1342 1343 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1344 1345 if (!status) { 1346 hw->fw_branch = resp->fw_branch; 1347 hw->fw_maj_ver = resp->fw_major; 1348 hw->fw_min_ver = resp->fw_minor; 1349 hw->fw_patch = resp->fw_patch; 1350 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1351 hw->api_branch = resp->api_branch; 1352 hw->api_maj_ver = resp->api_major; 1353 hw->api_min_ver = resp->api_minor; 1354 hw->api_patch = resp->api_patch; 1355 } 1356 1357 return status; 1358 } 1359 1360 /** 1361 * ice_aq_send_driver_ver 1362 * @hw: pointer to the HW struct 1363 * @dv: driver's major, minor version 1364 * @cd: pointer to command details structure or NULL 1365 * 1366 * Send the driver version (0x0002) to the firmware 1367 */ 1368 enum ice_status 1369 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1370 struct ice_sq_cd *cd) 1371 { 1372 struct ice_aqc_driver_ver *cmd; 1373 struct ice_aq_desc desc; 1374 u16 len; 1375 1376 cmd = &desc.params.driver_ver; 1377 1378 if (!dv) 1379 return ICE_ERR_PARAM; 1380 1381 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1382 1383 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1384 cmd->major_ver = dv->major_ver; 1385 cmd->minor_ver = dv->minor_ver; 1386 cmd->build_ver = dv->build_ver; 1387 cmd->subbuild_ver = dv->subbuild_ver; 1388 1389 len = 0; 1390 while (len < sizeof(dv->driver_string) && 1391 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1392 len++; 1393 1394 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1395 } 1396 1397 /** 1398 * ice_aq_q_shutdown 1399 * @hw: pointer to the HW struct 1400 * @unloading: is the driver unloading itself 1401 * 1402 * Tell the Firmware that we're shutting down the AdminQ and whether 1403 * or not the driver is unloading as well (0x0003). 1404 */ 1405 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1406 { 1407 struct ice_aqc_q_shutdown *cmd; 1408 struct ice_aq_desc desc; 1409 1410 cmd = &desc.params.q_shutdown; 1411 1412 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1413 1414 if (unloading) 1415 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1416 1417 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1418 } 1419 1420 /** 1421 * ice_aq_req_res 1422 * @hw: pointer to the HW struct 1423 * @res: resource ID 1424 * @access: access type 1425 * @sdp_number: resource number 1426 * @timeout: the maximum time in ms that the driver may hold the resource 1427 * @cd: pointer to command details structure or NULL 1428 * 1429 * Requests common resource using the admin queue commands (0x0008). 1430 * When attempting to acquire the Global Config Lock, the driver can 1431 * learn of three states: 1432 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1433 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1434 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1435 * successfully downloaded the package; the driver does 1436 * not have to download the package and can continue 1437 * loading 1438 * 1439 * Note that if the caller is in an acquire lock, perform action, release lock 1440 * phase of operation, it is possible that the FW may detect a timeout and issue 1441 * a CORER. In this case, the driver will receive a CORER interrupt and will 1442 * have to determine its cause. The calling thread that is handling this flow 1443 * will likely get an error propagated back to it indicating the Download 1444 * Package, Update Package or the Release Resource AQ commands timed out. 1445 */ 1446 static enum ice_status 1447 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1448 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1449 struct ice_sq_cd *cd) 1450 { 1451 struct ice_aqc_req_res *cmd_resp; 1452 struct ice_aq_desc desc; 1453 enum ice_status status; 1454 1455 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1456 1457 cmd_resp = &desc.params.res_owner; 1458 1459 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1460 1461 cmd_resp->res_id = CPU_TO_LE16(res); 1462 cmd_resp->access_type = CPU_TO_LE16(access); 1463 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1464 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1465 *timeout = 0; 1466 1467 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1468 1469 /* The completion specifies the maximum time in ms that the driver 1470 * may hold the resource in the Timeout field. 1471 */ 1472 1473 /* Global config lock response utilizes an additional status field. 1474 * 1475 * If the Global config lock resource is held by some other driver, the 1476 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1477 * and the timeout field indicates the maximum time the current owner 1478 * of the resource has to free it. 1479 */ 1480 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1481 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1482 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1483 return ICE_SUCCESS; 1484 } else if (LE16_TO_CPU(cmd_resp->status) == 1485 ICE_AQ_RES_GLBL_IN_PROG) { 1486 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1487 return ICE_ERR_AQ_ERROR; 1488 } else if (LE16_TO_CPU(cmd_resp->status) == 1489 ICE_AQ_RES_GLBL_DONE) { 1490 return ICE_ERR_AQ_NO_WORK; 1491 } 1492 1493 /* invalid FW response, force a timeout immediately */ 1494 *timeout = 0; 1495 return ICE_ERR_AQ_ERROR; 1496 } 1497 1498 /* If the resource is held by some other driver, the command completes 1499 * with a busy return value and the timeout field indicates the maximum 1500 * time the current owner of the resource has to free it. 1501 */ 1502 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1503 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1504 1505 return status; 1506 } 1507 1508 /** 1509 * ice_aq_release_res 1510 * @hw: pointer to the HW struct 1511 * @res: resource ID 1512 * @sdp_number: resource number 1513 * @cd: pointer to command details structure or NULL 1514 * 1515 * release common resource using the admin queue commands (0x0009) 1516 */ 1517 static enum ice_status 1518 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1519 struct ice_sq_cd *cd) 1520 { 1521 struct ice_aqc_req_res *cmd; 1522 struct ice_aq_desc desc; 1523 1524 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1525 1526 cmd = &desc.params.res_owner; 1527 1528 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1529 1530 cmd->res_id = CPU_TO_LE16(res); 1531 cmd->res_number = CPU_TO_LE32(sdp_number); 1532 1533 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1534 } 1535 1536 /** 1537 * ice_acquire_res 1538 * @hw: pointer to the HW structure 1539 * @res: resource ID 1540 * @access: access type (read or write) 1541 * @timeout: timeout in milliseconds 1542 * 1543 * This function will attempt to acquire the ownership of a resource. 1544 */ 1545 enum ice_status 1546 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1547 enum ice_aq_res_access_type access, u32 timeout) 1548 { 1549 #define ICE_RES_POLLING_DELAY_MS 10 1550 u32 delay = ICE_RES_POLLING_DELAY_MS; 1551 u32 time_left = timeout; 1552 enum ice_status status; 1553 1554 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1555 1556 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1557 1558 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1559 * previously acquired the resource and performed any necessary updates; 1560 * in this case the caller does not obtain the resource and has no 1561 * further work to do. 1562 */ 1563 if (status == ICE_ERR_AQ_NO_WORK) 1564 goto ice_acquire_res_exit; 1565 1566 if (status) 1567 ice_debug(hw, ICE_DBG_RES, 1568 "resource %d acquire type %d failed.\n", res, access); 1569 1570 /* If necessary, poll until the current lock owner timeouts */ 1571 timeout = time_left; 1572 while (status && timeout && time_left) { 1573 ice_msec_delay(delay, true); 1574 timeout = (timeout > delay) ? timeout - delay : 0; 1575 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1576 1577 if (status == ICE_ERR_AQ_NO_WORK) 1578 /* lock free, but no work to do */ 1579 break; 1580 1581 if (!status) 1582 /* lock acquired */ 1583 break; 1584 } 1585 if (status && status != ICE_ERR_AQ_NO_WORK) 1586 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1587 1588 ice_acquire_res_exit: 1589 if (status == ICE_ERR_AQ_NO_WORK) { 1590 if (access == ICE_RES_WRITE) 1591 ice_debug(hw, ICE_DBG_RES, 1592 "resource indicates no work to do.\n"); 1593 else 1594 ice_debug(hw, ICE_DBG_RES, 1595 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1596 } 1597 return status; 1598 } 1599 1600 /** 1601 * ice_release_res 1602 * @hw: pointer to the HW structure 1603 * @res: resource ID 1604 * 1605 * This function will release a resource using the proper Admin Command. 1606 */ 1607 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1608 { 1609 enum ice_status status; 1610 u32 total_delay = 0; 1611 1612 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1613 1614 status = ice_aq_release_res(hw, res, 0, NULL); 1615 1616 /* there are some rare cases when trying to release the resource 1617 * results in an admin queue timeout, so handle them correctly 1618 */ 1619 while ((status == ICE_ERR_AQ_TIMEOUT) && 1620 (total_delay < hw->adminq.sq_cmd_timeout)) { 1621 ice_msec_delay(1, true); 1622 status = ice_aq_release_res(hw, res, 0, NULL); 1623 total_delay++; 1624 } 1625 } 1626 1627 /** 1628 * ice_aq_alloc_free_res - command to allocate/free resources 1629 * @hw: pointer to the HW struct 1630 * @num_entries: number of resource entries in buffer 1631 * @buf: Indirect buffer to hold data parameters and response 1632 * @buf_size: size of buffer for indirect commands 1633 * @opc: pass in the command opcode 1634 * @cd: pointer to command details structure or NULL 1635 * 1636 * Helper function to allocate/free resources using the admin queue commands 1637 */ 1638 enum ice_status 1639 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1640 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1641 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1642 { 1643 struct ice_aqc_alloc_free_res_cmd *cmd; 1644 struct ice_aq_desc desc; 1645 1646 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1647 1648 cmd = &desc.params.sw_res_ctrl; 1649 1650 if (!buf) 1651 return ICE_ERR_PARAM; 1652 1653 if (buf_size < (num_entries * sizeof(buf->elem[0]))) 1654 return ICE_ERR_PARAM; 1655 1656 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1657 1658 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1659 1660 cmd->num_entries = CPU_TO_LE16(num_entries); 1661 1662 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1663 } 1664 1665 /** 1666 * ice_alloc_hw_res - allocate resource 1667 * @hw: pointer to the HW struct 1668 * @type: type of resource 1669 * @num: number of resources to allocate 1670 * @btm: allocate from bottom 1671 * @res: pointer to array that will receive the resources 1672 */ 1673 enum ice_status 1674 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1675 { 1676 struct ice_aqc_alloc_free_res_elem *buf; 1677 enum ice_status status; 1678 u16 buf_len; 1679 1680 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1); 1681 buf = (struct ice_aqc_alloc_free_res_elem *) 1682 ice_malloc(hw, buf_len); 1683 if (!buf) 1684 return ICE_ERR_NO_MEMORY; 1685 1686 /* Prepare buffer to allocate resource. */ 1687 buf->num_elems = CPU_TO_LE16(num); 1688 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1689 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1690 if (btm) 1691 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1692 1693 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1694 ice_aqc_opc_alloc_res, NULL); 1695 if (status) 1696 goto ice_alloc_res_exit; 1697 1698 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num, 1699 ICE_NONDMA_TO_NONDMA); 1700 1701 ice_alloc_res_exit: 1702 ice_free(hw, buf); 1703 return status; 1704 } 1705 1706 /** 1707 * ice_free_hw_res - free allocated HW resource 1708 * @hw: pointer to the HW struct 1709 * @type: type of resource to free 1710 * @num: number of resources 1711 * @res: pointer to array that contains the resources to free 1712 */ 1713 enum ice_status 1714 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1715 { 1716 struct ice_aqc_alloc_free_res_elem *buf; 1717 enum ice_status status; 1718 u16 buf_len; 1719 1720 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1); 1721 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1722 if (!buf) 1723 return ICE_ERR_NO_MEMORY; 1724 1725 /* Prepare buffer to free resource. */ 1726 buf->num_elems = CPU_TO_LE16(num); 1727 buf->res_type = CPU_TO_LE16(type); 1728 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num, 1729 ICE_NONDMA_TO_NONDMA); 1730 1731 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1732 ice_aqc_opc_free_res, NULL); 1733 if (status) 1734 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1735 1736 ice_free(hw, buf); 1737 return status; 1738 } 1739 1740 /** 1741 * ice_get_num_per_func - determine number of resources per PF 1742 * @hw: pointer to the HW structure 1743 * @max: value to be evenly split between each PF 1744 * 1745 * Determine the number of valid functions by going through the bitmap returned 1746 * from parsing capabilities and use this to calculate the number of resources 1747 * per PF based on the max value passed in. 1748 */ 1749 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1750 { 1751 u8 funcs; 1752 1753 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1754 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 1755 ICE_CAPS_VALID_FUNCS_M); 1756 1757 if (!funcs) 1758 return 0; 1759 1760 return max / funcs; 1761 } 1762 1763 /** 1764 * ice_parse_caps - parse function/device capabilities 1765 * @hw: pointer to the HW struct 1766 * @buf: pointer to a buffer containing function/device capability records 1767 * @cap_count: number of capability records in the list 1768 * @opc: type of capabilities list to parse 1769 * 1770 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1771 */ 1772 static void 1773 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1774 enum ice_adminq_opc opc) 1775 { 1776 struct ice_aqc_list_caps_elem *cap_resp; 1777 struct ice_hw_func_caps *func_p = NULL; 1778 struct ice_hw_dev_caps *dev_p = NULL; 1779 struct ice_hw_common_caps *caps; 1780 char const *prefix; 1781 u32 i; 1782 1783 if (!buf) 1784 return; 1785 1786 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1787 1788 if (opc == ice_aqc_opc_list_dev_caps) { 1789 dev_p = &hw->dev_caps; 1790 caps = &dev_p->common_cap; 1791 prefix = "dev cap"; 1792 } else if (opc == ice_aqc_opc_list_func_caps) { 1793 func_p = &hw->func_caps; 1794 caps = &func_p->common_cap; 1795 prefix = "func cap"; 1796 } else { 1797 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1798 return; 1799 } 1800 1801 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1802 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id); 1803 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id); 1804 u32 number = LE32_TO_CPU(cap_resp->number); 1805 u16 cap = LE16_TO_CPU(cap_resp->cap); 1806 1807 switch (cap) { 1808 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1809 caps->valid_functions = number; 1810 ice_debug(hw, ICE_DBG_INIT, 1811 "%s: valid_functions (bitmap) = %d\n", prefix, 1812 caps->valid_functions); 1813 1814 /* store func count for resource management purposes */ 1815 if (dev_p) 1816 dev_p->num_funcs = ice_hweight32(number); 1817 break; 1818 case ICE_AQC_CAPS_VSI: 1819 if (dev_p) { 1820 dev_p->num_vsi_allocd_to_host = number; 1821 ice_debug(hw, ICE_DBG_INIT, 1822 "%s: num_vsi_allocd_to_host = %d\n", 1823 prefix, 1824 dev_p->num_vsi_allocd_to_host); 1825 } else if (func_p) { 1826 func_p->guar_num_vsi = 1827 ice_get_num_per_func(hw, ICE_MAX_VSI); 1828 ice_debug(hw, ICE_DBG_INIT, 1829 "%s: guar_num_vsi (fw) = %d\n", 1830 prefix, number); 1831 ice_debug(hw, ICE_DBG_INIT, 1832 "%s: guar_num_vsi = %d\n", 1833 prefix, func_p->guar_num_vsi); 1834 } 1835 break; 1836 case ICE_AQC_CAPS_DCB: 1837 caps->dcb = (number == 1); 1838 caps->active_tc_bitmap = logical_id; 1839 caps->maxtc = phys_id; 1840 ice_debug(hw, ICE_DBG_INIT, 1841 "%s: dcb = %d\n", prefix, caps->dcb); 1842 ice_debug(hw, ICE_DBG_INIT, 1843 "%s: active_tc_bitmap = %d\n", prefix, 1844 caps->active_tc_bitmap); 1845 ice_debug(hw, ICE_DBG_INIT, 1846 "%s: maxtc = %d\n", prefix, caps->maxtc); 1847 break; 1848 case ICE_AQC_CAPS_RSS: 1849 caps->rss_table_size = number; 1850 caps->rss_table_entry_width = logical_id; 1851 ice_debug(hw, ICE_DBG_INIT, 1852 "%s: rss_table_size = %d\n", prefix, 1853 caps->rss_table_size); 1854 ice_debug(hw, ICE_DBG_INIT, 1855 "%s: rss_table_entry_width = %d\n", prefix, 1856 caps->rss_table_entry_width); 1857 break; 1858 case ICE_AQC_CAPS_RXQS: 1859 caps->num_rxq = number; 1860 caps->rxq_first_id = phys_id; 1861 ice_debug(hw, ICE_DBG_INIT, 1862 "%s: num_rxq = %d\n", prefix, 1863 caps->num_rxq); 1864 ice_debug(hw, ICE_DBG_INIT, 1865 "%s: rxq_first_id = %d\n", prefix, 1866 caps->rxq_first_id); 1867 break; 1868 case ICE_AQC_CAPS_TXQS: 1869 caps->num_txq = number; 1870 caps->txq_first_id = phys_id; 1871 ice_debug(hw, ICE_DBG_INIT, 1872 "%s: num_txq = %d\n", prefix, 1873 caps->num_txq); 1874 ice_debug(hw, ICE_DBG_INIT, 1875 "%s: txq_first_id = %d\n", prefix, 1876 caps->txq_first_id); 1877 break; 1878 case ICE_AQC_CAPS_MSIX: 1879 caps->num_msix_vectors = number; 1880 caps->msix_vector_first_id = phys_id; 1881 ice_debug(hw, ICE_DBG_INIT, 1882 "%s: num_msix_vectors = %d\n", prefix, 1883 caps->num_msix_vectors); 1884 ice_debug(hw, ICE_DBG_INIT, 1885 "%s: msix_vector_first_id = %d\n", prefix, 1886 caps->msix_vector_first_id); 1887 break; 1888 case ICE_AQC_CAPS_FD: 1889 { 1890 u32 reg_val, val; 1891 1892 if (dev_p) { 1893 dev_p->num_flow_director_fltr = number; 1894 ice_debug(hw, ICE_DBG_INIT, 1895 "%s: num_flow_director_fltr = %d\n", 1896 prefix, 1897 dev_p->num_flow_director_fltr); 1898 } 1899 if (func_p) { 1900 reg_val = rd32(hw, GLQF_FD_SIZE); 1901 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 1902 GLQF_FD_SIZE_FD_GSIZE_S; 1903 func_p->fd_fltr_guar = 1904 ice_get_num_per_func(hw, val); 1905 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 1906 GLQF_FD_SIZE_FD_BSIZE_S; 1907 func_p->fd_fltr_best_effort = val; 1908 ice_debug(hw, ICE_DBG_INIT, 1909 "%s: fd_fltr_guar = %d\n", 1910 prefix, func_p->fd_fltr_guar); 1911 ice_debug(hw, ICE_DBG_INIT, 1912 "%s: fd_fltr_best_effort = %d\n", 1913 prefix, func_p->fd_fltr_best_effort); 1914 } 1915 break; 1916 } 1917 case ICE_AQC_CAPS_MAX_MTU: 1918 caps->max_mtu = number; 1919 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1920 prefix, caps->max_mtu); 1921 break; 1922 default: 1923 ice_debug(hw, ICE_DBG_INIT, 1924 "%s: unknown capability[%d]: 0x%x\n", prefix, 1925 i, cap); 1926 break; 1927 } 1928 } 1929 1930 /* Re-calculate capabilities that are dependent on the number of 1931 * physical ports; i.e. some features are not supported or function 1932 * differently on devices with more than 4 ports. 1933 */ 1934 if (hw->dev_caps.num_funcs > 4) { 1935 /* Max 4 TCs per port */ 1936 caps->maxtc = 4; 1937 ice_debug(hw, ICE_DBG_INIT, 1938 "%s: maxtc = %d (based on #ports)\n", prefix, 1939 caps->maxtc); 1940 } 1941 } 1942 1943 /** 1944 * ice_aq_discover_caps - query function/device capabilities 1945 * @hw: pointer to the HW struct 1946 * @buf: a virtual buffer to hold the capabilities 1947 * @buf_size: Size of the virtual buffer 1948 * @cap_count: cap count needed if AQ err==ENOMEM 1949 * @opc: capabilities type to discover - pass in the command opcode 1950 * @cd: pointer to command details structure or NULL 1951 * 1952 * Get the function(0x000a)/device(0x000b) capabilities description from 1953 * the firmware. 1954 */ 1955 static enum ice_status 1956 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 1957 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1958 { 1959 struct ice_aqc_list_caps *cmd; 1960 struct ice_aq_desc desc; 1961 enum ice_status status; 1962 1963 cmd = &desc.params.get_cap; 1964 1965 if (opc != ice_aqc_opc_list_func_caps && 1966 opc != ice_aqc_opc_list_dev_caps) 1967 return ICE_ERR_PARAM; 1968 1969 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1970 1971 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1972 if (!status) 1973 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc); 1974 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM) 1975 *cap_count = LE32_TO_CPU(cmd->count); 1976 return status; 1977 } 1978 1979 /** 1980 * ice_discover_caps - get info about the HW 1981 * @hw: pointer to the hardware structure 1982 * @opc: capabilities type to discover - pass in the command opcode 1983 */ 1984 static enum ice_status 1985 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc) 1986 { 1987 enum ice_status status; 1988 u32 cap_count; 1989 u16 cbuf_len; 1990 u8 retries; 1991 1992 /* The driver doesn't know how many capabilities the device will return 1993 * so the buffer size required isn't known ahead of time. The driver 1994 * starts with cbuf_len and if this turns out to be insufficient, the 1995 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs. 1996 * The driver then allocates the buffer based on the count and retries 1997 * the operation. So it follows that the retry count is 2. 1998 */ 1999 #define ICE_GET_CAP_BUF_COUNT 40 2000 #define ICE_GET_CAP_RETRY_COUNT 2 2001 2002 cap_count = ICE_GET_CAP_BUF_COUNT; 2003 retries = ICE_GET_CAP_RETRY_COUNT; 2004 2005 do { 2006 void *cbuf; 2007 2008 cbuf_len = (u16)(cap_count * 2009 sizeof(struct ice_aqc_list_caps_elem)); 2010 cbuf = ice_malloc(hw, cbuf_len); 2011 if (!cbuf) 2012 return ICE_ERR_NO_MEMORY; 2013 2014 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count, 2015 opc, NULL); 2016 ice_free(hw, cbuf); 2017 2018 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) 2019 break; 2020 2021 /* If ENOMEM is returned, try again with bigger buffer */ 2022 } while (--retries); 2023 2024 return status; 2025 } 2026 2027 /** 2028 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2029 * @hw: pointer to the hardware structure 2030 */ 2031 void ice_set_safe_mode_caps(struct ice_hw *hw) 2032 { 2033 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2034 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2035 u32 valid_func, rxq_first_id, txq_first_id; 2036 u32 msix_vector_first_id, max_mtu; 2037 u32 num_funcs; 2038 2039 /* cache some func_caps values that should be restored after memset */ 2040 valid_func = func_caps->common_cap.valid_functions; 2041 txq_first_id = func_caps->common_cap.txq_first_id; 2042 rxq_first_id = func_caps->common_cap.rxq_first_id; 2043 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id; 2044 max_mtu = func_caps->common_cap.max_mtu; 2045 2046 /* unset func capabilities */ 2047 memset(func_caps, 0, sizeof(*func_caps)); 2048 2049 /* restore cached values */ 2050 func_caps->common_cap.valid_functions = valid_func; 2051 func_caps->common_cap.txq_first_id = txq_first_id; 2052 func_caps->common_cap.rxq_first_id = rxq_first_id; 2053 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 2054 func_caps->common_cap.max_mtu = max_mtu; 2055 2056 /* one Tx and one Rx queue in safe mode */ 2057 func_caps->common_cap.num_rxq = 1; 2058 func_caps->common_cap.num_txq = 1; 2059 2060 /* two MSIX vectors, one for traffic and one for misc causes */ 2061 func_caps->common_cap.num_msix_vectors = 2; 2062 func_caps->guar_num_vsi = 1; 2063 2064 /* cache some dev_caps values that should be restored after memset */ 2065 valid_func = dev_caps->common_cap.valid_functions; 2066 txq_first_id = dev_caps->common_cap.txq_first_id; 2067 rxq_first_id = dev_caps->common_cap.rxq_first_id; 2068 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id; 2069 max_mtu = dev_caps->common_cap.max_mtu; 2070 num_funcs = dev_caps->num_funcs; 2071 2072 /* unset dev capabilities */ 2073 memset(dev_caps, 0, sizeof(*dev_caps)); 2074 2075 /* restore cached values */ 2076 dev_caps->common_cap.valid_functions = valid_func; 2077 dev_caps->common_cap.txq_first_id = txq_first_id; 2078 dev_caps->common_cap.rxq_first_id = rxq_first_id; 2079 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 2080 dev_caps->common_cap.max_mtu = max_mtu; 2081 dev_caps->num_funcs = num_funcs; 2082 2083 /* one Tx and one Rx queue per function in safe mode */ 2084 dev_caps->common_cap.num_rxq = num_funcs; 2085 dev_caps->common_cap.num_txq = num_funcs; 2086 2087 /* two MSIX vectors per function */ 2088 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2089 } 2090 2091 /** 2092 * ice_get_caps - get info about the HW 2093 * @hw: pointer to the hardware structure 2094 */ 2095 enum ice_status ice_get_caps(struct ice_hw *hw) 2096 { 2097 enum ice_status status; 2098 2099 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps); 2100 if (!status) 2101 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps); 2102 2103 return status; 2104 } 2105 2106 /** 2107 * ice_aq_manage_mac_write - manage MAC address write command 2108 * @hw: pointer to the HW struct 2109 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2110 * @flags: flags to control write behavior 2111 * @cd: pointer to command details structure or NULL 2112 * 2113 * This function is used to write MAC address to the NVM (0x0108). 2114 */ 2115 enum ice_status 2116 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2117 struct ice_sq_cd *cd) 2118 { 2119 struct ice_aqc_manage_mac_write *cmd; 2120 struct ice_aq_desc desc; 2121 2122 cmd = &desc.params.mac_write; 2123 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2124 2125 cmd->flags = flags; 2126 2127 /* Prep values for flags, sah, sal */ 2128 cmd->sah = HTONS(*((const u16 *)mac_addr)); 2129 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2))); 2130 2131 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2132 } 2133 2134 /** 2135 * ice_aq_clear_pxe_mode 2136 * @hw: pointer to the HW struct 2137 * 2138 * Tell the firmware that the driver is taking over from PXE (0x0110). 2139 */ 2140 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2141 { 2142 struct ice_aq_desc desc; 2143 2144 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2145 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2146 2147 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2148 } 2149 2150 /** 2151 * ice_clear_pxe_mode - clear pxe operations mode 2152 * @hw: pointer to the HW struct 2153 * 2154 * Make sure all PXE mode settings are cleared, including things 2155 * like descriptor fetch/write-back mode. 2156 */ 2157 void ice_clear_pxe_mode(struct ice_hw *hw) 2158 { 2159 if (ice_check_sq_alive(hw, &hw->adminq)) 2160 ice_aq_clear_pxe_mode(hw); 2161 } 2162 2163 /** 2164 * ice_get_link_speed_based_on_phy_type - returns link speed 2165 * @phy_type_low: lower part of phy_type 2166 * @phy_type_high: higher part of phy_type 2167 * 2168 * This helper function will convert an entry in PHY type structure 2169 * [phy_type_low, phy_type_high] to its corresponding link speed. 2170 * Note: In the structure of [phy_type_low, phy_type_high], there should 2171 * be one bit set, as this function will convert one PHY type to its 2172 * speed. 2173 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2174 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2175 */ 2176 static u16 2177 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2178 { 2179 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2180 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2181 2182 switch (phy_type_low) { 2183 case ICE_PHY_TYPE_LOW_100BASE_TX: 2184 case ICE_PHY_TYPE_LOW_100M_SGMII: 2185 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2186 break; 2187 case ICE_PHY_TYPE_LOW_1000BASE_T: 2188 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2189 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2190 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2191 case ICE_PHY_TYPE_LOW_1G_SGMII: 2192 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2193 break; 2194 case ICE_PHY_TYPE_LOW_2500BASE_T: 2195 case ICE_PHY_TYPE_LOW_2500BASE_X: 2196 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2197 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2198 break; 2199 case ICE_PHY_TYPE_LOW_5GBASE_T: 2200 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2201 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2202 break; 2203 case ICE_PHY_TYPE_LOW_10GBASE_T: 2204 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2205 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2206 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2207 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2208 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2209 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2210 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2211 break; 2212 case ICE_PHY_TYPE_LOW_25GBASE_T: 2213 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2214 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2215 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2216 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2217 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2218 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2219 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2220 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2221 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2222 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2223 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2224 break; 2225 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2226 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2227 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2228 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2229 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2230 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2231 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2232 break; 2233 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2234 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2235 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2236 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2237 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2238 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2239 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2240 case ICE_PHY_TYPE_LOW_50G_AUI2: 2241 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2242 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2243 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2244 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2246 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2247 case ICE_PHY_TYPE_LOW_50G_AUI1: 2248 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2249 break; 2250 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2251 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2252 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2253 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2254 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2255 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2256 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2257 case ICE_PHY_TYPE_LOW_100G_AUI4: 2258 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2259 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2260 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2261 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2262 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2263 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2264 break; 2265 default: 2266 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2267 break; 2268 } 2269 2270 switch (phy_type_high) { 2271 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2272 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2273 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2274 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2275 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2276 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2277 break; 2278 default: 2279 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2280 break; 2281 } 2282 2283 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2284 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2285 return ICE_AQ_LINK_SPEED_UNKNOWN; 2286 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2287 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2288 return ICE_AQ_LINK_SPEED_UNKNOWN; 2289 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2290 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2291 return speed_phy_type_low; 2292 else 2293 return speed_phy_type_high; 2294 } 2295 2296 /** 2297 * ice_update_phy_type 2298 * @phy_type_low: pointer to the lower part of phy_type 2299 * @phy_type_high: pointer to the higher part of phy_type 2300 * @link_speeds_bitmap: targeted link speeds bitmap 2301 * 2302 * Note: For the link_speeds_bitmap structure, you can check it at 2303 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2304 * link_speeds_bitmap include multiple speeds. 2305 * 2306 * Each entry in this [phy_type_low, phy_type_high] structure will 2307 * present a certain link speed. This helper function will turn on bits 2308 * in [phy_type_low, phy_type_high] structure based on the value of 2309 * link_speeds_bitmap input parameter. 2310 */ 2311 void 2312 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2313 u16 link_speeds_bitmap) 2314 { 2315 u64 pt_high; 2316 u64 pt_low; 2317 int index; 2318 u16 speed; 2319 2320 /* We first check with low part of phy_type */ 2321 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2322 pt_low = BIT_ULL(index); 2323 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2324 2325 if (link_speeds_bitmap & speed) 2326 *phy_type_low |= BIT_ULL(index); 2327 } 2328 2329 /* We then check with high part of phy_type */ 2330 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2331 pt_high = BIT_ULL(index); 2332 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2333 2334 if (link_speeds_bitmap & speed) 2335 *phy_type_high |= BIT_ULL(index); 2336 } 2337 } 2338 2339 /** 2340 * ice_aq_set_phy_cfg 2341 * @hw: pointer to the HW struct 2342 * @pi: port info structure of the interested logical port 2343 * @cfg: structure with PHY configuration data to be set 2344 * @cd: pointer to command details structure or NULL 2345 * 2346 * Set the various PHY configuration parameters supported on the Port. 2347 * One or more of the Set PHY config parameters may be ignored in an MFP 2348 * mode as the PF may not have the privilege to set some of the PHY Config 2349 * parameters. This status will be indicated by the command response (0x0601). 2350 */ 2351 enum ice_status 2352 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2353 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2354 { 2355 struct ice_aq_desc desc; 2356 enum ice_status status; 2357 2358 if (!cfg) 2359 return ICE_ERR_PARAM; 2360 2361 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2362 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2363 ice_debug(hw, ICE_DBG_PHY, 2364 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2365 cfg->caps); 2366 2367 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2368 } 2369 2370 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2371 desc.params.set_phy.lport_num = pi->lport; 2372 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2373 2374 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n", 2375 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 2376 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n", 2377 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 2378 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps); 2379 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n", 2380 cfg->low_power_ctrl); 2381 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap); 2382 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value); 2383 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt); 2384 2385 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2386 2387 if (!status) 2388 pi->phy.curr_user_phy_cfg = *cfg; 2389 2390 return status; 2391 } 2392 2393 /** 2394 * ice_update_link_info - update status of the HW network link 2395 * @pi: port info structure of the interested logical port 2396 */ 2397 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2398 { 2399 struct ice_link_status *li; 2400 enum ice_status status; 2401 2402 if (!pi) 2403 return ICE_ERR_PARAM; 2404 2405 li = &pi->phy.link_info; 2406 2407 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2408 if (status) 2409 return status; 2410 2411 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2412 struct ice_aqc_get_phy_caps_data *pcaps; 2413 struct ice_hw *hw; 2414 2415 hw = pi->hw; 2416 pcaps = (struct ice_aqc_get_phy_caps_data *) 2417 ice_malloc(hw, sizeof(*pcaps)); 2418 if (!pcaps) 2419 return ICE_ERR_NO_MEMORY; 2420 2421 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2422 pcaps, NULL); 2423 if (status == ICE_SUCCESS) 2424 ice_memcpy(li->module_type, &pcaps->module_type, 2425 sizeof(li->module_type), 2426 ICE_NONDMA_TO_NONDMA); 2427 2428 ice_free(hw, pcaps); 2429 } 2430 2431 return status; 2432 } 2433 2434 /** 2435 * ice_cache_phy_user_req 2436 * @pi: port information structure 2437 * @cache_data: PHY logging data 2438 * @cache_mode: PHY logging mode 2439 * 2440 * Log the user request on (FC, FEC, SPEED) for later user. 2441 */ 2442 static void 2443 ice_cache_phy_user_req(struct ice_port_info *pi, 2444 struct ice_phy_cache_mode_data cache_data, 2445 enum ice_phy_cache_mode cache_mode) 2446 { 2447 if (!pi) 2448 return; 2449 2450 switch (cache_mode) { 2451 case ICE_FC_MODE: 2452 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2453 break; 2454 case ICE_SPEED_MODE: 2455 pi->phy.curr_user_speed_req = 2456 cache_data.data.curr_user_speed_req; 2457 break; 2458 case ICE_FEC_MODE: 2459 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2460 break; 2461 default: 2462 break; 2463 } 2464 } 2465 2466 /** 2467 * ice_caps_to_fc_mode 2468 * @caps: PHY capabilities 2469 * 2470 * Convert PHY FC capabilities to ice FC mode 2471 */ 2472 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2473 { 2474 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2475 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2476 return ICE_FC_FULL; 2477 2478 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2479 return ICE_FC_TX_PAUSE; 2480 2481 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2482 return ICE_FC_RX_PAUSE; 2483 2484 return ICE_FC_NONE; 2485 } 2486 2487 /** 2488 * ice_caps_to_fec_mode 2489 * @caps: PHY capabilities 2490 * @fec_options: Link FEC options 2491 * 2492 * Convert PHY FEC capabilities to ice FEC mode 2493 */ 2494 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2495 { 2496 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2497 return ICE_FEC_AUTO; 2498 2499 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2500 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2501 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2502 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2503 return ICE_FEC_BASER; 2504 2505 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2506 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2507 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2508 return ICE_FEC_RS; 2509 2510 return ICE_FEC_NONE; 2511 } 2512 2513 /** 2514 * ice_set_fc 2515 * @pi: port information structure 2516 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2517 * @ena_auto_link_update: enable automatic link update 2518 * 2519 * Set the requested flow control mode. 2520 */ 2521 enum ice_status 2522 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2523 { 2524 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2525 struct ice_phy_cache_mode_data cache_data; 2526 struct ice_aqc_get_phy_caps_data *pcaps; 2527 enum ice_status status; 2528 u8 pause_mask = 0x0; 2529 struct ice_hw *hw; 2530 2531 if (!pi) 2532 return ICE_ERR_PARAM; 2533 hw = pi->hw; 2534 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; 2535 2536 /* Cache user FC request */ 2537 cache_data.data.curr_user_fc_req = pi->fc.req_mode; 2538 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2539 2540 switch (pi->fc.req_mode) { 2541 case ICE_FC_FULL: 2542 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2543 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2544 break; 2545 case ICE_FC_RX_PAUSE: 2546 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2547 break; 2548 case ICE_FC_TX_PAUSE: 2549 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2550 break; 2551 default: 2552 break; 2553 } 2554 2555 pcaps = (struct ice_aqc_get_phy_caps_data *) 2556 ice_malloc(hw, sizeof(*pcaps)); 2557 if (!pcaps) 2558 return ICE_ERR_NO_MEMORY; 2559 2560 /* Get the current PHY config */ 2561 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2562 NULL); 2563 if (status) { 2564 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2565 goto out; 2566 } 2567 2568 /* clear the old pause settings */ 2569 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2570 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2571 2572 /* set the new capabilities */ 2573 cfg.caps |= pause_mask; 2574 2575 /* If the capabilities have changed, then set the new config */ 2576 if (cfg.caps != pcaps->caps) { 2577 int retry_count, retry_max = 10; 2578 2579 /* Auto restart link so settings take effect */ 2580 if (ena_auto_link_update) 2581 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2582 /* Copy over all the old settings */ 2583 cfg.phy_type_high = pcaps->phy_type_high; 2584 cfg.phy_type_low = pcaps->phy_type_low; 2585 cfg.low_power_ctrl = pcaps->low_power_ctrl; 2586 cfg.eee_cap = pcaps->eee_cap; 2587 cfg.eeer_value = pcaps->eeer_value; 2588 cfg.link_fec_opt = pcaps->link_fec_options; 2589 2590 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2591 if (status) { 2592 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2593 goto out; 2594 } 2595 2596 /* Update the link info 2597 * It sometimes takes a really long time for link to 2598 * come back from the atomic reset. Thus, we wait a 2599 * little bit. 2600 */ 2601 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2602 status = ice_update_link_info(pi); 2603 2604 if (status == ICE_SUCCESS) 2605 break; 2606 2607 ice_msec_delay(100, true); 2608 } 2609 2610 if (status) 2611 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2612 } 2613 2614 out: 2615 ice_free(hw, pcaps); 2616 return status; 2617 } 2618 2619 /** 2620 * ice_phy_caps_equals_cfg 2621 * @phy_caps: PHY capabilities 2622 * @phy_cfg: PHY configuration 2623 * 2624 * Helper function to determine if PHY capabilities matches PHY 2625 * configuration 2626 */ 2627 bool 2628 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 2629 struct ice_aqc_set_phy_cfg_data *phy_cfg) 2630 { 2631 u8 caps_mask, cfg_mask; 2632 2633 if (!phy_caps || !phy_cfg) 2634 return false; 2635 2636 /* These bits are not common between capabilities and configuration. 2637 * Do not use them to determine equality. 2638 */ 2639 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 2640 ICE_AQC_PHY_EN_MOD_QUAL); 2641 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2642 2643 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 2644 phy_caps->phy_type_high != phy_cfg->phy_type_high || 2645 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 2646 phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl || 2647 phy_caps->eee_cap != phy_cfg->eee_cap || 2648 phy_caps->eeer_value != phy_cfg->eeer_value || 2649 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 2650 return false; 2651 2652 return true; 2653 } 2654 2655 /** 2656 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2657 * @caps: PHY ability structure to copy date from 2658 * @cfg: PHY configuration structure to copy data to 2659 * 2660 * Helper function to copy AQC PHY get ability data to PHY set configuration 2661 * data structure 2662 */ 2663 void 2664 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps, 2665 struct ice_aqc_set_phy_cfg_data *cfg) 2666 { 2667 if (!caps || !cfg) 2668 return; 2669 2670 cfg->phy_type_low = caps->phy_type_low; 2671 cfg->phy_type_high = caps->phy_type_high; 2672 cfg->caps = caps->caps; 2673 cfg->low_power_ctrl = caps->low_power_ctrl; 2674 cfg->eee_cap = caps->eee_cap; 2675 cfg->eeer_value = caps->eeer_value; 2676 cfg->link_fec_opt = caps->link_fec_options; 2677 } 2678 2679 /** 2680 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 2681 * @cfg: PHY configuration data to set FEC mode 2682 * @fec: FEC mode to configure 2683 * 2684 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC 2685 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps 2686 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling. 2687 */ 2688 void 2689 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec) 2690 { 2691 switch (fec) { 2692 case ICE_FEC_BASER: 2693 /* Clear RS bits, and AND BASE-R ability 2694 * bits and OR request bits. 2695 */ 2696 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2697 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2698 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2699 ICE_AQC_PHY_FEC_25G_KR_REQ; 2700 break; 2701 case ICE_FEC_RS: 2702 /* Clear BASE-R bits, and AND RS ability 2703 * bits and OR request bits. 2704 */ 2705 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2706 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2707 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2708 break; 2709 case ICE_FEC_NONE: 2710 /* Clear all FEC option bits. */ 2711 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2712 break; 2713 case ICE_FEC_AUTO: 2714 /* AND auto FEC bit, and all caps bits. */ 2715 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 2716 break; 2717 } 2718 } 2719 2720 /** 2721 * ice_get_link_status - get status of the HW network link 2722 * @pi: port information structure 2723 * @link_up: pointer to bool (true/false = linkup/linkdown) 2724 * 2725 * Variable link_up is true if link is up, false if link is down. 2726 * The variable link_up is invalid if status is non zero. As a 2727 * result of this call, link status reporting becomes enabled 2728 */ 2729 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 2730 { 2731 struct ice_phy_info *phy_info; 2732 enum ice_status status = ICE_SUCCESS; 2733 2734 if (!pi || !link_up) 2735 return ICE_ERR_PARAM; 2736 2737 phy_info = &pi->phy; 2738 2739 if (phy_info->get_link_info) { 2740 status = ice_update_link_info(pi); 2741 2742 if (status) 2743 ice_debug(pi->hw, ICE_DBG_LINK, 2744 "get link status error, status = %d\n", 2745 status); 2746 } 2747 2748 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 2749 2750 return status; 2751 } 2752 2753 /** 2754 * ice_aq_set_link_restart_an 2755 * @pi: pointer to the port information structure 2756 * @ena_link: if true: enable link, if false: disable link 2757 * @cd: pointer to command details structure or NULL 2758 * 2759 * Sets up the link and restarts the Auto-Negotiation over the link. 2760 */ 2761 enum ice_status 2762 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 2763 struct ice_sq_cd *cd) 2764 { 2765 struct ice_aqc_restart_an *cmd; 2766 struct ice_aq_desc desc; 2767 2768 cmd = &desc.params.restart_an; 2769 2770 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 2771 2772 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 2773 cmd->lport_num = pi->lport; 2774 if (ena_link) 2775 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 2776 else 2777 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 2778 2779 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2780 } 2781 2782 /** 2783 * ice_aq_set_event_mask 2784 * @hw: pointer to the HW struct 2785 * @port_num: port number of the physical function 2786 * @mask: event mask to be set 2787 * @cd: pointer to command details structure or NULL 2788 * 2789 * Set event mask (0x0613) 2790 */ 2791 enum ice_status 2792 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 2793 struct ice_sq_cd *cd) 2794 { 2795 struct ice_aqc_set_event_mask *cmd; 2796 struct ice_aq_desc desc; 2797 2798 cmd = &desc.params.set_event_mask; 2799 2800 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 2801 2802 cmd->lport_num = port_num; 2803 2804 cmd->event_mask = CPU_TO_LE16(mask); 2805 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2806 } 2807 2808 /** 2809 * ice_aq_set_mac_loopback 2810 * @hw: pointer to the HW struct 2811 * @ena_lpbk: Enable or Disable loopback 2812 * @cd: pointer to command details structure or NULL 2813 * 2814 * Enable/disable loopback on a given port 2815 */ 2816 enum ice_status 2817 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 2818 { 2819 struct ice_aqc_set_mac_lb *cmd; 2820 struct ice_aq_desc desc; 2821 2822 cmd = &desc.params.set_mac_lb; 2823 2824 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 2825 if (ena_lpbk) 2826 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 2827 2828 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2829 } 2830 2831 /** 2832 * ice_aq_set_port_id_led 2833 * @pi: pointer to the port information 2834 * @is_orig_mode: is this LED set to original mode (by the net-list) 2835 * @cd: pointer to command details structure or NULL 2836 * 2837 * Set LED value for the given port (0x06e9) 2838 */ 2839 enum ice_status 2840 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 2841 struct ice_sq_cd *cd) 2842 { 2843 struct ice_aqc_set_port_id_led *cmd; 2844 struct ice_hw *hw = pi->hw; 2845 struct ice_aq_desc desc; 2846 2847 cmd = &desc.params.set_port_id_led; 2848 2849 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 2850 2851 if (is_orig_mode) 2852 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 2853 else 2854 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 2855 2856 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2857 } 2858 2859 /** 2860 * ice_aq_sff_eeprom 2861 * @hw: pointer to the HW struct 2862 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 2863 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 2864 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 2865 * @page: QSFP page 2866 * @set_page: set or ignore the page 2867 * @data: pointer to data buffer to be read/written to the I2C device. 2868 * @length: 1-16 for read, 1 for write. 2869 * @write: 0 read, 1 for write. 2870 * @cd: pointer to command details structure or NULL 2871 * 2872 * Read/Write SFF EEPROM (0x06EE) 2873 */ 2874 enum ice_status 2875 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 2876 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 2877 bool write, struct ice_sq_cd *cd) 2878 { 2879 struct ice_aqc_sff_eeprom *cmd; 2880 struct ice_aq_desc desc; 2881 enum ice_status status; 2882 2883 if (!data || (mem_addr & 0xff00)) 2884 return ICE_ERR_PARAM; 2885 2886 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 2887 cmd = &desc.params.read_write_sff_param; 2888 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); 2889 cmd->lport_num = (u8)(lport & 0xff); 2890 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 2891 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 2892 ICE_AQC_SFF_I2CBUS_7BIT_M) | 2893 ((set_page << 2894 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 2895 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 2896 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 2897 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 2898 if (write) 2899 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 2900 2901 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 2902 return status; 2903 } 2904 2905 /** 2906 * __ice_aq_get_set_rss_lut 2907 * @hw: pointer to the hardware structure 2908 * @vsi_id: VSI FW index 2909 * @lut_type: LUT table type 2910 * @lut: pointer to the LUT buffer provided by the caller 2911 * @lut_size: size of the LUT buffer 2912 * @glob_lut_idx: global LUT index 2913 * @set: set true to set the table, false to get the table 2914 * 2915 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 2916 */ 2917 static enum ice_status 2918 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 2919 u16 lut_size, u8 glob_lut_idx, bool set) 2920 { 2921 struct ice_aqc_get_set_rss_lut *cmd_resp; 2922 struct ice_aq_desc desc; 2923 enum ice_status status; 2924 u16 flags = 0; 2925 2926 cmd_resp = &desc.params.get_set_rss_lut; 2927 2928 if (set) { 2929 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 2930 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2931 } else { 2932 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 2933 } 2934 2935 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 2936 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 2937 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 2938 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 2939 2940 switch (lut_type) { 2941 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 2942 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 2943 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 2944 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 2945 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 2946 break; 2947 default: 2948 status = ICE_ERR_PARAM; 2949 goto ice_aq_get_set_rss_lut_exit; 2950 } 2951 2952 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 2953 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 2954 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 2955 2956 if (!set) 2957 goto ice_aq_get_set_rss_lut_send; 2958 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2959 if (!set) 2960 goto ice_aq_get_set_rss_lut_send; 2961 } else { 2962 goto ice_aq_get_set_rss_lut_send; 2963 } 2964 2965 /* LUT size is only valid for Global and PF table types */ 2966 switch (lut_size) { 2967 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 2968 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 2969 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2970 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2971 break; 2972 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 2973 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 2974 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2975 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2976 break; 2977 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 2978 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2979 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 2980 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2981 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2982 break; 2983 } 2984 /* fall-through */ 2985 default: 2986 status = ICE_ERR_PARAM; 2987 goto ice_aq_get_set_rss_lut_exit; 2988 } 2989 2990 ice_aq_get_set_rss_lut_send: 2991 cmd_resp->flags = CPU_TO_LE16(flags); 2992 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 2993 2994 ice_aq_get_set_rss_lut_exit: 2995 return status; 2996 } 2997 2998 /** 2999 * ice_aq_get_rss_lut 3000 * @hw: pointer to the hardware structure 3001 * @vsi_handle: software VSI handle 3002 * @lut_type: LUT table type 3003 * @lut: pointer to the LUT buffer provided by the caller 3004 * @lut_size: size of the LUT buffer 3005 * 3006 * get the RSS lookup table, PF or VSI type 3007 */ 3008 enum ice_status 3009 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3010 u8 *lut, u16 lut_size) 3011 { 3012 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3013 return ICE_ERR_PARAM; 3014 3015 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3016 lut_type, lut, lut_size, 0, false); 3017 } 3018 3019 /** 3020 * ice_aq_set_rss_lut 3021 * @hw: pointer to the hardware structure 3022 * @vsi_handle: software VSI handle 3023 * @lut_type: LUT table type 3024 * @lut: pointer to the LUT buffer provided by the caller 3025 * @lut_size: size of the LUT buffer 3026 * 3027 * set the RSS lookup table, PF or VSI type 3028 */ 3029 enum ice_status 3030 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3031 u8 *lut, u16 lut_size) 3032 { 3033 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3034 return ICE_ERR_PARAM; 3035 3036 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3037 lut_type, lut, lut_size, 0, true); 3038 } 3039 3040 /** 3041 * __ice_aq_get_set_rss_key 3042 * @hw: pointer to the HW struct 3043 * @vsi_id: VSI FW index 3044 * @key: pointer to key info struct 3045 * @set: set true to set the key, false to get the key 3046 * 3047 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3048 */ 3049 static enum 3050 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3051 struct ice_aqc_get_set_rss_keys *key, 3052 bool set) 3053 { 3054 struct ice_aqc_get_set_rss_key *cmd_resp; 3055 u16 key_size = sizeof(*key); 3056 struct ice_aq_desc desc; 3057 3058 cmd_resp = &desc.params.get_set_rss_key; 3059 3060 if (set) { 3061 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3062 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3063 } else { 3064 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3065 } 3066 3067 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3068 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3069 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3070 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3071 3072 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3073 } 3074 3075 /** 3076 * ice_aq_get_rss_key 3077 * @hw: pointer to the HW struct 3078 * @vsi_handle: software VSI handle 3079 * @key: pointer to key info struct 3080 * 3081 * get the RSS key per VSI 3082 */ 3083 enum ice_status 3084 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3085 struct ice_aqc_get_set_rss_keys *key) 3086 { 3087 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3088 return ICE_ERR_PARAM; 3089 3090 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3091 key, false); 3092 } 3093 3094 /** 3095 * ice_aq_set_rss_key 3096 * @hw: pointer to the HW struct 3097 * @vsi_handle: software VSI handle 3098 * @keys: pointer to key info struct 3099 * 3100 * set the RSS key per VSI 3101 */ 3102 enum ice_status 3103 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3104 struct ice_aqc_get_set_rss_keys *keys) 3105 { 3106 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3107 return ICE_ERR_PARAM; 3108 3109 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3110 keys, true); 3111 } 3112 3113 /** 3114 * ice_aq_add_lan_txq 3115 * @hw: pointer to the hardware structure 3116 * @num_qgrps: Number of added queue groups 3117 * @qg_list: list of queue groups to be added 3118 * @buf_size: size of buffer for indirect command 3119 * @cd: pointer to command details structure or NULL 3120 * 3121 * Add Tx LAN queue (0x0C30) 3122 * 3123 * NOTE: 3124 * Prior to calling add Tx LAN queue: 3125 * Initialize the following as part of the Tx queue context: 3126 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3127 * Cache profile and Packet shaper profile. 3128 * 3129 * After add Tx LAN queue AQ command is completed: 3130 * Interrupts should be associated with specific queues, 3131 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3132 * flow. 3133 */ 3134 enum ice_status 3135 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3136 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3137 struct ice_sq_cd *cd) 3138 { 3139 u16 i, sum_header_size, sum_q_size = 0; 3140 struct ice_aqc_add_tx_qgrp *list; 3141 struct ice_aqc_add_txqs *cmd; 3142 struct ice_aq_desc desc; 3143 3144 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3145 3146 cmd = &desc.params.add_txqs; 3147 3148 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3149 3150 if (!qg_list) 3151 return ICE_ERR_PARAM; 3152 3153 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3154 return ICE_ERR_PARAM; 3155 3156 sum_header_size = num_qgrps * 3157 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 3158 3159 list = qg_list; 3160 for (i = 0; i < num_qgrps; i++) { 3161 struct ice_aqc_add_txqs_perq *q = list->txqs; 3162 3163 sum_q_size += list->num_txqs * sizeof(*q); 3164 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 3165 } 3166 3167 if (buf_size != (sum_header_size + sum_q_size)) 3168 return ICE_ERR_PARAM; 3169 3170 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3171 3172 cmd->num_qgrps = num_qgrps; 3173 3174 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3175 } 3176 3177 /** 3178 * ice_aq_dis_lan_txq 3179 * @hw: pointer to the hardware structure 3180 * @num_qgrps: number of groups in the list 3181 * @qg_list: the list of groups to disable 3182 * @buf_size: the total size of the qg_list buffer in bytes 3183 * @rst_src: if called due to reset, specifies the reset source 3184 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3185 * @cd: pointer to command details structure or NULL 3186 * 3187 * Disable LAN Tx queue (0x0C31) 3188 */ 3189 static enum ice_status 3190 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3191 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3192 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3193 struct ice_sq_cd *cd) 3194 { 3195 struct ice_aqc_dis_txqs *cmd; 3196 struct ice_aq_desc desc; 3197 enum ice_status status; 3198 u16 i, sz = 0; 3199 3200 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3201 cmd = &desc.params.dis_txqs; 3202 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3203 3204 /* qg_list can be NULL only in VM/VF reset flow */ 3205 if (!qg_list && !rst_src) 3206 return ICE_ERR_PARAM; 3207 3208 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3209 return ICE_ERR_PARAM; 3210 3211 cmd->num_entries = num_qgrps; 3212 3213 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3214 ICE_AQC_Q_DIS_TIMEOUT_M); 3215 3216 switch (rst_src) { 3217 case ICE_VM_RESET: 3218 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3219 cmd->vmvf_and_timeout |= 3220 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3221 break; 3222 case ICE_NO_RESET: 3223 default: 3224 break; 3225 } 3226 3227 /* flush pipe on time out */ 3228 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3229 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3230 if (!qg_list) 3231 goto do_aq; 3232 3233 /* set RD bit to indicate that command buffer is provided by the driver 3234 * and it needs to be read by the firmware 3235 */ 3236 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3237 3238 for (i = 0; i < num_qgrps; ++i) { 3239 /* Calculate the size taken up by the queue IDs in this group */ 3240 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 3241 3242 /* Add the size of the group header */ 3243 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 3244 3245 /* If the num of queues is even, add 2 bytes of padding */ 3246 if ((qg_list[i].num_qs % 2) == 0) 3247 sz += 2; 3248 } 3249 3250 if (buf_size != sz) 3251 return ICE_ERR_PARAM; 3252 3253 do_aq: 3254 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3255 if (status) { 3256 if (!qg_list) 3257 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3258 vmvf_num, hw->adminq.sq_last_status); 3259 else 3260 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3261 LE16_TO_CPU(qg_list[0].q_id[0]), 3262 hw->adminq.sq_last_status); 3263 } 3264 return status; 3265 } 3266 3267 /** 3268 * ice_aq_move_recfg_lan_txq 3269 * @hw: pointer to the hardware structure 3270 * @num_qs: number of queues to move/reconfigure 3271 * @is_move: true if this operation involves node movement 3272 * @is_tc_change: true if this operation involves a TC change 3273 * @subseq_call: true if this operation is a subsequent call 3274 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 3275 * @timeout: timeout in units of 100 usec (valid values 0-50) 3276 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 3277 * @buf: struct containing src/dest TEID and per-queue info 3278 * @buf_size: size of buffer for indirect command 3279 * @txqs_moved: out param, number of queues successfully moved 3280 * @cd: pointer to command details structure or NULL 3281 * 3282 * Move / Reconfigure Tx LAN queues (0x0C32) 3283 */ 3284 enum ice_status 3285 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 3286 bool is_tc_change, bool subseq_call, bool flush_pipe, 3287 u8 timeout, u32 *blocked_cgds, 3288 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 3289 u8 *txqs_moved, struct ice_sq_cd *cd) 3290 { 3291 struct ice_aqc_move_txqs *cmd; 3292 struct ice_aq_desc desc; 3293 enum ice_status status; 3294 3295 cmd = &desc.params.move_txqs; 3296 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 3297 3298 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 3299 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 3300 return ICE_ERR_PARAM; 3301 3302 if (is_tc_change && !flush_pipe && !blocked_cgds) 3303 return ICE_ERR_PARAM; 3304 3305 if (!is_move && !is_tc_change) 3306 return ICE_ERR_PARAM; 3307 3308 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3309 3310 if (is_move) 3311 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 3312 3313 if (is_tc_change) 3314 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 3315 3316 if (subseq_call) 3317 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 3318 3319 if (flush_pipe) 3320 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 3321 3322 cmd->num_qs = num_qs; 3323 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 3324 ICE_AQC_Q_CMD_TIMEOUT_M); 3325 3326 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3327 3328 if (!status && txqs_moved) 3329 *txqs_moved = cmd->num_qs; 3330 3331 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 3332 is_tc_change && !flush_pipe) 3333 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 3334 3335 return status; 3336 } 3337 3338 /* End of FW Admin Queue command wrappers */ 3339 3340 /** 3341 * ice_write_byte - write a byte to a packed context structure 3342 * @src_ctx: the context structure to read from 3343 * @dest_ctx: the context to be written to 3344 * @ce_info: a description of the struct to be filled 3345 */ 3346 static void 3347 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3348 { 3349 u8 src_byte, dest_byte, mask; 3350 u8 *from, *dest; 3351 u16 shift_width; 3352 3353 /* copy from the next struct field */ 3354 from = src_ctx + ce_info->offset; 3355 3356 /* prepare the bits and mask */ 3357 shift_width = ce_info->lsb % 8; 3358 mask = (u8)(BIT(ce_info->width) - 1); 3359 3360 src_byte = *from; 3361 src_byte &= mask; 3362 3363 /* shift to correct alignment */ 3364 mask <<= shift_width; 3365 src_byte <<= shift_width; 3366 3367 /* get the current bits from the target bit string */ 3368 dest = dest_ctx + (ce_info->lsb / 8); 3369 3370 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3371 3372 dest_byte &= ~mask; /* get the bits not changing */ 3373 dest_byte |= src_byte; /* add in the new bits */ 3374 3375 /* put it all back */ 3376 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3377 } 3378 3379 /** 3380 * ice_write_word - write a word to a packed context structure 3381 * @src_ctx: the context structure to read from 3382 * @dest_ctx: the context to be written to 3383 * @ce_info: a description of the struct to be filled 3384 */ 3385 static void 3386 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3387 { 3388 u16 src_word, mask; 3389 __le16 dest_word; 3390 u8 *from, *dest; 3391 u16 shift_width; 3392 3393 /* copy from the next struct field */ 3394 from = src_ctx + ce_info->offset; 3395 3396 /* prepare the bits and mask */ 3397 shift_width = ce_info->lsb % 8; 3398 mask = BIT(ce_info->width) - 1; 3399 3400 /* don't swizzle the bits until after the mask because the mask bits 3401 * will be in a different bit position on big endian machines 3402 */ 3403 src_word = *(u16 *)from; 3404 src_word &= mask; 3405 3406 /* shift to correct alignment */ 3407 mask <<= shift_width; 3408 src_word <<= shift_width; 3409 3410 /* get the current bits from the target bit string */ 3411 dest = dest_ctx + (ce_info->lsb / 8); 3412 3413 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 3414 3415 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 3416 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 3417 3418 /* put it all back */ 3419 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3420 } 3421 3422 /** 3423 * ice_write_dword - write a dword to a packed context structure 3424 * @src_ctx: the context structure to read from 3425 * @dest_ctx: the context to be written to 3426 * @ce_info: a description of the struct to be filled 3427 */ 3428 static void 3429 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3430 { 3431 u32 src_dword, mask; 3432 __le32 dest_dword; 3433 u8 *from, *dest; 3434 u16 shift_width; 3435 3436 /* copy from the next struct field */ 3437 from = src_ctx + ce_info->offset; 3438 3439 /* prepare the bits and mask */ 3440 shift_width = ce_info->lsb % 8; 3441 3442 /* if the field width is exactly 32 on an x86 machine, then the shift 3443 * operation will not work because the SHL instructions count is masked 3444 * to 5 bits so the shift will do nothing 3445 */ 3446 if (ce_info->width < 32) 3447 mask = BIT(ce_info->width) - 1; 3448 else 3449 mask = (u32)~0; 3450 3451 /* don't swizzle the bits until after the mask because the mask bits 3452 * will be in a different bit position on big endian machines 3453 */ 3454 src_dword = *(u32 *)from; 3455 src_dword &= mask; 3456 3457 /* shift to correct alignment */ 3458 mask <<= shift_width; 3459 src_dword <<= shift_width; 3460 3461 /* get the current bits from the target bit string */ 3462 dest = dest_ctx + (ce_info->lsb / 8); 3463 3464 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 3465 3466 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 3467 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 3468 3469 /* put it all back */ 3470 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3471 } 3472 3473 /** 3474 * ice_write_qword - write a qword to a packed context structure 3475 * @src_ctx: the context structure to read from 3476 * @dest_ctx: the context to be written to 3477 * @ce_info: a description of the struct to be filled 3478 */ 3479 static void 3480 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3481 { 3482 u64 src_qword, mask; 3483 __le64 dest_qword; 3484 u8 *from, *dest; 3485 u16 shift_width; 3486 3487 /* copy from the next struct field */ 3488 from = src_ctx + ce_info->offset; 3489 3490 /* prepare the bits and mask */ 3491 shift_width = ce_info->lsb % 8; 3492 3493 /* if the field width is exactly 64 on an x86 machine, then the shift 3494 * operation will not work because the SHL instructions count is masked 3495 * to 6 bits so the shift will do nothing 3496 */ 3497 if (ce_info->width < 64) 3498 mask = BIT_ULL(ce_info->width) - 1; 3499 else 3500 mask = (u64)~0; 3501 3502 /* don't swizzle the bits until after the mask because the mask bits 3503 * will be in a different bit position on big endian machines 3504 */ 3505 src_qword = *(u64 *)from; 3506 src_qword &= mask; 3507 3508 /* shift to correct alignment */ 3509 mask <<= shift_width; 3510 src_qword <<= shift_width; 3511 3512 /* get the current bits from the target bit string */ 3513 dest = dest_ctx + (ce_info->lsb / 8); 3514 3515 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 3516 3517 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 3518 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 3519 3520 /* put it all back */ 3521 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3522 } 3523 3524 /** 3525 * ice_set_ctx - set context bits in packed structure 3526 * @src_ctx: pointer to a generic non-packed context structure 3527 * @dest_ctx: pointer to memory for the packed structure 3528 * @ce_info: a description of the structure to be transformed 3529 */ 3530 enum ice_status 3531 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3532 { 3533 int f; 3534 3535 for (f = 0; ce_info[f].width; f++) { 3536 /* We have to deal with each element of the FW response 3537 * using the correct size so that we are correct regardless 3538 * of the endianness of the machine. 3539 */ 3540 switch (ce_info[f].size_of) { 3541 case sizeof(u8): 3542 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3543 break; 3544 case sizeof(u16): 3545 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3546 break; 3547 case sizeof(u32): 3548 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3549 break; 3550 case sizeof(u64): 3551 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3552 break; 3553 default: 3554 return ICE_ERR_INVAL_SIZE; 3555 } 3556 } 3557 3558 return ICE_SUCCESS; 3559 } 3560 3561 /** 3562 * ice_read_byte - read context byte into struct 3563 * @src_ctx: the context structure to read from 3564 * @dest_ctx: the context to be written to 3565 * @ce_info: a description of the struct to be filled 3566 */ 3567 static void 3568 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3569 { 3570 u8 dest_byte, mask; 3571 u8 *src, *target; 3572 u16 shift_width; 3573 3574 /* prepare the bits and mask */ 3575 shift_width = ce_info->lsb % 8; 3576 mask = (u8)(BIT(ce_info->width) - 1); 3577 3578 /* shift to correct alignment */ 3579 mask <<= shift_width; 3580 3581 /* get the current bits from the src bit string */ 3582 src = src_ctx + (ce_info->lsb / 8); 3583 3584 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3585 3586 dest_byte &= ~(mask); 3587 3588 dest_byte >>= shift_width; 3589 3590 /* get the address from the struct field */ 3591 target = dest_ctx + ce_info->offset; 3592 3593 /* put it back in the struct */ 3594 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3595 } 3596 3597 /** 3598 * ice_read_word - read context word into struct 3599 * @src_ctx: the context structure to read from 3600 * @dest_ctx: the context to be written to 3601 * @ce_info: a description of the struct to be filled 3602 */ 3603 static void 3604 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3605 { 3606 u16 dest_word, mask; 3607 u8 *src, *target; 3608 __le16 src_word; 3609 u16 shift_width; 3610 3611 /* prepare the bits and mask */ 3612 shift_width = ce_info->lsb % 8; 3613 mask = BIT(ce_info->width) - 1; 3614 3615 /* shift to correct alignment */ 3616 mask <<= shift_width; 3617 3618 /* get the current bits from the src bit string */ 3619 src = src_ctx + (ce_info->lsb / 8); 3620 3621 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 3622 3623 /* the data in the memory is stored as little endian so mask it 3624 * correctly 3625 */ 3626 src_word &= ~(CPU_TO_LE16(mask)); 3627 3628 /* get the data back into host order before shifting */ 3629 dest_word = LE16_TO_CPU(src_word); 3630 3631 dest_word >>= shift_width; 3632 3633 /* get the address from the struct field */ 3634 target = dest_ctx + ce_info->offset; 3635 3636 /* put it back in the struct */ 3637 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3638 } 3639 3640 /** 3641 * ice_read_dword - read context dword into struct 3642 * @src_ctx: the context structure to read from 3643 * @dest_ctx: the context to be written to 3644 * @ce_info: a description of the struct to be filled 3645 */ 3646 static void 3647 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3648 { 3649 u32 dest_dword, mask; 3650 __le32 src_dword; 3651 u8 *src, *target; 3652 u16 shift_width; 3653 3654 /* prepare the bits and mask */ 3655 shift_width = ce_info->lsb % 8; 3656 3657 /* if the field width is exactly 32 on an x86 machine, then the shift 3658 * operation will not work because the SHL instructions count is masked 3659 * to 5 bits so the shift will do nothing 3660 */ 3661 if (ce_info->width < 32) 3662 mask = BIT(ce_info->width) - 1; 3663 else 3664 mask = (u32)~0; 3665 3666 /* shift to correct alignment */ 3667 mask <<= shift_width; 3668 3669 /* get the current bits from the src bit string */ 3670 src = src_ctx + (ce_info->lsb / 8); 3671 3672 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 3673 3674 /* the data in the memory is stored as little endian so mask it 3675 * correctly 3676 */ 3677 src_dword &= ~(CPU_TO_LE32(mask)); 3678 3679 /* get the data back into host order before shifting */ 3680 dest_dword = LE32_TO_CPU(src_dword); 3681 3682 dest_dword >>= shift_width; 3683 3684 /* get the address from the struct field */ 3685 target = dest_ctx + ce_info->offset; 3686 3687 /* put it back in the struct */ 3688 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3689 } 3690 3691 /** 3692 * ice_read_qword - read context qword into struct 3693 * @src_ctx: the context structure to read from 3694 * @dest_ctx: the context to be written to 3695 * @ce_info: a description of the struct to be filled 3696 */ 3697 static void 3698 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3699 { 3700 u64 dest_qword, mask; 3701 __le64 src_qword; 3702 u8 *src, *target; 3703 u16 shift_width; 3704 3705 /* prepare the bits and mask */ 3706 shift_width = ce_info->lsb % 8; 3707 3708 /* if the field width is exactly 64 on an x86 machine, then the shift 3709 * operation will not work because the SHL instructions count is masked 3710 * to 6 bits so the shift will do nothing 3711 */ 3712 if (ce_info->width < 64) 3713 mask = BIT_ULL(ce_info->width) - 1; 3714 else 3715 mask = (u64)~0; 3716 3717 /* shift to correct alignment */ 3718 mask <<= shift_width; 3719 3720 /* get the current bits from the src bit string */ 3721 src = src_ctx + (ce_info->lsb / 8); 3722 3723 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 3724 3725 /* the data in the memory is stored as little endian so mask it 3726 * correctly 3727 */ 3728 src_qword &= ~(CPU_TO_LE64(mask)); 3729 3730 /* get the data back into host order before shifting */ 3731 dest_qword = LE64_TO_CPU(src_qword); 3732 3733 dest_qword >>= shift_width; 3734 3735 /* get the address from the struct field */ 3736 target = dest_ctx + ce_info->offset; 3737 3738 /* put it back in the struct */ 3739 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3740 } 3741 3742 /** 3743 * ice_get_ctx - extract context bits from a packed structure 3744 * @src_ctx: pointer to a generic packed context structure 3745 * @dest_ctx: pointer to a generic non-packed context structure 3746 * @ce_info: a description of the structure to be read from 3747 */ 3748 enum ice_status 3749 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 3750 { 3751 int f; 3752 3753 for (f = 0; ce_info[f].width; f++) { 3754 switch (ce_info[f].size_of) { 3755 case 1: 3756 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 3757 break; 3758 case 2: 3759 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 3760 break; 3761 case 4: 3762 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 3763 break; 3764 case 8: 3765 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 3766 break; 3767 default: 3768 /* nothing to do, just keep going */ 3769 break; 3770 } 3771 } 3772 3773 return ICE_SUCCESS; 3774 } 3775 3776 /** 3777 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3778 * @hw: pointer to the HW struct 3779 * @vsi_handle: software VSI handle 3780 * @tc: TC number 3781 * @q_handle: software queue handle 3782 */ 3783 struct ice_q_ctx * 3784 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3785 { 3786 struct ice_vsi_ctx *vsi; 3787 struct ice_q_ctx *q_ctx; 3788 3789 vsi = ice_get_vsi_ctx(hw, vsi_handle); 3790 if (!vsi) 3791 return NULL; 3792 if (q_handle >= vsi->num_lan_q_entries[tc]) 3793 return NULL; 3794 if (!vsi->lan_q_ctx[tc]) 3795 return NULL; 3796 q_ctx = vsi->lan_q_ctx[tc]; 3797 return &q_ctx[q_handle]; 3798 } 3799 3800 /** 3801 * ice_ena_vsi_txq 3802 * @pi: port information structure 3803 * @vsi_handle: software VSI handle 3804 * @tc: TC number 3805 * @q_handle: software queue handle 3806 * @num_qgrps: Number of added queue groups 3807 * @buf: list of queue groups to be added 3808 * @buf_size: size of buffer for indirect command 3809 * @cd: pointer to command details structure or NULL 3810 * 3811 * This function adds one LAN queue 3812 */ 3813 enum ice_status 3814 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3815 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3816 struct ice_sq_cd *cd) 3817 { 3818 struct ice_aqc_txsched_elem_data node = { 0 }; 3819 struct ice_sched_node *parent; 3820 struct ice_q_ctx *q_ctx; 3821 enum ice_status status; 3822 struct ice_hw *hw; 3823 3824 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3825 return ICE_ERR_CFG; 3826 3827 if (num_qgrps > 1 || buf->num_txqs > 1) 3828 return ICE_ERR_MAX_LIMIT; 3829 3830 hw = pi->hw; 3831 3832 if (!ice_is_vsi_valid(hw, vsi_handle)) 3833 return ICE_ERR_PARAM; 3834 3835 ice_acquire_lock(&pi->sched_lock); 3836 3837 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3838 if (!q_ctx) { 3839 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3840 q_handle); 3841 status = ICE_ERR_PARAM; 3842 goto ena_txq_exit; 3843 } 3844 3845 /* find a parent node */ 3846 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3847 ICE_SCHED_NODE_OWNER_LAN); 3848 if (!parent) { 3849 status = ICE_ERR_PARAM; 3850 goto ena_txq_exit; 3851 } 3852 3853 buf->parent_teid = parent->info.node_teid; 3854 node.parent_teid = parent->info.node_teid; 3855 /* Mark that the values in the "generic" section as valid. The default 3856 * value in the "generic" section is zero. This means that : 3857 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3858 * - 0 priority among siblings, indicated by Bit 1-3. 3859 * - WFQ, indicated by Bit 4. 3860 * - 0 Adjustment value is used in PSM credit update flow, indicated by 3861 * Bit 5-6. 3862 * - Bit 7 is reserved. 3863 * Without setting the generic section as valid in valid_sections, the 3864 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3865 */ 3866 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 3867 3868 /* add the LAN queue */ 3869 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 3870 if (status != ICE_SUCCESS) { 3871 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 3872 LE16_TO_CPU(buf->txqs[0].txq_id), 3873 hw->adminq.sq_last_status); 3874 goto ena_txq_exit; 3875 } 3876 3877 node.node_teid = buf->txqs[0].q_teid; 3878 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3879 q_ctx->q_handle = q_handle; 3880 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 3881 3882 /* add a leaf node into scheduler tree queue layer */ 3883 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 3884 if (!status) 3885 status = ice_sched_replay_q_bw(pi, q_ctx); 3886 3887 ena_txq_exit: 3888 ice_release_lock(&pi->sched_lock); 3889 return status; 3890 } 3891 3892 /** 3893 * ice_dis_vsi_txq 3894 * @pi: port information structure 3895 * @vsi_handle: software VSI handle 3896 * @tc: TC number 3897 * @num_queues: number of queues 3898 * @q_handles: pointer to software queue handle array 3899 * @q_ids: pointer to the q_id array 3900 * @q_teids: pointer to queue node teids 3901 * @rst_src: if called due to reset, specifies the reset source 3902 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3903 * @cd: pointer to command details structure or NULL 3904 * 3905 * This function removes queues and their corresponding nodes in SW DB 3906 */ 3907 enum ice_status 3908 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3909 u16 *q_handles, u16 *q_ids, u32 *q_teids, 3910 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3911 struct ice_sq_cd *cd) 3912 { 3913 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 3914 struct ice_aqc_dis_txq_item qg_list; 3915 struct ice_q_ctx *q_ctx; 3916 u16 i; 3917 3918 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3919 return ICE_ERR_CFG; 3920 3921 if (!num_queues) { 3922 /* if queue is disabled already yet the disable queue command 3923 * has to be sent to complete the VF reset, then call 3924 * ice_aq_dis_lan_txq without any queue information 3925 */ 3926 if (rst_src) 3927 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, 3928 vmvf_num, NULL); 3929 return ICE_ERR_CFG; 3930 } 3931 3932 ice_acquire_lock(&pi->sched_lock); 3933 3934 for (i = 0; i < num_queues; i++) { 3935 struct ice_sched_node *node; 3936 3937 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3938 if (!node) 3939 continue; 3940 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]); 3941 if (!q_ctx) { 3942 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 3943 q_handles[i]); 3944 continue; 3945 } 3946 if (q_ctx->q_handle != q_handles[i]) { 3947 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 3948 q_ctx->q_handle, q_handles[i]); 3949 continue; 3950 } 3951 qg_list.parent_teid = node->info.parent_teid; 3952 qg_list.num_qs = 1; 3953 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]); 3954 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 3955 sizeof(qg_list), rst_src, vmvf_num, 3956 cd); 3957 3958 if (status != ICE_SUCCESS) 3959 break; 3960 ice_free_sched_node(pi, node); 3961 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 3962 } 3963 ice_release_lock(&pi->sched_lock); 3964 return status; 3965 } 3966 3967 /** 3968 * ice_cfg_vsi_qs - configure the new/existing VSI queues 3969 * @pi: port information structure 3970 * @vsi_handle: software VSI handle 3971 * @tc_bitmap: TC bitmap 3972 * @maxqs: max queues array per TC 3973 * @owner: LAN or RDMA 3974 * 3975 * This function adds/updates the VSI queues per TC. 3976 */ 3977 static enum ice_status 3978 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 3979 u16 *maxqs, u8 owner) 3980 { 3981 enum ice_status status = ICE_SUCCESS; 3982 u8 i; 3983 3984 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3985 return ICE_ERR_CFG; 3986 3987 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3988 return ICE_ERR_PARAM; 3989 3990 ice_acquire_lock(&pi->sched_lock); 3991 3992 ice_for_each_traffic_class(i) { 3993 /* configuration is possible only if TC node is present */ 3994 if (!ice_sched_get_tc_node(pi, i)) 3995 continue; 3996 3997 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 3998 ice_is_tc_ena(tc_bitmap, i)); 3999 if (status) 4000 break; 4001 } 4002 4003 ice_release_lock(&pi->sched_lock); 4004 return status; 4005 } 4006 4007 /** 4008 * ice_cfg_vsi_lan - configure VSI LAN queues 4009 * @pi: port information structure 4010 * @vsi_handle: software VSI handle 4011 * @tc_bitmap: TC bitmap 4012 * @max_lanqs: max LAN queues array per TC 4013 * 4014 * This function adds/updates the VSI LAN queues per TC. 4015 */ 4016 enum ice_status 4017 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4018 u16 *max_lanqs) 4019 { 4020 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4021 ICE_SCHED_NODE_OWNER_LAN); 4022 } 4023 4024 /** 4025 * ice_replay_pre_init - replay pre initialization 4026 * @hw: pointer to the HW struct 4027 * 4028 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4029 */ 4030 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 4031 { 4032 struct ice_switch_info *sw = hw->switch_info; 4033 u8 i; 4034 4035 /* Delete old entries from replay filter list head if there is any */ 4036 ice_rm_all_sw_replay_rule_info(hw); 4037 /* In start of replay, move entries into replay_rules list, it 4038 * will allow adding rules entries back to filt_rules list, 4039 * which is operational list. 4040 */ 4041 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4042 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 4043 &sw->recp_list[i].filt_replay_rules); 4044 ice_sched_replay_agg_vsi_preinit(hw); 4045 4046 return ice_sched_replay_tc_node_bw(hw->port_info); 4047 } 4048 4049 /** 4050 * ice_replay_vsi - replay VSI configuration 4051 * @hw: pointer to the HW struct 4052 * @vsi_handle: driver VSI handle 4053 * 4054 * Restore all VSI configuration after reset. It is required to call this 4055 * function with main VSI first. 4056 */ 4057 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4058 { 4059 enum ice_status status; 4060 4061 if (!ice_is_vsi_valid(hw, vsi_handle)) 4062 return ICE_ERR_PARAM; 4063 4064 /* Replay pre-initialization if there is any */ 4065 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4066 status = ice_replay_pre_init(hw); 4067 if (status) 4068 return status; 4069 } 4070 /* Replay per VSI all RSS configurations */ 4071 status = ice_replay_rss_cfg(hw, vsi_handle); 4072 if (status) 4073 return status; 4074 /* Replay per VSI all filters */ 4075 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4076 if (!status) 4077 status = ice_replay_vsi_agg(hw, vsi_handle); 4078 return status; 4079 } 4080 4081 /** 4082 * ice_replay_post - post replay configuration cleanup 4083 * @hw: pointer to the HW struct 4084 * 4085 * Post replay cleanup. 4086 */ 4087 void ice_replay_post(struct ice_hw *hw) 4088 { 4089 /* Delete old entries from replay filter list head */ 4090 ice_rm_all_sw_replay_rule_info(hw); 4091 ice_sched_replay_agg(hw); 4092 } 4093 4094 /** 4095 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4096 * @hw: ptr to the hardware info 4097 * @reg: offset of 64 bit HW register to read from 4098 * @prev_stat_loaded: bool to specify if previous stats are loaded 4099 * @prev_stat: ptr to previous loaded stat value 4100 * @cur_stat: ptr to current stat value 4101 */ 4102 void 4103 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4104 u64 *prev_stat, u64 *cur_stat) 4105 { 4106 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4107 4108 /* device stats are not reset at PFR, they likely will not be zeroed 4109 * when the driver starts. Thus, save the value from the first read 4110 * without adding to the statistic value so that we report stats which 4111 * count up from zero. 4112 */ 4113 if (!prev_stat_loaded) { 4114 *prev_stat = new_data; 4115 return; 4116 } 4117 4118 /* Calculate the difference between the new and old values, and then 4119 * add it to the software stat value. 4120 */ 4121 if (new_data >= *prev_stat) 4122 *cur_stat += new_data - *prev_stat; 4123 else 4124 /* to manage the potential roll-over */ 4125 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4126 4127 /* Update the previously stored value to prepare for next read */ 4128 *prev_stat = new_data; 4129 } 4130 4131 /** 4132 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4133 * @hw: ptr to the hardware info 4134 * @reg: offset of HW register to read from 4135 * @prev_stat_loaded: bool to specify if previous stats are loaded 4136 * @prev_stat: ptr to previous loaded stat value 4137 * @cur_stat: ptr to current stat value 4138 */ 4139 void 4140 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4141 u64 *prev_stat, u64 *cur_stat) 4142 { 4143 u32 new_data; 4144 4145 new_data = rd32(hw, reg); 4146 4147 /* device stats are not reset at PFR, they likely will not be zeroed 4148 * when the driver starts. Thus, save the value from the first read 4149 * without adding to the statistic value so that we report stats which 4150 * count up from zero. 4151 */ 4152 if (!prev_stat_loaded) { 4153 *prev_stat = new_data; 4154 return; 4155 } 4156 4157 /* Calculate the difference between the new and old values, and then 4158 * add it to the software stat value. 4159 */ 4160 if (new_data >= *prev_stat) 4161 *cur_stat += new_data - *prev_stat; 4162 else 4163 /* to manage the potential roll-over */ 4164 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4165 4166 /* Update the previously stored value to prepare for next read */ 4167 *prev_stat = new_data; 4168 } 4169 4170 /** 4171 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 4172 * @hw: ptr to the hardware info 4173 * @vsi_handle: VSI handle 4174 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 4175 * @cur_stats: ptr to current stats structure 4176 * 4177 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 4178 * thus cannot be read using the normal ice_stat_update32 function. 4179 * 4180 * Read the GLV_REPC register associated with the given VSI, and update the 4181 * rx_no_desc and rx_error values in the ice_eth_stats structure. 4182 * 4183 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 4184 * cleared each time it's read. 4185 * 4186 * Note that the GLV_RDPC register also counts the causes that would trigger 4187 * GLV_REPC. However, it does not give the finer grained detail about why the 4188 * packets are being dropped. The GLV_REPC values can be used to distinguish 4189 * whether Rx packets are dropped due to errors or due to no available 4190 * descriptors. 4191 */ 4192 void 4193 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 4194 struct ice_eth_stats *cur_stats) 4195 { 4196 u16 vsi_num, no_desc, error_cnt; 4197 u32 repc; 4198 4199 if (!ice_is_vsi_valid(hw, vsi_handle)) 4200 return; 4201 4202 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 4203 4204 /* If we haven't loaded stats yet, just clear the current value */ 4205 if (!prev_stat_loaded) { 4206 wr32(hw, GLV_REPC(vsi_num), 0); 4207 return; 4208 } 4209 4210 repc = rd32(hw, GLV_REPC(vsi_num)); 4211 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 4212 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 4213 4214 /* Clear the count by writing to the stats register */ 4215 wr32(hw, GLV_REPC(vsi_num), 0); 4216 4217 cur_stats->rx_no_desc += no_desc; 4218 cur_stats->rx_errors += error_cnt; 4219 } 4220 4221 /** 4222 * ice_sched_query_elem - query element information from HW 4223 * @hw: pointer to the HW struct 4224 * @node_teid: node TEID to be queried 4225 * @buf: buffer to element information 4226 * 4227 * This function queries HW element information 4228 */ 4229 enum ice_status 4230 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4231 struct ice_aqc_get_elem *buf) 4232 { 4233 u16 buf_size, num_elem_ret = 0; 4234 enum ice_status status; 4235 4236 buf_size = sizeof(*buf); 4237 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 4238 buf->generic[0].node_teid = CPU_TO_LE32(node_teid); 4239 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4240 NULL); 4241 if (status != ICE_SUCCESS || num_elem_ret != 1) 4242 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4243 return status; 4244 } 4245 4246 /** 4247 * ice_get_fw_mode - returns FW mode 4248 * @hw: pointer to the HW struct 4249 */ 4250 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 4251 { 4252 #define ICE_FW_MODE_DBG_M BIT(0) 4253 #define ICE_FW_MODE_REC_M BIT(1) 4254 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 4255 u32 fw_mode; 4256 4257 /* check the current FW mode */ 4258 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 4259 4260 if (fw_mode & ICE_FW_MODE_DBG_M) 4261 return ICE_FW_MODE_DBG; 4262 else if (fw_mode & ICE_FW_MODE_REC_M) 4263 return ICE_FW_MODE_REC; 4264 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 4265 return ICE_FW_MODE_ROLLBACK; 4266 else 4267 return ICE_FW_MODE_NORMAL; 4268 } 4269