1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #include "ice_common.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 9 #include "ice_flow.h" 10 #include "ice_switch.h" 11 12 #define ICE_PF_RESET_WAIT_COUNT 300 13 14 /** 15 * ice_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the MAC type of the adapter based on the 19 * vendor ID and device ID stored in the HW structure. 20 */ 21 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 22 { 23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 24 25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 26 return ICE_ERR_DEVICE_NOT_SUPPORTED; 27 28 switch (hw->device_id) { 29 case ICE_DEV_ID_E810C_BACKPLANE: 30 case ICE_DEV_ID_E810C_QSFP: 31 case ICE_DEV_ID_E810C_SFP: 32 case ICE_DEV_ID_E810_XXV_BACKPLANE: 33 case ICE_DEV_ID_E810_XXV_QSFP: 34 case ICE_DEV_ID_E810_XXV_SFP: 35 hw->mac_type = ICE_MAC_E810; 36 break; 37 case ICE_DEV_ID_E822C_10G_BASE_T: 38 case ICE_DEV_ID_E822C_BACKPLANE: 39 case ICE_DEV_ID_E822C_QSFP: 40 case ICE_DEV_ID_E822C_SFP: 41 case ICE_DEV_ID_E822C_SGMII: 42 case ICE_DEV_ID_E822L_10G_BASE_T: 43 case ICE_DEV_ID_E822L_BACKPLANE: 44 case ICE_DEV_ID_E822L_SFP: 45 case ICE_DEV_ID_E822L_SGMII: 46 case ICE_DEV_ID_E823L_10G_BASE_T: 47 case ICE_DEV_ID_E823L_1GBE: 48 case ICE_DEV_ID_E823L_BACKPLANE: 49 case ICE_DEV_ID_E823L_QSFP: 50 case ICE_DEV_ID_E823L_SFP: 51 hw->mac_type = ICE_MAC_GENERIC; 52 break; 53 default: 54 hw->mac_type = ICE_MAC_UNKNOWN; 55 break; 56 } 57 58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 59 return ICE_SUCCESS; 60 } 61 62 /** 63 * ice_clear_pf_cfg - Clear PF configuration 64 * @hw: pointer to the hardware structure 65 * 66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 67 * configuration, flow director filters, etc.). 68 */ 69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 70 { 71 struct ice_aq_desc desc; 72 73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 74 75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 76 } 77 78 /** 79 * ice_aq_manage_mac_read - manage MAC address read command 80 * @hw: pointer to the HW struct 81 * @buf: a virtual buffer to hold the manage MAC read response 82 * @buf_size: Size of the virtual buffer 83 * @cd: pointer to command details structure or NULL 84 * 85 * This function is used to return per PF station MAC address (0x0107). 86 * NOTE: Upon successful completion of this command, MAC address information 87 * is returned in user specified buffer. Please interpret user specified 88 * buffer as "manage_mac_read" response. 89 * Response such as various MAC addresses are stored in HW struct (port.mac) 90 * ice_discover_dev_caps is expected to be called before this function is 91 * called. 92 */ 93 static enum ice_status 94 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 95 struct ice_sq_cd *cd) 96 { 97 struct ice_aqc_manage_mac_read_resp *resp; 98 struct ice_aqc_manage_mac_read *cmd; 99 struct ice_aq_desc desc; 100 enum ice_status status; 101 u16 flags; 102 u8 i; 103 104 cmd = &desc.params.mac_read; 105 106 if (buf_size < sizeof(*resp)) 107 return ICE_ERR_BUF_TOO_SHORT; 108 109 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 110 111 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 112 if (status) 113 return status; 114 115 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 116 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 117 118 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 119 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 120 return ICE_ERR_CFG; 121 } 122 123 /* A single port can report up to two (LAN and WoL) addresses */ 124 for (i = 0; i < cmd->num_addr; i++) 125 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 126 ice_memcpy(hw->port_info->mac.lan_addr, 127 resp[i].mac_addr, ETH_ALEN, 128 ICE_DMA_TO_NONDMA); 129 ice_memcpy(hw->port_info->mac.perm_addr, 130 resp[i].mac_addr, 131 ETH_ALEN, ICE_DMA_TO_NONDMA); 132 break; 133 } 134 return ICE_SUCCESS; 135 } 136 137 /** 138 * ice_aq_get_phy_caps - returns PHY capabilities 139 * @pi: port information structure 140 * @qual_mods: report qualified modules 141 * @report_mode: report mode capabilities 142 * @pcaps: structure for PHY capabilities to be filled 143 * @cd: pointer to command details structure or NULL 144 * 145 * Returns the various PHY capabilities supported on the Port (0x0600) 146 */ 147 enum ice_status 148 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 149 struct ice_aqc_get_phy_caps_data *pcaps, 150 struct ice_sq_cd *cd) 151 { 152 struct ice_aqc_get_phy_caps *cmd; 153 u16 pcaps_size = sizeof(*pcaps); 154 struct ice_aq_desc desc; 155 enum ice_status status; 156 struct ice_hw *hw; 157 158 cmd = &desc.params.get_phy; 159 160 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 161 return ICE_ERR_PARAM; 162 hw = pi->hw; 163 164 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 165 !ice_fw_supports_report_dflt_cfg(hw)) 166 return ICE_ERR_PARAM; 167 168 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 169 170 if (qual_mods) 171 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 172 173 cmd->param0 |= CPU_TO_LE16(report_mode); 174 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 175 176 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 177 report_mode); 178 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 179 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); 180 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 181 (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); 182 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 183 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 184 pcaps->low_power_ctrl_an); 185 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 186 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 187 pcaps->eeer_value); 188 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 189 pcaps->link_fec_options); 190 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 191 pcaps->module_compliance_enforcement); 192 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 193 pcaps->extended_compliance_code); 194 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 195 pcaps->module_type[0]); 196 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 197 pcaps->module_type[1]); 198 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 199 pcaps->module_type[2]); 200 201 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 202 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 203 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 204 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 205 sizeof(pi->phy.link_info.module_type), 206 ICE_NONDMA_TO_NONDMA); 207 } 208 209 return status; 210 } 211 212 /** 213 * ice_aq_get_link_topo_handle - get link topology node return status 214 * @pi: port information structure 215 * @node_type: requested node type 216 * @cd: pointer to command details structure or NULL 217 * 218 * Get link topology node return status for specified node type (0x06E0) 219 * 220 * Node type cage can be used to determine if cage is present. If AQC 221 * returns error (ENOENT), then no cage present. If no cage present, then 222 * connection type is backplane or BASE-T. 223 */ 224 static enum ice_status 225 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 226 struct ice_sq_cd *cd) 227 { 228 struct ice_aqc_get_link_topo *cmd; 229 struct ice_aq_desc desc; 230 231 cmd = &desc.params.get_link_topo; 232 233 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 234 235 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 236 ICE_AQC_LINK_TOPO_NODE_CTX_S); 237 238 /* set node type */ 239 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 240 241 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 242 } 243 244 /** 245 * ice_is_media_cage_present 246 * @pi: port information structure 247 * 248 * Returns true if media cage is present, else false. If no cage, then 249 * media type is backplane or BASE-T. 250 */ 251 static bool ice_is_media_cage_present(struct ice_port_info *pi) 252 { 253 /* Node type cage can be used to determine if cage is present. If AQC 254 * returns error (ENOENT), then no cage present. If no cage present then 255 * connection type is backplane or BASE-T. 256 */ 257 return !ice_aq_get_link_topo_handle(pi, 258 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 259 NULL); 260 } 261 262 /** 263 * ice_get_media_type - Gets media type 264 * @pi: port information structure 265 */ 266 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 267 { 268 struct ice_link_status *hw_link_info; 269 270 if (!pi) 271 return ICE_MEDIA_UNKNOWN; 272 273 hw_link_info = &pi->phy.link_info; 274 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 275 /* If more than one media type is selected, report unknown */ 276 return ICE_MEDIA_UNKNOWN; 277 278 if (hw_link_info->phy_type_low) { 279 /* 1G SGMII is a special case where some DA cable PHYs 280 * may show this as an option when it really shouldn't 281 * be since SGMII is meant to be between a MAC and a PHY 282 * in a backplane. Try to detect this case and handle it 283 */ 284 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 285 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 286 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 287 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 288 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 289 return ICE_MEDIA_DA; 290 291 switch (hw_link_info->phy_type_low) { 292 case ICE_PHY_TYPE_LOW_1000BASE_SX: 293 case ICE_PHY_TYPE_LOW_1000BASE_LX: 294 case ICE_PHY_TYPE_LOW_10GBASE_SR: 295 case ICE_PHY_TYPE_LOW_10GBASE_LR: 296 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 297 case ICE_PHY_TYPE_LOW_25GBASE_SR: 298 case ICE_PHY_TYPE_LOW_25GBASE_LR: 299 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 300 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 301 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 302 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 303 case ICE_PHY_TYPE_LOW_50GBASE_SR: 304 case ICE_PHY_TYPE_LOW_50GBASE_FR: 305 case ICE_PHY_TYPE_LOW_50GBASE_LR: 306 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 307 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 308 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 309 case ICE_PHY_TYPE_LOW_100GBASE_DR: 310 return ICE_MEDIA_FIBER; 311 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 312 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 313 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 314 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 315 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 316 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 317 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 318 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 319 return ICE_MEDIA_FIBER; 320 case ICE_PHY_TYPE_LOW_100BASE_TX: 321 case ICE_PHY_TYPE_LOW_1000BASE_T: 322 case ICE_PHY_TYPE_LOW_2500BASE_T: 323 case ICE_PHY_TYPE_LOW_5GBASE_T: 324 case ICE_PHY_TYPE_LOW_10GBASE_T: 325 case ICE_PHY_TYPE_LOW_25GBASE_T: 326 return ICE_MEDIA_BASET; 327 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 328 case ICE_PHY_TYPE_LOW_25GBASE_CR: 329 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 330 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 331 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 332 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 333 case ICE_PHY_TYPE_LOW_50GBASE_CP: 334 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 335 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 336 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 337 return ICE_MEDIA_DA; 338 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 339 case ICE_PHY_TYPE_LOW_40G_XLAUI: 340 case ICE_PHY_TYPE_LOW_50G_LAUI2: 341 case ICE_PHY_TYPE_LOW_50G_AUI2: 342 case ICE_PHY_TYPE_LOW_50G_AUI1: 343 case ICE_PHY_TYPE_LOW_100G_AUI4: 344 case ICE_PHY_TYPE_LOW_100G_CAUI4: 345 if (ice_is_media_cage_present(pi)) 346 return ICE_MEDIA_AUI; 347 /* fall-through */ 348 case ICE_PHY_TYPE_LOW_1000BASE_KX: 349 case ICE_PHY_TYPE_LOW_2500BASE_KX: 350 case ICE_PHY_TYPE_LOW_2500BASE_X: 351 case ICE_PHY_TYPE_LOW_5GBASE_KR: 352 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 353 case ICE_PHY_TYPE_LOW_25GBASE_KR: 354 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 355 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 356 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 357 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 358 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 359 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 360 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 361 return ICE_MEDIA_BACKPLANE; 362 } 363 } else { 364 switch (hw_link_info->phy_type_high) { 365 case ICE_PHY_TYPE_HIGH_100G_AUI2: 366 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 367 if (ice_is_media_cage_present(pi)) 368 return ICE_MEDIA_AUI; 369 /* fall-through */ 370 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 371 return ICE_MEDIA_BACKPLANE; 372 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 373 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 374 return ICE_MEDIA_FIBER; 375 } 376 } 377 return ICE_MEDIA_UNKNOWN; 378 } 379 380 /** 381 * ice_aq_get_link_info 382 * @pi: port information structure 383 * @ena_lse: enable/disable LinkStatusEvent reporting 384 * @link: pointer to link status structure - optional 385 * @cd: pointer to command details structure or NULL 386 * 387 * Get Link Status (0x607). Returns the link status of the adapter. 388 */ 389 enum ice_status 390 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 391 struct ice_link_status *link, struct ice_sq_cd *cd) 392 { 393 struct ice_aqc_get_link_status_data link_data = { 0 }; 394 struct ice_aqc_get_link_status *resp; 395 struct ice_link_status *li_old, *li; 396 enum ice_media_type *hw_media_type; 397 struct ice_fc_info *hw_fc_info; 398 bool tx_pause, rx_pause; 399 struct ice_aq_desc desc; 400 enum ice_status status; 401 struct ice_hw *hw; 402 u16 cmd_flags; 403 404 if (!pi) 405 return ICE_ERR_PARAM; 406 hw = pi->hw; 407 li_old = &pi->phy.link_info_old; 408 hw_media_type = &pi->phy.media_type; 409 li = &pi->phy.link_info; 410 hw_fc_info = &pi->fc; 411 412 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 413 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 414 resp = &desc.params.get_link_status; 415 resp->cmd_flags = CPU_TO_LE16(cmd_flags); 416 resp->lport_num = pi->lport; 417 418 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 419 420 if (status != ICE_SUCCESS) 421 return status; 422 423 /* save off old link status information */ 424 *li_old = *li; 425 426 /* update current link status information */ 427 li->link_speed = LE16_TO_CPU(link_data.link_speed); 428 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 429 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 430 *hw_media_type = ice_get_media_type(pi); 431 li->link_info = link_data.link_info; 432 li->an_info = link_data.an_info; 433 li->ext_info = link_data.ext_info; 434 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 435 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 436 li->topo_media_conflict = link_data.topo_media_conflict; 437 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 438 ICE_AQ_CFG_PACING_TYPE_M); 439 440 /* update fc info */ 441 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 442 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 443 if (tx_pause && rx_pause) 444 hw_fc_info->current_mode = ICE_FC_FULL; 445 else if (tx_pause) 446 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 447 else if (rx_pause) 448 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 449 else 450 hw_fc_info->current_mode = ICE_FC_NONE; 451 452 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 453 454 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 455 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 456 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 457 (unsigned long long)li->phy_type_low); 458 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 459 (unsigned long long)li->phy_type_high); 460 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 461 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 462 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 463 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 464 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 465 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 466 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 467 li->max_frame_size); 468 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 469 470 /* save link status information */ 471 if (link) 472 *link = *li; 473 474 /* flag cleared so calling functions don't call AQ again */ 475 pi->phy.get_link_info = false; 476 477 return ICE_SUCCESS; 478 } 479 480 /** 481 * ice_fill_tx_timer_and_fc_thresh 482 * @hw: pointer to the HW struct 483 * @cmd: pointer to MAC cfg structure 484 * 485 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 486 * descriptor 487 */ 488 static void 489 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 490 struct ice_aqc_set_mac_cfg *cmd) 491 { 492 u16 fc_thres_val, tx_timer_val; 493 u32 val; 494 495 /* We read back the transmit timer and fc threshold value of 496 * LFC. Thus, we will use index = 497 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 498 * 499 * Also, because we are opearating on transmit timer and fc 500 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 501 */ 502 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 503 504 /* Retrieve the transmit timer */ 505 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 506 tx_timer_val = val & 507 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 508 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 509 510 /* Retrieve the fc threshold */ 511 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 512 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 513 514 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 515 } 516 517 /** 518 * ice_aq_set_mac_cfg 519 * @hw: pointer to the HW struct 520 * @max_frame_size: Maximum Frame Size to be supported 521 * @cd: pointer to command details structure or NULL 522 * 523 * Set MAC configuration (0x0603) 524 */ 525 enum ice_status 526 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 527 { 528 struct ice_aqc_set_mac_cfg *cmd; 529 struct ice_aq_desc desc; 530 531 cmd = &desc.params.set_mac_cfg; 532 533 if (max_frame_size == 0) 534 return ICE_ERR_PARAM; 535 536 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 537 538 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 539 540 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 541 542 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 543 } 544 545 /** 546 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 547 * @hw: pointer to the HW struct 548 */ 549 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 550 { 551 struct ice_switch_info *sw; 552 enum ice_status status; 553 554 hw->switch_info = (struct ice_switch_info *) 555 ice_malloc(hw, sizeof(*hw->switch_info)); 556 557 sw = hw->switch_info; 558 559 if (!sw) 560 return ICE_ERR_NO_MEMORY; 561 562 INIT_LIST_HEAD(&sw->vsi_list_map_head); 563 sw->prof_res_bm_init = 0; 564 565 status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 566 if (status) { 567 ice_free(hw, hw->switch_info); 568 return status; 569 } 570 return ICE_SUCCESS; 571 } 572 573 /** 574 * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 575 * @hw: pointer to the HW struct 576 * @sw: pointer to switch info struct for which function clears filters 577 */ 578 static void 579 ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 580 { 581 struct ice_vsi_list_map_info *v_pos_map; 582 struct ice_vsi_list_map_info *v_tmp_map; 583 struct ice_sw_recipe *recps; 584 u8 i; 585 586 if (!sw) 587 return; 588 589 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 590 ice_vsi_list_map_info, list_entry) { 591 LIST_DEL(&v_pos_map->list_entry); 592 ice_free(hw, v_pos_map); 593 } 594 recps = sw->recp_list; 595 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 596 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 597 598 recps[i].root_rid = i; 599 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 600 &recps[i].rg_list, ice_recp_grp_entry, 601 l_entry) { 602 LIST_DEL(&rg_entry->l_entry); 603 ice_free(hw, rg_entry); 604 } 605 606 if (recps[i].adv_rule) { 607 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 608 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 609 610 ice_destroy_lock(&recps[i].filt_rule_lock); 611 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 612 &recps[i].filt_rules, 613 ice_adv_fltr_mgmt_list_entry, 614 list_entry) { 615 LIST_DEL(&lst_itr->list_entry); 616 ice_free(hw, lst_itr->lkups); 617 ice_free(hw, lst_itr); 618 } 619 } else { 620 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 621 622 ice_destroy_lock(&recps[i].filt_rule_lock); 623 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 624 &recps[i].filt_rules, 625 ice_fltr_mgmt_list_entry, 626 list_entry) { 627 LIST_DEL(&lst_itr->list_entry); 628 ice_free(hw, lst_itr); 629 } 630 } 631 if (recps[i].root_buf) 632 ice_free(hw, recps[i].root_buf); 633 } 634 ice_rm_sw_replay_rule_info(hw, sw); 635 ice_free(hw, sw->recp_list); 636 ice_free(hw, sw); 637 } 638 639 /** 640 * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks 641 * @hw: pointer to the HW struct 642 */ 643 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 644 { 645 ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 646 } 647 648 /** 649 * ice_get_itr_intrl_gran 650 * @hw: pointer to the HW struct 651 * 652 * Determines the ITR/INTRL granularities based on the maximum aggregate 653 * bandwidth according to the device's configuration during power-on. 654 */ 655 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 656 { 657 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 658 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 659 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 660 661 switch (max_agg_bw) { 662 case ICE_MAX_AGG_BW_200G: 663 case ICE_MAX_AGG_BW_100G: 664 case ICE_MAX_AGG_BW_50G: 665 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 666 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 667 break; 668 case ICE_MAX_AGG_BW_25G: 669 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 670 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 671 break; 672 } 673 } 674 675 /** 676 * ice_print_rollback_msg - print FW rollback message 677 * @hw: pointer to the hardware structure 678 */ 679 void ice_print_rollback_msg(struct ice_hw *hw) 680 { 681 char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 682 struct ice_orom_info *orom; 683 struct ice_nvm_info *nvm; 684 685 orom = &hw->flash.orom; 686 nvm = &hw->flash.nvm; 687 688 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 689 nvm->major, nvm->minor, nvm->eetrack, orom->major, 690 orom->build, orom->patch); 691 ice_warn(hw, 692 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 693 nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 694 } 695 696 /** 697 * ice_init_hw - main hardware initialization routine 698 * @hw: pointer to the hardware structure 699 */ 700 enum ice_status ice_init_hw(struct ice_hw *hw) 701 { 702 struct ice_aqc_get_phy_caps_data *pcaps; 703 enum ice_status status; 704 u16 mac_buf_len; 705 void *mac_buf; 706 707 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 708 709 /* Set MAC type based on DeviceID */ 710 status = ice_set_mac_type(hw); 711 if (status) 712 return status; 713 714 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 715 PF_FUNC_RID_FUNCTION_NUMBER_M) >> 716 PF_FUNC_RID_FUNCTION_NUMBER_S; 717 718 status = ice_reset(hw, ICE_RESET_PFR); 719 if (status) 720 return status; 721 722 ice_get_itr_intrl_gran(hw); 723 724 status = ice_create_all_ctrlq(hw); 725 if (status) 726 goto err_unroll_cqinit; 727 728 status = ice_init_nvm(hw); 729 if (status) 730 goto err_unroll_cqinit; 731 732 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 733 ice_print_rollback_msg(hw); 734 735 status = ice_clear_pf_cfg(hw); 736 if (status) 737 goto err_unroll_cqinit; 738 739 /* Set bit to enable Flow Director filters */ 740 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 741 INIT_LIST_HEAD(&hw->fdir_list_head); 742 743 ice_clear_pxe_mode(hw); 744 745 status = ice_get_caps(hw); 746 if (status) 747 goto err_unroll_cqinit; 748 749 hw->port_info = (struct ice_port_info *) 750 ice_malloc(hw, sizeof(*hw->port_info)); 751 if (!hw->port_info) { 752 status = ICE_ERR_NO_MEMORY; 753 goto err_unroll_cqinit; 754 } 755 756 /* set the back pointer to HW */ 757 hw->port_info->hw = hw; 758 759 /* Initialize port_info struct with switch configuration data */ 760 status = ice_get_initial_sw_cfg(hw); 761 if (status) 762 goto err_unroll_alloc; 763 764 hw->evb_veb = true; 765 /* Query the allocated resources for Tx scheduler */ 766 status = ice_sched_query_res_alloc(hw); 767 if (status) { 768 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 769 goto err_unroll_alloc; 770 } 771 ice_sched_get_psm_clk_freq(hw); 772 773 /* Initialize port_info struct with scheduler data */ 774 status = ice_sched_init_port(hw->port_info); 775 if (status) 776 goto err_unroll_sched; 777 pcaps = (struct ice_aqc_get_phy_caps_data *) 778 ice_malloc(hw, sizeof(*pcaps)); 779 if (!pcaps) { 780 status = ICE_ERR_NO_MEMORY; 781 goto err_unroll_sched; 782 } 783 784 /* Initialize port_info struct with PHY capabilities */ 785 status = ice_aq_get_phy_caps(hw->port_info, false, 786 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); 787 ice_free(hw, pcaps); 788 if (status) 789 ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", 790 status); 791 792 /* Initialize port_info struct with link information */ 793 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 794 if (status) 795 goto err_unroll_sched; 796 /* need a valid SW entry point to build a Tx tree */ 797 if (!hw->sw_entry_point_layer) { 798 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 799 status = ICE_ERR_CFG; 800 goto err_unroll_sched; 801 } 802 INIT_LIST_HEAD(&hw->agg_list); 803 /* Initialize max burst size */ 804 if (!hw->max_burst_size) 805 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 806 status = ice_init_fltr_mgmt_struct(hw); 807 if (status) 808 goto err_unroll_sched; 809 810 /* Get MAC information */ 811 /* A single port can report up to two (LAN and WoL) addresses */ 812 mac_buf = ice_calloc(hw, 2, 813 sizeof(struct ice_aqc_manage_mac_read_resp)); 814 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 815 816 if (!mac_buf) { 817 status = ICE_ERR_NO_MEMORY; 818 goto err_unroll_fltr_mgmt_struct; 819 } 820 821 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 822 ice_free(hw, mac_buf); 823 824 if (status) 825 goto err_unroll_fltr_mgmt_struct; 826 /* enable jumbo frame support at MAC level */ 827 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 828 if (status) 829 goto err_unroll_fltr_mgmt_struct; 830 /* Obtain counter base index which would be used by flow director */ 831 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 832 if (status) 833 goto err_unroll_fltr_mgmt_struct; 834 status = ice_init_hw_tbls(hw); 835 if (status) 836 goto err_unroll_fltr_mgmt_struct; 837 ice_init_lock(&hw->tnl_lock); 838 839 ice_init_vlan_mode_ops(hw); 840 841 return ICE_SUCCESS; 842 843 err_unroll_fltr_mgmt_struct: 844 ice_cleanup_fltr_mgmt_struct(hw); 845 err_unroll_sched: 846 ice_sched_cleanup_all(hw); 847 err_unroll_alloc: 848 ice_free(hw, hw->port_info); 849 hw->port_info = NULL; 850 err_unroll_cqinit: 851 ice_destroy_all_ctrlq(hw); 852 return status; 853 } 854 855 /** 856 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 857 * @hw: pointer to the hardware structure 858 * 859 * This should be called only during nominal operation, not as a result of 860 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 861 * applicable initializations if it fails for any reason. 862 */ 863 void ice_deinit_hw(struct ice_hw *hw) 864 { 865 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 866 ice_cleanup_fltr_mgmt_struct(hw); 867 868 ice_sched_cleanup_all(hw); 869 ice_sched_clear_agg(hw); 870 ice_free_seg(hw); 871 ice_free_hw_tbls(hw); 872 ice_destroy_lock(&hw->tnl_lock); 873 874 if (hw->port_info) { 875 ice_free(hw, hw->port_info); 876 hw->port_info = NULL; 877 } 878 879 ice_destroy_all_ctrlq(hw); 880 881 /* Clear VSI contexts if not already cleared */ 882 ice_clear_all_vsi_ctx(hw); 883 } 884 885 /** 886 * ice_check_reset - Check to see if a global reset is complete 887 * @hw: pointer to the hardware structure 888 */ 889 enum ice_status ice_check_reset(struct ice_hw *hw) 890 { 891 u32 cnt, reg = 0, grst_timeout, uld_mask; 892 893 /* Poll for Device Active state in case a recent CORER, GLOBR, 894 * or EMPR has occurred. The grst delay value is in 100ms units. 895 * Add 1sec for outstanding AQ commands that can take a long time. 896 */ 897 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 898 GLGEN_RSTCTL_GRSTDEL_S) + 10; 899 900 for (cnt = 0; cnt < grst_timeout; cnt++) { 901 ice_msec_delay(100, true); 902 reg = rd32(hw, GLGEN_RSTAT); 903 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 904 break; 905 } 906 907 if (cnt == grst_timeout) { 908 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 909 return ICE_ERR_RESET_FAILED; 910 } 911 912 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 913 GLNVM_ULD_PCIER_DONE_1_M |\ 914 GLNVM_ULD_CORER_DONE_M |\ 915 GLNVM_ULD_GLOBR_DONE_M |\ 916 GLNVM_ULD_POR_DONE_M |\ 917 GLNVM_ULD_POR_DONE_1_M |\ 918 GLNVM_ULD_PCIER_DONE_2_M) 919 920 uld_mask = ICE_RESET_DONE_MASK; 921 922 /* Device is Active; check Global Reset processes are done */ 923 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 924 reg = rd32(hw, GLNVM_ULD) & uld_mask; 925 if (reg == uld_mask) { 926 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 927 break; 928 } 929 ice_msec_delay(10, true); 930 } 931 932 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 933 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 934 reg); 935 return ICE_ERR_RESET_FAILED; 936 } 937 938 return ICE_SUCCESS; 939 } 940 941 /** 942 * ice_pf_reset - Reset the PF 943 * @hw: pointer to the hardware structure 944 * 945 * If a global reset has been triggered, this function checks 946 * for its completion and then issues the PF reset 947 */ 948 static enum ice_status ice_pf_reset(struct ice_hw *hw) 949 { 950 u32 cnt, reg; 951 952 /* If at function entry a global reset was already in progress, i.e. 953 * state is not 'device active' or any of the reset done bits are not 954 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 955 * global reset is done. 956 */ 957 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 958 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 959 /* poll on global reset currently in progress until done */ 960 if (ice_check_reset(hw)) 961 return ICE_ERR_RESET_FAILED; 962 963 return ICE_SUCCESS; 964 } 965 966 /* Reset the PF */ 967 reg = rd32(hw, PFGEN_CTRL); 968 969 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 970 971 /* Wait for the PFR to complete. The wait time is the global config lock 972 * timeout plus the PFR timeout which will account for a possible reset 973 * that is occurring during a download package operation. 974 */ 975 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 976 ICE_PF_RESET_WAIT_COUNT; cnt++) { 977 reg = rd32(hw, PFGEN_CTRL); 978 if (!(reg & PFGEN_CTRL_PFSWR_M)) 979 break; 980 981 ice_msec_delay(1, true); 982 } 983 984 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 985 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 986 return ICE_ERR_RESET_FAILED; 987 } 988 989 return ICE_SUCCESS; 990 } 991 992 /** 993 * ice_reset - Perform different types of reset 994 * @hw: pointer to the hardware structure 995 * @req: reset request 996 * 997 * This function triggers a reset as specified by the req parameter. 998 * 999 * Note: 1000 * If anything other than a PF reset is triggered, PXE mode is restored. 1001 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1002 * interface has been restored in the rebuild flow. 1003 */ 1004 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1005 { 1006 u32 val = 0; 1007 1008 switch (req) { 1009 case ICE_RESET_PFR: 1010 return ice_pf_reset(hw); 1011 case ICE_RESET_CORER: 1012 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1013 val = GLGEN_RTRIG_CORER_M; 1014 break; 1015 case ICE_RESET_GLOBR: 1016 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1017 val = GLGEN_RTRIG_GLOBR_M; 1018 break; 1019 default: 1020 return ICE_ERR_PARAM; 1021 } 1022 1023 val |= rd32(hw, GLGEN_RTRIG); 1024 wr32(hw, GLGEN_RTRIG, val); 1025 ice_flush(hw); 1026 1027 /* wait for the FW to be ready */ 1028 return ice_check_reset(hw); 1029 } 1030 1031 /** 1032 * ice_copy_rxq_ctx_to_hw 1033 * @hw: pointer to the hardware structure 1034 * @ice_rxq_ctx: pointer to the rxq context 1035 * @rxq_index: the index of the Rx queue 1036 * 1037 * Copies rxq context from dense structure to HW register space 1038 */ 1039 static enum ice_status 1040 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1041 { 1042 u8 i; 1043 1044 if (!ice_rxq_ctx) 1045 return ICE_ERR_BAD_PTR; 1046 1047 if (rxq_index > QRX_CTRL_MAX_INDEX) 1048 return ICE_ERR_PARAM; 1049 1050 /* Copy each dword separately to HW */ 1051 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1052 wr32(hw, QRX_CONTEXT(i, rxq_index), 1053 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1054 1055 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1056 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1057 } 1058 1059 return ICE_SUCCESS; 1060 } 1061 1062 /* LAN Rx Queue Context */ 1063 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1064 /* Field Width LSB */ 1065 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1066 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1067 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1068 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1069 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1070 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1071 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1072 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1073 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1074 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1075 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1076 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1077 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1078 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1079 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1080 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1081 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1082 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1083 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1084 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1085 { 0 } 1086 }; 1087 1088 /** 1089 * ice_write_rxq_ctx 1090 * @hw: pointer to the hardware structure 1091 * @rlan_ctx: pointer to the rxq context 1092 * @rxq_index: the index of the Rx queue 1093 * 1094 * Converts rxq context from sparse to dense structure and then writes 1095 * it to HW register space and enables the hardware to prefetch descriptors 1096 * instead of only fetching them on demand 1097 */ 1098 enum ice_status 1099 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1100 u32 rxq_index) 1101 { 1102 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1103 1104 if (!rlan_ctx) 1105 return ICE_ERR_BAD_PTR; 1106 1107 rlan_ctx->prefena = 1; 1108 1109 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1110 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1111 } 1112 1113 /** 1114 * ice_clear_rxq_ctx 1115 * @hw: pointer to the hardware structure 1116 * @rxq_index: the index of the Rx queue to clear 1117 * 1118 * Clears rxq context in HW register space 1119 */ 1120 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 1121 { 1122 u8 i; 1123 1124 if (rxq_index > QRX_CTRL_MAX_INDEX) 1125 return ICE_ERR_PARAM; 1126 1127 /* Clear each dword register separately */ 1128 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 1129 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 1130 1131 return ICE_SUCCESS; 1132 } 1133 1134 /* LAN Tx Queue Context */ 1135 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1136 /* Field Width LSB */ 1137 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1138 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1139 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1140 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1141 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1142 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1143 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1144 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1145 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1146 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1147 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1148 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1149 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1150 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1151 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1152 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1153 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1154 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1155 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1156 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1157 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1158 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1159 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1160 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1161 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1162 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1163 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1164 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1165 { 0 } 1166 }; 1167 1168 /** 1169 * ice_copy_tx_cmpltnq_ctx_to_hw 1170 * @hw: pointer to the hardware structure 1171 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 1172 * @tx_cmpltnq_index: the index of the completion queue 1173 * 1174 * Copies Tx completion queue context from dense structure to HW register space 1175 */ 1176 static enum ice_status 1177 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 1178 u32 tx_cmpltnq_index) 1179 { 1180 u8 i; 1181 1182 if (!ice_tx_cmpltnq_ctx) 1183 return ICE_ERR_BAD_PTR; 1184 1185 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1186 return ICE_ERR_PARAM; 1187 1188 /* Copy each dword separately to HW */ 1189 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 1190 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 1191 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1192 1193 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 1194 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 1195 } 1196 1197 return ICE_SUCCESS; 1198 } 1199 1200 /* LAN Tx Completion Queue Context */ 1201 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 1202 /* Field Width LSB */ 1203 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 1204 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 1205 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 1206 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 1207 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 1208 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 1209 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 1210 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 1211 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 1212 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 1213 { 0 } 1214 }; 1215 1216 /** 1217 * ice_write_tx_cmpltnq_ctx 1218 * @hw: pointer to the hardware structure 1219 * @tx_cmpltnq_ctx: pointer to the completion queue context 1220 * @tx_cmpltnq_index: the index of the completion queue 1221 * 1222 * Converts completion queue context from sparse to dense structure and then 1223 * writes it to HW register space 1224 */ 1225 enum ice_status 1226 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 1227 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 1228 u32 tx_cmpltnq_index) 1229 { 1230 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1231 1232 ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 1233 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 1234 } 1235 1236 /** 1237 * ice_clear_tx_cmpltnq_ctx 1238 * @hw: pointer to the hardware structure 1239 * @tx_cmpltnq_index: the index of the completion queue to clear 1240 * 1241 * Clears Tx completion queue context in HW register space 1242 */ 1243 enum ice_status 1244 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 1245 { 1246 u8 i; 1247 1248 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 1249 return ICE_ERR_PARAM; 1250 1251 /* Clear each dword register separately */ 1252 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 1253 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 1254 1255 return ICE_SUCCESS; 1256 } 1257 1258 /** 1259 * ice_copy_tx_drbell_q_ctx_to_hw 1260 * @hw: pointer to the hardware structure 1261 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 1262 * @tx_drbell_q_index: the index of the doorbell queue 1263 * 1264 * Copies doorbell queue context from dense structure to HW register space 1265 */ 1266 static enum ice_status 1267 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 1268 u32 tx_drbell_q_index) 1269 { 1270 u8 i; 1271 1272 if (!ice_tx_drbell_q_ctx) 1273 return ICE_ERR_BAD_PTR; 1274 1275 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1276 return ICE_ERR_PARAM; 1277 1278 /* Copy each dword separately to HW */ 1279 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 1280 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 1281 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1282 1283 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 1284 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 1285 } 1286 1287 return ICE_SUCCESS; 1288 } 1289 1290 /* LAN Tx Doorbell Queue Context info */ 1291 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 1292 /* Field Width LSB */ 1293 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 1294 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 1295 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 1296 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 1297 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 1298 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 1299 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 1300 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 1301 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 1302 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 1303 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 1304 { 0 } 1305 }; 1306 1307 /** 1308 * ice_write_tx_drbell_q_ctx 1309 * @hw: pointer to the hardware structure 1310 * @tx_drbell_q_ctx: pointer to the doorbell queue context 1311 * @tx_drbell_q_index: the index of the doorbell queue 1312 * 1313 * Converts doorbell queue context from sparse to dense structure and then 1314 * writes it to HW register space 1315 */ 1316 enum ice_status 1317 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 1318 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 1319 u32 tx_drbell_q_index) 1320 { 1321 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 1322 1323 ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 1324 ice_tx_drbell_q_ctx_info); 1325 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 1326 } 1327 1328 /** 1329 * ice_clear_tx_drbell_q_ctx 1330 * @hw: pointer to the hardware structure 1331 * @tx_drbell_q_index: the index of the doorbell queue to clear 1332 * 1333 * Clears doorbell queue context in HW register space 1334 */ 1335 enum ice_status 1336 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 1337 { 1338 u8 i; 1339 1340 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 1341 return ICE_ERR_PARAM; 1342 1343 /* Clear each dword register separately */ 1344 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 1345 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 1346 1347 return ICE_SUCCESS; 1348 } 1349 1350 /* FW Admin Queue command wrappers */ 1351 1352 /** 1353 * ice_should_retry_sq_send_cmd 1354 * @opcode: AQ opcode 1355 * 1356 * Decide if we should retry the send command routine for the ATQ, depending 1357 * on the opcode. 1358 */ 1359 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1360 { 1361 switch (opcode) { 1362 case ice_aqc_opc_get_link_topo: 1363 case ice_aqc_opc_lldp_stop: 1364 case ice_aqc_opc_lldp_start: 1365 case ice_aqc_opc_lldp_filter_ctrl: 1366 return true; 1367 } 1368 1369 return false; 1370 } 1371 1372 /** 1373 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1374 * @hw: pointer to the HW struct 1375 * @cq: pointer to the specific Control queue 1376 * @desc: prefilled descriptor describing the command 1377 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1378 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1379 * @cd: pointer to command details structure 1380 * 1381 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1382 * Queue if the EBUSY AQ error is returned. 1383 */ 1384 static enum ice_status 1385 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1386 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1387 struct ice_sq_cd *cd) 1388 { 1389 struct ice_aq_desc desc_cpy; 1390 enum ice_status status; 1391 bool is_cmd_for_retry; 1392 u8 *buf_cpy = NULL; 1393 u8 idx = 0; 1394 u16 opcode; 1395 1396 opcode = LE16_TO_CPU(desc->opcode); 1397 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1398 ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); 1399 1400 if (is_cmd_for_retry) { 1401 if (buf) { 1402 buf_cpy = (u8 *)ice_malloc(hw, buf_size); 1403 if (!buf_cpy) 1404 return ICE_ERR_NO_MEMORY; 1405 } 1406 1407 ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), 1408 ICE_NONDMA_TO_NONDMA); 1409 } 1410 1411 do { 1412 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1413 1414 if (!is_cmd_for_retry || status == ICE_SUCCESS || 1415 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1416 break; 1417 1418 if (buf_cpy) 1419 ice_memcpy(buf, buf_cpy, buf_size, 1420 ICE_NONDMA_TO_NONDMA); 1421 1422 ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), 1423 ICE_NONDMA_TO_NONDMA); 1424 1425 ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); 1426 1427 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1428 1429 if (buf_cpy) 1430 ice_free(hw, buf_cpy); 1431 1432 return status; 1433 } 1434 1435 /** 1436 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1437 * @hw: pointer to the HW struct 1438 * @desc: descriptor describing the command 1439 * @buf: buffer to use for indirect commands (NULL for direct commands) 1440 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1441 * @cd: pointer to command details structure 1442 * 1443 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1444 */ 1445 enum ice_status 1446 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1447 u16 buf_size, struct ice_sq_cd *cd) 1448 { 1449 if (hw->aq_send_cmd_fn) { 1450 enum ice_status status = ICE_ERR_NOT_READY; 1451 u16 retval = ICE_AQ_RC_OK; 1452 1453 ice_acquire_lock(&hw->adminq.sq_lock); 1454 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc, 1455 buf, buf_size)) { 1456 retval = LE16_TO_CPU(desc->retval); 1457 /* strip off FW internal code */ 1458 if (retval) 1459 retval &= 0xff; 1460 if (retval == ICE_AQ_RC_OK) 1461 status = ICE_SUCCESS; 1462 else 1463 status = ICE_ERR_AQ_ERROR; 1464 } 1465 1466 hw->adminq.sq_last_status = (enum ice_aq_err)retval; 1467 ice_release_lock(&hw->adminq.sq_lock); 1468 1469 return status; 1470 } 1471 return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1472 } 1473 1474 /** 1475 * ice_aq_get_fw_ver 1476 * @hw: pointer to the HW struct 1477 * @cd: pointer to command details structure or NULL 1478 * 1479 * Get the firmware version (0x0001) from the admin queue commands 1480 */ 1481 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1482 { 1483 struct ice_aqc_get_ver *resp; 1484 struct ice_aq_desc desc; 1485 enum ice_status status; 1486 1487 resp = &desc.params.get_ver; 1488 1489 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1490 1491 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1492 1493 if (!status) { 1494 hw->fw_branch = resp->fw_branch; 1495 hw->fw_maj_ver = resp->fw_major; 1496 hw->fw_min_ver = resp->fw_minor; 1497 hw->fw_patch = resp->fw_patch; 1498 hw->fw_build = LE32_TO_CPU(resp->fw_build); 1499 hw->api_branch = resp->api_branch; 1500 hw->api_maj_ver = resp->api_major; 1501 hw->api_min_ver = resp->api_minor; 1502 hw->api_patch = resp->api_patch; 1503 } 1504 1505 return status; 1506 } 1507 1508 /** 1509 * ice_aq_send_driver_ver 1510 * @hw: pointer to the HW struct 1511 * @dv: driver's major, minor version 1512 * @cd: pointer to command details structure or NULL 1513 * 1514 * Send the driver version (0x0002) to the firmware 1515 */ 1516 enum ice_status 1517 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1518 struct ice_sq_cd *cd) 1519 { 1520 struct ice_aqc_driver_ver *cmd; 1521 struct ice_aq_desc desc; 1522 u16 len; 1523 1524 cmd = &desc.params.driver_ver; 1525 1526 if (!dv) 1527 return ICE_ERR_PARAM; 1528 1529 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1530 1531 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1532 cmd->major_ver = dv->major_ver; 1533 cmd->minor_ver = dv->minor_ver; 1534 cmd->build_ver = dv->build_ver; 1535 cmd->subbuild_ver = dv->subbuild_ver; 1536 1537 len = 0; 1538 while (len < sizeof(dv->driver_string) && 1539 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 1540 len++; 1541 1542 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1543 } 1544 1545 /** 1546 * ice_aq_q_shutdown 1547 * @hw: pointer to the HW struct 1548 * @unloading: is the driver unloading itself 1549 * 1550 * Tell the Firmware that we're shutting down the AdminQ and whether 1551 * or not the driver is unloading as well (0x0003). 1552 */ 1553 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1554 { 1555 struct ice_aqc_q_shutdown *cmd; 1556 struct ice_aq_desc desc; 1557 1558 cmd = &desc.params.q_shutdown; 1559 1560 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1561 1562 if (unloading) 1563 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1564 1565 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1566 } 1567 1568 /** 1569 * ice_aq_req_res 1570 * @hw: pointer to the HW struct 1571 * @res: resource ID 1572 * @access: access type 1573 * @sdp_number: resource number 1574 * @timeout: the maximum time in ms that the driver may hold the resource 1575 * @cd: pointer to command details structure or NULL 1576 * 1577 * Requests common resource using the admin queue commands (0x0008). 1578 * When attempting to acquire the Global Config Lock, the driver can 1579 * learn of three states: 1580 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1581 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1582 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1583 * successfully downloaded the package; the driver does 1584 * not have to download the package and can continue 1585 * loading 1586 * 1587 * Note that if the caller is in an acquire lock, perform action, release lock 1588 * phase of operation, it is possible that the FW may detect a timeout and issue 1589 * a CORER. In this case, the driver will receive a CORER interrupt and will 1590 * have to determine its cause. The calling thread that is handling this flow 1591 * will likely get an error propagated back to it indicating the Download 1592 * Package, Update Package or the Release Resource AQ commands timed out. 1593 */ 1594 static enum ice_status 1595 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1596 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1597 struct ice_sq_cd *cd) 1598 { 1599 struct ice_aqc_req_res *cmd_resp; 1600 struct ice_aq_desc desc; 1601 enum ice_status status; 1602 1603 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1604 1605 cmd_resp = &desc.params.res_owner; 1606 1607 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1608 1609 cmd_resp->res_id = CPU_TO_LE16(res); 1610 cmd_resp->access_type = CPU_TO_LE16(access); 1611 cmd_resp->res_number = CPU_TO_LE32(sdp_number); 1612 cmd_resp->timeout = CPU_TO_LE32(*timeout); 1613 *timeout = 0; 1614 1615 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1616 1617 /* The completion specifies the maximum time in ms that the driver 1618 * may hold the resource in the Timeout field. 1619 */ 1620 1621 /* Global config lock response utilizes an additional status field. 1622 * 1623 * If the Global config lock resource is held by some other driver, the 1624 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1625 * and the timeout field indicates the maximum time the current owner 1626 * of the resource has to free it. 1627 */ 1628 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1629 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1630 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1631 return ICE_SUCCESS; 1632 } else if (LE16_TO_CPU(cmd_resp->status) == 1633 ICE_AQ_RES_GLBL_IN_PROG) { 1634 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1635 return ICE_ERR_AQ_ERROR; 1636 } else if (LE16_TO_CPU(cmd_resp->status) == 1637 ICE_AQ_RES_GLBL_DONE) { 1638 return ICE_ERR_AQ_NO_WORK; 1639 } 1640 1641 /* invalid FW response, force a timeout immediately */ 1642 *timeout = 0; 1643 return ICE_ERR_AQ_ERROR; 1644 } 1645 1646 /* If the resource is held by some other driver, the command completes 1647 * with a busy return value and the timeout field indicates the maximum 1648 * time the current owner of the resource has to free it. 1649 */ 1650 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1651 *timeout = LE32_TO_CPU(cmd_resp->timeout); 1652 1653 return status; 1654 } 1655 1656 /** 1657 * ice_aq_release_res 1658 * @hw: pointer to the HW struct 1659 * @res: resource ID 1660 * @sdp_number: resource number 1661 * @cd: pointer to command details structure or NULL 1662 * 1663 * release common resource using the admin queue commands (0x0009) 1664 */ 1665 static enum ice_status 1666 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1667 struct ice_sq_cd *cd) 1668 { 1669 struct ice_aqc_req_res *cmd; 1670 struct ice_aq_desc desc; 1671 1672 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1673 1674 cmd = &desc.params.res_owner; 1675 1676 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1677 1678 cmd->res_id = CPU_TO_LE16(res); 1679 cmd->res_number = CPU_TO_LE32(sdp_number); 1680 1681 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1682 } 1683 1684 /** 1685 * ice_acquire_res 1686 * @hw: pointer to the HW structure 1687 * @res: resource ID 1688 * @access: access type (read or write) 1689 * @timeout: timeout in milliseconds 1690 * 1691 * This function will attempt to acquire the ownership of a resource. 1692 */ 1693 enum ice_status 1694 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1695 enum ice_aq_res_access_type access, u32 timeout) 1696 { 1697 #define ICE_RES_POLLING_DELAY_MS 10 1698 u32 delay = ICE_RES_POLLING_DELAY_MS; 1699 u32 time_left = timeout; 1700 enum ice_status status; 1701 1702 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1703 1704 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1705 1706 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1707 * previously acquired the resource and performed any necessary updates; 1708 * in this case the caller does not obtain the resource and has no 1709 * further work to do. 1710 */ 1711 if (status == ICE_ERR_AQ_NO_WORK) 1712 goto ice_acquire_res_exit; 1713 1714 if (status) 1715 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1716 1717 /* If necessary, poll until the current lock owner timeouts */ 1718 timeout = time_left; 1719 while (status && timeout && time_left) { 1720 ice_msec_delay(delay, true); 1721 timeout = (timeout > delay) ? timeout - delay : 0; 1722 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1723 1724 if (status == ICE_ERR_AQ_NO_WORK) 1725 /* lock free, but no work to do */ 1726 break; 1727 1728 if (!status) 1729 /* lock acquired */ 1730 break; 1731 } 1732 if (status && status != ICE_ERR_AQ_NO_WORK) 1733 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1734 1735 ice_acquire_res_exit: 1736 if (status == ICE_ERR_AQ_NO_WORK) { 1737 if (access == ICE_RES_WRITE) 1738 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1739 else 1740 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1741 } 1742 return status; 1743 } 1744 1745 /** 1746 * ice_release_res 1747 * @hw: pointer to the HW structure 1748 * @res: resource ID 1749 * 1750 * This function will release a resource using the proper Admin Command. 1751 */ 1752 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1753 { 1754 enum ice_status status; 1755 u32 total_delay = 0; 1756 1757 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1758 1759 status = ice_aq_release_res(hw, res, 0, NULL); 1760 1761 /* there are some rare cases when trying to release the resource 1762 * results in an admin queue timeout, so handle them correctly 1763 */ 1764 while ((status == ICE_ERR_AQ_TIMEOUT) && 1765 (total_delay < hw->adminq.sq_cmd_timeout)) { 1766 ice_msec_delay(1, true); 1767 status = ice_aq_release_res(hw, res, 0, NULL); 1768 total_delay++; 1769 } 1770 } 1771 1772 /** 1773 * ice_aq_alloc_free_res - command to allocate/free resources 1774 * @hw: pointer to the HW struct 1775 * @num_entries: number of resource entries in buffer 1776 * @buf: Indirect buffer to hold data parameters and response 1777 * @buf_size: size of buffer for indirect commands 1778 * @opc: pass in the command opcode 1779 * @cd: pointer to command details structure or NULL 1780 * 1781 * Helper function to allocate/free resources using the admin queue commands 1782 */ 1783 enum ice_status 1784 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1785 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1786 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1787 { 1788 struct ice_aqc_alloc_free_res_cmd *cmd; 1789 struct ice_aq_desc desc; 1790 1791 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 1792 1793 cmd = &desc.params.sw_res_ctrl; 1794 1795 if (!buf) 1796 return ICE_ERR_PARAM; 1797 1798 if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) 1799 return ICE_ERR_PARAM; 1800 1801 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1802 1803 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 1804 1805 cmd->num_entries = CPU_TO_LE16(num_entries); 1806 1807 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1808 } 1809 1810 /** 1811 * ice_alloc_hw_res - allocate resource 1812 * @hw: pointer to the HW struct 1813 * @type: type of resource 1814 * @num: number of resources to allocate 1815 * @btm: allocate from bottom 1816 * @res: pointer to array that will receive the resources 1817 */ 1818 enum ice_status 1819 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1820 { 1821 struct ice_aqc_alloc_free_res_elem *buf; 1822 enum ice_status status; 1823 u16 buf_len; 1824 1825 buf_len = ice_struct_size(buf, elem, num); 1826 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1827 if (!buf) 1828 return ICE_ERR_NO_MEMORY; 1829 1830 /* Prepare buffer to allocate resource. */ 1831 buf->num_elems = CPU_TO_LE16(num); 1832 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1833 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1834 if (btm) 1835 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1836 1837 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1838 ice_aqc_opc_alloc_res, NULL); 1839 if (status) 1840 goto ice_alloc_res_exit; 1841 1842 ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num, 1843 ICE_NONDMA_TO_NONDMA); 1844 1845 ice_alloc_res_exit: 1846 ice_free(hw, buf); 1847 return status; 1848 } 1849 1850 /** 1851 * ice_free_hw_res - free allocated HW resource 1852 * @hw: pointer to the HW struct 1853 * @type: type of resource to free 1854 * @num: number of resources 1855 * @res: pointer to array that contains the resources to free 1856 */ 1857 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1858 { 1859 struct ice_aqc_alloc_free_res_elem *buf; 1860 enum ice_status status; 1861 u16 buf_len; 1862 1863 buf_len = ice_struct_size(buf, elem, num); 1864 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 1865 if (!buf) 1866 return ICE_ERR_NO_MEMORY; 1867 1868 /* Prepare buffer to free resource. */ 1869 buf->num_elems = CPU_TO_LE16(num); 1870 buf->res_type = CPU_TO_LE16(type); 1871 ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num, 1872 ICE_NONDMA_TO_NONDMA); 1873 1874 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1875 ice_aqc_opc_free_res, NULL); 1876 if (status) 1877 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1878 1879 ice_free(hw, buf); 1880 return status; 1881 } 1882 1883 /** 1884 * ice_get_num_per_func - determine number of resources per PF 1885 * @hw: pointer to the HW structure 1886 * @max: value to be evenly split between each PF 1887 * 1888 * Determine the number of valid functions by going through the bitmap returned 1889 * from parsing capabilities and use this to calculate the number of resources 1890 * per PF based on the max value passed in. 1891 */ 1892 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1893 { 1894 u8 funcs; 1895 1896 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1897 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 1898 ICE_CAPS_VALID_FUNCS_M); 1899 1900 if (!funcs) 1901 return 0; 1902 1903 return max / funcs; 1904 } 1905 1906 /** 1907 * ice_parse_common_caps - parse common device/function capabilities 1908 * @hw: pointer to the HW struct 1909 * @caps: pointer to common capabilities structure 1910 * @elem: the capability element to parse 1911 * @prefix: message prefix for tracing capabilities 1912 * 1913 * Given a capability element, extract relevant details into the common 1914 * capability structure. 1915 * 1916 * Returns: true if the capability matches one of the common capability ids, 1917 * false otherwise. 1918 */ 1919 static bool 1920 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1921 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1922 { 1923 u32 logical_id = LE32_TO_CPU(elem->logical_id); 1924 u32 phys_id = LE32_TO_CPU(elem->phys_id); 1925 u32 number = LE32_TO_CPU(elem->number); 1926 u16 cap = LE16_TO_CPU(elem->cap); 1927 bool found = true; 1928 1929 switch (cap) { 1930 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1931 caps->valid_functions = number; 1932 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1933 caps->valid_functions); 1934 break; 1935 case ICE_AQC_CAPS_DCB: 1936 caps->dcb = (number == 1); 1937 caps->active_tc_bitmap = logical_id; 1938 caps->maxtc = phys_id; 1939 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 1940 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1941 caps->active_tc_bitmap); 1942 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1943 break; 1944 case ICE_AQC_CAPS_RSS: 1945 caps->rss_table_size = number; 1946 caps->rss_table_entry_width = logical_id; 1947 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 1948 caps->rss_table_size); 1949 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 1950 caps->rss_table_entry_width); 1951 break; 1952 case ICE_AQC_CAPS_RXQS: 1953 caps->num_rxq = number; 1954 caps->rxq_first_id = phys_id; 1955 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1956 caps->num_rxq); 1957 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 1958 caps->rxq_first_id); 1959 break; 1960 case ICE_AQC_CAPS_TXQS: 1961 caps->num_txq = number; 1962 caps->txq_first_id = phys_id; 1963 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1964 caps->num_txq); 1965 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 1966 caps->txq_first_id); 1967 break; 1968 case ICE_AQC_CAPS_MSIX: 1969 caps->num_msix_vectors = number; 1970 caps->msix_vector_first_id = phys_id; 1971 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 1972 caps->num_msix_vectors); 1973 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 1974 caps->msix_vector_first_id); 1975 break; 1976 case ICE_AQC_CAPS_NVM_MGMT: 1977 caps->sec_rev_disabled = 1978 (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? 1979 true : false; 1980 ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, 1981 caps->sec_rev_disabled); 1982 caps->update_disabled = 1983 (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? 1984 true : false; 1985 ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, 1986 caps->update_disabled); 1987 caps->nvm_unified_update = 1988 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1989 true : false; 1990 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1991 caps->nvm_unified_update); 1992 break; 1993 case ICE_AQC_CAPS_MAX_MTU: 1994 caps->max_mtu = number; 1995 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1996 prefix, caps->max_mtu); 1997 break; 1998 default: 1999 /* Not one of the recognized common capabilities */ 2000 found = false; 2001 } 2002 2003 return found; 2004 } 2005 2006 /** 2007 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2008 * @hw: pointer to the HW structure 2009 * @caps: pointer to capabilities structure to fix 2010 * 2011 * Re-calculate the capabilities that are dependent on the number of physical 2012 * ports; i.e. some features are not supported or function differently on 2013 * devices with more than 4 ports. 2014 */ 2015 static void 2016 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2017 { 2018 /* This assumes device capabilities are always scanned before function 2019 * capabilities during the initialization flow. 2020 */ 2021 if (hw->dev_caps.num_funcs > 4) { 2022 /* Max 4 TCs per port */ 2023 caps->maxtc = 4; 2024 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2025 caps->maxtc); 2026 } 2027 } 2028 2029 /** 2030 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2031 * @hw: pointer to the HW struct 2032 * @func_p: pointer to function capabilities structure 2033 * @cap: pointer to the capability element to parse 2034 * 2035 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2036 */ 2037 static void 2038 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2039 struct ice_aqc_list_caps_elem *cap) 2040 { 2041 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2042 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2043 LE32_TO_CPU(cap->number)); 2044 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2045 func_p->guar_num_vsi); 2046 } 2047 2048 /** 2049 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2050 * @hw: pointer to the HW struct 2051 * @func_p: pointer to function capabilities structure 2052 * 2053 * Extract function capabilities for ICE_AQC_CAPS_FD. 2054 */ 2055 static void 2056 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2057 { 2058 u32 reg_val, val; 2059 2060 if (hw->dcf_enabled) 2061 return; 2062 reg_val = rd32(hw, GLQF_FD_SIZE); 2063 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2064 GLQF_FD_SIZE_FD_GSIZE_S; 2065 func_p->fd_fltr_guar = 2066 ice_get_num_per_func(hw, val); 2067 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2068 GLQF_FD_SIZE_FD_BSIZE_S; 2069 func_p->fd_fltr_best_effort = val; 2070 2071 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2072 func_p->fd_fltr_guar); 2073 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2074 func_p->fd_fltr_best_effort); 2075 } 2076 2077 /** 2078 * ice_parse_func_caps - Parse function capabilities 2079 * @hw: pointer to the HW struct 2080 * @func_p: pointer to function capabilities structure 2081 * @buf: buffer containing the function capability records 2082 * @cap_count: the number of capabilities 2083 * 2084 * Helper function to parse function (0x000A) capabilities list. For 2085 * capabilities shared between device and function, this relies on 2086 * ice_parse_common_caps. 2087 * 2088 * Loop through the list of provided capabilities and extract the relevant 2089 * data into the function capabilities structured. 2090 */ 2091 static void 2092 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2093 void *buf, u32 cap_count) 2094 { 2095 struct ice_aqc_list_caps_elem *cap_resp; 2096 u32 i; 2097 2098 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2099 2100 ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 2101 2102 for (i = 0; i < cap_count; i++) { 2103 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2104 bool found; 2105 2106 found = ice_parse_common_caps(hw, &func_p->common_cap, 2107 &cap_resp[i], "func caps"); 2108 2109 switch (cap) { 2110 case ICE_AQC_CAPS_VSI: 2111 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2112 break; 2113 case ICE_AQC_CAPS_FD: 2114 ice_parse_fdir_func_caps(hw, func_p); 2115 break; 2116 default: 2117 /* Don't list common capabilities as unknown */ 2118 if (!found) 2119 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2120 i, cap); 2121 break; 2122 } 2123 } 2124 2125 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2126 } 2127 2128 /** 2129 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2130 * @hw: pointer to the HW struct 2131 * @dev_p: pointer to device capabilities structure 2132 * @cap: capability element to parse 2133 * 2134 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2135 */ 2136 static void 2137 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2138 struct ice_aqc_list_caps_elem *cap) 2139 { 2140 u32 number = LE32_TO_CPU(cap->number); 2141 2142 dev_p->num_funcs = ice_hweight32(number); 2143 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2144 dev_p->num_funcs); 2145 } 2146 2147 /** 2148 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2149 * @hw: pointer to the HW struct 2150 * @dev_p: pointer to device capabilities structure 2151 * @cap: capability element to parse 2152 * 2153 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2154 */ 2155 static void 2156 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2157 struct ice_aqc_list_caps_elem *cap) 2158 { 2159 u32 number = LE32_TO_CPU(cap->number); 2160 2161 dev_p->num_vsi_allocd_to_host = number; 2162 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2163 dev_p->num_vsi_allocd_to_host); 2164 } 2165 2166 /** 2167 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2168 * @hw: pointer to the HW struct 2169 * @dev_p: pointer to device capabilities structure 2170 * @cap: capability element to parse 2171 * 2172 * Parse ICE_AQC_CAPS_FD for device capabilities. 2173 */ 2174 static void 2175 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2176 struct ice_aqc_list_caps_elem *cap) 2177 { 2178 u32 number = LE32_TO_CPU(cap->number); 2179 2180 dev_p->num_flow_director_fltr = number; 2181 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2182 dev_p->num_flow_director_fltr); 2183 } 2184 2185 /** 2186 * ice_parse_dev_caps - Parse device capabilities 2187 * @hw: pointer to the HW struct 2188 * @dev_p: pointer to device capabilities structure 2189 * @buf: buffer containing the device capability records 2190 * @cap_count: the number of capabilities 2191 * 2192 * Helper device to parse device (0x000B) capabilities list. For 2193 * capabilities shared between device and function, this relies on 2194 * ice_parse_common_caps. 2195 * 2196 * Loop through the list of provided capabilities and extract the relevant 2197 * data into the device capabilities structured. 2198 */ 2199 static void 2200 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2201 void *buf, u32 cap_count) 2202 { 2203 struct ice_aqc_list_caps_elem *cap_resp; 2204 u32 i; 2205 2206 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2207 2208 ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 2209 2210 for (i = 0; i < cap_count; i++) { 2211 u16 cap = LE16_TO_CPU(cap_resp[i].cap); 2212 bool found; 2213 2214 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2215 &cap_resp[i], "dev caps"); 2216 2217 switch (cap) { 2218 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2219 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2220 break; 2221 case ICE_AQC_CAPS_VSI: 2222 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2223 break; 2224 case ICE_AQC_CAPS_FD: 2225 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2226 break; 2227 default: 2228 /* Don't list common capabilities as unknown */ 2229 if (!found) 2230 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2231 i, cap); 2232 break; 2233 } 2234 } 2235 2236 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2237 } 2238 2239 /** 2240 * ice_aq_list_caps - query function/device capabilities 2241 * @hw: pointer to the HW struct 2242 * @buf: a buffer to hold the capabilities 2243 * @buf_size: size of the buffer 2244 * @cap_count: if not NULL, set to the number of capabilities reported 2245 * @opc: capabilities type to discover, device or function 2246 * @cd: pointer to command details structure or NULL 2247 * 2248 * Get the function (0x000A) or device (0x000B) capabilities description from 2249 * firmware and store it in the buffer. 2250 * 2251 * If the cap_count pointer is not NULL, then it is set to the number of 2252 * capabilities firmware will report. Note that if the buffer size is too 2253 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2254 * cap_count will still be updated in this case. It is recommended that the 2255 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2256 * firmware could return) to avoid this. 2257 */ 2258 static enum ice_status 2259 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2260 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2261 { 2262 struct ice_aqc_list_caps *cmd; 2263 struct ice_aq_desc desc; 2264 enum ice_status status; 2265 2266 cmd = &desc.params.get_cap; 2267 2268 if (opc != ice_aqc_opc_list_func_caps && 2269 opc != ice_aqc_opc_list_dev_caps) 2270 return ICE_ERR_PARAM; 2271 2272 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2273 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2274 2275 if (cap_count) 2276 *cap_count = LE32_TO_CPU(cmd->count); 2277 2278 return status; 2279 } 2280 2281 /** 2282 * ice_discover_dev_caps - Read and extract device capabilities 2283 * @hw: pointer to the hardware structure 2284 * @dev_caps: pointer to device capabilities structure 2285 * 2286 * Read the device capabilities and extract them into the dev_caps structure 2287 * for later use. 2288 */ 2289 static enum ice_status 2290 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2291 { 2292 enum ice_status status; 2293 u32 cap_count = 0; 2294 void *cbuf; 2295 2296 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2297 if (!cbuf) 2298 return ICE_ERR_NO_MEMORY; 2299 2300 /* Although the driver doesn't know the number of capabilities the 2301 * device will return, we can simply send a 4KB buffer, the maximum 2302 * possible size that firmware can return. 2303 */ 2304 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2305 2306 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2307 ice_aqc_opc_list_dev_caps, NULL); 2308 if (!status) 2309 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2310 ice_free(hw, cbuf); 2311 2312 return status; 2313 } 2314 2315 /** 2316 * ice_discover_func_caps - Read and extract function capabilities 2317 * @hw: pointer to the hardware structure 2318 * @func_caps: pointer to function capabilities structure 2319 * 2320 * Read the function capabilities and extract them into the func_caps structure 2321 * for later use. 2322 */ 2323 static enum ice_status 2324 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2325 { 2326 enum ice_status status; 2327 u32 cap_count = 0; 2328 void *cbuf; 2329 2330 cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 2331 if (!cbuf) 2332 return ICE_ERR_NO_MEMORY; 2333 2334 /* Although the driver doesn't know the number of capabilities the 2335 * device will return, we can simply send a 4KB buffer, the maximum 2336 * possible size that firmware can return. 2337 */ 2338 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2339 2340 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2341 ice_aqc_opc_list_func_caps, NULL); 2342 if (!status) 2343 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2344 ice_free(hw, cbuf); 2345 2346 return status; 2347 } 2348 2349 /** 2350 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2351 * @hw: pointer to the hardware structure 2352 */ 2353 void ice_set_safe_mode_caps(struct ice_hw *hw) 2354 { 2355 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2356 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2357 struct ice_hw_common_caps cached_caps; 2358 u32 num_funcs; 2359 2360 /* cache some func_caps values that should be restored after memset */ 2361 cached_caps = func_caps->common_cap; 2362 2363 /* unset func capabilities */ 2364 memset(func_caps, 0, sizeof(*func_caps)); 2365 2366 #define ICE_RESTORE_FUNC_CAP(name) \ 2367 func_caps->common_cap.name = cached_caps.name 2368 2369 /* restore cached values */ 2370 ICE_RESTORE_FUNC_CAP(valid_functions); 2371 ICE_RESTORE_FUNC_CAP(txq_first_id); 2372 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2373 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2374 ICE_RESTORE_FUNC_CAP(max_mtu); 2375 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2376 2377 /* one Tx and one Rx queue in safe mode */ 2378 func_caps->common_cap.num_rxq = 1; 2379 func_caps->common_cap.num_txq = 1; 2380 2381 /* two MSIX vectors, one for traffic and one for misc causes */ 2382 func_caps->common_cap.num_msix_vectors = 2; 2383 func_caps->guar_num_vsi = 1; 2384 2385 /* cache some dev_caps values that should be restored after memset */ 2386 cached_caps = dev_caps->common_cap; 2387 num_funcs = dev_caps->num_funcs; 2388 2389 /* unset dev capabilities */ 2390 memset(dev_caps, 0, sizeof(*dev_caps)); 2391 2392 #define ICE_RESTORE_DEV_CAP(name) \ 2393 dev_caps->common_cap.name = cached_caps.name 2394 2395 /* restore cached values */ 2396 ICE_RESTORE_DEV_CAP(valid_functions); 2397 ICE_RESTORE_DEV_CAP(txq_first_id); 2398 ICE_RESTORE_DEV_CAP(rxq_first_id); 2399 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2400 ICE_RESTORE_DEV_CAP(max_mtu); 2401 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2402 dev_caps->num_funcs = num_funcs; 2403 2404 /* one Tx and one Rx queue per function in safe mode */ 2405 dev_caps->common_cap.num_rxq = num_funcs; 2406 dev_caps->common_cap.num_txq = num_funcs; 2407 2408 /* two MSIX vectors per function */ 2409 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2410 } 2411 2412 /** 2413 * ice_get_caps - get info about the HW 2414 * @hw: pointer to the hardware structure 2415 */ 2416 enum ice_status ice_get_caps(struct ice_hw *hw) 2417 { 2418 enum ice_status status; 2419 2420 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2421 if (status) 2422 return status; 2423 2424 return ice_discover_func_caps(hw, &hw->func_caps); 2425 } 2426 2427 /** 2428 * ice_aq_manage_mac_write - manage MAC address write command 2429 * @hw: pointer to the HW struct 2430 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2431 * @flags: flags to control write behavior 2432 * @cd: pointer to command details structure or NULL 2433 * 2434 * This function is used to write MAC address to the NVM (0x0108). 2435 */ 2436 enum ice_status 2437 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2438 struct ice_sq_cd *cd) 2439 { 2440 struct ice_aqc_manage_mac_write *cmd; 2441 struct ice_aq_desc desc; 2442 2443 cmd = &desc.params.mac_write; 2444 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2445 2446 cmd->flags = flags; 2447 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 2448 2449 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2450 } 2451 2452 /** 2453 * ice_aq_clear_pxe_mode 2454 * @hw: pointer to the HW struct 2455 * 2456 * Tell the firmware that the driver is taking over from PXE (0x0110). 2457 */ 2458 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2459 { 2460 struct ice_aq_desc desc; 2461 2462 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2463 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2464 2465 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2466 } 2467 2468 /** 2469 * ice_clear_pxe_mode - clear pxe operations mode 2470 * @hw: pointer to the HW struct 2471 * 2472 * Make sure all PXE mode settings are cleared, including things 2473 * like descriptor fetch/write-back mode. 2474 */ 2475 void ice_clear_pxe_mode(struct ice_hw *hw) 2476 { 2477 if (ice_check_sq_alive(hw, &hw->adminq)) 2478 ice_aq_clear_pxe_mode(hw); 2479 } 2480 2481 /** 2482 * ice_aq_set_port_params - set physical port parameters. 2483 * @pi: pointer to the port info struct 2484 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 2485 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 2486 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 2487 * @double_vlan: if set double VLAN is enabled 2488 * @cd: pointer to command details structure or NULL 2489 * 2490 * Set Physical port parameters (0x0203) 2491 */ 2492 enum ice_status 2493 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 2494 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 2495 struct ice_sq_cd *cd) 2496 2497 { 2498 struct ice_aqc_set_port_params *cmd; 2499 struct ice_hw *hw = pi->hw; 2500 struct ice_aq_desc desc; 2501 u16 cmd_flags = 0; 2502 2503 cmd = &desc.params.set_port_params; 2504 2505 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2506 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 2507 if (save_bad_pac) 2508 cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; 2509 if (pad_short_pac) 2510 cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; 2511 if (double_vlan) 2512 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2513 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 2514 2515 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2516 } 2517 2518 /** 2519 * ice_get_link_speed_based_on_phy_type - returns link speed 2520 * @phy_type_low: lower part of phy_type 2521 * @phy_type_high: higher part of phy_type 2522 * 2523 * This helper function will convert an entry in PHY type structure 2524 * [phy_type_low, phy_type_high] to its corresponding link speed. 2525 * Note: In the structure of [phy_type_low, phy_type_high], there should 2526 * be one bit set, as this function will convert one PHY type to its 2527 * speed. 2528 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2529 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2530 */ 2531 static u16 2532 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2533 { 2534 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2535 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2536 2537 switch (phy_type_low) { 2538 case ICE_PHY_TYPE_LOW_100BASE_TX: 2539 case ICE_PHY_TYPE_LOW_100M_SGMII: 2540 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2541 break; 2542 case ICE_PHY_TYPE_LOW_1000BASE_T: 2543 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2544 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2545 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2546 case ICE_PHY_TYPE_LOW_1G_SGMII: 2547 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2548 break; 2549 case ICE_PHY_TYPE_LOW_2500BASE_T: 2550 case ICE_PHY_TYPE_LOW_2500BASE_X: 2551 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2552 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2553 break; 2554 case ICE_PHY_TYPE_LOW_5GBASE_T: 2555 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2556 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2557 break; 2558 case ICE_PHY_TYPE_LOW_10GBASE_T: 2559 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2560 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2561 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2562 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2563 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2564 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2565 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2566 break; 2567 case ICE_PHY_TYPE_LOW_25GBASE_T: 2568 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2569 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2570 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2571 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2572 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2573 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2574 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2575 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2576 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2577 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2578 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2579 break; 2580 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2581 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2582 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2583 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2584 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2585 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2586 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2587 break; 2588 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2589 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2590 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2591 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2592 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2593 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2594 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2595 case ICE_PHY_TYPE_LOW_50G_AUI2: 2596 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2597 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2598 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2599 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2600 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2601 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2602 case ICE_PHY_TYPE_LOW_50G_AUI1: 2603 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2604 break; 2605 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2606 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2607 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2608 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2609 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2610 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2611 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2612 case ICE_PHY_TYPE_LOW_100G_AUI4: 2613 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2614 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2615 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2616 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2617 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2618 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2619 break; 2620 default: 2621 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2622 break; 2623 } 2624 2625 switch (phy_type_high) { 2626 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2627 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2628 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2629 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2630 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2631 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2632 break; 2633 default: 2634 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2635 break; 2636 } 2637 2638 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2639 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2640 return ICE_AQ_LINK_SPEED_UNKNOWN; 2641 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2642 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2643 return ICE_AQ_LINK_SPEED_UNKNOWN; 2644 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2645 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2646 return speed_phy_type_low; 2647 else 2648 return speed_phy_type_high; 2649 } 2650 2651 /** 2652 * ice_update_phy_type 2653 * @phy_type_low: pointer to the lower part of phy_type 2654 * @phy_type_high: pointer to the higher part of phy_type 2655 * @link_speeds_bitmap: targeted link speeds bitmap 2656 * 2657 * Note: For the link_speeds_bitmap structure, you can check it at 2658 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2659 * link_speeds_bitmap include multiple speeds. 2660 * 2661 * Each entry in this [phy_type_low, phy_type_high] structure will 2662 * present a certain link speed. This helper function will turn on bits 2663 * in [phy_type_low, phy_type_high] structure based on the value of 2664 * link_speeds_bitmap input parameter. 2665 */ 2666 void 2667 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2668 u16 link_speeds_bitmap) 2669 { 2670 u64 pt_high; 2671 u64 pt_low; 2672 int index; 2673 u16 speed; 2674 2675 /* We first check with low part of phy_type */ 2676 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2677 pt_low = BIT_ULL(index); 2678 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2679 2680 if (link_speeds_bitmap & speed) 2681 *phy_type_low |= BIT_ULL(index); 2682 } 2683 2684 /* We then check with high part of phy_type */ 2685 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2686 pt_high = BIT_ULL(index); 2687 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2688 2689 if (link_speeds_bitmap & speed) 2690 *phy_type_high |= BIT_ULL(index); 2691 } 2692 } 2693 2694 /** 2695 * ice_aq_set_phy_cfg 2696 * @hw: pointer to the HW struct 2697 * @pi: port info structure of the interested logical port 2698 * @cfg: structure with PHY configuration data to be set 2699 * @cd: pointer to command details structure or NULL 2700 * 2701 * Set the various PHY configuration parameters supported on the Port. 2702 * One or more of the Set PHY config parameters may be ignored in an MFP 2703 * mode as the PF may not have the privilege to set some of the PHY Config 2704 * parameters. This status will be indicated by the command response (0x0601). 2705 */ 2706 enum ice_status 2707 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2708 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2709 { 2710 struct ice_aq_desc desc; 2711 enum ice_status status; 2712 2713 if (!cfg) 2714 return ICE_ERR_PARAM; 2715 2716 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2717 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2718 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2719 cfg->caps); 2720 2721 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2722 } 2723 2724 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2725 desc.params.set_phy.lport_num = pi->lport; 2726 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 2727 2728 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2729 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2730 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 2731 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2732 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 2733 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2734 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2735 cfg->low_power_ctrl_an); 2736 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2737 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2738 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2739 cfg->link_fec_opt); 2740 2741 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2742 2743 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2744 status = ICE_SUCCESS; 2745 2746 if (!status) 2747 pi->phy.curr_user_phy_cfg = *cfg; 2748 2749 return status; 2750 } 2751 2752 /** 2753 * ice_update_link_info - update status of the HW network link 2754 * @pi: port info structure of the interested logical port 2755 */ 2756 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2757 { 2758 struct ice_link_status *li; 2759 enum ice_status status; 2760 2761 if (!pi) 2762 return ICE_ERR_PARAM; 2763 2764 li = &pi->phy.link_info; 2765 2766 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2767 if (status) 2768 return status; 2769 2770 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2771 struct ice_aqc_get_phy_caps_data *pcaps; 2772 struct ice_hw *hw; 2773 2774 hw = pi->hw; 2775 pcaps = (struct ice_aqc_get_phy_caps_data *) 2776 ice_malloc(hw, sizeof(*pcaps)); 2777 if (!pcaps) 2778 return ICE_ERR_NO_MEMORY; 2779 2780 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2781 pcaps, NULL); 2782 2783 if (status == ICE_SUCCESS) 2784 ice_memcpy(li->module_type, &pcaps->module_type, 2785 sizeof(li->module_type), 2786 ICE_NONDMA_TO_NONDMA); 2787 2788 ice_free(hw, pcaps); 2789 } 2790 2791 return status; 2792 } 2793 2794 /** 2795 * ice_cache_phy_user_req 2796 * @pi: port information structure 2797 * @cache_data: PHY logging data 2798 * @cache_mode: PHY logging mode 2799 * 2800 * Log the user request on (FC, FEC, SPEED) for later user. 2801 */ 2802 static void 2803 ice_cache_phy_user_req(struct ice_port_info *pi, 2804 struct ice_phy_cache_mode_data cache_data, 2805 enum ice_phy_cache_mode cache_mode) 2806 { 2807 if (!pi) 2808 return; 2809 2810 switch (cache_mode) { 2811 case ICE_FC_MODE: 2812 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2813 break; 2814 case ICE_SPEED_MODE: 2815 pi->phy.curr_user_speed_req = 2816 cache_data.data.curr_user_speed_req; 2817 break; 2818 case ICE_FEC_MODE: 2819 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2820 break; 2821 default: 2822 break; 2823 } 2824 } 2825 2826 /** 2827 * ice_caps_to_fc_mode 2828 * @caps: PHY capabilities 2829 * 2830 * Convert PHY FC capabilities to ice FC mode 2831 */ 2832 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2833 { 2834 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2835 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2836 return ICE_FC_FULL; 2837 2838 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2839 return ICE_FC_TX_PAUSE; 2840 2841 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2842 return ICE_FC_RX_PAUSE; 2843 2844 return ICE_FC_NONE; 2845 } 2846 2847 /** 2848 * ice_caps_to_fec_mode 2849 * @caps: PHY capabilities 2850 * @fec_options: Link FEC options 2851 * 2852 * Convert PHY FEC capabilities to ice FEC mode 2853 */ 2854 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2855 { 2856 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2857 return ICE_FEC_AUTO; 2858 2859 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2860 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2861 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2862 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2863 return ICE_FEC_BASER; 2864 2865 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2866 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2867 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2868 return ICE_FEC_RS; 2869 2870 return ICE_FEC_NONE; 2871 } 2872 2873 /** 2874 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2875 * @pi: port information structure 2876 * @cfg: PHY configuration data to set FC mode 2877 * @req_mode: FC mode to configure 2878 */ 2879 static enum ice_status 2880 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2881 enum ice_fc_mode req_mode) 2882 { 2883 struct ice_phy_cache_mode_data cache_data; 2884 u8 pause_mask = 0x0; 2885 2886 if (!pi || !cfg) 2887 return ICE_ERR_BAD_PTR; 2888 2889 switch (req_mode) { 2890 case ICE_FC_AUTO: 2891 { 2892 struct ice_aqc_get_phy_caps_data *pcaps; 2893 enum ice_status status; 2894 2895 pcaps = (struct ice_aqc_get_phy_caps_data *) 2896 ice_malloc(pi->hw, sizeof(*pcaps)); 2897 if (!pcaps) 2898 return ICE_ERR_NO_MEMORY; 2899 2900 /* Query the value of FC that both the NIC and attached media 2901 * can do. 2902 */ 2903 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2904 pcaps, NULL); 2905 if (status) { 2906 ice_free(pi->hw, pcaps); 2907 return status; 2908 } 2909 2910 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2911 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2912 2913 ice_free(pi->hw, pcaps); 2914 break; 2915 } 2916 case ICE_FC_FULL: 2917 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2918 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2919 break; 2920 case ICE_FC_RX_PAUSE: 2921 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2922 break; 2923 case ICE_FC_TX_PAUSE: 2924 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2925 break; 2926 default: 2927 break; 2928 } 2929 2930 /* clear the old pause settings */ 2931 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2932 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2933 2934 /* set the new capabilities */ 2935 cfg->caps |= pause_mask; 2936 2937 /* Cache user FC request */ 2938 cache_data.data.curr_user_fc_req = req_mode; 2939 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2940 2941 return ICE_SUCCESS; 2942 } 2943 2944 /** 2945 * ice_set_fc 2946 * @pi: port information structure 2947 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2948 * @ena_auto_link_update: enable automatic link update 2949 * 2950 * Set the requested flow control mode. 2951 */ 2952 enum ice_status 2953 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2954 { 2955 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2956 struct ice_aqc_get_phy_caps_data *pcaps; 2957 enum ice_status status; 2958 struct ice_hw *hw; 2959 2960 if (!pi || !aq_failures) 2961 return ICE_ERR_BAD_PTR; 2962 2963 *aq_failures = 0; 2964 hw = pi->hw; 2965 2966 pcaps = (struct ice_aqc_get_phy_caps_data *) 2967 ice_malloc(hw, sizeof(*pcaps)); 2968 if (!pcaps) 2969 return ICE_ERR_NO_MEMORY; 2970 2971 /* Get the current PHY config */ 2972 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 2973 pcaps, NULL); 2974 2975 if (status) { 2976 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2977 goto out; 2978 } 2979 2980 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2981 2982 /* Configure the set PHY data */ 2983 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2984 if (status) { 2985 if (status != ICE_ERR_BAD_PTR) 2986 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2987 2988 goto out; 2989 } 2990 2991 /* If the capabilities have changed, then set the new config */ 2992 if (cfg.caps != pcaps->caps) { 2993 int retry_count, retry_max = 10; 2994 2995 /* Auto restart link so settings take effect */ 2996 if (ena_auto_link_update) 2997 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2998 2999 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3000 if (status) { 3001 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3002 goto out; 3003 } 3004 3005 /* Update the link info 3006 * It sometimes takes a really long time for link to 3007 * come back from the atomic reset. Thus, we wait a 3008 * little bit. 3009 */ 3010 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3011 status = ice_update_link_info(pi); 3012 3013 if (status == ICE_SUCCESS) 3014 break; 3015 3016 ice_msec_delay(100, true); 3017 } 3018 3019 if (status) 3020 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3021 } 3022 3023 out: 3024 ice_free(hw, pcaps); 3025 return status; 3026 } 3027 3028 /** 3029 * ice_phy_caps_equals_cfg 3030 * @phy_caps: PHY capabilities 3031 * @phy_cfg: PHY configuration 3032 * 3033 * Helper function to determine if PHY capabilities matches PHY 3034 * configuration 3035 */ 3036 bool 3037 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3038 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3039 { 3040 u8 caps_mask, cfg_mask; 3041 3042 if (!phy_caps || !phy_cfg) 3043 return false; 3044 3045 /* These bits are not common between capabilities and configuration. 3046 * Do not use them to determine equality. 3047 */ 3048 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3049 ICE_AQC_PHY_EN_MOD_QUAL); 3050 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3051 3052 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3053 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3054 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3055 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3056 phy_caps->eee_cap != phy_cfg->eee_cap || 3057 phy_caps->eeer_value != phy_cfg->eeer_value || 3058 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3059 return false; 3060 3061 return true; 3062 } 3063 3064 /** 3065 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3066 * @pi: port information structure 3067 * @caps: PHY ability structure to copy date from 3068 * @cfg: PHY configuration structure to copy data to 3069 * 3070 * Helper function to copy AQC PHY get ability data to PHY set configuration 3071 * data structure 3072 */ 3073 void 3074 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3075 struct ice_aqc_get_phy_caps_data *caps, 3076 struct ice_aqc_set_phy_cfg_data *cfg) 3077 { 3078 if (!pi || !caps || !cfg) 3079 return; 3080 3081 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 3082 cfg->phy_type_low = caps->phy_type_low; 3083 cfg->phy_type_high = caps->phy_type_high; 3084 cfg->caps = caps->caps; 3085 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3086 cfg->eee_cap = caps->eee_cap; 3087 cfg->eeer_value = caps->eeer_value; 3088 cfg->link_fec_opt = caps->link_fec_options; 3089 cfg->module_compliance_enforcement = 3090 caps->module_compliance_enforcement; 3091 } 3092 3093 /** 3094 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3095 * @pi: port information structure 3096 * @cfg: PHY configuration data to set FEC mode 3097 * @fec: FEC mode to configure 3098 */ 3099 enum ice_status 3100 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3101 enum ice_fec_mode fec) 3102 { 3103 struct ice_aqc_get_phy_caps_data *pcaps; 3104 enum ice_status status = ICE_SUCCESS; 3105 struct ice_hw *hw; 3106 3107 if (!pi || !cfg) 3108 return ICE_ERR_BAD_PTR; 3109 3110 hw = pi->hw; 3111 3112 pcaps = (struct ice_aqc_get_phy_caps_data *) 3113 ice_malloc(hw, sizeof(*pcaps)); 3114 if (!pcaps) 3115 return ICE_ERR_NO_MEMORY; 3116 3117 status = ice_aq_get_phy_caps(pi, false, 3118 (ice_fw_supports_report_dflt_cfg(hw) ? 3119 ICE_AQC_REPORT_DFLT_CFG : 3120 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3121 3122 if (status) 3123 goto out; 3124 3125 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 3126 cfg->link_fec_opt = pcaps->link_fec_options; 3127 3128 switch (fec) { 3129 case ICE_FEC_BASER: 3130 /* Clear RS bits, and AND BASE-R ability 3131 * bits and OR request bits. 3132 */ 3133 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3134 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3135 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3136 ICE_AQC_PHY_FEC_25G_KR_REQ; 3137 break; 3138 case ICE_FEC_RS: 3139 /* Clear BASE-R bits, and AND RS ability 3140 * bits and OR request bits. 3141 */ 3142 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3143 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3144 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3145 break; 3146 case ICE_FEC_NONE: 3147 /* Clear all FEC option bits. */ 3148 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3149 break; 3150 case ICE_FEC_AUTO: 3151 /* AND auto FEC bit, and all caps bits. */ 3152 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3153 cfg->link_fec_opt |= pcaps->link_fec_options; 3154 break; 3155 default: 3156 status = ICE_ERR_PARAM; 3157 break; 3158 } 3159 3160 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && 3161 !ice_fw_supports_report_dflt_cfg(pi->hw)) { 3162 struct ice_link_default_override_tlv tlv; 3163 3164 if (ice_get_link_default_override(&tlv, pi)) 3165 goto out; 3166 3167 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3168 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3169 cfg->link_fec_opt = tlv.fec_options; 3170 } 3171 3172 out: 3173 ice_free(hw, pcaps); 3174 3175 return status; 3176 } 3177 3178 /** 3179 * ice_get_link_status - get status of the HW network link 3180 * @pi: port information structure 3181 * @link_up: pointer to bool (true/false = linkup/linkdown) 3182 * 3183 * Variable link_up is true if link is up, false if link is down. 3184 * The variable link_up is invalid if status is non zero. As a 3185 * result of this call, link status reporting becomes enabled 3186 */ 3187 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3188 { 3189 struct ice_phy_info *phy_info; 3190 enum ice_status status = ICE_SUCCESS; 3191 3192 if (!pi || !link_up) 3193 return ICE_ERR_PARAM; 3194 3195 phy_info = &pi->phy; 3196 3197 if (phy_info->get_link_info) { 3198 status = ice_update_link_info(pi); 3199 3200 if (status) 3201 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3202 status); 3203 } 3204 3205 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3206 3207 return status; 3208 } 3209 3210 /** 3211 * ice_aq_set_link_restart_an 3212 * @pi: pointer to the port information structure 3213 * @ena_link: if true: enable link, if false: disable link 3214 * @cd: pointer to command details structure or NULL 3215 * 3216 * Sets up the link and restarts the Auto-Negotiation over the link. 3217 */ 3218 enum ice_status 3219 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3220 struct ice_sq_cd *cd) 3221 { 3222 struct ice_aqc_restart_an *cmd; 3223 struct ice_aq_desc desc; 3224 3225 cmd = &desc.params.restart_an; 3226 3227 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3228 3229 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3230 cmd->lport_num = pi->lport; 3231 if (ena_link) 3232 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3233 else 3234 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3235 3236 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3237 } 3238 3239 /** 3240 * ice_aq_set_event_mask 3241 * @hw: pointer to the HW struct 3242 * @port_num: port number of the physical function 3243 * @mask: event mask to be set 3244 * @cd: pointer to command details structure or NULL 3245 * 3246 * Set event mask (0x0613) 3247 */ 3248 enum ice_status 3249 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3250 struct ice_sq_cd *cd) 3251 { 3252 struct ice_aqc_set_event_mask *cmd; 3253 struct ice_aq_desc desc; 3254 3255 cmd = &desc.params.set_event_mask; 3256 3257 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3258 3259 cmd->lport_num = port_num; 3260 3261 cmd->event_mask = CPU_TO_LE16(mask); 3262 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3263 } 3264 3265 /** 3266 * ice_aq_set_mac_loopback 3267 * @hw: pointer to the HW struct 3268 * @ena_lpbk: Enable or Disable loopback 3269 * @cd: pointer to command details structure or NULL 3270 * 3271 * Enable/disable loopback on a given port 3272 */ 3273 enum ice_status 3274 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3275 { 3276 struct ice_aqc_set_mac_lb *cmd; 3277 struct ice_aq_desc desc; 3278 3279 cmd = &desc.params.set_mac_lb; 3280 3281 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3282 if (ena_lpbk) 3283 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3284 3285 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3286 } 3287 3288 /** 3289 * ice_aq_set_port_id_led 3290 * @pi: pointer to the port information 3291 * @is_orig_mode: is this LED set to original mode (by the net-list) 3292 * @cd: pointer to command details structure or NULL 3293 * 3294 * Set LED value for the given port (0x06e9) 3295 */ 3296 enum ice_status 3297 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3298 struct ice_sq_cd *cd) 3299 { 3300 struct ice_aqc_set_port_id_led *cmd; 3301 struct ice_hw *hw = pi->hw; 3302 struct ice_aq_desc desc; 3303 3304 cmd = &desc.params.set_port_id_led; 3305 3306 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3307 3308 if (is_orig_mode) 3309 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3310 else 3311 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3312 3313 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3314 } 3315 3316 /** 3317 * ice_aq_sff_eeprom 3318 * @hw: pointer to the HW struct 3319 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3320 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3321 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3322 * @page: QSFP page 3323 * @set_page: set or ignore the page 3324 * @data: pointer to data buffer to be read/written to the I2C device. 3325 * @length: 1-16 for read, 1 for write. 3326 * @write: 0 read, 1 for write. 3327 * @cd: pointer to command details structure or NULL 3328 * 3329 * Read/Write SFF EEPROM (0x06EE) 3330 */ 3331 enum ice_status 3332 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3333 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3334 bool write, struct ice_sq_cd *cd) 3335 { 3336 struct ice_aqc_sff_eeprom *cmd; 3337 struct ice_aq_desc desc; 3338 enum ice_status status; 3339 3340 if (!data || (mem_addr & 0xff00)) 3341 return ICE_ERR_PARAM; 3342 3343 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3344 cmd = &desc.params.read_write_sff_param; 3345 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 3346 cmd->lport_num = (u8)(lport & 0xff); 3347 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3348 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 3349 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3350 ((set_page << 3351 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3352 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3353 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 3354 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3355 if (write) 3356 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 3357 3358 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3359 return status; 3360 } 3361 3362 /** 3363 * __ice_aq_get_set_rss_lut 3364 * @hw: pointer to the hardware structure 3365 * @params: RSS LUT parameters 3366 * @set: set true to set the table, false to get the table 3367 * 3368 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3369 */ 3370 static enum ice_status 3371 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3372 { 3373 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3374 struct ice_aqc_get_set_rss_lut *cmd_resp; 3375 struct ice_aq_desc desc; 3376 enum ice_status status; 3377 u8 *lut; 3378 3379 if (!params) 3380 return ICE_ERR_PARAM; 3381 3382 vsi_handle = params->vsi_handle; 3383 lut = params->lut; 3384 3385 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3386 return ICE_ERR_PARAM; 3387 3388 lut_size = params->lut_size; 3389 lut_type = params->lut_type; 3390 glob_lut_idx = params->global_lut_id; 3391 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3392 3393 cmd_resp = &desc.params.get_set_rss_lut; 3394 3395 if (set) { 3396 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3397 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3398 } else { 3399 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3400 } 3401 3402 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3403 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3404 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3405 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3406 3407 switch (lut_type) { 3408 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3409 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3410 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3411 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3412 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3413 break; 3414 default: 3415 status = ICE_ERR_PARAM; 3416 goto ice_aq_get_set_rss_lut_exit; 3417 } 3418 3419 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3420 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3421 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3422 3423 if (!set) 3424 goto ice_aq_get_set_rss_lut_send; 3425 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3426 if (!set) 3427 goto ice_aq_get_set_rss_lut_send; 3428 } else { 3429 goto ice_aq_get_set_rss_lut_send; 3430 } 3431 3432 /* LUT size is only valid for Global and PF table types */ 3433 switch (lut_size) { 3434 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3435 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 3436 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3437 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3438 break; 3439 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3440 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3441 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3442 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3443 break; 3444 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3445 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3446 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3447 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3448 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3449 break; 3450 } 3451 /* fall-through */ 3452 default: 3453 status = ICE_ERR_PARAM; 3454 goto ice_aq_get_set_rss_lut_exit; 3455 } 3456 3457 ice_aq_get_set_rss_lut_send: 3458 cmd_resp->flags = CPU_TO_LE16(flags); 3459 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3460 3461 ice_aq_get_set_rss_lut_exit: 3462 return status; 3463 } 3464 3465 /** 3466 * ice_aq_get_rss_lut 3467 * @hw: pointer to the hardware structure 3468 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3469 * 3470 * get the RSS lookup table, PF or VSI type 3471 */ 3472 enum ice_status 3473 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3474 { 3475 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3476 } 3477 3478 /** 3479 * ice_aq_set_rss_lut 3480 * @hw: pointer to the hardware structure 3481 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3482 * 3483 * set the RSS lookup table, PF or VSI type 3484 */ 3485 enum ice_status 3486 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3487 { 3488 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3489 } 3490 3491 /** 3492 * __ice_aq_get_set_rss_key 3493 * @hw: pointer to the HW struct 3494 * @vsi_id: VSI FW index 3495 * @key: pointer to key info struct 3496 * @set: set true to set the key, false to get the key 3497 * 3498 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3499 */ 3500 static enum 3501 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3502 struct ice_aqc_get_set_rss_keys *key, 3503 bool set) 3504 { 3505 struct ice_aqc_get_set_rss_key *cmd_resp; 3506 u16 key_size = sizeof(*key); 3507 struct ice_aq_desc desc; 3508 3509 cmd_resp = &desc.params.get_set_rss_key; 3510 3511 if (set) { 3512 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3513 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3514 } else { 3515 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3516 } 3517 3518 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 3519 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3520 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3521 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3522 3523 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3524 } 3525 3526 /** 3527 * ice_aq_get_rss_key 3528 * @hw: pointer to the HW struct 3529 * @vsi_handle: software VSI handle 3530 * @key: pointer to key info struct 3531 * 3532 * get the RSS key per VSI 3533 */ 3534 enum ice_status 3535 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3536 struct ice_aqc_get_set_rss_keys *key) 3537 { 3538 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3539 return ICE_ERR_PARAM; 3540 3541 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3542 key, false); 3543 } 3544 3545 /** 3546 * ice_aq_set_rss_key 3547 * @hw: pointer to the HW struct 3548 * @vsi_handle: software VSI handle 3549 * @keys: pointer to key info struct 3550 * 3551 * set the RSS key per VSI 3552 */ 3553 enum ice_status 3554 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3555 struct ice_aqc_get_set_rss_keys *keys) 3556 { 3557 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3558 return ICE_ERR_PARAM; 3559 3560 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3561 keys, true); 3562 } 3563 3564 /** 3565 * ice_aq_add_lan_txq 3566 * @hw: pointer to the hardware structure 3567 * @num_qgrps: Number of added queue groups 3568 * @qg_list: list of queue groups to be added 3569 * @buf_size: size of buffer for indirect command 3570 * @cd: pointer to command details structure or NULL 3571 * 3572 * Add Tx LAN queue (0x0C30) 3573 * 3574 * NOTE: 3575 * Prior to calling add Tx LAN queue: 3576 * Initialize the following as part of the Tx queue context: 3577 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3578 * Cache profile and Packet shaper profile. 3579 * 3580 * After add Tx LAN queue AQ command is completed: 3581 * Interrupts should be associated with specific queues, 3582 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3583 * flow. 3584 */ 3585 enum ice_status 3586 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3587 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3588 struct ice_sq_cd *cd) 3589 { 3590 struct ice_aqc_add_tx_qgrp *list; 3591 struct ice_aqc_add_txqs *cmd; 3592 struct ice_aq_desc desc; 3593 u16 i, sum_size = 0; 3594 3595 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3596 3597 cmd = &desc.params.add_txqs; 3598 3599 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3600 3601 if (!qg_list) 3602 return ICE_ERR_PARAM; 3603 3604 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3605 return ICE_ERR_PARAM; 3606 3607 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3608 sum_size += ice_struct_size(list, txqs, list->num_txqs); 3609 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3610 list->num_txqs); 3611 } 3612 3613 if (buf_size != sum_size) 3614 return ICE_ERR_PARAM; 3615 3616 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3617 3618 cmd->num_qgrps = num_qgrps; 3619 3620 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3621 } 3622 3623 /** 3624 * ice_aq_dis_lan_txq 3625 * @hw: pointer to the hardware structure 3626 * @num_qgrps: number of groups in the list 3627 * @qg_list: the list of groups to disable 3628 * @buf_size: the total size of the qg_list buffer in bytes 3629 * @rst_src: if called due to reset, specifies the reset source 3630 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3631 * @cd: pointer to command details structure or NULL 3632 * 3633 * Disable LAN Tx queue (0x0C31) 3634 */ 3635 static enum ice_status 3636 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3637 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3638 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3639 struct ice_sq_cd *cd) 3640 { 3641 struct ice_aqc_dis_txq_item *item; 3642 struct ice_aqc_dis_txqs *cmd; 3643 struct ice_aq_desc desc; 3644 enum ice_status status; 3645 u16 i, sz = 0; 3646 3647 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 3648 cmd = &desc.params.dis_txqs; 3649 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3650 3651 /* qg_list can be NULL only in VM/VF reset flow */ 3652 if (!qg_list && !rst_src) 3653 return ICE_ERR_PARAM; 3654 3655 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3656 return ICE_ERR_PARAM; 3657 3658 cmd->num_entries = num_qgrps; 3659 3660 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3661 ICE_AQC_Q_DIS_TIMEOUT_M); 3662 3663 switch (rst_src) { 3664 case ICE_VM_RESET: 3665 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3666 cmd->vmvf_and_timeout |= 3667 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3668 break; 3669 case ICE_NO_RESET: 3670 default: 3671 break; 3672 } 3673 3674 /* flush pipe on time out */ 3675 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3676 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3677 if (!qg_list) 3678 goto do_aq; 3679 3680 /* set RD bit to indicate that command buffer is provided by the driver 3681 * and it needs to be read by the firmware 3682 */ 3683 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3684 3685 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3686 u16 item_size = ice_struct_size(item, q_id, item->num_qs); 3687 3688 /* If the num of queues is even, add 2 bytes of padding */ 3689 if ((item->num_qs % 2) == 0) 3690 item_size += 2; 3691 3692 sz += item_size; 3693 3694 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3695 } 3696 3697 if (buf_size != sz) 3698 return ICE_ERR_PARAM; 3699 3700 do_aq: 3701 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3702 if (status) { 3703 if (!qg_list) 3704 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3705 vmvf_num, hw->adminq.sq_last_status); 3706 else 3707 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3708 LE16_TO_CPU(qg_list[0].q_id[0]), 3709 hw->adminq.sq_last_status); 3710 } 3711 return status; 3712 } 3713 3714 /** 3715 * ice_aq_move_recfg_lan_txq 3716 * @hw: pointer to the hardware structure 3717 * @num_qs: number of queues to move/reconfigure 3718 * @is_move: true if this operation involves node movement 3719 * @is_tc_change: true if this operation involves a TC change 3720 * @subseq_call: true if this operation is a subsequent call 3721 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 3722 * @timeout: timeout in units of 100 usec (valid values 0-50) 3723 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 3724 * @buf: struct containing src/dest TEID and per-queue info 3725 * @buf_size: size of buffer for indirect command 3726 * @txqs_moved: out param, number of queues successfully moved 3727 * @cd: pointer to command details structure or NULL 3728 * 3729 * Move / Reconfigure Tx LAN queues (0x0C32) 3730 */ 3731 enum ice_status 3732 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 3733 bool is_tc_change, bool subseq_call, bool flush_pipe, 3734 u8 timeout, u32 *blocked_cgds, 3735 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 3736 u8 *txqs_moved, struct ice_sq_cd *cd) 3737 { 3738 struct ice_aqc_move_txqs *cmd; 3739 struct ice_aq_desc desc; 3740 enum ice_status status; 3741 3742 cmd = &desc.params.move_txqs; 3743 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 3744 3745 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 3746 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 3747 return ICE_ERR_PARAM; 3748 3749 if (is_tc_change && !flush_pipe && !blocked_cgds) 3750 return ICE_ERR_PARAM; 3751 3752 if (!is_move && !is_tc_change) 3753 return ICE_ERR_PARAM; 3754 3755 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 3756 3757 if (is_move) 3758 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 3759 3760 if (is_tc_change) 3761 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 3762 3763 if (subseq_call) 3764 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 3765 3766 if (flush_pipe) 3767 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 3768 3769 cmd->num_qs = num_qs; 3770 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 3771 ICE_AQC_Q_CMD_TIMEOUT_M); 3772 3773 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3774 3775 if (!status && txqs_moved) 3776 *txqs_moved = cmd->num_qs; 3777 3778 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 3779 is_tc_change && !flush_pipe) 3780 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 3781 3782 return status; 3783 } 3784 3785 /* End of FW Admin Queue command wrappers */ 3786 3787 /** 3788 * ice_write_byte - write a byte to a packed context structure 3789 * @src_ctx: the context structure to read from 3790 * @dest_ctx: the context to be written to 3791 * @ce_info: a description of the struct to be filled 3792 */ 3793 static void 3794 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3795 { 3796 u8 src_byte, dest_byte, mask; 3797 u8 *from, *dest; 3798 u16 shift_width; 3799 3800 /* copy from the next struct field */ 3801 from = src_ctx + ce_info->offset; 3802 3803 /* prepare the bits and mask */ 3804 shift_width = ce_info->lsb % 8; 3805 mask = (u8)(BIT(ce_info->width) - 1); 3806 3807 src_byte = *from; 3808 src_byte &= mask; 3809 3810 /* shift to correct alignment */ 3811 mask <<= shift_width; 3812 src_byte <<= shift_width; 3813 3814 /* get the current bits from the target bit string */ 3815 dest = dest_ctx + (ce_info->lsb / 8); 3816 3817 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 3818 3819 dest_byte &= ~mask; /* get the bits not changing */ 3820 dest_byte |= src_byte; /* add in the new bits */ 3821 3822 /* put it all back */ 3823 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 3824 } 3825 3826 /** 3827 * ice_write_word - write a word to a packed context structure 3828 * @src_ctx: the context structure to read from 3829 * @dest_ctx: the context to be written to 3830 * @ce_info: a description of the struct to be filled 3831 */ 3832 static void 3833 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3834 { 3835 u16 src_word, mask; 3836 __le16 dest_word; 3837 u8 *from, *dest; 3838 u16 shift_width; 3839 3840 /* copy from the next struct field */ 3841 from = src_ctx + ce_info->offset; 3842 3843 /* prepare the bits and mask */ 3844 shift_width = ce_info->lsb % 8; 3845 mask = BIT(ce_info->width) - 1; 3846 3847 /* don't swizzle the bits until after the mask because the mask bits 3848 * will be in a different bit position on big endian machines 3849 */ 3850 src_word = *(u16 *)from; 3851 src_word &= mask; 3852 3853 /* shift to correct alignment */ 3854 mask <<= shift_width; 3855 src_word <<= shift_width; 3856 3857 /* get the current bits from the target bit string */ 3858 dest = dest_ctx + (ce_info->lsb / 8); 3859 3860 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 3861 3862 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 3863 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 3864 3865 /* put it all back */ 3866 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 3867 } 3868 3869 /** 3870 * ice_write_dword - write a dword to a packed context structure 3871 * @src_ctx: the context structure to read from 3872 * @dest_ctx: the context to be written to 3873 * @ce_info: a description of the struct to be filled 3874 */ 3875 static void 3876 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3877 { 3878 u32 src_dword, mask; 3879 __le32 dest_dword; 3880 u8 *from, *dest; 3881 u16 shift_width; 3882 3883 /* copy from the next struct field */ 3884 from = src_ctx + ce_info->offset; 3885 3886 /* prepare the bits and mask */ 3887 shift_width = ce_info->lsb % 8; 3888 3889 /* if the field width is exactly 32 on an x86 machine, then the shift 3890 * operation will not work because the SHL instructions count is masked 3891 * to 5 bits so the shift will do nothing 3892 */ 3893 if (ce_info->width < 32) 3894 mask = BIT(ce_info->width) - 1; 3895 else 3896 mask = (u32)~0; 3897 3898 /* don't swizzle the bits until after the mask because the mask bits 3899 * will be in a different bit position on big endian machines 3900 */ 3901 src_dword = *(u32 *)from; 3902 src_dword &= mask; 3903 3904 /* shift to correct alignment */ 3905 mask <<= shift_width; 3906 src_dword <<= shift_width; 3907 3908 /* get the current bits from the target bit string */ 3909 dest = dest_ctx + (ce_info->lsb / 8); 3910 3911 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 3912 3913 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 3914 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 3915 3916 /* put it all back */ 3917 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 3918 } 3919 3920 /** 3921 * ice_write_qword - write a qword to a packed context structure 3922 * @src_ctx: the context structure to read from 3923 * @dest_ctx: the context to be written to 3924 * @ce_info: a description of the struct to be filled 3925 */ 3926 static void 3927 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3928 { 3929 u64 src_qword, mask; 3930 __le64 dest_qword; 3931 u8 *from, *dest; 3932 u16 shift_width; 3933 3934 /* copy from the next struct field */ 3935 from = src_ctx + ce_info->offset; 3936 3937 /* prepare the bits and mask */ 3938 shift_width = ce_info->lsb % 8; 3939 3940 /* if the field width is exactly 64 on an x86 machine, then the shift 3941 * operation will not work because the SHL instructions count is masked 3942 * to 6 bits so the shift will do nothing 3943 */ 3944 if (ce_info->width < 64) 3945 mask = BIT_ULL(ce_info->width) - 1; 3946 else 3947 mask = (u64)~0; 3948 3949 /* don't swizzle the bits until after the mask because the mask bits 3950 * will be in a different bit position on big endian machines 3951 */ 3952 src_qword = *(u64 *)from; 3953 src_qword &= mask; 3954 3955 /* shift to correct alignment */ 3956 mask <<= shift_width; 3957 src_qword <<= shift_width; 3958 3959 /* get the current bits from the target bit string */ 3960 dest = dest_ctx + (ce_info->lsb / 8); 3961 3962 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 3963 3964 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 3965 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 3966 3967 /* put it all back */ 3968 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 3969 } 3970 3971 /** 3972 * ice_set_ctx - set context bits in packed structure 3973 * @hw: pointer to the hardware structure 3974 * @src_ctx: pointer to a generic non-packed context structure 3975 * @dest_ctx: pointer to memory for the packed structure 3976 * @ce_info: a description of the structure to be transformed 3977 */ 3978 enum ice_status 3979 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3980 const struct ice_ctx_ele *ce_info) 3981 { 3982 int f; 3983 3984 for (f = 0; ce_info[f].width; f++) { 3985 /* We have to deal with each element of the FW response 3986 * using the correct size so that we are correct regardless 3987 * of the endianness of the machine. 3988 */ 3989 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3990 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3991 f, ce_info[f].width, ce_info[f].size_of); 3992 continue; 3993 } 3994 switch (ce_info[f].size_of) { 3995 case sizeof(u8): 3996 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3997 break; 3998 case sizeof(u16): 3999 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4000 break; 4001 case sizeof(u32): 4002 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4003 break; 4004 case sizeof(u64): 4005 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4006 break; 4007 default: 4008 return ICE_ERR_INVAL_SIZE; 4009 } 4010 } 4011 4012 return ICE_SUCCESS; 4013 } 4014 4015 /** 4016 * ice_read_byte - read context byte into struct 4017 * @src_ctx: the context structure to read from 4018 * @dest_ctx: the context to be written to 4019 * @ce_info: a description of the struct to be filled 4020 */ 4021 static void 4022 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4023 { 4024 u8 dest_byte, mask; 4025 u8 *src, *target; 4026 u16 shift_width; 4027 4028 /* prepare the bits and mask */ 4029 shift_width = ce_info->lsb % 8; 4030 mask = (u8)(BIT(ce_info->width) - 1); 4031 4032 /* shift to correct alignment */ 4033 mask <<= shift_width; 4034 4035 /* get the current bits from the src bit string */ 4036 src = src_ctx + (ce_info->lsb / 8); 4037 4038 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 4039 4040 dest_byte &= ~(mask); 4041 4042 dest_byte >>= shift_width; 4043 4044 /* get the address from the struct field */ 4045 target = dest_ctx + ce_info->offset; 4046 4047 /* put it back in the struct */ 4048 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 4049 } 4050 4051 /** 4052 * ice_read_word - read context word into struct 4053 * @src_ctx: the context structure to read from 4054 * @dest_ctx: the context to be written to 4055 * @ce_info: a description of the struct to be filled 4056 */ 4057 static void 4058 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4059 { 4060 u16 dest_word, mask; 4061 u8 *src, *target; 4062 __le16 src_word; 4063 u16 shift_width; 4064 4065 /* prepare the bits and mask */ 4066 shift_width = ce_info->lsb % 8; 4067 mask = BIT(ce_info->width) - 1; 4068 4069 /* shift to correct alignment */ 4070 mask <<= shift_width; 4071 4072 /* get the current bits from the src bit string */ 4073 src = src_ctx + (ce_info->lsb / 8); 4074 4075 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 4076 4077 /* the data in the memory is stored as little endian so mask it 4078 * correctly 4079 */ 4080 src_word &= ~(CPU_TO_LE16(mask)); 4081 4082 /* get the data back into host order before shifting */ 4083 dest_word = LE16_TO_CPU(src_word); 4084 4085 dest_word >>= shift_width; 4086 4087 /* get the address from the struct field */ 4088 target = dest_ctx + ce_info->offset; 4089 4090 /* put it back in the struct */ 4091 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 4092 } 4093 4094 /** 4095 * ice_read_dword - read context dword into struct 4096 * @src_ctx: the context structure to read from 4097 * @dest_ctx: the context to be written to 4098 * @ce_info: a description of the struct to be filled 4099 */ 4100 static void 4101 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4102 { 4103 u32 dest_dword, mask; 4104 __le32 src_dword; 4105 u8 *src, *target; 4106 u16 shift_width; 4107 4108 /* prepare the bits and mask */ 4109 shift_width = ce_info->lsb % 8; 4110 4111 /* if the field width is exactly 32 on an x86 machine, then the shift 4112 * operation will not work because the SHL instructions count is masked 4113 * to 5 bits so the shift will do nothing 4114 */ 4115 if (ce_info->width < 32) 4116 mask = BIT(ce_info->width) - 1; 4117 else 4118 mask = (u32)~0; 4119 4120 /* shift to correct alignment */ 4121 mask <<= shift_width; 4122 4123 /* get the current bits from the src bit string */ 4124 src = src_ctx + (ce_info->lsb / 8); 4125 4126 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 4127 4128 /* the data in the memory is stored as little endian so mask it 4129 * correctly 4130 */ 4131 src_dword &= ~(CPU_TO_LE32(mask)); 4132 4133 /* get the data back into host order before shifting */ 4134 dest_dword = LE32_TO_CPU(src_dword); 4135 4136 dest_dword >>= shift_width; 4137 4138 /* get the address from the struct field */ 4139 target = dest_ctx + ce_info->offset; 4140 4141 /* put it back in the struct */ 4142 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 4143 } 4144 4145 /** 4146 * ice_read_qword - read context qword into struct 4147 * @src_ctx: the context structure to read from 4148 * @dest_ctx: the context to be written to 4149 * @ce_info: a description of the struct to be filled 4150 */ 4151 static void 4152 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4153 { 4154 u64 dest_qword, mask; 4155 __le64 src_qword; 4156 u8 *src, *target; 4157 u16 shift_width; 4158 4159 /* prepare the bits and mask */ 4160 shift_width = ce_info->lsb % 8; 4161 4162 /* if the field width is exactly 64 on an x86 machine, then the shift 4163 * operation will not work because the SHL instructions count is masked 4164 * to 6 bits so the shift will do nothing 4165 */ 4166 if (ce_info->width < 64) 4167 mask = BIT_ULL(ce_info->width) - 1; 4168 else 4169 mask = (u64)~0; 4170 4171 /* shift to correct alignment */ 4172 mask <<= shift_width; 4173 4174 /* get the current bits from the src bit string */ 4175 src = src_ctx + (ce_info->lsb / 8); 4176 4177 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 4178 4179 /* the data in the memory is stored as little endian so mask it 4180 * correctly 4181 */ 4182 src_qword &= ~(CPU_TO_LE64(mask)); 4183 4184 /* get the data back into host order before shifting */ 4185 dest_qword = LE64_TO_CPU(src_qword); 4186 4187 dest_qword >>= shift_width; 4188 4189 /* get the address from the struct field */ 4190 target = dest_ctx + ce_info->offset; 4191 4192 /* put it back in the struct */ 4193 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 4194 } 4195 4196 /** 4197 * ice_get_ctx - extract context bits from a packed structure 4198 * @src_ctx: pointer to a generic packed context structure 4199 * @dest_ctx: pointer to a generic non-packed context structure 4200 * @ce_info: a description of the structure to be read from 4201 */ 4202 enum ice_status 4203 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 4204 { 4205 int f; 4206 4207 for (f = 0; ce_info[f].width; f++) { 4208 switch (ce_info[f].size_of) { 4209 case 1: 4210 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 4211 break; 4212 case 2: 4213 ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 4214 break; 4215 case 4: 4216 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 4217 break; 4218 case 8: 4219 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 4220 break; 4221 default: 4222 /* nothing to do, just keep going */ 4223 break; 4224 } 4225 } 4226 4227 return ICE_SUCCESS; 4228 } 4229 4230 /** 4231 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4232 * @hw: pointer to the HW struct 4233 * @vsi_handle: software VSI handle 4234 * @tc: TC number 4235 * @q_handle: software queue handle 4236 */ 4237 struct ice_q_ctx * 4238 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4239 { 4240 struct ice_vsi_ctx *vsi; 4241 struct ice_q_ctx *q_ctx; 4242 4243 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4244 if (!vsi) 4245 return NULL; 4246 if (q_handle >= vsi->num_lan_q_entries[tc]) 4247 return NULL; 4248 if (!vsi->lan_q_ctx[tc]) 4249 return NULL; 4250 q_ctx = vsi->lan_q_ctx[tc]; 4251 return &q_ctx[q_handle]; 4252 } 4253 4254 /** 4255 * ice_ena_vsi_txq 4256 * @pi: port information structure 4257 * @vsi_handle: software VSI handle 4258 * @tc: TC number 4259 * @q_handle: software queue handle 4260 * @num_qgrps: Number of added queue groups 4261 * @buf: list of queue groups to be added 4262 * @buf_size: size of buffer for indirect command 4263 * @cd: pointer to command details structure or NULL 4264 * 4265 * This function adds one LAN queue 4266 */ 4267 enum ice_status 4268 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4269 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4270 struct ice_sq_cd *cd) 4271 { 4272 struct ice_aqc_txsched_elem_data node = { 0 }; 4273 struct ice_sched_node *parent; 4274 struct ice_q_ctx *q_ctx; 4275 enum ice_status status; 4276 struct ice_hw *hw; 4277 4278 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4279 return ICE_ERR_CFG; 4280 4281 if (num_qgrps > 1 || buf->num_txqs > 1) 4282 return ICE_ERR_MAX_LIMIT; 4283 4284 hw = pi->hw; 4285 4286 if (!ice_is_vsi_valid(hw, vsi_handle)) 4287 return ICE_ERR_PARAM; 4288 4289 ice_acquire_lock(&pi->sched_lock); 4290 4291 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4292 if (!q_ctx) { 4293 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4294 q_handle); 4295 status = ICE_ERR_PARAM; 4296 goto ena_txq_exit; 4297 } 4298 4299 /* find a parent node */ 4300 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4301 ICE_SCHED_NODE_OWNER_LAN); 4302 if (!parent) { 4303 status = ICE_ERR_PARAM; 4304 goto ena_txq_exit; 4305 } 4306 4307 buf->parent_teid = parent->info.node_teid; 4308 node.parent_teid = parent->info.node_teid; 4309 /* Mark that the values in the "generic" section as valid. The default 4310 * value in the "generic" section is zero. This means that : 4311 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4312 * - 0 priority among siblings, indicated by Bit 1-3. 4313 * - WFQ, indicated by Bit 4. 4314 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4315 * Bit 5-6. 4316 * - Bit 7 is reserved. 4317 * Without setting the generic section as valid in valid_sections, the 4318 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4319 */ 4320 buf->txqs[0].info.valid_sections = 4321 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4322 ICE_AQC_ELEM_VALID_EIR; 4323 buf->txqs[0].info.generic = 0; 4324 buf->txqs[0].info.cir_bw.bw_profile_idx = 4325 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4326 buf->txqs[0].info.cir_bw.bw_alloc = 4327 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4328 buf->txqs[0].info.eir_bw.bw_profile_idx = 4329 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 4330 buf->txqs[0].info.eir_bw.bw_alloc = 4331 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 4332 4333 /* add the LAN queue */ 4334 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4335 if (status != ICE_SUCCESS) { 4336 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4337 LE16_TO_CPU(buf->txqs[0].txq_id), 4338 hw->adminq.sq_last_status); 4339 goto ena_txq_exit; 4340 } 4341 4342 node.node_teid = buf->txqs[0].q_teid; 4343 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4344 q_ctx->q_handle = q_handle; 4345 q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 4346 4347 /* add a leaf node into scheduler tree queue layer */ 4348 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4349 if (!status) 4350 status = ice_sched_replay_q_bw(pi, q_ctx); 4351 4352 ena_txq_exit: 4353 ice_release_lock(&pi->sched_lock); 4354 return status; 4355 } 4356 4357 /** 4358 * ice_dis_vsi_txq 4359 * @pi: port information structure 4360 * @vsi_handle: software VSI handle 4361 * @tc: TC number 4362 * @num_queues: number of queues 4363 * @q_handles: pointer to software queue handle array 4364 * @q_ids: pointer to the q_id array 4365 * @q_teids: pointer to queue node teids 4366 * @rst_src: if called due to reset, specifies the reset source 4367 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4368 * @cd: pointer to command details structure or NULL 4369 * 4370 * This function removes queues and their corresponding nodes in SW DB 4371 */ 4372 enum ice_status 4373 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4374 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4375 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4376 struct ice_sq_cd *cd) 4377 { 4378 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4379 struct ice_aqc_dis_txq_item *qg_list; 4380 struct ice_q_ctx *q_ctx; 4381 struct ice_hw *hw; 4382 u16 i, buf_size; 4383 4384 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4385 return ICE_ERR_CFG; 4386 4387 hw = pi->hw; 4388 4389 if (!num_queues) { 4390 /* if queue is disabled already yet the disable queue command 4391 * has to be sent to complete the VF reset, then call 4392 * ice_aq_dis_lan_txq without any queue information 4393 */ 4394 if (rst_src) 4395 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4396 vmvf_num, NULL); 4397 return ICE_ERR_CFG; 4398 } 4399 4400 buf_size = ice_struct_size(qg_list, q_id, 1); 4401 qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size); 4402 if (!qg_list) 4403 return ICE_ERR_NO_MEMORY; 4404 4405 ice_acquire_lock(&pi->sched_lock); 4406 4407 for (i = 0; i < num_queues; i++) { 4408 struct ice_sched_node *node; 4409 4410 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4411 if (!node) 4412 continue; 4413 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4414 if (!q_ctx) { 4415 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4416 q_handles[i]); 4417 continue; 4418 } 4419 if (q_ctx->q_handle != q_handles[i]) { 4420 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4421 q_ctx->q_handle, q_handles[i]); 4422 continue; 4423 } 4424 qg_list->parent_teid = node->info.parent_teid; 4425 qg_list->num_qs = 1; 4426 qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]); 4427 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4428 vmvf_num, cd); 4429 4430 if (status != ICE_SUCCESS) 4431 break; 4432 ice_free_sched_node(pi, node); 4433 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4434 } 4435 ice_release_lock(&pi->sched_lock); 4436 ice_free(hw, qg_list); 4437 return status; 4438 } 4439 4440 /** 4441 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4442 * @pi: port information structure 4443 * @vsi_handle: software VSI handle 4444 * @tc_bitmap: TC bitmap 4445 * @maxqs: max queues array per TC 4446 * @owner: LAN or RDMA 4447 * 4448 * This function adds/updates the VSI queues per TC. 4449 */ 4450 static enum ice_status 4451 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4452 u16 *maxqs, u8 owner) 4453 { 4454 enum ice_status status = ICE_SUCCESS; 4455 u8 i; 4456 4457 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4458 return ICE_ERR_CFG; 4459 4460 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4461 return ICE_ERR_PARAM; 4462 4463 ice_acquire_lock(&pi->sched_lock); 4464 4465 ice_for_each_traffic_class(i) { 4466 /* configuration is possible only if TC node is present */ 4467 if (!ice_sched_get_tc_node(pi, i)) 4468 continue; 4469 4470 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4471 ice_is_tc_ena(tc_bitmap, i)); 4472 if (status) 4473 break; 4474 } 4475 4476 ice_release_lock(&pi->sched_lock); 4477 return status; 4478 } 4479 4480 /** 4481 * ice_cfg_vsi_lan - configure VSI LAN queues 4482 * @pi: port information structure 4483 * @vsi_handle: software VSI handle 4484 * @tc_bitmap: TC bitmap 4485 * @max_lanqs: max LAN queues array per TC 4486 * 4487 * This function adds/updates the VSI LAN queues per TC. 4488 */ 4489 enum ice_status 4490 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4491 u16 *max_lanqs) 4492 { 4493 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4494 ICE_SCHED_NODE_OWNER_LAN); 4495 } 4496 4497 /** 4498 * ice_is_main_vsi - checks whether the VSI is main VSI 4499 * @hw: pointer to the HW struct 4500 * @vsi_handle: VSI handle 4501 * 4502 * Checks whether the VSI is the main VSI (the first PF VSI created on 4503 * given PF). 4504 */ 4505 static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 4506 { 4507 return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 4508 } 4509 4510 /** 4511 * ice_replay_pre_init - replay pre initialization 4512 * @hw: pointer to the HW struct 4513 * @sw: pointer to switch info struct for which function initializes filters 4514 * 4515 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4516 */ 4517 static enum ice_status 4518 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 4519 { 4520 enum ice_status status; 4521 u8 i; 4522 4523 /* Delete old entries from replay filter list head if there is any */ 4524 ice_rm_sw_replay_rule_info(hw, sw); 4525 /* In start of replay, move entries into replay_rules list, it 4526 * will allow adding rules entries back to filt_rules list, 4527 * which is operational list. 4528 */ 4529 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4530 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 4531 &sw->recp_list[i].filt_replay_rules); 4532 ice_sched_replay_agg_vsi_preinit(hw); 4533 4534 status = ice_sched_replay_root_node_bw(hw->port_info); 4535 if (status) 4536 return status; 4537 4538 return ice_sched_replay_tc_node_bw(hw->port_info); 4539 } 4540 4541 /** 4542 * ice_replay_vsi - replay VSI configuration 4543 * @hw: pointer to the HW struct 4544 * @vsi_handle: driver VSI handle 4545 * 4546 * Restore all VSI configuration after reset. It is required to call this 4547 * function with main VSI first. 4548 */ 4549 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4550 { 4551 struct ice_switch_info *sw = hw->switch_info; 4552 struct ice_port_info *pi = hw->port_info; 4553 enum ice_status status; 4554 4555 if (!ice_is_vsi_valid(hw, vsi_handle)) 4556 return ICE_ERR_PARAM; 4557 4558 /* Replay pre-initialization if there is any */ 4559 if (ice_is_main_vsi(hw, vsi_handle)) { 4560 status = ice_replay_pre_init(hw, sw); 4561 if (status) 4562 return status; 4563 } 4564 /* Replay per VSI all RSS configurations */ 4565 status = ice_replay_rss_cfg(hw, vsi_handle); 4566 if (status) 4567 return status; 4568 /* Replay per VSI all filters */ 4569 status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 4570 if (!status) 4571 status = ice_replay_vsi_agg(hw, vsi_handle); 4572 return status; 4573 } 4574 4575 /** 4576 * ice_replay_post - post replay configuration cleanup 4577 * @hw: pointer to the HW struct 4578 * 4579 * Post replay cleanup. 4580 */ 4581 void ice_replay_post(struct ice_hw *hw) 4582 { 4583 /* Delete old entries from replay filter list head */ 4584 ice_rm_all_sw_replay_rule_info(hw); 4585 ice_sched_replay_agg(hw); 4586 } 4587 4588 /** 4589 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4590 * @hw: ptr to the hardware info 4591 * @reg: offset of 64 bit HW register to read from 4592 * @prev_stat_loaded: bool to specify if previous stats are loaded 4593 * @prev_stat: ptr to previous loaded stat value 4594 * @cur_stat: ptr to current stat value 4595 */ 4596 void 4597 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4598 u64 *prev_stat, u64 *cur_stat) 4599 { 4600 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4601 4602 /* device stats are not reset at PFR, they likely will not be zeroed 4603 * when the driver starts. Thus, save the value from the first read 4604 * without adding to the statistic value so that we report stats which 4605 * count up from zero. 4606 */ 4607 if (!prev_stat_loaded) { 4608 *prev_stat = new_data; 4609 return; 4610 } 4611 4612 /* Calculate the difference between the new and old values, and then 4613 * add it to the software stat value. 4614 */ 4615 if (new_data >= *prev_stat) 4616 *cur_stat += new_data - *prev_stat; 4617 else 4618 /* to manage the potential roll-over */ 4619 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4620 4621 /* Update the previously stored value to prepare for next read */ 4622 *prev_stat = new_data; 4623 } 4624 4625 /** 4626 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4627 * @hw: ptr to the hardware info 4628 * @reg: offset of HW register to read from 4629 * @prev_stat_loaded: bool to specify if previous stats are loaded 4630 * @prev_stat: ptr to previous loaded stat value 4631 * @cur_stat: ptr to current stat value 4632 */ 4633 void 4634 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4635 u64 *prev_stat, u64 *cur_stat) 4636 { 4637 u32 new_data; 4638 4639 new_data = rd32(hw, reg); 4640 4641 /* device stats are not reset at PFR, they likely will not be zeroed 4642 * when the driver starts. Thus, save the value from the first read 4643 * without adding to the statistic value so that we report stats which 4644 * count up from zero. 4645 */ 4646 if (!prev_stat_loaded) { 4647 *prev_stat = new_data; 4648 return; 4649 } 4650 4651 /* Calculate the difference between the new and old values, and then 4652 * add it to the software stat value. 4653 */ 4654 if (new_data >= *prev_stat) 4655 *cur_stat += new_data - *prev_stat; 4656 else 4657 /* to manage the potential roll-over */ 4658 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4659 4660 /* Update the previously stored value to prepare for next read */ 4661 *prev_stat = new_data; 4662 } 4663 4664 /** 4665 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 4666 * @hw: ptr to the hardware info 4667 * @vsi_handle: VSI handle 4668 * @prev_stat_loaded: bool to specify if the previous stat values are loaded 4669 * @cur_stats: ptr to current stats structure 4670 * 4671 * The GLV_REPC statistic register actually tracks two 16bit statistics, and 4672 * thus cannot be read using the normal ice_stat_update32 function. 4673 * 4674 * Read the GLV_REPC register associated with the given VSI, and update the 4675 * rx_no_desc and rx_error values in the ice_eth_stats structure. 4676 * 4677 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 4678 * cleared each time it's read. 4679 * 4680 * Note that the GLV_RDPC register also counts the causes that would trigger 4681 * GLV_REPC. However, it does not give the finer grained detail about why the 4682 * packets are being dropped. The GLV_REPC values can be used to distinguish 4683 * whether Rx packets are dropped due to errors or due to no available 4684 * descriptors. 4685 */ 4686 void 4687 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 4688 struct ice_eth_stats *cur_stats) 4689 { 4690 u16 vsi_num, no_desc, error_cnt; 4691 u32 repc; 4692 4693 if (!ice_is_vsi_valid(hw, vsi_handle)) 4694 return; 4695 4696 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 4697 4698 /* If we haven't loaded stats yet, just clear the current value */ 4699 if (!prev_stat_loaded) { 4700 wr32(hw, GLV_REPC(vsi_num), 0); 4701 return; 4702 } 4703 4704 repc = rd32(hw, GLV_REPC(vsi_num)); 4705 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 4706 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 4707 4708 /* Clear the count by writing to the stats register */ 4709 wr32(hw, GLV_REPC(vsi_num), 0); 4710 4711 cur_stats->rx_no_desc += no_desc; 4712 cur_stats->rx_errors += error_cnt; 4713 } 4714 4715 /** 4716 * ice_sched_query_elem - query element information from HW 4717 * @hw: pointer to the HW struct 4718 * @node_teid: node TEID to be queried 4719 * @buf: buffer to element information 4720 * 4721 * This function queries HW element information 4722 */ 4723 enum ice_status 4724 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4725 struct ice_aqc_txsched_elem_data *buf) 4726 { 4727 u16 buf_size, num_elem_ret = 0; 4728 enum ice_status status; 4729 4730 buf_size = sizeof(*buf); 4731 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 4732 buf->node_teid = CPU_TO_LE32(node_teid); 4733 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4734 NULL); 4735 if (status != ICE_SUCCESS || num_elem_ret != 1) 4736 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4737 return status; 4738 } 4739 4740 /** 4741 * ice_get_fw_mode - returns FW mode 4742 * @hw: pointer to the HW struct 4743 */ 4744 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 4745 { 4746 #define ICE_FW_MODE_DBG_M BIT(0) 4747 #define ICE_FW_MODE_REC_M BIT(1) 4748 #define ICE_FW_MODE_ROLLBACK_M BIT(2) 4749 u32 fw_mode; 4750 4751 /* check the current FW mode */ 4752 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 4753 4754 if (fw_mode & ICE_FW_MODE_DBG_M) 4755 return ICE_FW_MODE_DBG; 4756 else if (fw_mode & ICE_FW_MODE_REC_M) 4757 return ICE_FW_MODE_REC; 4758 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 4759 return ICE_FW_MODE_ROLLBACK; 4760 else 4761 return ICE_FW_MODE_NORMAL; 4762 } 4763 4764 /** 4765 * ice_fw_supports_link_override 4766 * @hw: pointer to the hardware structure 4767 * 4768 * Checks if the firmware supports link override 4769 */ 4770 bool ice_fw_supports_link_override(struct ice_hw *hw) 4771 { 4772 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4773 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4774 return true; 4775 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4776 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4777 return true; 4778 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4779 return true; 4780 } 4781 4782 return false; 4783 } 4784 4785 /** 4786 * ice_get_link_default_override 4787 * @ldo: pointer to the link default override struct 4788 * @pi: pointer to the port info struct 4789 * 4790 * Gets the link default override for a port 4791 */ 4792 enum ice_status 4793 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4794 struct ice_port_info *pi) 4795 { 4796 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4797 struct ice_hw *hw = pi->hw; 4798 enum ice_status status; 4799 4800 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4801 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4802 if (status) { 4803 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4804 return status; 4805 } 4806 4807 /* Each port has its own config; calculate for our port */ 4808 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4809 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4810 4811 /* link options first */ 4812 status = ice_read_sr_word(hw, tlv_start, &buf); 4813 if (status) { 4814 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4815 return status; 4816 } 4817 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4818 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4819 ICE_LINK_OVERRIDE_PHY_CFG_S; 4820 4821 /* link PHY config */ 4822 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4823 status = ice_read_sr_word(hw, offset, &buf); 4824 if (status) { 4825 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4826 return status; 4827 } 4828 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4829 4830 /* PHY types low */ 4831 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4832 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4833 status = ice_read_sr_word(hw, (offset + i), &buf); 4834 if (status) { 4835 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4836 return status; 4837 } 4838 /* shift 16 bits at a time to fill 64 bits */ 4839 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4840 } 4841 4842 /* PHY types high */ 4843 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4844 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4845 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4846 status = ice_read_sr_word(hw, (offset + i), &buf); 4847 if (status) { 4848 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4849 return status; 4850 } 4851 /* shift 16 bits at a time to fill 64 bits */ 4852 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4853 } 4854 4855 return status; 4856 } 4857 4858 /** 4859 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4860 * @caps: get PHY capability data 4861 */ 4862 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4863 { 4864 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4865 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4866 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4867 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4868 return true; 4869 4870 return false; 4871 } 4872 4873 /** 4874 * ice_aq_set_lldp_mib - Set the LLDP MIB 4875 * @hw: pointer to the HW struct 4876 * @mib_type: Local, Remote or both Local and Remote MIBs 4877 * @buf: pointer to the caller-supplied buffer to store the MIB block 4878 * @buf_size: size of the buffer (in bytes) 4879 * @cd: pointer to command details structure or NULL 4880 * 4881 * Set the LLDP MIB. (0x0A08) 4882 */ 4883 enum ice_status 4884 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 4885 struct ice_sq_cd *cd) 4886 { 4887 struct ice_aqc_lldp_set_local_mib *cmd; 4888 struct ice_aq_desc desc; 4889 4890 cmd = &desc.params.lldp_set_mib; 4891 4892 if (buf_size == 0 || !buf) 4893 return ICE_ERR_PARAM; 4894 4895 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 4896 4897 desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD); 4898 desc.datalen = CPU_TO_LE16(buf_size); 4899 4900 cmd->type = mib_type; 4901 cmd->length = CPU_TO_LE16(buf_size); 4902 4903 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4904 } 4905 4906 /** 4907 * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl 4908 * @hw: pointer to HW struct 4909 */ 4910 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 4911 { 4912 if (hw->mac_type != ICE_MAC_E810) 4913 return false; 4914 4915 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 4916 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 4917 return true; 4918 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 4919 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 4920 return true; 4921 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 4922 return true; 4923 } 4924 return false; 4925 } 4926 4927 /** 4928 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 4929 * @hw: pointer to HW struct 4930 * @vsi_num: absolute HW index for VSI 4931 * @add: boolean for if adding or removing a filter 4932 */ 4933 enum ice_status 4934 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 4935 { 4936 struct ice_aqc_lldp_filter_ctrl *cmd; 4937 struct ice_aq_desc desc; 4938 4939 cmd = &desc.params.lldp_filter_ctrl; 4940 4941 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 4942 4943 if (add) 4944 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 4945 else 4946 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 4947 4948 cmd->vsi_num = CPU_TO_LE16(vsi_num); 4949 4950 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4951 } 4952 4953 /** 4954 * ice_fw_supports_report_dflt_cfg 4955 * @hw: pointer to the hardware structure 4956 * 4957 * Checks if the firmware supports report default configuration 4958 */ 4959 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 4960 { 4961 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 4962 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 4963 return true; 4964 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 4965 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 4966 return true; 4967 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 4968 return true; 4969 } 4970 return false; 4971 } 4972