1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2019 3 */ 4 5 #ifndef _ICE_ADMINQ_CMD_H_ 6 #define _ICE_ADMINQ_CMD_H_ 7 8 /* This header file defines the Admin Queue commands, error codes and 9 * descriptor format. It is shared between Firmware and Software. 10 */ 11 12 #define ICE_MAX_VSI 768 13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 15 16 struct ice_aqc_generic { 17 __le32 param0; 18 __le32 param1; 19 __le32 addr_high; 20 __le32 addr_low; 21 }; 22 23 /* Get version (direct 0x0001) */ 24 struct ice_aqc_get_ver { 25 __le32 rom_ver; 26 __le32 fw_build; 27 u8 fw_branch; 28 u8 fw_major; 29 u8 fw_minor; 30 u8 fw_patch; 31 u8 api_branch; 32 u8 api_major; 33 u8 api_minor; 34 u8 api_patch; 35 }; 36 37 /* Send driver version (indirect 0x0002) */ 38 struct ice_aqc_driver_ver { 39 u8 major_ver; 40 u8 minor_ver; 41 u8 build_ver; 42 u8 subbuild_ver; 43 u8 reserved[4]; 44 __le32 addr_high; 45 __le32 addr_low; 46 }; 47 48 /* Queue Shutdown (direct 0x0003) */ 49 struct ice_aqc_q_shutdown { 50 u8 driver_unloading; 51 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 52 u8 reserved[15]; 53 }; 54 55 /* Request resource ownership (direct 0x0008) 56 * Release resource ownership (direct 0x0009) 57 */ 58 struct ice_aqc_req_res { 59 __le16 res_id; 60 #define ICE_AQC_RES_ID_NVM 1 61 #define ICE_AQC_RES_ID_SDP 2 62 #define ICE_AQC_RES_ID_CHNG_LOCK 3 63 #define ICE_AQC_RES_ID_GLBL_LOCK 4 64 __le16 access_type; 65 #define ICE_AQC_RES_ACCESS_READ 1 66 #define ICE_AQC_RES_ACCESS_WRITE 2 67 68 /* Upon successful completion, FW writes this value and driver is 69 * expected to release resource before timeout. This value is provided 70 * in milliseconds. 71 */ 72 __le32 timeout; 73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 77 /* For SDP: pin ID of the SDP */ 78 __le32 res_number; 79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 80 __le16 status; 81 #define ICE_AQ_RES_GLBL_SUCCESS 0 82 #define ICE_AQ_RES_GLBL_IN_PROG 1 83 #define ICE_AQ_RES_GLBL_DONE 2 84 u8 reserved[2]; 85 }; 86 87 /* Get function capabilities (indirect 0x000A) 88 * Get device capabilities (indirect 0x000B) 89 */ 90 struct ice_aqc_list_caps { 91 u8 cmd_flags; 92 u8 pf_index; 93 u8 reserved[2]; 94 __le32 count; 95 __le32 addr_high; 96 __le32 addr_low; 97 }; 98 99 /* Device/Function buffer entry, repeated per reported capability */ 100 struct ice_aqc_list_caps_elem { 101 __le16 cap; 102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 113 u8 major_ver; 114 u8 minor_ver; 115 /* Number of resources described by this capability */ 116 __le32 number; 117 /* Only meaningful for some types of resources */ 118 __le32 logical_id; 119 /* Only meaningful for some types of resources */ 120 __le32 phys_id; 121 __le64 rsvd1; 122 __le64 rsvd2; 123 }; 124 125 /* Manage MAC address, read command - indirect (0x0107) 126 * This struct is also used for the response 127 */ 128 struct ice_aqc_manage_mac_read { 129 __le16 flags; /* Zeroed by device driver */ 130 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 131 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 132 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 133 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 134 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 135 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 136 #define ICE_AQC_MAN_MAC_READ_S 4 137 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 138 u8 rsvd[2]; 139 u8 num_addr; /* Used in response */ 140 u8 rsvd1[3]; 141 __le32 addr_high; 142 __le32 addr_low; 143 }; 144 145 /* Response buffer format for manage MAC read command */ 146 struct ice_aqc_manage_mac_read_resp { 147 u8 lport_num; 148 u8 addr_type; 149 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 150 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 151 u8 mac_addr[ETH_ALEN]; 152 }; 153 154 /* Manage MAC address, write command - direct (0x0108) */ 155 struct ice_aqc_manage_mac_write { 156 u8 rsvd; 157 u8 flags; 158 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 159 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 160 #define ICE_AQC_MAN_MAC_WR_S 6 161 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 162 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 163 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 164 /* High 16 bits of MAC address in big endian order */ 165 __be16 sah; 166 /* Low 32 bits of MAC address in big endian order */ 167 __be32 sal; 168 __le32 addr_high; 169 __le32 addr_low; 170 }; 171 172 /* Clear PXE Command and response (direct 0x0110) */ 173 struct ice_aqc_clear_pxe { 174 u8 rx_cnt; 175 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 176 u8 reserved[15]; 177 }; 178 179 /* Configure No-Drop Policy Command (direct 0x0112) */ 180 struct ice_aqc_config_no_drop_policy { 181 u8 opts; 182 #define ICE_AQC_FORCE_NO_DROP BIT(0) 183 u8 rsvd[15]; 184 }; 185 186 /* Get switch configuration (0x0200) */ 187 struct ice_aqc_get_sw_cfg { 188 /* Reserved for command and copy of request flags for response */ 189 __le16 flags; 190 /* First desc in case of command and next_elem in case of response 191 * In case of response, if it is not zero, means all the configuration 192 * was not returned and new command shall be sent with this value in 193 * the 'first desc' field 194 */ 195 __le16 element; 196 /* Reserved for command, only used for response */ 197 __le16 num_elems; 198 __le16 rsvd; 199 __le32 addr_high; 200 __le32 addr_low; 201 }; 202 203 /* Each entry in the response buffer is of the following type: */ 204 struct ice_aqc_get_sw_cfg_resp_elem { 205 /* VSI/Port Number */ 206 __le16 vsi_port_num; 207 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 208 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 209 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 210 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 211 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 212 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 213 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 214 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 215 216 /* SWID VSI/Port belongs to */ 217 __le16 swid; 218 219 /* Bit 14..0 : PF/VF number VSI belongs to 220 * Bit 15 : VF indication bit 221 */ 222 __le16 pf_vf_num; 223 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 224 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 225 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 226 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 227 }; 228 229 /* The response buffer is as follows. Note that the length of the 230 * elements array varies with the length of the command response. 231 */ 232 struct ice_aqc_get_sw_cfg_resp { 233 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 234 }; 235 236 /* These resource type defines are used for all switch resource 237 * commands where a resource type is required, such as: 238 * Get Resource Allocation command (indirect 0x0204) 239 * Allocate Resources command (indirect 0x0208) 240 * Free Resources command (indirect 0x0209) 241 * Get Allocated Resource Descriptors Command (indirect 0x020A) 242 */ 243 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 244 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 245 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 246 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 247 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 248 #define ICE_AQC_RES_TYPE_RECIPE 0x05 249 #define ICE_AQC_RES_TYPE_PROFILE 0x06 250 #define ICE_AQC_RES_TYPE_SWID 0x07 251 #define ICE_AQC_RES_TYPE_VSI 0x08 252 #define ICE_AQC_RES_TYPE_FLU 0x09 253 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 254 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 255 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 256 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 257 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 258 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 259 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 260 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 261 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 262 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 263 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 264 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 265 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 266 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 267 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 268 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 269 /* Resource types 0x62-67 are reserved for Hash profile builder */ 270 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 271 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 272 273 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 274 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 275 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 276 277 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 278 279 #define ICE_AQC_RES_TYPE_S 0 280 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 281 282 /* Get Resource Allocation command (indirect 0x0204) */ 283 struct ice_aqc_get_res_alloc { 284 __le16 resp_elem_num; /* Used in response, reserved in command */ 285 u8 reserved[6]; 286 __le32 addr_high; 287 __le32 addr_low; 288 }; 289 290 /* Get Resource Allocation Response Buffer per response */ 291 struct ice_aqc_get_res_resp_elem { 292 __le16 res_type; /* Types defined above cmd 0x0204 */ 293 __le16 total_capacity; /* Resources available to all PF's */ 294 __le16 total_function; /* Resources allocated for a PF */ 295 __le16 total_shared; /* Resources allocated as shared */ 296 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 297 }; 298 299 /* Buffer for Get Resource command */ 300 struct ice_aqc_get_res_resp { 301 /* Number of resource entries to be calculated using 302 * datalen/sizeof(struct ice_aqc_cmd_resp)). 303 * Value of 'datalen' gets updated as part of response. 304 */ 305 struct ice_aqc_get_res_resp_elem elem[1]; 306 }; 307 308 /* Allocate Resources command (indirect 0x0208) 309 * Free Resources command (indirect 0x0209) 310 */ 311 struct ice_aqc_alloc_free_res_cmd { 312 __le16 num_entries; /* Number of Resource entries */ 313 u8 reserved[6]; 314 __le32 addr_high; 315 __le32 addr_low; 316 }; 317 318 /* Resource descriptor */ 319 struct ice_aqc_res_elem { 320 union { 321 __le16 sw_resp; 322 __le16 flu_resp; 323 } e; 324 }; 325 326 /* Buffer for Allocate/Free Resources commands */ 327 struct ice_aqc_alloc_free_res_elem { 328 __le16 res_type; /* Types defined above cmd 0x0204 */ 329 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 330 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 331 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 332 __le16 num_elems; 333 struct ice_aqc_res_elem elem[1]; 334 }; 335 336 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 337 struct ice_aqc_get_allocd_res_desc { 338 union { 339 struct { 340 __le16 res; /* Types defined above cmd 0x0204 */ 341 __le16 first_desc; 342 __le32 reserved; 343 } cmd; 344 struct { 345 __le16 res; 346 __le16 next_desc; 347 __le16 num_desc; 348 __le16 reserved; 349 } resp; 350 } ops; 351 __le32 addr_high; 352 __le32 addr_low; 353 }; 354 355 struct ice_aqc_get_allocd_res_desc_resp { 356 struct ice_aqc_res_elem elem[1]; 357 }; 358 359 /* Add VSI (indirect 0x0210) 360 * Update VSI (indirect 0x0211) 361 * Get VSI (indirect 0x0212) 362 * Free VSI (indirect 0x0213) 363 */ 364 struct ice_aqc_add_get_update_free_vsi { 365 __le16 vsi_num; 366 #define ICE_AQ_VSI_NUM_S 0 367 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 368 #define ICE_AQ_VSI_IS_VALID BIT(15) 369 __le16 cmd_flags; 370 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 371 u8 vf_id; 372 u8 reserved; 373 __le16 vsi_flags; 374 #define ICE_AQ_VSI_TYPE_S 0 375 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 376 #define ICE_AQ_VSI_TYPE_VF 0x0 377 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 378 #define ICE_AQ_VSI_TYPE_PF 0x2 379 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 380 __le32 addr_high; 381 __le32 addr_low; 382 }; 383 384 /* Response descriptor for: 385 * Add VSI (indirect 0x0210) 386 * Update VSI (indirect 0x0211) 387 * Free VSI (indirect 0x0213) 388 */ 389 struct ice_aqc_add_update_free_vsi_resp { 390 __le16 vsi_num; 391 __le16 ext_status; 392 __le16 vsi_used; 393 __le16 vsi_free; 394 __le32 addr_high; 395 __le32 addr_low; 396 }; 397 398 struct ice_aqc_get_vsi_resp { 399 __le16 vsi_num; 400 u8 vf_id; 401 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 402 * These are found above in struct ice_aqc_add_get_update_free_vsi. 403 */ 404 u8 vsi_flags; 405 __le16 vsi_used; 406 __le16 vsi_free; 407 __le32 addr_high; 408 __le32 addr_low; 409 }; 410 411 struct ice_aqc_vsi_props { 412 __le16 valid_sections; 413 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 414 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 415 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 416 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 417 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 418 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 419 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 420 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 421 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 422 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 423 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 424 /* switch section */ 425 u8 sw_id; 426 u8 sw_flags; 427 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 428 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 429 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 430 u8 sw_flags2; 431 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 432 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 433 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 434 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 435 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 436 u8 veb_stat_id; 437 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 438 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 439 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 440 /* security section */ 441 u8 sec_flags; 442 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 443 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 444 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 445 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 446 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 447 u8 sec_reserved; 448 /* VLAN section */ 449 __le16 pvid; /* VLANS include priority bits */ 450 u8 pvlan_reserved[2]; 451 u8 vlan_flags; 452 #define ICE_AQ_VSI_VLAN_MODE_S 0 453 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 454 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 455 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 456 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 457 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 458 #define ICE_AQ_VSI_VLAN_EMOD_S 3 459 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 460 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 461 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 462 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 463 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 464 u8 pvlan_reserved2[3]; 465 /* ingress egress up sections */ 466 __le32 ingress_table; /* bitmap, 3 bits per up */ 467 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 468 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 469 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 470 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 471 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 472 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 473 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 474 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 475 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 476 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 477 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 478 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 479 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 480 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 481 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 482 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 483 __le32 egress_table; /* same defines as for ingress table */ 484 /* outer tags section */ 485 __le16 outer_tag; 486 u8 outer_tag_flags; 487 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 488 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 489 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 490 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 491 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 492 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 493 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 494 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 495 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 496 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 497 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 498 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 499 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 500 u8 outer_tag_reserved; 501 /* queue mapping section */ 502 __le16 mapping_flags; 503 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 504 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 505 __le16 q_mapping[16]; 506 #define ICE_AQ_VSI_Q_S 0 507 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 508 __le16 tc_mapping[8]; 509 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 510 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 511 #define ICE_AQ_VSI_TC_Q_NUM_S 11 512 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 513 /* queueing option section */ 514 u8 q_opt_rss; 515 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 516 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 517 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 518 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 519 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 520 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 521 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 522 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 523 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 524 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 525 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 526 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 527 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 528 u8 q_opt_tc; 529 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 530 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 531 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 532 u8 q_opt_flags; 533 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 534 u8 q_opt_reserved[3]; 535 /* outer up section */ 536 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 537 /* section 10 */ 538 __le16 sect_10_reserved; 539 /* flow director section */ 540 __le16 fd_options; 541 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 542 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 543 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 544 __le16 max_fd_fltr_dedicated; 545 __le16 max_fd_fltr_shared; 546 __le16 fd_def_q; 547 #define ICE_AQ_VSI_FD_DEF_Q_S 0 548 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 549 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 550 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 551 __le16 fd_report_opt; 552 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 553 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 554 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 555 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 556 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 557 /* PASID section */ 558 __le32 pasid_id; 559 #define ICE_AQ_VSI_PASID_ID_S 0 560 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 561 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 562 u8 reserved[24]; 563 }; 564 565 /* Add/update mirror rule - direct (0x0260) */ 566 #define ICE_AQC_RULE_ID_VALID_S 7 567 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 568 #define ICE_AQC_RULE_ID_S 0 569 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 570 571 /* Following defines to be used while processing caller specified mirror list 572 * of VSI indexes. 573 */ 574 /* Action: Byte.bit (1.7) 575 * 0 = Remove VSI from mirror rule 576 * 1 = Add VSI to mirror rule 577 */ 578 #define ICE_AQC_RULE_ACT_S 15 579 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 580 /* Action: 1.2:0.0 = Mirrored VSI */ 581 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 582 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 583 584 /* This is to be used by add/update mirror rule Admin Queue command. 585 * In case of add mirror rule - if rule ID is specified as 586 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 587 * If specified rule_id is valid, then it is used. If specified rule_id 588 * is in use then new mirroring rule is added. 589 */ 590 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 591 592 struct ice_aqc_add_update_mir_rule { 593 __le16 rule_id; 594 595 __le16 rule_type; 596 #define ICE_AQC_RULE_TYPE_S 0 597 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 598 /* VPORT ingress/egress */ 599 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 600 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 601 /* Physical port ingress mirroring. 602 * All traffic received by this port 603 */ 604 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 605 /* Physical port egress mirroring. All traffic sent by this port */ 606 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 607 608 /* Number of mirrored entries. 609 * The values are in the command buffer 610 */ 611 __le16 num_entries; 612 613 /* Destination VSI */ 614 __le16 dest; 615 __le32 addr_high; 616 __le32 addr_low; 617 }; 618 619 /* Delete mirror rule - direct(0x0261) */ 620 struct ice_aqc_delete_mir_rule { 621 __le16 rule_id; 622 __le16 rsvd; 623 624 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 625 * the PF allocated resources, otherwise it is returned to the 626 * shared pool 627 */ 628 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 629 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 630 __le16 flags; 631 632 u8 reserved[10]; 633 }; 634 635 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 636 /* This structure holds get storm configuration response and same structure 637 * is used to perform set_storm_cfg 638 */ 639 struct ice_aqc_storm_cfg { 640 __le32 bcast_thresh_size; 641 __le32 mcast_thresh_size; 642 /* Bit 18:0 - Traffic upper threshold size 643 * Bit 31:19 - Reserved 644 */ 645 #define ICE_AQ_THRESHOLD_S 0 646 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 647 648 __le32 storm_ctrl_ctrl; 649 /* Bit 0: MDIPW - Drop Multicast packets in previous window 650 * Bit 1: MDICW - Drop multicast packets in current window 651 * Bit 2: BDIPW - Drop broadcast packets in previous window 652 * Bit 3: BDICW - Drop broadcast packets in current window 653 */ 654 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 655 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 656 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 657 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 658 /* Bit 7:5 : Reserved */ 659 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 660 * interval size for applying ingress broadcast or multicast storm 661 * control. 662 */ 663 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 664 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 665 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 666 __le32 reserved; 667 }; 668 669 #define ICE_MAX_NUM_RECIPES 64 670 671 /* Add/Get Recipe (indirect 0x0290/0x0292)*/ 672 struct ice_aqc_add_get_recipe { 673 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 674 __le16 return_index; /* Input, used for Get cmd only */ 675 u8 reserved[4]; 676 __le32 addr_high; 677 __le32 addr_low; 678 }; 679 680 struct ice_aqc_recipe_content { 681 u8 rid; 682 #define ICE_AQ_RECIPE_ID_S 0 683 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 684 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 685 #define ICE_AQ_SW_ID_LKUP_IDX 0 686 u8 lkup_indx[5]; 687 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 688 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 689 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 690 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 691 __le16 mask[5]; 692 u8 result_indx; 693 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 694 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 695 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 696 u8 rsvd0[3]; 697 u8 act_ctrl_join_priority; 698 u8 act_ctrl_fwd_priority; 699 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 700 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 701 u8 act_ctrl; 702 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 703 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 704 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 705 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 706 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 707 u8 rsvd1; 708 __le32 dflt_act; 709 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 710 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 711 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 712 }; 713 714 struct ice_aqc_recipe_data_elem { 715 u8 recipe_indx; 716 u8 resp_bits; 717 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 718 u8 rsvd0[2]; 719 u8 recipe_bitmap[8]; 720 u8 rsvd1[4]; 721 struct ice_aqc_recipe_content content; 722 u8 rsvd2[20]; 723 }; 724 725 /* This struct contains a number of entries as per the 726 * num_sub_recipes in the command 727 */ 728 struct ice_aqc_add_get_recipe_data { 729 struct ice_aqc_recipe_data_elem recipe[1]; 730 }; 731 732 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 733 struct ice_aqc_recipe_to_profile { 734 __le16 profile_id; 735 u8 rsvd[6]; 736 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES); 737 }; 738 739 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 740 */ 741 struct ice_aqc_sw_rules { 742 /* ops: add switch rules, referring the number of rules. 743 * ops: update switch rules, referring the number of filters 744 * ops: remove switch rules, referring the entry index. 745 * ops: get switch rules, referring to the number of filters. 746 */ 747 __le16 num_rules_fltr_entry_index; 748 u8 reserved[6]; 749 __le32 addr_high; 750 __le32 addr_low; 751 }; 752 753 #pragma pack(1) 754 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 755 * This structures describes the lookup rules and associated actions. "index" 756 * is returned as part of a response to a successful Add command, and can be 757 * used to identify the rule for Update/Get/Remove commands. 758 */ 759 struct ice_sw_rule_lkup_rx_tx { 760 __le16 recipe_id; 761 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 762 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 763 __le16 src; 764 __le32 act; 765 766 /* Bit 0:1 - Action type */ 767 #define ICE_SINGLE_ACT_TYPE_S 0x00 768 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 769 770 /* Bit 2 - Loop back enable 771 * Bit 3 - LAN enable 772 */ 773 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 774 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 775 776 /* Action type = 0 - Forward to VSI or VSI list */ 777 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 778 779 #define ICE_SINGLE_ACT_VSI_ID_S 4 780 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 781 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 782 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 783 /* This bit needs to be set if action is forward to VSI list */ 784 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 785 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 786 #define ICE_SINGLE_ACT_DROP BIT(18) 787 788 /* Action type = 1 - Forward to Queue of Queue group */ 789 #define ICE_SINGLE_ACT_TO_Q 0x1 790 #define ICE_SINGLE_ACT_Q_INDEX_S 4 791 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 792 #define ICE_SINGLE_ACT_Q_REGION_S 15 793 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 794 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 795 796 /* Action type = 2 - Prune */ 797 #define ICE_SINGLE_ACT_PRUNE 0x2 798 #define ICE_SINGLE_ACT_EGRESS BIT(15) 799 #define ICE_SINGLE_ACT_INGRESS BIT(16) 800 #define ICE_SINGLE_ACT_PRUNET BIT(17) 801 /* Bit 18 should be set to 0 for this action */ 802 803 /* Action type = 2 - Pointer */ 804 #define ICE_SINGLE_ACT_PTR 0x2 805 #define ICE_SINGLE_ACT_PTR_VAL_S 4 806 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 807 /* Bit 18 should be set to 1 */ 808 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 809 810 /* Action type = 3 - Other actions. Last two bits 811 * are other action identifier 812 */ 813 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 814 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 815 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 816 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 817 818 /* Bit 17:18 - Defines other actions */ 819 /* Other action = 0 - Mirror VSI */ 820 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 821 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 822 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 823 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 824 825 /* Other action = 3 - Set Stat count */ 826 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 827 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 828 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 829 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 830 831 __le16 index; /* The index of the rule in the lookup table */ 832 /* Length and values of the header to be matched per recipe or 833 * lookup-type 834 */ 835 __le16 hdr_len; 836 u8 hdr[1]; 837 }; 838 #pragma pack() 839 840 /* Add/Update/Remove large action command/response entry 841 * "index" is returned as part of a response to a successful Add command, and 842 * can be used to identify the action for Update/Get/Remove commands. 843 */ 844 struct ice_sw_rule_lg_act { 845 __le16 index; /* Index in large action table */ 846 __le16 size; 847 __le32 act[1]; /* array of size for actions */ 848 /* Max number of large actions */ 849 #define ICE_MAX_LG_ACT 4 850 /* Bit 0:1 - Action type */ 851 #define ICE_LG_ACT_TYPE_S 0 852 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 853 854 /* Action type = 0 - Forward to VSI or VSI list */ 855 #define ICE_LG_ACT_VSI_FORWARDING 0 856 #define ICE_LG_ACT_VSI_ID_S 3 857 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 858 #define ICE_LG_ACT_VSI_LIST_ID_S 3 859 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 860 /* This bit needs to be set if action is forward to VSI list */ 861 #define ICE_LG_ACT_VSI_LIST BIT(13) 862 863 #define ICE_LG_ACT_VALID_BIT BIT(16) 864 865 /* Action type = 1 - Forward to Queue of Queue group */ 866 #define ICE_LG_ACT_TO_Q 0x1 867 #define ICE_LG_ACT_Q_INDEX_S 3 868 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 869 #define ICE_LG_ACT_Q_REGION_S 14 870 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 871 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 872 873 /* Action type = 2 - Prune */ 874 #define ICE_LG_ACT_PRUNE 0x2 875 #define ICE_LG_ACT_EGRESS BIT(14) 876 #define ICE_LG_ACT_INGRESS BIT(15) 877 #define ICE_LG_ACT_PRUNET BIT(16) 878 879 /* Action type = 3 - Mirror VSI */ 880 #define ICE_LG_OTHER_ACT_MIRROR 0x3 881 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 882 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 883 884 /* Action type = 5 - Generic Value */ 885 #define ICE_LG_ACT_GENERIC 0x5 886 #define ICE_LG_ACT_GENERIC_VALUE_S 3 887 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 888 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 889 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 890 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 891 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 892 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 893 894 /* Action = 7 - Set Stat count */ 895 #define ICE_LG_ACT_STAT_COUNT 0x7 896 #define ICE_LG_ACT_STAT_COUNT_S 3 897 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 898 }; 899 900 /* Add/Update/Remove VSI list command/response entry 901 * "index" is returned as part of a response to a successful Add command, and 902 * can be used to identify the VSI list for Update/Get/Remove commands. 903 */ 904 struct ice_sw_rule_vsi_list { 905 __le16 index; /* Index of VSI/Prune list */ 906 __le16 number_vsi; 907 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 908 }; 909 910 #pragma pack(1) 911 /* Query VSI list command/response entry */ 912 struct ice_sw_rule_vsi_list_query { 913 __le16 index; 914 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 915 }; 916 #pragma pack() 917 918 #pragma pack(1) 919 /* Add switch rule response: 920 * Content of return buffer is same as the input buffer. The status field and 921 * LUT index are updated as part of the response 922 */ 923 struct ice_aqc_sw_rules_elem { 924 __le16 type; /* Switch rule type, one of T_... */ 925 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 926 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 927 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 928 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 929 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 930 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 931 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 932 __le16 status; 933 union { 934 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 935 struct ice_sw_rule_lg_act lg_act; 936 struct ice_sw_rule_vsi_list vsi_list; 937 struct ice_sw_rule_vsi_list_query vsi_list_query; 938 } pdata; 939 }; 940 941 #pragma pack() 942 943 /* PFC Ignore (direct 0x0301) 944 * The command and response use the same descriptor structure 945 */ 946 struct ice_aqc_pfc_ignore { 947 u8 tc_bitmap; 948 u8 cmd_flags; /* unused in response */ 949 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 950 #define ICE_AQC_PFC_IGNORE_CLEAR 0 951 u8 reserved[14]; 952 }; 953 954 /* Set PFC Mode (direct 0x0303) 955 * Query PFC Mode (direct 0x0302) 956 */ 957 struct ice_aqc_set_query_pfc_mode { 958 u8 pfc_mode; 959 /* For Set Command response, reserved in all other cases */ 960 #define ICE_AQC_PFC_NOT_CONFIGURED 0 961 /* For Query Command response, reserved in all other cases */ 962 #define ICE_AQC_DCB_DIS 0 963 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 964 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 965 u8 rsvd[15]; 966 }; 967 968 /* Set DCB Parameters (direct 0x0306) */ 969 struct ice_aqc_set_dcb_params { 970 u8 cmd_flags; /* unused in response */ 971 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 972 u8 valid_flags; /* unused in response */ 973 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 974 u8 rsvd[14]; 975 }; 976 977 /* Get Default Topology (indirect 0x0400) */ 978 struct ice_aqc_get_topo { 979 u8 port_num; 980 u8 num_branches; 981 __le16 reserved1; 982 __le32 reserved2; 983 __le32 addr_high; 984 __le32 addr_low; 985 }; 986 987 /* Update TSE (indirect 0x0403) 988 * Get TSE (indirect 0x0404) 989 * Add TSE (indirect 0x0401) 990 * Delete TSE (indirect 0x040F) 991 * Move TSE (indirect 0x0408) 992 * Suspend Nodes (indirect 0x0409) 993 * Resume Nodes (indirect 0x040A) 994 */ 995 struct ice_aqc_sched_elem_cmd { 996 __le16 num_elem_req; /* Used by commands */ 997 __le16 num_elem_resp; /* Used by responses */ 998 __le32 reserved; 999 __le32 addr_high; 1000 __le32 addr_low; 1001 }; 1002 1003 /* This is the buffer for: 1004 * Suspend Nodes (indirect 0x0409) 1005 * Resume Nodes (indirect 0x040A) 1006 */ 1007 struct ice_aqc_suspend_resume_elem { 1008 __le32 teid[1]; 1009 }; 1010 1011 struct ice_aqc_txsched_move_grp_info_hdr { 1012 __le32 src_parent_teid; 1013 __le32 dest_parent_teid; 1014 __le16 num_elems; 1015 __le16 reserved; 1016 }; 1017 1018 struct ice_aqc_move_elem { 1019 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1020 __le32 teid[1]; 1021 }; 1022 1023 struct ice_aqc_elem_info_bw { 1024 __le16 bw_profile_idx; 1025 __le16 bw_alloc; 1026 }; 1027 1028 struct ice_aqc_txsched_elem { 1029 u8 elem_type; /* Special field, reserved for some aq calls */ 1030 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1031 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1032 #define ICE_AQC_ELEM_TYPE_TC 0x2 1033 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1034 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1035 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1036 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1037 u8 valid_sections; 1038 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1039 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1040 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1041 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1042 u8 generic; 1043 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1044 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1045 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1046 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1047 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1048 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1049 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1050 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1051 u8 flags; /* Special field, reserved for some aq calls */ 1052 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1053 struct ice_aqc_elem_info_bw cir_bw; 1054 struct ice_aqc_elem_info_bw eir_bw; 1055 __le16 srl_id; 1056 __le16 reserved2; 1057 }; 1058 1059 struct ice_aqc_txsched_elem_data { 1060 __le32 parent_teid; 1061 __le32 node_teid; 1062 struct ice_aqc_txsched_elem data; 1063 }; 1064 1065 struct ice_aqc_txsched_topo_grp_info_hdr { 1066 __le32 parent_teid; 1067 __le16 num_elems; 1068 __le16 reserved2; 1069 }; 1070 1071 struct ice_aqc_add_elem { 1072 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1073 struct ice_aqc_txsched_elem_data generic[1]; 1074 }; 1075 1076 struct ice_aqc_conf_elem { 1077 struct ice_aqc_txsched_elem_data generic[1]; 1078 }; 1079 1080 struct ice_aqc_get_elem { 1081 struct ice_aqc_txsched_elem_data generic[1]; 1082 }; 1083 1084 struct ice_aqc_get_topo_elem { 1085 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1086 struct ice_aqc_txsched_elem_data 1087 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1088 }; 1089 1090 struct ice_aqc_delete_elem { 1091 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1092 __le32 teid[1]; 1093 }; 1094 1095 /* Query Port ETS (indirect 0x040E) 1096 * 1097 * This indirect command is used to query port TC node configuration. 1098 */ 1099 struct ice_aqc_query_port_ets { 1100 __le32 port_teid; 1101 __le32 reserved; 1102 __le32 addr_high; 1103 __le32 addr_low; 1104 }; 1105 1106 struct ice_aqc_port_ets_elem { 1107 u8 tc_valid_bits; 1108 u8 reserved[3]; 1109 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1110 __le32 up2tc; 1111 u8 tc_bw_share[8]; 1112 __le32 port_eir_prof_id; 1113 __le32 port_cir_prof_id; 1114 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1115 __le32 tc_node_prio; 1116 #define ICE_TC_NODE_PRIO_S 0x4 1117 u8 reserved1[4]; 1118 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1119 }; 1120 1121 /* Rate limiting profile for 1122 * Add RL profile (indirect 0x0410) 1123 * Query RL profile (indirect 0x0411) 1124 * Remove RL profile (indirect 0x0415) 1125 * These indirect commands acts on single or multiple 1126 * RL profiles with specified data. 1127 */ 1128 struct ice_aqc_rl_profile { 1129 __le16 num_profiles; 1130 __le16 num_processed; /* Only for response. Reserved in Command. */ 1131 u8 reserved[4]; 1132 __le32 addr_high; 1133 __le32 addr_low; 1134 }; 1135 1136 struct ice_aqc_rl_profile_elem { 1137 u8 level; 1138 u8 flags; 1139 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1140 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1141 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1142 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1143 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1144 /* The following flag is used for Query RL Profile Data */ 1145 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1146 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1147 1148 __le16 profile_id; 1149 __le16 max_burst_size; 1150 __le16 rl_multiply; 1151 __le16 wake_up_calc; 1152 __le16 rl_encode; 1153 }; 1154 1155 struct ice_aqc_rl_profile_generic_elem { 1156 struct ice_aqc_rl_profile_elem generic[1]; 1157 }; 1158 1159 /* Configure L2 Node CGD (indirect 0x0414) 1160 * This indirect command allows configuring a congestion domain for given L2 1161 * node TEIDs in the scheduler topology. 1162 */ 1163 struct ice_aqc_cfg_l2_node_cgd { 1164 __le16 num_l2_nodes; 1165 u8 reserved[6]; 1166 __le32 addr_high; 1167 __le32 addr_low; 1168 }; 1169 1170 struct ice_aqc_cfg_l2_node_cgd_elem { 1171 __le32 node_teid; 1172 u8 cgd; 1173 u8 reserved[3]; 1174 }; 1175 1176 struct ice_aqc_cfg_l2_node_cgd_data { 1177 struct ice_aqc_cfg_l2_node_cgd_elem elem[1]; 1178 }; 1179 1180 /* Query Scheduler Resource Allocation (indirect 0x0412) 1181 * This indirect command retrieves the scheduler resources allocated by 1182 * EMP Firmware to the given PF. 1183 */ 1184 struct ice_aqc_query_txsched_res { 1185 u8 reserved[8]; 1186 __le32 addr_high; 1187 __le32 addr_low; 1188 }; 1189 1190 struct ice_aqc_generic_sched_props { 1191 __le16 phys_levels; 1192 __le16 logical_levels; 1193 u8 flattening_bitmap; 1194 u8 max_device_cgds; 1195 u8 max_pf_cgds; 1196 u8 rsvd0; 1197 __le16 rdma_qsets; 1198 u8 rsvd1[22]; 1199 }; 1200 1201 struct ice_aqc_layer_props { 1202 u8 logical_layer; 1203 u8 chunk_size; 1204 __le16 max_device_nodes; 1205 __le16 max_pf_nodes; 1206 u8 rsvd0[4]; 1207 __le16 max_sibl_grp_sz; 1208 __le16 max_cir_rl_profiles; 1209 __le16 max_eir_rl_profiles; 1210 __le16 max_srl_profiles; 1211 u8 rsvd1[14]; 1212 }; 1213 1214 struct ice_aqc_query_txsched_res_resp { 1215 struct ice_aqc_generic_sched_props sched_props; 1216 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1217 }; 1218 1219 /* Query Node to Root Topology (indirect 0x0413) 1220 * This command uses ice_aqc_get_elem as its data buffer. 1221 */ 1222 struct ice_aqc_query_node_to_root { 1223 __le32 teid; 1224 __le32 num_nodes; /* Response only */ 1225 __le32 addr_high; 1226 __le32 addr_low; 1227 }; 1228 1229 /* Get PHY capabilities (indirect 0x0600) */ 1230 struct ice_aqc_get_phy_caps { 1231 u8 lport_num; 1232 u8 reserved; 1233 __le16 param0; 1234 /* 18.0 - Report qualified modules */ 1235 #define ICE_AQC_GET_PHY_RQM BIT(0) 1236 /* 18.1 - 18.2 : Report mode 1237 * 00b - Report NVM capabilities 1238 * 01b - Report topology capabilities 1239 * 10b - Report SW configured 1240 */ 1241 #define ICE_AQC_REPORT_MODE_S 1 1242 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 1243 #define ICE_AQC_REPORT_NVM_CAP 0 1244 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 1245 #define ICE_AQC_REPORT_SW_CFG BIT(2) 1246 __le32 reserved1; 1247 __le32 addr_high; 1248 __le32 addr_low; 1249 }; 1250 1251 /* This is #define of PHY type (Extended): 1252 * The first set of defines is for phy_type_low. 1253 */ 1254 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1255 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1256 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1257 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1258 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1259 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1260 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1261 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1262 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1263 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1264 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1265 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1266 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1267 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1268 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1269 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1270 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1271 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1272 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1273 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1274 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1275 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1276 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1277 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1278 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1279 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1280 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1281 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1282 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1283 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1284 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1285 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1286 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1287 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1288 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1289 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1290 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1291 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1292 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1293 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1294 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1295 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1296 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1297 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1298 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1299 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1300 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1301 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1302 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1303 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1304 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1305 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1306 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1307 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1308 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1309 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1310 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1311 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1312 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1313 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1314 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1315 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1316 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1317 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1318 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1319 /* The second set of defines is for phy_type_high. */ 1320 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1321 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1322 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1323 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1324 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1325 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 1326 1327 struct ice_aqc_get_phy_caps_data { 1328 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1329 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1330 u8 caps; 1331 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1332 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1333 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1334 #define ICE_AQC_PHY_EN_LINK BIT(3) 1335 #define ICE_AQC_PHY_AN_MODE BIT(4) 1336 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1337 #define ICE_AQC_PHY_EN_LESM BIT(6) 1338 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1339 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1340 u8 low_power_ctrl; 1341 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1342 __le16 eee_cap; 1343 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1344 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1345 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1346 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1347 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1348 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1349 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1350 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1351 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1352 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1353 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1354 __le16 eeer_value; 1355 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1356 u8 phy_fw_ver[8]; 1357 u8 link_fec_options; 1358 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1359 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1360 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1361 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1362 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1363 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1364 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1365 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1366 u8 rsvd1; /* Byte 35 reserved */ 1367 u8 extended_compliance_code; 1368 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1369 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1370 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1371 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1372 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1373 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1374 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1375 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1376 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1377 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1378 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1379 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1380 u8 qualified_module_count; 1381 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1382 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1383 struct { 1384 u8 v_oui[3]; 1385 u8 rsvd3; 1386 u8 v_part[16]; 1387 __le32 v_rev; 1388 __le64 rsvd4; 1389 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1390 }; 1391 1392 /* Set PHY capabilities (direct 0x0601) 1393 * NOTE: This command must be followed by setup link and restart auto-neg 1394 */ 1395 struct ice_aqc_set_phy_cfg { 1396 u8 lport_num; 1397 u8 reserved[7]; 1398 __le32 addr_high; 1399 __le32 addr_low; 1400 }; 1401 1402 /* Set PHY config command data structure */ 1403 struct ice_aqc_set_phy_cfg_data { 1404 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1405 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1406 u8 caps; 1407 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1408 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1409 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1410 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1411 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1412 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1413 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1414 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1415 u8 low_power_ctrl; 1416 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1417 __le16 eeer_value; 1418 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1419 u8 rsvd1; 1420 }; 1421 1422 /* Set MAC Config command data structure (direct 0x0603) */ 1423 struct ice_aqc_set_mac_cfg { 1424 __le16 max_frame_size; 1425 u8 params; 1426 #define ICE_AQ_SET_MAC_PACE_S 3 1427 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1428 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1429 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1430 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1431 u8 tx_tmr_priority; 1432 __le16 tx_tmr_value; 1433 __le16 fc_refresh_threshold; 1434 u8 drop_opts; 1435 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1436 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1437 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1438 u8 reserved[7]; 1439 }; 1440 1441 /* Restart AN command data structure (direct 0x0605) 1442 * Also used for response, with only the lport_num field present. 1443 */ 1444 struct ice_aqc_restart_an { 1445 u8 lport_num; 1446 u8 reserved; 1447 u8 cmd_flags; 1448 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1449 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1450 u8 reserved2[13]; 1451 }; 1452 1453 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1454 struct ice_aqc_get_link_status { 1455 u8 lport_num; 1456 u8 reserved; 1457 __le16 cmd_flags; 1458 #define ICE_AQ_LSE_M 0x3 1459 #define ICE_AQ_LSE_NOP 0x0 1460 #define ICE_AQ_LSE_DIS 0x2 1461 #define ICE_AQ_LSE_ENA 0x3 1462 /* only response uses this flag */ 1463 #define ICE_AQ_LSE_IS_ENABLED 0x1 1464 __le32 reserved2; 1465 __le32 addr_high; 1466 __le32 addr_low; 1467 }; 1468 1469 /* Get link status response data structure, also used for Link Status Event */ 1470 struct ice_aqc_get_link_status_data { 1471 u8 topo_media_conflict; 1472 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1473 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1474 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1475 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1476 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1477 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1478 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1479 u8 link_cfg_err; 1480 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1481 u8 link_info; 1482 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1483 #define ICE_AQ_LINK_FAULT BIT(1) 1484 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1485 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1486 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1487 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1488 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1489 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1490 u8 an_info; 1491 #define ICE_AQ_AN_COMPLETED BIT(0) 1492 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1493 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1494 #define ICE_AQ_FEC_EN BIT(3) 1495 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1496 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1497 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1498 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1499 u8 ext_info; 1500 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1501 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1502 /* Port Tx Suspended */ 1503 #define ICE_AQ_LINK_TX_S 2 1504 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1505 #define ICE_AQ_LINK_TX_ACTIVE 0 1506 #define ICE_AQ_LINK_TX_DRAINED 1 1507 #define ICE_AQ_LINK_TX_FLUSHED 3 1508 u8 lb_status; 1509 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1510 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1511 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1512 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1513 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1514 __le16 max_frame_size; 1515 u8 cfg; 1516 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1517 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1518 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1519 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1520 /* Pacing Config */ 1521 #define ICE_AQ_CFG_PACING_S 3 1522 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1523 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1524 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1525 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1526 /* External Device Power Ability */ 1527 u8 power_desc; 1528 #define ICE_AQ_PWR_CLASS_M 0x3 1529 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1530 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1531 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1532 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1533 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1534 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1535 __le16 link_speed; 1536 #define ICE_AQ_LINK_SPEED_M 0x7FF 1537 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1538 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1539 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1540 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1541 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1542 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1543 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1544 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1545 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1546 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1547 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1548 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1549 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1550 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1551 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1552 }; 1553 1554 /* Set event mask command (direct 0x0613) */ 1555 struct ice_aqc_set_event_mask { 1556 u8 lport_num; 1557 u8 reserved[7]; 1558 __le16 event_mask; 1559 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1560 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1561 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1562 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1563 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1564 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1565 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1566 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1567 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1568 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1569 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1570 u8 reserved1[6]; 1571 }; 1572 1573 /* Set MAC Loopback command (direct 0x0620) */ 1574 struct ice_aqc_set_mac_lb { 1575 u8 lb_mode; 1576 #define ICE_AQ_MAC_LB_EN BIT(0) 1577 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1578 u8 reserved[15]; 1579 }; 1580 1581 struct ice_aqc_link_topo_addr { 1582 u8 lport_num; 1583 u8 lport_num_valid; 1584 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1585 u8 node_type_ctx; 1586 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1587 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1588 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1589 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1590 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1591 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1592 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1593 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1594 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1595 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1596 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1597 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1598 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1599 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1600 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1601 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1602 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1603 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1604 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1605 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1606 u8 index; 1607 __le16 handle; 1608 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1609 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1610 /* Used to decode the handle field */ 1611 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1612 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1613 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1614 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1615 /* In case of a Mezzanine type */ 1616 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1617 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1618 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1619 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1620 /* In case of a LOM type */ 1621 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1622 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1623 }; 1624 1625 /* Get Link Topology Handle (direct, 0x06E0) */ 1626 struct ice_aqc_get_link_topo { 1627 struct ice_aqc_link_topo_addr addr; 1628 u8 node_part_num; 1629 u8 rsvd[9]; 1630 }; 1631 1632 /* Set Port Identification LED (direct, 0x06E9) */ 1633 struct ice_aqc_set_port_id_led { 1634 u8 lport_num; 1635 u8 lport_num_valid; 1636 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1637 u8 ident_mode; 1638 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1639 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1640 u8 rsvd[13]; 1641 }; 1642 1643 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1644 struct ice_aqc_sff_eeprom { 1645 u8 lport_num; 1646 u8 lport_num_valid; 1647 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1648 __le16 i2c_bus_addr; 1649 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1650 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1651 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1652 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1653 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1654 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1655 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1656 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1657 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1658 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1659 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1660 __le16 i2c_mem_addr; 1661 __le16 eeprom_page; 1662 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1663 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1664 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1665 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1666 __le32 addr_high; 1667 __le32 addr_low; 1668 }; 1669 1670 /* NVM Read command (indirect 0x0701) 1671 * NVM Erase commands (direct 0x0702) 1672 * NVM Write commands (indirect 0x0703) 1673 * NVM Write Activate commands (direct 0x0707) 1674 * NVM Shadow RAM Dump commands (direct 0x0707) 1675 */ 1676 struct ice_aqc_nvm { 1677 __le16 offset_low; 1678 u8 offset_high; 1679 u8 cmd_flags; 1680 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1681 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 1682 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 1683 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1684 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1685 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1686 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1687 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1688 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1689 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1690 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1691 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1692 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 1693 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1694 __le16 module_typeid; 1695 __le16 length; 1696 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1697 __le32 addr_high; 1698 __le32 addr_low; 1699 }; 1700 1701 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 1702 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 1703 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 1704 1705 #define ICE_AQC_NVM_START_POINT 0 1706 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 1707 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 1708 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 1709 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 1710 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 1711 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 1712 1713 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 1714 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 1715 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 1716 1717 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 1718 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 1719 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 1720 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 1721 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 1722 1723 /* Used for 0x0704 as well as for 0x0705 commands */ 1724 struct ice_aqc_nvm_cfg { 1725 u8 cmd_flags; 1726 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 1727 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 1728 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 1729 u8 reserved; 1730 __le16 count; 1731 __le16 id; 1732 u8 reserved1[2]; 1733 __le32 addr_high; 1734 __le32 addr_low; 1735 }; 1736 1737 struct ice_aqc_nvm_cfg_data { 1738 __le16 field_id; 1739 __le16 field_options; 1740 __le16 field_value; 1741 }; 1742 1743 /* NVM Checksum Command (direct, 0x0706) */ 1744 struct ice_aqc_nvm_checksum { 1745 u8 flags; 1746 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1747 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1748 u8 rsvd; 1749 __le16 checksum; /* Used only by response */ 1750 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1751 u8 rsvd2[12]; 1752 }; 1753 1754 /* Get LLDP MIB (indirect 0x0A00) 1755 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1756 * as the format is the same. 1757 */ 1758 struct ice_aqc_lldp_get_mib { 1759 u8 type; 1760 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1761 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1762 #define ICE_AQ_LLDP_MIB_LOCAL 0 1763 #define ICE_AQ_LLDP_MIB_REMOTE 1 1764 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1765 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1766 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1767 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1768 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1769 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1770 #define ICE_AQ_LLDP_TX_S 0x4 1771 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1772 #define ICE_AQ_LLDP_TX_ACTIVE 0 1773 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1774 #define ICE_AQ_LLDP_TX_FLUSHED 3 1775 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1776 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1777 * Get LLDP MIB (0x0A00) response only. 1778 */ 1779 u8 reserved1; 1780 __le16 local_len; 1781 __le16 remote_len; 1782 u8 reserved2[2]; 1783 __le32 addr_high; 1784 __le32 addr_low; 1785 }; 1786 1787 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1788 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1789 struct ice_aqc_lldp_set_mib_change { 1790 u8 command; 1791 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1792 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1793 u8 reserved[15]; 1794 }; 1795 1796 /* Add LLDP TLV (indirect 0x0A02) 1797 * Delete LLDP TLV (indirect 0x0A04) 1798 */ 1799 struct ice_aqc_lldp_add_delete_tlv { 1800 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1801 u8 reserved1[1]; 1802 __le16 len; 1803 u8 reserved2[4]; 1804 __le32 addr_high; 1805 __le32 addr_low; 1806 }; 1807 1808 /* Update LLDP TLV (indirect 0x0A03) */ 1809 struct ice_aqc_lldp_update_tlv { 1810 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1811 u8 reserved; 1812 __le16 old_len; 1813 __le16 new_offset; 1814 __le16 new_len; 1815 __le32 addr_high; 1816 __le32 addr_low; 1817 }; 1818 1819 /* Stop LLDP (direct 0x0A05) */ 1820 struct ice_aqc_lldp_stop { 1821 u8 command; 1822 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1823 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1824 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1825 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1826 u8 reserved[15]; 1827 }; 1828 1829 /* Start LLDP (direct 0x0A06) */ 1830 struct ice_aqc_lldp_start { 1831 u8 command; 1832 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1833 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1834 u8 reserved[15]; 1835 }; 1836 1837 /* Get CEE DCBX Oper Config (0x0A07) 1838 * The command uses the generic descriptor struct and 1839 * returns the struct below as an indirect response. 1840 */ 1841 struct ice_aqc_get_cee_dcb_cfg_resp { 1842 u8 oper_num_tc; 1843 u8 oper_prio_tc[4]; 1844 u8 oper_tc_bw[8]; 1845 u8 oper_pfc_en; 1846 __le16 oper_app_prio; 1847 #define ICE_AQC_CEE_APP_FCOE_S 0 1848 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1849 #define ICE_AQC_CEE_APP_ISCSI_S 3 1850 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1851 #define ICE_AQC_CEE_APP_FIP_S 8 1852 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1853 __le32 tlv_status; 1854 #define ICE_AQC_CEE_PG_STATUS_S 0 1855 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1856 #define ICE_AQC_CEE_PFC_STATUS_S 3 1857 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1858 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1859 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1860 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1861 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1862 #define ICE_AQC_CEE_FIP_STATUS_S 16 1863 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1864 u8 reserved[12]; 1865 }; 1866 1867 /* Set Local LLDP MIB (indirect 0x0A08) 1868 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1869 */ 1870 struct ice_aqc_lldp_set_local_mib { 1871 u8 type; 1872 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1873 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1874 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1875 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1876 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1877 u8 reserved0; 1878 __le16 length; 1879 u8 reserved1[4]; 1880 __le32 addr_high; 1881 __le32 addr_low; 1882 }; 1883 1884 struct ice_aqc_lldp_set_local_mib_resp { 1885 u8 status; 1886 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 1887 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 1888 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 1889 u8 reserved[15]; 1890 }; 1891 1892 /* Stop/Start LLDP Agent (direct 0x0A09) 1893 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1894 * The same structure is used for the response, with the command field 1895 * being used as the status field. 1896 */ 1897 struct ice_aqc_lldp_stop_start_specific_agent { 1898 u8 command; 1899 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1900 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1901 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1902 u8 reserved[15]; 1903 }; 1904 1905 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1906 struct ice_aqc_get_set_rss_key { 1907 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1908 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1909 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1910 __le16 vsi_id; 1911 u8 reserved[6]; 1912 __le32 addr_high; 1913 __le32 addr_low; 1914 }; 1915 1916 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1917 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1918 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1919 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1920 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1921 1922 /** 1923 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 1924 * @standard_rss_key: 40 most significant bytes of hash key 1925 * @extended_hash_key: 12 least significant bytes of hash key 1926 * 1927 * Set/Get 40 byte hash key using standard_rss_key field, and set 1928 * extended_hash_key field to zero. Set/Get 52 byte hash key using 1929 * standard_rss_key field for 40 most significant bytes and the 1930 * extended_hash_key field for the 12 least significant bytes of hash key. 1931 */ 1932 struct ice_aqc_get_set_rss_keys { 1933 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1934 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1935 }; 1936 1937 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1938 struct ice_aqc_get_set_rss_lut { 1939 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1940 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1941 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1942 __le16 vsi_id; 1943 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1944 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1945 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1946 1947 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1948 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1949 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1950 1951 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1952 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1953 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1954 1955 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1956 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1957 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1958 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1959 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1960 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1961 1962 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1963 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1964 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1965 1966 __le16 flags; 1967 __le32 reserved; 1968 __le32 addr_high; 1969 __le32 addr_low; 1970 }; 1971 1972 /* Clear FD Table Command (direct, 0x0B06) */ 1973 struct ice_aqc_clear_fd_table { 1974 u8 clear_type; 1975 #define CL_FD_VM_VF_TYPE_VSI_IDX 1 1976 #define CL_FD_VM_VF_TYPE_PF_IDX 2 1977 u8 rsvd; 1978 __le16 vsi_index; 1979 u8 reserved[12]; 1980 }; 1981 1982 /* Add Tx LAN Queues (indirect 0x0C30) */ 1983 struct ice_aqc_add_txqs { 1984 u8 num_qgrps; 1985 u8 reserved[3]; 1986 __le32 reserved1; 1987 __le32 addr_high; 1988 __le32 addr_low; 1989 }; 1990 1991 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1992 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1993 */ 1994 struct ice_aqc_add_txqs_perq { 1995 __le16 txq_id; 1996 u8 rsvd[2]; 1997 __le32 q_teid; 1998 u8 txq_ctx[22]; 1999 u8 rsvd2[2]; 2000 struct ice_aqc_txsched_elem info; 2001 }; 2002 2003 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2004 * is an array of the following structs. Please note that the length of 2005 * each struct ice_aqc_add_tx_qgrp is variable due 2006 * to the variable number of queues in each group! 2007 */ 2008 struct ice_aqc_add_tx_qgrp { 2009 __le32 parent_teid; 2010 u8 num_txqs; 2011 u8 rsvd[3]; 2012 struct ice_aqc_add_txqs_perq txqs[1]; 2013 }; 2014 2015 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2016 struct ice_aqc_dis_txqs { 2017 u8 cmd_type; 2018 #define ICE_AQC_Q_DIS_CMD_S 0 2019 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2020 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2021 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2022 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2023 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2024 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2025 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2026 u8 num_entries; 2027 __le16 vmvf_and_timeout; 2028 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2029 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2030 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2031 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2032 __le32 blocked_cgds; 2033 __le32 addr_high; 2034 __le32 addr_low; 2035 }; 2036 2037 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2038 * contains the following structures, arrayed one after the 2039 * other. 2040 * Note: Since the q_id is 16 bits wide, if the 2041 * number of queues is even, then 2 bytes of alignment MUST be 2042 * added before the start of the next group, to allow correct 2043 * alignment of the parent_teid field. 2044 */ 2045 struct ice_aqc_dis_txq_item { 2046 __le32 parent_teid; 2047 u8 num_qs; 2048 u8 rsvd; 2049 /* The length of the q_id array varies according to num_qs */ 2050 __le16 q_id[1]; 2051 /* This only applies from F8 onward */ 2052 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2053 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2054 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2055 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2056 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2057 }; 2058 2059 struct ice_aqc_dis_txq { 2060 struct ice_aqc_dis_txq_item qgrps[1]; 2061 }; 2062 2063 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2064 struct ice_aqc_txqs_cleanup { 2065 __le16 caller_opc; 2066 __le16 cmd_tag; 2067 u8 reserved[12]; 2068 }; 2069 2070 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2071 struct ice_aqc_move_txqs { 2072 u8 cmd_type; 2073 #define ICE_AQC_Q_CMD_TYPE_S 0 2074 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2075 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2076 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2077 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2078 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2079 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2080 u8 num_qs; 2081 u8 rsvd; 2082 u8 timeout; 2083 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2084 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2085 __le32 blocked_cgds; 2086 __le32 addr_high; 2087 __le32 addr_low; 2088 }; 2089 2090 /* This is the descriptor of each queue entry for the move Tx LAN Queues 2091 * command (0x0C32). 2092 */ 2093 struct ice_aqc_move_txqs_elem { 2094 __le16 txq_id; 2095 u8 q_cgd; 2096 u8 rsvd; 2097 __le32 q_teid; 2098 }; 2099 2100 struct ice_aqc_move_txqs_data { 2101 __le32 src_teid; 2102 __le32 dest_teid; 2103 struct ice_aqc_move_txqs_elem txqs[1]; 2104 }; 2105 2106 /* Download Package (indirect 0x0C40) */ 2107 /* Also used for Update Package (indirect 0x0C42) */ 2108 struct ice_aqc_download_pkg { 2109 u8 flags; 2110 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2111 u8 reserved[3]; 2112 __le32 reserved1; 2113 __le32 addr_high; 2114 __le32 addr_low; 2115 }; 2116 2117 struct ice_aqc_download_pkg_resp { 2118 __le32 error_offset; 2119 __le32 error_info; 2120 __le32 addr_high; 2121 __le32 addr_low; 2122 }; 2123 2124 /* Get Package Info List (indirect 0x0C43) */ 2125 struct ice_aqc_get_pkg_info_list { 2126 __le32 reserved1; 2127 __le32 reserved2; 2128 __le32 addr_high; 2129 __le32 addr_low; 2130 }; 2131 2132 /* Version format for packages */ 2133 struct ice_pkg_ver { 2134 u8 major; 2135 u8 minor; 2136 u8 update; 2137 u8 draft; 2138 }; 2139 2140 #define ICE_PKG_NAME_SIZE 32 2141 2142 struct ice_aqc_get_pkg_info { 2143 struct ice_pkg_ver ver; 2144 char name[ICE_PKG_NAME_SIZE]; 2145 u8 is_in_nvm; 2146 u8 is_active; 2147 u8 is_active_at_boot; 2148 u8 is_modified; 2149 }; 2150 2151 /* Get Package Info List response buffer format (0x0C43) */ 2152 struct ice_aqc_get_pkg_info_resp { 2153 __le32 count; 2154 struct ice_aqc_get_pkg_info pkg_info[1]; 2155 }; 2156 2157 /* Lan Queue Overflow Event (direct, 0x1001) */ 2158 struct ice_aqc_event_lan_overflow { 2159 __le32 prtdcb_ruptq; 2160 __le32 qtx_ctl; 2161 u8 reserved[8]; 2162 }; 2163 2164 /** 2165 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2166 * @flags: ICE_AQ_FLAG_* flags 2167 * @opcode: AQ command opcode 2168 * @datalen: length in bytes of indirect/external data buffer 2169 * @retval: return value from firmware 2170 * @cookie_h: opaque data high-half 2171 * @cookie_l: opaque data low-half 2172 * @params: command-specific parameters 2173 * 2174 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2175 * (ATQ). The firmware writes back onto the command descriptor and returns 2176 * the result of the command. Asynchronous events that are not an immediate 2177 * result of the command are written to the Admin Receive Queue (ARQ) using 2178 * the same descriptor format. Descriptors are in little-endian notation with 2179 * 32-bit words. 2180 */ 2181 struct ice_aq_desc { 2182 __le16 flags; 2183 __le16 opcode; 2184 __le16 datalen; 2185 __le16 retval; 2186 __le32 cookie_high; 2187 __le32 cookie_low; 2188 union { 2189 u8 raw[16]; 2190 struct ice_aqc_generic generic; 2191 struct ice_aqc_get_ver get_ver; 2192 struct ice_aqc_driver_ver driver_ver; 2193 struct ice_aqc_q_shutdown q_shutdown; 2194 struct ice_aqc_req_res res_owner; 2195 struct ice_aqc_manage_mac_read mac_read; 2196 struct ice_aqc_manage_mac_write mac_write; 2197 struct ice_aqc_clear_pxe clear_pxe; 2198 struct ice_aqc_config_no_drop_policy no_drop; 2199 struct ice_aqc_add_update_mir_rule add_update_rule; 2200 struct ice_aqc_delete_mir_rule del_rule; 2201 struct ice_aqc_list_caps get_cap; 2202 struct ice_aqc_get_phy_caps get_phy; 2203 struct ice_aqc_set_phy_cfg set_phy; 2204 struct ice_aqc_restart_an restart_an; 2205 struct ice_aqc_sff_eeprom read_write_sff_param; 2206 struct ice_aqc_set_port_id_led set_port_id_led; 2207 struct ice_aqc_get_sw_cfg get_sw_conf; 2208 struct ice_aqc_sw_rules sw_rules; 2209 struct ice_aqc_storm_cfg storm_conf; 2210 struct ice_aqc_add_get_recipe add_get_recipe; 2211 struct ice_aqc_recipe_to_profile recipe_to_profile; 2212 struct ice_aqc_get_topo get_topo; 2213 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2214 struct ice_aqc_query_txsched_res query_sched_res; 2215 struct ice_aqc_query_node_to_root query_node_to_root; 2216 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2217 struct ice_aqc_query_port_ets port_ets; 2218 struct ice_aqc_rl_profile rl_profile; 2219 struct ice_aqc_nvm nvm; 2220 struct ice_aqc_nvm_cfg nvm_cfg; 2221 struct ice_aqc_nvm_checksum nvm_checksum; 2222 struct ice_aqc_pfc_ignore pfc_ignore; 2223 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2224 struct ice_aqc_set_dcb_params set_dcb_params; 2225 struct ice_aqc_lldp_get_mib lldp_get_mib; 2226 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2227 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2228 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2229 struct ice_aqc_lldp_stop lldp_stop; 2230 struct ice_aqc_lldp_start lldp_start; 2231 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2232 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2233 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2234 struct ice_aqc_get_set_rss_key get_set_rss_key; 2235 struct ice_aqc_clear_fd_table clear_fd_table; 2236 struct ice_aqc_add_txqs add_txqs; 2237 struct ice_aqc_dis_txqs dis_txqs; 2238 struct ice_aqc_move_txqs move_txqs; 2239 struct ice_aqc_txqs_cleanup txqs_cleanup; 2240 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2241 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2242 struct ice_aqc_get_vsi_resp get_vsi_resp; 2243 struct ice_aqc_download_pkg download_pkg; 2244 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2245 struct ice_aqc_set_mac_lb set_mac_lb; 2246 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2247 struct ice_aqc_get_res_alloc get_res; 2248 struct ice_aqc_get_allocd_res_desc get_res_desc; 2249 struct ice_aqc_set_mac_cfg set_mac_cfg; 2250 struct ice_aqc_set_event_mask set_event_mask; 2251 struct ice_aqc_get_link_status get_link_status; 2252 struct ice_aqc_event_lan_overflow lan_overflow; 2253 struct ice_aqc_get_link_topo get_link_topo; 2254 } params; 2255 }; 2256 2257 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2258 #define ICE_AQ_LG_BUF 512 2259 2260 /* Flags sub-structure 2261 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2262 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2263 */ 2264 2265 /* command flags and offsets */ 2266 #define ICE_AQ_FLAG_DD_S 0 2267 #define ICE_AQ_FLAG_CMP_S 1 2268 #define ICE_AQ_FLAG_ERR_S 2 2269 #define ICE_AQ_FLAG_VFE_S 3 2270 #define ICE_AQ_FLAG_LB_S 9 2271 #define ICE_AQ_FLAG_RD_S 10 2272 #define ICE_AQ_FLAG_VFC_S 11 2273 #define ICE_AQ_FLAG_BUF_S 12 2274 #define ICE_AQ_FLAG_SI_S 13 2275 #define ICE_AQ_FLAG_EI_S 14 2276 #define ICE_AQ_FLAG_FE_S 15 2277 2278 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2279 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2280 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2281 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2282 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2283 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2284 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2285 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2286 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2287 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2288 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2289 2290 /* error codes */ 2291 enum ice_aq_err { 2292 ICE_AQ_RC_OK = 0, /* Success */ 2293 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2294 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2295 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2296 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2297 ICE_AQ_RC_EIO = 5, /* I/O error */ 2298 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2299 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2300 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2301 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2302 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2303 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2304 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2305 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2306 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2307 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2308 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2309 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2310 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2311 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2312 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2313 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2314 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2315 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2316 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2317 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2318 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2319 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2320 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2321 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2322 }; 2323 2324 /* Admin Queue command opcodes */ 2325 enum ice_adminq_opc { 2326 /* AQ commands */ 2327 ice_aqc_opc_get_ver = 0x0001, 2328 ice_aqc_opc_driver_ver = 0x0002, 2329 ice_aqc_opc_q_shutdown = 0x0003, 2330 ice_aqc_opc_get_exp_err = 0x0005, 2331 2332 /* resource ownership */ 2333 ice_aqc_opc_req_res = 0x0008, 2334 ice_aqc_opc_release_res = 0x0009, 2335 2336 /* device/function capabilities */ 2337 ice_aqc_opc_list_func_caps = 0x000A, 2338 ice_aqc_opc_list_dev_caps = 0x000B, 2339 2340 /* manage MAC address */ 2341 ice_aqc_opc_manage_mac_read = 0x0107, 2342 ice_aqc_opc_manage_mac_write = 0x0108, 2343 2344 /* PXE */ 2345 ice_aqc_opc_clear_pxe_mode = 0x0110, 2346 2347 ice_aqc_opc_config_no_drop_policy = 0x0112, 2348 2349 /* internal switch commands */ 2350 ice_aqc_opc_get_sw_cfg = 0x0200, 2351 2352 /* Alloc/Free/Get Resources */ 2353 ice_aqc_opc_get_res_alloc = 0x0204, 2354 ice_aqc_opc_alloc_res = 0x0208, 2355 ice_aqc_opc_free_res = 0x0209, 2356 ice_aqc_opc_get_allocd_res_desc = 0x020A, 2357 2358 /* VSI commands */ 2359 ice_aqc_opc_add_vsi = 0x0210, 2360 ice_aqc_opc_update_vsi = 0x0211, 2361 ice_aqc_opc_get_vsi_params = 0x0212, 2362 ice_aqc_opc_free_vsi = 0x0213, 2363 2364 /* Mirroring rules - add/update, delete */ 2365 ice_aqc_opc_add_update_mir_rule = 0x0260, 2366 ice_aqc_opc_del_mir_rule = 0x0261, 2367 2368 /* storm configuration */ 2369 ice_aqc_opc_set_storm_cfg = 0x0280, 2370 ice_aqc_opc_get_storm_cfg = 0x0281, 2371 2372 /* recipe commands */ 2373 ice_aqc_opc_add_recipe = 0x0290, 2374 ice_aqc_opc_recipe_to_profile = 0x0291, 2375 ice_aqc_opc_get_recipe = 0x0292, 2376 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2377 2378 /* switch rules population commands */ 2379 ice_aqc_opc_add_sw_rules = 0x02A0, 2380 ice_aqc_opc_update_sw_rules = 0x02A1, 2381 ice_aqc_opc_remove_sw_rules = 0x02A2, 2382 ice_aqc_opc_get_sw_rules = 0x02A3, 2383 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2384 2385 /* DCB commands */ 2386 ice_aqc_opc_pfc_ignore = 0x0301, 2387 ice_aqc_opc_query_pfc_mode = 0x0302, 2388 ice_aqc_opc_set_pfc_mode = 0x0303, 2389 ice_aqc_opc_set_dcb_params = 0x0306, 2390 2391 /* transmit scheduler commands */ 2392 ice_aqc_opc_get_dflt_topo = 0x0400, 2393 ice_aqc_opc_add_sched_elems = 0x0401, 2394 ice_aqc_opc_cfg_sched_elems = 0x0403, 2395 ice_aqc_opc_get_sched_elems = 0x0404, 2396 ice_aqc_opc_move_sched_elems = 0x0408, 2397 ice_aqc_opc_suspend_sched_elems = 0x0409, 2398 ice_aqc_opc_resume_sched_elems = 0x040A, 2399 ice_aqc_opc_query_port_ets = 0x040E, 2400 ice_aqc_opc_delete_sched_elems = 0x040F, 2401 ice_aqc_opc_add_rl_profiles = 0x0410, 2402 ice_aqc_opc_query_rl_profiles = 0x0411, 2403 ice_aqc_opc_query_sched_res = 0x0412, 2404 ice_aqc_opc_query_node_to_root = 0x0413, 2405 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 2406 ice_aqc_opc_remove_rl_profiles = 0x0415, 2407 2408 /* PHY commands */ 2409 ice_aqc_opc_get_phy_caps = 0x0600, 2410 ice_aqc_opc_set_phy_cfg = 0x0601, 2411 ice_aqc_opc_set_mac_cfg = 0x0603, 2412 ice_aqc_opc_restart_an = 0x0605, 2413 ice_aqc_opc_get_link_status = 0x0607, 2414 ice_aqc_opc_set_event_mask = 0x0613, 2415 ice_aqc_opc_set_mac_lb = 0x0620, 2416 ice_aqc_opc_get_link_topo = 0x06E0, 2417 ice_aqc_opc_set_port_id_led = 0x06E9, 2418 ice_aqc_opc_get_port_options = 0x06EA, 2419 ice_aqc_opc_set_port_option = 0x06EB, 2420 ice_aqc_opc_set_gpio = 0x06EC, 2421 ice_aqc_opc_get_gpio = 0x06ED, 2422 ice_aqc_opc_sff_eeprom = 0x06EE, 2423 2424 /* NVM commands */ 2425 ice_aqc_opc_nvm_read = 0x0701, 2426 ice_aqc_opc_nvm_erase = 0x0702, 2427 ice_aqc_opc_nvm_write = 0x0703, 2428 ice_aqc_opc_nvm_cfg_read = 0x0704, 2429 ice_aqc_opc_nvm_cfg_write = 0x0705, 2430 ice_aqc_opc_nvm_checksum = 0x0706, 2431 ice_aqc_opc_nvm_write_activate = 0x0707, 2432 ice_aqc_opc_nvm_sr_dump = 0x0707, 2433 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 2434 ice_aqc_opc_nvm_update_empr = 0x0709, 2435 2436 /* LLDP commands */ 2437 ice_aqc_opc_lldp_get_mib = 0x0A00, 2438 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2439 ice_aqc_opc_lldp_add_tlv = 0x0A02, 2440 ice_aqc_opc_lldp_update_tlv = 0x0A03, 2441 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 2442 ice_aqc_opc_lldp_stop = 0x0A05, 2443 ice_aqc_opc_lldp_start = 0x0A06, 2444 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2445 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2446 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2447 2448 /* RSS commands */ 2449 ice_aqc_opc_set_rss_key = 0x0B02, 2450 ice_aqc_opc_set_rss_lut = 0x0B03, 2451 ice_aqc_opc_get_rss_key = 0x0B04, 2452 ice_aqc_opc_get_rss_lut = 0x0B05, 2453 ice_aqc_opc_clear_fd_table = 0x0B06, 2454 2455 /* Tx queue handling commands/events */ 2456 ice_aqc_opc_add_txqs = 0x0C30, 2457 ice_aqc_opc_dis_txqs = 0x0C31, 2458 ice_aqc_opc_txqs_cleanup = 0x0C31, 2459 ice_aqc_opc_move_recfg_txqs = 0x0C32, 2460 2461 /* package commands */ 2462 ice_aqc_opc_download_pkg = 0x0C40, 2463 ice_aqc_opc_upload_section = 0x0C41, 2464 ice_aqc_opc_update_pkg = 0x0C42, 2465 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2466 2467 /* Standalone Commands/Events */ 2468 ice_aqc_opc_event_lan_overflow = 0x1001, 2469 }; 2470 2471 #endif /* _ICE_ADMINQ_CMD_H_ */ 2472