1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2019 3 */ 4 5 #ifndef _ICE_ADMINQ_CMD_H_ 6 #define _ICE_ADMINQ_CMD_H_ 7 8 /* This header file defines the Admin Queue commands, error codes and 9 * descriptor format. It is shared between Firmware and Software. 10 */ 11 12 13 #define ICE_MAX_VSI 768 14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 16 17 18 struct ice_aqc_generic { 19 __le32 param0; 20 __le32 param1; 21 __le32 addr_high; 22 __le32 addr_low; 23 }; 24 25 26 /* Get version (direct 0x0001) */ 27 struct ice_aqc_get_ver { 28 __le32 rom_ver; 29 __le32 fw_build; 30 u8 fw_branch; 31 u8 fw_major; 32 u8 fw_minor; 33 u8 fw_patch; 34 u8 api_branch; 35 u8 api_major; 36 u8 api_minor; 37 u8 api_patch; 38 }; 39 40 41 /* Send driver version (indirect 0x0002) */ 42 struct ice_aqc_driver_ver { 43 u8 major_ver; 44 u8 minor_ver; 45 u8 build_ver; 46 u8 subbuild_ver; 47 u8 reserved[4]; 48 __le32 addr_high; 49 __le32 addr_low; 50 }; 51 52 53 /* Queue Shutdown (direct 0x0003) */ 54 struct ice_aqc_q_shutdown { 55 u8 driver_unloading; 56 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 57 u8 reserved[15]; 58 }; 59 60 61 62 63 /* Request resource ownership (direct 0x0008) 64 * Release resource ownership (direct 0x0009) 65 */ 66 struct ice_aqc_req_res { 67 __le16 res_id; 68 #define ICE_AQC_RES_ID_NVM 1 69 #define ICE_AQC_RES_ID_SDP 2 70 #define ICE_AQC_RES_ID_CHNG_LOCK 3 71 #define ICE_AQC_RES_ID_GLBL_LOCK 4 72 __le16 access_type; 73 #define ICE_AQC_RES_ACCESS_READ 1 74 #define ICE_AQC_RES_ACCESS_WRITE 2 75 76 /* Upon successful completion, FW writes this value and driver is 77 * expected to release resource before timeout. This value is provided 78 * in milliseconds. 79 */ 80 __le32 timeout; 81 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 82 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 83 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 84 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 85 /* For SDP: pin ID of the SDP */ 86 __le32 res_number; 87 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 88 __le16 status; 89 #define ICE_AQ_RES_GLBL_SUCCESS 0 90 #define ICE_AQ_RES_GLBL_IN_PROG 1 91 #define ICE_AQ_RES_GLBL_DONE 2 92 u8 reserved[2]; 93 }; 94 95 96 /* Get function capabilities (indirect 0x000A) 97 * Get device capabilities (indirect 0x000B) 98 */ 99 struct ice_aqc_list_caps { 100 u8 cmd_flags; 101 u8 pf_index; 102 u8 reserved[2]; 103 __le32 count; 104 __le32 addr_high; 105 __le32 addr_low; 106 }; 107 108 109 /* Device/Function buffer entry, repeated per reported capability */ 110 struct ice_aqc_list_caps_elem { 111 __le16 cap; 112 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 113 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 114 #define ICE_AQC_CAPS_VSI 0x0017 115 #define ICE_AQC_CAPS_DCB 0x0018 116 #define ICE_AQC_CAPS_RSS 0x0040 117 #define ICE_AQC_CAPS_RXQS 0x0041 118 #define ICE_AQC_CAPS_TXQS 0x0042 119 #define ICE_AQC_CAPS_MSIX 0x0043 120 #define ICE_AQC_CAPS_FD 0x0045 121 #define ICE_AQC_CAPS_MAX_MTU 0x0047 122 123 u8 major_ver; 124 u8 minor_ver; 125 /* Number of resources described by this capability */ 126 __le32 number; 127 /* Only meaningful for some types of resources */ 128 __le32 logical_id; 129 /* Only meaningful for some types of resources */ 130 __le32 phys_id; 131 __le64 rsvd1; 132 __le64 rsvd2; 133 }; 134 135 136 /* Manage MAC address, read command - indirect (0x0107) 137 * This struct is also used for the response 138 */ 139 struct ice_aqc_manage_mac_read { 140 __le16 flags; /* Zeroed by device driver */ 141 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 142 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 143 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 144 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 145 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 146 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 147 #define ICE_AQC_MAN_MAC_READ_S 4 148 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 149 u8 rsvd[2]; 150 u8 num_addr; /* Used in response */ 151 u8 rsvd1[3]; 152 __le32 addr_high; 153 __le32 addr_low; 154 }; 155 156 157 /* Response buffer format for manage MAC read command */ 158 struct ice_aqc_manage_mac_read_resp { 159 u8 lport_num; 160 u8 addr_type; 161 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 162 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 163 u8 mac_addr[ETH_ALEN]; 164 }; 165 166 167 /* Manage MAC address, write command - direct (0x0108) */ 168 struct ice_aqc_manage_mac_write { 169 u8 rsvd; 170 u8 flags; 171 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 172 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 173 #define ICE_AQC_MAN_MAC_WR_S 6 174 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 175 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 176 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 177 /* High 16 bits of MAC address in big endian order */ 178 __be16 sah; 179 /* Low 32 bits of MAC address in big endian order */ 180 __be32 sal; 181 __le32 addr_high; 182 __le32 addr_low; 183 }; 184 185 186 /* Clear PXE Command and response (direct 0x0110) */ 187 struct ice_aqc_clear_pxe { 188 u8 rx_cnt; 189 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 190 u8 reserved[15]; 191 }; 192 193 194 /* Configure No-Drop Policy Command (direct 0x0112) */ 195 struct ice_aqc_config_no_drop_policy { 196 u8 opts; 197 #define ICE_AQC_FORCE_NO_DROP BIT(0) 198 u8 rsvd[15]; 199 }; 200 201 /* Get switch configuration (0x0200) */ 202 struct ice_aqc_get_sw_cfg { 203 /* Reserved for command and copy of request flags for response */ 204 __le16 flags; 205 /* First desc in case of command and next_elem in case of response 206 * In case of response, if it is not zero, means all the configuration 207 * was not returned and new command shall be sent with this value in 208 * the 'first desc' field 209 */ 210 __le16 element; 211 /* Reserved for command, only used for response */ 212 __le16 num_elems; 213 __le16 rsvd; 214 __le32 addr_high; 215 __le32 addr_low; 216 }; 217 218 219 /* Each entry in the response buffer is of the following type: */ 220 struct ice_aqc_get_sw_cfg_resp_elem { 221 /* VSI/Port Number */ 222 __le16 vsi_port_num; 223 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 224 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 225 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 226 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 227 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 228 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 229 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 230 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 231 232 /* SWID VSI/Port belongs to */ 233 __le16 swid; 234 235 /* Bit 14..0 : PF/VF number VSI belongs to 236 * Bit 15 : VF indication bit 237 */ 238 __le16 pf_vf_num; 239 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 240 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 241 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 242 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 243 }; 244 245 246 /* The response buffer is as follows. Note that the length of the 247 * elements array varies with the length of the command response. 248 */ 249 struct ice_aqc_get_sw_cfg_resp { 250 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 251 }; 252 253 254 255 /* These resource type defines are used for all switch resource 256 * commands where a resource type is required, such as: 257 * Get Resource Allocation command (indirect 0x0204) 258 * Allocate Resources command (indirect 0x0208) 259 * Free Resources command (indirect 0x0209) 260 * Get Allocated Resource Descriptors Command (indirect 0x020A) 261 */ 262 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 263 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 264 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 265 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 266 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 267 #define ICE_AQC_RES_TYPE_RECIPE 0x05 268 #define ICE_AQC_RES_TYPE_PROFILE 0x06 269 #define ICE_AQC_RES_TYPE_SWID 0x07 270 #define ICE_AQC_RES_TYPE_VSI 0x08 271 #define ICE_AQC_RES_TYPE_FLU 0x09 272 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 273 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 274 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 275 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 276 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 277 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 278 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 279 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 280 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 281 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 282 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 283 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 284 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 285 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 286 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 287 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 288 /* Resource types 0x62-67 are reserved for Hash profile builder */ 289 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 290 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 291 292 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 293 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 294 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 295 296 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 297 298 #define ICE_AQC_RES_TYPE_S 0 299 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 300 301 /* Get Resource Allocation command (indirect 0x0204) */ 302 struct ice_aqc_get_res_alloc { 303 __le16 resp_elem_num; /* Used in response, reserved in command */ 304 u8 reserved[6]; 305 __le32 addr_high; 306 __le32 addr_low; 307 }; 308 309 /* Get Resource Allocation Response Buffer per response */ 310 struct ice_aqc_get_res_resp_elem { 311 __le16 res_type; /* Types defined above cmd 0x0204 */ 312 __le16 total_capacity; /* Resources available to all PF's */ 313 __le16 total_function; /* Resources allocated for a PF */ 314 __le16 total_shared; /* Resources allocated as shared */ 315 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 316 }; 317 318 /* Buffer for Get Resource command */ 319 struct ice_aqc_get_res_resp { 320 /* Number of resource entries to be calculated using 321 * datalen/sizeof(struct ice_aqc_cmd_resp)). 322 * Value of 'datalen' gets updated as part of response. 323 */ 324 struct ice_aqc_get_res_resp_elem elem[1]; 325 }; 326 327 328 /* Allocate Resources command (indirect 0x0208) 329 * Free Resources command (indirect 0x0209) 330 */ 331 struct ice_aqc_alloc_free_res_cmd { 332 __le16 num_entries; /* Number of Resource entries */ 333 u8 reserved[6]; 334 __le32 addr_high; 335 __le32 addr_low; 336 }; 337 338 339 /* Resource descriptor */ 340 struct ice_aqc_res_elem { 341 union { 342 __le16 sw_resp; 343 __le16 flu_resp; 344 } e; 345 }; 346 347 348 /* Buffer for Allocate/Free Resources commands */ 349 struct ice_aqc_alloc_free_res_elem { 350 __le16 res_type; /* Types defined above cmd 0x0204 */ 351 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 352 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 353 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 354 __le16 num_elems; 355 struct ice_aqc_res_elem elem[1]; 356 }; 357 358 359 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 360 struct ice_aqc_get_allocd_res_desc { 361 union { 362 struct { 363 __le16 res; /* Types defined above cmd 0x0204 */ 364 __le16 first_desc; 365 __le32 reserved; 366 } cmd; 367 struct { 368 __le16 res; 369 __le16 next_desc; 370 __le16 num_desc; 371 __le16 reserved; 372 } resp; 373 } ops; 374 __le32 addr_high; 375 __le32 addr_low; 376 }; 377 378 struct ice_aqc_get_allocd_res_desc_resp { 379 struct ice_aqc_res_elem elem[1]; 380 }; 381 382 383 /* Add VSI (indirect 0x0210) 384 * Update VSI (indirect 0x0211) 385 * Get VSI (indirect 0x0212) 386 * Free VSI (indirect 0x0213) 387 */ 388 struct ice_aqc_add_get_update_free_vsi { 389 __le16 vsi_num; 390 #define ICE_AQ_VSI_NUM_S 0 391 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 392 #define ICE_AQ_VSI_IS_VALID BIT(15) 393 __le16 cmd_flags; 394 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 395 u8 vf_id; 396 u8 reserved; 397 __le16 vsi_flags; 398 #define ICE_AQ_VSI_TYPE_S 0 399 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 400 #define ICE_AQ_VSI_TYPE_VF 0x0 401 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 402 #define ICE_AQ_VSI_TYPE_PF 0x2 403 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 404 __le32 addr_high; 405 __le32 addr_low; 406 }; 407 408 409 /* Response descriptor for: 410 * Add VSI (indirect 0x0210) 411 * Update VSI (indirect 0x0211) 412 * Free VSI (indirect 0x0213) 413 */ 414 struct ice_aqc_add_update_free_vsi_resp { 415 __le16 vsi_num; 416 __le16 ext_status; 417 __le16 vsi_used; 418 __le16 vsi_free; 419 __le32 addr_high; 420 __le32 addr_low; 421 }; 422 423 424 struct ice_aqc_get_vsi_resp { 425 __le16 vsi_num; 426 u8 vf_id; 427 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 428 * These are found above in struct ice_aqc_add_get_update_free_vsi. 429 */ 430 u8 vsi_flags; 431 __le16 vsi_used; 432 __le16 vsi_free; 433 __le32 addr_high; 434 __le32 addr_low; 435 }; 436 437 438 struct ice_aqc_vsi_props { 439 __le16 valid_sections; 440 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 441 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 442 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 443 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 444 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 445 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 446 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 447 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 448 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 449 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 450 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 451 /* switch section */ 452 u8 sw_id; 453 u8 sw_flags; 454 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 455 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 456 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 457 u8 sw_flags2; 458 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 459 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 460 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 461 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 462 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 463 u8 veb_stat_id; 464 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 465 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 466 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 467 /* security section */ 468 u8 sec_flags; 469 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 470 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 471 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 472 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 473 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 474 u8 sec_reserved; 475 /* VLAN section */ 476 __le16 pvid; /* VLANS include priority bits */ 477 u8 pvlan_reserved[2]; 478 u8 vlan_flags; 479 #define ICE_AQ_VSI_VLAN_MODE_S 0 480 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 481 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 482 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 483 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 484 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 485 #define ICE_AQ_VSI_VLAN_EMOD_S 3 486 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 487 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 488 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 489 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 490 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 491 u8 pvlan_reserved2[3]; 492 /* ingress egress up sections */ 493 __le32 ingress_table; /* bitmap, 3 bits per up */ 494 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 495 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 496 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 497 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 498 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 499 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 500 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 501 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 502 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 503 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 504 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 505 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 506 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 507 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 508 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 509 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 510 __le32 egress_table; /* same defines as for ingress table */ 511 /* outer tags section */ 512 __le16 outer_tag; 513 u8 outer_tag_flags; 514 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 515 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 516 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 517 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 518 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 519 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 520 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 521 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 522 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 523 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 524 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 525 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 526 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 527 u8 outer_tag_reserved; 528 /* queue mapping section */ 529 __le16 mapping_flags; 530 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 531 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 532 __le16 q_mapping[16]; 533 #define ICE_AQ_VSI_Q_S 0 534 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 535 __le16 tc_mapping[8]; 536 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 537 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 538 #define ICE_AQ_VSI_TC_Q_NUM_S 11 539 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 540 /* queueing option section */ 541 u8 q_opt_rss; 542 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 543 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 544 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 545 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 546 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 547 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 548 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 549 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 550 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 551 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 552 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 553 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 554 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 555 u8 q_opt_tc; 556 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 557 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 558 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 559 u8 q_opt_flags; 560 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 561 u8 q_opt_reserved[3]; 562 /* outer up section */ 563 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 564 /* section 10 */ 565 __le16 sect_10_reserved; 566 /* flow director section */ 567 __le16 fd_options; 568 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 569 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 570 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 571 __le16 max_fd_fltr_dedicated; 572 __le16 max_fd_fltr_shared; 573 __le16 fd_def_q; 574 #define ICE_AQ_VSI_FD_DEF_Q_S 0 575 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 576 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 577 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 578 __le16 fd_report_opt; 579 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 580 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 581 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 582 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 583 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 584 /* PASID section */ 585 __le32 pasid_id; 586 #define ICE_AQ_VSI_PASID_ID_S 0 587 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 588 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 589 u8 reserved[24]; 590 }; 591 592 593 /* Add/update mirror rule - direct (0x0260) */ 594 #define ICE_AQC_RULE_ID_VALID_S 7 595 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 596 #define ICE_AQC_RULE_ID_S 0 597 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 598 599 /* Following defines to be used while processing caller specified mirror list 600 * of VSI indexes. 601 */ 602 /* Action: Byte.bit (1.7) 603 * 0 = Remove VSI from mirror rule 604 * 1 = Add VSI to mirror rule 605 */ 606 #define ICE_AQC_RULE_ACT_S 15 607 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 608 /* Action: 1.2:0.0 = Mirrored VSI */ 609 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 610 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 611 612 /* This is to be used by add/update mirror rule Admin Queue command. 613 * In case of add mirror rule - if rule ID is specified as 614 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 615 * If specified rule_id is valid, then it is used. If specified rule_id 616 * is in use then new mirroring rule is added. 617 */ 618 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 619 620 struct ice_aqc_add_update_mir_rule { 621 __le16 rule_id; 622 623 __le16 rule_type; 624 #define ICE_AQC_RULE_TYPE_S 0 625 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 626 /* VPORT ingress/egress */ 627 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 628 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 629 /* Physical port ingress mirroring. 630 * All traffic received by this port 631 */ 632 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 633 /* Physical port egress mirroring. All traffic sent by this port */ 634 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 635 636 /* Number of mirrored entries. 637 * The values are in the command buffer 638 */ 639 __le16 num_entries; 640 641 /* Destination VSI */ 642 __le16 dest; 643 __le32 addr_high; 644 __le32 addr_low; 645 }; 646 647 /* Delete mirror rule - direct(0x0261) */ 648 struct ice_aqc_delete_mir_rule { 649 __le16 rule_id; 650 __le16 rsvd; 651 652 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 653 * the PF allocated resources, otherwise it is returned to the 654 * shared pool 655 */ 656 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 657 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 658 __le16 flags; 659 660 u8 reserved[10]; 661 }; 662 663 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 664 /* This structure holds get storm configuration response and same structure 665 * is used to perform set_storm_cfg 666 */ 667 struct ice_aqc_storm_cfg { 668 __le32 bcast_thresh_size; 669 __le32 mcast_thresh_size; 670 /* Bit 18:0 - Traffic upper threshold size 671 * Bit 31:19 - Reserved 672 */ 673 #define ICE_AQ_THRESHOLD_S 0 674 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 675 676 __le32 storm_ctrl_ctrl; 677 /* Bit 0: MDIPW - Drop Multicast packets in previous window 678 * Bit 1: MDICW - Drop multicast packets in current window 679 * Bit 2: BDIPW - Drop broadcast packets in previous window 680 * Bit 3: BDICW - Drop broadcast packets in current window 681 */ 682 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 683 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 684 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 685 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 686 /* Bit 7:5 : Reserved */ 687 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 688 * interval size for applying ingress broadcast or multicast storm 689 * control. 690 */ 691 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 692 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 693 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 694 __le32 reserved; 695 }; 696 697 698 #define ICE_MAX_NUM_RECIPES 64 699 700 /* Add/Get Recipe (indirect 0x0290/0x0292)*/ 701 struct ice_aqc_add_get_recipe { 702 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 703 __le16 return_index; /* Input, used for Get cmd only */ 704 u8 reserved[4]; 705 __le32 addr_high; 706 __le32 addr_low; 707 }; 708 709 struct ice_aqc_recipe_content { 710 u8 rid; 711 #define ICE_AQ_RECIPE_ID_S 0 712 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 713 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 714 #define ICE_AQ_SW_ID_LKUP_IDX 0 715 u8 lkup_indx[5]; 716 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 717 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 718 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 719 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 720 __le16 mask[5]; 721 u8 result_indx; 722 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 723 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 724 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 725 u8 rsvd0[3]; 726 u8 act_ctrl_join_priority; 727 u8 act_ctrl_fwd_priority; 728 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 729 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 730 u8 act_ctrl; 731 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 732 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 733 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 734 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 735 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 736 u8 rsvd1; 737 __le32 dflt_act; 738 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 739 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 740 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 741 }; 742 743 struct ice_aqc_recipe_data_elem { 744 u8 recipe_indx; 745 u8 resp_bits; 746 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 747 u8 rsvd0[2]; 748 u8 recipe_bitmap[8]; 749 u8 rsvd1[4]; 750 struct ice_aqc_recipe_content content; 751 u8 rsvd2[20]; 752 }; 753 754 /* This struct contains a number of entries as per the 755 * num_sub_recipes in the command 756 */ 757 struct ice_aqc_add_get_recipe_data { 758 struct ice_aqc_recipe_data_elem recipe[1]; 759 }; 760 761 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 762 struct ice_aqc_recipe_to_profile { 763 __le16 profile_id; 764 u8 rsvd[6]; 765 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES); 766 }; 767 768 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 769 */ 770 struct ice_aqc_sw_rules { 771 /* ops: add switch rules, referring the number of rules. 772 * ops: update switch rules, referring the number of filters 773 * ops: remove switch rules, referring the entry index. 774 * ops: get switch rules, referring to the number of filters. 775 */ 776 __le16 num_rules_fltr_entry_index; 777 u8 reserved[6]; 778 __le32 addr_high; 779 __le32 addr_low; 780 }; 781 782 783 #pragma pack(1) 784 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 785 * This structures describes the lookup rules and associated actions. "index" 786 * is returned as part of a response to a successful Add command, and can be 787 * used to identify the rule for Update/Get/Remove commands. 788 */ 789 struct ice_sw_rule_lkup_rx_tx { 790 __le16 recipe_id; 791 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 792 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 793 __le16 src; 794 __le32 act; 795 796 /* Bit 0:1 - Action type */ 797 #define ICE_SINGLE_ACT_TYPE_S 0x00 798 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 799 800 /* Bit 2 - Loop back enable 801 * Bit 3 - LAN enable 802 */ 803 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 804 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 805 806 /* Action type = 0 - Forward to VSI or VSI list */ 807 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 808 809 #define ICE_SINGLE_ACT_VSI_ID_S 4 810 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 811 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 812 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 813 /* This bit needs to be set if action is forward to VSI list */ 814 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 815 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 816 #define ICE_SINGLE_ACT_DROP BIT(18) 817 818 /* Action type = 1 - Forward to Queue of Queue group */ 819 #define ICE_SINGLE_ACT_TO_Q 0x1 820 #define ICE_SINGLE_ACT_Q_INDEX_S 4 821 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 822 #define ICE_SINGLE_ACT_Q_REGION_S 15 823 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 824 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 825 826 /* Action type = 2 - Prune */ 827 #define ICE_SINGLE_ACT_PRUNE 0x2 828 #define ICE_SINGLE_ACT_EGRESS BIT(15) 829 #define ICE_SINGLE_ACT_INGRESS BIT(16) 830 #define ICE_SINGLE_ACT_PRUNET BIT(17) 831 /* Bit 18 should be set to 0 for this action */ 832 833 /* Action type = 2 - Pointer */ 834 #define ICE_SINGLE_ACT_PTR 0x2 835 #define ICE_SINGLE_ACT_PTR_VAL_S 4 836 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 837 /* Bit 18 should be set to 1 */ 838 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 839 840 /* Action type = 3 - Other actions. Last two bits 841 * are other action identifier 842 */ 843 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 844 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 845 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 846 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 847 848 /* Bit 17:18 - Defines other actions */ 849 /* Other action = 0 - Mirror VSI */ 850 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 851 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 852 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 853 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 854 855 /* Other action = 3 - Set Stat count */ 856 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 857 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 858 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 859 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 860 861 __le16 index; /* The index of the rule in the lookup table */ 862 /* Length and values of the header to be matched per recipe or 863 * lookup-type 864 */ 865 __le16 hdr_len; 866 u8 hdr[1]; 867 }; 868 #pragma pack() 869 870 871 /* Add/Update/Remove large action command/response entry 872 * "index" is returned as part of a response to a successful Add command, and 873 * can be used to identify the action for Update/Get/Remove commands. 874 */ 875 struct ice_sw_rule_lg_act { 876 __le16 index; /* Index in large action table */ 877 __le16 size; 878 __le32 act[1]; /* array of size for actions */ 879 /* Max number of large actions */ 880 #define ICE_MAX_LG_ACT 4 881 /* Bit 0:1 - Action type */ 882 #define ICE_LG_ACT_TYPE_S 0 883 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 884 885 /* Action type = 0 - Forward to VSI or VSI list */ 886 #define ICE_LG_ACT_VSI_FORWARDING 0 887 #define ICE_LG_ACT_VSI_ID_S 3 888 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 889 #define ICE_LG_ACT_VSI_LIST_ID_S 3 890 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 891 /* This bit needs to be set if action is forward to VSI list */ 892 #define ICE_LG_ACT_VSI_LIST BIT(13) 893 894 #define ICE_LG_ACT_VALID_BIT BIT(16) 895 896 /* Action type = 1 - Forward to Queue of Queue group */ 897 #define ICE_LG_ACT_TO_Q 0x1 898 #define ICE_LG_ACT_Q_INDEX_S 3 899 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 900 #define ICE_LG_ACT_Q_REGION_S 14 901 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 902 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 903 904 /* Action type = 2 - Prune */ 905 #define ICE_LG_ACT_PRUNE 0x2 906 #define ICE_LG_ACT_EGRESS BIT(14) 907 #define ICE_LG_ACT_INGRESS BIT(15) 908 #define ICE_LG_ACT_PRUNET BIT(16) 909 910 /* Action type = 3 - Mirror VSI */ 911 #define ICE_LG_OTHER_ACT_MIRROR 0x3 912 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 913 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 914 915 /* Action type = 5 - Generic Value */ 916 #define ICE_LG_ACT_GENERIC 0x5 917 #define ICE_LG_ACT_GENERIC_VALUE_S 3 918 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 919 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 920 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 921 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 922 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 923 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 924 925 /* Action = 7 - Set Stat count */ 926 #define ICE_LG_ACT_STAT_COUNT 0x7 927 #define ICE_LG_ACT_STAT_COUNT_S 3 928 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 929 }; 930 931 932 /* Add/Update/Remove VSI list command/response entry 933 * "index" is returned as part of a response to a successful Add command, and 934 * can be used to identify the VSI list for Update/Get/Remove commands. 935 */ 936 struct ice_sw_rule_vsi_list { 937 __le16 index; /* Index of VSI/Prune list */ 938 __le16 number_vsi; 939 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 940 }; 941 942 943 #pragma pack(1) 944 /* Query VSI list command/response entry */ 945 struct ice_sw_rule_vsi_list_query { 946 __le16 index; 947 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 948 }; 949 #pragma pack() 950 951 952 #pragma pack(1) 953 /* Add switch rule response: 954 * Content of return buffer is same as the input buffer. The status field and 955 * LUT index are updated as part of the response 956 */ 957 struct ice_aqc_sw_rules_elem { 958 __le16 type; /* Switch rule type, one of T_... */ 959 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 960 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 961 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 962 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 963 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 964 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 965 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 966 __le16 status; 967 union { 968 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 969 struct ice_sw_rule_lg_act lg_act; 970 struct ice_sw_rule_vsi_list vsi_list; 971 struct ice_sw_rule_vsi_list_query vsi_list_query; 972 } pdata; 973 }; 974 975 #pragma pack() 976 977 978 /* PFC Ignore (direct 0x0301) 979 * The command and response use the same descriptor structure 980 */ 981 struct ice_aqc_pfc_ignore { 982 u8 tc_bitmap; 983 u8 cmd_flags; /* unused in response */ 984 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 985 #define ICE_AQC_PFC_IGNORE_CLEAR 0 986 u8 reserved[14]; 987 }; 988 989 /* Set PFC Mode (direct 0x0303) 990 * Query PFC Mode (direct 0x0302) 991 */ 992 struct ice_aqc_set_query_pfc_mode { 993 u8 pfc_mode; 994 /* For Set Command response, reserved in all other cases */ 995 #define ICE_AQC_PFC_NOT_CONFIGURED 0 996 /* For Query Command response, reserved in all other cases */ 997 #define ICE_AQC_DCB_DIS 0 998 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 999 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 1000 u8 rsvd[15]; 1001 }; 1002 1003 /* Set DCB Parameters (direct 0x0306) */ 1004 struct ice_aqc_set_dcb_params { 1005 u8 cmd_flags; /* unused in response */ 1006 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 1007 u8 valid_flags; /* unused in response */ 1008 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1009 u8 rsvd[14]; 1010 }; 1011 1012 1013 /* Get Default Topology (indirect 0x0400) */ 1014 struct ice_aqc_get_topo { 1015 u8 port_num; 1016 u8 num_branches; 1017 __le16 reserved1; 1018 __le32 reserved2; 1019 __le32 addr_high; 1020 __le32 addr_low; 1021 }; 1022 1023 1024 /* Update TSE (indirect 0x0403) 1025 * Get TSE (indirect 0x0404) 1026 * Add TSE (indirect 0x0401) 1027 * Delete TSE (indirect 0x040F) 1028 * Move TSE (indirect 0x0408) 1029 * Suspend Nodes (indirect 0x0409) 1030 * Resume Nodes (indirect 0x040A) 1031 */ 1032 struct ice_aqc_sched_elem_cmd { 1033 __le16 num_elem_req; /* Used by commands */ 1034 __le16 num_elem_resp; /* Used by responses */ 1035 __le32 reserved; 1036 __le32 addr_high; 1037 __le32 addr_low; 1038 }; 1039 1040 1041 /* This is the buffer for: 1042 * Suspend Nodes (indirect 0x0409) 1043 * Resume Nodes (indirect 0x040A) 1044 */ 1045 struct ice_aqc_suspend_resume_elem { 1046 __le32 teid[1]; 1047 }; 1048 1049 1050 struct ice_aqc_txsched_move_grp_info_hdr { 1051 __le32 src_parent_teid; 1052 __le32 dest_parent_teid; 1053 __le16 num_elems; 1054 __le16 reserved; 1055 }; 1056 1057 1058 struct ice_aqc_move_elem { 1059 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1060 __le32 teid[1]; 1061 }; 1062 1063 1064 struct ice_aqc_elem_info_bw { 1065 __le16 bw_profile_idx; 1066 __le16 bw_alloc; 1067 }; 1068 1069 1070 struct ice_aqc_txsched_elem { 1071 u8 elem_type; /* Special field, reserved for some aq calls */ 1072 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1073 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1074 #define ICE_AQC_ELEM_TYPE_TC 0x2 1075 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1076 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1077 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1078 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1079 u8 valid_sections; 1080 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1081 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1082 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1083 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1084 u8 generic; 1085 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1086 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1087 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1088 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1089 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1090 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1091 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1092 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1093 u8 flags; /* Special field, reserved for some aq calls */ 1094 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1095 struct ice_aqc_elem_info_bw cir_bw; 1096 struct ice_aqc_elem_info_bw eir_bw; 1097 __le16 srl_id; 1098 __le16 reserved2; 1099 }; 1100 1101 1102 struct ice_aqc_txsched_elem_data { 1103 __le32 parent_teid; 1104 __le32 node_teid; 1105 struct ice_aqc_txsched_elem data; 1106 }; 1107 1108 1109 struct ice_aqc_txsched_topo_grp_info_hdr { 1110 __le32 parent_teid; 1111 __le16 num_elems; 1112 __le16 reserved2; 1113 }; 1114 1115 1116 struct ice_aqc_add_elem { 1117 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1118 struct ice_aqc_txsched_elem_data generic[1]; 1119 }; 1120 1121 1122 struct ice_aqc_conf_elem { 1123 struct ice_aqc_txsched_elem_data generic[1]; 1124 }; 1125 1126 1127 struct ice_aqc_get_elem { 1128 struct ice_aqc_txsched_elem_data generic[1]; 1129 }; 1130 1131 1132 struct ice_aqc_get_topo_elem { 1133 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1134 struct ice_aqc_txsched_elem_data 1135 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1136 }; 1137 1138 1139 struct ice_aqc_delete_elem { 1140 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1141 __le32 teid[1]; 1142 }; 1143 1144 1145 /* Query Port ETS (indirect 0x040E) 1146 * 1147 * This indirect command is used to query port TC node configuration. 1148 */ 1149 struct ice_aqc_query_port_ets { 1150 __le32 port_teid; 1151 __le32 reserved; 1152 __le32 addr_high; 1153 __le32 addr_low; 1154 }; 1155 1156 struct ice_aqc_port_ets_elem { 1157 u8 tc_valid_bits; 1158 u8 reserved[3]; 1159 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1160 __le32 up2tc; 1161 u8 tc_bw_share[8]; 1162 __le32 port_eir_prof_id; 1163 __le32 port_cir_prof_id; 1164 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1165 __le32 tc_node_prio; 1166 #define ICE_TC_NODE_PRIO_S 0x4 1167 u8 reserved1[4]; 1168 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1169 }; 1170 1171 1172 /* Rate limiting profile for 1173 * Add RL profile (indirect 0x0410) 1174 * Query RL profile (indirect 0x0411) 1175 * Remove RL profile (indirect 0x0415) 1176 * These indirect commands acts on single or multiple 1177 * RL profiles with specified data. 1178 */ 1179 struct ice_aqc_rl_profile { 1180 __le16 num_profiles; 1181 __le16 num_processed; /* Only for response. Reserved in Command. */ 1182 u8 reserved[4]; 1183 __le32 addr_high; 1184 __le32 addr_low; 1185 }; 1186 1187 1188 struct ice_aqc_rl_profile_elem { 1189 u8 level; 1190 u8 flags; 1191 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1192 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1193 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1194 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1195 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1196 /* The following flag is used for Query RL Profile Data */ 1197 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1198 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1199 1200 __le16 profile_id; 1201 __le16 max_burst_size; 1202 __le16 rl_multiply; 1203 __le16 wake_up_calc; 1204 __le16 rl_encode; 1205 }; 1206 1207 1208 struct ice_aqc_rl_profile_generic_elem { 1209 struct ice_aqc_rl_profile_elem generic[1]; 1210 }; 1211 1212 1213 1214 /* Configure L2 Node CGD (indirect 0x0414) 1215 * This indirect command allows configuring a congestion domain for given L2 1216 * node TEIDs in the scheduler topology. 1217 */ 1218 struct ice_aqc_cfg_l2_node_cgd { 1219 __le16 num_l2_nodes; 1220 u8 reserved[6]; 1221 __le32 addr_high; 1222 __le32 addr_low; 1223 }; 1224 1225 1226 struct ice_aqc_cfg_l2_node_cgd_elem { 1227 __le32 node_teid; 1228 u8 cgd; 1229 u8 reserved[3]; 1230 }; 1231 1232 1233 struct ice_aqc_cfg_l2_node_cgd_data { 1234 struct ice_aqc_cfg_l2_node_cgd_elem elem[1]; 1235 }; 1236 1237 1238 /* Query Scheduler Resource Allocation (indirect 0x0412) 1239 * This indirect command retrieves the scheduler resources allocated by 1240 * EMP Firmware to the given PF. 1241 */ 1242 struct ice_aqc_query_txsched_res { 1243 u8 reserved[8]; 1244 __le32 addr_high; 1245 __le32 addr_low; 1246 }; 1247 1248 1249 struct ice_aqc_generic_sched_props { 1250 __le16 phys_levels; 1251 __le16 logical_levels; 1252 u8 flattening_bitmap; 1253 u8 max_device_cgds; 1254 u8 max_pf_cgds; 1255 u8 rsvd0; 1256 __le16 rdma_qsets; 1257 u8 rsvd1[22]; 1258 }; 1259 1260 1261 struct ice_aqc_layer_props { 1262 u8 logical_layer; 1263 u8 chunk_size; 1264 __le16 max_device_nodes; 1265 __le16 max_pf_nodes; 1266 u8 rsvd0[4]; 1267 __le16 max_sibl_grp_sz; 1268 __le16 max_cir_rl_profiles; 1269 __le16 max_eir_rl_profiles; 1270 __le16 max_srl_profiles; 1271 u8 rsvd1[14]; 1272 }; 1273 1274 1275 struct ice_aqc_query_txsched_res_resp { 1276 struct ice_aqc_generic_sched_props sched_props; 1277 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1278 }; 1279 1280 1281 /* Query Node to Root Topology (indirect 0x0413) 1282 * This command uses ice_aqc_get_elem as its data buffer. 1283 */ 1284 struct ice_aqc_query_node_to_root { 1285 __le32 teid; 1286 __le32 num_nodes; /* Response only */ 1287 __le32 addr_high; 1288 __le32 addr_low; 1289 }; 1290 1291 1292 /* Get PHY capabilities (indirect 0x0600) */ 1293 struct ice_aqc_get_phy_caps { 1294 u8 lport_num; 1295 u8 reserved; 1296 __le16 param0; 1297 /* 18.0 - Report qualified modules */ 1298 #define ICE_AQC_GET_PHY_RQM BIT(0) 1299 /* 18.1 - 18.2 : Report mode 1300 * 00b - Report NVM capabilities 1301 * 01b - Report topology capabilities 1302 * 10b - Report SW configured 1303 */ 1304 #define ICE_AQC_REPORT_MODE_S 1 1305 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 1306 #define ICE_AQC_REPORT_NVM_CAP 0 1307 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 1308 #define ICE_AQC_REPORT_SW_CFG BIT(2) 1309 __le32 reserved1; 1310 __le32 addr_high; 1311 __le32 addr_low; 1312 }; 1313 1314 1315 /* This is #define of PHY type (Extended): 1316 * The first set of defines is for phy_type_low. 1317 */ 1318 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1319 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1320 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1321 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1322 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1323 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1324 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1325 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1326 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1327 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1328 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1329 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1330 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1331 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1332 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1333 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1334 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1335 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1336 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1337 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1338 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1339 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1340 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1341 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1342 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1343 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1344 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1345 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1346 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1347 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1348 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1349 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1350 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1351 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1352 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1353 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1354 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1355 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1356 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1357 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1358 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1359 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1360 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1361 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1362 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1363 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1364 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1365 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1366 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1367 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1368 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1369 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1370 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1371 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1372 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1373 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1374 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1375 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1376 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1377 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1378 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1379 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1380 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1381 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1382 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1383 /* The second set of defines is for phy_type_high. */ 1384 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1385 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1386 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1387 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1388 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1389 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 1390 1391 struct ice_aqc_get_phy_caps_data { 1392 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1393 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1394 u8 caps; 1395 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1396 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1397 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1398 #define ICE_AQC_PHY_EN_LINK BIT(3) 1399 #define ICE_AQC_PHY_AN_MODE BIT(4) 1400 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1401 #define ICE_AQC_PHY_EN_LESM BIT(6) 1402 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1403 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1404 u8 low_power_ctrl; 1405 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1406 __le16 eee_cap; 1407 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1408 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1409 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1410 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1411 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1412 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1413 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1414 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1415 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1416 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1417 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1418 __le16 eeer_value; 1419 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1420 u8 phy_fw_ver[8]; 1421 u8 link_fec_options; 1422 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1423 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1424 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1425 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1426 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1427 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1428 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1429 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1430 u8 rsvd1; /* Byte 35 reserved */ 1431 u8 extended_compliance_code; 1432 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1433 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1434 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1435 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1436 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1437 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1438 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1439 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1440 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1441 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1442 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1443 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1444 u8 qualified_module_count; 1445 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1446 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1447 struct { 1448 u8 v_oui[3]; 1449 u8 rsvd3; 1450 u8 v_part[16]; 1451 __le32 v_rev; 1452 __le64 rsvd4; 1453 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1454 }; 1455 1456 1457 /* Set PHY capabilities (direct 0x0601) 1458 * NOTE: This command must be followed by setup link and restart auto-neg 1459 */ 1460 struct ice_aqc_set_phy_cfg { 1461 u8 lport_num; 1462 u8 reserved[7]; 1463 __le32 addr_high; 1464 __le32 addr_low; 1465 }; 1466 1467 1468 /* Set PHY config command data structure */ 1469 struct ice_aqc_set_phy_cfg_data { 1470 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1471 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1472 u8 caps; 1473 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1474 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1475 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1476 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1477 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1478 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1479 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1480 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1481 u8 low_power_ctrl; 1482 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1483 __le16 eeer_value; 1484 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1485 u8 rsvd1; 1486 }; 1487 1488 1489 /* Set MAC Config command data structure (direct 0x0603) */ 1490 struct ice_aqc_set_mac_cfg { 1491 __le16 max_frame_size; 1492 u8 params; 1493 #define ICE_AQ_SET_MAC_PACE_S 3 1494 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1495 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1496 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1497 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1498 u8 tx_tmr_priority; 1499 __le16 tx_tmr_value; 1500 __le16 fc_refresh_threshold; 1501 u8 drop_opts; 1502 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1503 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1504 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1505 u8 reserved[7]; 1506 }; 1507 1508 1509 /* Restart AN command data structure (direct 0x0605) 1510 * Also used for response, with only the lport_num field present. 1511 */ 1512 struct ice_aqc_restart_an { 1513 u8 lport_num; 1514 u8 reserved; 1515 u8 cmd_flags; 1516 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1517 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1518 u8 reserved2[13]; 1519 }; 1520 1521 1522 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1523 struct ice_aqc_get_link_status { 1524 u8 lport_num; 1525 u8 reserved; 1526 __le16 cmd_flags; 1527 #define ICE_AQ_LSE_M 0x3 1528 #define ICE_AQ_LSE_NOP 0x0 1529 #define ICE_AQ_LSE_DIS 0x2 1530 #define ICE_AQ_LSE_ENA 0x3 1531 /* only response uses this flag */ 1532 #define ICE_AQ_LSE_IS_ENABLED 0x1 1533 __le32 reserved2; 1534 __le32 addr_high; 1535 __le32 addr_low; 1536 }; 1537 1538 1539 /* Get link status response data structure, also used for Link Status Event */ 1540 struct ice_aqc_get_link_status_data { 1541 u8 topo_media_conflict; 1542 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1543 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1544 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1545 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1546 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1547 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1548 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1549 u8 link_cfg_err; 1550 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1551 u8 link_info; 1552 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1553 #define ICE_AQ_LINK_FAULT BIT(1) 1554 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1555 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1556 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1557 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1558 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1559 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1560 u8 an_info; 1561 #define ICE_AQ_AN_COMPLETED BIT(0) 1562 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1563 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1564 #define ICE_AQ_FEC_EN BIT(3) 1565 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1566 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1567 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1568 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1569 u8 ext_info; 1570 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1571 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1572 /* Port Tx Suspended */ 1573 #define ICE_AQ_LINK_TX_S 2 1574 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1575 #define ICE_AQ_LINK_TX_ACTIVE 0 1576 #define ICE_AQ_LINK_TX_DRAINED 1 1577 #define ICE_AQ_LINK_TX_FLUSHED 3 1578 u8 reserved2; 1579 __le16 max_frame_size; 1580 u8 cfg; 1581 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1582 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1583 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1584 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1585 /* Pacing Config */ 1586 #define ICE_AQ_CFG_PACING_S 3 1587 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1588 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1589 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1590 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1591 /* External Device Power Ability */ 1592 u8 power_desc; 1593 #define ICE_AQ_PWR_CLASS_M 0x3 1594 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1595 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1596 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1597 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1598 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1599 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1600 __le16 link_speed; 1601 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1602 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1603 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1604 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1605 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1606 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1607 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1608 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1609 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1610 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1611 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1612 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1613 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1614 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1615 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1616 }; 1617 1618 1619 /* Set event mask command (direct 0x0613) */ 1620 struct ice_aqc_set_event_mask { 1621 u8 lport_num; 1622 u8 reserved[7]; 1623 __le16 event_mask; 1624 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1625 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1626 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1627 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1628 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1629 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1630 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1631 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1632 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1633 u8 reserved1[6]; 1634 }; 1635 1636 1637 1638 /* Set MAC Loopback command (direct 0x0620) */ 1639 struct ice_aqc_set_mac_lb { 1640 u8 lb_mode; 1641 #define ICE_AQ_MAC_LB_EN BIT(0) 1642 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1643 u8 reserved[15]; 1644 }; 1645 1646 1647 1648 1649 1650 /* Set Port Identification LED (direct, 0x06E9) */ 1651 struct ice_aqc_set_port_id_led { 1652 u8 lport_num; 1653 u8 lport_num_valid; 1654 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1655 u8 ident_mode; 1656 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1657 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1658 u8 rsvd[13]; 1659 }; 1660 1661 1662 1663 /* NVM Read command (indirect 0x0701) 1664 * NVM Erase commands (direct 0x0702) 1665 * NVM Update commands (indirect 0x0703) 1666 */ 1667 struct ice_aqc_nvm { 1668 __le16 offset_low; 1669 u8 offset_high; 1670 u8 cmd_flags; 1671 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1672 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1673 #define ICE_AQC_NVM_PRESERVATION_S 1 1674 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1675 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1676 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1677 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1678 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1679 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1680 __le16 module_typeid; 1681 __le16 length; 1682 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1683 __le32 addr_high; 1684 __le32 addr_low; 1685 }; 1686 1687 1688 /* Used for 0x0704 as well as for 0x0705 commands */ 1689 struct ice_aqc_nvm_cfg { 1690 u8 cmd_flags; 1691 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 1692 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 1693 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 1694 u8 reserved; 1695 __le16 count; 1696 __le16 id; 1697 u8 reserved1[2]; 1698 __le32 addr_high; 1699 __le32 addr_low; 1700 }; 1701 1702 1703 struct ice_aqc_nvm_cfg_data { 1704 __le16 field_id; 1705 __le16 field_options; 1706 __le16 field_value; 1707 }; 1708 1709 1710 /* NVM Checksum Command (direct, 0x0706) */ 1711 struct ice_aqc_nvm_checksum { 1712 u8 flags; 1713 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1714 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1715 u8 rsvd; 1716 __le16 checksum; /* Used only by response */ 1717 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1718 u8 rsvd2[12]; 1719 }; 1720 1721 1722 1723 1724 /* Get LLDP MIB (indirect 0x0A00) 1725 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1726 * as the format is the same. 1727 */ 1728 struct ice_aqc_lldp_get_mib { 1729 u8 type; 1730 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1731 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1732 #define ICE_AQ_LLDP_MIB_LOCAL 0 1733 #define ICE_AQ_LLDP_MIB_REMOTE 1 1734 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1735 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1736 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1737 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1738 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1739 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1740 #define ICE_AQ_LLDP_TX_S 0x4 1741 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1742 #define ICE_AQ_LLDP_TX_ACTIVE 0 1743 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1744 #define ICE_AQ_LLDP_TX_FLUSHED 3 1745 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1746 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1747 * Get LLDP MIB (0x0A00) response only. 1748 */ 1749 u8 reserved1; 1750 __le16 local_len; 1751 __le16 remote_len; 1752 u8 reserved2[2]; 1753 __le32 addr_high; 1754 __le32 addr_low; 1755 }; 1756 1757 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1758 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1759 struct ice_aqc_lldp_set_mib_change { 1760 u8 command; 1761 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1762 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1763 u8 reserved[15]; 1764 }; 1765 1766 /* Add LLDP TLV (indirect 0x0A02) 1767 * Delete LLDP TLV (indirect 0x0A04) 1768 */ 1769 struct ice_aqc_lldp_add_delete_tlv { 1770 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1771 u8 reserved1[1]; 1772 __le16 len; 1773 u8 reserved2[4]; 1774 __le32 addr_high; 1775 __le32 addr_low; 1776 }; 1777 1778 /* Update LLDP TLV (indirect 0x0A03) */ 1779 struct ice_aqc_lldp_update_tlv { 1780 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1781 u8 reserved; 1782 __le16 old_len; 1783 __le16 new_offset; 1784 __le16 new_len; 1785 __le32 addr_high; 1786 __le32 addr_low; 1787 }; 1788 1789 /* Stop LLDP (direct 0x0A05) */ 1790 struct ice_aqc_lldp_stop { 1791 u8 command; 1792 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1793 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1794 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1795 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1796 u8 reserved[15]; 1797 }; 1798 1799 /* Start LLDP (direct 0x0A06) */ 1800 struct ice_aqc_lldp_start { 1801 u8 command; 1802 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1803 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1804 u8 reserved[15]; 1805 }; 1806 1807 /* Get CEE DCBX Oper Config (0x0A07) 1808 * The command uses the generic descriptor struct and 1809 * returns the struct below as an indirect response. 1810 */ 1811 struct ice_aqc_get_cee_dcb_cfg_resp { 1812 u8 oper_num_tc; 1813 u8 oper_prio_tc[4]; 1814 u8 oper_tc_bw[8]; 1815 u8 oper_pfc_en; 1816 __le16 oper_app_prio; 1817 #define ICE_AQC_CEE_APP_FCOE_S 0 1818 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1819 #define ICE_AQC_CEE_APP_ISCSI_S 3 1820 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1821 #define ICE_AQC_CEE_APP_FIP_S 8 1822 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1823 __le32 tlv_status; 1824 #define ICE_AQC_CEE_PG_STATUS_S 0 1825 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1826 #define ICE_AQC_CEE_PFC_STATUS_S 3 1827 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1828 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1829 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1830 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1831 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1832 #define ICE_AQC_CEE_FIP_STATUS_S 16 1833 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1834 u8 reserved[12]; 1835 }; 1836 1837 /* Set Local LLDP MIB (indirect 0x0A08) 1838 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1839 */ 1840 struct ice_aqc_lldp_set_local_mib { 1841 u8 type; 1842 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1843 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1844 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1845 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1846 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1847 u8 reserved0; 1848 __le16 length; 1849 u8 reserved1[4]; 1850 __le32 addr_high; 1851 __le32 addr_low; 1852 }; 1853 1854 struct ice_aqc_lldp_set_local_mib_resp { 1855 u8 status; 1856 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 1857 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 1858 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 1859 u8 reserved[15]; 1860 }; 1861 1862 /* Stop/Start LLDP Agent (direct 0x0A09) 1863 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1864 * The same structure is used for the response, with the command field 1865 * being used as the status field. 1866 */ 1867 struct ice_aqc_lldp_stop_start_specific_agent { 1868 u8 command; 1869 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1870 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1871 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1872 u8 reserved[15]; 1873 }; 1874 1875 1876 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1877 struct ice_aqc_get_set_rss_key { 1878 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1879 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1880 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1881 __le16 vsi_id; 1882 u8 reserved[6]; 1883 __le32 addr_high; 1884 __le32 addr_low; 1885 }; 1886 1887 1888 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1889 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1890 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1891 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1892 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1893 1894 /** 1895 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 1896 * @standard_rss_key: 40 most significant bytes of hash key 1897 * @extended_hash_key: 12 least significant bytes of hash key 1898 * 1899 * Set/Get 40 byte hash key using standard_rss_key field, and set 1900 * extended_hash_key field to zero. Set/Get 52 byte hash key using 1901 * standard_rss_key field for 40 most significant bytes and the 1902 * extended_hash_key field for the 12 least significant bytes of hash key. 1903 */ 1904 struct ice_aqc_get_set_rss_keys { 1905 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1906 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1907 }; 1908 1909 1910 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1911 struct ice_aqc_get_set_rss_lut { 1912 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1913 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1914 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1915 __le16 vsi_id; 1916 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1917 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1918 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1919 1920 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1921 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1922 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1923 1924 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1925 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1926 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1927 1928 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1929 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1930 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1931 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1932 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1933 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1934 1935 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1936 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1937 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1938 1939 __le16 flags; 1940 __le32 reserved; 1941 __le32 addr_high; 1942 __le32 addr_low; 1943 }; 1944 1945 1946 /* Clear FD Table Command (direct, 0x0B06) */ 1947 struct ice_aqc_clear_fd_table { 1948 u8 clear_type; 1949 #define CL_FD_VM_VF_TYPE_VSI_IDX 1 1950 #define CL_FD_VM_VF_TYPE_PF_IDX 2 1951 u8 rsvd; 1952 __le16 vsi_index; 1953 u8 reserved[12]; 1954 }; 1955 1956 1957 1958 1959 /* Add Tx LAN Queues (indirect 0x0C30) */ 1960 struct ice_aqc_add_txqs { 1961 u8 num_qgrps; 1962 u8 reserved[3]; 1963 __le32 reserved1; 1964 __le32 addr_high; 1965 __le32 addr_low; 1966 }; 1967 1968 1969 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1970 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1971 */ 1972 struct ice_aqc_add_txqs_perq { 1973 __le16 txq_id; 1974 u8 rsvd[2]; 1975 __le32 q_teid; 1976 u8 txq_ctx[22]; 1977 u8 rsvd2[2]; 1978 struct ice_aqc_txsched_elem info; 1979 }; 1980 1981 1982 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1983 * is an array of the following structs. Please note that the length of 1984 * each struct ice_aqc_add_tx_qgrp is variable due 1985 * to the variable number of queues in each group! 1986 */ 1987 struct ice_aqc_add_tx_qgrp { 1988 __le32 parent_teid; 1989 u8 num_txqs; 1990 u8 rsvd[3]; 1991 struct ice_aqc_add_txqs_perq txqs[1]; 1992 }; 1993 1994 1995 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1996 struct ice_aqc_dis_txqs { 1997 u8 cmd_type; 1998 #define ICE_AQC_Q_DIS_CMD_S 0 1999 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2000 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2001 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2002 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2003 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2004 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2005 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2006 u8 num_entries; 2007 __le16 vmvf_and_timeout; 2008 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2009 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2010 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2011 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2012 __le32 blocked_cgds; 2013 __le32 addr_high; 2014 __le32 addr_low; 2015 }; 2016 2017 2018 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2019 * contains the following structures, arrayed one after the 2020 * other. 2021 * Note: Since the q_id is 16 bits wide, if the 2022 * number of queues is even, then 2 bytes of alignment MUST be 2023 * added before the start of the next group, to allow correct 2024 * alignment of the parent_teid field. 2025 */ 2026 struct ice_aqc_dis_txq_item { 2027 __le32 parent_teid; 2028 u8 num_qs; 2029 u8 rsvd; 2030 /* The length of the q_id array varies according to num_qs */ 2031 __le16 q_id[1]; 2032 /* This only applies from F8 onward */ 2033 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2034 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2035 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2036 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2037 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2038 }; 2039 2040 2041 struct ice_aqc_dis_txq { 2042 struct ice_aqc_dis_txq_item qgrps[1]; 2043 }; 2044 2045 2046 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2047 struct ice_aqc_txqs_cleanup { 2048 __le16 caller_opc; 2049 __le16 cmd_tag; 2050 u8 reserved[12]; 2051 }; 2052 2053 2054 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2055 struct ice_aqc_move_txqs { 2056 u8 cmd_type; 2057 #define ICE_AQC_Q_CMD_TYPE_S 0 2058 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2059 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2060 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2061 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2062 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2063 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2064 u8 num_qs; 2065 u8 rsvd; 2066 u8 timeout; 2067 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2068 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2069 __le32 blocked_cgds; 2070 __le32 addr_high; 2071 __le32 addr_low; 2072 }; 2073 2074 2075 /* This is the descriptor of each queue entry for the move Tx LAN Queues 2076 * command (0x0C32). 2077 */ 2078 struct ice_aqc_move_txqs_elem { 2079 __le16 txq_id; 2080 u8 q_cgd; 2081 u8 rsvd; 2082 __le32 q_teid; 2083 }; 2084 2085 2086 struct ice_aqc_move_txqs_data { 2087 __le32 src_teid; 2088 __le32 dest_teid; 2089 struct ice_aqc_move_txqs_elem txqs[1]; 2090 }; 2091 2092 2093 2094 /* Download Package (indirect 0x0C40) */ 2095 /* Also used for Update Package (indirect 0x0C42) */ 2096 struct ice_aqc_download_pkg { 2097 u8 flags; 2098 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2099 u8 reserved[3]; 2100 __le32 reserved1; 2101 __le32 addr_high; 2102 __le32 addr_low; 2103 }; 2104 2105 struct ice_aqc_download_pkg_resp { 2106 __le32 error_offset; 2107 __le32 error_info; 2108 __le32 addr_high; 2109 __le32 addr_low; 2110 }; 2111 2112 /* Get Package Info List (indirect 0x0C43) */ 2113 struct ice_aqc_get_pkg_info_list { 2114 __le32 reserved1; 2115 __le32 reserved2; 2116 __le32 addr_high; 2117 __le32 addr_low; 2118 }; 2119 2120 /* Version format for packages */ 2121 struct ice_pkg_ver { 2122 u8 major; 2123 u8 minor; 2124 u8 update; 2125 u8 draft; 2126 }; 2127 2128 #define ICE_PKG_NAME_SIZE 32 2129 2130 struct ice_aqc_get_pkg_info { 2131 struct ice_pkg_ver ver; 2132 char name[ICE_PKG_NAME_SIZE]; 2133 u8 is_in_nvm; 2134 u8 is_active; 2135 u8 is_active_at_boot; 2136 u8 is_modified; 2137 }; 2138 2139 /* Get Package Info List response buffer format (0x0C43) */ 2140 struct ice_aqc_get_pkg_info_resp { 2141 __le32 count; 2142 struct ice_aqc_get_pkg_info pkg_info[1]; 2143 }; 2144 2145 2146 2147 2148 /* Lan Queue Overflow Event (direct, 0x1001) */ 2149 struct ice_aqc_event_lan_overflow { 2150 __le32 prtdcb_ruptq; 2151 __le32 qtx_ctl; 2152 u8 reserved[8]; 2153 }; 2154 2155 2156 2157 /* Configure Firmware Logging Command (indirect 0xFF09) 2158 * Logging Information Read Response (indirect 0xFF10) 2159 * Note: The 0xFF10 command has no input parameters. 2160 */ 2161 struct ice_aqc_fw_logging { 2162 u8 log_ctrl; 2163 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 2164 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 2165 u8 rsvd0; 2166 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 2167 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 2168 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 2169 u8 rsvd1[5]; 2170 __le32 addr_high; 2171 __le32 addr_low; 2172 }; 2173 2174 2175 enum ice_aqc_fw_logging_mod { 2176 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2177 ICE_AQC_FW_LOG_ID_CTRL, 2178 ICE_AQC_FW_LOG_ID_LINK, 2179 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2180 ICE_AQC_FW_LOG_ID_DNL, 2181 ICE_AQC_FW_LOG_ID_I2C, 2182 ICE_AQC_FW_LOG_ID_SDP, 2183 ICE_AQC_FW_LOG_ID_MDIO, 2184 ICE_AQC_FW_LOG_ID_ADMINQ, 2185 ICE_AQC_FW_LOG_ID_HDMA, 2186 ICE_AQC_FW_LOG_ID_LLDP, 2187 ICE_AQC_FW_LOG_ID_DCBX, 2188 ICE_AQC_FW_LOG_ID_DCB, 2189 ICE_AQC_FW_LOG_ID_NETPROXY, 2190 ICE_AQC_FW_LOG_ID_NVM, 2191 ICE_AQC_FW_LOG_ID_AUTH, 2192 ICE_AQC_FW_LOG_ID_VPD, 2193 ICE_AQC_FW_LOG_ID_IOSF, 2194 ICE_AQC_FW_LOG_ID_PARSER, 2195 ICE_AQC_FW_LOG_ID_SW, 2196 ICE_AQC_FW_LOG_ID_SCHEDULER, 2197 ICE_AQC_FW_LOG_ID_TXQ, 2198 ICE_AQC_FW_LOG_ID_RSVD, 2199 ICE_AQC_FW_LOG_ID_POST, 2200 ICE_AQC_FW_LOG_ID_WATCHDOG, 2201 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2202 ICE_AQC_FW_LOG_ID_MNG, 2203 ICE_AQC_FW_LOG_ID_SYNCE, 2204 ICE_AQC_FW_LOG_ID_MAX, 2205 }; 2206 2207 /* This is the buffer for both of the logging commands. 2208 * The entry array size depends on the datalen parameter in the descriptor. 2209 * There will be a total of datalen / 2 entries. 2210 */ 2211 struct ice_aqc_fw_logging_data { 2212 __le16 entry[1]; 2213 #define ICE_AQC_FW_LOG_ID_S 0 2214 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 2215 2216 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 2217 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 2218 2219 #define ICE_AQC_FW_LOG_EN_S 12 2220 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 2221 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 2222 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 2223 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 2224 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 2225 }; 2226 2227 2228 /* Get/Clear FW Log (indirect 0xFF11) */ 2229 struct ice_aqc_get_clear_fw_log { 2230 u8 flags; 2231 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 2232 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 2233 u8 rsvd1[7]; 2234 __le32 addr_high; 2235 __le32 addr_low; 2236 }; 2237 2238 2239 /** 2240 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2241 * @flags: ICE_AQ_FLAG_* flags 2242 * @opcode: AQ command opcode 2243 * @datalen: length in bytes of indirect/external data buffer 2244 * @retval: return value from firmware 2245 * @cookie_h: opaque data high-half 2246 * @cookie_l: opaque data low-half 2247 * @params: command-specific parameters 2248 * 2249 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2250 * (ATQ). The firmware writes back onto the command descriptor and returns 2251 * the result of the command. Asynchronous events that are not an immediate 2252 * result of the command are written to the Admin Receive Queue (ARQ) using 2253 * the same descriptor format. Descriptors are in little-endian notation with 2254 * 32-bit words. 2255 */ 2256 struct ice_aq_desc { 2257 __le16 flags; 2258 __le16 opcode; 2259 __le16 datalen; 2260 __le16 retval; 2261 __le32 cookie_high; 2262 __le32 cookie_low; 2263 union { 2264 u8 raw[16]; 2265 struct ice_aqc_generic generic; 2266 struct ice_aqc_get_ver get_ver; 2267 struct ice_aqc_driver_ver driver_ver; 2268 struct ice_aqc_q_shutdown q_shutdown; 2269 struct ice_aqc_req_res res_owner; 2270 struct ice_aqc_manage_mac_read mac_read; 2271 struct ice_aqc_manage_mac_write mac_write; 2272 struct ice_aqc_clear_pxe clear_pxe; 2273 struct ice_aqc_config_no_drop_policy no_drop; 2274 struct ice_aqc_add_update_mir_rule add_update_rule; 2275 struct ice_aqc_delete_mir_rule del_rule; 2276 struct ice_aqc_list_caps get_cap; 2277 struct ice_aqc_get_phy_caps get_phy; 2278 struct ice_aqc_set_phy_cfg set_phy; 2279 struct ice_aqc_restart_an restart_an; 2280 struct ice_aqc_set_port_id_led set_port_id_led; 2281 struct ice_aqc_get_sw_cfg get_sw_conf; 2282 struct ice_aqc_sw_rules sw_rules; 2283 struct ice_aqc_storm_cfg storm_conf; 2284 struct ice_aqc_add_get_recipe add_get_recipe; 2285 struct ice_aqc_recipe_to_profile recipe_to_profile; 2286 struct ice_aqc_get_topo get_topo; 2287 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2288 struct ice_aqc_query_txsched_res query_sched_res; 2289 struct ice_aqc_query_node_to_root query_node_to_root; 2290 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2291 struct ice_aqc_query_port_ets port_ets; 2292 struct ice_aqc_rl_profile rl_profile; 2293 struct ice_aqc_nvm nvm; 2294 struct ice_aqc_nvm_cfg nvm_cfg; 2295 struct ice_aqc_nvm_checksum nvm_checksum; 2296 struct ice_aqc_pfc_ignore pfc_ignore; 2297 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2298 struct ice_aqc_set_dcb_params set_dcb_params; 2299 struct ice_aqc_lldp_get_mib lldp_get_mib; 2300 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2301 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2302 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2303 struct ice_aqc_lldp_stop lldp_stop; 2304 struct ice_aqc_lldp_start lldp_start; 2305 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2306 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2307 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2308 struct ice_aqc_get_set_rss_key get_set_rss_key; 2309 struct ice_aqc_clear_fd_table clear_fd_table; 2310 struct ice_aqc_add_txqs add_txqs; 2311 struct ice_aqc_dis_txqs dis_txqs; 2312 struct ice_aqc_txqs_cleanup txqs_cleanup; 2313 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2314 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2315 struct ice_aqc_get_vsi_resp get_vsi_resp; 2316 struct ice_aqc_download_pkg download_pkg; 2317 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2318 struct ice_aqc_fw_logging fw_logging; 2319 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 2320 struct ice_aqc_set_mac_lb set_mac_lb; 2321 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2322 struct ice_aqc_get_res_alloc get_res; 2323 struct ice_aqc_get_allocd_res_desc get_res_desc; 2324 struct ice_aqc_set_mac_cfg set_mac_cfg; 2325 struct ice_aqc_set_event_mask set_event_mask; 2326 struct ice_aqc_get_link_status get_link_status; 2327 } params; 2328 }; 2329 2330 2331 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2332 #define ICE_AQ_LG_BUF 512 2333 2334 /* Flags sub-structure 2335 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2336 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2337 */ 2338 2339 /* command flags and offsets */ 2340 #define ICE_AQ_FLAG_DD_S 0 2341 #define ICE_AQ_FLAG_CMP_S 1 2342 #define ICE_AQ_FLAG_ERR_S 2 2343 #define ICE_AQ_FLAG_VFE_S 3 2344 #define ICE_AQ_FLAG_LB_S 9 2345 #define ICE_AQ_FLAG_RD_S 10 2346 #define ICE_AQ_FLAG_VFC_S 11 2347 #define ICE_AQ_FLAG_BUF_S 12 2348 #define ICE_AQ_FLAG_SI_S 13 2349 #define ICE_AQ_FLAG_EI_S 14 2350 #define ICE_AQ_FLAG_FE_S 15 2351 2352 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2353 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2354 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2355 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2356 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2357 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2358 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2359 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2360 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2361 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2362 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2363 2364 /* error codes */ 2365 enum ice_aq_err { 2366 ICE_AQ_RC_OK = 0, /* Success */ 2367 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2368 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2369 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2370 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2371 ICE_AQ_RC_EIO = 5, /* I/O error */ 2372 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2373 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2374 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2375 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2376 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2377 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2378 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2379 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2380 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2381 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2382 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2383 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2384 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2385 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2386 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2387 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2388 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2389 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2390 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2391 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2392 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2393 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2394 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2395 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2396 }; 2397 2398 /* Admin Queue command opcodes */ 2399 enum ice_adminq_opc { 2400 /* AQ commands */ 2401 ice_aqc_opc_get_ver = 0x0001, 2402 ice_aqc_opc_driver_ver = 0x0002, 2403 ice_aqc_opc_q_shutdown = 0x0003, 2404 ice_aqc_opc_get_exp_err = 0x0005, 2405 2406 /* resource ownership */ 2407 ice_aqc_opc_req_res = 0x0008, 2408 ice_aqc_opc_release_res = 0x0009, 2409 2410 /* device/function capabilities */ 2411 ice_aqc_opc_list_func_caps = 0x000A, 2412 ice_aqc_opc_list_dev_caps = 0x000B, 2413 2414 /* manage MAC address */ 2415 ice_aqc_opc_manage_mac_read = 0x0107, 2416 ice_aqc_opc_manage_mac_write = 0x0108, 2417 2418 /* PXE */ 2419 ice_aqc_opc_clear_pxe_mode = 0x0110, 2420 2421 ice_aqc_opc_config_no_drop_policy = 0x0112, 2422 2423 /* internal switch commands */ 2424 ice_aqc_opc_get_sw_cfg = 0x0200, 2425 2426 /* Alloc/Free/Get Resources */ 2427 ice_aqc_opc_get_res_alloc = 0x0204, 2428 ice_aqc_opc_alloc_res = 0x0208, 2429 ice_aqc_opc_free_res = 0x0209, 2430 ice_aqc_opc_get_allocd_res_desc = 0x020A, 2431 2432 /* VSI commands */ 2433 ice_aqc_opc_add_vsi = 0x0210, 2434 ice_aqc_opc_update_vsi = 0x0211, 2435 ice_aqc_opc_get_vsi_params = 0x0212, 2436 ice_aqc_opc_free_vsi = 0x0213, 2437 2438 /* Mirroring rules - add/update, delete */ 2439 ice_aqc_opc_add_update_mir_rule = 0x0260, 2440 ice_aqc_opc_del_mir_rule = 0x0261, 2441 2442 /* storm configuration */ 2443 ice_aqc_opc_set_storm_cfg = 0x0280, 2444 ice_aqc_opc_get_storm_cfg = 0x0281, 2445 2446 /* recipe commands */ 2447 ice_aqc_opc_add_recipe = 0x0290, 2448 ice_aqc_opc_recipe_to_profile = 0x0291, 2449 ice_aqc_opc_get_recipe = 0x0292, 2450 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2451 2452 /* switch rules population commands */ 2453 ice_aqc_opc_add_sw_rules = 0x02A0, 2454 ice_aqc_opc_update_sw_rules = 0x02A1, 2455 ice_aqc_opc_remove_sw_rules = 0x02A2, 2456 ice_aqc_opc_get_sw_rules = 0x02A3, 2457 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2458 2459 /* DCB commands */ 2460 ice_aqc_opc_pfc_ignore = 0x0301, 2461 ice_aqc_opc_query_pfc_mode = 0x0302, 2462 ice_aqc_opc_set_pfc_mode = 0x0303, 2463 ice_aqc_opc_set_dcb_params = 0x0306, 2464 2465 /* transmit scheduler commands */ 2466 ice_aqc_opc_get_dflt_topo = 0x0400, 2467 ice_aqc_opc_add_sched_elems = 0x0401, 2468 ice_aqc_opc_cfg_sched_elems = 0x0403, 2469 ice_aqc_opc_get_sched_elems = 0x0404, 2470 ice_aqc_opc_move_sched_elems = 0x0408, 2471 ice_aqc_opc_suspend_sched_elems = 0x0409, 2472 ice_aqc_opc_resume_sched_elems = 0x040A, 2473 ice_aqc_opc_query_port_ets = 0x040E, 2474 ice_aqc_opc_delete_sched_elems = 0x040F, 2475 ice_aqc_opc_add_rl_profiles = 0x0410, 2476 ice_aqc_opc_query_rl_profiles = 0x0411, 2477 ice_aqc_opc_query_sched_res = 0x0412, 2478 ice_aqc_opc_query_node_to_root = 0x0413, 2479 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 2480 ice_aqc_opc_remove_rl_profiles = 0x0415, 2481 2482 /* PHY commands */ 2483 ice_aqc_opc_get_phy_caps = 0x0600, 2484 ice_aqc_opc_set_phy_cfg = 0x0601, 2485 ice_aqc_opc_set_mac_cfg = 0x0603, 2486 ice_aqc_opc_restart_an = 0x0605, 2487 ice_aqc_opc_get_link_status = 0x0607, 2488 ice_aqc_opc_set_event_mask = 0x0613, 2489 ice_aqc_opc_set_mac_lb = 0x0620, 2490 ice_aqc_opc_set_port_id_led = 0x06E9, 2491 ice_aqc_opc_get_port_options = 0x06EA, 2492 ice_aqc_opc_set_port_option = 0x06EB, 2493 ice_aqc_opc_set_gpio = 0x06EC, 2494 ice_aqc_opc_get_gpio = 0x06ED, 2495 2496 /* NVM commands */ 2497 ice_aqc_opc_nvm_read = 0x0701, 2498 ice_aqc_opc_nvm_erase = 0x0702, 2499 ice_aqc_opc_nvm_update = 0x0703, 2500 ice_aqc_opc_nvm_cfg_read = 0x0704, 2501 ice_aqc_opc_nvm_cfg_write = 0x0705, 2502 ice_aqc_opc_nvm_checksum = 0x0706, 2503 2504 /* LLDP commands */ 2505 ice_aqc_opc_lldp_get_mib = 0x0A00, 2506 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2507 ice_aqc_opc_lldp_add_tlv = 0x0A02, 2508 ice_aqc_opc_lldp_update_tlv = 0x0A03, 2509 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 2510 ice_aqc_opc_lldp_stop = 0x0A05, 2511 ice_aqc_opc_lldp_start = 0x0A06, 2512 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2513 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2514 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2515 2516 /* RSS commands */ 2517 ice_aqc_opc_set_rss_key = 0x0B02, 2518 ice_aqc_opc_set_rss_lut = 0x0B03, 2519 ice_aqc_opc_get_rss_key = 0x0B04, 2520 ice_aqc_opc_get_rss_lut = 0x0B05, 2521 ice_aqc_opc_clear_fd_table = 0x0B06, 2522 2523 /* Tx queue handling commands/events */ 2524 ice_aqc_opc_add_txqs = 0x0C30, 2525 ice_aqc_opc_dis_txqs = 0x0C31, 2526 ice_aqc_opc_txqs_cleanup = 0x0C31, 2527 ice_aqc_opc_move_recfg_txqs = 0x0C32, 2528 2529 /* package commands */ 2530 ice_aqc_opc_download_pkg = 0x0C40, 2531 ice_aqc_opc_upload_section = 0x0C41, 2532 ice_aqc_opc_update_pkg = 0x0C42, 2533 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2534 2535 2536 2537 /* Standalone Commands/Events */ 2538 ice_aqc_opc_event_lan_overflow = 0x1001, 2539 2540 /* debug commands */ 2541 ice_aqc_opc_fw_logging = 0xFF09, 2542 ice_aqc_opc_fw_logging_info = 0xFF10, 2543 ice_aqc_opc_get_clear_fw_log = 0xFF11 2544 }; 2545 2546 #endif /* _ICE_ADMINQ_CMD_H_ */ 2547