1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #ifndef _ICE_ADMINQ_CMD_H_ 6 #define _ICE_ADMINQ_CMD_H_ 7 8 /* This header file defines the Admin Queue commands, error codes and 9 * descriptor format. It is shared between Firmware and Software. 10 */ 11 12 #define ICE_MAX_VSI 768 13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 15 16 struct ice_aqc_generic { 17 __le32 param0; 18 __le32 param1; 19 __le32 addr_high; 20 __le32 addr_low; 21 }; 22 23 /* Get version (direct 0x0001) */ 24 struct ice_aqc_get_ver { 25 __le32 rom_ver; 26 __le32 fw_build; 27 u8 fw_branch; 28 u8 fw_major; 29 u8 fw_minor; 30 u8 fw_patch; 31 u8 api_branch; 32 u8 api_major; 33 u8 api_minor; 34 u8 api_patch; 35 }; 36 37 /* Send driver version (indirect 0x0002) */ 38 struct ice_aqc_driver_ver { 39 u8 major_ver; 40 u8 minor_ver; 41 u8 build_ver; 42 u8 subbuild_ver; 43 u8 reserved[4]; 44 __le32 addr_high; 45 __le32 addr_low; 46 }; 47 48 /* Queue Shutdown (direct 0x0003) */ 49 struct ice_aqc_q_shutdown { 50 u8 driver_unloading; 51 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 52 u8 reserved[15]; 53 }; 54 55 /* Request resource ownership (direct 0x0008) 56 * Release resource ownership (direct 0x0009) 57 */ 58 struct ice_aqc_req_res { 59 __le16 res_id; 60 #define ICE_AQC_RES_ID_NVM 1 61 #define ICE_AQC_RES_ID_SDP 2 62 #define ICE_AQC_RES_ID_CHNG_LOCK 3 63 #define ICE_AQC_RES_ID_GLBL_LOCK 4 64 __le16 access_type; 65 #define ICE_AQC_RES_ACCESS_READ 1 66 #define ICE_AQC_RES_ACCESS_WRITE 2 67 68 /* Upon successful completion, FW writes this value and driver is 69 * expected to release resource before timeout. This value is provided 70 * in milliseconds. 71 */ 72 __le32 timeout; 73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 77 /* For SDP: pin ID of the SDP */ 78 __le32 res_number; 79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 80 __le16 status; 81 #define ICE_AQ_RES_GLBL_SUCCESS 0 82 #define ICE_AQ_RES_GLBL_IN_PROG 1 83 #define ICE_AQ_RES_GLBL_DONE 2 84 u8 reserved[2]; 85 }; 86 87 /* Get function capabilities (indirect 0x000A) 88 * Get device capabilities (indirect 0x000B) 89 */ 90 struct ice_aqc_list_caps { 91 u8 cmd_flags; 92 u8 pf_index; 93 u8 reserved[2]; 94 __le32 count; 95 __le32 addr_high; 96 __le32 addr_low; 97 }; 98 99 /* Device/Function buffer entry, repeated per reported capability */ 100 struct ice_aqc_list_caps_elem { 101 __le16 cap; 102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 #define ICE_AQC_CAPS_IWARP 0x0051 113 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 114 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 115 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 116 117 u8 major_ver; 118 u8 minor_ver; 119 /* Number of resources described by this capability */ 120 __le32 number; 121 /* Only meaningful for some types of resources */ 122 __le32 logical_id; 123 /* Only meaningful for some types of resources */ 124 __le32 phys_id; 125 __le64 rsvd1; 126 __le64 rsvd2; 127 }; 128 129 /* Manage MAC address, read command - indirect (0x0107) 130 * This struct is also used for the response 131 */ 132 struct ice_aqc_manage_mac_read { 133 __le16 flags; /* Zeroed by device driver */ 134 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 135 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 136 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 137 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 138 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 139 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 140 #define ICE_AQC_MAN_MAC_READ_S 4 141 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 142 u8 rsvd[2]; 143 u8 num_addr; /* Used in response */ 144 u8 rsvd1[3]; 145 __le32 addr_high; 146 __le32 addr_low; 147 }; 148 149 /* Response buffer format for manage MAC read command */ 150 struct ice_aqc_manage_mac_read_resp { 151 u8 lport_num; 152 u8 addr_type; 153 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 154 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 155 u8 mac_addr[ETH_ALEN]; 156 }; 157 158 /* Manage MAC address, write command - direct (0x0108) */ 159 struct ice_aqc_manage_mac_write { 160 u8 rsvd; 161 u8 flags; 162 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 163 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 164 #define ICE_AQC_MAN_MAC_WR_S 6 165 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 166 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 167 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 168 /* byte stream in network order */ 169 u8 mac_addr[ETH_ALEN]; 170 __le32 addr_high; 171 __le32 addr_low; 172 }; 173 174 /* Clear PXE Command and response (direct 0x0110) */ 175 struct ice_aqc_clear_pxe { 176 u8 rx_cnt; 177 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 178 u8 reserved[15]; 179 }; 180 181 /* Configure No-Drop Policy Command (direct 0x0112) */ 182 struct ice_aqc_config_no_drop_policy { 183 u8 opts; 184 #define ICE_AQC_FORCE_NO_DROP BIT(0) 185 u8 rsvd[15]; 186 }; 187 188 /* Get switch configuration (0x0200) */ 189 struct ice_aqc_get_sw_cfg { 190 /* Reserved for command and copy of request flags for response */ 191 __le16 flags; 192 /* First desc in case of command and next_elem in case of response 193 * In case of response, if it is not zero, means all the configuration 194 * was not returned and new command shall be sent with this value in 195 * the 'first desc' field 196 */ 197 __le16 element; 198 /* Reserved for command, only used for response */ 199 __le16 num_elems; 200 __le16 rsvd; 201 __le32 addr_high; 202 __le32 addr_low; 203 }; 204 205 /* Each entry in the response buffer is of the following type: */ 206 struct ice_aqc_get_sw_cfg_resp_elem { 207 /* VSI/Port Number */ 208 __le16 vsi_port_num; 209 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 210 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 211 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 212 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 213 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 214 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 215 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 216 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 217 218 /* SWID VSI/Port belongs to */ 219 __le16 swid; 220 221 /* Bit 14..0 : PF/VF number VSI belongs to 222 * Bit 15 : VF indication bit 223 */ 224 __le16 pf_vf_num; 225 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 226 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 227 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 228 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 229 }; 230 231 /* Set Port parameters, (direct, 0x0203) */ 232 struct ice_aqc_set_port_params { 233 __le16 cmd_flags; 234 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 235 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 236 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 237 __le16 bad_frame_vsi; 238 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 239 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 240 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 241 __le16 swid; 242 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 243 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 244 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 245 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 246 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 247 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 248 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 249 u8 reserved[10]; 250 }; 251 252 /* These resource type defines are used for all switch resource 253 * commands where a resource type is required, such as: 254 * Get Resource Allocation command (indirect 0x0204) 255 * Allocate Resources command (indirect 0x0208) 256 * Free Resources command (indirect 0x0209) 257 * Get Allocated Resource Descriptors Command (indirect 0x020A) 258 */ 259 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 260 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 261 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 262 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 263 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 264 #define ICE_AQC_RES_TYPE_RECIPE 0x05 265 #define ICE_AQC_RES_TYPE_PROFILE 0x06 266 #define ICE_AQC_RES_TYPE_SWID 0x07 267 #define ICE_AQC_RES_TYPE_VSI 0x08 268 #define ICE_AQC_RES_TYPE_FLU 0x09 269 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 270 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 271 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 272 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 273 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 274 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 275 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 276 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 277 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 278 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 279 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 280 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 281 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 282 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 283 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 284 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 285 /* Resource types 0x62-67 are reserved for Hash profile builder */ 286 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 287 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 288 289 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 290 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 291 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 292 293 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 294 295 #define ICE_AQC_RES_TYPE_S 0 296 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 297 298 /* Get Resource Allocation command (indirect 0x0204) */ 299 struct ice_aqc_get_res_alloc { 300 __le16 resp_elem_num; /* Used in response, reserved in command */ 301 u8 reserved[6]; 302 __le32 addr_high; 303 __le32 addr_low; 304 }; 305 306 /* Get Resource Allocation Response Buffer per response */ 307 struct ice_aqc_get_res_resp_elem { 308 __le16 res_type; /* Types defined above cmd 0x0204 */ 309 __le16 total_capacity; /* Resources available to all PF's */ 310 __le16 total_function; /* Resources allocated for a PF */ 311 __le16 total_shared; /* Resources allocated as shared */ 312 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 313 }; 314 315 /* Allocate Resources command (indirect 0x0208) 316 * Free Resources command (indirect 0x0209) 317 */ 318 struct ice_aqc_alloc_free_res_cmd { 319 __le16 num_entries; /* Number of Resource entries */ 320 u8 reserved[6]; 321 __le32 addr_high; 322 __le32 addr_low; 323 }; 324 325 /* Resource descriptor */ 326 struct ice_aqc_res_elem { 327 union { 328 __le16 sw_resp; 329 __le16 flu_resp; 330 } e; 331 }; 332 333 /* Buffer for Allocate/Free Resources commands */ 334 struct ice_aqc_alloc_free_res_elem { 335 __le16 res_type; /* Types defined above cmd 0x0204 */ 336 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 337 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 338 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 339 __le16 num_elems; 340 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 341 }; 342 343 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 344 struct ice_aqc_get_allocd_res_desc { 345 union { 346 struct { 347 __le16 res; /* Types defined above cmd 0x0204 */ 348 __le16 first_desc; 349 __le32 reserved; 350 } cmd; 351 struct { 352 __le16 res; 353 __le16 next_desc; 354 __le16 num_desc; 355 __le16 reserved; 356 } resp; 357 } ops; 358 __le32 addr_high; 359 __le32 addr_low; 360 }; 361 362 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 363 struct ice_aqc_set_vlan_mode { 364 u8 reserved; 365 u8 l2tag_prio_tagging; 366 #define ICE_AQ_VLAN_PRIO_TAG_S 0 367 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 368 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 369 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 370 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 371 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 372 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 373 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 374 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 375 u8 l2tag_reserved[64]; 376 u8 rdma_packet; 377 #define ICE_AQ_VLAN_RDMA_TAG_S 0 378 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 379 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 380 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 381 u8 rdma_reserved[2]; 382 u8 mng_vlan_prot_id; 383 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 384 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 385 u8 prot_id_reserved[30]; 386 }; 387 388 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 389 struct ice_aqc_get_vlan_mode { 390 u8 vlan_mode; 391 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 392 u8 l2tag_prio_tagging; 393 u8 reserved[98]; 394 }; 395 396 /* Add VSI (indirect 0x0210) 397 * Update VSI (indirect 0x0211) 398 * Get VSI (indirect 0x0212) 399 * Free VSI (indirect 0x0213) 400 */ 401 struct ice_aqc_add_get_update_free_vsi { 402 __le16 vsi_num; 403 #define ICE_AQ_VSI_NUM_S 0 404 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 405 #define ICE_AQ_VSI_IS_VALID BIT(15) 406 __le16 cmd_flags; 407 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 408 u8 vf_id; 409 u8 reserved; 410 __le16 vsi_flags; 411 #define ICE_AQ_VSI_TYPE_S 0 412 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 413 #define ICE_AQ_VSI_TYPE_VF 0x0 414 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 415 #define ICE_AQ_VSI_TYPE_PF 0x2 416 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 417 __le32 addr_high; 418 __le32 addr_low; 419 }; 420 421 /* Response descriptor for: 422 * Add VSI (indirect 0x0210) 423 * Update VSI (indirect 0x0211) 424 * Free VSI (indirect 0x0213) 425 */ 426 struct ice_aqc_add_update_free_vsi_resp { 427 __le16 vsi_num; 428 __le16 ext_status; 429 __le16 vsi_used; 430 __le16 vsi_free; 431 __le32 addr_high; 432 __le32 addr_low; 433 }; 434 435 struct ice_aqc_get_vsi_resp { 436 __le16 vsi_num; 437 u8 vf_id; 438 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 439 * These are found above in struct ice_aqc_add_get_update_free_vsi. 440 */ 441 u8 vsi_flags; 442 __le16 vsi_used; 443 __le16 vsi_free; 444 __le32 addr_high; 445 __le32 addr_low; 446 }; 447 448 struct ice_aqc_vsi_props { 449 __le16 valid_sections; 450 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 451 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 452 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 453 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 454 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 455 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 456 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 457 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 458 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 459 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10) 460 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 461 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 462 /* switch section */ 463 u8 sw_id; 464 u8 sw_flags; 465 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 466 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 467 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 468 u8 sw_flags2; 469 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 470 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 471 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 472 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 473 u8 veb_stat_id; 474 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 475 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 476 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 477 /* security section */ 478 u8 sec_flags; 479 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 480 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 481 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 482 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 483 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 484 u8 sec_reserved; 485 /* VLAN section */ 486 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 487 u8 inner_vlan_reserved[2]; 488 u8 inner_vlan_flags; 489 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 490 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 491 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 492 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 493 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 494 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 495 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 496 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 497 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 498 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 499 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 500 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 501 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 502 u8 inner_vlan_reserved2[3]; 503 /* ingress egress up sections */ 504 __le32 ingress_table; /* bitmap, 3 bits per up */ 505 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 506 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 507 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 508 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 509 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 510 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 511 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 512 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 513 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 514 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 515 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 516 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 517 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 518 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 519 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 520 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 521 __le32 egress_table; /* same defines as for ingress table */ 522 /* outer tags section */ 523 __le16 port_based_outer_vlan; 524 u8 outer_vlan_flags; 525 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 526 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 527 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 528 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 529 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 530 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 531 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 532 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 533 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 534 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 535 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 536 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 537 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 538 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(6) 539 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 540 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 541 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 542 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 543 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 544 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 545 u8 outer_vlan_reserved; 546 /* queue mapping section */ 547 __le16 mapping_flags; 548 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 549 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 550 __le16 q_mapping[16]; 551 #define ICE_AQ_VSI_Q_S 0 552 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 553 __le16 tc_mapping[8]; 554 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 555 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 556 #define ICE_AQ_VSI_TC_Q_NUM_S 11 557 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 558 /* queueing option section */ 559 u8 q_opt_rss; 560 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 561 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 562 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 563 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 564 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 565 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 566 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 567 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 568 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 569 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 570 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 571 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 572 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 573 u8 q_opt_tc; 574 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 575 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 576 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 577 u8 q_opt_flags; 578 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 579 u8 q_opt_reserved[3]; 580 /* outer up section */ 581 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 582 /* ACL section */ 583 __le16 acl_def_act; 584 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0 585 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S) 586 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4 587 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S) 588 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8 589 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S) 590 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12 591 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S) 592 /* flow director section */ 593 __le16 fd_options; 594 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 595 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 596 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 597 __le16 max_fd_fltr_dedicated; 598 __le16 max_fd_fltr_shared; 599 __le16 fd_def_q; 600 #define ICE_AQ_VSI_FD_DEF_Q_S 0 601 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 602 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 603 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 604 __le16 fd_report_opt; 605 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 606 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 607 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 608 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 609 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 610 /* PASID section */ 611 __le32 pasid_id; 612 #define ICE_AQ_VSI_PASID_ID_S 0 613 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 614 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 615 u8 reserved[24]; 616 }; 617 618 /* Add/update mirror rule - direct (0x0260) */ 619 #define ICE_AQC_RULE_ID_VALID_S 7 620 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 621 #define ICE_AQC_RULE_ID_S 0 622 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 623 624 /* Following defines to be used while processing caller specified mirror list 625 * of VSI indexes. 626 */ 627 /* Action: Byte.bit (1.7) 628 * 0 = Remove VSI from mirror rule 629 * 1 = Add VSI to mirror rule 630 */ 631 #define ICE_AQC_RULE_ACT_S 15 632 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 633 /* Action: 1.2:0.0 = Mirrored VSI */ 634 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 635 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 636 637 /* This is to be used by add/update mirror rule Admin Queue command. 638 * In case of add mirror rule - if rule ID is specified as 639 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 640 * If specified rule_id is valid, then it is used. If specified rule_id 641 * is in use then new mirroring rule is added. 642 */ 643 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 644 645 struct ice_aqc_add_update_mir_rule { 646 __le16 rule_id; 647 648 __le16 rule_type; 649 #define ICE_AQC_RULE_TYPE_S 0 650 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 651 /* VPORT ingress/egress */ 652 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 653 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 654 /* Physical port ingress mirroring. 655 * All traffic received by this port 656 */ 657 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 658 /* Physical port egress mirroring. All traffic sent by this port */ 659 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 660 661 /* Number of mirrored entries. 662 * The values are in the command buffer 663 */ 664 __le16 num_entries; 665 666 /* Destination VSI */ 667 __le16 dest; 668 __le32 addr_high; 669 __le32 addr_low; 670 }; 671 672 /* Delete mirror rule - direct(0x0261) */ 673 struct ice_aqc_delete_mir_rule { 674 __le16 rule_id; 675 __le16 rsvd; 676 677 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 678 * the PF allocated resources, otherwise it is returned to the 679 * shared pool 680 */ 681 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 682 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 683 __le16 flags; 684 685 u8 reserved[10]; 686 }; 687 688 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 689 /* This structure holds get storm configuration response and same structure 690 * is used to perform set_storm_cfg 691 */ 692 struct ice_aqc_storm_cfg { 693 __le32 bcast_thresh_size; 694 __le32 mcast_thresh_size; 695 /* Bit 18:0 - Traffic upper threshold size 696 * Bit 31:19 - Reserved 697 */ 698 #define ICE_AQ_THRESHOLD_S 0 699 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 700 701 __le32 storm_ctrl_ctrl; 702 /* Bit 0: MDIPW - Drop Multicast packets in previous window 703 * Bit 1: MDICW - Drop multicast packets in current window 704 * Bit 2: BDIPW - Drop broadcast packets in previous window 705 * Bit 3: BDICW - Drop broadcast packets in current window 706 */ 707 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 708 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 709 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 710 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 711 /* Bit 7:5 : Reserved */ 712 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 713 * interval size for applying ingress broadcast or multicast storm 714 * control. 715 */ 716 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 717 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 718 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 719 __le32 reserved; 720 }; 721 722 #define ICE_MAX_NUM_RECIPES 64 723 724 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 725 struct ice_aqc_add_get_recipe { 726 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 727 __le16 return_index; /* Input, used for Get cmd only */ 728 u8 reserved[4]; 729 __le32 addr_high; 730 __le32 addr_low; 731 }; 732 733 struct ice_aqc_recipe_content { 734 u8 rid; 735 #define ICE_AQ_RECIPE_ID_S 0 736 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 737 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 738 #define ICE_AQ_SW_ID_LKUP_IDX 0 739 u8 lkup_indx[5]; 740 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 741 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 742 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 743 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 744 __le16 mask[5]; 745 u8 result_indx; 746 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 747 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 748 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 749 u8 rsvd0[3]; 750 u8 act_ctrl_join_priority; 751 u8 act_ctrl_fwd_priority; 752 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 753 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 754 u8 act_ctrl; 755 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 756 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 757 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 758 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 759 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 760 u8 rsvd1; 761 __le32 dflt_act; 762 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 763 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 764 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 765 }; 766 767 struct ice_aqc_recipe_data_elem { 768 u8 recipe_indx; 769 u8 resp_bits; 770 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 771 u8 rsvd0[2]; 772 u8 recipe_bitmap[8]; 773 u8 rsvd1[4]; 774 struct ice_aqc_recipe_content content; 775 u8 rsvd2[20]; 776 }; 777 778 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 779 struct ice_aqc_recipe_to_profile { 780 __le16 profile_id; 781 u8 rsvd[6]; 782 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES); 783 }; 784 785 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 786 */ 787 struct ice_aqc_sw_rules { 788 /* ops: add switch rules, referring the number of rules. 789 * ops: update switch rules, referring the number of filters 790 * ops: remove switch rules, referring the entry index. 791 * ops: get switch rules, referring to the number of filters. 792 */ 793 __le16 num_rules_fltr_entry_index; 794 u8 reserved[6]; 795 __le32 addr_high; 796 __le32 addr_low; 797 }; 798 799 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 800 * This structures describes the lookup rules and associated actions. "index" 801 * is returned as part of a response to a successful Add command, and can be 802 * used to identify the rule for Update/Get/Remove commands. 803 */ 804 struct ice_sw_rule_lkup_rx_tx { 805 __le16 recipe_id; 806 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 807 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 808 __le16 src; 809 __le32 act; 810 811 /* Bit 0:1 - Action type */ 812 #define ICE_SINGLE_ACT_TYPE_S 0x00 813 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 814 815 /* Bit 2 - Loop back enable 816 * Bit 3 - LAN enable 817 */ 818 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 819 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 820 821 /* Action type = 0 - Forward to VSI or VSI list */ 822 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 823 824 #define ICE_SINGLE_ACT_VSI_ID_S 4 825 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 826 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 827 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 828 /* This bit needs to be set if action is forward to VSI list */ 829 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 830 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 831 #define ICE_SINGLE_ACT_DROP BIT(18) 832 833 /* Action type = 1 - Forward to Queue of Queue group */ 834 #define ICE_SINGLE_ACT_TO_Q 0x1 835 #define ICE_SINGLE_ACT_Q_INDEX_S 4 836 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 837 #define ICE_SINGLE_ACT_Q_REGION_S 15 838 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 839 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 840 841 /* Action type = 2 - Prune */ 842 #define ICE_SINGLE_ACT_PRUNE 0x2 843 #define ICE_SINGLE_ACT_EGRESS BIT(15) 844 #define ICE_SINGLE_ACT_INGRESS BIT(16) 845 #define ICE_SINGLE_ACT_PRUNET BIT(17) 846 /* Bit 18 should be set to 0 for this action */ 847 848 /* Action type = 2 - Pointer */ 849 #define ICE_SINGLE_ACT_PTR 0x2 850 #define ICE_SINGLE_ACT_PTR_VAL_S 4 851 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 852 /* Bit 18 should be set to 1 */ 853 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 854 855 /* Action type = 3 - Other actions. Last two bits 856 * are other action identifier 857 */ 858 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 859 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 860 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 861 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 862 863 /* Bit 17:18 - Defines other actions */ 864 /* Other action = 0 - Mirror VSI */ 865 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 866 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 867 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 868 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 869 870 /* Other action = 3 - Set Stat count */ 871 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 872 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 873 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 874 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 875 876 __le16 index; /* The index of the rule in the lookup table */ 877 /* Length and values of the header to be matched per recipe or 878 * lookup-type 879 */ 880 __le16 hdr_len; 881 u8 hdr[STRUCT_HACK_VAR_LEN]; 882 }; 883 884 /* Add/Update/Remove large action command/response entry 885 * "index" is returned as part of a response to a successful Add command, and 886 * can be used to identify the action for Update/Get/Remove commands. 887 */ 888 struct ice_sw_rule_lg_act { 889 __le16 index; /* Index in large action table */ 890 __le16 size; 891 /* Max number of large actions */ 892 #define ICE_MAX_LG_ACT 4 893 /* Bit 0:1 - Action type */ 894 #define ICE_LG_ACT_TYPE_S 0 895 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 896 897 /* Action type = 0 - Forward to VSI or VSI list */ 898 #define ICE_LG_ACT_VSI_FORWARDING 0 899 #define ICE_LG_ACT_VSI_ID_S 3 900 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 901 #define ICE_LG_ACT_VSI_LIST_ID_S 3 902 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 903 /* This bit needs to be set if action is forward to VSI list */ 904 #define ICE_LG_ACT_VSI_LIST BIT(13) 905 906 #define ICE_LG_ACT_VALID_BIT BIT(16) 907 908 /* Action type = 1 - Forward to Queue of Queue group */ 909 #define ICE_LG_ACT_TO_Q 0x1 910 #define ICE_LG_ACT_Q_INDEX_S 3 911 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 912 #define ICE_LG_ACT_Q_REGION_S 14 913 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 914 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 915 916 /* Action type = 2 - Prune */ 917 #define ICE_LG_ACT_PRUNE 0x2 918 #define ICE_LG_ACT_EGRESS BIT(14) 919 #define ICE_LG_ACT_INGRESS BIT(15) 920 #define ICE_LG_ACT_PRUNET BIT(16) 921 922 /* Action type = 3 - Mirror VSI */ 923 #define ICE_LG_OTHER_ACT_MIRROR 0x3 924 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 925 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 926 927 /* Action type = 5 - Generic Value */ 928 #define ICE_LG_ACT_GENERIC 0x5 929 #define ICE_LG_ACT_GENERIC_VALUE_S 3 930 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 931 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 932 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 933 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 934 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 935 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 936 937 /* Action = 7 - Set Stat count */ 938 #define ICE_LG_ACT_STAT_COUNT 0x7 939 #define ICE_LG_ACT_STAT_COUNT_S 3 940 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 941 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 942 }; 943 944 /* Add/Update/Remove VSI list command/response entry 945 * "index" is returned as part of a response to a successful Add command, and 946 * can be used to identify the VSI list for Update/Get/Remove commands. 947 */ 948 struct ice_sw_rule_vsi_list { 949 __le16 index; /* Index of VSI/Prune list */ 950 __le16 number_vsi; 951 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 952 }; 953 954 #pragma pack(1) 955 /* Query VSI list command/response entry */ 956 struct ice_sw_rule_vsi_list_query { 957 __le16 index; 958 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 959 }; 960 #pragma pack() 961 962 #pragma pack(1) 963 /* Add switch rule response: 964 * Content of return buffer is same as the input buffer. The status field and 965 * LUT index are updated as part of the response 966 */ 967 struct ice_aqc_sw_rules_elem { 968 __le16 type; /* Switch rule type, one of T_... */ 969 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 970 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 971 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 972 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 973 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 974 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 975 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 976 __le16 status; 977 union { 978 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 979 struct ice_sw_rule_lg_act lg_act; 980 struct ice_sw_rule_vsi_list vsi_list; 981 struct ice_sw_rule_vsi_list_query vsi_list_query; 982 } pdata; 983 }; 984 985 #pragma pack() 986 987 /* PFC Ignore (direct 0x0301) 988 * The command and response use the same descriptor structure 989 */ 990 struct ice_aqc_pfc_ignore { 991 u8 tc_bitmap; 992 u8 cmd_flags; /* unused in response */ 993 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 994 #define ICE_AQC_PFC_IGNORE_CLEAR 0 995 u8 reserved[14]; 996 }; 997 998 /* Set PFC Mode (direct 0x0303) 999 * Query PFC Mode (direct 0x0302) 1000 */ 1001 struct ice_aqc_set_query_pfc_mode { 1002 u8 pfc_mode; 1003 /* For Set Command response, reserved in all other cases */ 1004 #define ICE_AQC_PFC_NOT_CONFIGURED 0 1005 /* For Query Command response, reserved in all other cases */ 1006 #define ICE_AQC_DCB_DIS 0 1007 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 1008 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 1009 u8 rsvd[15]; 1010 }; 1011 1012 /* Set DCB Parameters (direct 0x0306) */ 1013 struct ice_aqc_set_dcb_params { 1014 u8 cmd_flags; /* unused in response */ 1015 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 1016 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 1017 u8 valid_flags; /* unused in response */ 1018 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1019 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 1020 u8 rsvd[14]; 1021 }; 1022 1023 /* Get Default Topology (indirect 0x0400) */ 1024 struct ice_aqc_get_topo { 1025 u8 port_num; 1026 u8 num_branches; 1027 __le16 reserved1; 1028 __le32 reserved2; 1029 __le32 addr_high; 1030 __le32 addr_low; 1031 }; 1032 1033 /* Update TSE (indirect 0x0403) 1034 * Get TSE (indirect 0x0404) 1035 * Add TSE (indirect 0x0401) 1036 * Delete TSE (indirect 0x040F) 1037 * Move TSE (indirect 0x0408) 1038 * Suspend Nodes (indirect 0x0409) 1039 * Resume Nodes (indirect 0x040A) 1040 */ 1041 struct ice_aqc_sched_elem_cmd { 1042 __le16 num_elem_req; /* Used by commands */ 1043 __le16 num_elem_resp; /* Used by responses */ 1044 __le32 reserved; 1045 __le32 addr_high; 1046 __le32 addr_low; 1047 }; 1048 1049 struct ice_aqc_txsched_move_grp_info_hdr { 1050 __le32 src_parent_teid; 1051 __le32 dest_parent_teid; 1052 __le16 num_elems; 1053 u8 flags; 1054 u8 reserved; 1055 }; 1056 1057 struct ice_aqc_move_elem { 1058 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1059 __le32 teid[STRUCT_HACK_VAR_LEN]; 1060 }; 1061 1062 struct ice_aqc_elem_info_bw { 1063 __le16 bw_profile_idx; 1064 __le16 bw_alloc; 1065 }; 1066 1067 struct ice_aqc_txsched_elem { 1068 u8 elem_type; /* Special field, reserved for some aq calls */ 1069 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1070 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1071 #define ICE_AQC_ELEM_TYPE_TC 0x2 1072 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1073 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1074 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1075 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1076 u8 valid_sections; 1077 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1078 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1079 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1080 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1081 u8 generic; 1082 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1083 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1084 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1085 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1086 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1087 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1088 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1089 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1090 u8 flags; /* Special field, reserved for some aq calls */ 1091 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1092 struct ice_aqc_elem_info_bw cir_bw; 1093 struct ice_aqc_elem_info_bw eir_bw; 1094 __le16 srl_id; 1095 __le16 reserved2; 1096 }; 1097 1098 struct ice_aqc_txsched_elem_data { 1099 __le32 parent_teid; 1100 __le32 node_teid; 1101 struct ice_aqc_txsched_elem data; 1102 }; 1103 1104 struct ice_aqc_txsched_topo_grp_info_hdr { 1105 __le32 parent_teid; 1106 __le16 num_elems; 1107 __le16 reserved2; 1108 }; 1109 1110 struct ice_aqc_add_elem { 1111 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1112 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1113 }; 1114 1115 struct ice_aqc_get_topo_elem { 1116 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1117 struct ice_aqc_txsched_elem_data 1118 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1119 }; 1120 1121 struct ice_aqc_delete_elem { 1122 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1123 __le32 teid[STRUCT_HACK_VAR_LEN]; 1124 }; 1125 1126 /* Query Port ETS (indirect 0x040E) 1127 * 1128 * This indirect command is used to query port TC node configuration. 1129 */ 1130 struct ice_aqc_query_port_ets { 1131 __le32 port_teid; 1132 __le32 reserved; 1133 __le32 addr_high; 1134 __le32 addr_low; 1135 }; 1136 1137 struct ice_aqc_port_ets_elem { 1138 u8 tc_valid_bits; 1139 u8 reserved[3]; 1140 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1141 __le32 up2tc; 1142 u8 tc_bw_share[8]; 1143 __le32 port_eir_prof_id; 1144 __le32 port_cir_prof_id; 1145 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1146 __le32 tc_node_prio; 1147 #define ICE_TC_NODE_PRIO_S 0x4 1148 u8 reserved1[4]; 1149 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1150 }; 1151 1152 /* Rate limiting profile for 1153 * Add RL profile (indirect 0x0410) 1154 * Query RL profile (indirect 0x0411) 1155 * Remove RL profile (indirect 0x0415) 1156 * These indirect commands acts on single or multiple 1157 * RL profiles with specified data. 1158 */ 1159 struct ice_aqc_rl_profile { 1160 __le16 num_profiles; 1161 __le16 num_processed; /* Only for response. Reserved in Command. */ 1162 u8 reserved[4]; 1163 __le32 addr_high; 1164 __le32 addr_low; 1165 }; 1166 1167 struct ice_aqc_rl_profile_elem { 1168 u8 level; 1169 u8 flags; 1170 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1171 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1172 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1173 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1174 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1175 /* The following flag is used for Query RL Profile Data */ 1176 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1177 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1178 1179 __le16 profile_id; 1180 __le16 max_burst_size; 1181 __le16 rl_multiply; 1182 __le16 wake_up_calc; 1183 __le16 rl_encode; 1184 }; 1185 1186 /* Configure L2 Node CGD (indirect 0x0414) 1187 * This indirect command allows configuring a congestion domain for given L2 1188 * node TEIDs in the scheduler topology. 1189 */ 1190 struct ice_aqc_cfg_l2_node_cgd { 1191 __le16 num_l2_nodes; 1192 u8 reserved[6]; 1193 __le32 addr_high; 1194 __le32 addr_low; 1195 }; 1196 1197 struct ice_aqc_cfg_l2_node_cgd_elem { 1198 __le32 node_teid; 1199 u8 cgd; 1200 u8 reserved[3]; 1201 }; 1202 1203 /* Query Scheduler Resource Allocation (indirect 0x0412) 1204 * This indirect command retrieves the scheduler resources allocated by 1205 * EMP Firmware to the given PF. 1206 */ 1207 struct ice_aqc_query_txsched_res { 1208 u8 reserved[8]; 1209 __le32 addr_high; 1210 __le32 addr_low; 1211 }; 1212 1213 struct ice_aqc_generic_sched_props { 1214 __le16 phys_levels; 1215 __le16 logical_levels; 1216 u8 flattening_bitmap; 1217 u8 max_device_cgds; 1218 u8 max_pf_cgds; 1219 u8 rsvd0; 1220 __le16 rdma_qsets; 1221 u8 rsvd1[22]; 1222 }; 1223 1224 struct ice_aqc_layer_props { 1225 u8 logical_layer; 1226 u8 chunk_size; 1227 __le16 max_device_nodes; 1228 __le16 max_pf_nodes; 1229 u8 rsvd0[4]; 1230 __le16 max_sibl_grp_sz; 1231 __le16 max_cir_rl_profiles; 1232 __le16 max_eir_rl_profiles; 1233 __le16 max_srl_profiles; 1234 u8 rsvd1[14]; 1235 }; 1236 1237 struct ice_aqc_query_txsched_res_resp { 1238 struct ice_aqc_generic_sched_props sched_props; 1239 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1240 }; 1241 1242 /* Query Node to Root Topology (indirect 0x0413) 1243 * This command uses ice_aqc_get_elem as its data buffer. 1244 */ 1245 struct ice_aqc_query_node_to_root { 1246 __le32 teid; 1247 __le32 num_nodes; /* Response only */ 1248 __le32 addr_high; 1249 __le32 addr_low; 1250 }; 1251 1252 /* Get PHY capabilities (indirect 0x0600) */ 1253 struct ice_aqc_get_phy_caps { 1254 u8 lport_num; 1255 u8 reserved; 1256 __le16 param0; 1257 /* 18.0 - Report qualified modules */ 1258 #define ICE_AQC_GET_PHY_RQM BIT(0) 1259 /* 18.1 - 18.3 : Report mode 1260 * 000b - Report NVM capabilities 1261 * 001b - Report topology capabilities 1262 * 010b - Report SW configured 1263 * 100b - Report default capabilities 1264 */ 1265 #define ICE_AQC_REPORT_MODE_S 1 1266 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1267 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1268 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1269 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1270 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1271 __le32 reserved1; 1272 __le32 addr_high; 1273 __le32 addr_low; 1274 }; 1275 1276 /* This is #define of PHY type (Extended): 1277 * The first set of defines is for phy_type_low. 1278 */ 1279 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1280 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1281 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1282 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1283 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1284 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1285 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1286 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1287 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1288 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1289 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1290 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1291 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1292 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1293 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1294 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1295 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1296 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1297 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1298 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1299 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1300 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1301 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1302 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1303 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1304 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1305 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1306 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1307 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1308 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1309 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1310 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1311 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1312 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1313 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1314 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1315 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1316 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1317 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1318 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1319 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1320 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1321 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1322 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1323 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1324 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1325 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1326 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1327 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1328 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1329 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1330 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1331 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1332 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1333 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1334 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1335 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1336 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1337 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1338 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1339 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1340 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1341 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1342 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1343 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1344 /* The second set of defines is for phy_type_high. */ 1345 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1346 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1347 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1348 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1349 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1350 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1351 1352 struct ice_aqc_get_phy_caps_data { 1353 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1354 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1355 u8 caps; 1356 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1357 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1358 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1359 #define ICE_AQC_PHY_EN_LINK BIT(3) 1360 #define ICE_AQC_PHY_AN_MODE BIT(4) 1361 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1362 #define ICE_AQC_PHY_EN_LESM BIT(6) 1363 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1364 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1365 u8 low_power_ctrl_an; 1366 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1367 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1368 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1369 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1370 __le16 eee_cap; 1371 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1372 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1373 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1374 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1375 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1376 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1377 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1378 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1379 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1380 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1381 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1382 __le16 eeer_value; 1383 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1384 u8 phy_fw_ver[8]; 1385 u8 link_fec_options; 1386 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1387 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1388 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1389 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1390 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1391 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1392 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1393 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1394 u8 module_compliance_enforcement; 1395 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1396 u8 extended_compliance_code; 1397 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1398 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1399 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1400 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1401 #define ICE_AQC_MOD_TYPE_IDENT 1 1402 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1403 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1404 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1405 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1406 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1407 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1408 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1409 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1410 u8 qualified_module_count; 1411 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1412 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1413 struct { 1414 u8 v_oui[3]; 1415 u8 rsvd3; 1416 u8 v_part[16]; 1417 __le32 v_rev; 1418 __le64 rsvd4; 1419 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1420 }; 1421 1422 /* Set PHY capabilities (direct 0x0601) 1423 * NOTE: This command must be followed by setup link and restart auto-neg 1424 */ 1425 struct ice_aqc_set_phy_cfg { 1426 u8 lport_num; 1427 u8 reserved[7]; 1428 __le32 addr_high; 1429 __le32 addr_low; 1430 }; 1431 1432 /* Set PHY config command data structure */ 1433 struct ice_aqc_set_phy_cfg_data { 1434 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1435 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1436 u8 caps; 1437 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1438 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1439 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1440 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1441 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1442 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1443 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1444 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1445 u8 low_power_ctrl_an; 1446 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1447 __le16 eeer_value; 1448 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1449 u8 module_compliance_enforcement; 1450 }; 1451 1452 /* Set MAC Config command data structure (direct 0x0603) */ 1453 struct ice_aqc_set_mac_cfg { 1454 __le16 max_frame_size; 1455 u8 params; 1456 #define ICE_AQ_SET_MAC_PACE_S 3 1457 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1458 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1459 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1460 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1461 u8 tx_tmr_priority; 1462 __le16 tx_tmr_value; 1463 __le16 fc_refresh_threshold; 1464 u8 drop_opts; 1465 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1466 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1467 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1468 u8 reserved[7]; 1469 }; 1470 1471 /* Restart AN command data structure (direct 0x0605) 1472 * Also used for response, with only the lport_num field present. 1473 */ 1474 struct ice_aqc_restart_an { 1475 u8 lport_num; 1476 u8 reserved; 1477 u8 cmd_flags; 1478 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1479 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1480 u8 reserved2[13]; 1481 }; 1482 1483 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1484 struct ice_aqc_get_link_status { 1485 u8 lport_num; 1486 u8 reserved; 1487 __le16 cmd_flags; 1488 #define ICE_AQ_LSE_M 0x3 1489 #define ICE_AQ_LSE_NOP 0x0 1490 #define ICE_AQ_LSE_DIS 0x2 1491 #define ICE_AQ_LSE_ENA 0x3 1492 /* only response uses this flag */ 1493 #define ICE_AQ_LSE_IS_ENABLED 0x1 1494 __le32 reserved2; 1495 __le32 addr_high; 1496 __le32 addr_low; 1497 }; 1498 1499 /* Get link status response data structure, also used for Link Status Event */ 1500 struct ice_aqc_get_link_status_data { 1501 u8 topo_media_conflict; 1502 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1503 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1504 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1505 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1506 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1507 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1508 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1509 u8 link_cfg_err; 1510 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1511 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1512 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1513 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1514 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1515 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1516 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1517 u8 link_info; 1518 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1519 #define ICE_AQ_LINK_FAULT BIT(1) 1520 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1521 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1522 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1523 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1524 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1525 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1526 u8 an_info; 1527 #define ICE_AQ_AN_COMPLETED BIT(0) 1528 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1529 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1530 #define ICE_AQ_FEC_EN BIT(3) 1531 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1532 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1533 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1534 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1535 u8 ext_info; 1536 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1537 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1538 /* Port Tx Suspended */ 1539 #define ICE_AQ_LINK_TX_S 2 1540 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1541 #define ICE_AQ_LINK_TX_ACTIVE 0 1542 #define ICE_AQ_LINK_TX_DRAINED 1 1543 #define ICE_AQ_LINK_TX_FLUSHED 3 1544 u8 lb_status; 1545 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1546 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1547 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1548 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1549 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1550 __le16 max_frame_size; 1551 u8 cfg; 1552 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1553 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1554 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1555 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1556 /* Pacing Config */ 1557 #define ICE_AQ_CFG_PACING_S 3 1558 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1559 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1560 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1561 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1562 /* External Device Power Ability */ 1563 u8 power_desc; 1564 #define ICE_AQ_PWR_CLASS_M 0x3F 1565 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1566 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1567 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1568 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1569 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1570 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1571 __le16 link_speed; 1572 #define ICE_AQ_LINK_SPEED_M 0x7FF 1573 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1574 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1575 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1576 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1577 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1578 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1579 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1580 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1581 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1582 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1583 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1584 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1585 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1586 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1587 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1588 }; 1589 1590 /* Set event mask command (direct 0x0613) */ 1591 struct ice_aqc_set_event_mask { 1592 u8 lport_num; 1593 u8 reserved[7]; 1594 __le16 event_mask; 1595 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1596 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1597 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1598 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1599 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1600 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1601 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1602 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1603 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1604 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1605 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1606 u8 reserved1[6]; 1607 }; 1608 1609 /* Set MAC Loopback command (direct 0x0620) */ 1610 struct ice_aqc_set_mac_lb { 1611 u8 lb_mode; 1612 #define ICE_AQ_MAC_LB_EN BIT(0) 1613 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1614 u8 reserved[15]; 1615 }; 1616 1617 struct ice_aqc_link_topo_addr { 1618 u8 lport_num; 1619 u8 lport_num_valid; 1620 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1621 u8 node_type_ctx; 1622 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1623 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1624 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1625 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1626 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1627 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1628 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1629 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1630 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1631 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1632 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1633 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1634 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1635 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1636 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1637 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1638 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1639 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1640 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1641 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1642 u8 index; 1643 __le16 handle; 1644 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1645 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1646 /* Used to decode the handle field */ 1647 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1648 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1649 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1650 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1651 /* In case of a Mezzanine type */ 1652 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1653 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1654 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1655 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1656 /* In case of a LOM type */ 1657 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1658 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1659 }; 1660 1661 /* Get Link Topology Handle (direct, 0x06E0) */ 1662 struct ice_aqc_get_link_topo { 1663 struct ice_aqc_link_topo_addr addr; 1664 u8 node_part_num; 1665 u8 rsvd[9]; 1666 }; 1667 1668 /* Set Port Identification LED (direct, 0x06E9) */ 1669 struct ice_aqc_set_port_id_led { 1670 u8 lport_num; 1671 u8 lport_num_valid; 1672 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1673 u8 ident_mode; 1674 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1675 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1676 u8 rsvd[13]; 1677 }; 1678 1679 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1680 struct ice_aqc_sff_eeprom { 1681 u8 lport_num; 1682 u8 lport_num_valid; 1683 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1684 __le16 i2c_bus_addr; 1685 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1686 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1687 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1688 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1689 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1690 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1691 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1692 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1693 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1694 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1695 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1696 __le16 i2c_mem_addr; 1697 __le16 eeprom_page; 1698 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1699 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1700 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1701 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1702 __le32 addr_high; 1703 __le32 addr_low; 1704 }; 1705 1706 /* SW Set GPIO command (indirect 0x6EF) 1707 * SW Get GPIO command (indirect 0x6F0) 1708 */ 1709 struct ice_aqc_sw_gpio { 1710 __le16 gpio_ctrl_handle; 1711 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 1712 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 1713 u8 gpio_num; 1714 #define ICE_AQC_SW_GPIO_NUMBER_S 0 1715 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 1716 u8 gpio_params; 1717 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 1718 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 1719 u8 rsvd[12]; 1720 }; 1721 1722 /* Program topology device NVM (direct, 0x06F2) */ 1723 struct ice_aqc_program_topology_device_nvm { 1724 u8 lport_num; 1725 u8 lport_num_valid; 1726 u8 node_type_ctx; 1727 u8 index; 1728 u8 rsvd[12]; 1729 }; 1730 1731 /* Read topology device NVM (indirect, 0x06F3) */ 1732 struct ice_aqc_read_topology_device_nvm { 1733 u8 lport_num; 1734 u8 lport_num_valid; 1735 u8 node_type_ctx; 1736 u8 index; 1737 __le32 start_address; 1738 u8 data_read[8]; 1739 }; 1740 1741 /* NVM Read command (indirect 0x0701) 1742 * NVM Erase commands (direct 0x0702) 1743 * NVM Write commands (indirect 0x0703) 1744 * NVM Write Activate commands (direct 0x0707) 1745 * NVM Shadow RAM Dump commands (direct 0x0707) 1746 */ 1747 struct ice_aqc_nvm { 1748 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1749 __le16 offset_low; 1750 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 1751 u8 cmd_flags; 1752 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1753 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 1754 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 1755 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1756 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1757 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1758 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1759 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1760 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1761 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1762 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1763 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1764 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1765 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 1766 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1767 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ 1768 #define ICE_AQC_NVM_PERST_FLAG 1 1769 #define ICE_AQC_NVM_EMPR_FLAG 2 1770 #define ICE_AQC_NVM_EMPR_ENA BIT(0) 1771 __le16 module_typeid; 1772 __le16 length; 1773 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1774 __le32 addr_high; 1775 __le32 addr_low; 1776 }; 1777 1778 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 1779 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 1780 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 1781 1782 #define ICE_AQC_NVM_START_POINT 0 1783 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 1784 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 1785 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 1786 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 1787 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 1788 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 1789 1790 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 1791 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 1792 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 1793 1794 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 1795 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 1796 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 1797 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 1798 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 1799 1800 /* Used for 0x0704 as well as for 0x0705 commands */ 1801 struct ice_aqc_nvm_cfg { 1802 u8 cmd_flags; 1803 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 1804 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 1805 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 1806 u8 reserved; 1807 __le16 count; 1808 __le16 id; 1809 u8 reserved1[2]; 1810 __le32 addr_high; 1811 __le32 addr_low; 1812 }; 1813 1814 struct ice_aqc_nvm_cfg_data { 1815 __le16 field_id; 1816 __le16 field_options; 1817 __le16 field_value; 1818 }; 1819 1820 /* NVM Checksum Command (direct, 0x0706) */ 1821 struct ice_aqc_nvm_checksum { 1822 u8 flags; 1823 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1824 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1825 u8 rsvd; 1826 __le16 checksum; /* Used only by response */ 1827 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1828 u8 rsvd2[12]; 1829 }; 1830 1831 /* Get LLDP MIB (indirect 0x0A00) 1832 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1833 * as the format is the same. 1834 */ 1835 struct ice_aqc_lldp_get_mib { 1836 u8 type; 1837 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1838 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1839 #define ICE_AQ_LLDP_MIB_LOCAL 0 1840 #define ICE_AQ_LLDP_MIB_REMOTE 1 1841 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1842 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1843 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1844 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1845 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1846 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1847 #define ICE_AQ_LLDP_TX_S 0x4 1848 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1849 #define ICE_AQ_LLDP_TX_ACTIVE 0 1850 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1851 #define ICE_AQ_LLDP_TX_FLUSHED 3 1852 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1853 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1854 * Get LLDP MIB (0x0A00) response only. 1855 */ 1856 u8 reserved1; 1857 __le16 local_len; 1858 __le16 remote_len; 1859 u8 reserved2[2]; 1860 __le32 addr_high; 1861 __le32 addr_low; 1862 }; 1863 1864 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1865 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1866 struct ice_aqc_lldp_set_mib_change { 1867 u8 command; 1868 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1869 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1870 u8 reserved[15]; 1871 }; 1872 1873 /* Add LLDP TLV (indirect 0x0A02) 1874 * Delete LLDP TLV (indirect 0x0A04) 1875 */ 1876 struct ice_aqc_lldp_add_delete_tlv { 1877 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1878 u8 reserved1[1]; 1879 __le16 len; 1880 u8 reserved2[4]; 1881 __le32 addr_high; 1882 __le32 addr_low; 1883 }; 1884 1885 /* Update LLDP TLV (indirect 0x0A03) */ 1886 struct ice_aqc_lldp_update_tlv { 1887 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1888 u8 reserved; 1889 __le16 old_len; 1890 __le16 new_offset; 1891 __le16 new_len; 1892 __le32 addr_high; 1893 __le32 addr_low; 1894 }; 1895 1896 /* Stop LLDP (direct 0x0A05) */ 1897 struct ice_aqc_lldp_stop { 1898 u8 command; 1899 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1900 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1901 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1902 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1903 u8 reserved[15]; 1904 }; 1905 1906 /* Start LLDP (direct 0x0A06) */ 1907 struct ice_aqc_lldp_start { 1908 u8 command; 1909 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1910 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1911 u8 reserved[15]; 1912 }; 1913 1914 /* Get CEE DCBX Oper Config (0x0A07) 1915 * The command uses the generic descriptor struct and 1916 * returns the struct below as an indirect response. 1917 */ 1918 struct ice_aqc_get_cee_dcb_cfg_resp { 1919 u8 oper_num_tc; 1920 u8 oper_prio_tc[4]; 1921 u8 oper_tc_bw[8]; 1922 u8 oper_pfc_en; 1923 __le16 oper_app_prio; 1924 #define ICE_AQC_CEE_APP_FCOE_S 0 1925 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1926 #define ICE_AQC_CEE_APP_ISCSI_S 3 1927 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1928 #define ICE_AQC_CEE_APP_FIP_S 8 1929 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1930 __le32 tlv_status; 1931 #define ICE_AQC_CEE_PG_STATUS_S 0 1932 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1933 #define ICE_AQC_CEE_PFC_STATUS_S 3 1934 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1935 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1936 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1937 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1938 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1939 #define ICE_AQC_CEE_FIP_STATUS_S 16 1940 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1941 u8 reserved[12]; 1942 }; 1943 1944 /* Set Local LLDP MIB (indirect 0x0A08) 1945 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1946 */ 1947 struct ice_aqc_lldp_set_local_mib { 1948 u8 type; 1949 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1950 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1951 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1952 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1953 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1954 u8 reserved0; 1955 __le16 length; 1956 u8 reserved1[4]; 1957 __le32 addr_high; 1958 __le32 addr_low; 1959 }; 1960 1961 struct ice_aqc_lldp_set_local_mib_resp { 1962 u8 status; 1963 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 1964 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 1965 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 1966 u8 reserved[15]; 1967 }; 1968 1969 /* Stop/Start LLDP Agent (direct 0x0A09) 1970 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1971 * The same structure is used for the response, with the command field 1972 * being used as the status field. 1973 */ 1974 struct ice_aqc_lldp_stop_start_specific_agent { 1975 u8 command; 1976 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1977 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1978 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1979 u8 reserved[15]; 1980 }; 1981 1982 /* LLDP Filter Control (direct 0x0A0A) */ 1983 struct ice_aqc_lldp_filter_ctrl { 1984 u8 cmd_flags; 1985 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 1986 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1987 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1988 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 1989 u8 reserved1; 1990 __le16 vsi_num; 1991 u8 reserved2[12]; 1992 }; 1993 1994 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1995 struct ice_aqc_get_set_rss_key { 1996 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1997 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1998 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1999 __le16 vsi_id; 2000 u8 reserved[6]; 2001 __le32 addr_high; 2002 __le32 addr_low; 2003 }; 2004 2005 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2006 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2007 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2008 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2009 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2010 2011 /** 2012 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2013 * @standard_rss_key: 40 most significant bytes of hash key 2014 * @extended_hash_key: 12 least significant bytes of hash key 2015 * 2016 * Set/Get 40 byte hash key using standard_rss_key field, and set 2017 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2018 * standard_rss_key field for 40 most significant bytes and the 2019 * extended_hash_key field for the 12 least significant bytes of hash key. 2020 */ 2021 struct ice_aqc_get_set_rss_keys { 2022 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2023 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2024 }; 2025 2026 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2027 struct ice_aqc_get_set_rss_lut { 2028 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2029 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2030 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2031 __le16 vsi_id; 2032 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2033 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2034 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2035 2036 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2037 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2038 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2039 2040 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2041 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2042 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2043 2044 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2045 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2046 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2047 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2048 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2049 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2050 2051 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2052 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2053 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2054 2055 __le16 flags; 2056 __le32 reserved; 2057 __le32 addr_high; 2058 __le32 addr_low; 2059 }; 2060 2061 /* Clear FD Table Command (direct, 0x0B06) */ 2062 struct ice_aqc_clear_fd_table { 2063 u8 clear_type; 2064 #define CL_FD_VM_VF_TYPE_VSI_IDX 1 2065 #define CL_FD_VM_VF_TYPE_PF_IDX 2 2066 u8 rsvd; 2067 __le16 vsi_index; 2068 u8 reserved[12]; 2069 }; 2070 2071 /* Allocate ACL table (indirect 0x0C10) */ 2072 #define ICE_AQC_ACL_KEY_WIDTH 40 2073 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5 2074 #define ICE_AQC_ACL_TCAM_DEPTH 512 2075 #define ICE_ACL_ENTRY_ALLOC_UNIT 64 2076 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15 2077 #define ICE_AQC_MAX_ACTION_MEMORIES 20 2078 #define ICE_AQC_MAX_ACTION_ENTRIES 512 2079 #define ICE_AQC_ACL_SLICES 16 2080 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000 2081 /* The ACL block supports up to 8 actions per a single output. */ 2082 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4 2083 2084 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \ 2085 ICE_ACL_ENTRY_ALLOC_UNIT) 2086 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \ 2087 ICE_AQC_MAX_TCAM_ALLOC_UNITS) 2088 2089 struct ice_aqc_acl_alloc_table { 2090 __le16 table_width; 2091 __le16 table_depth; 2092 u8 act_pairs_per_entry; 2093 /* For non-concurrent table allocation, this field needs 2094 * to be set to zero(0) otherwise it shall specify the 2095 * amount of concurrent tables whose AllocIDs are 2096 * specified in buffer. Thus the newly allocated table 2097 * is concurrent with table IDs specified in AllocIDs. 2098 */ 2099 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0 2100 u8 table_type; 2101 __le16 reserved; 2102 __le32 addr_high; 2103 __le32 addr_low; 2104 }; 2105 2106 /* Allocate ACL table command buffer format */ 2107 struct ice_aqc_acl_alloc_table_data { 2108 /* Dependent table AllocIDs. Each word in this 15 word array specifies 2109 * a dependent table AllocID according to the amount specified in the 2110 * "table_type" field. All unused words shall be set to 0xFFFF 2111 */ 2112 #define ICE_AQC_CONCURR_ID_INVALID 0xffff 2113 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL]; 2114 }; 2115 2116 /* Deallocate ACL table (indirect 0x0C11) 2117 * Allocate ACL action-pair (indirect 0x0C12) 2118 * Deallocate ACL action-pair (indirect 0x0C13) 2119 */ 2120 2121 /* Following structure is common and used in case of deallocation 2122 * of ACL table and action-pair 2123 */ 2124 struct ice_aqc_acl_tbl_actpair { 2125 /* Alloc ID of the table being released */ 2126 __le16 alloc_id; 2127 u8 reserved[6]; 2128 __le32 addr_high; 2129 __le32 addr_low; 2130 }; 2131 2132 /* This response structure is same in case of alloc/dealloc table, 2133 * alloc/dealloc action-pair 2134 */ 2135 struct ice_aqc_acl_generic { 2136 /* if alloc_id is below 0x1000 then alllocation failed due to 2137 * unavailable resources, else this is set by FW to identify 2138 * table allocation 2139 */ 2140 __le16 alloc_id; 2141 2142 union { 2143 /* to be used only in case of alloc/dealloc table */ 2144 struct { 2145 /* Index of the first TCAM block, otherwise set to 0xFF 2146 * for a failed allocation 2147 */ 2148 u8 first_tcam; 2149 /* Index of the last TCAM block. This index shall be 2150 * set to the value of first_tcam for single TCAM block 2151 * allocation, otherwise set to 0xFF for a failed 2152 * allocation 2153 */ 2154 u8 last_tcam; 2155 } table; 2156 /* reserved in case of alloc/dealloc action-pair */ 2157 struct { 2158 __le16 reserved; 2159 } act_pair; 2160 } ops; 2161 2162 /* index of first entry (in both TCAM and action memories), 2163 * otherwise set to 0xFF for a failed allocation 2164 */ 2165 __le16 first_entry; 2166 /* index of last entry (in both TCAM and action memories), 2167 * otherwise set to 0xFF for a failed allocation 2168 */ 2169 __le16 last_entry; 2170 2171 /* Each act_mem element specifies the order of the memory 2172 * otherwise 0xFF 2173 */ 2174 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES]; 2175 }; 2176 2177 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate 2178 * response buffer since original command buffer gets updated with 2179 * 'scen_id' in case of success 2180 */ 2181 struct ice_aqc_acl_alloc_scen { 2182 union { 2183 struct { 2184 u8 reserved[8]; 2185 } cmd; 2186 struct { 2187 __le16 scen_id; 2188 u8 reserved[6]; 2189 } resp; 2190 } ops; 2191 __le32 addr_high; 2192 __le32 addr_low; 2193 }; 2194 2195 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need 2196 * separate response buffer since nothing to be returned as a response 2197 * except status. 2198 */ 2199 struct ice_aqc_acl_dealloc_scen { 2200 __le16 scen_id; 2201 u8 reserved[14]; 2202 }; 2203 2204 /* Update ACL scenario (direct 0x0C1B) 2205 * Query ACL scenario (direct 0x0C23) 2206 */ 2207 struct ice_aqc_acl_update_query_scen { 2208 __le16 scen_id; 2209 u8 reserved[6]; 2210 __le32 addr_high; 2211 __le32 addr_low; 2212 }; 2213 2214 /* Input buffer format in case allocate/update ACL scenario and same format 2215 * is used for response buffer in case of query ACL scenario. 2216 * NOTE: de-allocate ACL scenario is direct command and doesn't require 2217 * "buffer", hence no buffer format. 2218 */ 2219 struct ice_aqc_acl_scen { 2220 struct { 2221 /* Byte [x] selection for the TCAM key. This value must be 2222 * set to 0x0 for unusued TCAM. 2223 * Only Bit 6..0 is used in each byte and MSB is reserved 2224 */ 2225 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F 2226 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20 2227 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E 2228 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE 2229 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F 2230 u8 tcam_select[5]; 2231 /* TCAM Block entry masking. This value should be set to 0x0 for 2232 * unused TCAM 2233 */ 2234 u8 chnk_msk; 2235 /* Bit 0 : masks TCAM entries 0-63 2236 * Bit 1 : masks TCAM entries 64-127 2237 * Bit 2 to 7 : follow the pattern of bit 0 and 1 2238 */ 2239 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0) 2240 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1) 2241 u8 start_cmp_set; 2242 2243 } tcam_cfg[ICE_AQC_ACL_SLICES]; 2244 2245 /* Each byte, Bit 6..0: Action memory association to a TCAM block, 2246 * otherwise it shall be set to 0x0 for disabled memory action. 2247 * Bit 7 : Action memory enable for this scenario 2248 */ 2249 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F 2250 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7) 2251 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES]; 2252 }; 2253 2254 /* Allocate ACL counters (indirect 0x0C16) */ 2255 struct ice_aqc_acl_alloc_counters { 2256 /* Amount of contiguous counters requested. Min value is 1 and 2257 * max value is 255 2258 */ 2259 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1 2260 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF 2261 u8 counter_amount; 2262 2263 /* Counter type: 'single counter' which can be configured to count 2264 * either bytes or packets 2265 */ 2266 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0 2267 2268 /* Counter type: 'counter pair' which counts number of bytes and number 2269 * of packets. 2270 */ 2271 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1 2272 /* requested counter type, single/dual */ 2273 u8 counters_type; 2274 2275 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */ 2276 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3 2277 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */ 2278 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1 2279 /* requested counter bank allocation */ 2280 u8 bank_alloc; 2281 2282 u8 reserved; 2283 2284 union { 2285 /* Applicable only in case of command */ 2286 struct { 2287 u8 reserved[12]; 2288 } cmd; 2289 /* Applicable only in case of response */ 2290 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF 2291 struct { 2292 /* Index of first allocated counter. 0xFFFF in case 2293 * of unsuccessful allocation 2294 */ 2295 __le16 first_counter; 2296 /* Index of last allocated counter. 0xFFFF in case 2297 * of unsuccessful allocation 2298 */ 2299 __le16 last_counter; 2300 u8 rsvd[8]; 2301 } resp; 2302 } ops; 2303 }; 2304 2305 /* De-allocate ACL counters (direct 0x0C17) */ 2306 struct ice_aqc_acl_dealloc_counters { 2307 /* first counter being released */ 2308 __le16 first_counter; 2309 /* last counter being released */ 2310 __le16 last_counter; 2311 /* requested counter type, single/dual */ 2312 u8 counters_type; 2313 /* requested counter bank allocation */ 2314 u8 bank_alloc; 2315 u8 reserved[10]; 2316 }; 2317 2318 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the 2319 * resources allocated for it using a single command 2320 */ 2321 struct ice_aqc_acl_dealloc_res { 2322 u8 reserved[16]; 2323 }; 2324 2325 /* Program ACL actionpair (indirect 0x0C1C) 2326 * Query ACL actionpair (indirect 0x0C25) 2327 */ 2328 struct ice_aqc_acl_actpair { 2329 /* action mem index to program/update */ 2330 u8 act_mem_index; 2331 u8 reserved; 2332 /* The entry index in action memory to be programmed/updated */ 2333 __le16 act_entry_index; 2334 __le32 reserved2; 2335 __le32 addr_high; 2336 __le32 addr_low; 2337 }; 2338 2339 /* Input buffer format for program/query action-pair admin command */ 2340 struct ice_acl_act_entry { 2341 /* Action priority, values must be between 0..7 */ 2342 #define ICE_AQC_ACT_PRIO_VALID_MAX 7 2343 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0) 2344 u8 prio; 2345 /* Action meta-data identifier. This field should be set to 0x0 2346 * for a NOP action 2347 */ 2348 #define ICE_AQC_ACT_MDID_S 8 2349 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S) 2350 u8 mdid; 2351 /* Action value */ 2352 #define ICE_AQC_ACT_VALUE_S 16 2353 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16) 2354 __le16 value; 2355 }; 2356 2357 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2 2358 struct ice_aqc_actpair { 2359 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR]; 2360 }; 2361 2362 /* Generic format used to describe either input or response buffer 2363 * for admin commands related to ACL profile 2364 */ 2365 struct ice_aqc_acl_prof_generic_frmt { 2366 /* The first byte of the byte selection base is reserved to keep the 2367 * first byte of the field vector where the packet direction info is 2368 * available. Thus we should start at index 1 of the field vector to 2369 * map its entries to the byte selection base. 2370 */ 2371 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1 2372 /* In each byte: 2373 * Bit 0..5 = Byte selection for the byte selection base from the 2374 * extracted fields (expressed as byte offset in extracted fields). 2375 * Applicable values are 0..63 2376 * Bit 6..7 = Reserved 2377 */ 2378 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30 2379 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS]; 2380 /* In each byte: 2381 * Bit 0..4 = Word selection for the word selection base from the 2382 * extracted fields (expressed as word offset in extracted fields). 2383 * Applicable values are 0..31 2384 * Bit 5..7 = Reserved 2385 */ 2386 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32 2387 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS]; 2388 /* In each byte: 2389 * Bit 0..3 = Double word selection for the double-word selection base 2390 * from the extracted fields (expressed as double-word offset in 2391 * extracted fields). 2392 * Applicable values are 0..15 2393 * Bit 4..7 = Reserved 2394 */ 2395 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15 2396 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS]; 2397 /* Scenario numbers for individual Physical Function's */ 2398 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8 2399 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS]; 2400 }; 2401 2402 /* Program ACL profile extraction (indirect 0x0C1D) 2403 * Program ACL profile ranges (indirect 0x0C1E) 2404 * Query ACL profile (indirect 0x0C21) 2405 * Query ACL profile ranges (indirect 0x0C22) 2406 */ 2407 struct ice_aqc_acl_profile { 2408 u8 profile_id; /* Programmed/Updated profile ID */ 2409 u8 reserved[7]; 2410 __le32 addr_high; 2411 __le32 addr_low; 2412 }; 2413 2414 /* Input buffer format for program profile extraction admin command and 2415 * response buffer format for query profile admin command is as defined 2416 * in struct ice_aqc_acl_prof_generic_frmt 2417 */ 2418 2419 /* Input buffer format for program profile ranges and query profile ranges 2420 * admin commands. Same format is used for response buffer in case of query 2421 * profile ranges command 2422 */ 2423 struct ice_acl_rng_data { 2424 /* The range checker output shall be sent when the value 2425 * related to this range checker is lower than low boundary 2426 */ 2427 __be16 low_boundary; 2428 /* The range checker output shall be sent when the value 2429 * related to this range checker is higher than high boundary 2430 */ 2431 __be16 high_boundary; 2432 /* A value of '0' in bit shall clear the relevant bit input 2433 * to the range checker 2434 */ 2435 __be16 mask; 2436 }; 2437 2438 struct ice_aqc_acl_profile_ranges { 2439 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8 2440 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG]; 2441 }; 2442 2443 /* Program ACL entry (indirect 0x0C20) 2444 * Query ACL entry (indirect 0x0C24) 2445 */ 2446 struct ice_aqc_acl_entry { 2447 u8 tcam_index; /* Updated TCAM block index */ 2448 u8 reserved; 2449 __le16 entry_index; /* Updated entry index */ 2450 __le32 reserved2; 2451 __le32 addr_high; 2452 __le32 addr_low; 2453 }; 2454 2455 /* Input buffer format in case of program ACL entry and response buffer format 2456 * in case of query ACL entry 2457 */ 2458 struct ice_aqc_acl_data { 2459 /* Entry key and entry key invert are 40 bits wide. 2460 * Byte 0..4 : entry key and Byte 5..7 are reserved 2461 * Byte 8..12: entry key invert and Byte 13..15 are reserved 2462 */ 2463 struct { 2464 u8 val[5]; 2465 u8 reserved[3]; 2466 } entry_key, entry_key_invert; 2467 }; 2468 2469 /* Query ACL counter (direct 0x0C27) */ 2470 struct ice_aqc_acl_query_counter { 2471 /* Queried counter index */ 2472 __le16 counter_index; 2473 /* Queried counter bank */ 2474 u8 counter_bank; 2475 union { 2476 struct { 2477 u8 reserved[13]; 2478 } cmd; 2479 struct { 2480 /* Holds counter value/packet counter value */ 2481 u8 val[5]; 2482 u8 reserved[8]; 2483 } resp; 2484 } ops; 2485 }; 2486 2487 /* Add Tx LAN Queues (indirect 0x0C30) */ 2488 struct ice_aqc_add_txqs { 2489 u8 num_qgrps; 2490 u8 reserved[3]; 2491 __le32 reserved1; 2492 __le32 addr_high; 2493 __le32 addr_low; 2494 }; 2495 2496 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2497 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2498 */ 2499 struct ice_aqc_add_txqs_perq { 2500 __le16 txq_id; 2501 u8 rsvd[2]; 2502 __le32 q_teid; 2503 u8 txq_ctx[22]; 2504 u8 rsvd2[2]; 2505 struct ice_aqc_txsched_elem info; 2506 }; 2507 2508 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2509 * is an array of the following structs. Please note that the length of 2510 * each struct ice_aqc_add_tx_qgrp is variable due 2511 * to the variable number of queues in each group! 2512 */ 2513 struct ice_aqc_add_tx_qgrp { 2514 __le32 parent_teid; 2515 u8 num_txqs; 2516 u8 rsvd[3]; 2517 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2518 }; 2519 2520 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2521 struct ice_aqc_dis_txqs { 2522 u8 cmd_type; 2523 #define ICE_AQC_Q_DIS_CMD_S 0 2524 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2525 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2526 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2527 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2528 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2529 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2530 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2531 u8 num_entries; 2532 __le16 vmvf_and_timeout; 2533 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2534 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2535 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2536 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2537 __le32 blocked_cgds; 2538 __le32 addr_high; 2539 __le32 addr_low; 2540 }; 2541 2542 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2543 * contains the following structures, arrayed one after the 2544 * other. 2545 * Note: Since the q_id is 16 bits wide, if the 2546 * number of queues is even, then 2 bytes of alignment MUST be 2547 * added before the start of the next group, to allow correct 2548 * alignment of the parent_teid field. 2549 */ 2550 #pragma pack(1) 2551 struct ice_aqc_dis_txq_item { 2552 __le32 parent_teid; 2553 u8 num_qs; 2554 u8 rsvd; 2555 /* The length of the q_id array varies according to num_qs */ 2556 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2557 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2558 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2559 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2560 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2561 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2562 }; 2563 2564 #pragma pack() 2565 2566 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2567 struct ice_aqc_txqs_cleanup { 2568 __le16 caller_opc; 2569 __le16 cmd_tag; 2570 u8 reserved[12]; 2571 }; 2572 2573 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2574 struct ice_aqc_move_txqs { 2575 u8 cmd_type; 2576 #define ICE_AQC_Q_CMD_TYPE_S 0 2577 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2578 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2579 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2580 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2581 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2582 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2583 u8 num_qs; 2584 u8 rsvd; 2585 u8 timeout; 2586 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2587 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2588 __le32 blocked_cgds; 2589 __le32 addr_high; 2590 __le32 addr_low; 2591 }; 2592 2593 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2594 struct ice_aqc_move_txqs_elem { 2595 __le16 txq_id; 2596 u8 q_cgd; 2597 u8 rsvd; 2598 __le32 q_teid; 2599 }; 2600 2601 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2602 struct ice_aqc_move_txqs_data { 2603 __le32 src_teid; 2604 __le32 dest_teid; 2605 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2606 }; 2607 2608 /* Download Package (indirect 0x0C40) */ 2609 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2610 struct ice_aqc_download_pkg { 2611 u8 flags; 2612 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2613 u8 reserved[3]; 2614 __le32 reserved1; 2615 __le32 addr_high; 2616 __le32 addr_low; 2617 }; 2618 2619 struct ice_aqc_download_pkg_resp { 2620 __le32 error_offset; 2621 __le32 error_info; 2622 __le32 addr_high; 2623 __le32 addr_low; 2624 }; 2625 2626 /* Get Package Info List (indirect 0x0C43) */ 2627 struct ice_aqc_get_pkg_info_list { 2628 __le32 reserved1; 2629 __le32 reserved2; 2630 __le32 addr_high; 2631 __le32 addr_low; 2632 }; 2633 2634 /* Version format for packages */ 2635 struct ice_pkg_ver { 2636 u8 major; 2637 u8 minor; 2638 u8 update; 2639 u8 draft; 2640 }; 2641 2642 #define ICE_PKG_NAME_SIZE 32 2643 #define ICE_SEG_ID_SIZE 28 2644 #define ICE_SEG_NAME_SIZE 28 2645 2646 struct ice_aqc_get_pkg_info { 2647 struct ice_pkg_ver ver; 2648 char name[ICE_SEG_NAME_SIZE]; 2649 __le32 track_id; 2650 u8 is_in_nvm; 2651 u8 is_active; 2652 u8 is_active_at_boot; 2653 u8 is_modified; 2654 }; 2655 2656 /* Get Package Info List response buffer format (0x0C43) */ 2657 struct ice_aqc_get_pkg_info_resp { 2658 __le32 count; 2659 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2660 }; 2661 2662 /* Driver Shared Parameters (direct, 0x0C90) */ 2663 struct ice_aqc_driver_shared_params { 2664 u8 set_or_get_op; 2665 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2666 #define ICE_AQC_DRIVER_PARAM_SET 0 2667 #define ICE_AQC_DRIVER_PARAM_GET 1 2668 u8 param_indx; 2669 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2670 u8 rsvd[2]; 2671 __le32 param_val; 2672 __le32 addr_high; 2673 __le32 addr_low; 2674 }; 2675 2676 /* Lan Queue Overflow Event (direct, 0x1001) */ 2677 struct ice_aqc_event_lan_overflow { 2678 __le32 prtdcb_ruptq; 2679 __le32 qtx_ctl; 2680 u8 reserved[8]; 2681 }; 2682 2683 /* Set Health Status (direct 0xFF20) */ 2684 struct ice_aqc_set_health_status_config { 2685 u8 event_source; 2686 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2687 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2688 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2689 u8 reserved[15]; 2690 }; 2691 2692 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2693 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2694 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2695 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2696 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2697 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2698 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2699 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2700 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2701 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2702 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2703 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2704 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2705 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2706 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2707 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2708 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2709 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2710 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2711 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2712 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2713 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2714 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2715 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2716 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2717 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2718 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2719 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2720 2721 /* Get Health Status codes (indirect 0xFF21) */ 2722 struct ice_aqc_get_supported_health_status_codes { 2723 __le16 health_code_count; 2724 u8 reserved[6]; 2725 __le32 addr_high; 2726 __le32 addr_low; 2727 }; 2728 2729 /* Get Health Status (indirect 0xFF22) */ 2730 struct ice_aqc_get_health_status { 2731 __le16 health_status_count; 2732 u8 reserved[6]; 2733 __le32 addr_high; 2734 __le32 addr_low; 2735 }; 2736 2737 /* Get Health Status event buffer entry, (0xFF22) 2738 * repeated per reported health status 2739 */ 2740 struct ice_aqc_health_status_elem { 2741 __le16 health_status_code; 2742 __le16 event_source; 2743 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2744 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2745 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2746 __le32 internal_data1; 2747 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2748 __le32 internal_data2; 2749 }; 2750 2751 /* Clear Health Status (direct 0xFF23) */ 2752 struct ice_aqc_clear_health_status { 2753 __le32 reserved[4]; 2754 }; 2755 2756 /* Set FW Logging configuration (indirect 0xFF30) 2757 * Register for FW Logging (indirect 0xFF31) 2758 * Query FW Logging (indirect 0xFF32) 2759 * FW Log Event (indirect 0xFF33) 2760 * Get FW Log (indirect 0xFF34) 2761 * Clear FW Log (indirect 0xFF35) 2762 */ 2763 2764 struct ice_aqc_fw_log { 2765 u8 cmd_flags; 2766 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2767 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2768 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2769 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2770 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2771 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0) 2772 u8 rsp_flag; 2773 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1) 2774 __le16 fw_rt_msb; 2775 union { 2776 struct { 2777 __le32 fw_rt_lsb; 2778 } sync; 2779 struct { 2780 __le16 log_resolution; 2781 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2782 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2783 __le16 mdl_cnt; 2784 } cfg; 2785 } ops; 2786 __le32 addr_high; 2787 __le32 addr_low; 2788 }; 2789 2790 /* Response Buffer for: 2791 * Set Firmware Logging Configuration (0xFF30) 2792 * Query FW Logging (0xFF32) 2793 */ 2794 struct ice_aqc_fw_log_cfg_resp { 2795 __le16 module_identifier; 2796 u8 log_level; 2797 u8 rsvd0; 2798 }; 2799 2800 /** 2801 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2802 * @flags: ICE_AQ_FLAG_* flags 2803 * @opcode: AQ command opcode 2804 * @datalen: length in bytes of indirect/external data buffer 2805 * @retval: return value from firmware 2806 * @cookie_high: opaque data high-half 2807 * @cookie_low: opaque data low-half 2808 * @params: command-specific parameters 2809 * 2810 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2811 * (ATQ). The firmware writes back onto the command descriptor and returns 2812 * the result of the command. Asynchronous events that are not an immediate 2813 * result of the command are written to the Admin Receive Queue (ARQ) using 2814 * the same descriptor format. Descriptors are in little-endian notation with 2815 * 32-bit words. 2816 */ 2817 struct ice_aq_desc { 2818 __le16 flags; 2819 __le16 opcode; 2820 __le16 datalen; 2821 __le16 retval; 2822 __le32 cookie_high; 2823 __le32 cookie_low; 2824 union { 2825 u8 raw[16]; 2826 struct ice_aqc_generic generic; 2827 struct ice_aqc_get_ver get_ver; 2828 struct ice_aqc_driver_ver driver_ver; 2829 struct ice_aqc_q_shutdown q_shutdown; 2830 struct ice_aqc_req_res res_owner; 2831 struct ice_aqc_manage_mac_read mac_read; 2832 struct ice_aqc_manage_mac_write mac_write; 2833 struct ice_aqc_clear_pxe clear_pxe; 2834 struct ice_aqc_config_no_drop_policy no_drop; 2835 struct ice_aqc_add_update_mir_rule add_update_rule; 2836 struct ice_aqc_delete_mir_rule del_rule; 2837 struct ice_aqc_list_caps get_cap; 2838 struct ice_aqc_get_phy_caps get_phy; 2839 struct ice_aqc_set_phy_cfg set_phy; 2840 struct ice_aqc_restart_an restart_an; 2841 struct ice_aqc_sff_eeprom read_write_sff_param; 2842 struct ice_aqc_set_port_id_led set_port_id_led; 2843 struct ice_aqc_get_sw_cfg get_sw_conf; 2844 struct ice_aqc_set_port_params set_port_params; 2845 struct ice_aqc_sw_rules sw_rules; 2846 struct ice_aqc_storm_cfg storm_conf; 2847 struct ice_aqc_add_get_recipe add_get_recipe; 2848 struct ice_aqc_recipe_to_profile recipe_to_profile; 2849 struct ice_aqc_get_topo get_topo; 2850 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2851 struct ice_aqc_query_txsched_res query_sched_res; 2852 struct ice_aqc_query_node_to_root query_node_to_root; 2853 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2854 struct ice_aqc_query_port_ets port_ets; 2855 struct ice_aqc_rl_profile rl_profile; 2856 struct ice_aqc_nvm nvm; 2857 struct ice_aqc_nvm_cfg nvm_cfg; 2858 struct ice_aqc_nvm_checksum nvm_checksum; 2859 struct ice_aqc_pfc_ignore pfc_ignore; 2860 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2861 struct ice_aqc_set_dcb_params set_dcb_params; 2862 struct ice_aqc_lldp_get_mib lldp_get_mib; 2863 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2864 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2865 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2866 struct ice_aqc_lldp_stop lldp_stop; 2867 struct ice_aqc_lldp_start lldp_start; 2868 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2869 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2870 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2871 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2872 struct ice_aqc_get_set_rss_key get_set_rss_key; 2873 struct ice_aqc_clear_fd_table clear_fd_table; 2874 struct ice_aqc_acl_alloc_table alloc_table; 2875 struct ice_aqc_acl_tbl_actpair tbl_actpair; 2876 struct ice_aqc_acl_alloc_scen alloc_scen; 2877 struct ice_aqc_acl_dealloc_scen dealloc_scen; 2878 struct ice_aqc_acl_update_query_scen update_query_scen; 2879 struct ice_aqc_acl_alloc_counters alloc_counters; 2880 struct ice_aqc_acl_dealloc_counters dealloc_counters; 2881 struct ice_aqc_acl_dealloc_res dealloc_res; 2882 struct ice_aqc_acl_entry program_query_entry; 2883 struct ice_aqc_acl_actpair program_query_actpair; 2884 struct ice_aqc_acl_profile profile; 2885 struct ice_aqc_acl_query_counter query_counter; 2886 struct ice_aqc_add_txqs add_txqs; 2887 struct ice_aqc_dis_txqs dis_txqs; 2888 struct ice_aqc_move_txqs move_txqs; 2889 struct ice_aqc_txqs_cleanup txqs_cleanup; 2890 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2891 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2892 struct ice_aqc_get_vsi_resp get_vsi_resp; 2893 struct ice_aqc_download_pkg download_pkg; 2894 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2895 struct ice_aqc_driver_shared_params drv_shared_params; 2896 struct ice_aqc_set_mac_lb set_mac_lb; 2897 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2898 struct ice_aqc_get_res_alloc get_res; 2899 struct ice_aqc_get_allocd_res_desc get_res_desc; 2900 struct ice_aqc_set_mac_cfg set_mac_cfg; 2901 struct ice_aqc_set_event_mask set_event_mask; 2902 struct ice_aqc_get_link_status get_link_status; 2903 struct ice_aqc_event_lan_overflow lan_overflow; 2904 struct ice_aqc_get_link_topo get_link_topo; 2905 struct ice_aqc_set_health_status_config 2906 set_health_status_config; 2907 struct ice_aqc_get_supported_health_status_codes 2908 get_supported_health_status_codes; 2909 struct ice_aqc_get_health_status get_health_status; 2910 struct ice_aqc_clear_health_status clear_health_status; 2911 } params; 2912 }; 2913 2914 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2915 #define ICE_AQ_LG_BUF 512 2916 2917 /* Flags sub-structure 2918 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2919 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2920 */ 2921 2922 /* command flags and offsets */ 2923 #define ICE_AQ_FLAG_DD_S 0 2924 #define ICE_AQ_FLAG_CMP_S 1 2925 #define ICE_AQ_FLAG_ERR_S 2 2926 #define ICE_AQ_FLAG_VFE_S 3 2927 #define ICE_AQ_FLAG_LB_S 9 2928 #define ICE_AQ_FLAG_RD_S 10 2929 #define ICE_AQ_FLAG_VFC_S 11 2930 #define ICE_AQ_FLAG_BUF_S 12 2931 #define ICE_AQ_FLAG_SI_S 13 2932 #define ICE_AQ_FLAG_EI_S 14 2933 #define ICE_AQ_FLAG_FE_S 15 2934 2935 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2936 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2937 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2938 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2939 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2940 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2941 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2942 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2943 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2944 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2945 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2946 2947 /* error codes */ 2948 enum ice_aq_err { 2949 ICE_AQ_RC_OK = 0, /* Success */ 2950 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2951 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2952 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2953 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2954 ICE_AQ_RC_EIO = 5, /* I/O error */ 2955 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2956 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2957 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2958 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2959 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2960 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2961 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2962 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2963 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2964 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2965 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2966 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2967 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2968 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2969 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2970 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2971 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2972 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2973 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2974 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2975 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2976 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2977 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2978 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2979 }; 2980 2981 /* Admin Queue command opcodes */ 2982 enum ice_adminq_opc { 2983 /* AQ commands */ 2984 ice_aqc_opc_get_ver = 0x0001, 2985 ice_aqc_opc_driver_ver = 0x0002, 2986 ice_aqc_opc_q_shutdown = 0x0003, 2987 ice_aqc_opc_get_exp_err = 0x0005, 2988 2989 /* resource ownership */ 2990 ice_aqc_opc_req_res = 0x0008, 2991 ice_aqc_opc_release_res = 0x0009, 2992 2993 /* device/function capabilities */ 2994 ice_aqc_opc_list_func_caps = 0x000A, 2995 ice_aqc_opc_list_dev_caps = 0x000B, 2996 2997 /* manage MAC address */ 2998 ice_aqc_opc_manage_mac_read = 0x0107, 2999 ice_aqc_opc_manage_mac_write = 0x0108, 3000 3001 /* PXE */ 3002 ice_aqc_opc_clear_pxe_mode = 0x0110, 3003 3004 ice_aqc_opc_config_no_drop_policy = 0x0112, 3005 3006 /* internal switch commands */ 3007 ice_aqc_opc_get_sw_cfg = 0x0200, 3008 ice_aqc_opc_set_port_params = 0x0203, 3009 3010 /* Alloc/Free/Get Resources */ 3011 ice_aqc_opc_get_res_alloc = 0x0204, 3012 ice_aqc_opc_alloc_res = 0x0208, 3013 ice_aqc_opc_free_res = 0x0209, 3014 ice_aqc_opc_get_allocd_res_desc = 0x020A, 3015 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 3016 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 3017 3018 /* VSI commands */ 3019 ice_aqc_opc_add_vsi = 0x0210, 3020 ice_aqc_opc_update_vsi = 0x0211, 3021 ice_aqc_opc_get_vsi_params = 0x0212, 3022 ice_aqc_opc_free_vsi = 0x0213, 3023 3024 /* Mirroring rules - add/update, delete */ 3025 ice_aqc_opc_add_update_mir_rule = 0x0260, 3026 ice_aqc_opc_del_mir_rule = 0x0261, 3027 3028 /* storm configuration */ 3029 ice_aqc_opc_set_storm_cfg = 0x0280, 3030 ice_aqc_opc_get_storm_cfg = 0x0281, 3031 3032 /* recipe commands */ 3033 ice_aqc_opc_add_recipe = 0x0290, 3034 ice_aqc_opc_recipe_to_profile = 0x0291, 3035 ice_aqc_opc_get_recipe = 0x0292, 3036 ice_aqc_opc_get_recipe_to_profile = 0x0293, 3037 3038 /* switch rules population commands */ 3039 ice_aqc_opc_add_sw_rules = 0x02A0, 3040 ice_aqc_opc_update_sw_rules = 0x02A1, 3041 ice_aqc_opc_remove_sw_rules = 0x02A2, 3042 ice_aqc_opc_get_sw_rules = 0x02A3, 3043 ice_aqc_opc_clear_pf_cfg = 0x02A4, 3044 3045 /* DCB commands */ 3046 ice_aqc_opc_pfc_ignore = 0x0301, 3047 ice_aqc_opc_query_pfc_mode = 0x0302, 3048 ice_aqc_opc_set_pfc_mode = 0x0303, 3049 ice_aqc_opc_set_dcb_params = 0x0306, 3050 3051 /* transmit scheduler commands */ 3052 ice_aqc_opc_get_dflt_topo = 0x0400, 3053 ice_aqc_opc_add_sched_elems = 0x0401, 3054 ice_aqc_opc_cfg_sched_elems = 0x0403, 3055 ice_aqc_opc_get_sched_elems = 0x0404, 3056 ice_aqc_opc_move_sched_elems = 0x0408, 3057 ice_aqc_opc_suspend_sched_elems = 0x0409, 3058 ice_aqc_opc_resume_sched_elems = 0x040A, 3059 ice_aqc_opc_query_port_ets = 0x040E, 3060 ice_aqc_opc_delete_sched_elems = 0x040F, 3061 ice_aqc_opc_add_rl_profiles = 0x0410, 3062 ice_aqc_opc_query_rl_profiles = 0x0411, 3063 ice_aqc_opc_query_sched_res = 0x0412, 3064 ice_aqc_opc_query_node_to_root = 0x0413, 3065 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 3066 ice_aqc_opc_remove_rl_profiles = 0x0415, 3067 3068 /* PHY commands */ 3069 ice_aqc_opc_get_phy_caps = 0x0600, 3070 ice_aqc_opc_set_phy_cfg = 0x0601, 3071 ice_aqc_opc_set_mac_cfg = 0x0603, 3072 ice_aqc_opc_restart_an = 0x0605, 3073 ice_aqc_opc_get_link_status = 0x0607, 3074 ice_aqc_opc_set_event_mask = 0x0613, 3075 ice_aqc_opc_set_mac_lb = 0x0620, 3076 ice_aqc_opc_get_link_topo = 0x06E0, 3077 ice_aqc_opc_set_port_id_led = 0x06E9, 3078 ice_aqc_opc_get_port_options = 0x06EA, 3079 ice_aqc_opc_set_port_option = 0x06EB, 3080 ice_aqc_opc_set_gpio = 0x06EC, 3081 ice_aqc_opc_get_gpio = 0x06ED, 3082 ice_aqc_opc_sff_eeprom = 0x06EE, 3083 ice_aqc_opc_sw_set_gpio = 0x06EF, 3084 ice_aqc_opc_sw_get_gpio = 0x06F0, 3085 ice_aqc_opc_program_topology_device_nvm = 0x06F2, 3086 ice_aqc_opc_read_topology_device_nvm = 0x06F3, 3087 3088 /* NVM commands */ 3089 ice_aqc_opc_nvm_read = 0x0701, 3090 ice_aqc_opc_nvm_erase = 0x0702, 3091 ice_aqc_opc_nvm_write = 0x0703, 3092 ice_aqc_opc_nvm_cfg_read = 0x0704, 3093 ice_aqc_opc_nvm_cfg_write = 0x0705, 3094 ice_aqc_opc_nvm_checksum = 0x0706, 3095 ice_aqc_opc_nvm_write_activate = 0x0707, 3096 ice_aqc_opc_nvm_sr_dump = 0x0707, 3097 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 3098 ice_aqc_opc_nvm_update_empr = 0x0709, 3099 3100 /* LLDP commands */ 3101 ice_aqc_opc_lldp_get_mib = 0x0A00, 3102 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 3103 ice_aqc_opc_lldp_add_tlv = 0x0A02, 3104 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3105 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3106 ice_aqc_opc_lldp_stop = 0x0A05, 3107 ice_aqc_opc_lldp_start = 0x0A06, 3108 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3109 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3110 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3111 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3112 3113 /* RSS commands */ 3114 ice_aqc_opc_set_rss_key = 0x0B02, 3115 ice_aqc_opc_set_rss_lut = 0x0B03, 3116 ice_aqc_opc_get_rss_key = 0x0B04, 3117 ice_aqc_opc_get_rss_lut = 0x0B05, 3118 ice_aqc_opc_clear_fd_table = 0x0B06, 3119 /* ACL commands */ 3120 ice_aqc_opc_alloc_acl_tbl = 0x0C10, 3121 ice_aqc_opc_dealloc_acl_tbl = 0x0C11, 3122 ice_aqc_opc_alloc_acl_actpair = 0x0C12, 3123 ice_aqc_opc_dealloc_acl_actpair = 0x0C13, 3124 ice_aqc_opc_alloc_acl_scen = 0x0C14, 3125 ice_aqc_opc_dealloc_acl_scen = 0x0C15, 3126 ice_aqc_opc_alloc_acl_counters = 0x0C16, 3127 ice_aqc_opc_dealloc_acl_counters = 0x0C17, 3128 ice_aqc_opc_dealloc_acl_res = 0x0C1A, 3129 ice_aqc_opc_update_acl_scen = 0x0C1B, 3130 ice_aqc_opc_program_acl_actpair = 0x0C1C, 3131 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D, 3132 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E, 3133 ice_aqc_opc_program_acl_entry = 0x0C20, 3134 ice_aqc_opc_query_acl_prof = 0x0C21, 3135 ice_aqc_opc_query_acl_prof_ranges = 0x0C22, 3136 ice_aqc_opc_query_acl_scen = 0x0C23, 3137 ice_aqc_opc_query_acl_entry = 0x0C24, 3138 ice_aqc_opc_query_acl_actpair = 0x0C25, 3139 ice_aqc_opc_query_acl_counter = 0x0C27, 3140 3141 /* Tx queue handling commands/events */ 3142 ice_aqc_opc_add_txqs = 0x0C30, 3143 ice_aqc_opc_dis_txqs = 0x0C31, 3144 ice_aqc_opc_txqs_cleanup = 0x0C31, 3145 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3146 3147 /* package commands */ 3148 ice_aqc_opc_download_pkg = 0x0C40, 3149 ice_aqc_opc_upload_section = 0x0C41, 3150 ice_aqc_opc_update_pkg = 0x0C42, 3151 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3152 3153 ice_aqc_opc_driver_shared_params = 0x0C90, 3154 3155 /* Standalone Commands/Events */ 3156 ice_aqc_opc_event_lan_overflow = 0x1001, 3157 3158 /* SystemDiagnostic commands */ 3159 ice_aqc_opc_set_health_status_config = 0xFF20, 3160 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3161 ice_aqc_opc_get_health_status = 0xFF22, 3162 ice_aqc_opc_clear_health_status = 0xFF23, 3163 3164 /* FW Logging Commands */ 3165 ice_aqc_opc_fw_logs_config = 0xFF30, 3166 ice_aqc_opc_fw_logs_register = 0xFF31, 3167 ice_aqc_opc_fw_logs_query = 0xFF32, 3168 ice_aqc_opc_fw_logs_event = 0xFF33, 3169 ice_aqc_opc_fw_logs_get = 0xFF34, 3170 ice_aqc_opc_fw_logs_clear = 0xFF35 3171 }; 3172 3173 #endif /* _ICE_ADMINQ_CMD_H_ */ 3174