1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #ifndef _ICE_ADMINQ_CMD_H_ 6 #define _ICE_ADMINQ_CMD_H_ 7 8 /* This header file defines the Admin Queue commands, error codes and 9 * descriptor format. It is shared between Firmware and Software. 10 */ 11 12 #define ICE_MAX_VSI 768 13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 15 16 struct ice_aqc_generic { 17 __le32 param0; 18 __le32 param1; 19 __le32 addr_high; 20 __le32 addr_low; 21 }; 22 23 /* Get version (direct 0x0001) */ 24 struct ice_aqc_get_ver { 25 __le32 rom_ver; 26 __le32 fw_build; 27 u8 fw_branch; 28 u8 fw_major; 29 u8 fw_minor; 30 u8 fw_patch; 31 u8 api_branch; 32 u8 api_major; 33 u8 api_minor; 34 u8 api_patch; 35 }; 36 37 /* Send driver version (indirect 0x0002) */ 38 struct ice_aqc_driver_ver { 39 u8 major_ver; 40 u8 minor_ver; 41 u8 build_ver; 42 u8 subbuild_ver; 43 u8 reserved[4]; 44 __le32 addr_high; 45 __le32 addr_low; 46 }; 47 48 /* Queue Shutdown (direct 0x0003) */ 49 struct ice_aqc_q_shutdown { 50 u8 driver_unloading; 51 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 52 u8 reserved[15]; 53 }; 54 55 /* Request resource ownership (direct 0x0008) 56 * Release resource ownership (direct 0x0009) 57 */ 58 struct ice_aqc_req_res { 59 __le16 res_id; 60 #define ICE_AQC_RES_ID_NVM 1 61 #define ICE_AQC_RES_ID_SDP 2 62 #define ICE_AQC_RES_ID_CHNG_LOCK 3 63 #define ICE_AQC_RES_ID_GLBL_LOCK 4 64 __le16 access_type; 65 #define ICE_AQC_RES_ACCESS_READ 1 66 #define ICE_AQC_RES_ACCESS_WRITE 2 67 68 /* Upon successful completion, FW writes this value and driver is 69 * expected to release resource before timeout. This value is provided 70 * in milliseconds. 71 */ 72 __le32 timeout; 73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 77 /* For SDP: pin ID of the SDP */ 78 __le32 res_number; 79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 80 __le16 status; 81 #define ICE_AQ_RES_GLBL_SUCCESS 0 82 #define ICE_AQ_RES_GLBL_IN_PROG 1 83 #define ICE_AQ_RES_GLBL_DONE 2 84 u8 reserved[2]; 85 }; 86 87 /* Get function capabilities (indirect 0x000A) 88 * Get device capabilities (indirect 0x000B) 89 */ 90 struct ice_aqc_list_caps { 91 u8 cmd_flags; 92 u8 pf_index; 93 u8 reserved[2]; 94 __le32 count; 95 __le32 addr_high; 96 __le32 addr_low; 97 }; 98 99 /* Device/Function buffer entry, repeated per reported capability */ 100 struct ice_aqc_list_caps_elem { 101 __le16 cap; 102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 #define ICE_AQC_CAPS_IWARP 0x0051 113 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 114 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 115 116 u8 major_ver; 117 u8 minor_ver; 118 /* Number of resources described by this capability */ 119 __le32 number; 120 /* Only meaningful for some types of resources */ 121 __le32 logical_id; 122 /* Only meaningful for some types of resources */ 123 __le32 phys_id; 124 __le64 rsvd1; 125 __le64 rsvd2; 126 }; 127 128 /* Manage MAC address, read command - indirect (0x0107) 129 * This struct is also used for the response 130 */ 131 struct ice_aqc_manage_mac_read { 132 __le16 flags; /* Zeroed by device driver */ 133 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 134 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 135 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 136 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 137 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 138 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 139 #define ICE_AQC_MAN_MAC_READ_S 4 140 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 141 u8 rsvd[2]; 142 u8 num_addr; /* Used in response */ 143 u8 rsvd1[3]; 144 __le32 addr_high; 145 __le32 addr_low; 146 }; 147 148 /* Response buffer format for manage MAC read command */ 149 struct ice_aqc_manage_mac_read_resp { 150 u8 lport_num; 151 u8 addr_type; 152 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 153 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 154 u8 mac_addr[ETH_ALEN]; 155 }; 156 157 /* Manage MAC address, write command - direct (0x0108) */ 158 struct ice_aqc_manage_mac_write { 159 u8 rsvd; 160 u8 flags; 161 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 162 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 163 #define ICE_AQC_MAN_MAC_WR_S 6 164 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 165 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 166 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 167 /* byte stream in network order */ 168 u8 mac_addr[ETH_ALEN]; 169 __le32 addr_high; 170 __le32 addr_low; 171 }; 172 173 /* Clear PXE Command and response (direct 0x0110) */ 174 struct ice_aqc_clear_pxe { 175 u8 rx_cnt; 176 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 177 u8 reserved[15]; 178 }; 179 180 /* Configure No-Drop Policy Command (direct 0x0112) */ 181 struct ice_aqc_config_no_drop_policy { 182 u8 opts; 183 #define ICE_AQC_FORCE_NO_DROP BIT(0) 184 u8 rsvd[15]; 185 }; 186 187 /* Get switch configuration (0x0200) */ 188 struct ice_aqc_get_sw_cfg { 189 /* Reserved for command and copy of request flags for response */ 190 __le16 flags; 191 /* First desc in case of command and next_elem in case of response 192 * In case of response, if it is not zero, means all the configuration 193 * was not returned and new command shall be sent with this value in 194 * the 'first desc' field 195 */ 196 __le16 element; 197 /* Reserved for command, only used for response */ 198 __le16 num_elems; 199 __le16 rsvd; 200 __le32 addr_high; 201 __le32 addr_low; 202 }; 203 204 /* Each entry in the response buffer is of the following type: */ 205 struct ice_aqc_get_sw_cfg_resp_elem { 206 /* VSI/Port Number */ 207 __le16 vsi_port_num; 208 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 209 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 210 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 211 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 212 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 213 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 214 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 215 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 216 217 /* SWID VSI/Port belongs to */ 218 __le16 swid; 219 220 /* Bit 14..0 : PF/VF number VSI belongs to 221 * Bit 15 : VF indication bit 222 */ 223 __le16 pf_vf_num; 224 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 225 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 226 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 227 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 228 }; 229 230 /* Set Port parameters, (direct, 0x0203) */ 231 struct ice_aqc_set_port_params { 232 __le16 cmd_flags; 233 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 234 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 235 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 236 __le16 bad_frame_vsi; 237 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 238 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 239 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 240 __le16 swid; 241 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 242 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 243 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 244 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 245 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 246 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 247 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 248 u8 reserved[10]; 249 }; 250 251 /* These resource type defines are used for all switch resource 252 * commands where a resource type is required, such as: 253 * Get Resource Allocation command (indirect 0x0204) 254 * Allocate Resources command (indirect 0x0208) 255 * Free Resources command (indirect 0x0209) 256 * Get Allocated Resource Descriptors Command (indirect 0x020A) 257 */ 258 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 259 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 260 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 261 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 262 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 263 #define ICE_AQC_RES_TYPE_RECIPE 0x05 264 #define ICE_AQC_RES_TYPE_PROFILE 0x06 265 #define ICE_AQC_RES_TYPE_SWID 0x07 266 #define ICE_AQC_RES_TYPE_VSI 0x08 267 #define ICE_AQC_RES_TYPE_FLU 0x09 268 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 269 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 270 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 271 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 272 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 273 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 274 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 275 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 276 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 277 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 278 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 279 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 280 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 281 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 282 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 283 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 284 /* Resource types 0x62-67 are reserved for Hash profile builder */ 285 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 286 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 287 288 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 289 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 290 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 291 292 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 293 294 #define ICE_AQC_RES_TYPE_S 0 295 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 296 297 /* Get Resource Allocation command (indirect 0x0204) */ 298 struct ice_aqc_get_res_alloc { 299 __le16 resp_elem_num; /* Used in response, reserved in command */ 300 u8 reserved[6]; 301 __le32 addr_high; 302 __le32 addr_low; 303 }; 304 305 /* Get Resource Allocation Response Buffer per response */ 306 struct ice_aqc_get_res_resp_elem { 307 __le16 res_type; /* Types defined above cmd 0x0204 */ 308 __le16 total_capacity; /* Resources available to all PF's */ 309 __le16 total_function; /* Resources allocated for a PF */ 310 __le16 total_shared; /* Resources allocated as shared */ 311 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 312 }; 313 314 /* Allocate Resources command (indirect 0x0208) 315 * Free Resources command (indirect 0x0209) 316 */ 317 struct ice_aqc_alloc_free_res_cmd { 318 __le16 num_entries; /* Number of Resource entries */ 319 u8 reserved[6]; 320 __le32 addr_high; 321 __le32 addr_low; 322 }; 323 324 /* Resource descriptor */ 325 struct ice_aqc_res_elem { 326 union { 327 __le16 sw_resp; 328 __le16 flu_resp; 329 } e; 330 }; 331 332 /* Buffer for Allocate/Free Resources commands */ 333 struct ice_aqc_alloc_free_res_elem { 334 __le16 res_type; /* Types defined above cmd 0x0204 */ 335 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 336 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 337 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 338 __le16 num_elems; 339 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 340 }; 341 342 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 343 struct ice_aqc_get_allocd_res_desc { 344 union { 345 struct { 346 __le16 res; /* Types defined above cmd 0x0204 */ 347 __le16 first_desc; 348 __le32 reserved; 349 } cmd; 350 struct { 351 __le16 res; 352 __le16 next_desc; 353 __le16 num_desc; 354 __le16 reserved; 355 } resp; 356 } ops; 357 __le32 addr_high; 358 __le32 addr_low; 359 }; 360 361 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 362 struct ice_aqc_set_vlan_mode { 363 u8 reserved; 364 u8 l2tag_prio_tagging; 365 #define ICE_AQ_VLAN_PRIO_TAG_S 0 366 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 367 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 368 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 369 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 370 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 371 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 372 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 373 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 374 u8 l2tag_reserved[64]; 375 u8 rdma_packet; 376 #define ICE_AQ_VLAN_RDMA_TAG_S 0 377 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 378 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 379 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 380 u8 rdma_reserved[2]; 381 u8 mng_vlan_prot_id; 382 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 383 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 384 u8 prot_id_reserved[30]; 385 }; 386 387 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 388 struct ice_aqc_get_vlan_mode { 389 u8 vlan_mode; 390 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 391 u8 l2tag_prio_tagging; 392 u8 reserved[98]; 393 }; 394 395 /* Add VSI (indirect 0x0210) 396 * Update VSI (indirect 0x0211) 397 * Get VSI (indirect 0x0212) 398 * Free VSI (indirect 0x0213) 399 */ 400 struct ice_aqc_add_get_update_free_vsi { 401 __le16 vsi_num; 402 #define ICE_AQ_VSI_NUM_S 0 403 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 404 #define ICE_AQ_VSI_IS_VALID BIT(15) 405 __le16 cmd_flags; 406 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 407 u8 vf_id; 408 u8 reserved; 409 __le16 vsi_flags; 410 #define ICE_AQ_VSI_TYPE_S 0 411 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 412 #define ICE_AQ_VSI_TYPE_VF 0x0 413 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 414 #define ICE_AQ_VSI_TYPE_PF 0x2 415 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 416 __le32 addr_high; 417 __le32 addr_low; 418 }; 419 420 /* Response descriptor for: 421 * Add VSI (indirect 0x0210) 422 * Update VSI (indirect 0x0211) 423 * Free VSI (indirect 0x0213) 424 */ 425 struct ice_aqc_add_update_free_vsi_resp { 426 __le16 vsi_num; 427 __le16 ext_status; 428 __le16 vsi_used; 429 __le16 vsi_free; 430 __le32 addr_high; 431 __le32 addr_low; 432 }; 433 434 struct ice_aqc_get_vsi_resp { 435 __le16 vsi_num; 436 u8 vf_id; 437 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 438 * These are found above in struct ice_aqc_add_get_update_free_vsi. 439 */ 440 u8 vsi_flags; 441 __le16 vsi_used; 442 __le16 vsi_free; 443 __le32 addr_high; 444 __le32 addr_low; 445 }; 446 447 struct ice_aqc_vsi_props { 448 __le16 valid_sections; 449 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 450 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 451 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 452 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 453 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 454 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 455 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 456 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 457 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 458 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10) 459 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 460 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 461 /* switch section */ 462 u8 sw_id; 463 u8 sw_flags; 464 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 465 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 466 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 467 u8 sw_flags2; 468 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 469 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 470 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 471 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 472 u8 veb_stat_id; 473 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 474 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 475 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 476 /* security section */ 477 u8 sec_flags; 478 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 479 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 480 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 481 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 482 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 483 u8 sec_reserved; 484 /* VLAN section */ 485 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 486 u8 inner_vlan_reserved[2]; 487 u8 inner_vlan_flags; 488 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 489 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 490 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 491 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 492 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 493 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 494 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 495 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 496 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 497 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 498 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 499 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 500 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 501 u8 inner_vlan_reserved2[3]; 502 /* ingress egress up sections */ 503 __le32 ingress_table; /* bitmap, 3 bits per up */ 504 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 505 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 506 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 507 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 508 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 509 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 510 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 511 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 512 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 513 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 514 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 515 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 516 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 517 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 518 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 519 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 520 __le32 egress_table; /* same defines as for ingress table */ 521 /* outer tags section */ 522 __le16 port_based_outer_vlan; 523 u8 outer_vlan_flags; 524 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 525 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 526 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 527 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 528 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 529 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 530 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 531 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 532 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 533 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 534 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 535 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 536 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 537 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(6) 538 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 539 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 540 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 541 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 542 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 543 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 544 u8 outer_vlan_reserved; 545 /* queue mapping section */ 546 __le16 mapping_flags; 547 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 548 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 549 __le16 q_mapping[16]; 550 #define ICE_AQ_VSI_Q_S 0 551 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 552 __le16 tc_mapping[8]; 553 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 554 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 555 #define ICE_AQ_VSI_TC_Q_NUM_S 11 556 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 557 /* queueing option section */ 558 u8 q_opt_rss; 559 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 560 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 561 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 562 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 563 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 564 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 565 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 566 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 567 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 568 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 569 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 570 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 571 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 572 u8 q_opt_tc; 573 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 574 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 575 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 576 u8 q_opt_flags; 577 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 578 u8 q_opt_reserved[3]; 579 /* outer up section */ 580 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 581 /* ACL section */ 582 __le16 acl_def_act; 583 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0 584 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S) 585 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4 586 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S) 587 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8 588 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S) 589 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12 590 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S) 591 /* flow director section */ 592 __le16 fd_options; 593 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 594 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 595 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 596 __le16 max_fd_fltr_dedicated; 597 __le16 max_fd_fltr_shared; 598 __le16 fd_def_q; 599 #define ICE_AQ_VSI_FD_DEF_Q_S 0 600 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 601 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 602 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 603 __le16 fd_report_opt; 604 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 605 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 606 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 607 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 608 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 609 /* PASID section */ 610 __le32 pasid_id; 611 #define ICE_AQ_VSI_PASID_ID_S 0 612 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 613 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 614 u8 reserved[24]; 615 }; 616 617 /* Add/update mirror rule - direct (0x0260) */ 618 #define ICE_AQC_RULE_ID_VALID_S 7 619 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 620 #define ICE_AQC_RULE_ID_S 0 621 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 622 623 /* Following defines to be used while processing caller specified mirror list 624 * of VSI indexes. 625 */ 626 /* Action: Byte.bit (1.7) 627 * 0 = Remove VSI from mirror rule 628 * 1 = Add VSI to mirror rule 629 */ 630 #define ICE_AQC_RULE_ACT_S 15 631 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 632 /* Action: 1.2:0.0 = Mirrored VSI */ 633 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 634 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 635 636 /* This is to be used by add/update mirror rule Admin Queue command. 637 * In case of add mirror rule - if rule ID is specified as 638 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 639 * If specified rule_id is valid, then it is used. If specified rule_id 640 * is in use then new mirroring rule is added. 641 */ 642 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 643 644 struct ice_aqc_add_update_mir_rule { 645 __le16 rule_id; 646 647 __le16 rule_type; 648 #define ICE_AQC_RULE_TYPE_S 0 649 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 650 /* VPORT ingress/egress */ 651 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 652 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 653 /* Physical port ingress mirroring. 654 * All traffic received by this port 655 */ 656 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 657 /* Physical port egress mirroring. All traffic sent by this port */ 658 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 659 660 /* Number of mirrored entries. 661 * The values are in the command buffer 662 */ 663 __le16 num_entries; 664 665 /* Destination VSI */ 666 __le16 dest; 667 __le32 addr_high; 668 __le32 addr_low; 669 }; 670 671 /* Delete mirror rule - direct(0x0261) */ 672 struct ice_aqc_delete_mir_rule { 673 __le16 rule_id; 674 __le16 rsvd; 675 676 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 677 * the PF allocated resources, otherwise it is returned to the 678 * shared pool 679 */ 680 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 681 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 682 __le16 flags; 683 684 u8 reserved[10]; 685 }; 686 687 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 688 /* This structure holds get storm configuration response and same structure 689 * is used to perform set_storm_cfg 690 */ 691 struct ice_aqc_storm_cfg { 692 __le32 bcast_thresh_size; 693 __le32 mcast_thresh_size; 694 /* Bit 18:0 - Traffic upper threshold size 695 * Bit 31:19 - Reserved 696 */ 697 #define ICE_AQ_THRESHOLD_S 0 698 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 699 700 __le32 storm_ctrl_ctrl; 701 /* Bit 0: MDIPW - Drop Multicast packets in previous window 702 * Bit 1: MDICW - Drop multicast packets in current window 703 * Bit 2: BDIPW - Drop broadcast packets in previous window 704 * Bit 3: BDICW - Drop broadcast packets in current window 705 */ 706 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 707 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 708 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 709 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 710 /* Bit 7:5 : Reserved */ 711 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 712 * interval size for applying ingress broadcast or multicast storm 713 * control. 714 */ 715 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 716 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 717 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 718 __le32 reserved; 719 }; 720 721 #define ICE_MAX_NUM_RECIPES 64 722 723 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 724 struct ice_aqc_add_get_recipe { 725 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 726 __le16 return_index; /* Input, used for Get cmd only */ 727 u8 reserved[4]; 728 __le32 addr_high; 729 __le32 addr_low; 730 }; 731 732 struct ice_aqc_recipe_content { 733 u8 rid; 734 #define ICE_AQ_RECIPE_ID_S 0 735 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 736 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 737 #define ICE_AQ_SW_ID_LKUP_IDX 0 738 u8 lkup_indx[5]; 739 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 740 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 741 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 742 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 743 __le16 mask[5]; 744 u8 result_indx; 745 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 746 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 747 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 748 u8 rsvd0[3]; 749 u8 act_ctrl_join_priority; 750 u8 act_ctrl_fwd_priority; 751 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 752 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 753 u8 act_ctrl; 754 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 755 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 756 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 757 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 758 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 759 u8 rsvd1; 760 __le32 dflt_act; 761 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 762 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 763 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 764 }; 765 766 struct ice_aqc_recipe_data_elem { 767 u8 recipe_indx; 768 u8 resp_bits; 769 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 770 u8 rsvd0[2]; 771 u8 recipe_bitmap[8]; 772 u8 rsvd1[4]; 773 struct ice_aqc_recipe_content content; 774 u8 rsvd2[20]; 775 }; 776 777 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 778 struct ice_aqc_recipe_to_profile { 779 __le16 profile_id; 780 u8 rsvd[6]; 781 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES); 782 }; 783 784 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 785 */ 786 struct ice_aqc_sw_rules { 787 /* ops: add switch rules, referring the number of rules. 788 * ops: update switch rules, referring the number of filters 789 * ops: remove switch rules, referring the entry index. 790 * ops: get switch rules, referring to the number of filters. 791 */ 792 __le16 num_rules_fltr_entry_index; 793 u8 reserved[6]; 794 __le32 addr_high; 795 __le32 addr_low; 796 }; 797 798 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 799 * This structures describes the lookup rules and associated actions. "index" 800 * is returned as part of a response to a successful Add command, and can be 801 * used to identify the rule for Update/Get/Remove commands. 802 */ 803 struct ice_sw_rule_lkup_rx_tx { 804 __le16 recipe_id; 805 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 806 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 807 __le16 src; 808 __le32 act; 809 810 /* Bit 0:1 - Action type */ 811 #define ICE_SINGLE_ACT_TYPE_S 0x00 812 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 813 814 /* Bit 2 - Loop back enable 815 * Bit 3 - LAN enable 816 */ 817 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 818 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 819 820 /* Action type = 0 - Forward to VSI or VSI list */ 821 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 822 823 #define ICE_SINGLE_ACT_VSI_ID_S 4 824 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 825 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 826 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 827 /* This bit needs to be set if action is forward to VSI list */ 828 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 829 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 830 #define ICE_SINGLE_ACT_DROP BIT(18) 831 832 /* Action type = 1 - Forward to Queue of Queue group */ 833 #define ICE_SINGLE_ACT_TO_Q 0x1 834 #define ICE_SINGLE_ACT_Q_INDEX_S 4 835 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 836 #define ICE_SINGLE_ACT_Q_REGION_S 15 837 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 838 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 839 840 /* Action type = 2 - Prune */ 841 #define ICE_SINGLE_ACT_PRUNE 0x2 842 #define ICE_SINGLE_ACT_EGRESS BIT(15) 843 #define ICE_SINGLE_ACT_INGRESS BIT(16) 844 #define ICE_SINGLE_ACT_PRUNET BIT(17) 845 /* Bit 18 should be set to 0 for this action */ 846 847 /* Action type = 2 - Pointer */ 848 #define ICE_SINGLE_ACT_PTR 0x2 849 #define ICE_SINGLE_ACT_PTR_VAL_S 4 850 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 851 /* Bit 18 should be set to 1 */ 852 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 853 854 /* Action type = 3 - Other actions. Last two bits 855 * are other action identifier 856 */ 857 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 858 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 859 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 860 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 861 862 /* Bit 17:18 - Defines other actions */ 863 /* Other action = 0 - Mirror VSI */ 864 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 865 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 866 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 867 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 868 869 /* Other action = 3 - Set Stat count */ 870 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 871 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 872 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 873 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 874 875 __le16 index; /* The index of the rule in the lookup table */ 876 /* Length and values of the header to be matched per recipe or 877 * lookup-type 878 */ 879 __le16 hdr_len; 880 u8 hdr[STRUCT_HACK_VAR_LEN]; 881 }; 882 883 /* Add/Update/Remove large action command/response entry 884 * "index" is returned as part of a response to a successful Add command, and 885 * can be used to identify the action for Update/Get/Remove commands. 886 */ 887 struct ice_sw_rule_lg_act { 888 __le16 index; /* Index in large action table */ 889 __le16 size; 890 /* Max number of large actions */ 891 #define ICE_MAX_LG_ACT 4 892 /* Bit 0:1 - Action type */ 893 #define ICE_LG_ACT_TYPE_S 0 894 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 895 896 /* Action type = 0 - Forward to VSI or VSI list */ 897 #define ICE_LG_ACT_VSI_FORWARDING 0 898 #define ICE_LG_ACT_VSI_ID_S 3 899 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 900 #define ICE_LG_ACT_VSI_LIST_ID_S 3 901 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 902 /* This bit needs to be set if action is forward to VSI list */ 903 #define ICE_LG_ACT_VSI_LIST BIT(13) 904 905 #define ICE_LG_ACT_VALID_BIT BIT(16) 906 907 /* Action type = 1 - Forward to Queue of Queue group */ 908 #define ICE_LG_ACT_TO_Q 0x1 909 #define ICE_LG_ACT_Q_INDEX_S 3 910 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 911 #define ICE_LG_ACT_Q_REGION_S 14 912 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 913 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 914 915 /* Action type = 2 - Prune */ 916 #define ICE_LG_ACT_PRUNE 0x2 917 #define ICE_LG_ACT_EGRESS BIT(14) 918 #define ICE_LG_ACT_INGRESS BIT(15) 919 #define ICE_LG_ACT_PRUNET BIT(16) 920 921 /* Action type = 3 - Mirror VSI */ 922 #define ICE_LG_OTHER_ACT_MIRROR 0x3 923 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 924 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 925 926 /* Action type = 5 - Generic Value */ 927 #define ICE_LG_ACT_GENERIC 0x5 928 #define ICE_LG_ACT_GENERIC_VALUE_S 3 929 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 930 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 931 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 932 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 933 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 934 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 935 936 /* Action = 7 - Set Stat count */ 937 #define ICE_LG_ACT_STAT_COUNT 0x7 938 #define ICE_LG_ACT_STAT_COUNT_S 3 939 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 940 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 941 }; 942 943 /* Add/Update/Remove VSI list command/response entry 944 * "index" is returned as part of a response to a successful Add command, and 945 * can be used to identify the VSI list for Update/Get/Remove commands. 946 */ 947 struct ice_sw_rule_vsi_list { 948 __le16 index; /* Index of VSI/Prune list */ 949 __le16 number_vsi; 950 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 951 }; 952 953 #pragma pack(1) 954 /* Query VSI list command/response entry */ 955 struct ice_sw_rule_vsi_list_query { 956 __le16 index; 957 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 958 }; 959 #pragma pack() 960 961 #pragma pack(1) 962 /* Add switch rule response: 963 * Content of return buffer is same as the input buffer. The status field and 964 * LUT index are updated as part of the response 965 */ 966 struct ice_aqc_sw_rules_elem { 967 __le16 type; /* Switch rule type, one of T_... */ 968 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 969 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 970 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 971 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 972 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 973 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 974 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 975 __le16 status; 976 union { 977 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 978 struct ice_sw_rule_lg_act lg_act; 979 struct ice_sw_rule_vsi_list vsi_list; 980 struct ice_sw_rule_vsi_list_query vsi_list_query; 981 } pdata; 982 }; 983 984 #pragma pack() 985 986 /* PFC Ignore (direct 0x0301) 987 * The command and response use the same descriptor structure 988 */ 989 struct ice_aqc_pfc_ignore { 990 u8 tc_bitmap; 991 u8 cmd_flags; /* unused in response */ 992 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 993 #define ICE_AQC_PFC_IGNORE_CLEAR 0 994 u8 reserved[14]; 995 }; 996 997 /* Set PFC Mode (direct 0x0303) 998 * Query PFC Mode (direct 0x0302) 999 */ 1000 struct ice_aqc_set_query_pfc_mode { 1001 u8 pfc_mode; 1002 /* For Set Command response, reserved in all other cases */ 1003 #define ICE_AQC_PFC_NOT_CONFIGURED 0 1004 /* For Query Command response, reserved in all other cases */ 1005 #define ICE_AQC_DCB_DIS 0 1006 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 1007 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 1008 u8 rsvd[15]; 1009 }; 1010 1011 /* Set DCB Parameters (direct 0x0306) */ 1012 struct ice_aqc_set_dcb_params { 1013 u8 cmd_flags; /* unused in response */ 1014 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 1015 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 1016 u8 valid_flags; /* unused in response */ 1017 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1018 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 1019 u8 rsvd[14]; 1020 }; 1021 1022 /* Get Default Topology (indirect 0x0400) */ 1023 struct ice_aqc_get_topo { 1024 u8 port_num; 1025 u8 num_branches; 1026 __le16 reserved1; 1027 __le32 reserved2; 1028 __le32 addr_high; 1029 __le32 addr_low; 1030 }; 1031 1032 /* Update TSE (indirect 0x0403) 1033 * Get TSE (indirect 0x0404) 1034 * Add TSE (indirect 0x0401) 1035 * Delete TSE (indirect 0x040F) 1036 * Move TSE (indirect 0x0408) 1037 * Suspend Nodes (indirect 0x0409) 1038 * Resume Nodes (indirect 0x040A) 1039 */ 1040 struct ice_aqc_sched_elem_cmd { 1041 __le16 num_elem_req; /* Used by commands */ 1042 __le16 num_elem_resp; /* Used by responses */ 1043 __le32 reserved; 1044 __le32 addr_high; 1045 __le32 addr_low; 1046 }; 1047 1048 struct ice_aqc_txsched_move_grp_info_hdr { 1049 __le32 src_parent_teid; 1050 __le32 dest_parent_teid; 1051 __le16 num_elems; 1052 u8 flags; 1053 u8 reserved; 1054 }; 1055 1056 struct ice_aqc_move_elem { 1057 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1058 __le32 teid[STRUCT_HACK_VAR_LEN]; 1059 }; 1060 1061 struct ice_aqc_elem_info_bw { 1062 __le16 bw_profile_idx; 1063 __le16 bw_alloc; 1064 }; 1065 1066 struct ice_aqc_txsched_elem { 1067 u8 elem_type; /* Special field, reserved for some aq calls */ 1068 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1069 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1070 #define ICE_AQC_ELEM_TYPE_TC 0x2 1071 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1072 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1073 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1074 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1075 u8 valid_sections; 1076 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1077 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1078 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1079 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1080 u8 generic; 1081 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1082 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1083 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1084 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1085 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1086 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1087 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1088 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1089 u8 flags; /* Special field, reserved for some aq calls */ 1090 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1091 struct ice_aqc_elem_info_bw cir_bw; 1092 struct ice_aqc_elem_info_bw eir_bw; 1093 __le16 srl_id; 1094 __le16 reserved2; 1095 }; 1096 1097 struct ice_aqc_txsched_elem_data { 1098 __le32 parent_teid; 1099 __le32 node_teid; 1100 struct ice_aqc_txsched_elem data; 1101 }; 1102 1103 struct ice_aqc_txsched_topo_grp_info_hdr { 1104 __le32 parent_teid; 1105 __le16 num_elems; 1106 __le16 reserved2; 1107 }; 1108 1109 struct ice_aqc_add_elem { 1110 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1111 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1112 }; 1113 1114 struct ice_aqc_get_topo_elem { 1115 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1116 struct ice_aqc_txsched_elem_data 1117 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1118 }; 1119 1120 struct ice_aqc_delete_elem { 1121 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1122 __le32 teid[STRUCT_HACK_VAR_LEN]; 1123 }; 1124 1125 /* Query Port ETS (indirect 0x040E) 1126 * 1127 * This indirect command is used to query port TC node configuration. 1128 */ 1129 struct ice_aqc_query_port_ets { 1130 __le32 port_teid; 1131 __le32 reserved; 1132 __le32 addr_high; 1133 __le32 addr_low; 1134 }; 1135 1136 struct ice_aqc_port_ets_elem { 1137 u8 tc_valid_bits; 1138 u8 reserved[3]; 1139 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1140 __le32 up2tc; 1141 u8 tc_bw_share[8]; 1142 __le32 port_eir_prof_id; 1143 __le32 port_cir_prof_id; 1144 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1145 __le32 tc_node_prio; 1146 #define ICE_TC_NODE_PRIO_S 0x4 1147 u8 reserved1[4]; 1148 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1149 }; 1150 1151 /* Rate limiting profile for 1152 * Add RL profile (indirect 0x0410) 1153 * Query RL profile (indirect 0x0411) 1154 * Remove RL profile (indirect 0x0415) 1155 * These indirect commands acts on single or multiple 1156 * RL profiles with specified data. 1157 */ 1158 struct ice_aqc_rl_profile { 1159 __le16 num_profiles; 1160 __le16 num_processed; /* Only for response. Reserved in Command. */ 1161 u8 reserved[4]; 1162 __le32 addr_high; 1163 __le32 addr_low; 1164 }; 1165 1166 struct ice_aqc_rl_profile_elem { 1167 u8 level; 1168 u8 flags; 1169 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1170 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1171 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1172 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1173 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1174 /* The following flag is used for Query RL Profile Data */ 1175 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1176 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1177 1178 __le16 profile_id; 1179 __le16 max_burst_size; 1180 __le16 rl_multiply; 1181 __le16 wake_up_calc; 1182 __le16 rl_encode; 1183 }; 1184 1185 /* Configure L2 Node CGD (indirect 0x0414) 1186 * This indirect command allows configuring a congestion domain for given L2 1187 * node TEIDs in the scheduler topology. 1188 */ 1189 struct ice_aqc_cfg_l2_node_cgd { 1190 __le16 num_l2_nodes; 1191 u8 reserved[6]; 1192 __le32 addr_high; 1193 __le32 addr_low; 1194 }; 1195 1196 struct ice_aqc_cfg_l2_node_cgd_elem { 1197 __le32 node_teid; 1198 u8 cgd; 1199 u8 reserved[3]; 1200 }; 1201 1202 /* Query Scheduler Resource Allocation (indirect 0x0412) 1203 * This indirect command retrieves the scheduler resources allocated by 1204 * EMP Firmware to the given PF. 1205 */ 1206 struct ice_aqc_query_txsched_res { 1207 u8 reserved[8]; 1208 __le32 addr_high; 1209 __le32 addr_low; 1210 }; 1211 1212 struct ice_aqc_generic_sched_props { 1213 __le16 phys_levels; 1214 __le16 logical_levels; 1215 u8 flattening_bitmap; 1216 u8 max_device_cgds; 1217 u8 max_pf_cgds; 1218 u8 rsvd0; 1219 __le16 rdma_qsets; 1220 u8 rsvd1[22]; 1221 }; 1222 1223 struct ice_aqc_layer_props { 1224 u8 logical_layer; 1225 u8 chunk_size; 1226 __le16 max_device_nodes; 1227 __le16 max_pf_nodes; 1228 u8 rsvd0[4]; 1229 __le16 max_sibl_grp_sz; 1230 __le16 max_cir_rl_profiles; 1231 __le16 max_eir_rl_profiles; 1232 __le16 max_srl_profiles; 1233 u8 rsvd1[14]; 1234 }; 1235 1236 struct ice_aqc_query_txsched_res_resp { 1237 struct ice_aqc_generic_sched_props sched_props; 1238 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1239 }; 1240 1241 /* Query Node to Root Topology (indirect 0x0413) 1242 * This command uses ice_aqc_get_elem as its data buffer. 1243 */ 1244 struct ice_aqc_query_node_to_root { 1245 __le32 teid; 1246 __le32 num_nodes; /* Response only */ 1247 __le32 addr_high; 1248 __le32 addr_low; 1249 }; 1250 1251 /* Get PHY capabilities (indirect 0x0600) */ 1252 struct ice_aqc_get_phy_caps { 1253 u8 lport_num; 1254 u8 reserved; 1255 __le16 param0; 1256 /* 18.0 - Report qualified modules */ 1257 #define ICE_AQC_GET_PHY_RQM BIT(0) 1258 /* 18.1 - 18.3 : Report mode 1259 * 000b - Report NVM capabilities 1260 * 001b - Report topology capabilities 1261 * 010b - Report SW configured 1262 * 100b - Report default capabilities 1263 */ 1264 #define ICE_AQC_REPORT_MODE_S 1 1265 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1266 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1267 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1268 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1269 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1270 __le32 reserved1; 1271 __le32 addr_high; 1272 __le32 addr_low; 1273 }; 1274 1275 /* This is #define of PHY type (Extended): 1276 * The first set of defines is for phy_type_low. 1277 */ 1278 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1279 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1280 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1281 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1282 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1283 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1284 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1285 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1286 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1287 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1288 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1289 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1290 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1291 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1292 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1293 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1294 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1295 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1296 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1297 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1298 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1299 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1300 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1301 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1302 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1303 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1304 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1305 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1306 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1307 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1308 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1309 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1310 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1311 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1312 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1313 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1314 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1315 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1316 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1317 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1318 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1319 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1320 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1321 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1322 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1323 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1324 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1325 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1326 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1327 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1328 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1329 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1330 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1331 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1332 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1333 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1334 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1335 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1336 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1337 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1338 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1339 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1340 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1341 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1342 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1343 /* The second set of defines is for phy_type_high. */ 1344 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1345 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1346 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1347 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1348 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1349 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1350 1351 struct ice_aqc_get_phy_caps_data { 1352 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1353 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1354 u8 caps; 1355 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1356 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1357 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1358 #define ICE_AQC_PHY_EN_LINK BIT(3) 1359 #define ICE_AQC_PHY_AN_MODE BIT(4) 1360 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1361 #define ICE_AQC_PHY_EN_LESM BIT(6) 1362 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1363 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1364 u8 low_power_ctrl_an; 1365 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1366 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1367 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1368 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1369 __le16 eee_cap; 1370 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1371 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1372 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1373 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1374 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1375 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1376 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1377 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1378 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1379 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1380 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1381 __le16 eeer_value; 1382 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1383 u8 phy_fw_ver[8]; 1384 u8 link_fec_options; 1385 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1386 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1387 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1388 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1389 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1390 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1391 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1392 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1393 u8 module_compliance_enforcement; 1394 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1395 u8 extended_compliance_code; 1396 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1397 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1398 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1399 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1400 #define ICE_AQC_MOD_TYPE_IDENT 1 1401 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1402 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1403 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1404 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1405 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1406 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1407 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1408 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1409 u8 qualified_module_count; 1410 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1411 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1412 struct { 1413 u8 v_oui[3]; 1414 u8 rsvd3; 1415 u8 v_part[16]; 1416 __le32 v_rev; 1417 __le64 rsvd4; 1418 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1419 }; 1420 1421 /* Set PHY capabilities (direct 0x0601) 1422 * NOTE: This command must be followed by setup link and restart auto-neg 1423 */ 1424 struct ice_aqc_set_phy_cfg { 1425 u8 lport_num; 1426 u8 reserved[7]; 1427 __le32 addr_high; 1428 __le32 addr_low; 1429 }; 1430 1431 /* Set PHY config command data structure */ 1432 struct ice_aqc_set_phy_cfg_data { 1433 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1434 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1435 u8 caps; 1436 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1437 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1438 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1439 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1440 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1441 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1442 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1443 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1444 u8 low_power_ctrl_an; 1445 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1446 __le16 eeer_value; 1447 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1448 u8 module_compliance_enforcement; 1449 }; 1450 1451 /* Set MAC Config command data structure (direct 0x0603) */ 1452 struct ice_aqc_set_mac_cfg { 1453 __le16 max_frame_size; 1454 u8 params; 1455 #define ICE_AQ_SET_MAC_PACE_S 3 1456 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1457 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1458 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1459 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1460 u8 tx_tmr_priority; 1461 __le16 tx_tmr_value; 1462 __le16 fc_refresh_threshold; 1463 u8 drop_opts; 1464 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1465 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1466 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1467 u8 reserved[7]; 1468 }; 1469 1470 /* Restart AN command data structure (direct 0x0605) 1471 * Also used for response, with only the lport_num field present. 1472 */ 1473 struct ice_aqc_restart_an { 1474 u8 lport_num; 1475 u8 reserved; 1476 u8 cmd_flags; 1477 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1478 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1479 u8 reserved2[13]; 1480 }; 1481 1482 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1483 struct ice_aqc_get_link_status { 1484 u8 lport_num; 1485 u8 reserved; 1486 __le16 cmd_flags; 1487 #define ICE_AQ_LSE_M 0x3 1488 #define ICE_AQ_LSE_NOP 0x0 1489 #define ICE_AQ_LSE_DIS 0x2 1490 #define ICE_AQ_LSE_ENA 0x3 1491 /* only response uses this flag */ 1492 #define ICE_AQ_LSE_IS_ENABLED 0x1 1493 __le32 reserved2; 1494 __le32 addr_high; 1495 __le32 addr_low; 1496 }; 1497 1498 /* Get link status response data structure, also used for Link Status Event */ 1499 struct ice_aqc_get_link_status_data { 1500 u8 topo_media_conflict; 1501 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1502 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1503 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1504 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1505 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1506 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1507 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1508 u8 link_cfg_err; 1509 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1510 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1511 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1512 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1513 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1514 u8 link_info; 1515 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1516 #define ICE_AQ_LINK_FAULT BIT(1) 1517 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1518 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1519 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1520 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1521 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1522 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1523 u8 an_info; 1524 #define ICE_AQ_AN_COMPLETED BIT(0) 1525 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1526 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1527 #define ICE_AQ_FEC_EN BIT(3) 1528 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1529 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1530 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1531 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1532 u8 ext_info; 1533 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1534 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1535 /* Port Tx Suspended */ 1536 #define ICE_AQ_LINK_TX_S 2 1537 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1538 #define ICE_AQ_LINK_TX_ACTIVE 0 1539 #define ICE_AQ_LINK_TX_DRAINED 1 1540 #define ICE_AQ_LINK_TX_FLUSHED 3 1541 u8 lb_status; 1542 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1543 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1544 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1545 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1546 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1547 __le16 max_frame_size; 1548 u8 cfg; 1549 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1550 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1551 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1552 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1553 /* Pacing Config */ 1554 #define ICE_AQ_CFG_PACING_S 3 1555 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1556 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1557 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1558 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1559 /* External Device Power Ability */ 1560 u8 power_desc; 1561 #define ICE_AQ_PWR_CLASS_M 0x3F 1562 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1563 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1564 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1565 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1566 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1567 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1568 __le16 link_speed; 1569 #define ICE_AQ_LINK_SPEED_M 0x7FF 1570 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1571 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1572 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1573 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1574 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1575 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1576 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1577 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1578 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1579 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1580 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1581 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1582 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1583 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1584 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1585 }; 1586 1587 /* Set event mask command (direct 0x0613) */ 1588 struct ice_aqc_set_event_mask { 1589 u8 lport_num; 1590 u8 reserved[7]; 1591 __le16 event_mask; 1592 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1593 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1594 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1595 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1596 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1597 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1598 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1599 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1600 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1601 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1602 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1603 u8 reserved1[6]; 1604 }; 1605 1606 /* Set MAC Loopback command (direct 0x0620) */ 1607 struct ice_aqc_set_mac_lb { 1608 u8 lb_mode; 1609 #define ICE_AQ_MAC_LB_EN BIT(0) 1610 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1611 u8 reserved[15]; 1612 }; 1613 1614 struct ice_aqc_link_topo_addr { 1615 u8 lport_num; 1616 u8 lport_num_valid; 1617 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1618 u8 node_type_ctx; 1619 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1620 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1621 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1622 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1623 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1624 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1625 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1626 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1627 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1628 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1629 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1630 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1631 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1632 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1633 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1634 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1635 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1636 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1637 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1638 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1639 u8 index; 1640 __le16 handle; 1641 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1642 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1643 /* Used to decode the handle field */ 1644 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1645 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1646 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1647 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1648 /* In case of a Mezzanine type */ 1649 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1650 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1651 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1652 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1653 /* In case of a LOM type */ 1654 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1655 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1656 }; 1657 1658 /* Get Link Topology Handle (direct, 0x06E0) */ 1659 struct ice_aqc_get_link_topo { 1660 struct ice_aqc_link_topo_addr addr; 1661 u8 node_part_num; 1662 u8 rsvd[9]; 1663 }; 1664 1665 /* Set Port Identification LED (direct, 0x06E9) */ 1666 struct ice_aqc_set_port_id_led { 1667 u8 lport_num; 1668 u8 lport_num_valid; 1669 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1670 u8 ident_mode; 1671 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1672 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1673 u8 rsvd[13]; 1674 }; 1675 1676 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1677 struct ice_aqc_sff_eeprom { 1678 u8 lport_num; 1679 u8 lport_num_valid; 1680 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1681 __le16 i2c_bus_addr; 1682 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1683 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1684 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1685 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1686 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1687 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1688 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1689 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1690 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1691 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1692 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1693 __le16 i2c_mem_addr; 1694 __le16 eeprom_page; 1695 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1696 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1697 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1698 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1699 __le32 addr_high; 1700 __le32 addr_low; 1701 }; 1702 1703 /* SW Set GPIO command (indirect 0x6EF) 1704 * SW Get GPIO command (indirect 0x6F0) 1705 */ 1706 struct ice_aqc_sw_gpio { 1707 __le16 gpio_ctrl_handle; 1708 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 1709 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 1710 u8 gpio_num; 1711 #define ICE_AQC_SW_GPIO_NUMBER_S 0 1712 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 1713 u8 gpio_params; 1714 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 1715 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 1716 u8 rsvd[12]; 1717 }; 1718 1719 /* NVM Read command (indirect 0x0701) 1720 * NVM Erase commands (direct 0x0702) 1721 * NVM Write commands (indirect 0x0703) 1722 * NVM Write Activate commands (direct 0x0707) 1723 * NVM Shadow RAM Dump commands (direct 0x0707) 1724 */ 1725 struct ice_aqc_nvm { 1726 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1727 __le16 offset_low; 1728 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 1729 u8 cmd_flags; 1730 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1731 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 1732 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 1733 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1734 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1735 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1736 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1737 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1738 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1739 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1740 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1741 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1742 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1743 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 1744 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1745 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ 1746 #define ICE_AQC_NVM_PERST_FLAG 1 1747 #define ICE_AQC_NVM_EMPR_FLAG 2 1748 __le16 module_typeid; 1749 __le16 length; 1750 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1751 __le32 addr_high; 1752 __le32 addr_low; 1753 }; 1754 1755 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 1756 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 1757 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 1758 1759 #define ICE_AQC_NVM_START_POINT 0 1760 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 1761 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 1762 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 1763 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 1764 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 1765 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 1766 1767 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 1768 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 1769 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 1770 1771 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 1772 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 1773 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 1774 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 1775 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 1776 1777 /* Used for 0x0704 as well as for 0x0705 commands */ 1778 struct ice_aqc_nvm_cfg { 1779 u8 cmd_flags; 1780 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 1781 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 1782 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 1783 u8 reserved; 1784 __le16 count; 1785 __le16 id; 1786 u8 reserved1[2]; 1787 __le32 addr_high; 1788 __le32 addr_low; 1789 }; 1790 1791 struct ice_aqc_nvm_cfg_data { 1792 __le16 field_id; 1793 __le16 field_options; 1794 __le16 field_value; 1795 }; 1796 1797 /* NVM Checksum Command (direct, 0x0706) */ 1798 struct ice_aqc_nvm_checksum { 1799 u8 flags; 1800 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1801 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1802 u8 rsvd; 1803 __le16 checksum; /* Used only by response */ 1804 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1805 u8 rsvd2[12]; 1806 }; 1807 1808 /* Get LLDP MIB (indirect 0x0A00) 1809 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1810 * as the format is the same. 1811 */ 1812 struct ice_aqc_lldp_get_mib { 1813 u8 type; 1814 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1815 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1816 #define ICE_AQ_LLDP_MIB_LOCAL 0 1817 #define ICE_AQ_LLDP_MIB_REMOTE 1 1818 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1819 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1820 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1821 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1822 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1823 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1824 #define ICE_AQ_LLDP_TX_S 0x4 1825 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1826 #define ICE_AQ_LLDP_TX_ACTIVE 0 1827 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1828 #define ICE_AQ_LLDP_TX_FLUSHED 3 1829 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1830 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1831 * Get LLDP MIB (0x0A00) response only. 1832 */ 1833 u8 reserved1; 1834 __le16 local_len; 1835 __le16 remote_len; 1836 u8 reserved2[2]; 1837 __le32 addr_high; 1838 __le32 addr_low; 1839 }; 1840 1841 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1842 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1843 struct ice_aqc_lldp_set_mib_change { 1844 u8 command; 1845 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1846 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1847 u8 reserved[15]; 1848 }; 1849 1850 /* Add LLDP TLV (indirect 0x0A02) 1851 * Delete LLDP TLV (indirect 0x0A04) 1852 */ 1853 struct ice_aqc_lldp_add_delete_tlv { 1854 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1855 u8 reserved1[1]; 1856 __le16 len; 1857 u8 reserved2[4]; 1858 __le32 addr_high; 1859 __le32 addr_low; 1860 }; 1861 1862 /* Update LLDP TLV (indirect 0x0A03) */ 1863 struct ice_aqc_lldp_update_tlv { 1864 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1865 u8 reserved; 1866 __le16 old_len; 1867 __le16 new_offset; 1868 __le16 new_len; 1869 __le32 addr_high; 1870 __le32 addr_low; 1871 }; 1872 1873 /* Stop LLDP (direct 0x0A05) */ 1874 struct ice_aqc_lldp_stop { 1875 u8 command; 1876 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1877 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1878 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1879 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1880 u8 reserved[15]; 1881 }; 1882 1883 /* Start LLDP (direct 0x0A06) */ 1884 struct ice_aqc_lldp_start { 1885 u8 command; 1886 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1887 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1888 u8 reserved[15]; 1889 }; 1890 1891 /* Get CEE DCBX Oper Config (0x0A07) 1892 * The command uses the generic descriptor struct and 1893 * returns the struct below as an indirect response. 1894 */ 1895 struct ice_aqc_get_cee_dcb_cfg_resp { 1896 u8 oper_num_tc; 1897 u8 oper_prio_tc[4]; 1898 u8 oper_tc_bw[8]; 1899 u8 oper_pfc_en; 1900 __le16 oper_app_prio; 1901 #define ICE_AQC_CEE_APP_FCOE_S 0 1902 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1903 #define ICE_AQC_CEE_APP_ISCSI_S 3 1904 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1905 #define ICE_AQC_CEE_APP_FIP_S 8 1906 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1907 __le32 tlv_status; 1908 #define ICE_AQC_CEE_PG_STATUS_S 0 1909 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1910 #define ICE_AQC_CEE_PFC_STATUS_S 3 1911 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1912 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1913 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1914 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1915 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1916 #define ICE_AQC_CEE_FIP_STATUS_S 16 1917 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1918 u8 reserved[12]; 1919 }; 1920 1921 /* Set Local LLDP MIB (indirect 0x0A08) 1922 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1923 */ 1924 struct ice_aqc_lldp_set_local_mib { 1925 u8 type; 1926 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1927 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1928 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1929 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1930 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1931 u8 reserved0; 1932 __le16 length; 1933 u8 reserved1[4]; 1934 __le32 addr_high; 1935 __le32 addr_low; 1936 }; 1937 1938 struct ice_aqc_lldp_set_local_mib_resp { 1939 u8 status; 1940 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 1941 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 1942 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 1943 u8 reserved[15]; 1944 }; 1945 1946 /* Stop/Start LLDP Agent (direct 0x0A09) 1947 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1948 * The same structure is used for the response, with the command field 1949 * being used as the status field. 1950 */ 1951 struct ice_aqc_lldp_stop_start_specific_agent { 1952 u8 command; 1953 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1954 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1955 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1956 u8 reserved[15]; 1957 }; 1958 1959 /* LLDP Filter Control (direct 0x0A0A) */ 1960 struct ice_aqc_lldp_filter_ctrl { 1961 u8 cmd_flags; 1962 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 1963 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1964 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1965 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 1966 u8 reserved1; 1967 __le16 vsi_num; 1968 u8 reserved2[12]; 1969 }; 1970 1971 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1972 struct ice_aqc_get_set_rss_key { 1973 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1974 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1975 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1976 __le16 vsi_id; 1977 u8 reserved[6]; 1978 __le32 addr_high; 1979 __le32 addr_low; 1980 }; 1981 1982 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1983 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1984 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1985 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1986 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1987 1988 /** 1989 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 1990 * @standard_rss_key: 40 most significant bytes of hash key 1991 * @extended_hash_key: 12 least significant bytes of hash key 1992 * 1993 * Set/Get 40 byte hash key using standard_rss_key field, and set 1994 * extended_hash_key field to zero. Set/Get 52 byte hash key using 1995 * standard_rss_key field for 40 most significant bytes and the 1996 * extended_hash_key field for the 12 least significant bytes of hash key. 1997 */ 1998 struct ice_aqc_get_set_rss_keys { 1999 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2000 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2001 }; 2002 2003 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2004 struct ice_aqc_get_set_rss_lut { 2005 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2006 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2007 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2008 __le16 vsi_id; 2009 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2010 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2011 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2012 2013 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2014 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2015 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2016 2017 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2018 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2019 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2020 2021 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2022 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2023 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2024 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2025 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2026 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2027 2028 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2029 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2030 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2031 2032 __le16 flags; 2033 __le32 reserved; 2034 __le32 addr_high; 2035 __le32 addr_low; 2036 }; 2037 2038 /* Clear FD Table Command (direct, 0x0B06) */ 2039 struct ice_aqc_clear_fd_table { 2040 u8 clear_type; 2041 #define CL_FD_VM_VF_TYPE_VSI_IDX 1 2042 #define CL_FD_VM_VF_TYPE_PF_IDX 2 2043 u8 rsvd; 2044 __le16 vsi_index; 2045 u8 reserved[12]; 2046 }; 2047 2048 /* Allocate ACL table (indirect 0x0C10) */ 2049 #define ICE_AQC_ACL_KEY_WIDTH 40 2050 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5 2051 #define ICE_AQC_ACL_TCAM_DEPTH 512 2052 #define ICE_ACL_ENTRY_ALLOC_UNIT 64 2053 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15 2054 #define ICE_AQC_MAX_ACTION_MEMORIES 20 2055 #define ICE_AQC_MAX_ACTION_ENTRIES 512 2056 #define ICE_AQC_ACL_SLICES 16 2057 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000 2058 /* The ACL block supports up to 8 actions per a single output. */ 2059 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4 2060 2061 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \ 2062 ICE_ACL_ENTRY_ALLOC_UNIT) 2063 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \ 2064 ICE_AQC_MAX_TCAM_ALLOC_UNITS) 2065 2066 struct ice_aqc_acl_alloc_table { 2067 __le16 table_width; 2068 __le16 table_depth; 2069 u8 act_pairs_per_entry; 2070 /* For non-concurrent table allocation, this field needs 2071 * to be set to zero(0) otherwise it shall specify the 2072 * amount of concurrent tables whose AllocIDs are 2073 * specified in buffer. Thus the newly allocated table 2074 * is concurrent with table IDs specified in AllocIDs. 2075 */ 2076 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0 2077 u8 table_type; 2078 __le16 reserved; 2079 __le32 addr_high; 2080 __le32 addr_low; 2081 }; 2082 2083 /* Allocate ACL table command buffer format */ 2084 struct ice_aqc_acl_alloc_table_data { 2085 /* Dependent table AllocIDs. Each word in this 15 word array specifies 2086 * a dependent table AllocID according to the amount specified in the 2087 * "table_type" field. All unused words shall be set to 0xFFFF 2088 */ 2089 #define ICE_AQC_CONCURR_ID_INVALID 0xffff 2090 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL]; 2091 }; 2092 2093 /* Deallocate ACL table (indirect 0x0C11) 2094 * Allocate ACL action-pair (indirect 0x0C12) 2095 * Deallocate ACL action-pair (indirect 0x0C13) 2096 */ 2097 2098 /* Following structure is common and used in case of deallocation 2099 * of ACL table and action-pair 2100 */ 2101 struct ice_aqc_acl_tbl_actpair { 2102 /* Alloc ID of the table being released */ 2103 __le16 alloc_id; 2104 u8 reserved[6]; 2105 __le32 addr_high; 2106 __le32 addr_low; 2107 }; 2108 2109 /* This response structure is same in case of alloc/dealloc table, 2110 * alloc/dealloc action-pair 2111 */ 2112 struct ice_aqc_acl_generic { 2113 /* if alloc_id is below 0x1000 then alllocation failed due to 2114 * unavailable resources, else this is set by FW to identify 2115 * table allocation 2116 */ 2117 __le16 alloc_id; 2118 2119 union { 2120 /* to be used only in case of alloc/dealloc table */ 2121 struct { 2122 /* Index of the first TCAM block, otherwise set to 0xFF 2123 * for a failed allocation 2124 */ 2125 u8 first_tcam; 2126 /* Index of the last TCAM block. This index shall be 2127 * set to the value of first_tcam for single TCAM block 2128 * allocation, otherwise set to 0xFF for a failed 2129 * allocation 2130 */ 2131 u8 last_tcam; 2132 } table; 2133 /* reserved in case of alloc/dealloc action-pair */ 2134 struct { 2135 __le16 reserved; 2136 } act_pair; 2137 } ops; 2138 2139 /* index of first entry (in both TCAM and action memories), 2140 * otherwise set to 0xFF for a failed allocation 2141 */ 2142 __le16 first_entry; 2143 /* index of last entry (in both TCAM and action memories), 2144 * otherwise set to 0xFF for a failed allocation 2145 */ 2146 __le16 last_entry; 2147 2148 /* Each act_mem element specifies the order of the memory 2149 * otherwise 0xFF 2150 */ 2151 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES]; 2152 }; 2153 2154 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate 2155 * response buffer since original command buffer gets updated with 2156 * 'scen_id' in case of success 2157 */ 2158 struct ice_aqc_acl_alloc_scen { 2159 union { 2160 struct { 2161 u8 reserved[8]; 2162 } cmd; 2163 struct { 2164 __le16 scen_id; 2165 u8 reserved[6]; 2166 } resp; 2167 } ops; 2168 __le32 addr_high; 2169 __le32 addr_low; 2170 }; 2171 2172 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need 2173 * separate response buffer since nothing to be returned as a response 2174 * except status. 2175 */ 2176 struct ice_aqc_acl_dealloc_scen { 2177 __le16 scen_id; 2178 u8 reserved[14]; 2179 }; 2180 2181 /* Update ACL scenario (direct 0x0C1B) 2182 * Query ACL scenario (direct 0x0C23) 2183 */ 2184 struct ice_aqc_acl_update_query_scen { 2185 __le16 scen_id; 2186 u8 reserved[6]; 2187 __le32 addr_high; 2188 __le32 addr_low; 2189 }; 2190 2191 /* Input buffer format in case allocate/update ACL scenario and same format 2192 * is used for response buffer in case of query ACL scenario. 2193 * NOTE: de-allocate ACL scenario is direct command and doesn't require 2194 * "buffer", hence no buffer format. 2195 */ 2196 struct ice_aqc_acl_scen { 2197 struct { 2198 /* Byte [x] selection for the TCAM key. This value must be 2199 * set to 0x0 for unusued TCAM. 2200 * Only Bit 6..0 is used in each byte and MSB is reserved 2201 */ 2202 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F 2203 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20 2204 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E 2205 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE 2206 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F 2207 u8 tcam_select[5]; 2208 /* TCAM Block entry masking. This value should be set to 0x0 for 2209 * unused TCAM 2210 */ 2211 u8 chnk_msk; 2212 /* Bit 0 : masks TCAM entries 0-63 2213 * Bit 1 : masks TCAM entries 64-127 2214 * Bit 2 to 7 : follow the pattern of bit 0 and 1 2215 */ 2216 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0) 2217 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1) 2218 u8 start_cmp_set; 2219 2220 } tcam_cfg[ICE_AQC_ACL_SLICES]; 2221 2222 /* Each byte, Bit 6..0: Action memory association to a TCAM block, 2223 * otherwise it shall be set to 0x0 for disabled memory action. 2224 * Bit 7 : Action memory enable for this scenario 2225 */ 2226 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F 2227 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7) 2228 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES]; 2229 }; 2230 2231 /* Allocate ACL counters (indirect 0x0C16) */ 2232 struct ice_aqc_acl_alloc_counters { 2233 /* Amount of contiguous counters requested. Min value is 1 and 2234 * max value is 255 2235 */ 2236 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1 2237 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF 2238 u8 counter_amount; 2239 2240 /* Counter type: 'single counter' which can be configured to count 2241 * either bytes or packets 2242 */ 2243 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0 2244 2245 /* Counter type: 'counter pair' which counts number of bytes and number 2246 * of packets. 2247 */ 2248 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1 2249 /* requested counter type, single/dual */ 2250 u8 counters_type; 2251 2252 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */ 2253 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3 2254 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */ 2255 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1 2256 /* requested counter bank allocation */ 2257 u8 bank_alloc; 2258 2259 u8 reserved; 2260 2261 union { 2262 /* Applicable only in case of command */ 2263 struct { 2264 u8 reserved[12]; 2265 } cmd; 2266 /* Applicable only in case of response */ 2267 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF 2268 struct { 2269 /* Index of first allocated counter. 0xFFFF in case 2270 * of unsuccessful allocation 2271 */ 2272 __le16 first_counter; 2273 /* Index of last allocated counter. 0xFFFF in case 2274 * of unsuccessful allocation 2275 */ 2276 __le16 last_counter; 2277 u8 rsvd[8]; 2278 } resp; 2279 } ops; 2280 }; 2281 2282 /* De-allocate ACL counters (direct 0x0C17) */ 2283 struct ice_aqc_acl_dealloc_counters { 2284 /* first counter being released */ 2285 __le16 first_counter; 2286 /* last counter being released */ 2287 __le16 last_counter; 2288 /* requested counter type, single/dual */ 2289 u8 counters_type; 2290 /* requested counter bank allocation */ 2291 u8 bank_alloc; 2292 u8 reserved[10]; 2293 }; 2294 2295 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the 2296 * resources allocated for it using a single command 2297 */ 2298 struct ice_aqc_acl_dealloc_res { 2299 u8 reserved[16]; 2300 }; 2301 2302 /* Program ACL actionpair (indirect 0x0C1C) 2303 * Query ACL actionpair (indirect 0x0C25) 2304 */ 2305 struct ice_aqc_acl_actpair { 2306 /* action mem index to program/update */ 2307 u8 act_mem_index; 2308 u8 reserved; 2309 /* The entry index in action memory to be programmed/updated */ 2310 __le16 act_entry_index; 2311 __le32 reserved2; 2312 __le32 addr_high; 2313 __le32 addr_low; 2314 }; 2315 2316 /* Input buffer format for program/query action-pair admin command */ 2317 struct ice_acl_act_entry { 2318 /* Action priority, values must be between 0..7 */ 2319 #define ICE_AQC_ACT_PRIO_VALID_MAX 7 2320 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0) 2321 u8 prio; 2322 /* Action meta-data identifier. This field should be set to 0x0 2323 * for a NOP action 2324 */ 2325 #define ICE_AQC_ACT_MDID_S 8 2326 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S) 2327 u8 mdid; 2328 /* Action value */ 2329 #define ICE_AQC_ACT_VALUE_S 16 2330 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16) 2331 __le16 value; 2332 }; 2333 2334 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2 2335 struct ice_aqc_actpair { 2336 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR]; 2337 }; 2338 2339 /* Generic format used to describe either input or response buffer 2340 * for admin commands related to ACL profile 2341 */ 2342 struct ice_aqc_acl_prof_generic_frmt { 2343 /* The first byte of the byte selection base is reserved to keep the 2344 * first byte of the field vector where the packet direction info is 2345 * available. Thus we should start at index 1 of the field vector to 2346 * map its entries to the byte selection base. 2347 */ 2348 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1 2349 /* In each byte: 2350 * Bit 0..5 = Byte selection for the byte selection base from the 2351 * extracted fields (expressed as byte offset in extracted fields). 2352 * Applicable values are 0..63 2353 * Bit 6..7 = Reserved 2354 */ 2355 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30 2356 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS]; 2357 /* In each byte: 2358 * Bit 0..4 = Word selection for the word selection base from the 2359 * extracted fields (expressed as word offset in extracted fields). 2360 * Applicable values are 0..31 2361 * Bit 5..7 = Reserved 2362 */ 2363 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32 2364 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS]; 2365 /* In each byte: 2366 * Bit 0..3 = Double word selection for the double-word selection base 2367 * from the extracted fields (expressed as double-word offset in 2368 * extracted fields). 2369 * Applicable values are 0..15 2370 * Bit 4..7 = Reserved 2371 */ 2372 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15 2373 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS]; 2374 /* Scenario numbers for individual Physical Function's */ 2375 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8 2376 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS]; 2377 }; 2378 2379 /* Program ACL profile extraction (indirect 0x0C1D) 2380 * Program ACL profile ranges (indirect 0x0C1E) 2381 * Query ACL profile (indirect 0x0C21) 2382 * Query ACL profile ranges (indirect 0x0C22) 2383 */ 2384 struct ice_aqc_acl_profile { 2385 u8 profile_id; /* Programmed/Updated profile ID */ 2386 u8 reserved[7]; 2387 __le32 addr_high; 2388 __le32 addr_low; 2389 }; 2390 2391 /* Input buffer format for program profile extraction admin command and 2392 * response buffer format for query profile admin command is as defined 2393 * in struct ice_aqc_acl_prof_generic_frmt 2394 */ 2395 2396 /* Input buffer format for program profile ranges and query profile ranges 2397 * admin commands. Same format is used for response buffer in case of query 2398 * profile ranges command 2399 */ 2400 struct ice_acl_rng_data { 2401 /* The range checker output shall be sent when the value 2402 * related to this range checker is lower than low boundary 2403 */ 2404 __be16 low_boundary; 2405 /* The range checker output shall be sent when the value 2406 * related to this range checker is higher than high boundary 2407 */ 2408 __be16 high_boundary; 2409 /* A value of '0' in bit shall clear the relevant bit input 2410 * to the range checker 2411 */ 2412 __be16 mask; 2413 }; 2414 2415 struct ice_aqc_acl_profile_ranges { 2416 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8 2417 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG]; 2418 }; 2419 2420 /* Program ACL entry (indirect 0x0C20) 2421 * Query ACL entry (indirect 0x0C24) 2422 */ 2423 struct ice_aqc_acl_entry { 2424 u8 tcam_index; /* Updated TCAM block index */ 2425 u8 reserved; 2426 __le16 entry_index; /* Updated entry index */ 2427 __le32 reserved2; 2428 __le32 addr_high; 2429 __le32 addr_low; 2430 }; 2431 2432 /* Input buffer format in case of program ACL entry and response buffer format 2433 * in case of query ACL entry 2434 */ 2435 struct ice_aqc_acl_data { 2436 /* Entry key and entry key invert are 40 bits wide. 2437 * Byte 0..4 : entry key and Byte 5..7 are reserved 2438 * Byte 8..12: entry key invert and Byte 13..15 are reserved 2439 */ 2440 struct { 2441 u8 val[5]; 2442 u8 reserved[3]; 2443 } entry_key, entry_key_invert; 2444 }; 2445 2446 /* Query ACL counter (direct 0x0C27) */ 2447 struct ice_aqc_acl_query_counter { 2448 /* Queried counter index */ 2449 __le16 counter_index; 2450 /* Queried counter bank */ 2451 u8 counter_bank; 2452 union { 2453 struct { 2454 u8 reserved[13]; 2455 } cmd; 2456 struct { 2457 /* Holds counter value/packet counter value */ 2458 u8 val[5]; 2459 u8 reserved[8]; 2460 } resp; 2461 } ops; 2462 }; 2463 2464 /* Add Tx LAN Queues (indirect 0x0C30) */ 2465 struct ice_aqc_add_txqs { 2466 u8 num_qgrps; 2467 u8 reserved[3]; 2468 __le32 reserved1; 2469 __le32 addr_high; 2470 __le32 addr_low; 2471 }; 2472 2473 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2474 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2475 */ 2476 struct ice_aqc_add_txqs_perq { 2477 __le16 txq_id; 2478 u8 rsvd[2]; 2479 __le32 q_teid; 2480 u8 txq_ctx[22]; 2481 u8 rsvd2[2]; 2482 struct ice_aqc_txsched_elem info; 2483 }; 2484 2485 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2486 * is an array of the following structs. Please note that the length of 2487 * each struct ice_aqc_add_tx_qgrp is variable due 2488 * to the variable number of queues in each group! 2489 */ 2490 struct ice_aqc_add_tx_qgrp { 2491 __le32 parent_teid; 2492 u8 num_txqs; 2493 u8 rsvd[3]; 2494 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2495 }; 2496 2497 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2498 struct ice_aqc_dis_txqs { 2499 u8 cmd_type; 2500 #define ICE_AQC_Q_DIS_CMD_S 0 2501 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2502 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2503 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2504 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2505 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2506 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2507 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2508 u8 num_entries; 2509 __le16 vmvf_and_timeout; 2510 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2511 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2512 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2513 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2514 __le32 blocked_cgds; 2515 __le32 addr_high; 2516 __le32 addr_low; 2517 }; 2518 2519 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2520 * contains the following structures, arrayed one after the 2521 * other. 2522 * Note: Since the q_id is 16 bits wide, if the 2523 * number of queues is even, then 2 bytes of alignment MUST be 2524 * added before the start of the next group, to allow correct 2525 * alignment of the parent_teid field. 2526 */ 2527 #pragma pack(1) 2528 struct ice_aqc_dis_txq_item { 2529 __le32 parent_teid; 2530 u8 num_qs; 2531 u8 rsvd; 2532 /* The length of the q_id array varies according to num_qs */ 2533 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2534 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2535 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2536 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2537 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2538 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2539 }; 2540 2541 #pragma pack() 2542 2543 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2544 struct ice_aqc_txqs_cleanup { 2545 __le16 caller_opc; 2546 __le16 cmd_tag; 2547 u8 reserved[12]; 2548 }; 2549 2550 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2551 struct ice_aqc_move_txqs { 2552 u8 cmd_type; 2553 #define ICE_AQC_Q_CMD_TYPE_S 0 2554 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2555 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2556 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2557 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2558 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2559 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2560 u8 num_qs; 2561 u8 rsvd; 2562 u8 timeout; 2563 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2564 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2565 __le32 blocked_cgds; 2566 __le32 addr_high; 2567 __le32 addr_low; 2568 }; 2569 2570 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2571 struct ice_aqc_move_txqs_elem { 2572 __le16 txq_id; 2573 u8 q_cgd; 2574 u8 rsvd; 2575 __le32 q_teid; 2576 }; 2577 2578 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2579 struct ice_aqc_move_txqs_data { 2580 __le32 src_teid; 2581 __le32 dest_teid; 2582 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2583 }; 2584 2585 /* Download Package (indirect 0x0C40) */ 2586 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2587 struct ice_aqc_download_pkg { 2588 u8 flags; 2589 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2590 u8 reserved[3]; 2591 __le32 reserved1; 2592 __le32 addr_high; 2593 __le32 addr_low; 2594 }; 2595 2596 struct ice_aqc_download_pkg_resp { 2597 __le32 error_offset; 2598 __le32 error_info; 2599 __le32 addr_high; 2600 __le32 addr_low; 2601 }; 2602 2603 /* Get Package Info List (indirect 0x0C43) */ 2604 struct ice_aqc_get_pkg_info_list { 2605 __le32 reserved1; 2606 __le32 reserved2; 2607 __le32 addr_high; 2608 __le32 addr_low; 2609 }; 2610 2611 /* Version format for packages */ 2612 struct ice_pkg_ver { 2613 u8 major; 2614 u8 minor; 2615 u8 update; 2616 u8 draft; 2617 }; 2618 2619 #define ICE_PKG_NAME_SIZE 32 2620 #define ICE_SEG_ID_SIZE 28 2621 #define ICE_SEG_NAME_SIZE 28 2622 2623 struct ice_aqc_get_pkg_info { 2624 struct ice_pkg_ver ver; 2625 char name[ICE_SEG_NAME_SIZE]; 2626 __le32 track_id; 2627 u8 is_in_nvm; 2628 u8 is_active; 2629 u8 is_active_at_boot; 2630 u8 is_modified; 2631 }; 2632 2633 /* Get Package Info List response buffer format (0x0C43) */ 2634 struct ice_aqc_get_pkg_info_resp { 2635 __le32 count; 2636 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2637 }; 2638 2639 /* Driver Shared Parameters (direct, 0x0C90) */ 2640 struct ice_aqc_driver_shared_params { 2641 u8 set_or_get_op; 2642 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2643 #define ICE_AQC_DRIVER_PARAM_SET 0 2644 #define ICE_AQC_DRIVER_PARAM_GET 1 2645 u8 param_indx; 2646 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2647 u8 rsvd[2]; 2648 __le32 param_val; 2649 __le32 addr_high; 2650 __le32 addr_low; 2651 }; 2652 2653 /* Lan Queue Overflow Event (direct, 0x1001) */ 2654 struct ice_aqc_event_lan_overflow { 2655 __le32 prtdcb_ruptq; 2656 __le32 qtx_ctl; 2657 u8 reserved[8]; 2658 }; 2659 2660 /* Set Health Status (direct 0xFF20) */ 2661 struct ice_aqc_set_health_status_config { 2662 u8 event_source; 2663 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2664 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2665 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2666 u8 reserved[15]; 2667 }; 2668 2669 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2670 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2671 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2672 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2673 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2674 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2675 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2676 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2677 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2678 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2679 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2680 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2681 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2682 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2683 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2684 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2685 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2686 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2687 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2688 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2689 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2690 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2691 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2692 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2693 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2694 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2695 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2696 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2697 2698 /* Get Health Status codes (indirect 0xFF21) */ 2699 struct ice_aqc_get_supported_health_status_codes { 2700 __le16 health_code_count; 2701 u8 reserved[6]; 2702 __le32 addr_high; 2703 __le32 addr_low; 2704 }; 2705 2706 /* Get Health Status (indirect 0xFF22) */ 2707 struct ice_aqc_get_health_status { 2708 __le16 health_status_count; 2709 u8 reserved[6]; 2710 __le32 addr_high; 2711 __le32 addr_low; 2712 }; 2713 2714 /* Get Health Status event buffer entry, (0xFF22) 2715 * repeated per reported health status 2716 */ 2717 struct ice_aqc_health_status_elem { 2718 __le16 health_status_code; 2719 __le16 event_source; 2720 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2721 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2722 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2723 __le32 internal_data1; 2724 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2725 __le32 internal_data2; 2726 }; 2727 2728 /* Clear Health Status (direct 0xFF23) */ 2729 struct ice_aqc_clear_health_status { 2730 __le32 reserved[4]; 2731 }; 2732 2733 /** 2734 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2735 * @flags: ICE_AQ_FLAG_* flags 2736 * @opcode: AQ command opcode 2737 * @datalen: length in bytes of indirect/external data buffer 2738 * @retval: return value from firmware 2739 * @cookie_high: opaque data high-half 2740 * @cookie_low: opaque data low-half 2741 * @params: command-specific parameters 2742 * 2743 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2744 * (ATQ). The firmware writes back onto the command descriptor and returns 2745 * the result of the command. Asynchronous events that are not an immediate 2746 * result of the command are written to the Admin Receive Queue (ARQ) using 2747 * the same descriptor format. Descriptors are in little-endian notation with 2748 * 32-bit words. 2749 */ 2750 struct ice_aq_desc { 2751 __le16 flags; 2752 __le16 opcode; 2753 __le16 datalen; 2754 __le16 retval; 2755 __le32 cookie_high; 2756 __le32 cookie_low; 2757 union { 2758 u8 raw[16]; 2759 struct ice_aqc_generic generic; 2760 struct ice_aqc_get_ver get_ver; 2761 struct ice_aqc_driver_ver driver_ver; 2762 struct ice_aqc_q_shutdown q_shutdown; 2763 struct ice_aqc_req_res res_owner; 2764 struct ice_aqc_manage_mac_read mac_read; 2765 struct ice_aqc_manage_mac_write mac_write; 2766 struct ice_aqc_clear_pxe clear_pxe; 2767 struct ice_aqc_config_no_drop_policy no_drop; 2768 struct ice_aqc_add_update_mir_rule add_update_rule; 2769 struct ice_aqc_delete_mir_rule del_rule; 2770 struct ice_aqc_list_caps get_cap; 2771 struct ice_aqc_get_phy_caps get_phy; 2772 struct ice_aqc_set_phy_cfg set_phy; 2773 struct ice_aqc_restart_an restart_an; 2774 struct ice_aqc_sff_eeprom read_write_sff_param; 2775 struct ice_aqc_set_port_id_led set_port_id_led; 2776 struct ice_aqc_get_sw_cfg get_sw_conf; 2777 struct ice_aqc_set_port_params set_port_params; 2778 struct ice_aqc_sw_rules sw_rules; 2779 struct ice_aqc_storm_cfg storm_conf; 2780 struct ice_aqc_add_get_recipe add_get_recipe; 2781 struct ice_aqc_recipe_to_profile recipe_to_profile; 2782 struct ice_aqc_get_topo get_topo; 2783 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2784 struct ice_aqc_query_txsched_res query_sched_res; 2785 struct ice_aqc_query_node_to_root query_node_to_root; 2786 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2787 struct ice_aqc_query_port_ets port_ets; 2788 struct ice_aqc_rl_profile rl_profile; 2789 struct ice_aqc_nvm nvm; 2790 struct ice_aqc_nvm_cfg nvm_cfg; 2791 struct ice_aqc_nvm_checksum nvm_checksum; 2792 struct ice_aqc_pfc_ignore pfc_ignore; 2793 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2794 struct ice_aqc_set_dcb_params set_dcb_params; 2795 struct ice_aqc_lldp_get_mib lldp_get_mib; 2796 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2797 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2798 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2799 struct ice_aqc_lldp_stop lldp_stop; 2800 struct ice_aqc_lldp_start lldp_start; 2801 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2802 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2803 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2804 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2805 struct ice_aqc_get_set_rss_key get_set_rss_key; 2806 struct ice_aqc_clear_fd_table clear_fd_table; 2807 struct ice_aqc_acl_alloc_table alloc_table; 2808 struct ice_aqc_acl_tbl_actpair tbl_actpair; 2809 struct ice_aqc_acl_alloc_scen alloc_scen; 2810 struct ice_aqc_acl_dealloc_scen dealloc_scen; 2811 struct ice_aqc_acl_update_query_scen update_query_scen; 2812 struct ice_aqc_acl_alloc_counters alloc_counters; 2813 struct ice_aqc_acl_dealloc_counters dealloc_counters; 2814 struct ice_aqc_acl_dealloc_res dealloc_res; 2815 struct ice_aqc_acl_entry program_query_entry; 2816 struct ice_aqc_acl_actpair program_query_actpair; 2817 struct ice_aqc_acl_profile profile; 2818 struct ice_aqc_acl_query_counter query_counter; 2819 struct ice_aqc_add_txqs add_txqs; 2820 struct ice_aqc_dis_txqs dis_txqs; 2821 struct ice_aqc_move_txqs move_txqs; 2822 struct ice_aqc_txqs_cleanup txqs_cleanup; 2823 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2824 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2825 struct ice_aqc_get_vsi_resp get_vsi_resp; 2826 struct ice_aqc_download_pkg download_pkg; 2827 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2828 struct ice_aqc_driver_shared_params drv_shared_params; 2829 struct ice_aqc_set_mac_lb set_mac_lb; 2830 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2831 struct ice_aqc_get_res_alloc get_res; 2832 struct ice_aqc_get_allocd_res_desc get_res_desc; 2833 struct ice_aqc_set_mac_cfg set_mac_cfg; 2834 struct ice_aqc_set_event_mask set_event_mask; 2835 struct ice_aqc_get_link_status get_link_status; 2836 struct ice_aqc_event_lan_overflow lan_overflow; 2837 struct ice_aqc_get_link_topo get_link_topo; 2838 struct ice_aqc_set_health_status_config 2839 set_health_status_config; 2840 struct ice_aqc_get_supported_health_status_codes 2841 get_supported_health_status_codes; 2842 struct ice_aqc_get_health_status get_health_status; 2843 struct ice_aqc_clear_health_status clear_health_status; 2844 } params; 2845 }; 2846 2847 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2848 #define ICE_AQ_LG_BUF 512 2849 2850 /* Flags sub-structure 2851 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2852 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2853 */ 2854 2855 /* command flags and offsets */ 2856 #define ICE_AQ_FLAG_DD_S 0 2857 #define ICE_AQ_FLAG_CMP_S 1 2858 #define ICE_AQ_FLAG_ERR_S 2 2859 #define ICE_AQ_FLAG_VFE_S 3 2860 #define ICE_AQ_FLAG_LB_S 9 2861 #define ICE_AQ_FLAG_RD_S 10 2862 #define ICE_AQ_FLAG_VFC_S 11 2863 #define ICE_AQ_FLAG_BUF_S 12 2864 #define ICE_AQ_FLAG_SI_S 13 2865 #define ICE_AQ_FLAG_EI_S 14 2866 #define ICE_AQ_FLAG_FE_S 15 2867 2868 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2869 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2870 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2871 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2872 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2873 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2874 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2875 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2876 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2877 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2878 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2879 2880 /* error codes */ 2881 enum ice_aq_err { 2882 ICE_AQ_RC_OK = 0, /* Success */ 2883 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2884 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2885 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2886 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2887 ICE_AQ_RC_EIO = 5, /* I/O error */ 2888 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2889 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2890 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2891 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2892 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2893 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2894 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2895 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2896 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2897 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2898 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2899 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2900 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2901 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2902 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2903 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2904 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2905 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2906 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2907 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2908 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2909 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2910 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2911 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2912 }; 2913 2914 /* Admin Queue command opcodes */ 2915 enum ice_adminq_opc { 2916 /* AQ commands */ 2917 ice_aqc_opc_get_ver = 0x0001, 2918 ice_aqc_opc_driver_ver = 0x0002, 2919 ice_aqc_opc_q_shutdown = 0x0003, 2920 ice_aqc_opc_get_exp_err = 0x0005, 2921 2922 /* resource ownership */ 2923 ice_aqc_opc_req_res = 0x0008, 2924 ice_aqc_opc_release_res = 0x0009, 2925 2926 /* device/function capabilities */ 2927 ice_aqc_opc_list_func_caps = 0x000A, 2928 ice_aqc_opc_list_dev_caps = 0x000B, 2929 2930 /* manage MAC address */ 2931 ice_aqc_opc_manage_mac_read = 0x0107, 2932 ice_aqc_opc_manage_mac_write = 0x0108, 2933 2934 /* PXE */ 2935 ice_aqc_opc_clear_pxe_mode = 0x0110, 2936 2937 ice_aqc_opc_config_no_drop_policy = 0x0112, 2938 2939 /* internal switch commands */ 2940 ice_aqc_opc_get_sw_cfg = 0x0200, 2941 ice_aqc_opc_set_port_params = 0x0203, 2942 2943 /* Alloc/Free/Get Resources */ 2944 ice_aqc_opc_get_res_alloc = 0x0204, 2945 ice_aqc_opc_alloc_res = 0x0208, 2946 ice_aqc_opc_free_res = 0x0209, 2947 ice_aqc_opc_get_allocd_res_desc = 0x020A, 2948 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2949 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 2950 2951 /* VSI commands */ 2952 ice_aqc_opc_add_vsi = 0x0210, 2953 ice_aqc_opc_update_vsi = 0x0211, 2954 ice_aqc_opc_get_vsi_params = 0x0212, 2955 ice_aqc_opc_free_vsi = 0x0213, 2956 2957 /* Mirroring rules - add/update, delete */ 2958 ice_aqc_opc_add_update_mir_rule = 0x0260, 2959 ice_aqc_opc_del_mir_rule = 0x0261, 2960 2961 /* storm configuration */ 2962 ice_aqc_opc_set_storm_cfg = 0x0280, 2963 ice_aqc_opc_get_storm_cfg = 0x0281, 2964 2965 /* recipe commands */ 2966 ice_aqc_opc_add_recipe = 0x0290, 2967 ice_aqc_opc_recipe_to_profile = 0x0291, 2968 ice_aqc_opc_get_recipe = 0x0292, 2969 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2970 2971 /* switch rules population commands */ 2972 ice_aqc_opc_add_sw_rules = 0x02A0, 2973 ice_aqc_opc_update_sw_rules = 0x02A1, 2974 ice_aqc_opc_remove_sw_rules = 0x02A2, 2975 ice_aqc_opc_get_sw_rules = 0x02A3, 2976 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2977 2978 /* DCB commands */ 2979 ice_aqc_opc_pfc_ignore = 0x0301, 2980 ice_aqc_opc_query_pfc_mode = 0x0302, 2981 ice_aqc_opc_set_pfc_mode = 0x0303, 2982 ice_aqc_opc_set_dcb_params = 0x0306, 2983 2984 /* transmit scheduler commands */ 2985 ice_aqc_opc_get_dflt_topo = 0x0400, 2986 ice_aqc_opc_add_sched_elems = 0x0401, 2987 ice_aqc_opc_cfg_sched_elems = 0x0403, 2988 ice_aqc_opc_get_sched_elems = 0x0404, 2989 ice_aqc_opc_move_sched_elems = 0x0408, 2990 ice_aqc_opc_suspend_sched_elems = 0x0409, 2991 ice_aqc_opc_resume_sched_elems = 0x040A, 2992 ice_aqc_opc_query_port_ets = 0x040E, 2993 ice_aqc_opc_delete_sched_elems = 0x040F, 2994 ice_aqc_opc_add_rl_profiles = 0x0410, 2995 ice_aqc_opc_query_rl_profiles = 0x0411, 2996 ice_aqc_opc_query_sched_res = 0x0412, 2997 ice_aqc_opc_query_node_to_root = 0x0413, 2998 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 2999 ice_aqc_opc_remove_rl_profiles = 0x0415, 3000 3001 /* PHY commands */ 3002 ice_aqc_opc_get_phy_caps = 0x0600, 3003 ice_aqc_opc_set_phy_cfg = 0x0601, 3004 ice_aqc_opc_set_mac_cfg = 0x0603, 3005 ice_aqc_opc_restart_an = 0x0605, 3006 ice_aqc_opc_get_link_status = 0x0607, 3007 ice_aqc_opc_set_event_mask = 0x0613, 3008 ice_aqc_opc_set_mac_lb = 0x0620, 3009 ice_aqc_opc_get_link_topo = 0x06E0, 3010 ice_aqc_opc_set_port_id_led = 0x06E9, 3011 ice_aqc_opc_get_port_options = 0x06EA, 3012 ice_aqc_opc_set_port_option = 0x06EB, 3013 ice_aqc_opc_set_gpio = 0x06EC, 3014 ice_aqc_opc_get_gpio = 0x06ED, 3015 ice_aqc_opc_sff_eeprom = 0x06EE, 3016 ice_aqc_opc_sw_set_gpio = 0x06EF, 3017 ice_aqc_opc_sw_get_gpio = 0x06F0, 3018 3019 /* NVM commands */ 3020 ice_aqc_opc_nvm_read = 0x0701, 3021 ice_aqc_opc_nvm_erase = 0x0702, 3022 ice_aqc_opc_nvm_write = 0x0703, 3023 ice_aqc_opc_nvm_cfg_read = 0x0704, 3024 ice_aqc_opc_nvm_cfg_write = 0x0705, 3025 ice_aqc_opc_nvm_checksum = 0x0706, 3026 ice_aqc_opc_nvm_write_activate = 0x0707, 3027 ice_aqc_opc_nvm_sr_dump = 0x0707, 3028 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 3029 ice_aqc_opc_nvm_update_empr = 0x0709, 3030 3031 /* LLDP commands */ 3032 ice_aqc_opc_lldp_get_mib = 0x0A00, 3033 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 3034 ice_aqc_opc_lldp_add_tlv = 0x0A02, 3035 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3036 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3037 ice_aqc_opc_lldp_stop = 0x0A05, 3038 ice_aqc_opc_lldp_start = 0x0A06, 3039 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3040 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3041 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3042 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3043 3044 /* RSS commands */ 3045 ice_aqc_opc_set_rss_key = 0x0B02, 3046 ice_aqc_opc_set_rss_lut = 0x0B03, 3047 ice_aqc_opc_get_rss_key = 0x0B04, 3048 ice_aqc_opc_get_rss_lut = 0x0B05, 3049 ice_aqc_opc_clear_fd_table = 0x0B06, 3050 /* ACL commands */ 3051 ice_aqc_opc_alloc_acl_tbl = 0x0C10, 3052 ice_aqc_opc_dealloc_acl_tbl = 0x0C11, 3053 ice_aqc_opc_alloc_acl_actpair = 0x0C12, 3054 ice_aqc_opc_dealloc_acl_actpair = 0x0C13, 3055 ice_aqc_opc_alloc_acl_scen = 0x0C14, 3056 ice_aqc_opc_dealloc_acl_scen = 0x0C15, 3057 ice_aqc_opc_alloc_acl_counters = 0x0C16, 3058 ice_aqc_opc_dealloc_acl_counters = 0x0C17, 3059 ice_aqc_opc_dealloc_acl_res = 0x0C1A, 3060 ice_aqc_opc_update_acl_scen = 0x0C1B, 3061 ice_aqc_opc_program_acl_actpair = 0x0C1C, 3062 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D, 3063 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E, 3064 ice_aqc_opc_program_acl_entry = 0x0C20, 3065 ice_aqc_opc_query_acl_prof = 0x0C21, 3066 ice_aqc_opc_query_acl_prof_ranges = 0x0C22, 3067 ice_aqc_opc_query_acl_scen = 0x0C23, 3068 ice_aqc_opc_query_acl_entry = 0x0C24, 3069 ice_aqc_opc_query_acl_actpair = 0x0C25, 3070 ice_aqc_opc_query_acl_counter = 0x0C27, 3071 3072 /* Tx queue handling commands/events */ 3073 ice_aqc_opc_add_txqs = 0x0C30, 3074 ice_aqc_opc_dis_txqs = 0x0C31, 3075 ice_aqc_opc_txqs_cleanup = 0x0C31, 3076 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3077 3078 /* package commands */ 3079 ice_aqc_opc_download_pkg = 0x0C40, 3080 ice_aqc_opc_upload_section = 0x0C41, 3081 ice_aqc_opc_update_pkg = 0x0C42, 3082 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3083 3084 ice_aqc_opc_driver_shared_params = 0x0C90, 3085 3086 /* Standalone Commands/Events */ 3087 ice_aqc_opc_event_lan_overflow = 0x1001, 3088 3089 /* SystemDiagnostic commands */ 3090 ice_aqc_opc_set_health_status_config = 0xFF20, 3091 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3092 ice_aqc_opc_get_health_status = 0xFF22, 3093 ice_aqc_opc_clear_health_status = 0xFF23 3094 }; 3095 3096 #endif /* _ICE_ADMINQ_CMD_H_ */ 3097