1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2018 3 */ 4 5 #ifndef _ICE_ADMINQ_CMD_H_ 6 #define _ICE_ADMINQ_CMD_H_ 7 8 /* This header file defines the Admin Queue commands, error codes and 9 * descriptor format. It is shared between Firmware and Software. 10 */ 11 12 13 #define ICE_MAX_VSI 768 14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 16 17 18 struct ice_aqc_generic { 19 __le32 param0; 20 __le32 param1; 21 __le32 addr_high; 22 __le32 addr_low; 23 }; 24 25 26 /* Get version (direct 0x0001) */ 27 struct ice_aqc_get_ver { 28 __le32 rom_ver; 29 __le32 fw_build; 30 u8 fw_branch; 31 u8 fw_major; 32 u8 fw_minor; 33 u8 fw_patch; 34 u8 api_branch; 35 u8 api_major; 36 u8 api_minor; 37 u8 api_patch; 38 }; 39 40 41 42 /* Queue Shutdown (direct 0x0003) */ 43 struct ice_aqc_q_shutdown { 44 __le32 driver_unloading; 45 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 46 u8 reserved[12]; 47 }; 48 49 50 51 52 /* Request resource ownership (direct 0x0008) 53 * Release resource ownership (direct 0x0009) 54 */ 55 struct ice_aqc_req_res { 56 __le16 res_id; 57 #define ICE_AQC_RES_ID_NVM 1 58 #define ICE_AQC_RES_ID_SDP 2 59 #define ICE_AQC_RES_ID_CHNG_LOCK 3 60 #define ICE_AQC_RES_ID_GLBL_LOCK 4 61 __le16 access_type; 62 #define ICE_AQC_RES_ACCESS_READ 1 63 #define ICE_AQC_RES_ACCESS_WRITE 2 64 65 /* Upon successful completion, FW writes this value and driver is 66 * expected to release resource before timeout. This value is provided 67 * in milliseconds. 68 */ 69 __le32 timeout; 70 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 71 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 72 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 73 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 74 /* For SDP: pin id of the SDP */ 75 __le32 res_number; 76 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 77 __le16 status; 78 #define ICE_AQ_RES_GLBL_SUCCESS 0 79 #define ICE_AQ_RES_GLBL_IN_PROG 1 80 #define ICE_AQ_RES_GLBL_DONE 2 81 u8 reserved[2]; 82 }; 83 84 85 /* Get function capabilities (indirect 0x000A) 86 * Get device capabilities (indirect 0x000B) 87 */ 88 struct ice_aqc_list_caps { 89 u8 cmd_flags; 90 u8 pf_index; 91 u8 reserved[2]; 92 __le32 count; 93 __le32 addr_high; 94 __le32 addr_low; 95 }; 96 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_VSI 0x0017 103 #define ICE_AQC_CAPS_RSS 0x0040 104 #define ICE_AQC_CAPS_RXQS 0x0041 105 #define ICE_AQC_CAPS_TXQS 0x0042 106 #define ICE_AQC_CAPS_MSIX 0x0043 107 #define ICE_AQC_CAPS_MAX_MTU 0x0047 108 109 u8 major_ver; 110 u8 minor_ver; 111 /* Number of resources described by this capability */ 112 __le32 number; 113 /* Only meaningful for some types of resources */ 114 __le32 logical_id; 115 /* Only meaningful for some types of resources */ 116 __le32 phys_id; 117 __le64 rsvd1; 118 __le64 rsvd2; 119 }; 120 121 122 /* Manage MAC address, read command - indirect (0x0107) 123 * This struct is also used for the response 124 */ 125 struct ice_aqc_manage_mac_read { 126 __le16 flags; /* Zeroed by device driver */ 127 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 128 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 129 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 130 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 131 #define ICE_AQC_MAN_MAC_READ_S 4 132 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 133 u8 lport_num; 134 u8 lport_num_valid; 135 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0) 136 u8 num_addr; /* Used in response */ 137 u8 reserved[3]; 138 __le32 addr_high; 139 __le32 addr_low; 140 }; 141 142 143 /* Response buffer format for manage MAC read command */ 144 struct ice_aqc_manage_mac_read_resp { 145 u8 lport_num; 146 u8 addr_type; 147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 149 u8 mac_addr[ETH_ALEN]; 150 }; 151 152 153 /* Manage MAC address, write command - direct (0x0108) */ 154 struct ice_aqc_manage_mac_write { 155 u8 port_num; 156 u8 flags; 157 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 158 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 159 #define ICE_AQC_MAN_MAC_WR_S 6 160 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 161 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 162 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 163 /* High 16 bits of MAC address in big endian order */ 164 __be16 sah; 165 /* Low 32 bits of MAC address in big endian order */ 166 __be32 sal; 167 __le32 addr_high; 168 __le32 addr_low; 169 }; 170 171 172 /* Clear PXE Command and response (direct 0x0110) */ 173 struct ice_aqc_clear_pxe { 174 u8 rx_cnt; 175 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 176 u8 reserved[15]; 177 }; 178 179 180 /* Get switch configuration (0x0200) */ 181 struct ice_aqc_get_sw_cfg { 182 /* Reserved for command and copy of request flags for response */ 183 __le16 flags; 184 /* First desc in case of command and next_elem in case of response 185 * In case of response, if it is not zero, means all the configuration 186 * was not returned and new command shall be sent with this value in 187 * the 'first desc' field 188 */ 189 __le16 element; 190 /* Reserved for command, only used for response */ 191 __le16 num_elems; 192 __le16 rsvd; 193 __le32 addr_high; 194 __le32 addr_low; 195 }; 196 197 198 /* Each entry in the response buffer is of the following type: */ 199 struct ice_aqc_get_sw_cfg_resp_elem { 200 /* VSI/Port Number */ 201 __le16 vsi_port_num; 202 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 203 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 204 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 205 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 206 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 207 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 208 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 209 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 210 211 /* SWID VSI/Port belongs to */ 212 __le16 swid; 213 214 /* Bit 14..0 : PF/VF number VSI belongs to 215 * Bit 15 : VF indication bit 216 */ 217 __le16 pf_vf_num; 218 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 219 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 220 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 221 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 222 }; 223 224 225 /* The response buffer is as follows. Note that the length of the 226 * elements array varies with the length of the command response. 227 */ 228 struct ice_aqc_get_sw_cfg_resp { 229 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 230 }; 231 232 233 234 /* These resource type defines are used for all switch resource 235 * commands where a resource type is required, such as: 236 * Get Resource Allocation command (indirect 0x0204) 237 * Allocate Resources command (indirect 0x0208) 238 * Free Resources command (indirect 0x0209) 239 * Get Allocated Resource Descriptors Command (indirect 0x020A) 240 */ 241 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 242 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 243 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 244 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 245 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 246 #define ICE_AQC_RES_TYPE_RECIPE 0x05 247 #define ICE_AQC_RES_TYPE_PROFILE 0x06 248 #define ICE_AQC_RES_TYPE_SWID 0x07 249 #define ICE_AQC_RES_TYPE_VSI 0x08 250 #define ICE_AQC_RES_TYPE_FLU 0x09 251 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 252 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 253 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 254 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 255 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 256 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 257 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 258 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 259 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 260 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 261 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 262 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 263 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 264 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 265 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 266 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 267 /* Resource types 0x62-67 are reserved for Hash profile builder */ 268 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 269 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 270 271 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 272 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 273 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 274 275 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 276 277 278 279 /* Allocate Resources command (indirect 0x0208) 280 * Free Resources command (indirect 0x0209) 281 */ 282 struct ice_aqc_alloc_free_res_cmd { 283 __le16 num_entries; /* Number of Resource entries */ 284 u8 reserved[6]; 285 __le32 addr_high; 286 __le32 addr_low; 287 }; 288 289 290 /* Resource descriptor */ 291 struct ice_aqc_res_elem { 292 union { 293 __le16 sw_resp; 294 __le16 flu_resp; 295 } e; 296 }; 297 298 299 /* Buffer for Allocate/Free Resources commands */ 300 struct ice_aqc_alloc_free_res_elem { 301 __le16 res_type; /* Types defined above cmd 0x0204 */ 302 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 303 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 304 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 305 __le16 num_elems; 306 struct ice_aqc_res_elem elem[1]; 307 }; 308 309 310 311 312 /* Add VSI (indirect 0x0210) 313 * Update VSI (indirect 0x0211) 314 * Get VSI (indirect 0x0212) 315 * Free VSI (indirect 0x0213) 316 */ 317 struct ice_aqc_add_get_update_free_vsi { 318 __le16 vsi_num; 319 #define ICE_AQ_VSI_NUM_S 0 320 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 321 #define ICE_AQ_VSI_IS_VALID BIT(15) 322 __le16 cmd_flags; 323 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 324 u8 vf_id; 325 u8 reserved; 326 __le16 vsi_flags; 327 #define ICE_AQ_VSI_TYPE_S 0 328 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 329 #define ICE_AQ_VSI_TYPE_VF 0x0 330 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 331 #define ICE_AQ_VSI_TYPE_PF 0x2 332 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 333 __le32 addr_high; 334 __le32 addr_low; 335 }; 336 337 338 /* Response descriptor for: 339 * Add VSI (indirect 0x0210) 340 * Update VSI (indirect 0x0211) 341 * Free VSI (indirect 0x0213) 342 */ 343 struct ice_aqc_add_update_free_vsi_resp { 344 __le16 vsi_num; 345 __le16 ext_status; 346 __le16 vsi_used; 347 __le16 vsi_free; 348 __le32 addr_high; 349 __le32 addr_low; 350 }; 351 352 353 354 struct ice_aqc_vsi_props { 355 __le16 valid_sections; 356 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 357 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 358 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 359 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 360 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 361 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 362 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 363 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 364 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 365 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 366 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 367 /* switch section */ 368 u8 sw_id; 369 u8 sw_flags; 370 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 371 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 372 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 373 u8 sw_flags2; 374 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 375 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 376 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 377 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 378 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 379 u8 veb_stat_id; 380 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 381 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 382 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 383 /* security section */ 384 u8 sec_flags; 385 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 386 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 387 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 388 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 389 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 390 u8 sec_reserved; 391 /* VLAN section */ 392 __le16 pvid; /* VLANS include priority bits */ 393 u8 pvlan_reserved[2]; 394 u8 vlan_flags; 395 #define ICE_AQ_VSI_VLAN_MODE_S 0 396 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 397 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 398 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 399 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 400 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 401 #define ICE_AQ_VSI_VLAN_EMOD_S 3 402 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 403 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 404 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 405 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 406 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 407 u8 pvlan_reserved2[3]; 408 /* ingress egress up sections */ 409 __le32 ingress_table; /* bitmap, 3 bits per up */ 410 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 411 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 412 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 413 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 414 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 415 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 416 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 417 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 418 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 419 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 420 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 421 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 422 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 423 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 424 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 425 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 426 __le32 egress_table; /* same defines as for ingress table */ 427 /* outer tags section */ 428 __le16 outer_tag; 429 u8 outer_tag_flags; 430 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 431 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 432 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 433 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 434 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 435 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 436 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 437 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 438 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 439 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 440 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 441 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 442 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 443 u8 outer_tag_reserved; 444 /* queue mapping section */ 445 __le16 mapping_flags; 446 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 447 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 448 __le16 q_mapping[16]; 449 #define ICE_AQ_VSI_Q_S 0 450 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 451 __le16 tc_mapping[8]; 452 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 453 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 454 #define ICE_AQ_VSI_TC_Q_NUM_S 11 455 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 456 /* queueing option section */ 457 u8 q_opt_rss; 458 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 459 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 460 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 461 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 462 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 463 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 464 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 465 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 466 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 467 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 468 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 469 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 470 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 471 u8 q_opt_tc; 472 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 473 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 474 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 475 u8 q_opt_flags; 476 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 477 u8 q_opt_reserved[3]; 478 /* outer up section */ 479 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 480 /* section 10 */ 481 __le16 sect_10_reserved; 482 /* flow director section */ 483 __le16 fd_options; 484 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 485 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 486 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 487 __le16 max_fd_fltr_dedicated; 488 __le16 max_fd_fltr_shared; 489 __le16 fd_def_q; 490 #define ICE_AQ_VSI_FD_DEF_Q_S 0 491 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 492 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 493 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 494 __le16 fd_report_opt; 495 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 496 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 497 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 498 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 499 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 500 /* PASID section */ 501 __le32 pasid_id; 502 #define ICE_AQ_VSI_PASID_ID_S 0 503 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 504 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 505 u8 reserved[24]; 506 }; 507 508 509 510 #define ICE_MAX_NUM_RECIPES 64 511 512 513 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 514 */ 515 struct ice_aqc_sw_rules { 516 /* ops: add switch rules, referring the number of rules. 517 * ops: update switch rules, referring the number of filters 518 * ops: remove switch rules, referring the entry index. 519 * ops: get switch rules, referring to the number of filters. 520 */ 521 __le16 num_rules_fltr_entry_index; 522 u8 reserved[6]; 523 __le32 addr_high; 524 __le32 addr_low; 525 }; 526 527 528 #pragma pack(1) 529 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 530 * This structures describes the lookup rules and associated actions. "index" 531 * is returned as part of a response to a successful Add command, and can be 532 * used to identify the rule for Update/Get/Remove commands. 533 */ 534 struct ice_sw_rule_lkup_rx_tx { 535 __le16 recipe_id; 536 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 537 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 538 __le16 src; 539 __le32 act; 540 541 /* Bit 0:1 - Action type */ 542 #define ICE_SINGLE_ACT_TYPE_S 0x00 543 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 544 545 /* Bit 2 - Loop back enable 546 * Bit 3 - LAN enable 547 */ 548 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 549 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 550 551 /* Action type = 0 - Forward to VSI or VSI list */ 552 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 553 554 #define ICE_SINGLE_ACT_VSI_ID_S 4 555 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 556 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 557 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 558 /* This bit needs to be set if action is forward to VSI list */ 559 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 560 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 561 #define ICE_SINGLE_ACT_DROP BIT(18) 562 563 /* Action type = 1 - Forward to Queue of Queue group */ 564 #define ICE_SINGLE_ACT_TO_Q 0x1 565 #define ICE_SINGLE_ACT_Q_INDEX_S 4 566 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 567 #define ICE_SINGLE_ACT_Q_REGION_S 15 568 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 569 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 570 571 /* Action type = 2 - Prune */ 572 #define ICE_SINGLE_ACT_PRUNE 0x2 573 #define ICE_SINGLE_ACT_EGRESS BIT(15) 574 #define ICE_SINGLE_ACT_INGRESS BIT(16) 575 #define ICE_SINGLE_ACT_PRUNET BIT(17) 576 /* Bit 18 should be set to 0 for this action */ 577 578 /* Action type = 2 - Pointer */ 579 #define ICE_SINGLE_ACT_PTR 0x2 580 #define ICE_SINGLE_ACT_PTR_VAL_S 4 581 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 582 /* Bit 18 should be set to 1 */ 583 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 584 585 /* Action type = 3 - Other actions. Last two bits 586 * are other action identifier 587 */ 588 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 589 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 590 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 591 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 592 593 /* Bit 17:18 - Defines other actions */ 594 /* Other action = 0 - Mirror VSI */ 595 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 596 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 597 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 598 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 599 600 /* Other action = 3 - Set Stat count */ 601 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 602 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 603 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 604 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 605 606 __le16 index; /* The index of the rule in the lookup table */ 607 /* Length and values of the header to be matched per recipe or 608 * lookup-type 609 */ 610 __le16 hdr_len; 611 u8 hdr[1]; 612 }; 613 #pragma pack() 614 615 616 /* Add/Update/Remove large action command/response entry 617 * "index" is returned as part of a response to a successful Add command, and 618 * can be used to identify the action for Update/Get/Remove commands. 619 */ 620 struct ice_sw_rule_lg_act { 621 __le16 index; /* Index in large action table */ 622 __le16 size; 623 __le32 act[1]; /* array of size for actions */ 624 /* Max number of large actions */ 625 #define ICE_MAX_LG_ACT 4 626 /* Bit 0:1 - Action type */ 627 #define ICE_LG_ACT_TYPE_S 0 628 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 629 630 /* Action type = 0 - Forward to VSI or VSI list */ 631 #define ICE_LG_ACT_VSI_FORWARDING 0 632 #define ICE_LG_ACT_VSI_ID_S 3 633 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 634 #define ICE_LG_ACT_VSI_LIST_ID_S 3 635 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 636 /* This bit needs to be set if action is forward to VSI list */ 637 #define ICE_LG_ACT_VSI_LIST BIT(13) 638 639 #define ICE_LG_ACT_VALID_BIT BIT(16) 640 641 /* Action type = 1 - Forward to Queue of Queue group */ 642 #define ICE_LG_ACT_TO_Q 0x1 643 #define ICE_LG_ACT_Q_INDEX_S 3 644 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 645 #define ICE_LG_ACT_Q_REGION_S 14 646 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 647 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 648 649 /* Action type = 2 - Prune */ 650 #define ICE_LG_ACT_PRUNE 0x2 651 #define ICE_LG_ACT_EGRESS BIT(14) 652 #define ICE_LG_ACT_INGRESS BIT(15) 653 #define ICE_LG_ACT_PRUNET BIT(16) 654 655 /* Action type = 3 - Mirror VSI */ 656 #define ICE_LG_OTHER_ACT_MIRROR 0x3 657 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 658 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 659 660 /* Action type = 5 - Generic Value */ 661 #define ICE_LG_ACT_GENERIC 0x5 662 #define ICE_LG_ACT_GENERIC_VALUE_S 3 663 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 664 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 665 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 666 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 667 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 668 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 669 670 /* Action = 7 - Set Stat count */ 671 #define ICE_LG_ACT_STAT_COUNT 0x7 672 #define ICE_LG_ACT_STAT_COUNT_S 3 673 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 674 }; 675 676 677 /* Add/Update/Remove VSI list command/response entry 678 * "index" is returned as part of a response to a successful Add command, and 679 * can be used to identify the VSI list for Update/Get/Remove commands. 680 */ 681 struct ice_sw_rule_vsi_list { 682 __le16 index; /* Index of VSI/Prune list */ 683 __le16 number_vsi; 684 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 685 }; 686 687 688 #pragma pack(1) 689 /* Query VSI list command/response entry */ 690 struct ice_sw_rule_vsi_list_query { 691 __le16 index; 692 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 693 }; 694 #pragma pack() 695 696 697 #pragma pack(1) 698 /* Add switch rule response: 699 * Content of return buffer is same as the input buffer. The status field and 700 * LUT index are updated as part of the response 701 */ 702 struct ice_aqc_sw_rules_elem { 703 __le16 type; /* Switch rule type, one of T_... */ 704 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 705 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 706 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 707 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 708 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 709 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 710 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 711 __le16 status; 712 union { 713 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 714 struct ice_sw_rule_lg_act lg_act; 715 struct ice_sw_rule_vsi_list vsi_list; 716 struct ice_sw_rule_vsi_list_query vsi_list_query; 717 } pdata; 718 }; 719 720 #pragma pack() 721 722 723 724 /* Get Default Topology (indirect 0x0400) */ 725 struct ice_aqc_get_topo { 726 u8 port_num; 727 u8 num_branches; 728 __le16 reserved1; 729 __le32 reserved2; 730 __le32 addr_high; 731 __le32 addr_low; 732 }; 733 734 735 /* Update TSE (indirect 0x0403) 736 * Get TSE (indirect 0x0404) 737 * Add TSE (indirect 0x0401) 738 * Delete TSE (indirect 0x040F) 739 * Move TSE (indirect 0x0408) 740 * Suspend Nodes (indirect 0x0409) 741 * Resume Nodes (indirect 0x040A) 742 */ 743 struct ice_aqc_sched_elem_cmd { 744 __le16 num_elem_req; /* Used by commands */ 745 __le16 num_elem_resp; /* Used by responses */ 746 __le32 reserved; 747 __le32 addr_high; 748 __le32 addr_low; 749 }; 750 751 752 /* This is the buffer for: 753 * Suspend Nodes (indirect 0x0409) 754 * Resume Nodes (indirect 0x040A) 755 */ 756 struct ice_aqc_suspend_resume_elem { 757 __le32 teid[1]; 758 }; 759 760 761 struct ice_aqc_txsched_move_grp_info_hdr { 762 __le32 src_parent_teid; 763 __le32 dest_parent_teid; 764 __le16 num_elems; 765 __le16 reserved; 766 }; 767 768 769 struct ice_aqc_move_elem { 770 struct ice_aqc_txsched_move_grp_info_hdr hdr; 771 __le32 teid[1]; 772 }; 773 774 775 struct ice_aqc_elem_info_bw { 776 __le16 bw_profile_idx; 777 __le16 bw_alloc; 778 }; 779 780 781 struct ice_aqc_txsched_elem { 782 u8 elem_type; /* Special field, reserved for some aq calls */ 783 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 784 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 785 #define ICE_AQC_ELEM_TYPE_TC 0x2 786 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 787 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 788 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 789 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 790 u8 valid_sections; 791 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 792 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 793 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 794 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 795 u8 generic; 796 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 797 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 798 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 799 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 800 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 801 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 802 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 803 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 804 u8 flags; /* Special field, reserved for some aq calls */ 805 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 806 struct ice_aqc_elem_info_bw cir_bw; 807 struct ice_aqc_elem_info_bw eir_bw; 808 __le16 srl_id; 809 __le16 reserved2; 810 }; 811 812 813 struct ice_aqc_txsched_elem_data { 814 __le32 parent_teid; 815 __le32 node_teid; 816 struct ice_aqc_txsched_elem data; 817 }; 818 819 820 struct ice_aqc_txsched_topo_grp_info_hdr { 821 __le32 parent_teid; 822 __le16 num_elems; 823 __le16 reserved2; 824 }; 825 826 827 struct ice_aqc_add_elem { 828 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 829 struct ice_aqc_txsched_elem_data generic[1]; 830 }; 831 832 833 struct ice_aqc_conf_elem { 834 struct ice_aqc_txsched_elem_data generic[1]; 835 }; 836 837 838 struct ice_aqc_get_elem { 839 struct ice_aqc_txsched_elem_data generic[1]; 840 }; 841 842 843 struct ice_aqc_get_topo_elem { 844 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 845 struct ice_aqc_txsched_elem_data 846 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 847 }; 848 849 850 struct ice_aqc_delete_elem { 851 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 852 __le32 teid[1]; 853 }; 854 855 856 857 858 /* Rate limiting profile for 859 * Add RL profile (indirect 0x0410) 860 * Query RL profile (indirect 0x0411) 861 * Remove RL profile (indirect 0x0415) 862 * These indirect commands acts on single or multiple 863 * RL profiles with specified data. 864 */ 865 struct ice_aqc_rl_profile { 866 __le16 num_profiles; 867 __le16 num_processed; /* Only for response. Reserved in Command. */ 868 u8 reserved[4]; 869 __le32 addr_high; 870 __le32 addr_low; 871 }; 872 873 874 struct ice_aqc_rl_profile_elem { 875 u8 level; 876 u8 flags; 877 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 878 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 879 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 880 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 881 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 882 /* The following flag is used for Query RL Profile Data */ 883 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 884 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 885 886 __le16 profile_id; 887 __le16 max_burst_size; 888 __le16 rl_multiply; 889 __le16 wake_up_calc; 890 __le16 rl_encode; 891 }; 892 893 894 struct ice_aqc_rl_profile_generic_elem { 895 struct ice_aqc_rl_profile_elem generic[1]; 896 }; 897 898 899 900 /* Configure L2 Node CGD (indirect 0x0414) 901 * This indirect command allows configuring a congestion domain for given L2 902 * node TEIDs in the scheduler topology. 903 */ 904 struct ice_aqc_cfg_l2_node_cgd { 905 __le16 num_l2_nodes; 906 u8 reserved[6]; 907 __le32 addr_high; 908 __le32 addr_low; 909 }; 910 911 912 struct ice_aqc_cfg_l2_node_cgd_elem { 913 __le32 node_teid; 914 u8 cgd; 915 u8 reserved[3]; 916 }; 917 918 919 struct ice_aqc_cfg_l2_node_cgd_data { 920 struct ice_aqc_cfg_l2_node_cgd_elem elem[1]; 921 }; 922 923 924 /* Query Scheduler Resource Allocation (indirect 0x0412) 925 * This indirect command retrieves the scheduler resources allocated by 926 * EMP Firmware to the given PF. 927 */ 928 struct ice_aqc_query_txsched_res { 929 u8 reserved[8]; 930 __le32 addr_high; 931 __le32 addr_low; 932 }; 933 934 935 struct ice_aqc_generic_sched_props { 936 __le16 phys_levels; 937 __le16 logical_levels; 938 u8 flattening_bitmap; 939 u8 max_device_cgds; 940 u8 max_pf_cgds; 941 u8 rsvd0; 942 __le16 rdma_qsets; 943 u8 rsvd1[22]; 944 }; 945 946 947 struct ice_aqc_layer_props { 948 u8 logical_layer; 949 u8 chunk_size; 950 __le16 max_device_nodes; 951 __le16 max_pf_nodes; 952 u8 rsvd0[4]; 953 __le16 max_sibl_grp_sz; 954 __le16 max_cir_rl_profiles; 955 __le16 max_eir_rl_profiles; 956 __le16 max_srl_profiles; 957 u8 rsvd1[14]; 958 }; 959 960 961 struct ice_aqc_query_txsched_res_resp { 962 struct ice_aqc_generic_sched_props sched_props; 963 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 964 }; 965 966 967 /* Query Node to Root Topology (indirect 0x0413) 968 * This command uses ice_aqc_get_elem as its data buffer. 969 */ 970 struct ice_aqc_query_node_to_root { 971 __le32 teid; 972 __le32 num_nodes; /* Response only */ 973 __le32 addr_high; 974 __le32 addr_low; 975 }; 976 977 978 /* Get PHY capabilities (indirect 0x0600) */ 979 struct ice_aqc_get_phy_caps { 980 u8 lport_num; 981 u8 reserved; 982 __le16 param0; 983 /* 18.0 - Report qualified modules */ 984 #define ICE_AQC_GET_PHY_RQM BIT(0) 985 /* 18.1 - 18.2 : Report mode 986 * 00b - Report NVM capabilities 987 * 01b - Report topology capabilities 988 * 10b - Report SW configured 989 */ 990 #define ICE_AQC_REPORT_MODE_S 1 991 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 992 #define ICE_AQC_REPORT_NVM_CAP 0 993 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 994 #define ICE_AQC_REPORT_SW_CFG BIT(2) 995 __le32 reserved1; 996 __le32 addr_high; 997 __le32 addr_low; 998 }; 999 1000 1001 /* This is #define of PHY type (Extended): 1002 * The first set of defines is for phy_type_low. 1003 */ 1004 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1005 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1006 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1007 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1008 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1009 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1010 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1011 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1012 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1013 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1014 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1015 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1016 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1017 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1018 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1019 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1020 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1021 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1022 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1023 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1024 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1025 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1026 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1027 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1028 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1029 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1030 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1031 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1032 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1033 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1034 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1035 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1036 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1037 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1038 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1039 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1040 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1041 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1042 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1043 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1044 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1045 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1046 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1047 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1048 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1049 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1050 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1051 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1052 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1053 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1054 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1055 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1056 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1057 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1058 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1059 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1060 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1061 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1062 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1063 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1064 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1065 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1066 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1067 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1068 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1069 /* The second set of defines is for phy_type_high. */ 1070 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1071 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1072 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1073 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1074 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1075 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 1076 1077 struct ice_aqc_get_phy_caps_data { 1078 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1079 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1080 u8 caps; 1081 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1082 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1083 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1084 #define ICE_AQC_PHY_EN_LINK BIT(3) 1085 #define ICE_AQC_PHY_AN_MODE BIT(4) 1086 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1087 #define ICE_AQC_PHY_EN_LESM BIT(6) 1088 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1089 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1090 u8 low_power_ctrl; 1091 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1092 __le16 eee_cap; 1093 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1094 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1095 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1096 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1097 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1098 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1099 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1100 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1101 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1102 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1103 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1104 __le16 eeer_value; 1105 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1106 u8 phy_fw_ver[8]; 1107 u8 link_fec_options; 1108 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1109 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1110 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1111 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1112 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1113 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1114 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1115 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1116 u8 extended_compliance_code; 1117 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1118 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1119 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1120 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1121 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1122 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1123 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1124 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1125 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1126 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1127 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1128 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1129 u8 qualified_module_count; 1130 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1131 struct { 1132 u8 v_oui[3]; 1133 u8 rsvd3; 1134 u8 v_part[16]; 1135 __le32 v_rev; 1136 __le64 rsvd8; 1137 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1138 }; 1139 1140 1141 /* Set PHY capabilities (direct 0x0601) 1142 * NOTE: This command must be followed by setup link and restart auto-neg 1143 */ 1144 struct ice_aqc_set_phy_cfg { 1145 u8 lport_num; 1146 u8 reserved[7]; 1147 __le32 addr_high; 1148 __le32 addr_low; 1149 }; 1150 1151 1152 /* Set PHY config command data structure */ 1153 struct ice_aqc_set_phy_cfg_data { 1154 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1155 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1156 u8 caps; 1157 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1158 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1159 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1160 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1161 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1162 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1163 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1164 u8 low_power_ctrl; 1165 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1166 __le16 eeer_value; 1167 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1168 u8 rsvd1; 1169 }; 1170 1171 1172 1173 /* Restart AN command data structure (direct 0x0605) 1174 * Also used for response, with only the lport_num field present. 1175 */ 1176 struct ice_aqc_restart_an { 1177 u8 lport_num; 1178 u8 reserved; 1179 u8 cmd_flags; 1180 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1181 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1182 u8 reserved2[13]; 1183 }; 1184 1185 1186 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1187 struct ice_aqc_get_link_status { 1188 u8 lport_num; 1189 u8 reserved; 1190 __le16 cmd_flags; 1191 #define ICE_AQ_LSE_M 0x3 1192 #define ICE_AQ_LSE_NOP 0x0 1193 #define ICE_AQ_LSE_DIS 0x2 1194 #define ICE_AQ_LSE_ENA 0x3 1195 /* only response uses this flag */ 1196 #define ICE_AQ_LSE_IS_ENABLED 0x1 1197 __le32 reserved2; 1198 __le32 addr_high; 1199 __le32 addr_low; 1200 }; 1201 1202 1203 /* Get link status response data structure, also used for Link Status Event */ 1204 struct ice_aqc_get_link_status_data { 1205 u8 topo_media_conflict; 1206 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1207 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1208 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1209 u8 reserved1; 1210 u8 link_info; 1211 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1212 #define ICE_AQ_LINK_FAULT BIT(1) 1213 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1214 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1215 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1216 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1217 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1218 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1219 u8 an_info; 1220 #define ICE_AQ_AN_COMPLETED BIT(0) 1221 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1222 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1223 #define ICE_AQ_FEC_EN BIT(3) 1224 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1225 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1226 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1227 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1228 u8 ext_info; 1229 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1230 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1231 /* Port TX Suspended */ 1232 #define ICE_AQ_LINK_TX_S 2 1233 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1234 #define ICE_AQ_LINK_TX_ACTIVE 0 1235 #define ICE_AQ_LINK_TX_DRAINED 1 1236 #define ICE_AQ_LINK_TX_FLUSHED 3 1237 u8 reserved2; 1238 __le16 max_frame_size; 1239 u8 cfg; 1240 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1241 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1242 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1243 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1244 /* Pacing Config */ 1245 #define ICE_AQ_CFG_PACING_S 3 1246 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1247 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1248 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1249 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1250 /* External Device Power Ability */ 1251 u8 power_desc; 1252 #define ICE_AQ_PWR_CLASS_M 0x3 1253 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1254 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1255 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1256 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1257 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1258 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1259 __le16 link_speed; 1260 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1261 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1262 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1263 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1264 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1265 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1266 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1267 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1268 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1269 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1270 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1271 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1272 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1273 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1274 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1275 }; 1276 1277 1278 /* Set event mask command (direct 0x0613) */ 1279 struct ice_aqc_set_event_mask { 1280 u8 lport_num; 1281 u8 reserved[7]; 1282 __le16 event_mask; 1283 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1284 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1285 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1286 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1287 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1288 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1289 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1290 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1291 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1292 u8 reserved1[6]; 1293 }; 1294 1295 1296 1297 /* Set MAC Loopback command (direct 0x0620) */ 1298 struct ice_aqc_set_mac_lb { 1299 u8 lb_mode; 1300 #define ICE_AQ_MAC_LB_EN BIT(0) 1301 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1302 u8 reserved[15]; 1303 }; 1304 1305 1306 1307 1308 1309 /* Set Port Identification LED (direct, 0x06E9) */ 1310 struct ice_aqc_set_port_id_led { 1311 u8 lport_num; 1312 u8 lport_num_valid; 1313 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1314 u8 ident_mode; 1315 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1316 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1317 u8 rsvd[13]; 1318 }; 1319 1320 1321 1322 /* NVM Read command (indirect 0x0701) 1323 * NVM Erase commands (direct 0x0702) 1324 * NVM Update commands (indirect 0x0703) 1325 */ 1326 struct ice_aqc_nvm { 1327 __le16 offset_low; 1328 u8 offset_high; 1329 u8 cmd_flags; 1330 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1331 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1332 #define ICE_AQC_NVM_PRESERVATION_S 1 1333 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1334 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1335 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1336 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1337 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1338 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1339 __le16 module_typeid; 1340 __le16 length; 1341 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1342 __le32 addr_high; 1343 __le32 addr_low; 1344 }; 1345 1346 1347 /* Used for 0x0704 as well as for 0x0705 commands */ 1348 struct ice_aqc_nvm_cfg { 1349 u8 cmd_flags; 1350 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 1351 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 1352 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 1353 u8 reserved; 1354 __le16 count; 1355 __le16 id; 1356 u8 reserved1[2]; 1357 __le32 addr_high; 1358 __le32 addr_low; 1359 }; 1360 1361 1362 struct ice_aqc_nvm_cfg_data { 1363 __le16 field_id; 1364 __le16 field_options; 1365 __le16 field_value; 1366 }; 1367 1368 1369 /* NVM Checksum Command (direct, 0x0706) */ 1370 struct ice_aqc_nvm_checksum { 1371 u8 flags; 1372 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1373 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1374 u8 rsvd; 1375 __le16 checksum; /* Used only by response */ 1376 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1377 u8 rsvd2[12]; 1378 }; 1379 1380 1381 1382 1383 1384 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1385 struct ice_aqc_get_set_rss_key { 1386 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1387 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1388 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1389 __le16 vsi_id; 1390 u8 reserved[6]; 1391 __le32 addr_high; 1392 __le32 addr_low; 1393 }; 1394 1395 1396 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1397 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1398 1399 struct ice_aqc_get_set_rss_keys { 1400 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1401 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1402 }; 1403 1404 1405 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1406 struct ice_aqc_get_set_rss_lut { 1407 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1408 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1409 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1410 __le16 vsi_id; 1411 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1412 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1413 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1414 1415 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1416 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1417 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1418 1419 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1420 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1421 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1422 1423 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1424 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1425 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1426 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1427 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1428 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1429 1430 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1431 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1432 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1433 1434 __le16 flags; 1435 __le32 reserved; 1436 __le32 addr_high; 1437 __le32 addr_low; 1438 }; 1439 1440 1441 1442 1443 1444 /* Add TX LAN Queues (indirect 0x0C30) */ 1445 struct ice_aqc_add_txqs { 1446 u8 num_qgrps; 1447 u8 reserved[3]; 1448 __le32 reserved1; 1449 __le32 addr_high; 1450 __le32 addr_low; 1451 }; 1452 1453 1454 /* This is the descriptor of each queue entry for the Add TX LAN Queues 1455 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1456 */ 1457 struct ice_aqc_add_txqs_perq { 1458 __le16 txq_id; 1459 u8 rsvd[2]; 1460 __le32 q_teid; 1461 u8 txq_ctx[22]; 1462 u8 rsvd2[2]; 1463 struct ice_aqc_txsched_elem info; 1464 }; 1465 1466 1467 /* The format of the command buffer for Add TX LAN Queues (0x0C30) 1468 * is an array of the following structs. Please note that the length of 1469 * each struct ice_aqc_add_tx_qgrp is variable due 1470 * to the variable number of queues in each group! 1471 */ 1472 struct ice_aqc_add_tx_qgrp { 1473 __le32 parent_teid; 1474 u8 num_txqs; 1475 u8 rsvd[3]; 1476 struct ice_aqc_add_txqs_perq txqs[1]; 1477 }; 1478 1479 1480 /* Disable TX LAN Queues (indirect 0x0C31) */ 1481 struct ice_aqc_dis_txqs { 1482 u8 cmd_type; 1483 #define ICE_AQC_Q_DIS_CMD_S 0 1484 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1485 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1486 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1487 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1488 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1489 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1490 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1491 u8 num_entries; 1492 __le16 vmvf_and_timeout; 1493 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1494 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1495 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1496 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1497 __le32 blocked_cgds; 1498 __le32 addr_high; 1499 __le32 addr_low; 1500 }; 1501 1502 1503 /* The buffer for Disable TX LAN Queues (indirect 0x0C31) 1504 * contains the following structures, arrayed one after the 1505 * other. 1506 * Note: Since the q_id is 16 bits wide, if the 1507 * number of queues is even, then 2 bytes of alignment MUST be 1508 * added before the start of the next group, to allow correct 1509 * alignment of the parent_teid field. 1510 */ 1511 struct ice_aqc_dis_txq_item { 1512 __le32 parent_teid; 1513 u8 num_qs; 1514 u8 rsvd; 1515 /* The length of the q_id array varies according to num_qs */ 1516 __le16 q_id[1]; 1517 /* This only applies from F8 onward */ 1518 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1519 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1520 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1521 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1522 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1523 }; 1524 1525 1526 struct ice_aqc_dis_txq { 1527 struct ice_aqc_dis_txq_item qgrps[1]; 1528 }; 1529 1530 1531 /* TX LAN Queues Cleanup Event (0x0C31) */ 1532 struct ice_aqc_txqs_cleanup { 1533 __le16 caller_opc; 1534 __le16 cmd_tag; 1535 u8 reserved[12]; 1536 }; 1537 1538 1539 /* Move / Reconfigure TX Queues (indirect 0x0C32) */ 1540 struct ice_aqc_move_txqs { 1541 u8 cmd_type; 1542 #define ICE_AQC_Q_CMD_TYPE_S 0 1543 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 1544 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 1545 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 1546 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 1547 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 1548 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 1549 u8 num_qs; 1550 u8 rsvd; 1551 u8 timeout; 1552 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 1553 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 1554 __le32 blocked_cgds; 1555 __le32 addr_high; 1556 __le32 addr_low; 1557 }; 1558 1559 1560 /* This is the descriptor of each queue entry for the move TX LAN Queues 1561 * command (0x0C32). 1562 */ 1563 struct ice_aqc_move_txqs_elem { 1564 __le16 txq_id; 1565 u8 q_cgd; 1566 u8 rsvd; 1567 __le32 q_teid; 1568 }; 1569 1570 1571 struct ice_aqc_move_txqs_data { 1572 __le32 src_teid; 1573 __le32 dest_teid; 1574 struct ice_aqc_move_txqs_elem txqs[1]; 1575 }; 1576 1577 1578 1579 /* Download Package (indirect 0x0C40) */ 1580 /* Also used for Update Package (indirect 0x0C42) */ 1581 struct ice_aqc_download_pkg { 1582 u8 flags; 1583 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 1584 u8 reserved[3]; 1585 __le32 reserved1; 1586 __le32 addr_high; 1587 __le32 addr_low; 1588 }; 1589 1590 struct ice_aqc_download_pkg_resp { 1591 __le32 error_offset; 1592 __le32 error_info; 1593 __le32 addr_high; 1594 __le32 addr_low; 1595 }; 1596 1597 /* Get Package Info List (indirect 0x0C43) */ 1598 struct ice_aqc_get_pkg_info_list { 1599 __le32 reserved1; 1600 __le32 reserved2; 1601 __le32 addr_high; 1602 __le32 addr_low; 1603 }; 1604 1605 /* Version format for packages */ 1606 struct ice_pkg_ver { 1607 u8 major; 1608 u8 minor; 1609 u8 update; 1610 u8 draft; 1611 }; 1612 1613 #define ICE_PKG_NAME_SIZE 32 1614 1615 struct ice_aqc_get_pkg_info { 1616 struct ice_pkg_ver ver; 1617 char name[ICE_PKG_NAME_SIZE]; 1618 u8 is_in_nvm; 1619 u8 is_active; 1620 u8 is_active_at_boot; 1621 u8 is_modified; 1622 }; 1623 1624 /* Get Package Info List response buffer format (0x0C43) */ 1625 struct ice_aqc_get_pkg_info_resp { 1626 __le32 count; 1627 struct ice_aqc_get_pkg_info pkg_info[1]; 1628 }; 1629 1630 1631 1632 1633 /* Lan Queue Overflow Event (direct, 0x1001) */ 1634 struct ice_aqc_event_lan_overflow { 1635 __le32 prtdcb_ruptq; 1636 __le32 qtx_ctl; 1637 u8 reserved[8]; 1638 }; 1639 1640 1641 1642 /* Configure Firmware Logging Command (indirect 0xFF09) 1643 * Logging Information Read Response (indirect 0xFF10) 1644 * Note: The 0xFF10 command has no input parameters. 1645 */ 1646 struct ice_aqc_fw_logging { 1647 u8 log_ctrl; 1648 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1649 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1650 u8 rsvd0; 1651 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1652 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1653 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1654 u8 rsvd1[5]; 1655 __le32 addr_high; 1656 __le32 addr_low; 1657 }; 1658 1659 1660 enum ice_aqc_fw_logging_mod { 1661 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1662 ICE_AQC_FW_LOG_ID_CTRL, 1663 ICE_AQC_FW_LOG_ID_LINK, 1664 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1665 ICE_AQC_FW_LOG_ID_DNL, 1666 ICE_AQC_FW_LOG_ID_I2C, 1667 ICE_AQC_FW_LOG_ID_SDP, 1668 ICE_AQC_FW_LOG_ID_MDIO, 1669 ICE_AQC_FW_LOG_ID_ADMINQ, 1670 ICE_AQC_FW_LOG_ID_HDMA, 1671 ICE_AQC_FW_LOG_ID_LLDP, 1672 ICE_AQC_FW_LOG_ID_DCBX, 1673 ICE_AQC_FW_LOG_ID_DCB, 1674 ICE_AQC_FW_LOG_ID_NETPROXY, 1675 ICE_AQC_FW_LOG_ID_NVM, 1676 ICE_AQC_FW_LOG_ID_AUTH, 1677 ICE_AQC_FW_LOG_ID_VPD, 1678 ICE_AQC_FW_LOG_ID_IOSF, 1679 ICE_AQC_FW_LOG_ID_PARSER, 1680 ICE_AQC_FW_LOG_ID_SW, 1681 ICE_AQC_FW_LOG_ID_SCHEDULER, 1682 ICE_AQC_FW_LOG_ID_TXQ, 1683 ICE_AQC_FW_LOG_ID_RSVD, 1684 ICE_AQC_FW_LOG_ID_POST, 1685 ICE_AQC_FW_LOG_ID_WATCHDOG, 1686 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1687 ICE_AQC_FW_LOG_ID_MNG, 1688 ICE_AQC_FW_LOG_ID_MAX, 1689 }; 1690 1691 /* This is the buffer for both of the logging commands. 1692 * The entry array size depends on the datalen parameter in the descriptor. 1693 * There will be a total of datalen / 2 entries. 1694 */ 1695 struct ice_aqc_fw_logging_data { 1696 __le16 entry[1]; 1697 #define ICE_AQC_FW_LOG_ID_S 0 1698 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1699 1700 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1701 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1702 1703 #define ICE_AQC_FW_LOG_EN_S 12 1704 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1705 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1706 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1707 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1708 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1709 }; 1710 1711 1712 /* Get/Clear FW Log (indirect 0xFF11) */ 1713 struct ice_aqc_get_clear_fw_log { 1714 u8 flags; 1715 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1716 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1717 u8 rsvd1[7]; 1718 __le32 addr_high; 1719 __le32 addr_low; 1720 }; 1721 1722 1723 /** 1724 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1725 * @flags: ICE_AQ_FLAG_* flags 1726 * @opcode: AQ command opcode 1727 * @datalen: length in bytes of indirect/external data buffer 1728 * @retval: return value from firmware 1729 * @cookie_h: opaque data high-half 1730 * @cookie_l: opaque data low-half 1731 * @params: command-specific parameters 1732 * 1733 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1734 * (ATQ). The firmware writes back onto the command descriptor and returns 1735 * the result of the command. Asynchronous events that are not an immediate 1736 * result of the command are written to the Admin Receive Queue (ARQ) using 1737 * the same descriptor format. Descriptors are in little-endian notation with 1738 * 32-bit words. 1739 */ 1740 struct ice_aq_desc { 1741 __le16 flags; 1742 __le16 opcode; 1743 __le16 datalen; 1744 __le16 retval; 1745 __le32 cookie_high; 1746 __le32 cookie_low; 1747 union { 1748 u8 raw[16]; 1749 struct ice_aqc_generic generic; 1750 struct ice_aqc_get_ver get_ver; 1751 struct ice_aqc_q_shutdown q_shutdown; 1752 struct ice_aqc_req_res res_owner; 1753 struct ice_aqc_manage_mac_read mac_read; 1754 struct ice_aqc_manage_mac_write mac_write; 1755 struct ice_aqc_clear_pxe clear_pxe; 1756 struct ice_aqc_list_caps get_cap; 1757 struct ice_aqc_get_phy_caps get_phy; 1758 struct ice_aqc_set_phy_cfg set_phy; 1759 struct ice_aqc_restart_an restart_an; 1760 struct ice_aqc_set_port_id_led set_port_id_led; 1761 struct ice_aqc_get_sw_cfg get_sw_conf; 1762 struct ice_aqc_sw_rules sw_rules; 1763 struct ice_aqc_get_topo get_topo; 1764 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 1765 struct ice_aqc_query_txsched_res query_sched_res; 1766 struct ice_aqc_query_node_to_root query_node_to_root; 1767 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 1768 struct ice_aqc_rl_profile rl_profile; 1769 1770 struct ice_aqc_nvm nvm; 1771 struct ice_aqc_nvm_cfg nvm_cfg; 1772 struct ice_aqc_nvm_checksum nvm_checksum; 1773 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1774 struct ice_aqc_get_set_rss_key get_set_rss_key; 1775 struct ice_aqc_add_txqs add_txqs; 1776 struct ice_aqc_dis_txqs dis_txqs; 1777 struct ice_aqc_txqs_cleanup txqs_cleanup; 1778 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1779 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1780 struct ice_aqc_download_pkg download_pkg; 1781 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 1782 struct ice_aqc_fw_logging fw_logging; 1783 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1784 struct ice_aqc_set_mac_lb set_mac_lb; 1785 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1786 struct ice_aqc_set_event_mask set_event_mask; 1787 struct ice_aqc_get_link_status get_link_status; 1788 } params; 1789 }; 1790 1791 1792 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1793 #define ICE_AQ_LG_BUF 512 1794 1795 /* Flags sub-structure 1796 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 1797 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 1798 */ 1799 1800 /* command flags and offsets */ 1801 #define ICE_AQ_FLAG_DD_S 0 1802 #define ICE_AQ_FLAG_CMP_S 1 1803 #define ICE_AQ_FLAG_ERR_S 2 1804 #define ICE_AQ_FLAG_VFE_S 3 1805 #define ICE_AQ_FLAG_LB_S 9 1806 #define ICE_AQ_FLAG_RD_S 10 1807 #define ICE_AQ_FLAG_VFC_S 11 1808 #define ICE_AQ_FLAG_BUF_S 12 1809 #define ICE_AQ_FLAG_SI_S 13 1810 #define ICE_AQ_FLAG_EI_S 14 1811 #define ICE_AQ_FLAG_FE_S 15 1812 1813 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 1814 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 1815 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1816 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 1817 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1818 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1819 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 1820 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1821 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1822 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 1823 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 1824 1825 /* error codes */ 1826 enum ice_aq_err { 1827 ICE_AQ_RC_OK = 0, /* Success */ 1828 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 1829 ICE_AQ_RC_ENOENT = 2, /* No such element */ 1830 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 1831 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 1832 ICE_AQ_RC_EIO = 5, /* I/O error */ 1833 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 1834 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 1835 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 1836 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1837 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 1838 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 1839 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1840 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1841 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 1842 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 1843 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1844 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1845 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 1846 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 1847 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 1848 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 1849 ICE_AQ_RC_EFBIG = 22, /* File too big */ 1850 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 1851 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 1852 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 1853 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 1854 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 1855 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 1856 }; 1857 1858 /* Admin Queue command opcodes */ 1859 enum ice_adminq_opc { 1860 /* AQ commands */ 1861 ice_aqc_opc_get_ver = 0x0001, 1862 ice_aqc_opc_driver_ver = 0x0002, 1863 ice_aqc_opc_q_shutdown = 0x0003, 1864 ice_aqc_opc_get_exp_err = 0x0005, 1865 1866 /* resource ownership */ 1867 ice_aqc_opc_req_res = 0x0008, 1868 ice_aqc_opc_release_res = 0x0009, 1869 1870 /* device/function capabilities */ 1871 ice_aqc_opc_list_func_caps = 0x000A, 1872 ice_aqc_opc_list_dev_caps = 0x000B, 1873 1874 /* manage MAC address */ 1875 ice_aqc_opc_manage_mac_read = 0x0107, 1876 ice_aqc_opc_manage_mac_write = 0x0108, 1877 1878 /* PXE */ 1879 ice_aqc_opc_clear_pxe_mode = 0x0110, 1880 1881 /* internal switch commands */ 1882 ice_aqc_opc_get_sw_cfg = 0x0200, 1883 1884 /* Alloc/Free/Get Resources */ 1885 ice_aqc_opc_get_res_alloc = 0x0204, 1886 ice_aqc_opc_alloc_res = 0x0208, 1887 ice_aqc_opc_free_res = 0x0209, 1888 ice_aqc_opc_get_allocd_res_desc = 0x020A, 1889 1890 /* VSI commands */ 1891 ice_aqc_opc_add_vsi = 0x0210, 1892 ice_aqc_opc_update_vsi = 0x0211, 1893 ice_aqc_opc_get_vsi_params = 0x0212, 1894 ice_aqc_opc_free_vsi = 0x0213, 1895 1896 1897 1898 /* switch rules population commands */ 1899 ice_aqc_opc_add_sw_rules = 0x02A0, 1900 ice_aqc_opc_update_sw_rules = 0x02A1, 1901 ice_aqc_opc_remove_sw_rules = 0x02A2, 1902 ice_aqc_opc_get_sw_rules = 0x02A3, 1903 ice_aqc_opc_clear_pf_cfg = 0x02A4, 1904 1905 1906 /* transmit scheduler commands */ 1907 ice_aqc_opc_get_dflt_topo = 0x0400, 1908 ice_aqc_opc_add_sched_elems = 0x0401, 1909 ice_aqc_opc_cfg_sched_elems = 0x0403, 1910 ice_aqc_opc_get_sched_elems = 0x0404, 1911 ice_aqc_opc_move_sched_elems = 0x0408, 1912 ice_aqc_opc_suspend_sched_elems = 0x0409, 1913 ice_aqc_opc_resume_sched_elems = 0x040A, 1914 ice_aqc_opc_suspend_sched_traffic = 0x040B, 1915 ice_aqc_opc_resume_sched_traffic = 0x040C, 1916 ice_aqc_opc_delete_sched_elems = 0x040F, 1917 ice_aqc_opc_add_rl_profiles = 0x0410, 1918 ice_aqc_opc_query_rl_profiles = 0x0411, 1919 ice_aqc_opc_query_sched_res = 0x0412, 1920 ice_aqc_opc_query_node_to_root = 0x0413, 1921 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 1922 ice_aqc_opc_remove_rl_profiles = 0x0415, 1923 1924 /* PHY commands */ 1925 ice_aqc_opc_get_phy_caps = 0x0600, 1926 ice_aqc_opc_set_phy_cfg = 0x0601, 1927 ice_aqc_opc_set_mac_cfg = 0x0603, 1928 ice_aqc_opc_restart_an = 0x0605, 1929 ice_aqc_opc_get_link_status = 0x0607, 1930 ice_aqc_opc_set_event_mask = 0x0613, 1931 ice_aqc_opc_set_mac_lb = 0x0620, 1932 ice_aqc_opc_set_port_id_led = 0x06E9, 1933 ice_aqc_opc_get_port_options = 0x06EA, 1934 ice_aqc_opc_set_port_option = 0x06EB, 1935 ice_aqc_opc_set_gpio = 0x06EC, 1936 ice_aqc_opc_get_gpio = 0x06ED, 1937 1938 /* NVM commands */ 1939 ice_aqc_opc_nvm_read = 0x0701, 1940 ice_aqc_opc_nvm_erase = 0x0702, 1941 ice_aqc_opc_nvm_update = 0x0703, 1942 ice_aqc_opc_nvm_cfg_read = 0x0704, 1943 ice_aqc_opc_nvm_cfg_write = 0x0705, 1944 ice_aqc_opc_nvm_checksum = 0x0706, 1945 1946 1947 /* RSS commands */ 1948 ice_aqc_opc_set_rss_key = 0x0B02, 1949 ice_aqc_opc_set_rss_lut = 0x0B03, 1950 ice_aqc_opc_get_rss_key = 0x0B04, 1951 ice_aqc_opc_get_rss_lut = 0x0B05, 1952 1953 /* TX queue handling commands/events */ 1954 ice_aqc_opc_add_txqs = 0x0C30, 1955 ice_aqc_opc_dis_txqs = 0x0C31, 1956 ice_aqc_opc_txqs_cleanup = 0x0C31, 1957 ice_aqc_opc_move_recfg_txqs = 0x0C32, 1958 1959 /* package commands */ 1960 ice_aqc_opc_download_pkg = 0x0C40, 1961 ice_aqc_opc_upload_section = 0x0C41, 1962 ice_aqc_opc_update_pkg = 0x0C42, 1963 ice_aqc_opc_get_pkg_info_list = 0x0C43, 1964 1965 1966 1967 /* Standalone Commands/Events */ 1968 ice_aqc_opc_event_lan_overflow = 0x1001, 1969 1970 /* debug commands */ 1971 ice_aqc_opc_fw_logging = 0xFF09, 1972 ice_aqc_opc_fw_logging_info = 0xFF10, 1973 ice_aqc_opc_get_clear_fw_log = 0xFF11 1974 }; 1975 1976 #endif /* _ICE_ADMINQ_CMD_H_ */ 1977