1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #ifndef _ICE_ADMINQ_CMD_H_ 6 #define _ICE_ADMINQ_CMD_H_ 7 8 /* This header file defines the Admin Queue commands, error codes and 9 * descriptor format. It is shared between Firmware and Software. 10 */ 11 12 #define ICE_MAX_VSI 768 13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 15 16 struct ice_aqc_generic { 17 __le32 param0; 18 __le32 param1; 19 __le32 addr_high; 20 __le32 addr_low; 21 }; 22 23 /* Get version (direct 0x0001) */ 24 struct ice_aqc_get_ver { 25 __le32 rom_ver; 26 __le32 fw_build; 27 u8 fw_branch; 28 u8 fw_major; 29 u8 fw_minor; 30 u8 fw_patch; 31 u8 api_branch; 32 u8 api_major; 33 u8 api_minor; 34 u8 api_patch; 35 }; 36 37 /* Send driver version (indirect 0x0002) */ 38 struct ice_aqc_driver_ver { 39 u8 major_ver; 40 u8 minor_ver; 41 u8 build_ver; 42 u8 subbuild_ver; 43 u8 reserved[4]; 44 __le32 addr_high; 45 __le32 addr_low; 46 }; 47 48 /* Queue Shutdown (direct 0x0003) */ 49 struct ice_aqc_q_shutdown { 50 u8 driver_unloading; 51 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 52 u8 reserved[15]; 53 }; 54 55 /* Request resource ownership (direct 0x0008) 56 * Release resource ownership (direct 0x0009) 57 */ 58 struct ice_aqc_req_res { 59 __le16 res_id; 60 #define ICE_AQC_RES_ID_NVM 1 61 #define ICE_AQC_RES_ID_SDP 2 62 #define ICE_AQC_RES_ID_CHNG_LOCK 3 63 #define ICE_AQC_RES_ID_GLBL_LOCK 4 64 __le16 access_type; 65 #define ICE_AQC_RES_ACCESS_READ 1 66 #define ICE_AQC_RES_ACCESS_WRITE 2 67 68 /* Upon successful completion, FW writes this value and driver is 69 * expected to release resource before timeout. This value is provided 70 * in milliseconds. 71 */ 72 __le32 timeout; 73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 77 /* For SDP: pin ID of the SDP */ 78 __le32 res_number; 79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 80 __le16 status; 81 #define ICE_AQ_RES_GLBL_SUCCESS 0 82 #define ICE_AQ_RES_GLBL_IN_PROG 1 83 #define ICE_AQ_RES_GLBL_DONE 2 84 u8 reserved[2]; 85 }; 86 87 /* Get function capabilities (indirect 0x000A) 88 * Get device capabilities (indirect 0x000B) 89 */ 90 struct ice_aqc_list_caps { 91 u8 cmd_flags; 92 u8 pf_index; 93 u8 reserved[2]; 94 __le32 count; 95 __le32 addr_high; 96 __le32 addr_low; 97 }; 98 99 /* Device/Function buffer entry, repeated per reported capability */ 100 struct ice_aqc_list_caps_elem { 101 __le16 cap; 102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 #define ICE_AQC_CAPS_IWARP 0x0051 113 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 114 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 115 116 u8 major_ver; 117 u8 minor_ver; 118 /* Number of resources described by this capability */ 119 __le32 number; 120 /* Only meaningful for some types of resources */ 121 __le32 logical_id; 122 /* Only meaningful for some types of resources */ 123 __le32 phys_id; 124 __le64 rsvd1; 125 __le64 rsvd2; 126 }; 127 128 /* Manage MAC address, read command - indirect (0x0107) 129 * This struct is also used for the response 130 */ 131 struct ice_aqc_manage_mac_read { 132 __le16 flags; /* Zeroed by device driver */ 133 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 134 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 135 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 136 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 137 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 138 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 139 #define ICE_AQC_MAN_MAC_READ_S 4 140 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 141 u8 rsvd[2]; 142 u8 num_addr; /* Used in response */ 143 u8 rsvd1[3]; 144 __le32 addr_high; 145 __le32 addr_low; 146 }; 147 148 /* Response buffer format for manage MAC read command */ 149 struct ice_aqc_manage_mac_read_resp { 150 u8 lport_num; 151 u8 addr_type; 152 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 153 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 154 u8 mac_addr[ETH_ALEN]; 155 }; 156 157 /* Manage MAC address, write command - direct (0x0108) */ 158 struct ice_aqc_manage_mac_write { 159 u8 rsvd; 160 u8 flags; 161 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 162 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 163 #define ICE_AQC_MAN_MAC_WR_S 6 164 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 165 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 166 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 167 /* byte stream in network order */ 168 u8 mac_addr[ETH_ALEN]; 169 __le32 addr_high; 170 __le32 addr_low; 171 }; 172 173 /* Clear PXE Command and response (direct 0x0110) */ 174 struct ice_aqc_clear_pxe { 175 u8 rx_cnt; 176 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 177 u8 reserved[15]; 178 }; 179 180 /* Configure No-Drop Policy Command (direct 0x0112) */ 181 struct ice_aqc_config_no_drop_policy { 182 u8 opts; 183 #define ICE_AQC_FORCE_NO_DROP BIT(0) 184 u8 rsvd[15]; 185 }; 186 187 /* Get switch configuration (0x0200) */ 188 struct ice_aqc_get_sw_cfg { 189 /* Reserved for command and copy of request flags for response */ 190 __le16 flags; 191 /* First desc in case of command and next_elem in case of response 192 * In case of response, if it is not zero, means all the configuration 193 * was not returned and new command shall be sent with this value in 194 * the 'first desc' field 195 */ 196 __le16 element; 197 /* Reserved for command, only used for response */ 198 __le16 num_elems; 199 __le16 rsvd; 200 __le32 addr_high; 201 __le32 addr_low; 202 }; 203 204 /* Each entry in the response buffer is of the following type: */ 205 struct ice_aqc_get_sw_cfg_resp_elem { 206 /* VSI/Port Number */ 207 __le16 vsi_port_num; 208 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 209 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 210 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 211 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 212 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 213 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 214 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 215 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 216 217 /* SWID VSI/Port belongs to */ 218 __le16 swid; 219 220 /* Bit 14..0 : PF/VF number VSI belongs to 221 * Bit 15 : VF indication bit 222 */ 223 __le16 pf_vf_num; 224 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 225 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 226 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 227 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 228 }; 229 230 /* Set Port parameters, (direct, 0x0203) */ 231 struct ice_aqc_set_port_params { 232 __le16 cmd_flags; 233 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 234 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 235 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 236 __le16 bad_frame_vsi; 237 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 238 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 239 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 240 __le16 swid; 241 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 242 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 243 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 244 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 245 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 246 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 247 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 248 u8 reserved[10]; 249 }; 250 251 /* These resource type defines are used for all switch resource 252 * commands where a resource type is required, such as: 253 * Get Resource Allocation command (indirect 0x0204) 254 * Allocate Resources command (indirect 0x0208) 255 * Free Resources command (indirect 0x0209) 256 * Get Allocated Resource Descriptors Command (indirect 0x020A) 257 */ 258 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 259 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 260 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 261 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 262 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 263 #define ICE_AQC_RES_TYPE_RECIPE 0x05 264 #define ICE_AQC_RES_TYPE_PROFILE 0x06 265 #define ICE_AQC_RES_TYPE_SWID 0x07 266 #define ICE_AQC_RES_TYPE_VSI 0x08 267 #define ICE_AQC_RES_TYPE_FLU 0x09 268 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 269 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 270 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 271 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 272 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 273 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 274 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 275 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 276 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 277 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 278 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 279 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 280 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 281 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 282 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 283 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 284 /* Resource types 0x62-67 are reserved for Hash profile builder */ 285 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 286 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 287 288 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 289 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 290 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 291 292 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 293 294 #define ICE_AQC_RES_TYPE_S 0 295 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 296 297 /* Get Resource Allocation command (indirect 0x0204) */ 298 struct ice_aqc_get_res_alloc { 299 __le16 resp_elem_num; /* Used in response, reserved in command */ 300 u8 reserved[6]; 301 __le32 addr_high; 302 __le32 addr_low; 303 }; 304 305 /* Get Resource Allocation Response Buffer per response */ 306 struct ice_aqc_get_res_resp_elem { 307 __le16 res_type; /* Types defined above cmd 0x0204 */ 308 __le16 total_capacity; /* Resources available to all PF's */ 309 __le16 total_function; /* Resources allocated for a PF */ 310 __le16 total_shared; /* Resources allocated as shared */ 311 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 312 }; 313 314 /* Allocate Resources command (indirect 0x0208) 315 * Free Resources command (indirect 0x0209) 316 */ 317 struct ice_aqc_alloc_free_res_cmd { 318 __le16 num_entries; /* Number of Resource entries */ 319 u8 reserved[6]; 320 __le32 addr_high; 321 __le32 addr_low; 322 }; 323 324 /* Resource descriptor */ 325 struct ice_aqc_res_elem { 326 union { 327 __le16 sw_resp; 328 __le16 flu_resp; 329 } e; 330 }; 331 332 /* Buffer for Allocate/Free Resources commands */ 333 struct ice_aqc_alloc_free_res_elem { 334 __le16 res_type; /* Types defined above cmd 0x0204 */ 335 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 336 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 337 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 338 __le16 num_elems; 339 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 340 }; 341 342 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 343 struct ice_aqc_get_allocd_res_desc { 344 union { 345 struct { 346 __le16 res; /* Types defined above cmd 0x0204 */ 347 __le16 first_desc; 348 __le32 reserved; 349 } cmd; 350 struct { 351 __le16 res; 352 __le16 next_desc; 353 __le16 num_desc; 354 __le16 reserved; 355 } resp; 356 } ops; 357 __le32 addr_high; 358 __le32 addr_low; 359 }; 360 361 /* Add VSI (indirect 0x0210) 362 * Update VSI (indirect 0x0211) 363 * Get VSI (indirect 0x0212) 364 * Free VSI (indirect 0x0213) 365 */ 366 struct ice_aqc_add_get_update_free_vsi { 367 __le16 vsi_num; 368 #define ICE_AQ_VSI_NUM_S 0 369 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 370 #define ICE_AQ_VSI_IS_VALID BIT(15) 371 __le16 cmd_flags; 372 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 373 u8 vf_id; 374 u8 reserved; 375 __le16 vsi_flags; 376 #define ICE_AQ_VSI_TYPE_S 0 377 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 378 #define ICE_AQ_VSI_TYPE_VF 0x0 379 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 380 #define ICE_AQ_VSI_TYPE_PF 0x2 381 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 382 __le32 addr_high; 383 __le32 addr_low; 384 }; 385 386 /* Response descriptor for: 387 * Add VSI (indirect 0x0210) 388 * Update VSI (indirect 0x0211) 389 * Free VSI (indirect 0x0213) 390 */ 391 struct ice_aqc_add_update_free_vsi_resp { 392 __le16 vsi_num; 393 __le16 ext_status; 394 __le16 vsi_used; 395 __le16 vsi_free; 396 __le32 addr_high; 397 __le32 addr_low; 398 }; 399 400 struct ice_aqc_get_vsi_resp { 401 __le16 vsi_num; 402 u8 vf_id; 403 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 404 * These are found above in struct ice_aqc_add_get_update_free_vsi. 405 */ 406 u8 vsi_flags; 407 __le16 vsi_used; 408 __le16 vsi_free; 409 __le32 addr_high; 410 __le32 addr_low; 411 }; 412 413 struct ice_aqc_vsi_props { 414 __le16 valid_sections; 415 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 416 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 417 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 418 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 419 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 420 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 421 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 422 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 423 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 424 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10) 425 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 426 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 427 /* switch section */ 428 u8 sw_id; 429 u8 sw_flags; 430 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 431 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 432 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 433 u8 sw_flags2; 434 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 435 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 436 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 437 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 438 u8 veb_stat_id; 439 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 440 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 441 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 442 /* security section */ 443 u8 sec_flags; 444 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 445 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 446 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 447 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 448 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 449 u8 sec_reserved; 450 /* VLAN section */ 451 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 452 u8 inner_vlan_reserved[2]; 453 u8 inner_vlan_flags; 454 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 455 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 456 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 457 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 458 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 459 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 460 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 461 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 462 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 463 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 464 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 465 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 466 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 467 u8 inner_vlan_reserved2[3]; 468 /* ingress egress up sections */ 469 __le32 ingress_table; /* bitmap, 3 bits per up */ 470 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 471 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 472 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 473 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 474 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 475 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 476 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 477 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 478 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 479 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 480 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 481 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 482 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 483 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 484 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 485 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 486 __le32 egress_table; /* same defines as for ingress table */ 487 /* outer tags section */ 488 __le16 port_based_outer_vlan; 489 u8 outer_vlan_flags; 490 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 491 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 492 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 493 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 494 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 495 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 496 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 497 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 498 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 499 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 500 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 501 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 502 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 503 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(4) 504 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 505 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 506 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 507 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 508 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 509 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 510 u8 outer_vlan_reserved; 511 /* queue mapping section */ 512 __le16 mapping_flags; 513 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 514 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 515 __le16 q_mapping[16]; 516 #define ICE_AQ_VSI_Q_S 0 517 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 518 __le16 tc_mapping[8]; 519 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 520 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 521 #define ICE_AQ_VSI_TC_Q_NUM_S 11 522 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 523 /* queueing option section */ 524 u8 q_opt_rss; 525 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 526 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 527 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 528 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 529 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 530 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 531 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 532 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 533 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 534 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 535 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 536 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 537 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 538 u8 q_opt_tc; 539 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 540 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 541 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 542 u8 q_opt_flags; 543 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 544 u8 q_opt_reserved[3]; 545 /* outer up section */ 546 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 547 /* ACL section */ 548 __le16 acl_def_act; 549 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0 550 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S) 551 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4 552 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S) 553 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8 554 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S) 555 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12 556 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S) 557 /* flow director section */ 558 __le16 fd_options; 559 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 560 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 561 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 562 __le16 max_fd_fltr_dedicated; 563 __le16 max_fd_fltr_shared; 564 __le16 fd_def_q; 565 #define ICE_AQ_VSI_FD_DEF_Q_S 0 566 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 567 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 568 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 569 __le16 fd_report_opt; 570 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 571 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 572 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 573 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 574 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 575 /* PASID section */ 576 __le32 pasid_id; 577 #define ICE_AQ_VSI_PASID_ID_S 0 578 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 579 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 580 u8 reserved[24]; 581 }; 582 583 /* Add/update mirror rule - direct (0x0260) */ 584 #define ICE_AQC_RULE_ID_VALID_S 7 585 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 586 #define ICE_AQC_RULE_ID_S 0 587 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 588 589 /* Following defines to be used while processing caller specified mirror list 590 * of VSI indexes. 591 */ 592 /* Action: Byte.bit (1.7) 593 * 0 = Remove VSI from mirror rule 594 * 1 = Add VSI to mirror rule 595 */ 596 #define ICE_AQC_RULE_ACT_S 15 597 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 598 /* Action: 1.2:0.0 = Mirrored VSI */ 599 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 600 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 601 602 /* This is to be used by add/update mirror rule Admin Queue command. 603 * In case of add mirror rule - if rule ID is specified as 604 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 605 * If specified rule_id is valid, then it is used. If specified rule_id 606 * is in use then new mirroring rule is added. 607 */ 608 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 609 610 struct ice_aqc_add_update_mir_rule { 611 __le16 rule_id; 612 613 __le16 rule_type; 614 #define ICE_AQC_RULE_TYPE_S 0 615 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 616 /* VPORT ingress/egress */ 617 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 618 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 619 /* Physical port ingress mirroring. 620 * All traffic received by this port 621 */ 622 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 623 /* Physical port egress mirroring. All traffic sent by this port */ 624 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 625 626 /* Number of mirrored entries. 627 * The values are in the command buffer 628 */ 629 __le16 num_entries; 630 631 /* Destination VSI */ 632 __le16 dest; 633 __le32 addr_high; 634 __le32 addr_low; 635 }; 636 637 /* Delete mirror rule - direct(0x0261) */ 638 struct ice_aqc_delete_mir_rule { 639 __le16 rule_id; 640 __le16 rsvd; 641 642 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 643 * the PF allocated resources, otherwise it is returned to the 644 * shared pool 645 */ 646 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 647 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 648 __le16 flags; 649 650 u8 reserved[10]; 651 }; 652 653 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 654 /* This structure holds get storm configuration response and same structure 655 * is used to perform set_storm_cfg 656 */ 657 struct ice_aqc_storm_cfg { 658 __le32 bcast_thresh_size; 659 __le32 mcast_thresh_size; 660 /* Bit 18:0 - Traffic upper threshold size 661 * Bit 31:19 - Reserved 662 */ 663 #define ICE_AQ_THRESHOLD_S 0 664 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 665 666 __le32 storm_ctrl_ctrl; 667 /* Bit 0: MDIPW - Drop Multicast packets in previous window 668 * Bit 1: MDICW - Drop multicast packets in current window 669 * Bit 2: BDIPW - Drop broadcast packets in previous window 670 * Bit 3: BDICW - Drop broadcast packets in current window 671 */ 672 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 673 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 674 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 675 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 676 /* Bit 7:5 : Reserved */ 677 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 678 * interval size for applying ingress broadcast or multicast storm 679 * control. 680 */ 681 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 682 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 683 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 684 __le32 reserved; 685 }; 686 687 #define ICE_MAX_NUM_RECIPES 64 688 689 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 690 struct ice_aqc_add_get_recipe { 691 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 692 __le16 return_index; /* Input, used for Get cmd only */ 693 u8 reserved[4]; 694 __le32 addr_high; 695 __le32 addr_low; 696 }; 697 698 struct ice_aqc_recipe_content { 699 u8 rid; 700 #define ICE_AQ_RECIPE_ID_S 0 701 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 702 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 703 #define ICE_AQ_SW_ID_LKUP_IDX 0 704 u8 lkup_indx[5]; 705 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 706 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 707 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 708 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 709 __le16 mask[5]; 710 u8 result_indx; 711 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 712 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 713 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 714 u8 rsvd0[3]; 715 u8 act_ctrl_join_priority; 716 u8 act_ctrl_fwd_priority; 717 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 718 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 719 u8 act_ctrl; 720 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 721 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 722 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 723 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 724 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 725 u8 rsvd1; 726 __le32 dflt_act; 727 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 728 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 729 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 730 }; 731 732 struct ice_aqc_recipe_data_elem { 733 u8 recipe_indx; 734 u8 resp_bits; 735 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 736 u8 rsvd0[2]; 737 u8 recipe_bitmap[8]; 738 u8 rsvd1[4]; 739 struct ice_aqc_recipe_content content; 740 u8 rsvd2[20]; 741 }; 742 743 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 744 struct ice_aqc_recipe_to_profile { 745 __le16 profile_id; 746 u8 rsvd[6]; 747 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES); 748 }; 749 750 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 751 */ 752 struct ice_aqc_sw_rules { 753 /* ops: add switch rules, referring the number of rules. 754 * ops: update switch rules, referring the number of filters 755 * ops: remove switch rules, referring the entry index. 756 * ops: get switch rules, referring to the number of filters. 757 */ 758 __le16 num_rules_fltr_entry_index; 759 u8 reserved[6]; 760 __le32 addr_high; 761 __le32 addr_low; 762 }; 763 764 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 765 * This structures describes the lookup rules and associated actions. "index" 766 * is returned as part of a response to a successful Add command, and can be 767 * used to identify the rule for Update/Get/Remove commands. 768 */ 769 struct ice_sw_rule_lkup_rx_tx { 770 __le16 recipe_id; 771 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 772 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 773 __le16 src; 774 __le32 act; 775 776 /* Bit 0:1 - Action type */ 777 #define ICE_SINGLE_ACT_TYPE_S 0x00 778 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 779 780 /* Bit 2 - Loop back enable 781 * Bit 3 - LAN enable 782 */ 783 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 784 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 785 786 /* Action type = 0 - Forward to VSI or VSI list */ 787 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 788 789 #define ICE_SINGLE_ACT_VSI_ID_S 4 790 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 791 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 792 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 793 /* This bit needs to be set if action is forward to VSI list */ 794 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 795 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 796 #define ICE_SINGLE_ACT_DROP BIT(18) 797 798 /* Action type = 1 - Forward to Queue of Queue group */ 799 #define ICE_SINGLE_ACT_TO_Q 0x1 800 #define ICE_SINGLE_ACT_Q_INDEX_S 4 801 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 802 #define ICE_SINGLE_ACT_Q_REGION_S 15 803 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 804 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 805 806 /* Action type = 2 - Prune */ 807 #define ICE_SINGLE_ACT_PRUNE 0x2 808 #define ICE_SINGLE_ACT_EGRESS BIT(15) 809 #define ICE_SINGLE_ACT_INGRESS BIT(16) 810 #define ICE_SINGLE_ACT_PRUNET BIT(17) 811 /* Bit 18 should be set to 0 for this action */ 812 813 /* Action type = 2 - Pointer */ 814 #define ICE_SINGLE_ACT_PTR 0x2 815 #define ICE_SINGLE_ACT_PTR_VAL_S 4 816 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 817 /* Bit 18 should be set to 1 */ 818 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 819 820 /* Action type = 3 - Other actions. Last two bits 821 * are other action identifier 822 */ 823 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 824 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 825 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 826 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 827 828 /* Bit 17:18 - Defines other actions */ 829 /* Other action = 0 - Mirror VSI */ 830 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 831 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 832 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 833 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 834 835 /* Other action = 3 - Set Stat count */ 836 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 837 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 838 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 839 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 840 841 __le16 index; /* The index of the rule in the lookup table */ 842 /* Length and values of the header to be matched per recipe or 843 * lookup-type 844 */ 845 __le16 hdr_len; 846 u8 hdr[STRUCT_HACK_VAR_LEN]; 847 }; 848 849 /* Add/Update/Remove large action command/response entry 850 * "index" is returned as part of a response to a successful Add command, and 851 * can be used to identify the action for Update/Get/Remove commands. 852 */ 853 struct ice_sw_rule_lg_act { 854 __le16 index; /* Index in large action table */ 855 __le16 size; 856 /* Max number of large actions */ 857 #define ICE_MAX_LG_ACT 4 858 /* Bit 0:1 - Action type */ 859 #define ICE_LG_ACT_TYPE_S 0 860 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 861 862 /* Action type = 0 - Forward to VSI or VSI list */ 863 #define ICE_LG_ACT_VSI_FORWARDING 0 864 #define ICE_LG_ACT_VSI_ID_S 3 865 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 866 #define ICE_LG_ACT_VSI_LIST_ID_S 3 867 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 868 /* This bit needs to be set if action is forward to VSI list */ 869 #define ICE_LG_ACT_VSI_LIST BIT(13) 870 871 #define ICE_LG_ACT_VALID_BIT BIT(16) 872 873 /* Action type = 1 - Forward to Queue of Queue group */ 874 #define ICE_LG_ACT_TO_Q 0x1 875 #define ICE_LG_ACT_Q_INDEX_S 3 876 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 877 #define ICE_LG_ACT_Q_REGION_S 14 878 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 879 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 880 881 /* Action type = 2 - Prune */ 882 #define ICE_LG_ACT_PRUNE 0x2 883 #define ICE_LG_ACT_EGRESS BIT(14) 884 #define ICE_LG_ACT_INGRESS BIT(15) 885 #define ICE_LG_ACT_PRUNET BIT(16) 886 887 /* Action type = 3 - Mirror VSI */ 888 #define ICE_LG_OTHER_ACT_MIRROR 0x3 889 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 890 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 891 892 /* Action type = 5 - Generic Value */ 893 #define ICE_LG_ACT_GENERIC 0x5 894 #define ICE_LG_ACT_GENERIC_VALUE_S 3 895 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 896 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 897 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 898 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 899 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 900 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 901 902 /* Action = 7 - Set Stat count */ 903 #define ICE_LG_ACT_STAT_COUNT 0x7 904 #define ICE_LG_ACT_STAT_COUNT_S 3 905 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 906 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 907 }; 908 909 /* Add/Update/Remove VSI list command/response entry 910 * "index" is returned as part of a response to a successful Add command, and 911 * can be used to identify the VSI list for Update/Get/Remove commands. 912 */ 913 struct ice_sw_rule_vsi_list { 914 __le16 index; /* Index of VSI/Prune list */ 915 __le16 number_vsi; 916 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 917 }; 918 919 #pragma pack(1) 920 /* Query VSI list command/response entry */ 921 struct ice_sw_rule_vsi_list_query { 922 __le16 index; 923 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 924 }; 925 #pragma pack() 926 927 #pragma pack(1) 928 /* Add switch rule response: 929 * Content of return buffer is same as the input buffer. The status field and 930 * LUT index are updated as part of the response 931 */ 932 struct ice_aqc_sw_rules_elem { 933 __le16 type; /* Switch rule type, one of T_... */ 934 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 935 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 936 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 937 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 938 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 939 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 940 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 941 __le16 status; 942 union { 943 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 944 struct ice_sw_rule_lg_act lg_act; 945 struct ice_sw_rule_vsi_list vsi_list; 946 struct ice_sw_rule_vsi_list_query vsi_list_query; 947 } pdata; 948 }; 949 950 #pragma pack() 951 952 /* PFC Ignore (direct 0x0301) 953 * The command and response use the same descriptor structure 954 */ 955 struct ice_aqc_pfc_ignore { 956 u8 tc_bitmap; 957 u8 cmd_flags; /* unused in response */ 958 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 959 #define ICE_AQC_PFC_IGNORE_CLEAR 0 960 u8 reserved[14]; 961 }; 962 963 /* Set PFC Mode (direct 0x0303) 964 * Query PFC Mode (direct 0x0302) 965 */ 966 struct ice_aqc_set_query_pfc_mode { 967 u8 pfc_mode; 968 /* For Set Command response, reserved in all other cases */ 969 #define ICE_AQC_PFC_NOT_CONFIGURED 0 970 /* For Query Command response, reserved in all other cases */ 971 #define ICE_AQC_DCB_DIS 0 972 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 973 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 974 u8 rsvd[15]; 975 }; 976 977 /* Set DCB Parameters (direct 0x0306) */ 978 struct ice_aqc_set_dcb_params { 979 u8 cmd_flags; /* unused in response */ 980 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 981 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 982 u8 valid_flags; /* unused in response */ 983 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 984 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 985 u8 rsvd[14]; 986 }; 987 988 /* Get Default Topology (indirect 0x0400) */ 989 struct ice_aqc_get_topo { 990 u8 port_num; 991 u8 num_branches; 992 __le16 reserved1; 993 __le32 reserved2; 994 __le32 addr_high; 995 __le32 addr_low; 996 }; 997 998 /* Update TSE (indirect 0x0403) 999 * Get TSE (indirect 0x0404) 1000 * Add TSE (indirect 0x0401) 1001 * Delete TSE (indirect 0x040F) 1002 * Move TSE (indirect 0x0408) 1003 * Suspend Nodes (indirect 0x0409) 1004 * Resume Nodes (indirect 0x040A) 1005 */ 1006 struct ice_aqc_sched_elem_cmd { 1007 __le16 num_elem_req; /* Used by commands */ 1008 __le16 num_elem_resp; /* Used by responses */ 1009 __le32 reserved; 1010 __le32 addr_high; 1011 __le32 addr_low; 1012 }; 1013 1014 struct ice_aqc_txsched_move_grp_info_hdr { 1015 __le32 src_parent_teid; 1016 __le32 dest_parent_teid; 1017 __le16 num_elems; 1018 u8 flags; 1019 u8 reserved; 1020 }; 1021 1022 struct ice_aqc_move_elem { 1023 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1024 __le32 teid[STRUCT_HACK_VAR_LEN]; 1025 }; 1026 1027 struct ice_aqc_elem_info_bw { 1028 __le16 bw_profile_idx; 1029 __le16 bw_alloc; 1030 }; 1031 1032 struct ice_aqc_txsched_elem { 1033 u8 elem_type; /* Special field, reserved for some aq calls */ 1034 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1035 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1036 #define ICE_AQC_ELEM_TYPE_TC 0x2 1037 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1038 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1039 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1040 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1041 u8 valid_sections; 1042 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1043 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1044 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1045 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1046 u8 generic; 1047 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1048 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1049 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1050 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1051 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1052 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1053 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1054 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1055 u8 flags; /* Special field, reserved for some aq calls */ 1056 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1057 struct ice_aqc_elem_info_bw cir_bw; 1058 struct ice_aqc_elem_info_bw eir_bw; 1059 __le16 srl_id; 1060 __le16 reserved2; 1061 }; 1062 1063 struct ice_aqc_txsched_elem_data { 1064 __le32 parent_teid; 1065 __le32 node_teid; 1066 struct ice_aqc_txsched_elem data; 1067 }; 1068 1069 struct ice_aqc_txsched_topo_grp_info_hdr { 1070 __le32 parent_teid; 1071 __le16 num_elems; 1072 __le16 reserved2; 1073 }; 1074 1075 struct ice_aqc_add_elem { 1076 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1077 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1078 }; 1079 1080 struct ice_aqc_get_topo_elem { 1081 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1082 struct ice_aqc_txsched_elem_data 1083 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1084 }; 1085 1086 struct ice_aqc_delete_elem { 1087 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1088 __le32 teid[STRUCT_HACK_VAR_LEN]; 1089 }; 1090 1091 /* Query Port ETS (indirect 0x040E) 1092 * 1093 * This indirect command is used to query port TC node configuration. 1094 */ 1095 struct ice_aqc_query_port_ets { 1096 __le32 port_teid; 1097 __le32 reserved; 1098 __le32 addr_high; 1099 __le32 addr_low; 1100 }; 1101 1102 struct ice_aqc_port_ets_elem { 1103 u8 tc_valid_bits; 1104 u8 reserved[3]; 1105 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1106 __le32 up2tc; 1107 u8 tc_bw_share[8]; 1108 __le32 port_eir_prof_id; 1109 __le32 port_cir_prof_id; 1110 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1111 __le32 tc_node_prio; 1112 #define ICE_TC_NODE_PRIO_S 0x4 1113 u8 reserved1[4]; 1114 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1115 }; 1116 1117 /* Rate limiting profile for 1118 * Add RL profile (indirect 0x0410) 1119 * Query RL profile (indirect 0x0411) 1120 * Remove RL profile (indirect 0x0415) 1121 * These indirect commands acts on single or multiple 1122 * RL profiles with specified data. 1123 */ 1124 struct ice_aqc_rl_profile { 1125 __le16 num_profiles; 1126 __le16 num_processed; /* Only for response. Reserved in Command. */ 1127 u8 reserved[4]; 1128 __le32 addr_high; 1129 __le32 addr_low; 1130 }; 1131 1132 struct ice_aqc_rl_profile_elem { 1133 u8 level; 1134 u8 flags; 1135 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1136 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1137 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1138 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1139 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1140 /* The following flag is used for Query RL Profile Data */ 1141 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1142 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1143 1144 __le16 profile_id; 1145 __le16 max_burst_size; 1146 __le16 rl_multiply; 1147 __le16 wake_up_calc; 1148 __le16 rl_encode; 1149 }; 1150 1151 /* Configure L2 Node CGD (indirect 0x0414) 1152 * This indirect command allows configuring a congestion domain for given L2 1153 * node TEIDs in the scheduler topology. 1154 */ 1155 struct ice_aqc_cfg_l2_node_cgd { 1156 __le16 num_l2_nodes; 1157 u8 reserved[6]; 1158 __le32 addr_high; 1159 __le32 addr_low; 1160 }; 1161 1162 struct ice_aqc_cfg_l2_node_cgd_elem { 1163 __le32 node_teid; 1164 u8 cgd; 1165 u8 reserved[3]; 1166 }; 1167 1168 /* Query Scheduler Resource Allocation (indirect 0x0412) 1169 * This indirect command retrieves the scheduler resources allocated by 1170 * EMP Firmware to the given PF. 1171 */ 1172 struct ice_aqc_query_txsched_res { 1173 u8 reserved[8]; 1174 __le32 addr_high; 1175 __le32 addr_low; 1176 }; 1177 1178 struct ice_aqc_generic_sched_props { 1179 __le16 phys_levels; 1180 __le16 logical_levels; 1181 u8 flattening_bitmap; 1182 u8 max_device_cgds; 1183 u8 max_pf_cgds; 1184 u8 rsvd0; 1185 __le16 rdma_qsets; 1186 u8 rsvd1[22]; 1187 }; 1188 1189 struct ice_aqc_layer_props { 1190 u8 logical_layer; 1191 u8 chunk_size; 1192 __le16 max_device_nodes; 1193 __le16 max_pf_nodes; 1194 u8 rsvd0[4]; 1195 __le16 max_sibl_grp_sz; 1196 __le16 max_cir_rl_profiles; 1197 __le16 max_eir_rl_profiles; 1198 __le16 max_srl_profiles; 1199 u8 rsvd1[14]; 1200 }; 1201 1202 struct ice_aqc_query_txsched_res_resp { 1203 struct ice_aqc_generic_sched_props sched_props; 1204 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1205 }; 1206 1207 /* Query Node to Root Topology (indirect 0x0413) 1208 * This command uses ice_aqc_get_elem as its data buffer. 1209 */ 1210 struct ice_aqc_query_node_to_root { 1211 __le32 teid; 1212 __le32 num_nodes; /* Response only */ 1213 __le32 addr_high; 1214 __le32 addr_low; 1215 }; 1216 1217 /* Get PHY capabilities (indirect 0x0600) */ 1218 struct ice_aqc_get_phy_caps { 1219 u8 lport_num; 1220 u8 reserved; 1221 __le16 param0; 1222 /* 18.0 - Report qualified modules */ 1223 #define ICE_AQC_GET_PHY_RQM BIT(0) 1224 /* 18.1 - 18.3 : Report mode 1225 * 000b - Report NVM capabilities 1226 * 001b - Report topology capabilities 1227 * 010b - Report SW configured 1228 * 100b - Report default capabilities 1229 */ 1230 #define ICE_AQC_REPORT_MODE_S 1 1231 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1232 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1233 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1234 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1235 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1236 __le32 reserved1; 1237 __le32 addr_high; 1238 __le32 addr_low; 1239 }; 1240 1241 /* This is #define of PHY type (Extended): 1242 * The first set of defines is for phy_type_low. 1243 */ 1244 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1245 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1246 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1247 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1248 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1249 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1250 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1251 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1252 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1253 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1254 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1255 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1256 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1257 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1258 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1259 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1260 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1261 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1262 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1263 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1264 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1265 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1266 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1267 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1268 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1269 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1270 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1271 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1272 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1273 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1274 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1275 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1276 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1277 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1278 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1279 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1280 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1281 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1282 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1283 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1284 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1285 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1286 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1287 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1288 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1289 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1290 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1291 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1292 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1293 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1294 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1295 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1296 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1297 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1298 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1299 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1300 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1301 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1302 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1303 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1304 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1305 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1306 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1307 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1308 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1309 /* The second set of defines is for phy_type_high. */ 1310 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1311 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1312 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1313 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1314 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1315 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1316 1317 struct ice_aqc_get_phy_caps_data { 1318 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1319 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1320 u8 caps; 1321 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1322 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1323 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1324 #define ICE_AQC_PHY_EN_LINK BIT(3) 1325 #define ICE_AQC_PHY_AN_MODE BIT(4) 1326 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1327 #define ICE_AQC_PHY_EN_LESM BIT(6) 1328 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1329 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1330 u8 low_power_ctrl_an; 1331 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1332 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1333 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1334 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1335 __le16 eee_cap; 1336 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1337 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1338 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1339 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1340 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1341 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1342 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1343 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1344 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1345 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1346 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1347 __le16 eeer_value; 1348 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1349 u8 phy_fw_ver[8]; 1350 u8 link_fec_options; 1351 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1352 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1353 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1354 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1355 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1356 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1357 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1358 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1359 u8 module_compliance_enforcement; 1360 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1361 u8 extended_compliance_code; 1362 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1363 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1364 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1365 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1366 #define ICE_AQC_MOD_TYPE_IDENT 1 1367 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1368 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1369 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1370 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1371 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1372 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1373 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1374 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1375 u8 qualified_module_count; 1376 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1377 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1378 struct { 1379 u8 v_oui[3]; 1380 u8 rsvd3; 1381 u8 v_part[16]; 1382 __le32 v_rev; 1383 __le64 rsvd4; 1384 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1385 }; 1386 1387 /* Set PHY capabilities (direct 0x0601) 1388 * NOTE: This command must be followed by setup link and restart auto-neg 1389 */ 1390 struct ice_aqc_set_phy_cfg { 1391 u8 lport_num; 1392 u8 reserved[7]; 1393 __le32 addr_high; 1394 __le32 addr_low; 1395 }; 1396 1397 /* Set PHY config command data structure */ 1398 struct ice_aqc_set_phy_cfg_data { 1399 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1400 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1401 u8 caps; 1402 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1403 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1404 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1405 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1406 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1407 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1408 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1409 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1410 u8 low_power_ctrl_an; 1411 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1412 __le16 eeer_value; 1413 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1414 u8 module_compliance_enforcement; 1415 }; 1416 1417 /* Set MAC Config command data structure (direct 0x0603) */ 1418 struct ice_aqc_set_mac_cfg { 1419 __le16 max_frame_size; 1420 u8 params; 1421 #define ICE_AQ_SET_MAC_PACE_S 3 1422 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1423 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1424 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1425 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1426 u8 tx_tmr_priority; 1427 __le16 tx_tmr_value; 1428 __le16 fc_refresh_threshold; 1429 u8 drop_opts; 1430 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1431 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1432 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1433 u8 reserved[7]; 1434 }; 1435 1436 /* Restart AN command data structure (direct 0x0605) 1437 * Also used for response, with only the lport_num field present. 1438 */ 1439 struct ice_aqc_restart_an { 1440 u8 lport_num; 1441 u8 reserved; 1442 u8 cmd_flags; 1443 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1444 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1445 u8 reserved2[13]; 1446 }; 1447 1448 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1449 struct ice_aqc_get_link_status { 1450 u8 lport_num; 1451 u8 reserved; 1452 __le16 cmd_flags; 1453 #define ICE_AQ_LSE_M 0x3 1454 #define ICE_AQ_LSE_NOP 0x0 1455 #define ICE_AQ_LSE_DIS 0x2 1456 #define ICE_AQ_LSE_ENA 0x3 1457 /* only response uses this flag */ 1458 #define ICE_AQ_LSE_IS_ENABLED 0x1 1459 __le32 reserved2; 1460 __le32 addr_high; 1461 __le32 addr_low; 1462 }; 1463 1464 /* Get link status response data structure, also used for Link Status Event */ 1465 struct ice_aqc_get_link_status_data { 1466 u8 topo_media_conflict; 1467 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1468 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1469 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1470 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1471 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1472 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1473 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1474 u8 link_cfg_err; 1475 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1476 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1477 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1478 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1479 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1480 u8 link_info; 1481 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1482 #define ICE_AQ_LINK_FAULT BIT(1) 1483 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1484 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1485 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1486 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1487 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1488 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1489 u8 an_info; 1490 #define ICE_AQ_AN_COMPLETED BIT(0) 1491 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1492 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1493 #define ICE_AQ_FEC_EN BIT(3) 1494 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1495 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1496 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1497 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1498 u8 ext_info; 1499 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1500 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1501 /* Port Tx Suspended */ 1502 #define ICE_AQ_LINK_TX_S 2 1503 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1504 #define ICE_AQ_LINK_TX_ACTIVE 0 1505 #define ICE_AQ_LINK_TX_DRAINED 1 1506 #define ICE_AQ_LINK_TX_FLUSHED 3 1507 u8 lb_status; 1508 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1509 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1510 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1511 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1512 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1513 __le16 max_frame_size; 1514 u8 cfg; 1515 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1516 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1517 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1518 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1519 /* Pacing Config */ 1520 #define ICE_AQ_CFG_PACING_S 3 1521 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1522 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1523 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1524 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1525 /* External Device Power Ability */ 1526 u8 power_desc; 1527 #define ICE_AQ_PWR_CLASS_M 0x3F 1528 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1529 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1530 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1531 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1532 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1533 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1534 __le16 link_speed; 1535 #define ICE_AQ_LINK_SPEED_M 0x7FF 1536 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1537 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1538 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1539 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1540 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1541 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1542 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1543 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1544 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1545 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1546 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1547 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1548 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1549 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1550 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1551 }; 1552 1553 /* Set event mask command (direct 0x0613) */ 1554 struct ice_aqc_set_event_mask { 1555 u8 lport_num; 1556 u8 reserved[7]; 1557 __le16 event_mask; 1558 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1559 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1560 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1561 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1562 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1563 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1564 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1565 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1566 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1567 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1568 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1569 u8 reserved1[6]; 1570 }; 1571 1572 /* Set MAC Loopback command (direct 0x0620) */ 1573 struct ice_aqc_set_mac_lb { 1574 u8 lb_mode; 1575 #define ICE_AQ_MAC_LB_EN BIT(0) 1576 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1577 u8 reserved[15]; 1578 }; 1579 1580 struct ice_aqc_link_topo_addr { 1581 u8 lport_num; 1582 u8 lport_num_valid; 1583 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1584 u8 node_type_ctx; 1585 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1586 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1587 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1588 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1589 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1590 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1591 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1592 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1593 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1594 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1595 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1596 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1597 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1598 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1599 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1600 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1601 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1602 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1603 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1604 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1605 u8 index; 1606 __le16 handle; 1607 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1608 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1609 /* Used to decode the handle field */ 1610 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1611 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1612 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1613 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1614 /* In case of a Mezzanine type */ 1615 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1616 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1617 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1618 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1619 /* In case of a LOM type */ 1620 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1621 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1622 }; 1623 1624 /* Get Link Topology Handle (direct, 0x06E0) */ 1625 struct ice_aqc_get_link_topo { 1626 struct ice_aqc_link_topo_addr addr; 1627 u8 node_part_num; 1628 u8 rsvd[9]; 1629 }; 1630 1631 /* Set Port Identification LED (direct, 0x06E9) */ 1632 struct ice_aqc_set_port_id_led { 1633 u8 lport_num; 1634 u8 lport_num_valid; 1635 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1636 u8 ident_mode; 1637 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1638 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1639 u8 rsvd[13]; 1640 }; 1641 1642 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1643 struct ice_aqc_sff_eeprom { 1644 u8 lport_num; 1645 u8 lport_num_valid; 1646 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1647 __le16 i2c_bus_addr; 1648 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1649 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1650 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1651 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1652 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1653 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1654 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1655 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1656 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1657 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1658 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1659 __le16 i2c_mem_addr; 1660 __le16 eeprom_page; 1661 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1662 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1663 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1664 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1665 __le32 addr_high; 1666 __le32 addr_low; 1667 }; 1668 1669 /* SW Set GPIO command (indirect 0x6EF) 1670 * SW Get GPIO command (indirect 0x6F0) 1671 */ 1672 struct ice_aqc_sw_gpio { 1673 __le16 gpio_ctrl_handle; 1674 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 1675 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 1676 u8 gpio_num; 1677 #define ICE_AQC_SW_GPIO_NUMBER_S 0 1678 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 1679 u8 gpio_params; 1680 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 1681 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 1682 u8 rsvd[12]; 1683 }; 1684 1685 /* NVM Read command (indirect 0x0701) 1686 * NVM Erase commands (direct 0x0702) 1687 * NVM Write commands (indirect 0x0703) 1688 * NVM Write Activate commands (direct 0x0707) 1689 * NVM Shadow RAM Dump commands (direct 0x0707) 1690 */ 1691 struct ice_aqc_nvm { 1692 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1693 __le16 offset_low; 1694 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 1695 u8 cmd_flags; 1696 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1697 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 1698 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 1699 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1700 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1701 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1702 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1703 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1704 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1705 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1706 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1707 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1708 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1709 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 1710 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1711 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ 1712 #define ICE_AQC_NVM_PERST_FLAG 1 1713 #define ICE_AQC_NVM_EMPR_FLAG 2 1714 __le16 module_typeid; 1715 __le16 length; 1716 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1717 __le32 addr_high; 1718 __le32 addr_low; 1719 }; 1720 1721 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 1722 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 1723 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 1724 1725 #define ICE_AQC_NVM_START_POINT 0 1726 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 1727 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 1728 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 1729 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 1730 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 1731 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 1732 1733 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 1734 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 1735 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 1736 1737 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 1738 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 1739 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 1740 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 1741 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 1742 1743 /* Used for 0x0704 as well as for 0x0705 commands */ 1744 struct ice_aqc_nvm_cfg { 1745 u8 cmd_flags; 1746 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 1747 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 1748 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 1749 u8 reserved; 1750 __le16 count; 1751 __le16 id; 1752 u8 reserved1[2]; 1753 __le32 addr_high; 1754 __le32 addr_low; 1755 }; 1756 1757 struct ice_aqc_nvm_cfg_data { 1758 __le16 field_id; 1759 __le16 field_options; 1760 __le16 field_value; 1761 }; 1762 1763 /* NVM Checksum Command (direct, 0x0706) */ 1764 struct ice_aqc_nvm_checksum { 1765 u8 flags; 1766 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1767 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1768 u8 rsvd; 1769 __le16 checksum; /* Used only by response */ 1770 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1771 u8 rsvd2[12]; 1772 }; 1773 1774 /* Get LLDP MIB (indirect 0x0A00) 1775 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1776 * as the format is the same. 1777 */ 1778 struct ice_aqc_lldp_get_mib { 1779 u8 type; 1780 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1781 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1782 #define ICE_AQ_LLDP_MIB_LOCAL 0 1783 #define ICE_AQ_LLDP_MIB_REMOTE 1 1784 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1785 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1786 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1787 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1788 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1789 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1790 #define ICE_AQ_LLDP_TX_S 0x4 1791 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1792 #define ICE_AQ_LLDP_TX_ACTIVE 0 1793 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1794 #define ICE_AQ_LLDP_TX_FLUSHED 3 1795 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1796 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1797 * Get LLDP MIB (0x0A00) response only. 1798 */ 1799 u8 reserved1; 1800 __le16 local_len; 1801 __le16 remote_len; 1802 u8 reserved2[2]; 1803 __le32 addr_high; 1804 __le32 addr_low; 1805 }; 1806 1807 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1808 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1809 struct ice_aqc_lldp_set_mib_change { 1810 u8 command; 1811 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1812 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1813 u8 reserved[15]; 1814 }; 1815 1816 /* Add LLDP TLV (indirect 0x0A02) 1817 * Delete LLDP TLV (indirect 0x0A04) 1818 */ 1819 struct ice_aqc_lldp_add_delete_tlv { 1820 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1821 u8 reserved1[1]; 1822 __le16 len; 1823 u8 reserved2[4]; 1824 __le32 addr_high; 1825 __le32 addr_low; 1826 }; 1827 1828 /* Update LLDP TLV (indirect 0x0A03) */ 1829 struct ice_aqc_lldp_update_tlv { 1830 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1831 u8 reserved; 1832 __le16 old_len; 1833 __le16 new_offset; 1834 __le16 new_len; 1835 __le32 addr_high; 1836 __le32 addr_low; 1837 }; 1838 1839 /* Stop LLDP (direct 0x0A05) */ 1840 struct ice_aqc_lldp_stop { 1841 u8 command; 1842 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1843 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1844 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1845 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1846 u8 reserved[15]; 1847 }; 1848 1849 /* Start LLDP (direct 0x0A06) */ 1850 struct ice_aqc_lldp_start { 1851 u8 command; 1852 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1853 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1854 u8 reserved[15]; 1855 }; 1856 1857 /* Get CEE DCBX Oper Config (0x0A07) 1858 * The command uses the generic descriptor struct and 1859 * returns the struct below as an indirect response. 1860 */ 1861 struct ice_aqc_get_cee_dcb_cfg_resp { 1862 u8 oper_num_tc; 1863 u8 oper_prio_tc[4]; 1864 u8 oper_tc_bw[8]; 1865 u8 oper_pfc_en; 1866 __le16 oper_app_prio; 1867 #define ICE_AQC_CEE_APP_FCOE_S 0 1868 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1869 #define ICE_AQC_CEE_APP_ISCSI_S 3 1870 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1871 #define ICE_AQC_CEE_APP_FIP_S 8 1872 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1873 __le32 tlv_status; 1874 #define ICE_AQC_CEE_PG_STATUS_S 0 1875 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1876 #define ICE_AQC_CEE_PFC_STATUS_S 3 1877 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1878 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1879 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1880 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1881 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1882 #define ICE_AQC_CEE_FIP_STATUS_S 16 1883 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1884 u8 reserved[12]; 1885 }; 1886 1887 /* Set Local LLDP MIB (indirect 0x0A08) 1888 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1889 */ 1890 struct ice_aqc_lldp_set_local_mib { 1891 u8 type; 1892 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1893 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1894 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1895 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1896 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1897 u8 reserved0; 1898 __le16 length; 1899 u8 reserved1[4]; 1900 __le32 addr_high; 1901 __le32 addr_low; 1902 }; 1903 1904 struct ice_aqc_lldp_set_local_mib_resp { 1905 u8 status; 1906 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 1907 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 1908 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 1909 u8 reserved[15]; 1910 }; 1911 1912 /* Stop/Start LLDP Agent (direct 0x0A09) 1913 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1914 * The same structure is used for the response, with the command field 1915 * being used as the status field. 1916 */ 1917 struct ice_aqc_lldp_stop_start_specific_agent { 1918 u8 command; 1919 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1920 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1921 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1922 u8 reserved[15]; 1923 }; 1924 1925 /* LLDP Filter Control (direct 0x0A0A) */ 1926 struct ice_aqc_lldp_filter_ctrl { 1927 u8 cmd_flags; 1928 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 1929 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1930 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1931 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 1932 u8 reserved1; 1933 __le16 vsi_num; 1934 u8 reserved2[12]; 1935 }; 1936 1937 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1938 struct ice_aqc_get_set_rss_key { 1939 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1940 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1941 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1942 __le16 vsi_id; 1943 u8 reserved[6]; 1944 __le32 addr_high; 1945 __le32 addr_low; 1946 }; 1947 1948 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1949 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1950 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1951 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1952 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1953 1954 /** 1955 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 1956 * @standard_rss_key: 40 most significant bytes of hash key 1957 * @extended_hash_key: 12 least significant bytes of hash key 1958 * 1959 * Set/Get 40 byte hash key using standard_rss_key field, and set 1960 * extended_hash_key field to zero. Set/Get 52 byte hash key using 1961 * standard_rss_key field for 40 most significant bytes and the 1962 * extended_hash_key field for the 12 least significant bytes of hash key. 1963 */ 1964 struct ice_aqc_get_set_rss_keys { 1965 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1966 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1967 }; 1968 1969 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1970 struct ice_aqc_get_set_rss_lut { 1971 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1972 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1973 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1974 __le16 vsi_id; 1975 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1976 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1977 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1978 1979 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1980 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1981 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1982 1983 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1984 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1985 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1986 1987 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1988 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1989 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1990 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1991 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1992 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1993 1994 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1995 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1996 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1997 1998 __le16 flags; 1999 __le32 reserved; 2000 __le32 addr_high; 2001 __le32 addr_low; 2002 }; 2003 2004 /* Clear FD Table Command (direct, 0x0B06) */ 2005 struct ice_aqc_clear_fd_table { 2006 u8 clear_type; 2007 #define CL_FD_VM_VF_TYPE_VSI_IDX 1 2008 #define CL_FD_VM_VF_TYPE_PF_IDX 2 2009 u8 rsvd; 2010 __le16 vsi_index; 2011 u8 reserved[12]; 2012 }; 2013 2014 /* Allocate ACL table (indirect 0x0C10) */ 2015 #define ICE_AQC_ACL_KEY_WIDTH 40 2016 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5 2017 #define ICE_AQC_ACL_TCAM_DEPTH 512 2018 #define ICE_ACL_ENTRY_ALLOC_UNIT 64 2019 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15 2020 #define ICE_AQC_MAX_ACTION_MEMORIES 20 2021 #define ICE_AQC_MAX_ACTION_ENTRIES 512 2022 #define ICE_AQC_ACL_SLICES 16 2023 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000 2024 /* The ACL block supports up to 8 actions per a single output. */ 2025 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4 2026 2027 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \ 2028 ICE_ACL_ENTRY_ALLOC_UNIT) 2029 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \ 2030 ICE_AQC_MAX_TCAM_ALLOC_UNITS) 2031 2032 struct ice_aqc_acl_alloc_table { 2033 __le16 table_width; 2034 __le16 table_depth; 2035 u8 act_pairs_per_entry; 2036 /* For non-concurrent table allocation, this field needs 2037 * to be set to zero(0) otherwise it shall specify the 2038 * amount of concurrent tables whose AllocIDs are 2039 * specified in buffer. Thus the newly allocated table 2040 * is concurrent with table IDs specified in AllocIDs. 2041 */ 2042 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0 2043 u8 table_type; 2044 __le16 reserved; 2045 __le32 addr_high; 2046 __le32 addr_low; 2047 }; 2048 2049 /* Allocate ACL table command buffer format */ 2050 struct ice_aqc_acl_alloc_table_data { 2051 /* Dependent table AllocIDs. Each word in this 15 word array specifies 2052 * a dependent table AllocID according to the amount specified in the 2053 * "table_type" field. All unused words shall be set to 0xFFFF 2054 */ 2055 #define ICE_AQC_CONCURR_ID_INVALID 0xffff 2056 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL]; 2057 }; 2058 2059 /* Deallocate ACL table (indirect 0x0C11) 2060 * Allocate ACL action-pair (indirect 0x0C12) 2061 * Deallocate ACL action-pair (indirect 0x0C13) 2062 */ 2063 2064 /* Following structure is common and used in case of deallocation 2065 * of ACL table and action-pair 2066 */ 2067 struct ice_aqc_acl_tbl_actpair { 2068 /* Alloc ID of the table being released */ 2069 __le16 alloc_id; 2070 u8 reserved[6]; 2071 __le32 addr_high; 2072 __le32 addr_low; 2073 }; 2074 2075 /* This response structure is same in case of alloc/dealloc table, 2076 * alloc/dealloc action-pair 2077 */ 2078 struct ice_aqc_acl_generic { 2079 /* if alloc_id is below 0x1000 then alllocation failed due to 2080 * unavailable resources, else this is set by FW to identify 2081 * table allocation 2082 */ 2083 __le16 alloc_id; 2084 2085 union { 2086 /* to be used only in case of alloc/dealloc table */ 2087 struct { 2088 /* Index of the first TCAM block, otherwise set to 0xFF 2089 * for a failed allocation 2090 */ 2091 u8 first_tcam; 2092 /* Index of the last TCAM block. This index shall be 2093 * set to the value of first_tcam for single TCAM block 2094 * allocation, otherwise set to 0xFF for a failed 2095 * allocation 2096 */ 2097 u8 last_tcam; 2098 } table; 2099 /* reserved in case of alloc/dealloc action-pair */ 2100 struct { 2101 __le16 reserved; 2102 } act_pair; 2103 } ops; 2104 2105 /* index of first entry (in both TCAM and action memories), 2106 * otherwise set to 0xFF for a failed allocation 2107 */ 2108 __le16 first_entry; 2109 /* index of last entry (in both TCAM and action memories), 2110 * otherwise set to 0xFF for a failed allocation 2111 */ 2112 __le16 last_entry; 2113 2114 /* Each act_mem element specifies the order of the memory 2115 * otherwise 0xFF 2116 */ 2117 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES]; 2118 }; 2119 2120 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate 2121 * response buffer since original command buffer gets updated with 2122 * 'scen_id' in case of success 2123 */ 2124 struct ice_aqc_acl_alloc_scen { 2125 union { 2126 struct { 2127 u8 reserved[8]; 2128 } cmd; 2129 struct { 2130 __le16 scen_id; 2131 u8 reserved[6]; 2132 } resp; 2133 } ops; 2134 __le32 addr_high; 2135 __le32 addr_low; 2136 }; 2137 2138 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need 2139 * separate response buffer since nothing to be returned as a response 2140 * except status. 2141 */ 2142 struct ice_aqc_acl_dealloc_scen { 2143 __le16 scen_id; 2144 u8 reserved[14]; 2145 }; 2146 2147 /* Update ACL scenario (direct 0x0C1B) 2148 * Query ACL scenario (direct 0x0C23) 2149 */ 2150 struct ice_aqc_acl_update_query_scen { 2151 __le16 scen_id; 2152 u8 reserved[6]; 2153 __le32 addr_high; 2154 __le32 addr_low; 2155 }; 2156 2157 /* Input buffer format in case allocate/update ACL scenario and same format 2158 * is used for response buffer in case of query ACL scenario. 2159 * NOTE: de-allocate ACL scenario is direct command and doesn't require 2160 * "buffer", hence no buffer format. 2161 */ 2162 struct ice_aqc_acl_scen { 2163 struct { 2164 /* Byte [x] selection for the TCAM key. This value must be 2165 * set to 0x0 for unusued TCAM. 2166 * Only Bit 6..0 is used in each byte and MSB is reserved 2167 */ 2168 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F 2169 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20 2170 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E 2171 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE 2172 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F 2173 u8 tcam_select[5]; 2174 /* TCAM Block entry masking. This value should be set to 0x0 for 2175 * unused TCAM 2176 */ 2177 u8 chnk_msk; 2178 /* Bit 0 : masks TCAM entries 0-63 2179 * Bit 1 : masks TCAM entries 64-127 2180 * Bit 2 to 7 : follow the pattern of bit 0 and 1 2181 */ 2182 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0) 2183 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1) 2184 u8 start_cmp_set; 2185 2186 } tcam_cfg[ICE_AQC_ACL_SLICES]; 2187 2188 /* Each byte, Bit 6..0: Action memory association to a TCAM block, 2189 * otherwise it shall be set to 0x0 for disabled memory action. 2190 * Bit 7 : Action memory enable for this scenario 2191 */ 2192 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F 2193 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7) 2194 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES]; 2195 }; 2196 2197 /* Allocate ACL counters (indirect 0x0C16) */ 2198 struct ice_aqc_acl_alloc_counters { 2199 /* Amount of contiguous counters requested. Min value is 1 and 2200 * max value is 255 2201 */ 2202 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1 2203 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF 2204 u8 counter_amount; 2205 2206 /* Counter type: 'single counter' which can be configured to count 2207 * either bytes or packets 2208 */ 2209 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0 2210 2211 /* Counter type: 'counter pair' which counts number of bytes and number 2212 * of packets. 2213 */ 2214 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1 2215 /* requested counter type, single/dual */ 2216 u8 counters_type; 2217 2218 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */ 2219 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3 2220 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */ 2221 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1 2222 /* requested counter bank allocation */ 2223 u8 bank_alloc; 2224 2225 u8 reserved; 2226 2227 union { 2228 /* Applicable only in case of command */ 2229 struct { 2230 u8 reserved[12]; 2231 } cmd; 2232 /* Applicable only in case of response */ 2233 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF 2234 struct { 2235 /* Index of first allocated counter. 0xFFFF in case 2236 * of unsuccessful allocation 2237 */ 2238 __le16 first_counter; 2239 /* Index of last allocated counter. 0xFFFF in case 2240 * of unsuccessful allocation 2241 */ 2242 __le16 last_counter; 2243 u8 rsvd[8]; 2244 } resp; 2245 } ops; 2246 }; 2247 2248 /* De-allocate ACL counters (direct 0x0C17) */ 2249 struct ice_aqc_acl_dealloc_counters { 2250 /* first counter being released */ 2251 __le16 first_counter; 2252 /* last counter being released */ 2253 __le16 last_counter; 2254 /* requested counter type, single/dual */ 2255 u8 counters_type; 2256 /* requested counter bank allocation */ 2257 u8 bank_alloc; 2258 u8 reserved[10]; 2259 }; 2260 2261 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the 2262 * resources allocated for it using a single command 2263 */ 2264 struct ice_aqc_acl_dealloc_res { 2265 u8 reserved[16]; 2266 }; 2267 2268 /* Program ACL actionpair (indirect 0x0C1C) 2269 * Query ACL actionpair (indirect 0x0C25) 2270 */ 2271 struct ice_aqc_acl_actpair { 2272 /* action mem index to program/update */ 2273 u8 act_mem_index; 2274 u8 reserved; 2275 /* The entry index in action memory to be programmed/updated */ 2276 __le16 act_entry_index; 2277 __le32 reserved2; 2278 __le32 addr_high; 2279 __le32 addr_low; 2280 }; 2281 2282 /* Input buffer format for program/query action-pair admin command */ 2283 struct ice_acl_act_entry { 2284 /* Action priority, values must be between 0..7 */ 2285 #define ICE_AQC_ACT_PRIO_VALID_MAX 7 2286 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0) 2287 u8 prio; 2288 /* Action meta-data identifier. This field should be set to 0x0 2289 * for a NOP action 2290 */ 2291 #define ICE_AQC_ACT_MDID_S 8 2292 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S) 2293 u8 mdid; 2294 /* Action value */ 2295 #define ICE_AQC_ACT_VALUE_S 16 2296 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16) 2297 __le16 value; 2298 }; 2299 2300 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2 2301 struct ice_aqc_actpair { 2302 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR]; 2303 }; 2304 2305 /* Generic format used to describe either input or response buffer 2306 * for admin commands related to ACL profile 2307 */ 2308 struct ice_aqc_acl_prof_generic_frmt { 2309 /* The first byte of the byte selection base is reserved to keep the 2310 * first byte of the field vector where the packet direction info is 2311 * available. Thus we should start at index 1 of the field vector to 2312 * map its entries to the byte selection base. 2313 */ 2314 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1 2315 /* In each byte: 2316 * Bit 0..5 = Byte selection for the byte selection base from the 2317 * extracted fields (expressed as byte offset in extracted fields). 2318 * Applicable values are 0..63 2319 * Bit 6..7 = Reserved 2320 */ 2321 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30 2322 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS]; 2323 /* In each byte: 2324 * Bit 0..4 = Word selection for the word selection base from the 2325 * extracted fields (expressed as word offset in extracted fields). 2326 * Applicable values are 0..31 2327 * Bit 5..7 = Reserved 2328 */ 2329 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32 2330 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS]; 2331 /* In each byte: 2332 * Bit 0..3 = Double word selection for the double-word selection base 2333 * from the extracted fields (expressed as double-word offset in 2334 * extracted fields). 2335 * Applicable values are 0..15 2336 * Bit 4..7 = Reserved 2337 */ 2338 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15 2339 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS]; 2340 /* Scenario numbers for individual Physical Function's */ 2341 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8 2342 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS]; 2343 }; 2344 2345 /* Program ACL profile extraction (indirect 0x0C1D) 2346 * Program ACL profile ranges (indirect 0x0C1E) 2347 * Query ACL profile (indirect 0x0C21) 2348 * Query ACL profile ranges (indirect 0x0C22) 2349 */ 2350 struct ice_aqc_acl_profile { 2351 u8 profile_id; /* Programmed/Updated profile ID */ 2352 u8 reserved[7]; 2353 __le32 addr_high; 2354 __le32 addr_low; 2355 }; 2356 2357 /* Input buffer format for program profile extraction admin command and 2358 * response buffer format for query profile admin command is as defined 2359 * in struct ice_aqc_acl_prof_generic_frmt 2360 */ 2361 2362 /* Input buffer format for program profile ranges and query profile ranges 2363 * admin commands. Same format is used for response buffer in case of query 2364 * profile ranges command 2365 */ 2366 struct ice_acl_rng_data { 2367 /* The range checker output shall be sent when the value 2368 * related to this range checker is lower than low boundary 2369 */ 2370 __be16 low_boundary; 2371 /* The range checker output shall be sent when the value 2372 * related to this range checker is higher than high boundary 2373 */ 2374 __be16 high_boundary; 2375 /* A value of '0' in bit shall clear the relevant bit input 2376 * to the range checker 2377 */ 2378 __be16 mask; 2379 }; 2380 2381 struct ice_aqc_acl_profile_ranges { 2382 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8 2383 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG]; 2384 }; 2385 2386 /* Program ACL entry (indirect 0x0C20) 2387 * Query ACL entry (indirect 0x0C24) 2388 */ 2389 struct ice_aqc_acl_entry { 2390 u8 tcam_index; /* Updated TCAM block index */ 2391 u8 reserved; 2392 __le16 entry_index; /* Updated entry index */ 2393 __le32 reserved2; 2394 __le32 addr_high; 2395 __le32 addr_low; 2396 }; 2397 2398 /* Input buffer format in case of program ACL entry and response buffer format 2399 * in case of query ACL entry 2400 */ 2401 struct ice_aqc_acl_data { 2402 /* Entry key and entry key invert are 40 bits wide. 2403 * Byte 0..4 : entry key and Byte 5..7 are reserved 2404 * Byte 8..12: entry key invert and Byte 13..15 are reserved 2405 */ 2406 struct { 2407 u8 val[5]; 2408 u8 reserved[3]; 2409 } entry_key, entry_key_invert; 2410 }; 2411 2412 /* Query ACL counter (direct 0x0C27) */ 2413 struct ice_aqc_acl_query_counter { 2414 /* Queried counter index */ 2415 __le16 counter_index; 2416 /* Queried counter bank */ 2417 u8 counter_bank; 2418 union { 2419 struct { 2420 u8 reserved[13]; 2421 } cmd; 2422 struct { 2423 /* Holds counter value/packet counter value */ 2424 u8 val[5]; 2425 u8 reserved[8]; 2426 } resp; 2427 } ops; 2428 }; 2429 2430 /* Add Tx LAN Queues (indirect 0x0C30) */ 2431 struct ice_aqc_add_txqs { 2432 u8 num_qgrps; 2433 u8 reserved[3]; 2434 __le32 reserved1; 2435 __le32 addr_high; 2436 __le32 addr_low; 2437 }; 2438 2439 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2440 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2441 */ 2442 struct ice_aqc_add_txqs_perq { 2443 __le16 txq_id; 2444 u8 rsvd[2]; 2445 __le32 q_teid; 2446 u8 txq_ctx[22]; 2447 u8 rsvd2[2]; 2448 struct ice_aqc_txsched_elem info; 2449 }; 2450 2451 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2452 * is an array of the following structs. Please note that the length of 2453 * each struct ice_aqc_add_tx_qgrp is variable due 2454 * to the variable number of queues in each group! 2455 */ 2456 struct ice_aqc_add_tx_qgrp { 2457 __le32 parent_teid; 2458 u8 num_txqs; 2459 u8 rsvd[3]; 2460 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2461 }; 2462 2463 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2464 struct ice_aqc_dis_txqs { 2465 u8 cmd_type; 2466 #define ICE_AQC_Q_DIS_CMD_S 0 2467 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2468 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2469 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2470 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2471 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2472 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2473 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2474 u8 num_entries; 2475 __le16 vmvf_and_timeout; 2476 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2477 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2478 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2479 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2480 __le32 blocked_cgds; 2481 __le32 addr_high; 2482 __le32 addr_low; 2483 }; 2484 2485 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2486 * contains the following structures, arrayed one after the 2487 * other. 2488 * Note: Since the q_id is 16 bits wide, if the 2489 * number of queues is even, then 2 bytes of alignment MUST be 2490 * added before the start of the next group, to allow correct 2491 * alignment of the parent_teid field. 2492 */ 2493 #pragma pack(1) 2494 struct ice_aqc_dis_txq_item { 2495 __le32 parent_teid; 2496 u8 num_qs; 2497 u8 rsvd; 2498 /* The length of the q_id array varies according to num_qs */ 2499 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2500 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2501 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2502 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2503 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2504 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2505 }; 2506 2507 #pragma pack() 2508 2509 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2510 struct ice_aqc_txqs_cleanup { 2511 __le16 caller_opc; 2512 __le16 cmd_tag; 2513 u8 reserved[12]; 2514 }; 2515 2516 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2517 struct ice_aqc_move_txqs { 2518 u8 cmd_type; 2519 #define ICE_AQC_Q_CMD_TYPE_S 0 2520 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2521 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2522 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2523 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2524 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2525 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2526 u8 num_qs; 2527 u8 rsvd; 2528 u8 timeout; 2529 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2530 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2531 __le32 blocked_cgds; 2532 __le32 addr_high; 2533 __le32 addr_low; 2534 }; 2535 2536 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2537 struct ice_aqc_move_txqs_elem { 2538 __le16 txq_id; 2539 u8 q_cgd; 2540 u8 rsvd; 2541 __le32 q_teid; 2542 }; 2543 2544 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2545 struct ice_aqc_move_txqs_data { 2546 __le32 src_teid; 2547 __le32 dest_teid; 2548 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2549 }; 2550 2551 /* Download Package (indirect 0x0C40) */ 2552 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2553 struct ice_aqc_download_pkg { 2554 u8 flags; 2555 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2556 u8 reserved[3]; 2557 __le32 reserved1; 2558 __le32 addr_high; 2559 __le32 addr_low; 2560 }; 2561 2562 struct ice_aqc_download_pkg_resp { 2563 __le32 error_offset; 2564 __le32 error_info; 2565 __le32 addr_high; 2566 __le32 addr_low; 2567 }; 2568 2569 /* Get Package Info List (indirect 0x0C43) */ 2570 struct ice_aqc_get_pkg_info_list { 2571 __le32 reserved1; 2572 __le32 reserved2; 2573 __le32 addr_high; 2574 __le32 addr_low; 2575 }; 2576 2577 /* Version format for packages */ 2578 struct ice_pkg_ver { 2579 u8 major; 2580 u8 minor; 2581 u8 update; 2582 u8 draft; 2583 }; 2584 2585 #define ICE_PKG_NAME_SIZE 32 2586 #define ICE_SEG_ID_SIZE 28 2587 #define ICE_SEG_NAME_SIZE 28 2588 2589 struct ice_aqc_get_pkg_info { 2590 struct ice_pkg_ver ver; 2591 char name[ICE_SEG_NAME_SIZE]; 2592 __le32 track_id; 2593 u8 is_in_nvm; 2594 u8 is_active; 2595 u8 is_active_at_boot; 2596 u8 is_modified; 2597 }; 2598 2599 /* Get Package Info List response buffer format (0x0C43) */ 2600 struct ice_aqc_get_pkg_info_resp { 2601 __le32 count; 2602 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2603 }; 2604 2605 /* Driver Shared Parameters (direct, 0x0C90) */ 2606 struct ice_aqc_driver_shared_params { 2607 u8 set_or_get_op; 2608 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2609 #define ICE_AQC_DRIVER_PARAM_SET 0 2610 #define ICE_AQC_DRIVER_PARAM_GET 1 2611 u8 param_indx; 2612 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2613 u8 rsvd[2]; 2614 __le32 param_val; 2615 __le32 addr_high; 2616 __le32 addr_low; 2617 }; 2618 2619 /* Lan Queue Overflow Event (direct, 0x1001) */ 2620 struct ice_aqc_event_lan_overflow { 2621 __le32 prtdcb_ruptq; 2622 __le32 qtx_ctl; 2623 u8 reserved[8]; 2624 }; 2625 2626 /* Set Health Status (direct 0xFF20) */ 2627 struct ice_aqc_set_health_status_config { 2628 u8 event_source; 2629 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2630 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2631 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2632 u8 reserved[15]; 2633 }; 2634 2635 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2636 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2637 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2638 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2639 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2640 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2641 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2642 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2643 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2644 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2645 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2646 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2647 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2648 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2649 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2650 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2651 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2652 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2653 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2654 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2655 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2656 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2657 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2658 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2659 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2660 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2661 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2662 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2663 2664 /* Get Health Status codes (indirect 0xFF21) */ 2665 struct ice_aqc_get_supported_health_status_codes { 2666 __le16 health_code_count; 2667 u8 reserved[6]; 2668 __le32 addr_high; 2669 __le32 addr_low; 2670 }; 2671 2672 /* Get Health Status (indirect 0xFF22) */ 2673 struct ice_aqc_get_health_status { 2674 __le16 health_status_count; 2675 u8 reserved[6]; 2676 __le32 addr_high; 2677 __le32 addr_low; 2678 }; 2679 2680 /* Get Health Status event buffer entry, (0xFF22) 2681 * repeated per reported health status 2682 */ 2683 struct ice_aqc_health_status_elem { 2684 __le16 health_status_code; 2685 __le16 event_source; 2686 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2687 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2688 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2689 __le32 internal_data1; 2690 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2691 __le32 internal_data2; 2692 }; 2693 2694 /* Clear Health Status (direct 0xFF23) */ 2695 struct ice_aqc_clear_health_status { 2696 __le32 reserved[4]; 2697 }; 2698 2699 /** 2700 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2701 * @flags: ICE_AQ_FLAG_* flags 2702 * @opcode: AQ command opcode 2703 * @datalen: length in bytes of indirect/external data buffer 2704 * @retval: return value from firmware 2705 * @cookie_high: opaque data high-half 2706 * @cookie_low: opaque data low-half 2707 * @params: command-specific parameters 2708 * 2709 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2710 * (ATQ). The firmware writes back onto the command descriptor and returns 2711 * the result of the command. Asynchronous events that are not an immediate 2712 * result of the command are written to the Admin Receive Queue (ARQ) using 2713 * the same descriptor format. Descriptors are in little-endian notation with 2714 * 32-bit words. 2715 */ 2716 struct ice_aq_desc { 2717 __le16 flags; 2718 __le16 opcode; 2719 __le16 datalen; 2720 __le16 retval; 2721 __le32 cookie_high; 2722 __le32 cookie_low; 2723 union { 2724 u8 raw[16]; 2725 struct ice_aqc_generic generic; 2726 struct ice_aqc_get_ver get_ver; 2727 struct ice_aqc_driver_ver driver_ver; 2728 struct ice_aqc_q_shutdown q_shutdown; 2729 struct ice_aqc_req_res res_owner; 2730 struct ice_aqc_manage_mac_read mac_read; 2731 struct ice_aqc_manage_mac_write mac_write; 2732 struct ice_aqc_clear_pxe clear_pxe; 2733 struct ice_aqc_config_no_drop_policy no_drop; 2734 struct ice_aqc_add_update_mir_rule add_update_rule; 2735 struct ice_aqc_delete_mir_rule del_rule; 2736 struct ice_aqc_list_caps get_cap; 2737 struct ice_aqc_get_phy_caps get_phy; 2738 struct ice_aqc_set_phy_cfg set_phy; 2739 struct ice_aqc_restart_an restart_an; 2740 struct ice_aqc_sff_eeprom read_write_sff_param; 2741 struct ice_aqc_set_port_id_led set_port_id_led; 2742 struct ice_aqc_get_sw_cfg get_sw_conf; 2743 struct ice_aqc_set_port_params set_port_params; 2744 struct ice_aqc_sw_rules sw_rules; 2745 struct ice_aqc_storm_cfg storm_conf; 2746 struct ice_aqc_add_get_recipe add_get_recipe; 2747 struct ice_aqc_recipe_to_profile recipe_to_profile; 2748 struct ice_aqc_get_topo get_topo; 2749 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2750 struct ice_aqc_query_txsched_res query_sched_res; 2751 struct ice_aqc_query_node_to_root query_node_to_root; 2752 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2753 struct ice_aqc_query_port_ets port_ets; 2754 struct ice_aqc_rl_profile rl_profile; 2755 struct ice_aqc_nvm nvm; 2756 struct ice_aqc_nvm_cfg nvm_cfg; 2757 struct ice_aqc_nvm_checksum nvm_checksum; 2758 struct ice_aqc_pfc_ignore pfc_ignore; 2759 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2760 struct ice_aqc_set_dcb_params set_dcb_params; 2761 struct ice_aqc_lldp_get_mib lldp_get_mib; 2762 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2763 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2764 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2765 struct ice_aqc_lldp_stop lldp_stop; 2766 struct ice_aqc_lldp_start lldp_start; 2767 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2768 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2769 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2770 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2771 struct ice_aqc_get_set_rss_key get_set_rss_key; 2772 struct ice_aqc_clear_fd_table clear_fd_table; 2773 struct ice_aqc_acl_alloc_table alloc_table; 2774 struct ice_aqc_acl_tbl_actpair tbl_actpair; 2775 struct ice_aqc_acl_alloc_scen alloc_scen; 2776 struct ice_aqc_acl_dealloc_scen dealloc_scen; 2777 struct ice_aqc_acl_update_query_scen update_query_scen; 2778 struct ice_aqc_acl_alloc_counters alloc_counters; 2779 struct ice_aqc_acl_dealloc_counters dealloc_counters; 2780 struct ice_aqc_acl_dealloc_res dealloc_res; 2781 struct ice_aqc_acl_entry program_query_entry; 2782 struct ice_aqc_acl_actpair program_query_actpair; 2783 struct ice_aqc_acl_profile profile; 2784 struct ice_aqc_acl_query_counter query_counter; 2785 struct ice_aqc_add_txqs add_txqs; 2786 struct ice_aqc_dis_txqs dis_txqs; 2787 struct ice_aqc_move_txqs move_txqs; 2788 struct ice_aqc_txqs_cleanup txqs_cleanup; 2789 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2790 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2791 struct ice_aqc_get_vsi_resp get_vsi_resp; 2792 struct ice_aqc_download_pkg download_pkg; 2793 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2794 struct ice_aqc_driver_shared_params drv_shared_params; 2795 struct ice_aqc_set_mac_lb set_mac_lb; 2796 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2797 struct ice_aqc_get_res_alloc get_res; 2798 struct ice_aqc_get_allocd_res_desc get_res_desc; 2799 struct ice_aqc_set_mac_cfg set_mac_cfg; 2800 struct ice_aqc_set_event_mask set_event_mask; 2801 struct ice_aqc_get_link_status get_link_status; 2802 struct ice_aqc_event_lan_overflow lan_overflow; 2803 struct ice_aqc_get_link_topo get_link_topo; 2804 struct ice_aqc_set_health_status_config 2805 set_health_status_config; 2806 struct ice_aqc_get_supported_health_status_codes 2807 get_supported_health_status_codes; 2808 struct ice_aqc_get_health_status get_health_status; 2809 struct ice_aqc_clear_health_status clear_health_status; 2810 } params; 2811 }; 2812 2813 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2814 #define ICE_AQ_LG_BUF 512 2815 2816 /* Flags sub-structure 2817 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2818 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2819 */ 2820 2821 /* command flags and offsets */ 2822 #define ICE_AQ_FLAG_DD_S 0 2823 #define ICE_AQ_FLAG_CMP_S 1 2824 #define ICE_AQ_FLAG_ERR_S 2 2825 #define ICE_AQ_FLAG_VFE_S 3 2826 #define ICE_AQ_FLAG_LB_S 9 2827 #define ICE_AQ_FLAG_RD_S 10 2828 #define ICE_AQ_FLAG_VFC_S 11 2829 #define ICE_AQ_FLAG_BUF_S 12 2830 #define ICE_AQ_FLAG_SI_S 13 2831 #define ICE_AQ_FLAG_EI_S 14 2832 #define ICE_AQ_FLAG_FE_S 15 2833 2834 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2835 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2836 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2837 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2838 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2839 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2840 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2841 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2842 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2843 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2844 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2845 2846 /* error codes */ 2847 enum ice_aq_err { 2848 ICE_AQ_RC_OK = 0, /* Success */ 2849 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2850 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2851 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2852 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2853 ICE_AQ_RC_EIO = 5, /* I/O error */ 2854 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2855 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2856 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2857 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2858 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2859 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2860 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2861 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2862 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2863 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2864 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2865 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2866 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2867 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2868 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2869 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2870 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2871 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2872 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2873 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2874 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2875 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2876 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2877 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2878 }; 2879 2880 /* Admin Queue command opcodes */ 2881 enum ice_adminq_opc { 2882 /* AQ commands */ 2883 ice_aqc_opc_get_ver = 0x0001, 2884 ice_aqc_opc_driver_ver = 0x0002, 2885 ice_aqc_opc_q_shutdown = 0x0003, 2886 ice_aqc_opc_get_exp_err = 0x0005, 2887 2888 /* resource ownership */ 2889 ice_aqc_opc_req_res = 0x0008, 2890 ice_aqc_opc_release_res = 0x0009, 2891 2892 /* device/function capabilities */ 2893 ice_aqc_opc_list_func_caps = 0x000A, 2894 ice_aqc_opc_list_dev_caps = 0x000B, 2895 2896 /* manage MAC address */ 2897 ice_aqc_opc_manage_mac_read = 0x0107, 2898 ice_aqc_opc_manage_mac_write = 0x0108, 2899 2900 /* PXE */ 2901 ice_aqc_opc_clear_pxe_mode = 0x0110, 2902 2903 ice_aqc_opc_config_no_drop_policy = 0x0112, 2904 2905 /* internal switch commands */ 2906 ice_aqc_opc_get_sw_cfg = 0x0200, 2907 ice_aqc_opc_set_port_params = 0x0203, 2908 2909 /* Alloc/Free/Get Resources */ 2910 ice_aqc_opc_get_res_alloc = 0x0204, 2911 ice_aqc_opc_alloc_res = 0x0208, 2912 ice_aqc_opc_free_res = 0x0209, 2913 ice_aqc_opc_get_allocd_res_desc = 0x020A, 2914 2915 /* VSI commands */ 2916 ice_aqc_opc_add_vsi = 0x0210, 2917 ice_aqc_opc_update_vsi = 0x0211, 2918 ice_aqc_opc_get_vsi_params = 0x0212, 2919 ice_aqc_opc_free_vsi = 0x0213, 2920 2921 /* Mirroring rules - add/update, delete */ 2922 ice_aqc_opc_add_update_mir_rule = 0x0260, 2923 ice_aqc_opc_del_mir_rule = 0x0261, 2924 2925 /* storm configuration */ 2926 ice_aqc_opc_set_storm_cfg = 0x0280, 2927 ice_aqc_opc_get_storm_cfg = 0x0281, 2928 2929 /* recipe commands */ 2930 ice_aqc_opc_add_recipe = 0x0290, 2931 ice_aqc_opc_recipe_to_profile = 0x0291, 2932 ice_aqc_opc_get_recipe = 0x0292, 2933 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2934 2935 /* switch rules population commands */ 2936 ice_aqc_opc_add_sw_rules = 0x02A0, 2937 ice_aqc_opc_update_sw_rules = 0x02A1, 2938 ice_aqc_opc_remove_sw_rules = 0x02A2, 2939 ice_aqc_opc_get_sw_rules = 0x02A3, 2940 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2941 2942 /* DCB commands */ 2943 ice_aqc_opc_pfc_ignore = 0x0301, 2944 ice_aqc_opc_query_pfc_mode = 0x0302, 2945 ice_aqc_opc_set_pfc_mode = 0x0303, 2946 ice_aqc_opc_set_dcb_params = 0x0306, 2947 2948 /* transmit scheduler commands */ 2949 ice_aqc_opc_get_dflt_topo = 0x0400, 2950 ice_aqc_opc_add_sched_elems = 0x0401, 2951 ice_aqc_opc_cfg_sched_elems = 0x0403, 2952 ice_aqc_opc_get_sched_elems = 0x0404, 2953 ice_aqc_opc_move_sched_elems = 0x0408, 2954 ice_aqc_opc_suspend_sched_elems = 0x0409, 2955 ice_aqc_opc_resume_sched_elems = 0x040A, 2956 ice_aqc_opc_query_port_ets = 0x040E, 2957 ice_aqc_opc_delete_sched_elems = 0x040F, 2958 ice_aqc_opc_add_rl_profiles = 0x0410, 2959 ice_aqc_opc_query_rl_profiles = 0x0411, 2960 ice_aqc_opc_query_sched_res = 0x0412, 2961 ice_aqc_opc_query_node_to_root = 0x0413, 2962 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 2963 ice_aqc_opc_remove_rl_profiles = 0x0415, 2964 2965 /* PHY commands */ 2966 ice_aqc_opc_get_phy_caps = 0x0600, 2967 ice_aqc_opc_set_phy_cfg = 0x0601, 2968 ice_aqc_opc_set_mac_cfg = 0x0603, 2969 ice_aqc_opc_restart_an = 0x0605, 2970 ice_aqc_opc_get_link_status = 0x0607, 2971 ice_aqc_opc_set_event_mask = 0x0613, 2972 ice_aqc_opc_set_mac_lb = 0x0620, 2973 ice_aqc_opc_get_link_topo = 0x06E0, 2974 ice_aqc_opc_set_port_id_led = 0x06E9, 2975 ice_aqc_opc_get_port_options = 0x06EA, 2976 ice_aqc_opc_set_port_option = 0x06EB, 2977 ice_aqc_opc_set_gpio = 0x06EC, 2978 ice_aqc_opc_get_gpio = 0x06ED, 2979 ice_aqc_opc_sff_eeprom = 0x06EE, 2980 ice_aqc_opc_sw_set_gpio = 0x06EF, 2981 ice_aqc_opc_sw_get_gpio = 0x06F0, 2982 2983 /* NVM commands */ 2984 ice_aqc_opc_nvm_read = 0x0701, 2985 ice_aqc_opc_nvm_erase = 0x0702, 2986 ice_aqc_opc_nvm_write = 0x0703, 2987 ice_aqc_opc_nvm_cfg_read = 0x0704, 2988 ice_aqc_opc_nvm_cfg_write = 0x0705, 2989 ice_aqc_opc_nvm_checksum = 0x0706, 2990 ice_aqc_opc_nvm_write_activate = 0x0707, 2991 ice_aqc_opc_nvm_sr_dump = 0x0707, 2992 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 2993 ice_aqc_opc_nvm_update_empr = 0x0709, 2994 2995 /* LLDP commands */ 2996 ice_aqc_opc_lldp_get_mib = 0x0A00, 2997 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2998 ice_aqc_opc_lldp_add_tlv = 0x0A02, 2999 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3000 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3001 ice_aqc_opc_lldp_stop = 0x0A05, 3002 ice_aqc_opc_lldp_start = 0x0A06, 3003 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3004 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3005 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3006 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3007 3008 /* RSS commands */ 3009 ice_aqc_opc_set_rss_key = 0x0B02, 3010 ice_aqc_opc_set_rss_lut = 0x0B03, 3011 ice_aqc_opc_get_rss_key = 0x0B04, 3012 ice_aqc_opc_get_rss_lut = 0x0B05, 3013 ice_aqc_opc_clear_fd_table = 0x0B06, 3014 /* ACL commands */ 3015 ice_aqc_opc_alloc_acl_tbl = 0x0C10, 3016 ice_aqc_opc_dealloc_acl_tbl = 0x0C11, 3017 ice_aqc_opc_alloc_acl_actpair = 0x0C12, 3018 ice_aqc_opc_dealloc_acl_actpair = 0x0C13, 3019 ice_aqc_opc_alloc_acl_scen = 0x0C14, 3020 ice_aqc_opc_dealloc_acl_scen = 0x0C15, 3021 ice_aqc_opc_alloc_acl_counters = 0x0C16, 3022 ice_aqc_opc_dealloc_acl_counters = 0x0C17, 3023 ice_aqc_opc_dealloc_acl_res = 0x0C1A, 3024 ice_aqc_opc_update_acl_scen = 0x0C1B, 3025 ice_aqc_opc_program_acl_actpair = 0x0C1C, 3026 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D, 3027 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E, 3028 ice_aqc_opc_program_acl_entry = 0x0C20, 3029 ice_aqc_opc_query_acl_prof = 0x0C21, 3030 ice_aqc_opc_query_acl_prof_ranges = 0x0C22, 3031 ice_aqc_opc_query_acl_scen = 0x0C23, 3032 ice_aqc_opc_query_acl_entry = 0x0C24, 3033 ice_aqc_opc_query_acl_actpair = 0x0C25, 3034 ice_aqc_opc_query_acl_counter = 0x0C27, 3035 3036 /* Tx queue handling commands/events */ 3037 ice_aqc_opc_add_txqs = 0x0C30, 3038 ice_aqc_opc_dis_txqs = 0x0C31, 3039 ice_aqc_opc_txqs_cleanup = 0x0C31, 3040 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3041 3042 /* package commands */ 3043 ice_aqc_opc_download_pkg = 0x0C40, 3044 ice_aqc_opc_upload_section = 0x0C41, 3045 ice_aqc_opc_update_pkg = 0x0C42, 3046 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3047 3048 ice_aqc_opc_driver_shared_params = 0x0C90, 3049 3050 /* Standalone Commands/Events */ 3051 ice_aqc_opc_event_lan_overflow = 0x1001, 3052 3053 /* SystemDiagnostic commands */ 3054 ice_aqc_opc_set_health_status_config = 0xFF20, 3055 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3056 ice_aqc_opc_get_health_status = 0xFF22, 3057 ice_aqc_opc_clear_health_status = 0xFF23 3058 }; 3059 3060 #endif /* _ICE_ADMINQ_CMD_H_ */ 3061