1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 13 #include <rte_debug.h> 14 #include <rte_ether.h> 15 #include <ethdev_driver.h> 16 #include <rte_log.h> 17 #include <rte_malloc.h> 18 #include <rte_tailq.h> 19 #include <rte_flow_driver.h> 20 #include <rte_bitmap.h> 21 22 #include "i40e_logs.h" 23 #include "base/i40e_type.h" 24 #include "base/i40e_prototype.h" 25 #include "i40e_ethdev.h" 26 #include "i40e_hash.h" 27 28 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET) 29 #define I40E_IPV6_FRAG_HEADER 44 30 #define I40E_TENANT_ARRAY_NUM 3 31 #define I40E_VLAN_TCI_MASK 0xFFFF 32 #define I40E_VLAN_PRI_MASK 0xE000 33 #define I40E_VLAN_CFI_MASK 0x1000 34 #define I40E_VLAN_VID_MASK 0x0FFF 35 36 static int i40e_flow_validate(struct rte_eth_dev *dev, 37 const struct rte_flow_attr *attr, 38 const struct rte_flow_item pattern[], 39 const struct rte_flow_action actions[], 40 struct rte_flow_error *error); 41 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev, 42 const struct rte_flow_attr *attr, 43 const struct rte_flow_item pattern[], 44 const struct rte_flow_action actions[], 45 struct rte_flow_error *error); 46 static int i40e_flow_destroy(struct rte_eth_dev *dev, 47 struct rte_flow *flow, 48 struct rte_flow_error *error); 49 static int i40e_flow_flush(struct rte_eth_dev *dev, 50 struct rte_flow_error *error); 51 static int i40e_flow_query(struct rte_eth_dev *dev, 52 struct rte_flow *flow, 53 const struct rte_flow_action *actions, 54 void *data, struct rte_flow_error *error); 55 static int 56 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev, 57 const struct rte_flow_item *pattern, 58 struct rte_flow_error *error, 59 struct rte_eth_ethertype_filter *filter); 60 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev, 61 const struct rte_flow_action *actions, 62 struct rte_flow_error *error, 63 struct rte_eth_ethertype_filter *filter); 64 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev, 65 const struct rte_flow_attr *attr, 66 const struct rte_flow_item *pattern, 67 struct rte_flow_error *error, 68 struct i40e_fdir_filter_conf *filter); 69 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev, 70 const struct rte_flow_action *actions, 71 struct rte_flow_error *error, 72 struct i40e_fdir_filter_conf *filter); 73 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev, 74 const struct rte_flow_action *actions, 75 struct rte_flow_error *error, 76 struct i40e_tunnel_filter_conf *filter); 77 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr, 78 struct rte_flow_error *error); 79 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev, 80 const struct rte_flow_attr *attr, 81 const struct rte_flow_item pattern[], 82 const struct rte_flow_action actions[], 83 struct rte_flow_error *error, 84 union i40e_filter_t *filter); 85 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev, 86 const struct rte_flow_attr *attr, 87 const struct rte_flow_item pattern[], 88 const struct rte_flow_action actions[], 89 struct rte_flow_error *error, 90 union i40e_filter_t *filter); 91 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev, 92 const struct rte_flow_attr *attr, 93 const struct rte_flow_item pattern[], 94 const struct rte_flow_action actions[], 95 struct rte_flow_error *error, 96 union i40e_filter_t *filter); 97 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev, 98 const struct rte_flow_attr *attr, 99 const struct rte_flow_item pattern[], 100 const struct rte_flow_action actions[], 101 struct rte_flow_error *error, 102 union i40e_filter_t *filter); 103 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev, 104 const struct rte_flow_attr *attr, 105 const struct rte_flow_item pattern[], 106 const struct rte_flow_action actions[], 107 struct rte_flow_error *error, 108 union i40e_filter_t *filter); 109 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev, 110 const struct rte_flow_attr *attr, 111 const struct rte_flow_item pattern[], 112 const struct rte_flow_action actions[], 113 struct rte_flow_error *error, 114 union i40e_filter_t *filter); 115 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf, 116 struct i40e_ethertype_filter *filter); 117 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf, 118 struct i40e_tunnel_filter *filter); 119 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf); 120 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf); 121 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf); 122 static int 123 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev, 124 const struct rte_flow_attr *attr, 125 const struct rte_flow_item pattern[], 126 const struct rte_flow_action actions[], 127 struct rte_flow_error *error, 128 union i40e_filter_t *filter); 129 static int 130 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev, 131 const struct rte_flow_item *pattern, 132 struct rte_flow_error *error, 133 struct i40e_tunnel_filter_conf *filter); 134 135 static int i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev, 136 const struct rte_flow_attr *attr, 137 const struct rte_flow_item pattern[], 138 const struct rte_flow_action actions[], 139 struct rte_flow_error *error, 140 union i40e_filter_t *filter); 141 const struct rte_flow_ops i40e_flow_ops = { 142 .validate = i40e_flow_validate, 143 .create = i40e_flow_create, 144 .destroy = i40e_flow_destroy, 145 .flush = i40e_flow_flush, 146 .query = i40e_flow_query, 147 }; 148 149 static union i40e_filter_t cons_filter; 150 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE; 151 /* internal pattern w/o VOID items */ 152 struct rte_flow_item g_items[32]; 153 154 /* Pattern matched ethertype filter */ 155 static enum rte_flow_item_type pattern_ethertype[] = { 156 RTE_FLOW_ITEM_TYPE_ETH, 157 RTE_FLOW_ITEM_TYPE_END, 158 }; 159 160 /* Pattern matched flow director filter */ 161 static enum rte_flow_item_type pattern_fdir_ipv4[] = { 162 RTE_FLOW_ITEM_TYPE_ETH, 163 RTE_FLOW_ITEM_TYPE_IPV4, 164 RTE_FLOW_ITEM_TYPE_END, 165 }; 166 167 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = { 168 RTE_FLOW_ITEM_TYPE_ETH, 169 RTE_FLOW_ITEM_TYPE_IPV4, 170 RTE_FLOW_ITEM_TYPE_UDP, 171 RTE_FLOW_ITEM_TYPE_END, 172 }; 173 174 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = { 175 RTE_FLOW_ITEM_TYPE_ETH, 176 RTE_FLOW_ITEM_TYPE_IPV4, 177 RTE_FLOW_ITEM_TYPE_TCP, 178 RTE_FLOW_ITEM_TYPE_END, 179 }; 180 181 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = { 182 RTE_FLOW_ITEM_TYPE_ETH, 183 RTE_FLOW_ITEM_TYPE_IPV4, 184 RTE_FLOW_ITEM_TYPE_SCTP, 185 RTE_FLOW_ITEM_TYPE_END, 186 }; 187 188 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = { 189 RTE_FLOW_ITEM_TYPE_ETH, 190 RTE_FLOW_ITEM_TYPE_IPV4, 191 RTE_FLOW_ITEM_TYPE_UDP, 192 RTE_FLOW_ITEM_TYPE_GTPC, 193 RTE_FLOW_ITEM_TYPE_END, 194 }; 195 196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = { 197 RTE_FLOW_ITEM_TYPE_ETH, 198 RTE_FLOW_ITEM_TYPE_IPV4, 199 RTE_FLOW_ITEM_TYPE_UDP, 200 RTE_FLOW_ITEM_TYPE_GTPU, 201 RTE_FLOW_ITEM_TYPE_END, 202 }; 203 204 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = { 205 RTE_FLOW_ITEM_TYPE_ETH, 206 RTE_FLOW_ITEM_TYPE_IPV4, 207 RTE_FLOW_ITEM_TYPE_UDP, 208 RTE_FLOW_ITEM_TYPE_GTPU, 209 RTE_FLOW_ITEM_TYPE_IPV4, 210 RTE_FLOW_ITEM_TYPE_END, 211 }; 212 213 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = { 214 RTE_FLOW_ITEM_TYPE_ETH, 215 RTE_FLOW_ITEM_TYPE_IPV4, 216 RTE_FLOW_ITEM_TYPE_UDP, 217 RTE_FLOW_ITEM_TYPE_GTPU, 218 RTE_FLOW_ITEM_TYPE_IPV6, 219 RTE_FLOW_ITEM_TYPE_END, 220 }; 221 222 static enum rte_flow_item_type pattern_fdir_ipv6[] = { 223 RTE_FLOW_ITEM_TYPE_ETH, 224 RTE_FLOW_ITEM_TYPE_IPV6, 225 RTE_FLOW_ITEM_TYPE_END, 226 }; 227 228 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = { 229 RTE_FLOW_ITEM_TYPE_ETH, 230 RTE_FLOW_ITEM_TYPE_IPV6, 231 RTE_FLOW_ITEM_TYPE_UDP, 232 RTE_FLOW_ITEM_TYPE_END, 233 }; 234 235 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = { 236 RTE_FLOW_ITEM_TYPE_ETH, 237 RTE_FLOW_ITEM_TYPE_IPV6, 238 RTE_FLOW_ITEM_TYPE_TCP, 239 RTE_FLOW_ITEM_TYPE_END, 240 }; 241 242 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = { 243 RTE_FLOW_ITEM_TYPE_ETH, 244 RTE_FLOW_ITEM_TYPE_IPV6, 245 RTE_FLOW_ITEM_TYPE_SCTP, 246 RTE_FLOW_ITEM_TYPE_END, 247 }; 248 249 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = { 250 RTE_FLOW_ITEM_TYPE_ETH, 251 RTE_FLOW_ITEM_TYPE_IPV6, 252 RTE_FLOW_ITEM_TYPE_UDP, 253 RTE_FLOW_ITEM_TYPE_GTPC, 254 RTE_FLOW_ITEM_TYPE_END, 255 }; 256 257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = { 258 RTE_FLOW_ITEM_TYPE_ETH, 259 RTE_FLOW_ITEM_TYPE_IPV6, 260 RTE_FLOW_ITEM_TYPE_UDP, 261 RTE_FLOW_ITEM_TYPE_GTPU, 262 RTE_FLOW_ITEM_TYPE_END, 263 }; 264 265 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = { 266 RTE_FLOW_ITEM_TYPE_ETH, 267 RTE_FLOW_ITEM_TYPE_IPV6, 268 RTE_FLOW_ITEM_TYPE_UDP, 269 RTE_FLOW_ITEM_TYPE_GTPU, 270 RTE_FLOW_ITEM_TYPE_IPV4, 271 RTE_FLOW_ITEM_TYPE_END, 272 }; 273 274 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = { 275 RTE_FLOW_ITEM_TYPE_ETH, 276 RTE_FLOW_ITEM_TYPE_IPV6, 277 RTE_FLOW_ITEM_TYPE_UDP, 278 RTE_FLOW_ITEM_TYPE_GTPU, 279 RTE_FLOW_ITEM_TYPE_IPV6, 280 RTE_FLOW_ITEM_TYPE_END, 281 }; 282 283 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = { 284 RTE_FLOW_ITEM_TYPE_ETH, 285 RTE_FLOW_ITEM_TYPE_RAW, 286 RTE_FLOW_ITEM_TYPE_END, 287 }; 288 289 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = { 290 RTE_FLOW_ITEM_TYPE_ETH, 291 RTE_FLOW_ITEM_TYPE_RAW, 292 RTE_FLOW_ITEM_TYPE_RAW, 293 RTE_FLOW_ITEM_TYPE_END, 294 }; 295 296 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = { 297 RTE_FLOW_ITEM_TYPE_ETH, 298 RTE_FLOW_ITEM_TYPE_RAW, 299 RTE_FLOW_ITEM_TYPE_RAW, 300 RTE_FLOW_ITEM_TYPE_RAW, 301 RTE_FLOW_ITEM_TYPE_END, 302 }; 303 304 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = { 305 RTE_FLOW_ITEM_TYPE_ETH, 306 RTE_FLOW_ITEM_TYPE_IPV4, 307 RTE_FLOW_ITEM_TYPE_RAW, 308 RTE_FLOW_ITEM_TYPE_END, 309 }; 310 311 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = { 312 RTE_FLOW_ITEM_TYPE_ETH, 313 RTE_FLOW_ITEM_TYPE_IPV4, 314 RTE_FLOW_ITEM_TYPE_RAW, 315 RTE_FLOW_ITEM_TYPE_RAW, 316 RTE_FLOW_ITEM_TYPE_END, 317 }; 318 319 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = { 320 RTE_FLOW_ITEM_TYPE_ETH, 321 RTE_FLOW_ITEM_TYPE_IPV4, 322 RTE_FLOW_ITEM_TYPE_RAW, 323 RTE_FLOW_ITEM_TYPE_RAW, 324 RTE_FLOW_ITEM_TYPE_RAW, 325 RTE_FLOW_ITEM_TYPE_END, 326 }; 327 328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = { 329 RTE_FLOW_ITEM_TYPE_ETH, 330 RTE_FLOW_ITEM_TYPE_IPV4, 331 RTE_FLOW_ITEM_TYPE_UDP, 332 RTE_FLOW_ITEM_TYPE_RAW, 333 RTE_FLOW_ITEM_TYPE_END, 334 }; 335 336 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = { 337 RTE_FLOW_ITEM_TYPE_ETH, 338 RTE_FLOW_ITEM_TYPE_IPV4, 339 RTE_FLOW_ITEM_TYPE_UDP, 340 RTE_FLOW_ITEM_TYPE_RAW, 341 RTE_FLOW_ITEM_TYPE_RAW, 342 RTE_FLOW_ITEM_TYPE_END, 343 }; 344 345 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = { 346 RTE_FLOW_ITEM_TYPE_ETH, 347 RTE_FLOW_ITEM_TYPE_IPV4, 348 RTE_FLOW_ITEM_TYPE_UDP, 349 RTE_FLOW_ITEM_TYPE_RAW, 350 RTE_FLOW_ITEM_TYPE_RAW, 351 RTE_FLOW_ITEM_TYPE_RAW, 352 RTE_FLOW_ITEM_TYPE_END, 353 }; 354 355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = { 356 RTE_FLOW_ITEM_TYPE_ETH, 357 RTE_FLOW_ITEM_TYPE_IPV4, 358 RTE_FLOW_ITEM_TYPE_TCP, 359 RTE_FLOW_ITEM_TYPE_RAW, 360 RTE_FLOW_ITEM_TYPE_END, 361 }; 362 363 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = { 364 RTE_FLOW_ITEM_TYPE_ETH, 365 RTE_FLOW_ITEM_TYPE_IPV4, 366 RTE_FLOW_ITEM_TYPE_TCP, 367 RTE_FLOW_ITEM_TYPE_RAW, 368 RTE_FLOW_ITEM_TYPE_RAW, 369 RTE_FLOW_ITEM_TYPE_END, 370 }; 371 372 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = { 373 RTE_FLOW_ITEM_TYPE_ETH, 374 RTE_FLOW_ITEM_TYPE_IPV4, 375 RTE_FLOW_ITEM_TYPE_TCP, 376 RTE_FLOW_ITEM_TYPE_RAW, 377 RTE_FLOW_ITEM_TYPE_RAW, 378 RTE_FLOW_ITEM_TYPE_RAW, 379 RTE_FLOW_ITEM_TYPE_END, 380 }; 381 382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = { 383 RTE_FLOW_ITEM_TYPE_ETH, 384 RTE_FLOW_ITEM_TYPE_IPV4, 385 RTE_FLOW_ITEM_TYPE_SCTP, 386 RTE_FLOW_ITEM_TYPE_RAW, 387 RTE_FLOW_ITEM_TYPE_END, 388 }; 389 390 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = { 391 RTE_FLOW_ITEM_TYPE_ETH, 392 RTE_FLOW_ITEM_TYPE_IPV4, 393 RTE_FLOW_ITEM_TYPE_SCTP, 394 RTE_FLOW_ITEM_TYPE_RAW, 395 RTE_FLOW_ITEM_TYPE_RAW, 396 RTE_FLOW_ITEM_TYPE_END, 397 }; 398 399 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = { 400 RTE_FLOW_ITEM_TYPE_ETH, 401 RTE_FLOW_ITEM_TYPE_IPV4, 402 RTE_FLOW_ITEM_TYPE_SCTP, 403 RTE_FLOW_ITEM_TYPE_RAW, 404 RTE_FLOW_ITEM_TYPE_RAW, 405 RTE_FLOW_ITEM_TYPE_RAW, 406 RTE_FLOW_ITEM_TYPE_END, 407 }; 408 409 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = { 410 RTE_FLOW_ITEM_TYPE_ETH, 411 RTE_FLOW_ITEM_TYPE_IPV6, 412 RTE_FLOW_ITEM_TYPE_RAW, 413 RTE_FLOW_ITEM_TYPE_END, 414 }; 415 416 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = { 417 RTE_FLOW_ITEM_TYPE_ETH, 418 RTE_FLOW_ITEM_TYPE_IPV6, 419 RTE_FLOW_ITEM_TYPE_RAW, 420 RTE_FLOW_ITEM_TYPE_RAW, 421 RTE_FLOW_ITEM_TYPE_END, 422 }; 423 424 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = { 425 RTE_FLOW_ITEM_TYPE_ETH, 426 RTE_FLOW_ITEM_TYPE_IPV6, 427 RTE_FLOW_ITEM_TYPE_RAW, 428 RTE_FLOW_ITEM_TYPE_RAW, 429 RTE_FLOW_ITEM_TYPE_RAW, 430 RTE_FLOW_ITEM_TYPE_END, 431 }; 432 433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = { 434 RTE_FLOW_ITEM_TYPE_ETH, 435 RTE_FLOW_ITEM_TYPE_IPV6, 436 RTE_FLOW_ITEM_TYPE_UDP, 437 RTE_FLOW_ITEM_TYPE_RAW, 438 RTE_FLOW_ITEM_TYPE_END, 439 }; 440 441 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = { 442 RTE_FLOW_ITEM_TYPE_ETH, 443 RTE_FLOW_ITEM_TYPE_IPV6, 444 RTE_FLOW_ITEM_TYPE_UDP, 445 RTE_FLOW_ITEM_TYPE_RAW, 446 RTE_FLOW_ITEM_TYPE_RAW, 447 RTE_FLOW_ITEM_TYPE_END, 448 }; 449 450 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = { 451 RTE_FLOW_ITEM_TYPE_ETH, 452 RTE_FLOW_ITEM_TYPE_IPV6, 453 RTE_FLOW_ITEM_TYPE_UDP, 454 RTE_FLOW_ITEM_TYPE_RAW, 455 RTE_FLOW_ITEM_TYPE_RAW, 456 RTE_FLOW_ITEM_TYPE_RAW, 457 RTE_FLOW_ITEM_TYPE_END, 458 }; 459 460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = { 461 RTE_FLOW_ITEM_TYPE_ETH, 462 RTE_FLOW_ITEM_TYPE_IPV6, 463 RTE_FLOW_ITEM_TYPE_TCP, 464 RTE_FLOW_ITEM_TYPE_RAW, 465 RTE_FLOW_ITEM_TYPE_END, 466 }; 467 468 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = { 469 RTE_FLOW_ITEM_TYPE_ETH, 470 RTE_FLOW_ITEM_TYPE_IPV6, 471 RTE_FLOW_ITEM_TYPE_TCP, 472 RTE_FLOW_ITEM_TYPE_RAW, 473 RTE_FLOW_ITEM_TYPE_RAW, 474 RTE_FLOW_ITEM_TYPE_END, 475 }; 476 477 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = { 478 RTE_FLOW_ITEM_TYPE_ETH, 479 RTE_FLOW_ITEM_TYPE_IPV6, 480 RTE_FLOW_ITEM_TYPE_TCP, 481 RTE_FLOW_ITEM_TYPE_RAW, 482 RTE_FLOW_ITEM_TYPE_RAW, 483 RTE_FLOW_ITEM_TYPE_RAW, 484 RTE_FLOW_ITEM_TYPE_END, 485 }; 486 487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = { 488 RTE_FLOW_ITEM_TYPE_ETH, 489 RTE_FLOW_ITEM_TYPE_IPV6, 490 RTE_FLOW_ITEM_TYPE_SCTP, 491 RTE_FLOW_ITEM_TYPE_RAW, 492 RTE_FLOW_ITEM_TYPE_END, 493 }; 494 495 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = { 496 RTE_FLOW_ITEM_TYPE_ETH, 497 RTE_FLOW_ITEM_TYPE_IPV6, 498 RTE_FLOW_ITEM_TYPE_SCTP, 499 RTE_FLOW_ITEM_TYPE_RAW, 500 RTE_FLOW_ITEM_TYPE_RAW, 501 RTE_FLOW_ITEM_TYPE_END, 502 }; 503 504 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = { 505 RTE_FLOW_ITEM_TYPE_ETH, 506 RTE_FLOW_ITEM_TYPE_IPV6, 507 RTE_FLOW_ITEM_TYPE_SCTP, 508 RTE_FLOW_ITEM_TYPE_RAW, 509 RTE_FLOW_ITEM_TYPE_RAW, 510 RTE_FLOW_ITEM_TYPE_RAW, 511 RTE_FLOW_ITEM_TYPE_END, 512 }; 513 514 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = { 515 RTE_FLOW_ITEM_TYPE_ETH, 516 RTE_FLOW_ITEM_TYPE_VLAN, 517 RTE_FLOW_ITEM_TYPE_END, 518 }; 519 520 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = { 521 RTE_FLOW_ITEM_TYPE_ETH, 522 RTE_FLOW_ITEM_TYPE_VLAN, 523 RTE_FLOW_ITEM_TYPE_IPV4, 524 RTE_FLOW_ITEM_TYPE_END, 525 }; 526 527 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = { 528 RTE_FLOW_ITEM_TYPE_ETH, 529 RTE_FLOW_ITEM_TYPE_VLAN, 530 RTE_FLOW_ITEM_TYPE_IPV4, 531 RTE_FLOW_ITEM_TYPE_UDP, 532 RTE_FLOW_ITEM_TYPE_END, 533 }; 534 535 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = { 536 RTE_FLOW_ITEM_TYPE_ETH, 537 RTE_FLOW_ITEM_TYPE_VLAN, 538 RTE_FLOW_ITEM_TYPE_IPV4, 539 RTE_FLOW_ITEM_TYPE_TCP, 540 RTE_FLOW_ITEM_TYPE_END, 541 }; 542 543 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = { 544 RTE_FLOW_ITEM_TYPE_ETH, 545 RTE_FLOW_ITEM_TYPE_VLAN, 546 RTE_FLOW_ITEM_TYPE_IPV4, 547 RTE_FLOW_ITEM_TYPE_SCTP, 548 RTE_FLOW_ITEM_TYPE_END, 549 }; 550 551 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = { 552 RTE_FLOW_ITEM_TYPE_ETH, 553 RTE_FLOW_ITEM_TYPE_VLAN, 554 RTE_FLOW_ITEM_TYPE_IPV6, 555 RTE_FLOW_ITEM_TYPE_END, 556 }; 557 558 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = { 559 RTE_FLOW_ITEM_TYPE_ETH, 560 RTE_FLOW_ITEM_TYPE_VLAN, 561 RTE_FLOW_ITEM_TYPE_IPV6, 562 RTE_FLOW_ITEM_TYPE_UDP, 563 RTE_FLOW_ITEM_TYPE_END, 564 }; 565 566 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = { 567 RTE_FLOW_ITEM_TYPE_ETH, 568 RTE_FLOW_ITEM_TYPE_VLAN, 569 RTE_FLOW_ITEM_TYPE_IPV6, 570 RTE_FLOW_ITEM_TYPE_TCP, 571 RTE_FLOW_ITEM_TYPE_END, 572 }; 573 574 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = { 575 RTE_FLOW_ITEM_TYPE_ETH, 576 RTE_FLOW_ITEM_TYPE_VLAN, 577 RTE_FLOW_ITEM_TYPE_IPV6, 578 RTE_FLOW_ITEM_TYPE_SCTP, 579 RTE_FLOW_ITEM_TYPE_END, 580 }; 581 582 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = { 583 RTE_FLOW_ITEM_TYPE_ETH, 584 RTE_FLOW_ITEM_TYPE_VLAN, 585 RTE_FLOW_ITEM_TYPE_RAW, 586 RTE_FLOW_ITEM_TYPE_END, 587 }; 588 589 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = { 590 RTE_FLOW_ITEM_TYPE_ETH, 591 RTE_FLOW_ITEM_TYPE_VLAN, 592 RTE_FLOW_ITEM_TYPE_RAW, 593 RTE_FLOW_ITEM_TYPE_RAW, 594 RTE_FLOW_ITEM_TYPE_END, 595 }; 596 597 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = { 598 RTE_FLOW_ITEM_TYPE_ETH, 599 RTE_FLOW_ITEM_TYPE_VLAN, 600 RTE_FLOW_ITEM_TYPE_RAW, 601 RTE_FLOW_ITEM_TYPE_RAW, 602 RTE_FLOW_ITEM_TYPE_RAW, 603 RTE_FLOW_ITEM_TYPE_END, 604 }; 605 606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = { 607 RTE_FLOW_ITEM_TYPE_ETH, 608 RTE_FLOW_ITEM_TYPE_VLAN, 609 RTE_FLOW_ITEM_TYPE_IPV4, 610 RTE_FLOW_ITEM_TYPE_RAW, 611 RTE_FLOW_ITEM_TYPE_END, 612 }; 613 614 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = { 615 RTE_FLOW_ITEM_TYPE_ETH, 616 RTE_FLOW_ITEM_TYPE_VLAN, 617 RTE_FLOW_ITEM_TYPE_IPV4, 618 RTE_FLOW_ITEM_TYPE_RAW, 619 RTE_FLOW_ITEM_TYPE_RAW, 620 RTE_FLOW_ITEM_TYPE_END, 621 }; 622 623 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = { 624 RTE_FLOW_ITEM_TYPE_ETH, 625 RTE_FLOW_ITEM_TYPE_VLAN, 626 RTE_FLOW_ITEM_TYPE_IPV4, 627 RTE_FLOW_ITEM_TYPE_RAW, 628 RTE_FLOW_ITEM_TYPE_RAW, 629 RTE_FLOW_ITEM_TYPE_RAW, 630 RTE_FLOW_ITEM_TYPE_END, 631 }; 632 633 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = { 634 RTE_FLOW_ITEM_TYPE_ETH, 635 RTE_FLOW_ITEM_TYPE_VLAN, 636 RTE_FLOW_ITEM_TYPE_IPV4, 637 RTE_FLOW_ITEM_TYPE_UDP, 638 RTE_FLOW_ITEM_TYPE_RAW, 639 RTE_FLOW_ITEM_TYPE_END, 640 }; 641 642 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = { 643 RTE_FLOW_ITEM_TYPE_ETH, 644 RTE_FLOW_ITEM_TYPE_VLAN, 645 RTE_FLOW_ITEM_TYPE_IPV4, 646 RTE_FLOW_ITEM_TYPE_UDP, 647 RTE_FLOW_ITEM_TYPE_RAW, 648 RTE_FLOW_ITEM_TYPE_RAW, 649 RTE_FLOW_ITEM_TYPE_END, 650 }; 651 652 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = { 653 RTE_FLOW_ITEM_TYPE_ETH, 654 RTE_FLOW_ITEM_TYPE_VLAN, 655 RTE_FLOW_ITEM_TYPE_IPV4, 656 RTE_FLOW_ITEM_TYPE_UDP, 657 RTE_FLOW_ITEM_TYPE_RAW, 658 RTE_FLOW_ITEM_TYPE_RAW, 659 RTE_FLOW_ITEM_TYPE_RAW, 660 RTE_FLOW_ITEM_TYPE_END, 661 }; 662 663 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = { 664 RTE_FLOW_ITEM_TYPE_ETH, 665 RTE_FLOW_ITEM_TYPE_VLAN, 666 RTE_FLOW_ITEM_TYPE_IPV4, 667 RTE_FLOW_ITEM_TYPE_TCP, 668 RTE_FLOW_ITEM_TYPE_RAW, 669 RTE_FLOW_ITEM_TYPE_END, 670 }; 671 672 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = { 673 RTE_FLOW_ITEM_TYPE_ETH, 674 RTE_FLOW_ITEM_TYPE_VLAN, 675 RTE_FLOW_ITEM_TYPE_IPV4, 676 RTE_FLOW_ITEM_TYPE_TCP, 677 RTE_FLOW_ITEM_TYPE_RAW, 678 RTE_FLOW_ITEM_TYPE_RAW, 679 RTE_FLOW_ITEM_TYPE_END, 680 }; 681 682 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = { 683 RTE_FLOW_ITEM_TYPE_ETH, 684 RTE_FLOW_ITEM_TYPE_VLAN, 685 RTE_FLOW_ITEM_TYPE_IPV4, 686 RTE_FLOW_ITEM_TYPE_TCP, 687 RTE_FLOW_ITEM_TYPE_RAW, 688 RTE_FLOW_ITEM_TYPE_RAW, 689 RTE_FLOW_ITEM_TYPE_RAW, 690 RTE_FLOW_ITEM_TYPE_END, 691 }; 692 693 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = { 694 RTE_FLOW_ITEM_TYPE_ETH, 695 RTE_FLOW_ITEM_TYPE_VLAN, 696 RTE_FLOW_ITEM_TYPE_IPV4, 697 RTE_FLOW_ITEM_TYPE_SCTP, 698 RTE_FLOW_ITEM_TYPE_RAW, 699 RTE_FLOW_ITEM_TYPE_END, 700 }; 701 702 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = { 703 RTE_FLOW_ITEM_TYPE_ETH, 704 RTE_FLOW_ITEM_TYPE_VLAN, 705 RTE_FLOW_ITEM_TYPE_IPV4, 706 RTE_FLOW_ITEM_TYPE_SCTP, 707 RTE_FLOW_ITEM_TYPE_RAW, 708 RTE_FLOW_ITEM_TYPE_RAW, 709 RTE_FLOW_ITEM_TYPE_END, 710 }; 711 712 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = { 713 RTE_FLOW_ITEM_TYPE_ETH, 714 RTE_FLOW_ITEM_TYPE_VLAN, 715 RTE_FLOW_ITEM_TYPE_IPV4, 716 RTE_FLOW_ITEM_TYPE_SCTP, 717 RTE_FLOW_ITEM_TYPE_RAW, 718 RTE_FLOW_ITEM_TYPE_RAW, 719 RTE_FLOW_ITEM_TYPE_RAW, 720 RTE_FLOW_ITEM_TYPE_END, 721 }; 722 723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = { 724 RTE_FLOW_ITEM_TYPE_ETH, 725 RTE_FLOW_ITEM_TYPE_VLAN, 726 RTE_FLOW_ITEM_TYPE_IPV6, 727 RTE_FLOW_ITEM_TYPE_RAW, 728 RTE_FLOW_ITEM_TYPE_END, 729 }; 730 731 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = { 732 RTE_FLOW_ITEM_TYPE_ETH, 733 RTE_FLOW_ITEM_TYPE_VLAN, 734 RTE_FLOW_ITEM_TYPE_IPV6, 735 RTE_FLOW_ITEM_TYPE_RAW, 736 RTE_FLOW_ITEM_TYPE_RAW, 737 RTE_FLOW_ITEM_TYPE_END, 738 }; 739 740 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = { 741 RTE_FLOW_ITEM_TYPE_ETH, 742 RTE_FLOW_ITEM_TYPE_VLAN, 743 RTE_FLOW_ITEM_TYPE_IPV6, 744 RTE_FLOW_ITEM_TYPE_RAW, 745 RTE_FLOW_ITEM_TYPE_RAW, 746 RTE_FLOW_ITEM_TYPE_RAW, 747 RTE_FLOW_ITEM_TYPE_END, 748 }; 749 750 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = { 751 RTE_FLOW_ITEM_TYPE_ETH, 752 RTE_FLOW_ITEM_TYPE_VLAN, 753 RTE_FLOW_ITEM_TYPE_IPV6, 754 RTE_FLOW_ITEM_TYPE_UDP, 755 RTE_FLOW_ITEM_TYPE_RAW, 756 RTE_FLOW_ITEM_TYPE_END, 757 }; 758 759 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = { 760 RTE_FLOW_ITEM_TYPE_ETH, 761 RTE_FLOW_ITEM_TYPE_VLAN, 762 RTE_FLOW_ITEM_TYPE_IPV6, 763 RTE_FLOW_ITEM_TYPE_UDP, 764 RTE_FLOW_ITEM_TYPE_RAW, 765 RTE_FLOW_ITEM_TYPE_RAW, 766 RTE_FLOW_ITEM_TYPE_END, 767 }; 768 769 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = { 770 RTE_FLOW_ITEM_TYPE_ETH, 771 RTE_FLOW_ITEM_TYPE_VLAN, 772 RTE_FLOW_ITEM_TYPE_IPV6, 773 RTE_FLOW_ITEM_TYPE_UDP, 774 RTE_FLOW_ITEM_TYPE_RAW, 775 RTE_FLOW_ITEM_TYPE_RAW, 776 RTE_FLOW_ITEM_TYPE_RAW, 777 RTE_FLOW_ITEM_TYPE_END, 778 }; 779 780 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = { 781 RTE_FLOW_ITEM_TYPE_ETH, 782 RTE_FLOW_ITEM_TYPE_VLAN, 783 RTE_FLOW_ITEM_TYPE_IPV6, 784 RTE_FLOW_ITEM_TYPE_TCP, 785 RTE_FLOW_ITEM_TYPE_RAW, 786 RTE_FLOW_ITEM_TYPE_END, 787 }; 788 789 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = { 790 RTE_FLOW_ITEM_TYPE_ETH, 791 RTE_FLOW_ITEM_TYPE_VLAN, 792 RTE_FLOW_ITEM_TYPE_IPV6, 793 RTE_FLOW_ITEM_TYPE_TCP, 794 RTE_FLOW_ITEM_TYPE_RAW, 795 RTE_FLOW_ITEM_TYPE_RAW, 796 RTE_FLOW_ITEM_TYPE_END, 797 }; 798 799 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = { 800 RTE_FLOW_ITEM_TYPE_ETH, 801 RTE_FLOW_ITEM_TYPE_VLAN, 802 RTE_FLOW_ITEM_TYPE_IPV6, 803 RTE_FLOW_ITEM_TYPE_TCP, 804 RTE_FLOW_ITEM_TYPE_RAW, 805 RTE_FLOW_ITEM_TYPE_RAW, 806 RTE_FLOW_ITEM_TYPE_RAW, 807 RTE_FLOW_ITEM_TYPE_END, 808 }; 809 810 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = { 811 RTE_FLOW_ITEM_TYPE_ETH, 812 RTE_FLOW_ITEM_TYPE_VLAN, 813 RTE_FLOW_ITEM_TYPE_IPV6, 814 RTE_FLOW_ITEM_TYPE_SCTP, 815 RTE_FLOW_ITEM_TYPE_RAW, 816 RTE_FLOW_ITEM_TYPE_END, 817 }; 818 819 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = { 820 RTE_FLOW_ITEM_TYPE_ETH, 821 RTE_FLOW_ITEM_TYPE_VLAN, 822 RTE_FLOW_ITEM_TYPE_IPV6, 823 RTE_FLOW_ITEM_TYPE_SCTP, 824 RTE_FLOW_ITEM_TYPE_RAW, 825 RTE_FLOW_ITEM_TYPE_RAW, 826 RTE_FLOW_ITEM_TYPE_END, 827 }; 828 829 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = { 830 RTE_FLOW_ITEM_TYPE_ETH, 831 RTE_FLOW_ITEM_TYPE_VLAN, 832 RTE_FLOW_ITEM_TYPE_IPV6, 833 RTE_FLOW_ITEM_TYPE_SCTP, 834 RTE_FLOW_ITEM_TYPE_RAW, 835 RTE_FLOW_ITEM_TYPE_RAW, 836 RTE_FLOW_ITEM_TYPE_RAW, 837 RTE_FLOW_ITEM_TYPE_END, 838 }; 839 840 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = { 841 RTE_FLOW_ITEM_TYPE_ETH, 842 RTE_FLOW_ITEM_TYPE_IPV4, 843 RTE_FLOW_ITEM_TYPE_VF, 844 RTE_FLOW_ITEM_TYPE_END, 845 }; 846 847 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = { 848 RTE_FLOW_ITEM_TYPE_ETH, 849 RTE_FLOW_ITEM_TYPE_IPV4, 850 RTE_FLOW_ITEM_TYPE_UDP, 851 RTE_FLOW_ITEM_TYPE_VF, 852 RTE_FLOW_ITEM_TYPE_END, 853 }; 854 855 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = { 856 RTE_FLOW_ITEM_TYPE_ETH, 857 RTE_FLOW_ITEM_TYPE_IPV4, 858 RTE_FLOW_ITEM_TYPE_TCP, 859 RTE_FLOW_ITEM_TYPE_VF, 860 RTE_FLOW_ITEM_TYPE_END, 861 }; 862 863 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = { 864 RTE_FLOW_ITEM_TYPE_ETH, 865 RTE_FLOW_ITEM_TYPE_IPV4, 866 RTE_FLOW_ITEM_TYPE_SCTP, 867 RTE_FLOW_ITEM_TYPE_VF, 868 RTE_FLOW_ITEM_TYPE_END, 869 }; 870 871 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = { 872 RTE_FLOW_ITEM_TYPE_ETH, 873 RTE_FLOW_ITEM_TYPE_IPV6, 874 RTE_FLOW_ITEM_TYPE_VF, 875 RTE_FLOW_ITEM_TYPE_END, 876 }; 877 878 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = { 879 RTE_FLOW_ITEM_TYPE_ETH, 880 RTE_FLOW_ITEM_TYPE_IPV6, 881 RTE_FLOW_ITEM_TYPE_UDP, 882 RTE_FLOW_ITEM_TYPE_VF, 883 RTE_FLOW_ITEM_TYPE_END, 884 }; 885 886 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = { 887 RTE_FLOW_ITEM_TYPE_ETH, 888 RTE_FLOW_ITEM_TYPE_IPV6, 889 RTE_FLOW_ITEM_TYPE_TCP, 890 RTE_FLOW_ITEM_TYPE_VF, 891 RTE_FLOW_ITEM_TYPE_END, 892 }; 893 894 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = { 895 RTE_FLOW_ITEM_TYPE_ETH, 896 RTE_FLOW_ITEM_TYPE_IPV6, 897 RTE_FLOW_ITEM_TYPE_SCTP, 898 RTE_FLOW_ITEM_TYPE_VF, 899 RTE_FLOW_ITEM_TYPE_END, 900 }; 901 902 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = { 903 RTE_FLOW_ITEM_TYPE_ETH, 904 RTE_FLOW_ITEM_TYPE_RAW, 905 RTE_FLOW_ITEM_TYPE_VF, 906 RTE_FLOW_ITEM_TYPE_END, 907 }; 908 909 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = { 910 RTE_FLOW_ITEM_TYPE_ETH, 911 RTE_FLOW_ITEM_TYPE_RAW, 912 RTE_FLOW_ITEM_TYPE_RAW, 913 RTE_FLOW_ITEM_TYPE_VF, 914 RTE_FLOW_ITEM_TYPE_END, 915 }; 916 917 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = { 918 RTE_FLOW_ITEM_TYPE_ETH, 919 RTE_FLOW_ITEM_TYPE_RAW, 920 RTE_FLOW_ITEM_TYPE_RAW, 921 RTE_FLOW_ITEM_TYPE_RAW, 922 RTE_FLOW_ITEM_TYPE_VF, 923 RTE_FLOW_ITEM_TYPE_END, 924 }; 925 926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = { 927 RTE_FLOW_ITEM_TYPE_ETH, 928 RTE_FLOW_ITEM_TYPE_IPV4, 929 RTE_FLOW_ITEM_TYPE_RAW, 930 RTE_FLOW_ITEM_TYPE_VF, 931 RTE_FLOW_ITEM_TYPE_END, 932 }; 933 934 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = { 935 RTE_FLOW_ITEM_TYPE_ETH, 936 RTE_FLOW_ITEM_TYPE_IPV4, 937 RTE_FLOW_ITEM_TYPE_RAW, 938 RTE_FLOW_ITEM_TYPE_RAW, 939 RTE_FLOW_ITEM_TYPE_VF, 940 RTE_FLOW_ITEM_TYPE_END, 941 }; 942 943 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = { 944 RTE_FLOW_ITEM_TYPE_ETH, 945 RTE_FLOW_ITEM_TYPE_IPV4, 946 RTE_FLOW_ITEM_TYPE_RAW, 947 RTE_FLOW_ITEM_TYPE_RAW, 948 RTE_FLOW_ITEM_TYPE_RAW, 949 RTE_FLOW_ITEM_TYPE_VF, 950 RTE_FLOW_ITEM_TYPE_END, 951 }; 952 953 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = { 954 RTE_FLOW_ITEM_TYPE_ETH, 955 RTE_FLOW_ITEM_TYPE_IPV4, 956 RTE_FLOW_ITEM_TYPE_UDP, 957 RTE_FLOW_ITEM_TYPE_RAW, 958 RTE_FLOW_ITEM_TYPE_VF, 959 RTE_FLOW_ITEM_TYPE_END, 960 }; 961 962 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = { 963 RTE_FLOW_ITEM_TYPE_ETH, 964 RTE_FLOW_ITEM_TYPE_IPV4, 965 RTE_FLOW_ITEM_TYPE_UDP, 966 RTE_FLOW_ITEM_TYPE_RAW, 967 RTE_FLOW_ITEM_TYPE_RAW, 968 RTE_FLOW_ITEM_TYPE_VF, 969 RTE_FLOW_ITEM_TYPE_END, 970 }; 971 972 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = { 973 RTE_FLOW_ITEM_TYPE_ETH, 974 RTE_FLOW_ITEM_TYPE_IPV4, 975 RTE_FLOW_ITEM_TYPE_UDP, 976 RTE_FLOW_ITEM_TYPE_RAW, 977 RTE_FLOW_ITEM_TYPE_RAW, 978 RTE_FLOW_ITEM_TYPE_RAW, 979 RTE_FLOW_ITEM_TYPE_VF, 980 RTE_FLOW_ITEM_TYPE_END, 981 }; 982 983 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = { 984 RTE_FLOW_ITEM_TYPE_ETH, 985 RTE_FLOW_ITEM_TYPE_IPV4, 986 RTE_FLOW_ITEM_TYPE_TCP, 987 RTE_FLOW_ITEM_TYPE_RAW, 988 RTE_FLOW_ITEM_TYPE_VF, 989 RTE_FLOW_ITEM_TYPE_END, 990 }; 991 992 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = { 993 RTE_FLOW_ITEM_TYPE_ETH, 994 RTE_FLOW_ITEM_TYPE_IPV4, 995 RTE_FLOW_ITEM_TYPE_TCP, 996 RTE_FLOW_ITEM_TYPE_RAW, 997 RTE_FLOW_ITEM_TYPE_RAW, 998 RTE_FLOW_ITEM_TYPE_VF, 999 RTE_FLOW_ITEM_TYPE_END, 1000 }; 1001 1002 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = { 1003 RTE_FLOW_ITEM_TYPE_ETH, 1004 RTE_FLOW_ITEM_TYPE_IPV4, 1005 RTE_FLOW_ITEM_TYPE_TCP, 1006 RTE_FLOW_ITEM_TYPE_RAW, 1007 RTE_FLOW_ITEM_TYPE_RAW, 1008 RTE_FLOW_ITEM_TYPE_RAW, 1009 RTE_FLOW_ITEM_TYPE_VF, 1010 RTE_FLOW_ITEM_TYPE_END, 1011 }; 1012 1013 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = { 1014 RTE_FLOW_ITEM_TYPE_ETH, 1015 RTE_FLOW_ITEM_TYPE_IPV4, 1016 RTE_FLOW_ITEM_TYPE_SCTP, 1017 RTE_FLOW_ITEM_TYPE_RAW, 1018 RTE_FLOW_ITEM_TYPE_VF, 1019 RTE_FLOW_ITEM_TYPE_END, 1020 }; 1021 1022 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = { 1023 RTE_FLOW_ITEM_TYPE_ETH, 1024 RTE_FLOW_ITEM_TYPE_IPV4, 1025 RTE_FLOW_ITEM_TYPE_SCTP, 1026 RTE_FLOW_ITEM_TYPE_RAW, 1027 RTE_FLOW_ITEM_TYPE_RAW, 1028 RTE_FLOW_ITEM_TYPE_VF, 1029 RTE_FLOW_ITEM_TYPE_END, 1030 }; 1031 1032 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = { 1033 RTE_FLOW_ITEM_TYPE_ETH, 1034 RTE_FLOW_ITEM_TYPE_IPV4, 1035 RTE_FLOW_ITEM_TYPE_SCTP, 1036 RTE_FLOW_ITEM_TYPE_RAW, 1037 RTE_FLOW_ITEM_TYPE_RAW, 1038 RTE_FLOW_ITEM_TYPE_RAW, 1039 RTE_FLOW_ITEM_TYPE_VF, 1040 RTE_FLOW_ITEM_TYPE_END, 1041 }; 1042 1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = { 1044 RTE_FLOW_ITEM_TYPE_ETH, 1045 RTE_FLOW_ITEM_TYPE_IPV6, 1046 RTE_FLOW_ITEM_TYPE_RAW, 1047 RTE_FLOW_ITEM_TYPE_VF, 1048 RTE_FLOW_ITEM_TYPE_END, 1049 }; 1050 1051 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = { 1052 RTE_FLOW_ITEM_TYPE_ETH, 1053 RTE_FLOW_ITEM_TYPE_IPV6, 1054 RTE_FLOW_ITEM_TYPE_RAW, 1055 RTE_FLOW_ITEM_TYPE_RAW, 1056 RTE_FLOW_ITEM_TYPE_VF, 1057 RTE_FLOW_ITEM_TYPE_END, 1058 }; 1059 1060 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = { 1061 RTE_FLOW_ITEM_TYPE_ETH, 1062 RTE_FLOW_ITEM_TYPE_IPV6, 1063 RTE_FLOW_ITEM_TYPE_RAW, 1064 RTE_FLOW_ITEM_TYPE_RAW, 1065 RTE_FLOW_ITEM_TYPE_RAW, 1066 RTE_FLOW_ITEM_TYPE_VF, 1067 RTE_FLOW_ITEM_TYPE_END, 1068 }; 1069 1070 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = { 1071 RTE_FLOW_ITEM_TYPE_ETH, 1072 RTE_FLOW_ITEM_TYPE_IPV6, 1073 RTE_FLOW_ITEM_TYPE_UDP, 1074 RTE_FLOW_ITEM_TYPE_RAW, 1075 RTE_FLOW_ITEM_TYPE_VF, 1076 RTE_FLOW_ITEM_TYPE_END, 1077 }; 1078 1079 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = { 1080 RTE_FLOW_ITEM_TYPE_ETH, 1081 RTE_FLOW_ITEM_TYPE_IPV6, 1082 RTE_FLOW_ITEM_TYPE_UDP, 1083 RTE_FLOW_ITEM_TYPE_RAW, 1084 RTE_FLOW_ITEM_TYPE_RAW, 1085 RTE_FLOW_ITEM_TYPE_VF, 1086 RTE_FLOW_ITEM_TYPE_END, 1087 }; 1088 1089 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = { 1090 RTE_FLOW_ITEM_TYPE_ETH, 1091 RTE_FLOW_ITEM_TYPE_IPV6, 1092 RTE_FLOW_ITEM_TYPE_UDP, 1093 RTE_FLOW_ITEM_TYPE_RAW, 1094 RTE_FLOW_ITEM_TYPE_RAW, 1095 RTE_FLOW_ITEM_TYPE_RAW, 1096 RTE_FLOW_ITEM_TYPE_VF, 1097 RTE_FLOW_ITEM_TYPE_END, 1098 }; 1099 1100 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = { 1101 RTE_FLOW_ITEM_TYPE_ETH, 1102 RTE_FLOW_ITEM_TYPE_IPV6, 1103 RTE_FLOW_ITEM_TYPE_TCP, 1104 RTE_FLOW_ITEM_TYPE_RAW, 1105 RTE_FLOW_ITEM_TYPE_VF, 1106 RTE_FLOW_ITEM_TYPE_END, 1107 }; 1108 1109 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = { 1110 RTE_FLOW_ITEM_TYPE_ETH, 1111 RTE_FLOW_ITEM_TYPE_IPV6, 1112 RTE_FLOW_ITEM_TYPE_TCP, 1113 RTE_FLOW_ITEM_TYPE_RAW, 1114 RTE_FLOW_ITEM_TYPE_RAW, 1115 RTE_FLOW_ITEM_TYPE_VF, 1116 RTE_FLOW_ITEM_TYPE_END, 1117 }; 1118 1119 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = { 1120 RTE_FLOW_ITEM_TYPE_ETH, 1121 RTE_FLOW_ITEM_TYPE_IPV6, 1122 RTE_FLOW_ITEM_TYPE_TCP, 1123 RTE_FLOW_ITEM_TYPE_RAW, 1124 RTE_FLOW_ITEM_TYPE_RAW, 1125 RTE_FLOW_ITEM_TYPE_RAW, 1126 RTE_FLOW_ITEM_TYPE_VF, 1127 RTE_FLOW_ITEM_TYPE_END, 1128 }; 1129 1130 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = { 1131 RTE_FLOW_ITEM_TYPE_ETH, 1132 RTE_FLOW_ITEM_TYPE_IPV6, 1133 RTE_FLOW_ITEM_TYPE_SCTP, 1134 RTE_FLOW_ITEM_TYPE_RAW, 1135 RTE_FLOW_ITEM_TYPE_VF, 1136 RTE_FLOW_ITEM_TYPE_END, 1137 }; 1138 1139 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = { 1140 RTE_FLOW_ITEM_TYPE_ETH, 1141 RTE_FLOW_ITEM_TYPE_IPV6, 1142 RTE_FLOW_ITEM_TYPE_SCTP, 1143 RTE_FLOW_ITEM_TYPE_RAW, 1144 RTE_FLOW_ITEM_TYPE_RAW, 1145 RTE_FLOW_ITEM_TYPE_VF, 1146 RTE_FLOW_ITEM_TYPE_END, 1147 }; 1148 1149 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = { 1150 RTE_FLOW_ITEM_TYPE_ETH, 1151 RTE_FLOW_ITEM_TYPE_IPV6, 1152 RTE_FLOW_ITEM_TYPE_SCTP, 1153 RTE_FLOW_ITEM_TYPE_RAW, 1154 RTE_FLOW_ITEM_TYPE_RAW, 1155 RTE_FLOW_ITEM_TYPE_RAW, 1156 RTE_FLOW_ITEM_TYPE_VF, 1157 RTE_FLOW_ITEM_TYPE_END, 1158 }; 1159 1160 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = { 1161 RTE_FLOW_ITEM_TYPE_ETH, 1162 RTE_FLOW_ITEM_TYPE_VLAN, 1163 RTE_FLOW_ITEM_TYPE_VF, 1164 RTE_FLOW_ITEM_TYPE_END, 1165 }; 1166 1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = { 1168 RTE_FLOW_ITEM_TYPE_ETH, 1169 RTE_FLOW_ITEM_TYPE_VLAN, 1170 RTE_FLOW_ITEM_TYPE_IPV4, 1171 RTE_FLOW_ITEM_TYPE_VF, 1172 RTE_FLOW_ITEM_TYPE_END, 1173 }; 1174 1175 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = { 1176 RTE_FLOW_ITEM_TYPE_ETH, 1177 RTE_FLOW_ITEM_TYPE_VLAN, 1178 RTE_FLOW_ITEM_TYPE_IPV4, 1179 RTE_FLOW_ITEM_TYPE_UDP, 1180 RTE_FLOW_ITEM_TYPE_VF, 1181 RTE_FLOW_ITEM_TYPE_END, 1182 }; 1183 1184 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = { 1185 RTE_FLOW_ITEM_TYPE_ETH, 1186 RTE_FLOW_ITEM_TYPE_VLAN, 1187 RTE_FLOW_ITEM_TYPE_IPV4, 1188 RTE_FLOW_ITEM_TYPE_TCP, 1189 RTE_FLOW_ITEM_TYPE_VF, 1190 RTE_FLOW_ITEM_TYPE_END, 1191 }; 1192 1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = { 1194 RTE_FLOW_ITEM_TYPE_ETH, 1195 RTE_FLOW_ITEM_TYPE_VLAN, 1196 RTE_FLOW_ITEM_TYPE_IPV4, 1197 RTE_FLOW_ITEM_TYPE_SCTP, 1198 RTE_FLOW_ITEM_TYPE_VF, 1199 RTE_FLOW_ITEM_TYPE_END, 1200 }; 1201 1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = { 1203 RTE_FLOW_ITEM_TYPE_ETH, 1204 RTE_FLOW_ITEM_TYPE_VLAN, 1205 RTE_FLOW_ITEM_TYPE_IPV6, 1206 RTE_FLOW_ITEM_TYPE_VF, 1207 RTE_FLOW_ITEM_TYPE_END, 1208 }; 1209 1210 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = { 1211 RTE_FLOW_ITEM_TYPE_ETH, 1212 RTE_FLOW_ITEM_TYPE_VLAN, 1213 RTE_FLOW_ITEM_TYPE_IPV6, 1214 RTE_FLOW_ITEM_TYPE_UDP, 1215 RTE_FLOW_ITEM_TYPE_VF, 1216 RTE_FLOW_ITEM_TYPE_END, 1217 }; 1218 1219 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = { 1220 RTE_FLOW_ITEM_TYPE_ETH, 1221 RTE_FLOW_ITEM_TYPE_VLAN, 1222 RTE_FLOW_ITEM_TYPE_IPV6, 1223 RTE_FLOW_ITEM_TYPE_TCP, 1224 RTE_FLOW_ITEM_TYPE_VF, 1225 RTE_FLOW_ITEM_TYPE_END, 1226 }; 1227 1228 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = { 1229 RTE_FLOW_ITEM_TYPE_ETH, 1230 RTE_FLOW_ITEM_TYPE_VLAN, 1231 RTE_FLOW_ITEM_TYPE_IPV6, 1232 RTE_FLOW_ITEM_TYPE_SCTP, 1233 RTE_FLOW_ITEM_TYPE_VF, 1234 RTE_FLOW_ITEM_TYPE_END, 1235 }; 1236 1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = { 1238 RTE_FLOW_ITEM_TYPE_ETH, 1239 RTE_FLOW_ITEM_TYPE_VLAN, 1240 RTE_FLOW_ITEM_TYPE_RAW, 1241 RTE_FLOW_ITEM_TYPE_VF, 1242 RTE_FLOW_ITEM_TYPE_END, 1243 }; 1244 1245 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = { 1246 RTE_FLOW_ITEM_TYPE_ETH, 1247 RTE_FLOW_ITEM_TYPE_VLAN, 1248 RTE_FLOW_ITEM_TYPE_RAW, 1249 RTE_FLOW_ITEM_TYPE_RAW, 1250 RTE_FLOW_ITEM_TYPE_VF, 1251 RTE_FLOW_ITEM_TYPE_END, 1252 }; 1253 1254 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = { 1255 RTE_FLOW_ITEM_TYPE_ETH, 1256 RTE_FLOW_ITEM_TYPE_VLAN, 1257 RTE_FLOW_ITEM_TYPE_RAW, 1258 RTE_FLOW_ITEM_TYPE_RAW, 1259 RTE_FLOW_ITEM_TYPE_RAW, 1260 RTE_FLOW_ITEM_TYPE_VF, 1261 RTE_FLOW_ITEM_TYPE_END, 1262 }; 1263 1264 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = { 1265 RTE_FLOW_ITEM_TYPE_ETH, 1266 RTE_FLOW_ITEM_TYPE_VLAN, 1267 RTE_FLOW_ITEM_TYPE_IPV4, 1268 RTE_FLOW_ITEM_TYPE_RAW, 1269 RTE_FLOW_ITEM_TYPE_VF, 1270 RTE_FLOW_ITEM_TYPE_END, 1271 }; 1272 1273 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = { 1274 RTE_FLOW_ITEM_TYPE_ETH, 1275 RTE_FLOW_ITEM_TYPE_VLAN, 1276 RTE_FLOW_ITEM_TYPE_IPV4, 1277 RTE_FLOW_ITEM_TYPE_RAW, 1278 RTE_FLOW_ITEM_TYPE_RAW, 1279 RTE_FLOW_ITEM_TYPE_VF, 1280 RTE_FLOW_ITEM_TYPE_END, 1281 }; 1282 1283 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = { 1284 RTE_FLOW_ITEM_TYPE_ETH, 1285 RTE_FLOW_ITEM_TYPE_VLAN, 1286 RTE_FLOW_ITEM_TYPE_IPV4, 1287 RTE_FLOW_ITEM_TYPE_RAW, 1288 RTE_FLOW_ITEM_TYPE_RAW, 1289 RTE_FLOW_ITEM_TYPE_RAW, 1290 RTE_FLOW_ITEM_TYPE_VF, 1291 RTE_FLOW_ITEM_TYPE_END, 1292 }; 1293 1294 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = { 1295 RTE_FLOW_ITEM_TYPE_ETH, 1296 RTE_FLOW_ITEM_TYPE_VLAN, 1297 RTE_FLOW_ITEM_TYPE_IPV4, 1298 RTE_FLOW_ITEM_TYPE_UDP, 1299 RTE_FLOW_ITEM_TYPE_RAW, 1300 RTE_FLOW_ITEM_TYPE_VF, 1301 RTE_FLOW_ITEM_TYPE_END, 1302 }; 1303 1304 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = { 1305 RTE_FLOW_ITEM_TYPE_ETH, 1306 RTE_FLOW_ITEM_TYPE_VLAN, 1307 RTE_FLOW_ITEM_TYPE_IPV4, 1308 RTE_FLOW_ITEM_TYPE_UDP, 1309 RTE_FLOW_ITEM_TYPE_RAW, 1310 RTE_FLOW_ITEM_TYPE_RAW, 1311 RTE_FLOW_ITEM_TYPE_VF, 1312 RTE_FLOW_ITEM_TYPE_END, 1313 }; 1314 1315 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = { 1316 RTE_FLOW_ITEM_TYPE_ETH, 1317 RTE_FLOW_ITEM_TYPE_VLAN, 1318 RTE_FLOW_ITEM_TYPE_IPV4, 1319 RTE_FLOW_ITEM_TYPE_UDP, 1320 RTE_FLOW_ITEM_TYPE_RAW, 1321 RTE_FLOW_ITEM_TYPE_RAW, 1322 RTE_FLOW_ITEM_TYPE_RAW, 1323 RTE_FLOW_ITEM_TYPE_VF, 1324 RTE_FLOW_ITEM_TYPE_END, 1325 }; 1326 1327 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = { 1328 RTE_FLOW_ITEM_TYPE_ETH, 1329 RTE_FLOW_ITEM_TYPE_VLAN, 1330 RTE_FLOW_ITEM_TYPE_IPV4, 1331 RTE_FLOW_ITEM_TYPE_TCP, 1332 RTE_FLOW_ITEM_TYPE_RAW, 1333 RTE_FLOW_ITEM_TYPE_VF, 1334 RTE_FLOW_ITEM_TYPE_END, 1335 }; 1336 1337 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = { 1338 RTE_FLOW_ITEM_TYPE_ETH, 1339 RTE_FLOW_ITEM_TYPE_VLAN, 1340 RTE_FLOW_ITEM_TYPE_IPV4, 1341 RTE_FLOW_ITEM_TYPE_TCP, 1342 RTE_FLOW_ITEM_TYPE_RAW, 1343 RTE_FLOW_ITEM_TYPE_RAW, 1344 RTE_FLOW_ITEM_TYPE_VF, 1345 RTE_FLOW_ITEM_TYPE_END, 1346 }; 1347 1348 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = { 1349 RTE_FLOW_ITEM_TYPE_ETH, 1350 RTE_FLOW_ITEM_TYPE_VLAN, 1351 RTE_FLOW_ITEM_TYPE_IPV4, 1352 RTE_FLOW_ITEM_TYPE_TCP, 1353 RTE_FLOW_ITEM_TYPE_RAW, 1354 RTE_FLOW_ITEM_TYPE_RAW, 1355 RTE_FLOW_ITEM_TYPE_RAW, 1356 RTE_FLOW_ITEM_TYPE_VF, 1357 RTE_FLOW_ITEM_TYPE_END, 1358 }; 1359 1360 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = { 1361 RTE_FLOW_ITEM_TYPE_ETH, 1362 RTE_FLOW_ITEM_TYPE_VLAN, 1363 RTE_FLOW_ITEM_TYPE_IPV4, 1364 RTE_FLOW_ITEM_TYPE_SCTP, 1365 RTE_FLOW_ITEM_TYPE_RAW, 1366 RTE_FLOW_ITEM_TYPE_VF, 1367 RTE_FLOW_ITEM_TYPE_END, 1368 }; 1369 1370 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = { 1371 RTE_FLOW_ITEM_TYPE_ETH, 1372 RTE_FLOW_ITEM_TYPE_VLAN, 1373 RTE_FLOW_ITEM_TYPE_IPV4, 1374 RTE_FLOW_ITEM_TYPE_SCTP, 1375 RTE_FLOW_ITEM_TYPE_RAW, 1376 RTE_FLOW_ITEM_TYPE_RAW, 1377 RTE_FLOW_ITEM_TYPE_VF, 1378 RTE_FLOW_ITEM_TYPE_END, 1379 }; 1380 1381 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = { 1382 RTE_FLOW_ITEM_TYPE_ETH, 1383 RTE_FLOW_ITEM_TYPE_VLAN, 1384 RTE_FLOW_ITEM_TYPE_IPV4, 1385 RTE_FLOW_ITEM_TYPE_SCTP, 1386 RTE_FLOW_ITEM_TYPE_RAW, 1387 RTE_FLOW_ITEM_TYPE_RAW, 1388 RTE_FLOW_ITEM_TYPE_RAW, 1389 RTE_FLOW_ITEM_TYPE_VF, 1390 RTE_FLOW_ITEM_TYPE_END, 1391 }; 1392 1393 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = { 1394 RTE_FLOW_ITEM_TYPE_ETH, 1395 RTE_FLOW_ITEM_TYPE_VLAN, 1396 RTE_FLOW_ITEM_TYPE_IPV6, 1397 RTE_FLOW_ITEM_TYPE_RAW, 1398 RTE_FLOW_ITEM_TYPE_VF, 1399 RTE_FLOW_ITEM_TYPE_END, 1400 }; 1401 1402 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = { 1403 RTE_FLOW_ITEM_TYPE_ETH, 1404 RTE_FLOW_ITEM_TYPE_VLAN, 1405 RTE_FLOW_ITEM_TYPE_IPV6, 1406 RTE_FLOW_ITEM_TYPE_RAW, 1407 RTE_FLOW_ITEM_TYPE_RAW, 1408 RTE_FLOW_ITEM_TYPE_VF, 1409 RTE_FLOW_ITEM_TYPE_END, 1410 }; 1411 1412 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = { 1413 RTE_FLOW_ITEM_TYPE_ETH, 1414 RTE_FLOW_ITEM_TYPE_VLAN, 1415 RTE_FLOW_ITEM_TYPE_IPV6, 1416 RTE_FLOW_ITEM_TYPE_RAW, 1417 RTE_FLOW_ITEM_TYPE_RAW, 1418 RTE_FLOW_ITEM_TYPE_RAW, 1419 RTE_FLOW_ITEM_TYPE_VF, 1420 RTE_FLOW_ITEM_TYPE_END, 1421 }; 1422 1423 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = { 1424 RTE_FLOW_ITEM_TYPE_ETH, 1425 RTE_FLOW_ITEM_TYPE_VLAN, 1426 RTE_FLOW_ITEM_TYPE_IPV6, 1427 RTE_FLOW_ITEM_TYPE_UDP, 1428 RTE_FLOW_ITEM_TYPE_RAW, 1429 RTE_FLOW_ITEM_TYPE_VF, 1430 RTE_FLOW_ITEM_TYPE_END, 1431 }; 1432 1433 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = { 1434 RTE_FLOW_ITEM_TYPE_ETH, 1435 RTE_FLOW_ITEM_TYPE_VLAN, 1436 RTE_FLOW_ITEM_TYPE_IPV6, 1437 RTE_FLOW_ITEM_TYPE_UDP, 1438 RTE_FLOW_ITEM_TYPE_RAW, 1439 RTE_FLOW_ITEM_TYPE_RAW, 1440 RTE_FLOW_ITEM_TYPE_VF, 1441 RTE_FLOW_ITEM_TYPE_END, 1442 }; 1443 1444 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = { 1445 RTE_FLOW_ITEM_TYPE_ETH, 1446 RTE_FLOW_ITEM_TYPE_VLAN, 1447 RTE_FLOW_ITEM_TYPE_IPV6, 1448 RTE_FLOW_ITEM_TYPE_UDP, 1449 RTE_FLOW_ITEM_TYPE_RAW, 1450 RTE_FLOW_ITEM_TYPE_RAW, 1451 RTE_FLOW_ITEM_TYPE_RAW, 1452 RTE_FLOW_ITEM_TYPE_VF, 1453 RTE_FLOW_ITEM_TYPE_END, 1454 }; 1455 1456 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = { 1457 RTE_FLOW_ITEM_TYPE_ETH, 1458 RTE_FLOW_ITEM_TYPE_VLAN, 1459 RTE_FLOW_ITEM_TYPE_IPV6, 1460 RTE_FLOW_ITEM_TYPE_TCP, 1461 RTE_FLOW_ITEM_TYPE_RAW, 1462 RTE_FLOW_ITEM_TYPE_VF, 1463 RTE_FLOW_ITEM_TYPE_END, 1464 }; 1465 1466 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = { 1467 RTE_FLOW_ITEM_TYPE_ETH, 1468 RTE_FLOW_ITEM_TYPE_VLAN, 1469 RTE_FLOW_ITEM_TYPE_IPV6, 1470 RTE_FLOW_ITEM_TYPE_TCP, 1471 RTE_FLOW_ITEM_TYPE_RAW, 1472 RTE_FLOW_ITEM_TYPE_RAW, 1473 RTE_FLOW_ITEM_TYPE_VF, 1474 RTE_FLOW_ITEM_TYPE_END, 1475 }; 1476 1477 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = { 1478 RTE_FLOW_ITEM_TYPE_ETH, 1479 RTE_FLOW_ITEM_TYPE_VLAN, 1480 RTE_FLOW_ITEM_TYPE_IPV6, 1481 RTE_FLOW_ITEM_TYPE_TCP, 1482 RTE_FLOW_ITEM_TYPE_RAW, 1483 RTE_FLOW_ITEM_TYPE_RAW, 1484 RTE_FLOW_ITEM_TYPE_RAW, 1485 RTE_FLOW_ITEM_TYPE_VF, 1486 RTE_FLOW_ITEM_TYPE_END, 1487 }; 1488 1489 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = { 1490 RTE_FLOW_ITEM_TYPE_ETH, 1491 RTE_FLOW_ITEM_TYPE_VLAN, 1492 RTE_FLOW_ITEM_TYPE_IPV6, 1493 RTE_FLOW_ITEM_TYPE_SCTP, 1494 RTE_FLOW_ITEM_TYPE_RAW, 1495 RTE_FLOW_ITEM_TYPE_VF, 1496 RTE_FLOW_ITEM_TYPE_END, 1497 }; 1498 1499 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = { 1500 RTE_FLOW_ITEM_TYPE_ETH, 1501 RTE_FLOW_ITEM_TYPE_VLAN, 1502 RTE_FLOW_ITEM_TYPE_IPV6, 1503 RTE_FLOW_ITEM_TYPE_SCTP, 1504 RTE_FLOW_ITEM_TYPE_RAW, 1505 RTE_FLOW_ITEM_TYPE_RAW, 1506 RTE_FLOW_ITEM_TYPE_VF, 1507 RTE_FLOW_ITEM_TYPE_END, 1508 }; 1509 1510 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = { 1511 RTE_FLOW_ITEM_TYPE_ETH, 1512 RTE_FLOW_ITEM_TYPE_VLAN, 1513 RTE_FLOW_ITEM_TYPE_IPV6, 1514 RTE_FLOW_ITEM_TYPE_SCTP, 1515 RTE_FLOW_ITEM_TYPE_RAW, 1516 RTE_FLOW_ITEM_TYPE_RAW, 1517 RTE_FLOW_ITEM_TYPE_RAW, 1518 RTE_FLOW_ITEM_TYPE_VF, 1519 RTE_FLOW_ITEM_TYPE_END, 1520 }; 1521 1522 /* Pattern matched tunnel filter */ 1523 static enum rte_flow_item_type pattern_vxlan_1[] = { 1524 RTE_FLOW_ITEM_TYPE_ETH, 1525 RTE_FLOW_ITEM_TYPE_IPV4, 1526 RTE_FLOW_ITEM_TYPE_UDP, 1527 RTE_FLOW_ITEM_TYPE_VXLAN, 1528 RTE_FLOW_ITEM_TYPE_ETH, 1529 RTE_FLOW_ITEM_TYPE_END, 1530 }; 1531 1532 static enum rte_flow_item_type pattern_vxlan_2[] = { 1533 RTE_FLOW_ITEM_TYPE_ETH, 1534 RTE_FLOW_ITEM_TYPE_IPV6, 1535 RTE_FLOW_ITEM_TYPE_UDP, 1536 RTE_FLOW_ITEM_TYPE_VXLAN, 1537 RTE_FLOW_ITEM_TYPE_ETH, 1538 RTE_FLOW_ITEM_TYPE_END, 1539 }; 1540 1541 static enum rte_flow_item_type pattern_vxlan_3[] = { 1542 RTE_FLOW_ITEM_TYPE_ETH, 1543 RTE_FLOW_ITEM_TYPE_IPV4, 1544 RTE_FLOW_ITEM_TYPE_UDP, 1545 RTE_FLOW_ITEM_TYPE_VXLAN, 1546 RTE_FLOW_ITEM_TYPE_ETH, 1547 RTE_FLOW_ITEM_TYPE_VLAN, 1548 RTE_FLOW_ITEM_TYPE_END, 1549 }; 1550 1551 static enum rte_flow_item_type pattern_vxlan_4[] = { 1552 RTE_FLOW_ITEM_TYPE_ETH, 1553 RTE_FLOW_ITEM_TYPE_IPV6, 1554 RTE_FLOW_ITEM_TYPE_UDP, 1555 RTE_FLOW_ITEM_TYPE_VXLAN, 1556 RTE_FLOW_ITEM_TYPE_ETH, 1557 RTE_FLOW_ITEM_TYPE_VLAN, 1558 RTE_FLOW_ITEM_TYPE_END, 1559 }; 1560 1561 static enum rte_flow_item_type pattern_nvgre_1[] = { 1562 RTE_FLOW_ITEM_TYPE_ETH, 1563 RTE_FLOW_ITEM_TYPE_IPV4, 1564 RTE_FLOW_ITEM_TYPE_NVGRE, 1565 RTE_FLOW_ITEM_TYPE_ETH, 1566 RTE_FLOW_ITEM_TYPE_END, 1567 }; 1568 1569 static enum rte_flow_item_type pattern_nvgre_2[] = { 1570 RTE_FLOW_ITEM_TYPE_ETH, 1571 RTE_FLOW_ITEM_TYPE_IPV6, 1572 RTE_FLOW_ITEM_TYPE_NVGRE, 1573 RTE_FLOW_ITEM_TYPE_ETH, 1574 RTE_FLOW_ITEM_TYPE_END, 1575 }; 1576 1577 static enum rte_flow_item_type pattern_nvgre_3[] = { 1578 RTE_FLOW_ITEM_TYPE_ETH, 1579 RTE_FLOW_ITEM_TYPE_IPV4, 1580 RTE_FLOW_ITEM_TYPE_NVGRE, 1581 RTE_FLOW_ITEM_TYPE_ETH, 1582 RTE_FLOW_ITEM_TYPE_VLAN, 1583 RTE_FLOW_ITEM_TYPE_END, 1584 }; 1585 1586 static enum rte_flow_item_type pattern_nvgre_4[] = { 1587 RTE_FLOW_ITEM_TYPE_ETH, 1588 RTE_FLOW_ITEM_TYPE_IPV6, 1589 RTE_FLOW_ITEM_TYPE_NVGRE, 1590 RTE_FLOW_ITEM_TYPE_ETH, 1591 RTE_FLOW_ITEM_TYPE_VLAN, 1592 RTE_FLOW_ITEM_TYPE_END, 1593 }; 1594 1595 static enum rte_flow_item_type pattern_mpls_1[] = { 1596 RTE_FLOW_ITEM_TYPE_ETH, 1597 RTE_FLOW_ITEM_TYPE_IPV4, 1598 RTE_FLOW_ITEM_TYPE_UDP, 1599 RTE_FLOW_ITEM_TYPE_MPLS, 1600 RTE_FLOW_ITEM_TYPE_END, 1601 }; 1602 1603 static enum rte_flow_item_type pattern_mpls_2[] = { 1604 RTE_FLOW_ITEM_TYPE_ETH, 1605 RTE_FLOW_ITEM_TYPE_IPV6, 1606 RTE_FLOW_ITEM_TYPE_UDP, 1607 RTE_FLOW_ITEM_TYPE_MPLS, 1608 RTE_FLOW_ITEM_TYPE_END, 1609 }; 1610 1611 static enum rte_flow_item_type pattern_mpls_3[] = { 1612 RTE_FLOW_ITEM_TYPE_ETH, 1613 RTE_FLOW_ITEM_TYPE_IPV4, 1614 RTE_FLOW_ITEM_TYPE_GRE, 1615 RTE_FLOW_ITEM_TYPE_MPLS, 1616 RTE_FLOW_ITEM_TYPE_END, 1617 }; 1618 1619 static enum rte_flow_item_type pattern_mpls_4[] = { 1620 RTE_FLOW_ITEM_TYPE_ETH, 1621 RTE_FLOW_ITEM_TYPE_IPV6, 1622 RTE_FLOW_ITEM_TYPE_GRE, 1623 RTE_FLOW_ITEM_TYPE_MPLS, 1624 RTE_FLOW_ITEM_TYPE_END, 1625 }; 1626 1627 static enum rte_flow_item_type pattern_qinq_1[] = { 1628 RTE_FLOW_ITEM_TYPE_ETH, 1629 RTE_FLOW_ITEM_TYPE_VLAN, 1630 RTE_FLOW_ITEM_TYPE_VLAN, 1631 RTE_FLOW_ITEM_TYPE_END, 1632 }; 1633 1634 static enum rte_flow_item_type pattern_fdir_ipv4_l2tpv3oip[] = { 1635 RTE_FLOW_ITEM_TYPE_ETH, 1636 RTE_FLOW_ITEM_TYPE_IPV4, 1637 RTE_FLOW_ITEM_TYPE_L2TPV3OIP, 1638 RTE_FLOW_ITEM_TYPE_END, 1639 }; 1640 1641 static enum rte_flow_item_type pattern_fdir_ipv6_l2tpv3oip[] = { 1642 RTE_FLOW_ITEM_TYPE_ETH, 1643 RTE_FLOW_ITEM_TYPE_IPV6, 1644 RTE_FLOW_ITEM_TYPE_L2TPV3OIP, 1645 RTE_FLOW_ITEM_TYPE_END, 1646 }; 1647 1648 static enum rte_flow_item_type pattern_fdir_ipv4_esp[] = { 1649 RTE_FLOW_ITEM_TYPE_ETH, 1650 RTE_FLOW_ITEM_TYPE_IPV4, 1651 RTE_FLOW_ITEM_TYPE_ESP, 1652 RTE_FLOW_ITEM_TYPE_END, 1653 }; 1654 1655 static enum rte_flow_item_type pattern_fdir_ipv6_esp[] = { 1656 RTE_FLOW_ITEM_TYPE_ETH, 1657 RTE_FLOW_ITEM_TYPE_IPV6, 1658 RTE_FLOW_ITEM_TYPE_ESP, 1659 RTE_FLOW_ITEM_TYPE_END, 1660 }; 1661 1662 static enum rte_flow_item_type pattern_fdir_ipv4_udp_esp[] = { 1663 RTE_FLOW_ITEM_TYPE_ETH, 1664 RTE_FLOW_ITEM_TYPE_IPV4, 1665 RTE_FLOW_ITEM_TYPE_UDP, 1666 RTE_FLOW_ITEM_TYPE_ESP, 1667 RTE_FLOW_ITEM_TYPE_END, 1668 }; 1669 1670 static enum rte_flow_item_type pattern_fdir_ipv6_udp_esp[] = { 1671 RTE_FLOW_ITEM_TYPE_ETH, 1672 RTE_FLOW_ITEM_TYPE_IPV6, 1673 RTE_FLOW_ITEM_TYPE_UDP, 1674 RTE_FLOW_ITEM_TYPE_ESP, 1675 RTE_FLOW_ITEM_TYPE_END, 1676 }; 1677 1678 static struct i40e_valid_pattern i40e_supported_patterns[] = { 1679 /* Ethertype */ 1680 { pattern_ethertype, i40e_flow_parse_ethertype_filter }, 1681 /* FDIR - support default flow type without flexible payload*/ 1682 { pattern_ethertype, i40e_flow_parse_fdir_filter }, 1683 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter }, 1684 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter }, 1685 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter }, 1686 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter }, 1687 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter }, 1688 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter }, 1689 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter }, 1690 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter }, 1691 { pattern_fdir_ipv4_esp, i40e_flow_parse_fdir_filter }, 1692 { pattern_fdir_ipv4_udp_esp, i40e_flow_parse_fdir_filter }, 1693 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter }, 1694 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter }, 1695 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter }, 1696 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter }, 1697 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter }, 1698 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter }, 1699 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter }, 1700 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter }, 1701 { pattern_fdir_ipv6_esp, i40e_flow_parse_fdir_filter }, 1702 { pattern_fdir_ipv6_udp_esp, i40e_flow_parse_fdir_filter }, 1703 /* FDIR - support default flow type with flexible payload */ 1704 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter }, 1705 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter }, 1706 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter }, 1707 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter }, 1708 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter }, 1709 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter }, 1710 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter }, 1711 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter }, 1712 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter }, 1713 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter }, 1714 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter }, 1715 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter }, 1716 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter }, 1717 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter }, 1718 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter }, 1719 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter }, 1720 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter }, 1721 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter }, 1722 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter }, 1723 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter }, 1724 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter }, 1725 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter }, 1726 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter }, 1727 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter }, 1728 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter }, 1729 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter }, 1730 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter }, 1731 /* FDIR - support single vlan input set */ 1732 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter }, 1733 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter }, 1734 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter }, 1735 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter }, 1736 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter }, 1737 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter }, 1738 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter }, 1739 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter }, 1740 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter }, 1741 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter }, 1742 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter }, 1743 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter }, 1744 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter }, 1745 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter }, 1746 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter }, 1747 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter }, 1748 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter }, 1749 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter }, 1750 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter }, 1751 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter }, 1752 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter }, 1753 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter }, 1754 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter }, 1755 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter }, 1756 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter }, 1757 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter }, 1758 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter }, 1759 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter }, 1760 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter }, 1761 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter }, 1762 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter }, 1763 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter }, 1764 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter }, 1765 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter }, 1766 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter }, 1767 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter }, 1768 /* FDIR - support VF item */ 1769 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter }, 1770 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter }, 1771 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter }, 1772 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter }, 1773 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter }, 1774 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter }, 1775 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter }, 1776 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter }, 1777 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter }, 1778 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter }, 1779 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter }, 1780 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter }, 1781 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter }, 1782 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter }, 1783 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1784 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1785 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1786 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1787 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1788 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1789 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1790 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1791 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1792 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter }, 1793 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter }, 1794 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter }, 1795 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1796 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1797 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1798 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1799 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1800 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1801 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1802 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1803 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1804 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter }, 1805 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter }, 1806 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter }, 1807 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter }, 1808 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter }, 1809 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter }, 1810 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter }, 1811 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter }, 1812 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter }, 1813 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter }, 1814 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter }, 1815 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter }, 1816 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter }, 1817 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter }, 1818 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter }, 1819 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1820 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1821 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1822 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1823 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1824 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1825 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1826 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1827 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1828 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter }, 1829 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter }, 1830 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter }, 1831 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1832 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1833 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1834 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1835 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1836 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1837 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1838 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1839 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1840 /* VXLAN */ 1841 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter }, 1842 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter }, 1843 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter }, 1844 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter }, 1845 /* NVGRE */ 1846 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter }, 1847 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter }, 1848 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter }, 1849 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter }, 1850 /* MPLSoUDP & MPLSoGRE */ 1851 { pattern_mpls_1, i40e_flow_parse_mpls_filter }, 1852 { pattern_mpls_2, i40e_flow_parse_mpls_filter }, 1853 { pattern_mpls_3, i40e_flow_parse_mpls_filter }, 1854 { pattern_mpls_4, i40e_flow_parse_mpls_filter }, 1855 /* GTP-C & GTP-U */ 1856 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter }, 1857 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter }, 1858 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter }, 1859 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter }, 1860 /* QINQ */ 1861 { pattern_qinq_1, i40e_flow_parse_qinq_filter }, 1862 /* L2TPv3 over IP */ 1863 { pattern_fdir_ipv4_l2tpv3oip, i40e_flow_parse_fdir_filter }, 1864 { pattern_fdir_ipv6_l2tpv3oip, i40e_flow_parse_fdir_filter }, 1865 /* L4 over port */ 1866 { pattern_fdir_ipv4_udp, i40e_flow_parse_l4_cloud_filter }, 1867 { pattern_fdir_ipv4_tcp, i40e_flow_parse_l4_cloud_filter }, 1868 { pattern_fdir_ipv4_sctp, i40e_flow_parse_l4_cloud_filter }, 1869 { pattern_fdir_ipv6_udp, i40e_flow_parse_l4_cloud_filter }, 1870 { pattern_fdir_ipv6_tcp, i40e_flow_parse_l4_cloud_filter }, 1871 { pattern_fdir_ipv6_sctp, i40e_flow_parse_l4_cloud_filter }, 1872 }; 1873 1874 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 1875 do { \ 1876 act = actions + index; \ 1877 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 1878 index++; \ 1879 act = actions + index; \ 1880 } \ 1881 } while (0) 1882 1883 /* Find the first VOID or non-VOID item pointer */ 1884 static const struct rte_flow_item * 1885 i40e_find_first_item(const struct rte_flow_item *item, bool is_void) 1886 { 1887 bool is_find; 1888 1889 while (item->type != RTE_FLOW_ITEM_TYPE_END) { 1890 if (is_void) 1891 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID; 1892 else 1893 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID; 1894 if (is_find) 1895 break; 1896 item++; 1897 } 1898 return item; 1899 } 1900 1901 /* Skip all VOID items of the pattern */ 1902 static void 1903 i40e_pattern_skip_void_item(struct rte_flow_item *items, 1904 const struct rte_flow_item *pattern) 1905 { 1906 uint32_t cpy_count = 0; 1907 const struct rte_flow_item *pb = pattern, *pe = pattern; 1908 1909 for (;;) { 1910 /* Find a non-void item first */ 1911 pb = i40e_find_first_item(pb, false); 1912 if (pb->type == RTE_FLOW_ITEM_TYPE_END) { 1913 pe = pb; 1914 break; 1915 } 1916 1917 /* Find a void item */ 1918 pe = i40e_find_first_item(pb + 1, true); 1919 1920 cpy_count = pe - pb; 1921 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count); 1922 1923 items += cpy_count; 1924 1925 if (pe->type == RTE_FLOW_ITEM_TYPE_END) { 1926 pb = pe; 1927 break; 1928 } 1929 1930 pb = pe + 1; 1931 } 1932 /* Copy the END item. */ 1933 rte_memcpy(items, pe, sizeof(struct rte_flow_item)); 1934 } 1935 1936 /* Check if the pattern matches a supported item type array */ 1937 static bool 1938 i40e_match_pattern(enum rte_flow_item_type *item_array, 1939 struct rte_flow_item *pattern) 1940 { 1941 struct rte_flow_item *item = pattern; 1942 1943 while ((*item_array == item->type) && 1944 (*item_array != RTE_FLOW_ITEM_TYPE_END)) { 1945 item_array++; 1946 item++; 1947 } 1948 1949 return (*item_array == RTE_FLOW_ITEM_TYPE_END && 1950 item->type == RTE_FLOW_ITEM_TYPE_END); 1951 } 1952 1953 /* Find if there's parse filter function matched */ 1954 static parse_filter_t 1955 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx) 1956 { 1957 parse_filter_t parse_filter = NULL; 1958 uint8_t i = *idx; 1959 1960 for (; i < RTE_DIM(i40e_supported_patterns); i++) { 1961 if (i40e_match_pattern(i40e_supported_patterns[i].items, 1962 pattern)) { 1963 parse_filter = i40e_supported_patterns[i].parse_filter; 1964 break; 1965 } 1966 } 1967 1968 *idx = ++i; 1969 1970 return parse_filter; 1971 } 1972 1973 /* Parse attributes */ 1974 static int 1975 i40e_flow_parse_attr(const struct rte_flow_attr *attr, 1976 struct rte_flow_error *error) 1977 { 1978 /* Must be input direction */ 1979 if (!attr->ingress) { 1980 rte_flow_error_set(error, EINVAL, 1981 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1982 attr, "Only support ingress."); 1983 return -rte_errno; 1984 } 1985 1986 /* Not supported */ 1987 if (attr->egress) { 1988 rte_flow_error_set(error, EINVAL, 1989 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, 1990 attr, "Not support egress."); 1991 return -rte_errno; 1992 } 1993 1994 /* Not supported */ 1995 if (attr->priority) { 1996 rte_flow_error_set(error, EINVAL, 1997 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1998 attr, "Not support priority."); 1999 return -rte_errno; 2000 } 2001 2002 /* Not supported */ 2003 if (attr->group) { 2004 rte_flow_error_set(error, EINVAL, 2005 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 2006 attr, "Not support group."); 2007 return -rte_errno; 2008 } 2009 2010 return 0; 2011 } 2012 2013 static uint16_t 2014 i40e_get_outer_vlan(struct rte_eth_dev *dev) 2015 { 2016 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2017 int qinq = dev->data->dev_conf.rxmode.offloads & 2018 DEV_RX_OFFLOAD_VLAN_EXTEND; 2019 uint64_t reg_r = 0; 2020 uint16_t reg_id; 2021 uint16_t tpid; 2022 2023 if (qinq) 2024 reg_id = 2; 2025 else 2026 reg_id = 3; 2027 2028 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), 2029 ®_r, NULL); 2030 2031 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF; 2032 2033 return tpid; 2034 } 2035 2036 /* 1. Last in item should be NULL as range is not supported. 2037 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE. 2038 * 3. SRC mac_addr mask should be 00:00:00:00:00:00. 2039 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or 2040 * FF:FF:FF:FF:FF:FF 2041 * 5. Ether_type mask should be 0xFFFF. 2042 */ 2043 static int 2044 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev, 2045 const struct rte_flow_item *pattern, 2046 struct rte_flow_error *error, 2047 struct rte_eth_ethertype_filter *filter) 2048 { 2049 const struct rte_flow_item *item = pattern; 2050 const struct rte_flow_item_eth *eth_spec; 2051 const struct rte_flow_item_eth *eth_mask; 2052 enum rte_flow_item_type item_type; 2053 2054 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 2055 if (item->last) { 2056 rte_flow_error_set(error, EINVAL, 2057 RTE_FLOW_ERROR_TYPE_ITEM, 2058 item, 2059 "Not support range"); 2060 return -rte_errno; 2061 } 2062 item_type = item->type; 2063 switch (item_type) { 2064 case RTE_FLOW_ITEM_TYPE_ETH: 2065 eth_spec = item->spec; 2066 eth_mask = item->mask; 2067 /* Get the MAC info. */ 2068 if (!eth_spec || !eth_mask) { 2069 rte_flow_error_set(error, EINVAL, 2070 RTE_FLOW_ERROR_TYPE_ITEM, 2071 item, 2072 "NULL ETH spec/mask"); 2073 return -rte_errno; 2074 } 2075 2076 /* Mask bits of source MAC address must be full of 0. 2077 * Mask bits of destination MAC address must be full 2078 * of 1 or full of 0. 2079 */ 2080 if (!rte_is_zero_ether_addr(ð_mask->src) || 2081 (!rte_is_zero_ether_addr(ð_mask->dst) && 2082 !rte_is_broadcast_ether_addr(ð_mask->dst))) { 2083 rte_flow_error_set(error, EINVAL, 2084 RTE_FLOW_ERROR_TYPE_ITEM, 2085 item, 2086 "Invalid MAC_addr mask"); 2087 return -rte_errno; 2088 } 2089 2090 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) { 2091 rte_flow_error_set(error, EINVAL, 2092 RTE_FLOW_ERROR_TYPE_ITEM, 2093 item, 2094 "Invalid ethertype mask"); 2095 return -rte_errno; 2096 } 2097 2098 /* If mask bits of destination MAC address 2099 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC. 2100 */ 2101 if (rte_is_broadcast_ether_addr(ð_mask->dst)) { 2102 filter->mac_addr = eth_spec->dst; 2103 filter->flags |= RTE_ETHTYPE_FLAGS_MAC; 2104 } else { 2105 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC; 2106 } 2107 filter->ether_type = rte_be_to_cpu_16(eth_spec->type); 2108 2109 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 2110 filter->ether_type == RTE_ETHER_TYPE_IPV6 || 2111 filter->ether_type == RTE_ETHER_TYPE_LLDP || 2112 filter->ether_type == i40e_get_outer_vlan(dev)) { 2113 rte_flow_error_set(error, EINVAL, 2114 RTE_FLOW_ERROR_TYPE_ITEM, 2115 item, 2116 "Unsupported ether_type in" 2117 " control packet filter."); 2118 return -rte_errno; 2119 } 2120 break; 2121 default: 2122 break; 2123 } 2124 } 2125 2126 return 0; 2127 } 2128 2129 /* Ethertype action only supports QUEUE or DROP. */ 2130 static int 2131 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev, 2132 const struct rte_flow_action *actions, 2133 struct rte_flow_error *error, 2134 struct rte_eth_ethertype_filter *filter) 2135 { 2136 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2137 const struct rte_flow_action *act; 2138 const struct rte_flow_action_queue *act_q; 2139 uint32_t index = 0; 2140 2141 /* Check if the first non-void action is QUEUE or DROP. */ 2142 NEXT_ITEM_OF_ACTION(act, actions, index); 2143 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE && 2144 act->type != RTE_FLOW_ACTION_TYPE_DROP) { 2145 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 2146 act, "Not supported action."); 2147 return -rte_errno; 2148 } 2149 2150 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 2151 act_q = act->conf; 2152 filter->queue = act_q->index; 2153 if (filter->queue >= pf->dev_data->nb_rx_queues) { 2154 rte_flow_error_set(error, EINVAL, 2155 RTE_FLOW_ERROR_TYPE_ACTION, 2156 act, "Invalid queue ID for" 2157 " ethertype_filter."); 2158 return -rte_errno; 2159 } 2160 } else { 2161 filter->flags |= RTE_ETHTYPE_FLAGS_DROP; 2162 } 2163 2164 /* Check if the next non-void item is END */ 2165 index++; 2166 NEXT_ITEM_OF_ACTION(act, actions, index); 2167 if (act->type != RTE_FLOW_ACTION_TYPE_END) { 2168 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 2169 act, "Not supported action."); 2170 return -rte_errno; 2171 } 2172 2173 return 0; 2174 } 2175 2176 static int 2177 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev, 2178 const struct rte_flow_attr *attr, 2179 const struct rte_flow_item pattern[], 2180 const struct rte_flow_action actions[], 2181 struct rte_flow_error *error, 2182 union i40e_filter_t *filter) 2183 { 2184 struct rte_eth_ethertype_filter *ethertype_filter = 2185 &filter->ethertype_filter; 2186 int ret; 2187 2188 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error, 2189 ethertype_filter); 2190 if (ret) 2191 return ret; 2192 2193 ret = i40e_flow_parse_ethertype_action(dev, actions, error, 2194 ethertype_filter); 2195 if (ret) 2196 return ret; 2197 2198 ret = i40e_flow_parse_attr(attr, error); 2199 if (ret) 2200 return ret; 2201 2202 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE; 2203 2204 return ret; 2205 } 2206 2207 static int 2208 i40e_flow_check_raw_item(const struct rte_flow_item *item, 2209 const struct rte_flow_item_raw *raw_spec, 2210 struct rte_flow_error *error) 2211 { 2212 if (!raw_spec->relative) { 2213 rte_flow_error_set(error, EINVAL, 2214 RTE_FLOW_ERROR_TYPE_ITEM, 2215 item, 2216 "Relative should be 1."); 2217 return -rte_errno; 2218 } 2219 2220 if (raw_spec->offset % sizeof(uint16_t)) { 2221 rte_flow_error_set(error, EINVAL, 2222 RTE_FLOW_ERROR_TYPE_ITEM, 2223 item, 2224 "Offset should be even."); 2225 return -rte_errno; 2226 } 2227 2228 if (raw_spec->search || raw_spec->limit) { 2229 rte_flow_error_set(error, EINVAL, 2230 RTE_FLOW_ERROR_TYPE_ITEM, 2231 item, 2232 "search or limit is not supported."); 2233 return -rte_errno; 2234 } 2235 2236 if (raw_spec->offset < 0) { 2237 rte_flow_error_set(error, EINVAL, 2238 RTE_FLOW_ERROR_TYPE_ITEM, 2239 item, 2240 "Offset should be non-negative."); 2241 return -rte_errno; 2242 } 2243 return 0; 2244 } 2245 2246 static int 2247 i40e_flow_set_fdir_inset(struct i40e_pf *pf, 2248 enum i40e_filter_pctype pctype, 2249 uint64_t input_set) 2250 { 2251 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 2252 uint64_t inset_reg = 0; 2253 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 2254 int i, num; 2255 2256 /* Check if the input set is valid */ 2257 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR, 2258 input_set) != 0) { 2259 PMD_DRV_LOG(ERR, "Invalid input set"); 2260 return -EINVAL; 2261 } 2262 2263 /* Check if the configuration is conflicted */ 2264 if (pf->fdir.inset_flag[pctype] && 2265 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t))) 2266 return -1; 2267 2268 if (pf->fdir.inset_flag[pctype] && 2269 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t))) 2270 return 0; 2271 2272 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 2273 I40E_INSET_MASK_NUM_REG); 2274 if (num < 0) 2275 return -EINVAL; 2276 2277 if (pf->support_multi_driver) { 2278 for (i = 0; i < num; i++) 2279 if (i40e_read_rx_ctl(hw, 2280 I40E_GLQF_FD_MSK(i, pctype)) != 2281 mask_reg[i]) { 2282 PMD_DRV_LOG(ERR, "Input set setting is not" 2283 " supported with" 2284 " `support-multi-driver`" 2285 " enabled!"); 2286 return -EPERM; 2287 } 2288 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 2289 if (i40e_read_rx_ctl(hw, 2290 I40E_GLQF_FD_MSK(i, pctype)) != 0) { 2291 PMD_DRV_LOG(ERR, "Input set setting is not" 2292 " supported with" 2293 " `support-multi-driver`" 2294 " enabled!"); 2295 return -EPERM; 2296 } 2297 2298 } else { 2299 for (i = 0; i < num; i++) 2300 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 2301 mask_reg[i]); 2302 /*clear unused mask registers of the pctype */ 2303 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 2304 i40e_check_write_reg(hw, 2305 I40E_GLQF_FD_MSK(i, pctype), 0); 2306 } 2307 2308 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 2309 2310 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 2311 (uint32_t)(inset_reg & UINT32_MAX)); 2312 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 2313 (uint32_t)((inset_reg >> 2314 I40E_32_BIT_WIDTH) & UINT32_MAX)); 2315 2316 I40E_WRITE_FLUSH(hw); 2317 2318 pf->fdir.input_set[pctype] = input_set; 2319 pf->fdir.inset_flag[pctype] = 1; 2320 return 0; 2321 } 2322 2323 static uint8_t 2324 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf, 2325 enum rte_flow_item_type item_type, 2326 struct i40e_fdir_filter_conf *filter) 2327 { 2328 struct i40e_customized_pctype *cus_pctype = NULL; 2329 2330 switch (item_type) { 2331 case RTE_FLOW_ITEM_TYPE_GTPC: 2332 cus_pctype = i40e_find_customized_pctype(pf, 2333 I40E_CUSTOMIZED_GTPC); 2334 break; 2335 case RTE_FLOW_ITEM_TYPE_GTPU: 2336 if (!filter->input.flow_ext.inner_ip) 2337 cus_pctype = i40e_find_customized_pctype(pf, 2338 I40E_CUSTOMIZED_GTPU); 2339 else if (filter->input.flow_ext.iip_type == 2340 I40E_FDIR_IPTYPE_IPV4) 2341 cus_pctype = i40e_find_customized_pctype(pf, 2342 I40E_CUSTOMIZED_GTPU_IPV4); 2343 else if (filter->input.flow_ext.iip_type == 2344 I40E_FDIR_IPTYPE_IPV6) 2345 cus_pctype = i40e_find_customized_pctype(pf, 2346 I40E_CUSTOMIZED_GTPU_IPV6); 2347 break; 2348 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP: 2349 if (filter->input.flow_ext.oip_type == I40E_FDIR_IPTYPE_IPV4) 2350 cus_pctype = i40e_find_customized_pctype(pf, 2351 I40E_CUSTOMIZED_IPV4_L2TPV3); 2352 else if (filter->input.flow_ext.oip_type == 2353 I40E_FDIR_IPTYPE_IPV6) 2354 cus_pctype = i40e_find_customized_pctype(pf, 2355 I40E_CUSTOMIZED_IPV6_L2TPV3); 2356 break; 2357 case RTE_FLOW_ITEM_TYPE_ESP: 2358 if (!filter->input.flow_ext.is_udp) { 2359 if (filter->input.flow_ext.oip_type == 2360 I40E_FDIR_IPTYPE_IPV4) 2361 cus_pctype = i40e_find_customized_pctype(pf, 2362 I40E_CUSTOMIZED_ESP_IPV4); 2363 else if (filter->input.flow_ext.oip_type == 2364 I40E_FDIR_IPTYPE_IPV6) 2365 cus_pctype = i40e_find_customized_pctype(pf, 2366 I40E_CUSTOMIZED_ESP_IPV6); 2367 } else { 2368 if (filter->input.flow_ext.oip_type == 2369 I40E_FDIR_IPTYPE_IPV4) 2370 cus_pctype = i40e_find_customized_pctype(pf, 2371 I40E_CUSTOMIZED_ESP_IPV4_UDP); 2372 else if (filter->input.flow_ext.oip_type == 2373 I40E_FDIR_IPTYPE_IPV6) 2374 cus_pctype = i40e_find_customized_pctype(pf, 2375 I40E_CUSTOMIZED_ESP_IPV6_UDP); 2376 filter->input.flow_ext.is_udp = false; 2377 } 2378 break; 2379 default: 2380 PMD_DRV_LOG(ERR, "Unsupported item type"); 2381 break; 2382 } 2383 2384 if (cus_pctype && cus_pctype->valid) 2385 return cus_pctype->pctype; 2386 2387 return I40E_FILTER_PCTYPE_INVALID; 2388 } 2389 2390 static void 2391 i40e_flow_set_filter_spi(struct i40e_fdir_filter_conf *filter, 2392 const struct rte_flow_item_esp *esp_spec) 2393 { 2394 if (filter->input.flow_ext.oip_type == 2395 I40E_FDIR_IPTYPE_IPV4) { 2396 if (filter->input.flow_ext.is_udp) 2397 filter->input.flow.esp_ipv4_udp_flow.spi = 2398 esp_spec->hdr.spi; 2399 else 2400 filter->input.flow.esp_ipv4_flow.spi = 2401 esp_spec->hdr.spi; 2402 } 2403 if (filter->input.flow_ext.oip_type == 2404 I40E_FDIR_IPTYPE_IPV6) { 2405 if (filter->input.flow_ext.is_udp) 2406 filter->input.flow.esp_ipv6_udp_flow.spi = 2407 esp_spec->hdr.spi; 2408 else 2409 filter->input.flow.esp_ipv6_flow.spi = 2410 esp_spec->hdr.spi; 2411 } 2412 } 2413 2414 /* 1. Last in item should be NULL as range is not supported. 2415 * 2. Supported patterns: refer to array i40e_supported_patterns. 2416 * 3. Default supported flow type and input set: refer to array 2417 * valid_fdir_inset_table in i40e_ethdev.c. 2418 * 4. Mask of fields which need to be matched should be 2419 * filled with 1. 2420 * 5. Mask of fields which needn't to be matched should be 2421 * filled with 0. 2422 * 6. GTP profile supports GTPv1 only. 2423 * 7. GTP-C response message ('source_port' = 2123) is not supported. 2424 */ 2425 static int 2426 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev, 2427 const struct rte_flow_attr *attr, 2428 const struct rte_flow_item *pattern, 2429 struct rte_flow_error *error, 2430 struct i40e_fdir_filter_conf *filter) 2431 { 2432 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2433 const struct rte_flow_item *item = pattern; 2434 const struct rte_flow_item_eth *eth_spec, *eth_mask; 2435 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask; 2436 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_last, *ipv4_mask; 2437 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask; 2438 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask; 2439 const struct rte_flow_item_udp *udp_spec, *udp_mask; 2440 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask; 2441 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask; 2442 const struct rte_flow_item_esp *esp_spec, *esp_mask; 2443 const struct rte_flow_item_raw *raw_spec, *raw_mask; 2444 const struct rte_flow_item_vf *vf_spec; 2445 const struct rte_flow_item_l2tpv3oip *l2tpv3oip_spec, *l2tpv3oip_mask; 2446 2447 uint8_t pctype = 0; 2448 uint64_t input_set = I40E_INSET_NONE; 2449 enum rte_flow_item_type item_type; 2450 enum rte_flow_item_type next_type; 2451 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END; 2452 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END; 2453 uint32_t i, j; 2454 uint8_t ipv6_addr_mask[16] = { 2455 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 2456 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2457 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX; 2458 uint8_t raw_id = 0; 2459 int32_t off_arr[I40E_MAX_FLXPLD_FIED]; 2460 uint16_t len_arr[I40E_MAX_FLXPLD_FIED]; 2461 struct i40e_fdir_flex_pit flex_pit; 2462 uint8_t next_dst_off = 0; 2463 uint16_t flex_size; 2464 uint16_t ether_type; 2465 uint32_t vtc_flow_cpu; 2466 bool outer_ip = true; 2467 uint8_t field_idx; 2468 int ret; 2469 2470 memset(off_arr, 0, sizeof(off_arr)); 2471 memset(len_arr, 0, sizeof(len_arr)); 2472 filter->input.flow_ext.customized_pctype = false; 2473 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 2474 if (item->last && item->type != RTE_FLOW_ITEM_TYPE_IPV4) { 2475 rte_flow_error_set(error, EINVAL, 2476 RTE_FLOW_ERROR_TYPE_ITEM, 2477 item, 2478 "Not support range"); 2479 return -rte_errno; 2480 } 2481 item_type = item->type; 2482 switch (item_type) { 2483 case RTE_FLOW_ITEM_TYPE_ETH: 2484 eth_spec = item->spec; 2485 eth_mask = item->mask; 2486 next_type = (item + 1)->type; 2487 2488 if (next_type == RTE_FLOW_ITEM_TYPE_END && 2489 (!eth_spec || !eth_mask)) { 2490 rte_flow_error_set(error, EINVAL, 2491 RTE_FLOW_ERROR_TYPE_ITEM, 2492 item, 2493 "NULL eth spec/mask."); 2494 return -rte_errno; 2495 } 2496 2497 if (eth_spec && eth_mask) { 2498 if (rte_is_broadcast_ether_addr(ð_mask->dst) && 2499 rte_is_zero_ether_addr(ð_mask->src)) { 2500 filter->input.flow.l2_flow.dst = 2501 eth_spec->dst; 2502 input_set |= I40E_INSET_DMAC; 2503 } else if (rte_is_zero_ether_addr(ð_mask->dst) && 2504 rte_is_broadcast_ether_addr(ð_mask->src)) { 2505 filter->input.flow.l2_flow.src = 2506 eth_spec->src; 2507 input_set |= I40E_INSET_SMAC; 2508 } else if (rte_is_broadcast_ether_addr(ð_mask->dst) && 2509 rte_is_broadcast_ether_addr(ð_mask->src)) { 2510 filter->input.flow.l2_flow.dst = 2511 eth_spec->dst; 2512 filter->input.flow.l2_flow.src = 2513 eth_spec->src; 2514 input_set |= (I40E_INSET_DMAC | I40E_INSET_SMAC); 2515 } else if (!rte_is_zero_ether_addr(ð_mask->src) || 2516 !rte_is_zero_ether_addr(ð_mask->dst)) { 2517 rte_flow_error_set(error, EINVAL, 2518 RTE_FLOW_ERROR_TYPE_ITEM, 2519 item, 2520 "Invalid MAC_addr mask."); 2521 return -rte_errno; 2522 } 2523 } 2524 if (eth_spec && eth_mask && 2525 next_type == RTE_FLOW_ITEM_TYPE_END) { 2526 if (eth_mask->type != RTE_BE16(0xffff)) { 2527 rte_flow_error_set(error, EINVAL, 2528 RTE_FLOW_ERROR_TYPE_ITEM, 2529 item, 2530 "Invalid type mask."); 2531 return -rte_errno; 2532 } 2533 2534 ether_type = rte_be_to_cpu_16(eth_spec->type); 2535 2536 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN || 2537 ether_type == RTE_ETHER_TYPE_IPV4 || 2538 ether_type == RTE_ETHER_TYPE_IPV6 || 2539 ether_type == i40e_get_outer_vlan(dev)) { 2540 rte_flow_error_set(error, EINVAL, 2541 RTE_FLOW_ERROR_TYPE_ITEM, 2542 item, 2543 "Unsupported ether_type."); 2544 return -rte_errno; 2545 } 2546 input_set |= I40E_INSET_LAST_ETHER_TYPE; 2547 filter->input.flow.l2_flow.ether_type = 2548 eth_spec->type; 2549 } 2550 2551 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD; 2552 layer_idx = I40E_FLXPLD_L2_IDX; 2553 2554 break; 2555 case RTE_FLOW_ITEM_TYPE_VLAN: 2556 vlan_spec = item->spec; 2557 vlan_mask = item->mask; 2558 2559 RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE)); 2560 if (vlan_spec && vlan_mask) { 2561 if (vlan_mask->tci != 2562 rte_cpu_to_be_16(I40E_VLAN_TCI_MASK) && 2563 vlan_mask->tci != 2564 rte_cpu_to_be_16(I40E_VLAN_PRI_MASK) && 2565 vlan_mask->tci != 2566 rte_cpu_to_be_16(I40E_VLAN_CFI_MASK) && 2567 vlan_mask->tci != 2568 rte_cpu_to_be_16(I40E_VLAN_VID_MASK)) { 2569 rte_flow_error_set(error, EINVAL, 2570 RTE_FLOW_ERROR_TYPE_ITEM, 2571 item, 2572 "Unsupported TCI mask."); 2573 } 2574 input_set |= I40E_INSET_VLAN_INNER; 2575 filter->input.flow_ext.vlan_tci = 2576 vlan_spec->tci; 2577 } 2578 if (vlan_spec && vlan_mask && vlan_mask->inner_type) { 2579 if (vlan_mask->inner_type != RTE_BE16(0xffff)) { 2580 rte_flow_error_set(error, EINVAL, 2581 RTE_FLOW_ERROR_TYPE_ITEM, 2582 item, 2583 "Invalid inner_type" 2584 " mask."); 2585 return -rte_errno; 2586 } 2587 2588 ether_type = 2589 rte_be_to_cpu_16(vlan_spec->inner_type); 2590 2591 if (ether_type == RTE_ETHER_TYPE_IPV4 || 2592 ether_type == RTE_ETHER_TYPE_IPV6 || 2593 ether_type == i40e_get_outer_vlan(dev)) { 2594 rte_flow_error_set(error, EINVAL, 2595 RTE_FLOW_ERROR_TYPE_ITEM, 2596 item, 2597 "Unsupported inner_type."); 2598 return -rte_errno; 2599 } 2600 input_set |= I40E_INSET_LAST_ETHER_TYPE; 2601 filter->input.flow.l2_flow.ether_type = 2602 vlan_spec->inner_type; 2603 } 2604 2605 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD; 2606 layer_idx = I40E_FLXPLD_L2_IDX; 2607 2608 break; 2609 case RTE_FLOW_ITEM_TYPE_IPV4: 2610 l3 = RTE_FLOW_ITEM_TYPE_IPV4; 2611 ipv4_spec = item->spec; 2612 ipv4_mask = item->mask; 2613 ipv4_last = item->last; 2614 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 2615 layer_idx = I40E_FLXPLD_L3_IDX; 2616 2617 if (ipv4_last) { 2618 if (!ipv4_spec || !ipv4_mask || !outer_ip) { 2619 rte_flow_error_set(error, EINVAL, 2620 RTE_FLOW_ERROR_TYPE_ITEM, 2621 item, 2622 "Not support range"); 2623 return -rte_errno; 2624 } 2625 /* Only fragment_offset supports range */ 2626 if (ipv4_last->hdr.version_ihl || 2627 ipv4_last->hdr.type_of_service || 2628 ipv4_last->hdr.total_length || 2629 ipv4_last->hdr.packet_id || 2630 ipv4_last->hdr.time_to_live || 2631 ipv4_last->hdr.next_proto_id || 2632 ipv4_last->hdr.hdr_checksum || 2633 ipv4_last->hdr.src_addr || 2634 ipv4_last->hdr.dst_addr) { 2635 rte_flow_error_set(error, EINVAL, 2636 RTE_FLOW_ERROR_TYPE_ITEM, 2637 item, 2638 "Not support range"); 2639 return -rte_errno; 2640 } 2641 } 2642 if (ipv4_spec && ipv4_mask && outer_ip) { 2643 /* Check IPv4 mask and update input set */ 2644 if (ipv4_mask->hdr.version_ihl || 2645 ipv4_mask->hdr.total_length || 2646 ipv4_mask->hdr.packet_id || 2647 ipv4_mask->hdr.hdr_checksum) { 2648 rte_flow_error_set(error, EINVAL, 2649 RTE_FLOW_ERROR_TYPE_ITEM, 2650 item, 2651 "Invalid IPv4 mask."); 2652 return -rte_errno; 2653 } 2654 2655 if (ipv4_mask->hdr.src_addr == UINT32_MAX) 2656 input_set |= I40E_INSET_IPV4_SRC; 2657 if (ipv4_mask->hdr.dst_addr == UINT32_MAX) 2658 input_set |= I40E_INSET_IPV4_DST; 2659 if (ipv4_mask->hdr.type_of_service == UINT8_MAX) 2660 input_set |= I40E_INSET_IPV4_TOS; 2661 if (ipv4_mask->hdr.time_to_live == UINT8_MAX) 2662 input_set |= I40E_INSET_IPV4_TTL; 2663 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX) 2664 input_set |= I40E_INSET_IPV4_PROTO; 2665 2666 /* Check if it is fragment. */ 2667 uint16_t frag_mask = 2668 ipv4_mask->hdr.fragment_offset; 2669 uint16_t frag_spec = 2670 ipv4_spec->hdr.fragment_offset; 2671 uint16_t frag_last = 0; 2672 if (ipv4_last) 2673 frag_last = 2674 ipv4_last->hdr.fragment_offset; 2675 if (frag_mask) { 2676 frag_mask = rte_be_to_cpu_16(frag_mask); 2677 frag_spec = rte_be_to_cpu_16(frag_spec); 2678 frag_last = rte_be_to_cpu_16(frag_last); 2679 /* frag_off mask has to be 0x3fff */ 2680 if (frag_mask != 2681 (RTE_IPV4_HDR_OFFSET_MASK | 2682 RTE_IPV4_HDR_MF_FLAG)) { 2683 rte_flow_error_set(error, 2684 EINVAL, 2685 RTE_FLOW_ERROR_TYPE_ITEM, 2686 item, 2687 "Invalid IPv4 fragment_offset mask"); 2688 return -rte_errno; 2689 } 2690 /* 2691 * non-frag rule: 2692 * mask=0x3fff,spec=0 2693 * frag rule: 2694 * mask=0x3fff,spec=0x8,last=0x2000 2695 */ 2696 if (frag_spec == 2697 (1 << RTE_IPV4_HDR_FO_SHIFT) && 2698 frag_last == RTE_IPV4_HDR_MF_FLAG) { 2699 pctype = 2700 I40E_FILTER_PCTYPE_FRAG_IPV4; 2701 } else if (frag_spec || frag_last) { 2702 rte_flow_error_set(error, 2703 EINVAL, 2704 RTE_FLOW_ERROR_TYPE_ITEM, 2705 item, 2706 "Invalid IPv4 fragment_offset rule"); 2707 return -rte_errno; 2708 } 2709 } else if (frag_spec || frag_last) { 2710 rte_flow_error_set(error, 2711 EINVAL, 2712 RTE_FLOW_ERROR_TYPE_ITEM, 2713 item, 2714 "Invalid fragment_offset"); 2715 return -rte_errno; 2716 } 2717 2718 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) { 2719 if (input_set & (I40E_INSET_IPV4_SRC | 2720 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS | 2721 I40E_INSET_IPV4_TTL | I40E_INSET_IPV4_PROTO)) { 2722 rte_flow_error_set(error, EINVAL, 2723 RTE_FLOW_ERROR_TYPE_ITEM, 2724 item, 2725 "L2 and L3 input set are exclusive."); 2726 return -rte_errno; 2727 } 2728 } else { 2729 /* Get the filter info */ 2730 filter->input.flow.ip4_flow.proto = 2731 ipv4_spec->hdr.next_proto_id; 2732 filter->input.flow.ip4_flow.tos = 2733 ipv4_spec->hdr.type_of_service; 2734 filter->input.flow.ip4_flow.ttl = 2735 ipv4_spec->hdr.time_to_live; 2736 filter->input.flow.ip4_flow.src_ip = 2737 ipv4_spec->hdr.src_addr; 2738 filter->input.flow.ip4_flow.dst_ip = 2739 ipv4_spec->hdr.dst_addr; 2740 2741 filter->input.flow_ext.inner_ip = false; 2742 filter->input.flow_ext.oip_type = 2743 I40E_FDIR_IPTYPE_IPV4; 2744 } 2745 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) { 2746 filter->input.flow_ext.inner_ip = true; 2747 filter->input.flow_ext.iip_type = 2748 I40E_FDIR_IPTYPE_IPV4; 2749 } else if (!ipv4_spec && !ipv4_mask && outer_ip) { 2750 filter->input.flow_ext.inner_ip = false; 2751 filter->input.flow_ext.oip_type = 2752 I40E_FDIR_IPTYPE_IPV4; 2753 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) { 2754 rte_flow_error_set(error, EINVAL, 2755 RTE_FLOW_ERROR_TYPE_ITEM, 2756 item, 2757 "Invalid inner IPv4 mask."); 2758 return -rte_errno; 2759 } 2760 2761 if (outer_ip) 2762 outer_ip = false; 2763 2764 break; 2765 case RTE_FLOW_ITEM_TYPE_IPV6: 2766 l3 = RTE_FLOW_ITEM_TYPE_IPV6; 2767 ipv6_spec = item->spec; 2768 ipv6_mask = item->mask; 2769 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER; 2770 layer_idx = I40E_FLXPLD_L3_IDX; 2771 2772 if (ipv6_spec && ipv6_mask && outer_ip) { 2773 /* Check IPv6 mask and update input set */ 2774 if (ipv6_mask->hdr.payload_len) { 2775 rte_flow_error_set(error, EINVAL, 2776 RTE_FLOW_ERROR_TYPE_ITEM, 2777 item, 2778 "Invalid IPv6 mask"); 2779 return -rte_errno; 2780 } 2781 2782 if (!memcmp(ipv6_mask->hdr.src_addr, 2783 ipv6_addr_mask, 2784 RTE_DIM(ipv6_mask->hdr.src_addr))) 2785 input_set |= I40E_INSET_IPV6_SRC; 2786 if (!memcmp(ipv6_mask->hdr.dst_addr, 2787 ipv6_addr_mask, 2788 RTE_DIM(ipv6_mask->hdr.dst_addr))) 2789 input_set |= I40E_INSET_IPV6_DST; 2790 2791 if ((ipv6_mask->hdr.vtc_flow & 2792 rte_cpu_to_be_32(I40E_IPV6_TC_MASK)) 2793 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK)) 2794 input_set |= I40E_INSET_IPV6_TC; 2795 if (ipv6_mask->hdr.proto == UINT8_MAX) 2796 input_set |= I40E_INSET_IPV6_NEXT_HDR; 2797 if (ipv6_mask->hdr.hop_limits == UINT8_MAX) 2798 input_set |= I40E_INSET_IPV6_HOP_LIMIT; 2799 2800 /* Get filter info */ 2801 vtc_flow_cpu = 2802 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow); 2803 filter->input.flow.ipv6_flow.tc = 2804 (uint8_t)(vtc_flow_cpu >> 2805 I40E_FDIR_IPv6_TC_OFFSET); 2806 filter->input.flow.ipv6_flow.proto = 2807 ipv6_spec->hdr.proto; 2808 filter->input.flow.ipv6_flow.hop_limits = 2809 ipv6_spec->hdr.hop_limits; 2810 2811 filter->input.flow_ext.inner_ip = false; 2812 filter->input.flow_ext.oip_type = 2813 I40E_FDIR_IPTYPE_IPV6; 2814 2815 rte_memcpy(filter->input.flow.ipv6_flow.src_ip, 2816 ipv6_spec->hdr.src_addr, 16); 2817 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip, 2818 ipv6_spec->hdr.dst_addr, 16); 2819 2820 /* Check if it is fragment. */ 2821 if (ipv6_spec->hdr.proto == 2822 I40E_IPV6_FRAG_HEADER) 2823 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6; 2824 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) { 2825 filter->input.flow_ext.inner_ip = true; 2826 filter->input.flow_ext.iip_type = 2827 I40E_FDIR_IPTYPE_IPV6; 2828 } else if (!ipv6_spec && !ipv6_mask && outer_ip) { 2829 filter->input.flow_ext.inner_ip = false; 2830 filter->input.flow_ext.oip_type = 2831 I40E_FDIR_IPTYPE_IPV6; 2832 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) { 2833 rte_flow_error_set(error, EINVAL, 2834 RTE_FLOW_ERROR_TYPE_ITEM, 2835 item, 2836 "Invalid inner IPv6 mask"); 2837 return -rte_errno; 2838 } 2839 2840 if (outer_ip) 2841 outer_ip = false; 2842 break; 2843 case RTE_FLOW_ITEM_TYPE_TCP: 2844 tcp_spec = item->spec; 2845 tcp_mask = item->mask; 2846 2847 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) 2848 pctype = 2849 I40E_FILTER_PCTYPE_NONF_IPV4_TCP; 2850 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) 2851 pctype = 2852 I40E_FILTER_PCTYPE_NONF_IPV6_TCP; 2853 if (tcp_spec && tcp_mask) { 2854 /* Check TCP mask and update input set */ 2855 if (tcp_mask->hdr.sent_seq || 2856 tcp_mask->hdr.recv_ack || 2857 tcp_mask->hdr.data_off || 2858 tcp_mask->hdr.tcp_flags || 2859 tcp_mask->hdr.rx_win || 2860 tcp_mask->hdr.cksum || 2861 tcp_mask->hdr.tcp_urp) { 2862 rte_flow_error_set(error, EINVAL, 2863 RTE_FLOW_ERROR_TYPE_ITEM, 2864 item, 2865 "Invalid TCP mask"); 2866 return -rte_errno; 2867 } 2868 2869 if (tcp_mask->hdr.src_port == UINT16_MAX) 2870 input_set |= I40E_INSET_SRC_PORT; 2871 if (tcp_mask->hdr.dst_port == UINT16_MAX) 2872 input_set |= I40E_INSET_DST_PORT; 2873 2874 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) { 2875 if (input_set & 2876 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) { 2877 rte_flow_error_set(error, EINVAL, 2878 RTE_FLOW_ERROR_TYPE_ITEM, 2879 item, 2880 "L2 and L4 input set are exclusive."); 2881 return -rte_errno; 2882 } 2883 } else { 2884 /* Get filter info */ 2885 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) { 2886 filter->input.flow.tcp4_flow.src_port = 2887 tcp_spec->hdr.src_port; 2888 filter->input.flow.tcp4_flow.dst_port = 2889 tcp_spec->hdr.dst_port; 2890 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) { 2891 filter->input.flow.tcp6_flow.src_port = 2892 tcp_spec->hdr.src_port; 2893 filter->input.flow.tcp6_flow.dst_port = 2894 tcp_spec->hdr.dst_port; 2895 } 2896 } 2897 } 2898 2899 layer_idx = I40E_FLXPLD_L4_IDX; 2900 2901 break; 2902 case RTE_FLOW_ITEM_TYPE_UDP: 2903 udp_spec = item->spec; 2904 udp_mask = item->mask; 2905 2906 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) 2907 pctype = 2908 I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 2909 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) 2910 pctype = 2911 I40E_FILTER_PCTYPE_NONF_IPV6_UDP; 2912 2913 if (udp_spec && udp_mask) { 2914 /* Check UDP mask and update input set*/ 2915 if (udp_mask->hdr.dgram_len || 2916 udp_mask->hdr.dgram_cksum) { 2917 rte_flow_error_set(error, EINVAL, 2918 RTE_FLOW_ERROR_TYPE_ITEM, 2919 item, 2920 "Invalid UDP mask"); 2921 return -rte_errno; 2922 } 2923 2924 if (udp_mask->hdr.src_port == UINT16_MAX) 2925 input_set |= I40E_INSET_SRC_PORT; 2926 if (udp_mask->hdr.dst_port == UINT16_MAX) 2927 input_set |= I40E_INSET_DST_PORT; 2928 2929 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) { 2930 if (input_set & 2931 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) { 2932 rte_flow_error_set(error, EINVAL, 2933 RTE_FLOW_ERROR_TYPE_ITEM, 2934 item, 2935 "L2 and L4 input set are exclusive."); 2936 return -rte_errno; 2937 } 2938 } else { 2939 /* Get filter info */ 2940 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) { 2941 filter->input.flow.udp4_flow.src_port = 2942 udp_spec->hdr.src_port; 2943 filter->input.flow.udp4_flow.dst_port = 2944 udp_spec->hdr.dst_port; 2945 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) { 2946 filter->input.flow.udp6_flow.src_port = 2947 udp_spec->hdr.src_port; 2948 filter->input.flow.udp6_flow.dst_port = 2949 udp_spec->hdr.dst_port; 2950 } 2951 } 2952 } 2953 filter->input.flow_ext.is_udp = true; 2954 layer_idx = I40E_FLXPLD_L4_IDX; 2955 2956 break; 2957 case RTE_FLOW_ITEM_TYPE_GTPC: 2958 case RTE_FLOW_ITEM_TYPE_GTPU: 2959 if (!pf->gtp_support) { 2960 rte_flow_error_set(error, EINVAL, 2961 RTE_FLOW_ERROR_TYPE_ITEM, 2962 item, 2963 "Unsupported protocol"); 2964 return -rte_errno; 2965 } 2966 2967 gtp_spec = item->spec; 2968 gtp_mask = item->mask; 2969 2970 if (gtp_spec && gtp_mask) { 2971 if (gtp_mask->v_pt_rsv_flags || 2972 gtp_mask->msg_type || 2973 gtp_mask->msg_len || 2974 gtp_mask->teid != UINT32_MAX) { 2975 rte_flow_error_set(error, EINVAL, 2976 RTE_FLOW_ERROR_TYPE_ITEM, 2977 item, 2978 "Invalid GTP mask"); 2979 return -rte_errno; 2980 } 2981 2982 filter->input.flow.gtp_flow.teid = 2983 gtp_spec->teid; 2984 filter->input.flow_ext.customized_pctype = true; 2985 cus_proto = item_type; 2986 } 2987 break; 2988 case RTE_FLOW_ITEM_TYPE_ESP: 2989 if (!pf->esp_support) { 2990 rte_flow_error_set(error, EINVAL, 2991 RTE_FLOW_ERROR_TYPE_ITEM, 2992 item, 2993 "Unsupported ESP protocol"); 2994 return -rte_errno; 2995 } 2996 2997 esp_spec = item->spec; 2998 esp_mask = item->mask; 2999 3000 if (!esp_spec || !esp_mask) { 3001 rte_flow_error_set(error, EINVAL, 3002 RTE_FLOW_ERROR_TYPE_ITEM, 3003 item, 3004 "Invalid ESP item"); 3005 return -rte_errno; 3006 } 3007 3008 if (esp_spec && esp_mask) { 3009 if (esp_mask->hdr.spi != UINT32_MAX) { 3010 rte_flow_error_set(error, EINVAL, 3011 RTE_FLOW_ERROR_TYPE_ITEM, 3012 item, 3013 "Invalid ESP mask"); 3014 return -rte_errno; 3015 } 3016 i40e_flow_set_filter_spi(filter, esp_spec); 3017 filter->input.flow_ext.customized_pctype = true; 3018 cus_proto = item_type; 3019 } 3020 break; 3021 case RTE_FLOW_ITEM_TYPE_SCTP: 3022 sctp_spec = item->spec; 3023 sctp_mask = item->mask; 3024 3025 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) 3026 pctype = 3027 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP; 3028 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) 3029 pctype = 3030 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP; 3031 3032 if (sctp_spec && sctp_mask) { 3033 /* Check SCTP mask and update input set */ 3034 if (sctp_mask->hdr.cksum) { 3035 rte_flow_error_set(error, EINVAL, 3036 RTE_FLOW_ERROR_TYPE_ITEM, 3037 item, 3038 "Invalid UDP mask"); 3039 return -rte_errno; 3040 } 3041 3042 if (sctp_mask->hdr.src_port == UINT16_MAX) 3043 input_set |= I40E_INSET_SRC_PORT; 3044 if (sctp_mask->hdr.dst_port == UINT16_MAX) 3045 input_set |= I40E_INSET_DST_PORT; 3046 if (sctp_mask->hdr.tag == UINT32_MAX) 3047 input_set |= I40E_INSET_SCTP_VT; 3048 3049 /* Get filter info */ 3050 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) { 3051 filter->input.flow.sctp4_flow.src_port = 3052 sctp_spec->hdr.src_port; 3053 filter->input.flow.sctp4_flow.dst_port = 3054 sctp_spec->hdr.dst_port; 3055 filter->input.flow.sctp4_flow.verify_tag 3056 = sctp_spec->hdr.tag; 3057 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) { 3058 filter->input.flow.sctp6_flow.src_port = 3059 sctp_spec->hdr.src_port; 3060 filter->input.flow.sctp6_flow.dst_port = 3061 sctp_spec->hdr.dst_port; 3062 filter->input.flow.sctp6_flow.verify_tag 3063 = sctp_spec->hdr.tag; 3064 } 3065 } 3066 3067 layer_idx = I40E_FLXPLD_L4_IDX; 3068 3069 break; 3070 case RTE_FLOW_ITEM_TYPE_RAW: 3071 raw_spec = item->spec; 3072 raw_mask = item->mask; 3073 3074 if (!raw_spec || !raw_mask) { 3075 rte_flow_error_set(error, EINVAL, 3076 RTE_FLOW_ERROR_TYPE_ITEM, 3077 item, 3078 "NULL RAW spec/mask"); 3079 return -rte_errno; 3080 } 3081 3082 if (pf->support_multi_driver) { 3083 rte_flow_error_set(error, ENOTSUP, 3084 RTE_FLOW_ERROR_TYPE_ITEM, 3085 item, 3086 "Unsupported flexible payload."); 3087 return -rte_errno; 3088 } 3089 3090 ret = i40e_flow_check_raw_item(item, raw_spec, error); 3091 if (ret < 0) 3092 return ret; 3093 3094 off_arr[raw_id] = raw_spec->offset; 3095 len_arr[raw_id] = raw_spec->length; 3096 3097 flex_size = 0; 3098 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit)); 3099 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id; 3100 flex_pit.size = 3101 raw_spec->length / sizeof(uint16_t); 3102 flex_pit.dst_offset = 3103 next_dst_off / sizeof(uint16_t); 3104 3105 for (i = 0; i <= raw_id; i++) { 3106 if (i == raw_id) 3107 flex_pit.src_offset += 3108 raw_spec->offset / 3109 sizeof(uint16_t); 3110 else 3111 flex_pit.src_offset += 3112 (off_arr[i] + len_arr[i]) / 3113 sizeof(uint16_t); 3114 flex_size += len_arr[i]; 3115 } 3116 if (((flex_pit.src_offset + flex_pit.size) >= 3117 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) || 3118 flex_size > I40E_FDIR_MAX_FLEXLEN) { 3119 rte_flow_error_set(error, EINVAL, 3120 RTE_FLOW_ERROR_TYPE_ITEM, 3121 item, 3122 "Exceeds maxmial payload limit."); 3123 return -rte_errno; 3124 } 3125 3126 for (i = 0; i < raw_spec->length; i++) { 3127 j = i + next_dst_off; 3128 filter->input.flow_ext.flexbytes[j] = 3129 raw_spec->pattern[i]; 3130 filter->input.flow_ext.flex_mask[j] = 3131 raw_mask->pattern[i]; 3132 } 3133 3134 next_dst_off += raw_spec->length; 3135 raw_id++; 3136 3137 memcpy(&filter->input.flow_ext.flex_pit[field_idx], 3138 &flex_pit, sizeof(struct i40e_fdir_flex_pit)); 3139 filter->input.flow_ext.layer_idx = layer_idx; 3140 filter->input.flow_ext.raw_id = raw_id; 3141 filter->input.flow_ext.is_flex_flow = true; 3142 break; 3143 case RTE_FLOW_ITEM_TYPE_VF: 3144 vf_spec = item->spec; 3145 if (!attr->transfer) { 3146 rte_flow_error_set(error, ENOTSUP, 3147 RTE_FLOW_ERROR_TYPE_ITEM, 3148 item, 3149 "Matching VF traffic" 3150 " without affecting it" 3151 " (transfer attribute)" 3152 " is unsupported"); 3153 return -rte_errno; 3154 } 3155 filter->input.flow_ext.is_vf = 1; 3156 filter->input.flow_ext.dst_id = vf_spec->id; 3157 if (filter->input.flow_ext.is_vf && 3158 filter->input.flow_ext.dst_id >= pf->vf_num) { 3159 rte_flow_error_set(error, EINVAL, 3160 RTE_FLOW_ERROR_TYPE_ITEM, 3161 item, 3162 "Invalid VF ID for FDIR."); 3163 return -rte_errno; 3164 } 3165 break; 3166 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP: 3167 l2tpv3oip_spec = item->spec; 3168 l2tpv3oip_mask = item->mask; 3169 3170 if (!l2tpv3oip_spec || !l2tpv3oip_mask) 3171 break; 3172 3173 if (l2tpv3oip_mask->session_id != UINT32_MAX) { 3174 rte_flow_error_set(error, EINVAL, 3175 RTE_FLOW_ERROR_TYPE_ITEM, 3176 item, 3177 "Invalid L2TPv3 mask"); 3178 return -rte_errno; 3179 } 3180 3181 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) { 3182 filter->input.flow.ip4_l2tpv3oip_flow.session_id = 3183 l2tpv3oip_spec->session_id; 3184 filter->input.flow_ext.oip_type = 3185 I40E_FDIR_IPTYPE_IPV4; 3186 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) { 3187 filter->input.flow.ip6_l2tpv3oip_flow.session_id = 3188 l2tpv3oip_spec->session_id; 3189 filter->input.flow_ext.oip_type = 3190 I40E_FDIR_IPTYPE_IPV6; 3191 } 3192 3193 filter->input.flow_ext.customized_pctype = true; 3194 cus_proto = item_type; 3195 break; 3196 default: 3197 break; 3198 } 3199 } 3200 3201 /* Get customized pctype value */ 3202 if (filter->input.flow_ext.customized_pctype) { 3203 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter); 3204 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 3205 rte_flow_error_set(error, EINVAL, 3206 RTE_FLOW_ERROR_TYPE_ITEM, 3207 item, 3208 "Unsupported pctype"); 3209 return -rte_errno; 3210 } 3211 } 3212 3213 /* If customized pctype is not used, set fdir configuration.*/ 3214 if (!filter->input.flow_ext.customized_pctype) { 3215 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set); 3216 if (ret == -1) { 3217 rte_flow_error_set(error, EINVAL, 3218 RTE_FLOW_ERROR_TYPE_ITEM, item, 3219 "Conflict with the first rule's input set."); 3220 return -rte_errno; 3221 } else if (ret == -EINVAL) { 3222 rte_flow_error_set(error, EINVAL, 3223 RTE_FLOW_ERROR_TYPE_ITEM, item, 3224 "Invalid pattern mask."); 3225 return -rte_errno; 3226 } 3227 } 3228 3229 filter->input.pctype = pctype; 3230 3231 return 0; 3232 } 3233 3234 /* Parse to get the action info of a FDIR filter. 3235 * FDIR action supports QUEUE or (QUEUE + MARK). 3236 */ 3237 static int 3238 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev, 3239 const struct rte_flow_action *actions, 3240 struct rte_flow_error *error, 3241 struct i40e_fdir_filter_conf *filter) 3242 { 3243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3244 const struct rte_flow_action *act; 3245 const struct rte_flow_action_queue *act_q; 3246 const struct rte_flow_action_mark *mark_spec = NULL; 3247 uint32_t index = 0; 3248 3249 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */ 3250 NEXT_ITEM_OF_ACTION(act, actions, index); 3251 switch (act->type) { 3252 case RTE_FLOW_ACTION_TYPE_QUEUE: 3253 act_q = act->conf; 3254 filter->action.rx_queue = act_q->index; 3255 if ((!filter->input.flow_ext.is_vf && 3256 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) || 3257 (filter->input.flow_ext.is_vf && 3258 filter->action.rx_queue >= pf->vf_nb_qps)) { 3259 rte_flow_error_set(error, EINVAL, 3260 RTE_FLOW_ERROR_TYPE_ACTION, act, 3261 "Invalid queue ID for FDIR."); 3262 return -rte_errno; 3263 } 3264 filter->action.behavior = I40E_FDIR_ACCEPT; 3265 break; 3266 case RTE_FLOW_ACTION_TYPE_DROP: 3267 filter->action.behavior = I40E_FDIR_REJECT; 3268 break; 3269 case RTE_FLOW_ACTION_TYPE_PASSTHRU: 3270 filter->action.behavior = I40E_FDIR_PASSTHRU; 3271 break; 3272 case RTE_FLOW_ACTION_TYPE_MARK: 3273 filter->action.behavior = I40E_FDIR_PASSTHRU; 3274 mark_spec = act->conf; 3275 filter->action.report_status = I40E_FDIR_REPORT_ID; 3276 filter->soft_id = mark_spec->id; 3277 break; 3278 default: 3279 rte_flow_error_set(error, EINVAL, 3280 RTE_FLOW_ERROR_TYPE_ACTION, act, 3281 "Invalid action."); 3282 return -rte_errno; 3283 } 3284 3285 /* Check if the next non-void item is MARK or FLAG or END. */ 3286 index++; 3287 NEXT_ITEM_OF_ACTION(act, actions, index); 3288 switch (act->type) { 3289 case RTE_FLOW_ACTION_TYPE_MARK: 3290 if (mark_spec) { 3291 /* Double MARK actions requested */ 3292 rte_flow_error_set(error, EINVAL, 3293 RTE_FLOW_ERROR_TYPE_ACTION, act, 3294 "Invalid action."); 3295 return -rte_errno; 3296 } 3297 mark_spec = act->conf; 3298 filter->action.report_status = I40E_FDIR_REPORT_ID; 3299 filter->soft_id = mark_spec->id; 3300 break; 3301 case RTE_FLOW_ACTION_TYPE_FLAG: 3302 if (mark_spec) { 3303 /* MARK + FLAG not supported */ 3304 rte_flow_error_set(error, EINVAL, 3305 RTE_FLOW_ERROR_TYPE_ACTION, act, 3306 "Invalid action."); 3307 return -rte_errno; 3308 } 3309 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS; 3310 break; 3311 case RTE_FLOW_ACTION_TYPE_RSS: 3312 if (filter->action.behavior != I40E_FDIR_PASSTHRU) { 3313 /* RSS filter won't be next if FDIR did not pass thru */ 3314 rte_flow_error_set(error, EINVAL, 3315 RTE_FLOW_ERROR_TYPE_ACTION, act, 3316 "Invalid action."); 3317 return -rte_errno; 3318 } 3319 break; 3320 case RTE_FLOW_ACTION_TYPE_END: 3321 return 0; 3322 default: 3323 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3324 act, "Invalid action."); 3325 return -rte_errno; 3326 } 3327 3328 /* Check if the next non-void item is END */ 3329 index++; 3330 NEXT_ITEM_OF_ACTION(act, actions, index); 3331 if (act->type != RTE_FLOW_ACTION_TYPE_END) { 3332 rte_flow_error_set(error, EINVAL, 3333 RTE_FLOW_ERROR_TYPE_ACTION, 3334 act, "Invalid action."); 3335 return -rte_errno; 3336 } 3337 3338 return 0; 3339 } 3340 3341 static int 3342 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev, 3343 const struct rte_flow_attr *attr, 3344 const struct rte_flow_item pattern[], 3345 const struct rte_flow_action actions[], 3346 struct rte_flow_error *error, 3347 union i40e_filter_t *filter) 3348 { 3349 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3350 struct i40e_fdir_filter_conf *fdir_filter = 3351 &filter->fdir_filter; 3352 int ret; 3353 3354 ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error, 3355 fdir_filter); 3356 if (ret) 3357 return ret; 3358 3359 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter); 3360 if (ret) 3361 return ret; 3362 3363 ret = i40e_flow_parse_attr(attr, error); 3364 if (ret) 3365 return ret; 3366 3367 cons_filter_type = RTE_ETH_FILTER_FDIR; 3368 3369 if (pf->fdir.fdir_vsi == NULL) { 3370 /* Enable fdir when fdir flow is added at first time. */ 3371 ret = i40e_fdir_setup(pf); 3372 if (ret != I40E_SUCCESS) { 3373 rte_flow_error_set(error, ENOTSUP, 3374 RTE_FLOW_ERROR_TYPE_HANDLE, 3375 NULL, "Failed to setup fdir."); 3376 return -rte_errno; 3377 } 3378 ret = i40e_fdir_configure(dev); 3379 if (ret < 0) { 3380 rte_flow_error_set(error, ENOTSUP, 3381 RTE_FLOW_ERROR_TYPE_HANDLE, 3382 NULL, "Failed to configure fdir."); 3383 goto err; 3384 } 3385 } 3386 3387 /* If create the first fdir rule, enable fdir check for rx queues */ 3388 if (TAILQ_EMPTY(&pf->fdir.fdir_list)) 3389 i40e_fdir_rx_proc_enable(dev, 1); 3390 3391 return 0; 3392 err: 3393 i40e_fdir_teardown(pf); 3394 return -rte_errno; 3395 } 3396 3397 /* Parse to get the action info of a tunnel filter 3398 * Tunnel action only supports PF, VF and QUEUE. 3399 */ 3400 static int 3401 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev, 3402 const struct rte_flow_action *actions, 3403 struct rte_flow_error *error, 3404 struct i40e_tunnel_filter_conf *filter) 3405 { 3406 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3407 const struct rte_flow_action *act; 3408 const struct rte_flow_action_queue *act_q; 3409 const struct rte_flow_action_vf *act_vf; 3410 uint32_t index = 0; 3411 3412 /* Check if the first non-void action is PF or VF. */ 3413 NEXT_ITEM_OF_ACTION(act, actions, index); 3414 if (act->type != RTE_FLOW_ACTION_TYPE_PF && 3415 act->type != RTE_FLOW_ACTION_TYPE_VF) { 3416 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3417 act, "Not supported action."); 3418 return -rte_errno; 3419 } 3420 3421 if (act->type == RTE_FLOW_ACTION_TYPE_VF) { 3422 act_vf = act->conf; 3423 filter->vf_id = act_vf->id; 3424 filter->is_to_vf = 1; 3425 if (filter->vf_id >= pf->vf_num) { 3426 rte_flow_error_set(error, EINVAL, 3427 RTE_FLOW_ERROR_TYPE_ACTION, 3428 act, "Invalid VF ID for tunnel filter"); 3429 return -rte_errno; 3430 } 3431 } 3432 3433 /* Check if the next non-void item is QUEUE */ 3434 index++; 3435 NEXT_ITEM_OF_ACTION(act, actions, index); 3436 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 3437 act_q = act->conf; 3438 filter->queue_id = act_q->index; 3439 if ((!filter->is_to_vf) && 3440 (filter->queue_id >= pf->dev_data->nb_rx_queues)) { 3441 rte_flow_error_set(error, EINVAL, 3442 RTE_FLOW_ERROR_TYPE_ACTION, 3443 act, "Invalid queue ID for tunnel filter"); 3444 return -rte_errno; 3445 } else if (filter->is_to_vf && 3446 (filter->queue_id >= pf->vf_nb_qps)) { 3447 rte_flow_error_set(error, EINVAL, 3448 RTE_FLOW_ERROR_TYPE_ACTION, 3449 act, "Invalid queue ID for tunnel filter"); 3450 return -rte_errno; 3451 } 3452 } 3453 3454 /* Check if the next non-void item is END */ 3455 index++; 3456 NEXT_ITEM_OF_ACTION(act, actions, index); 3457 if (act->type != RTE_FLOW_ACTION_TYPE_END) { 3458 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3459 act, "Not supported action."); 3460 return -rte_errno; 3461 } 3462 3463 return 0; 3464 } 3465 3466 /* 1. Last in item should be NULL as range is not supported. 3467 * 2. Supported filter types: Source port only and Destination port only. 3468 * 3. Mask of fields which need to be matched should be 3469 * filled with 1. 3470 * 4. Mask of fields which needn't to be matched should be 3471 * filled with 0. 3472 */ 3473 static int 3474 i40e_flow_parse_l4_pattern(const struct rte_flow_item *pattern, 3475 struct rte_flow_error *error, 3476 struct i40e_tunnel_filter_conf *filter) 3477 { 3478 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask; 3479 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask; 3480 const struct rte_flow_item_udp *udp_spec, *udp_mask; 3481 const struct rte_flow_item *item = pattern; 3482 enum rte_flow_item_type item_type; 3483 3484 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3485 if (item->last) { 3486 rte_flow_error_set(error, EINVAL, 3487 RTE_FLOW_ERROR_TYPE_ITEM, 3488 item, 3489 "Not support range"); 3490 return -rte_errno; 3491 } 3492 item_type = item->type; 3493 switch (item_type) { 3494 case RTE_FLOW_ITEM_TYPE_ETH: 3495 if (item->spec || item->mask) { 3496 rte_flow_error_set(error, EINVAL, 3497 RTE_FLOW_ERROR_TYPE_ITEM, 3498 item, 3499 "Invalid ETH item"); 3500 return -rte_errno; 3501 } 3502 3503 break; 3504 case RTE_FLOW_ITEM_TYPE_IPV4: 3505 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 3506 /* IPv4 is used to describe protocol, 3507 * spec and mask should be NULL. 3508 */ 3509 if (item->spec || item->mask) { 3510 rte_flow_error_set(error, EINVAL, 3511 RTE_FLOW_ERROR_TYPE_ITEM, 3512 item, 3513 "Invalid IPv4 item"); 3514 return -rte_errno; 3515 } 3516 3517 break; 3518 case RTE_FLOW_ITEM_TYPE_IPV6: 3519 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6; 3520 /* IPv6 is used to describe protocol, 3521 * spec and mask should be NULL. 3522 */ 3523 if (item->spec || item->mask) { 3524 rte_flow_error_set(error, EINVAL, 3525 RTE_FLOW_ERROR_TYPE_ITEM, 3526 item, 3527 "Invalid IPv6 item"); 3528 return -rte_errno; 3529 } 3530 3531 break; 3532 case RTE_FLOW_ITEM_TYPE_UDP: 3533 udp_spec = item->spec; 3534 udp_mask = item->mask; 3535 3536 if (!udp_spec || !udp_mask) { 3537 rte_flow_error_set(error, EINVAL, 3538 RTE_FLOW_ERROR_TYPE_ITEM, 3539 item, 3540 "Invalid udp item"); 3541 return -rte_errno; 3542 } 3543 3544 if (udp_spec->hdr.src_port != 0 && 3545 udp_spec->hdr.dst_port != 0) { 3546 rte_flow_error_set(error, EINVAL, 3547 RTE_FLOW_ERROR_TYPE_ITEM, 3548 item, 3549 "Invalid udp spec"); 3550 return -rte_errno; 3551 } 3552 3553 if (udp_spec->hdr.src_port != 0) { 3554 filter->l4_port_type = 3555 I40E_L4_PORT_TYPE_SRC; 3556 filter->tenant_id = 3557 rte_be_to_cpu_32(udp_spec->hdr.src_port); 3558 } 3559 3560 if (udp_spec->hdr.dst_port != 0) { 3561 filter->l4_port_type = 3562 I40E_L4_PORT_TYPE_DST; 3563 filter->tenant_id = 3564 rte_be_to_cpu_32(udp_spec->hdr.dst_port); 3565 } 3566 3567 filter->tunnel_type = I40E_CLOUD_TYPE_UDP; 3568 3569 break; 3570 case RTE_FLOW_ITEM_TYPE_TCP: 3571 tcp_spec = item->spec; 3572 tcp_mask = item->mask; 3573 3574 if (!tcp_spec || !tcp_mask) { 3575 rte_flow_error_set(error, EINVAL, 3576 RTE_FLOW_ERROR_TYPE_ITEM, 3577 item, 3578 "Invalid tcp item"); 3579 return -rte_errno; 3580 } 3581 3582 if (tcp_spec->hdr.src_port != 0 && 3583 tcp_spec->hdr.dst_port != 0) { 3584 rte_flow_error_set(error, EINVAL, 3585 RTE_FLOW_ERROR_TYPE_ITEM, 3586 item, 3587 "Invalid tcp spec"); 3588 return -rte_errno; 3589 } 3590 3591 if (tcp_spec->hdr.src_port != 0) { 3592 filter->l4_port_type = 3593 I40E_L4_PORT_TYPE_SRC; 3594 filter->tenant_id = 3595 rte_be_to_cpu_32(tcp_spec->hdr.src_port); 3596 } 3597 3598 if (tcp_spec->hdr.dst_port != 0) { 3599 filter->l4_port_type = 3600 I40E_L4_PORT_TYPE_DST; 3601 filter->tenant_id = 3602 rte_be_to_cpu_32(tcp_spec->hdr.dst_port); 3603 } 3604 3605 filter->tunnel_type = I40E_CLOUD_TYPE_TCP; 3606 3607 break; 3608 case RTE_FLOW_ITEM_TYPE_SCTP: 3609 sctp_spec = item->spec; 3610 sctp_mask = item->mask; 3611 3612 if (!sctp_spec || !sctp_mask) { 3613 rte_flow_error_set(error, EINVAL, 3614 RTE_FLOW_ERROR_TYPE_ITEM, 3615 item, 3616 "Invalid sctp item"); 3617 return -rte_errno; 3618 } 3619 3620 if (sctp_spec->hdr.src_port != 0 && 3621 sctp_spec->hdr.dst_port != 0) { 3622 rte_flow_error_set(error, EINVAL, 3623 RTE_FLOW_ERROR_TYPE_ITEM, 3624 item, 3625 "Invalid sctp spec"); 3626 return -rte_errno; 3627 } 3628 3629 if (sctp_spec->hdr.src_port != 0) { 3630 filter->l4_port_type = 3631 I40E_L4_PORT_TYPE_SRC; 3632 filter->tenant_id = 3633 rte_be_to_cpu_32(sctp_spec->hdr.src_port); 3634 } 3635 3636 if (sctp_spec->hdr.dst_port != 0) { 3637 filter->l4_port_type = 3638 I40E_L4_PORT_TYPE_DST; 3639 filter->tenant_id = 3640 rte_be_to_cpu_32(sctp_spec->hdr.dst_port); 3641 } 3642 3643 filter->tunnel_type = I40E_CLOUD_TYPE_SCTP; 3644 3645 break; 3646 default: 3647 break; 3648 } 3649 } 3650 3651 return 0; 3652 } 3653 3654 static int 3655 i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev, 3656 const struct rte_flow_attr *attr, 3657 const struct rte_flow_item pattern[], 3658 const struct rte_flow_action actions[], 3659 struct rte_flow_error *error, 3660 union i40e_filter_t *filter) 3661 { 3662 struct i40e_tunnel_filter_conf *tunnel_filter = 3663 &filter->consistent_tunnel_filter; 3664 int ret; 3665 3666 ret = i40e_flow_parse_l4_pattern(pattern, error, tunnel_filter); 3667 if (ret) 3668 return ret; 3669 3670 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 3671 if (ret) 3672 return ret; 3673 3674 ret = i40e_flow_parse_attr(attr, error); 3675 if (ret) 3676 return ret; 3677 3678 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 3679 3680 return ret; 3681 } 3682 3683 static uint16_t i40e_supported_tunnel_filter_types[] = { 3684 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID | 3685 ETH_TUNNEL_FILTER_IVLAN, 3686 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 3687 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID, 3688 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID | 3689 ETH_TUNNEL_FILTER_IMAC, 3690 ETH_TUNNEL_FILTER_IMAC, 3691 }; 3692 3693 static int 3694 i40e_check_tunnel_filter_type(uint8_t filter_type) 3695 { 3696 uint8_t i; 3697 3698 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) { 3699 if (filter_type == i40e_supported_tunnel_filter_types[i]) 3700 return 0; 3701 } 3702 3703 return -1; 3704 } 3705 3706 /* 1. Last in item should be NULL as range is not supported. 3707 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN, 3708 * IMAC_TENID, OMAC_TENID_IMAC and IMAC. 3709 * 3. Mask of fields which need to be matched should be 3710 * filled with 1. 3711 * 4. Mask of fields which needn't to be matched should be 3712 * filled with 0. 3713 */ 3714 static int 3715 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev, 3716 const struct rte_flow_item *pattern, 3717 struct rte_flow_error *error, 3718 struct i40e_tunnel_filter_conf *filter) 3719 { 3720 const struct rte_flow_item *item = pattern; 3721 const struct rte_flow_item_eth *eth_spec; 3722 const struct rte_flow_item_eth *eth_mask; 3723 const struct rte_flow_item_vxlan *vxlan_spec; 3724 const struct rte_flow_item_vxlan *vxlan_mask; 3725 const struct rte_flow_item_vlan *vlan_spec; 3726 const struct rte_flow_item_vlan *vlan_mask; 3727 uint8_t filter_type = 0; 3728 bool is_vni_masked = 0; 3729 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF}; 3730 enum rte_flow_item_type item_type; 3731 bool vxlan_flag = 0; 3732 uint32_t tenant_id_be = 0; 3733 int ret; 3734 3735 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3736 if (item->last) { 3737 rte_flow_error_set(error, EINVAL, 3738 RTE_FLOW_ERROR_TYPE_ITEM, 3739 item, 3740 "Not support range"); 3741 return -rte_errno; 3742 } 3743 item_type = item->type; 3744 switch (item_type) { 3745 case RTE_FLOW_ITEM_TYPE_ETH: 3746 eth_spec = item->spec; 3747 eth_mask = item->mask; 3748 3749 /* Check if ETH item is used for place holder. 3750 * If yes, both spec and mask should be NULL. 3751 * If no, both spec and mask shouldn't be NULL. 3752 */ 3753 if ((!eth_spec && eth_mask) || 3754 (eth_spec && !eth_mask)) { 3755 rte_flow_error_set(error, EINVAL, 3756 RTE_FLOW_ERROR_TYPE_ITEM, 3757 item, 3758 "Invalid ether spec/mask"); 3759 return -rte_errno; 3760 } 3761 3762 if (eth_spec && eth_mask) { 3763 /* DST address of inner MAC shouldn't be masked. 3764 * SRC address of Inner MAC should be masked. 3765 */ 3766 if (!rte_is_broadcast_ether_addr(ð_mask->dst) || 3767 !rte_is_zero_ether_addr(ð_mask->src) || 3768 eth_mask->type) { 3769 rte_flow_error_set(error, EINVAL, 3770 RTE_FLOW_ERROR_TYPE_ITEM, 3771 item, 3772 "Invalid ether spec/mask"); 3773 return -rte_errno; 3774 } 3775 3776 if (!vxlan_flag) { 3777 rte_memcpy(&filter->outer_mac, 3778 ð_spec->dst, 3779 RTE_ETHER_ADDR_LEN); 3780 filter_type |= ETH_TUNNEL_FILTER_OMAC; 3781 } else { 3782 rte_memcpy(&filter->inner_mac, 3783 ð_spec->dst, 3784 RTE_ETHER_ADDR_LEN); 3785 filter_type |= ETH_TUNNEL_FILTER_IMAC; 3786 } 3787 } 3788 break; 3789 case RTE_FLOW_ITEM_TYPE_VLAN: 3790 vlan_spec = item->spec; 3791 vlan_mask = item->mask; 3792 if (!(vlan_spec && vlan_mask) || 3793 vlan_mask->inner_type) { 3794 rte_flow_error_set(error, EINVAL, 3795 RTE_FLOW_ERROR_TYPE_ITEM, 3796 item, 3797 "Invalid vlan item"); 3798 return -rte_errno; 3799 } 3800 3801 if (vlan_spec && vlan_mask) { 3802 if (vlan_mask->tci == 3803 rte_cpu_to_be_16(I40E_VLAN_TCI_MASK)) 3804 filter->inner_vlan = 3805 rte_be_to_cpu_16(vlan_spec->tci) & 3806 I40E_VLAN_TCI_MASK; 3807 filter_type |= ETH_TUNNEL_FILTER_IVLAN; 3808 } 3809 break; 3810 case RTE_FLOW_ITEM_TYPE_IPV4: 3811 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 3812 /* IPv4 is used to describe protocol, 3813 * spec and mask should be NULL. 3814 */ 3815 if (item->spec || item->mask) { 3816 rte_flow_error_set(error, EINVAL, 3817 RTE_FLOW_ERROR_TYPE_ITEM, 3818 item, 3819 "Invalid IPv4 item"); 3820 return -rte_errno; 3821 } 3822 break; 3823 case RTE_FLOW_ITEM_TYPE_IPV6: 3824 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6; 3825 /* IPv6 is used to describe protocol, 3826 * spec and mask should be NULL. 3827 */ 3828 if (item->spec || item->mask) { 3829 rte_flow_error_set(error, EINVAL, 3830 RTE_FLOW_ERROR_TYPE_ITEM, 3831 item, 3832 "Invalid IPv6 item"); 3833 return -rte_errno; 3834 } 3835 break; 3836 case RTE_FLOW_ITEM_TYPE_UDP: 3837 /* UDP is used to describe protocol, 3838 * spec and mask should be NULL. 3839 */ 3840 if (item->spec || item->mask) { 3841 rte_flow_error_set(error, EINVAL, 3842 RTE_FLOW_ERROR_TYPE_ITEM, 3843 item, 3844 "Invalid UDP item"); 3845 return -rte_errno; 3846 } 3847 break; 3848 case RTE_FLOW_ITEM_TYPE_VXLAN: 3849 vxlan_spec = item->spec; 3850 vxlan_mask = item->mask; 3851 /* Check if VXLAN item is used to describe protocol. 3852 * If yes, both spec and mask should be NULL. 3853 * If no, both spec and mask shouldn't be NULL. 3854 */ 3855 if ((!vxlan_spec && vxlan_mask) || 3856 (vxlan_spec && !vxlan_mask)) { 3857 rte_flow_error_set(error, EINVAL, 3858 RTE_FLOW_ERROR_TYPE_ITEM, 3859 item, 3860 "Invalid VXLAN item"); 3861 return -rte_errno; 3862 } 3863 3864 /* Check if VNI is masked. */ 3865 if (vxlan_spec && vxlan_mask) { 3866 is_vni_masked = 3867 !!memcmp(vxlan_mask->vni, vni_mask, 3868 RTE_DIM(vni_mask)); 3869 if (is_vni_masked) { 3870 rte_flow_error_set(error, EINVAL, 3871 RTE_FLOW_ERROR_TYPE_ITEM, 3872 item, 3873 "Invalid VNI mask"); 3874 return -rte_errno; 3875 } 3876 3877 rte_memcpy(((uint8_t *)&tenant_id_be + 1), 3878 vxlan_spec->vni, 3); 3879 filter->tenant_id = 3880 rte_be_to_cpu_32(tenant_id_be); 3881 filter_type |= ETH_TUNNEL_FILTER_TENID; 3882 } 3883 3884 vxlan_flag = 1; 3885 break; 3886 default: 3887 break; 3888 } 3889 } 3890 3891 ret = i40e_check_tunnel_filter_type(filter_type); 3892 if (ret < 0) { 3893 rte_flow_error_set(error, EINVAL, 3894 RTE_FLOW_ERROR_TYPE_ITEM, 3895 NULL, 3896 "Invalid filter type"); 3897 return -rte_errno; 3898 } 3899 filter->filter_type = filter_type; 3900 3901 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN; 3902 3903 return 0; 3904 } 3905 3906 static int 3907 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev, 3908 const struct rte_flow_attr *attr, 3909 const struct rte_flow_item pattern[], 3910 const struct rte_flow_action actions[], 3911 struct rte_flow_error *error, 3912 union i40e_filter_t *filter) 3913 { 3914 struct i40e_tunnel_filter_conf *tunnel_filter = 3915 &filter->consistent_tunnel_filter; 3916 int ret; 3917 3918 ret = i40e_flow_parse_vxlan_pattern(dev, pattern, 3919 error, tunnel_filter); 3920 if (ret) 3921 return ret; 3922 3923 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 3924 if (ret) 3925 return ret; 3926 3927 ret = i40e_flow_parse_attr(attr, error); 3928 if (ret) 3929 return ret; 3930 3931 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 3932 3933 return ret; 3934 } 3935 3936 /* 1. Last in item should be NULL as range is not supported. 3937 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN, 3938 * IMAC_TENID, OMAC_TENID_IMAC and IMAC. 3939 * 3. Mask of fields which need to be matched should be 3940 * filled with 1. 3941 * 4. Mask of fields which needn't to be matched should be 3942 * filled with 0. 3943 */ 3944 static int 3945 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev, 3946 const struct rte_flow_item *pattern, 3947 struct rte_flow_error *error, 3948 struct i40e_tunnel_filter_conf *filter) 3949 { 3950 const struct rte_flow_item *item = pattern; 3951 const struct rte_flow_item_eth *eth_spec; 3952 const struct rte_flow_item_eth *eth_mask; 3953 const struct rte_flow_item_nvgre *nvgre_spec; 3954 const struct rte_flow_item_nvgre *nvgre_mask; 3955 const struct rte_flow_item_vlan *vlan_spec; 3956 const struct rte_flow_item_vlan *vlan_mask; 3957 enum rte_flow_item_type item_type; 3958 uint8_t filter_type = 0; 3959 bool is_tni_masked = 0; 3960 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF}; 3961 bool nvgre_flag = 0; 3962 uint32_t tenant_id_be = 0; 3963 int ret; 3964 3965 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3966 if (item->last) { 3967 rte_flow_error_set(error, EINVAL, 3968 RTE_FLOW_ERROR_TYPE_ITEM, 3969 item, 3970 "Not support range"); 3971 return -rte_errno; 3972 } 3973 item_type = item->type; 3974 switch (item_type) { 3975 case RTE_FLOW_ITEM_TYPE_ETH: 3976 eth_spec = item->spec; 3977 eth_mask = item->mask; 3978 3979 /* Check if ETH item is used for place holder. 3980 * If yes, both spec and mask should be NULL. 3981 * If no, both spec and mask shouldn't be NULL. 3982 */ 3983 if ((!eth_spec && eth_mask) || 3984 (eth_spec && !eth_mask)) { 3985 rte_flow_error_set(error, EINVAL, 3986 RTE_FLOW_ERROR_TYPE_ITEM, 3987 item, 3988 "Invalid ether spec/mask"); 3989 return -rte_errno; 3990 } 3991 3992 if (eth_spec && eth_mask) { 3993 /* DST address of inner MAC shouldn't be masked. 3994 * SRC address of Inner MAC should be masked. 3995 */ 3996 if (!rte_is_broadcast_ether_addr(ð_mask->dst) || 3997 !rte_is_zero_ether_addr(ð_mask->src) || 3998 eth_mask->type) { 3999 rte_flow_error_set(error, EINVAL, 4000 RTE_FLOW_ERROR_TYPE_ITEM, 4001 item, 4002 "Invalid ether spec/mask"); 4003 return -rte_errno; 4004 } 4005 4006 if (!nvgre_flag) { 4007 rte_memcpy(&filter->outer_mac, 4008 ð_spec->dst, 4009 RTE_ETHER_ADDR_LEN); 4010 filter_type |= ETH_TUNNEL_FILTER_OMAC; 4011 } else { 4012 rte_memcpy(&filter->inner_mac, 4013 ð_spec->dst, 4014 RTE_ETHER_ADDR_LEN); 4015 filter_type |= ETH_TUNNEL_FILTER_IMAC; 4016 } 4017 } 4018 4019 break; 4020 case RTE_FLOW_ITEM_TYPE_VLAN: 4021 vlan_spec = item->spec; 4022 vlan_mask = item->mask; 4023 if (!(vlan_spec && vlan_mask) || 4024 vlan_mask->inner_type) { 4025 rte_flow_error_set(error, EINVAL, 4026 RTE_FLOW_ERROR_TYPE_ITEM, 4027 item, 4028 "Invalid vlan item"); 4029 return -rte_errno; 4030 } 4031 4032 if (vlan_spec && vlan_mask) { 4033 if (vlan_mask->tci == 4034 rte_cpu_to_be_16(I40E_VLAN_TCI_MASK)) 4035 filter->inner_vlan = 4036 rte_be_to_cpu_16(vlan_spec->tci) & 4037 I40E_VLAN_TCI_MASK; 4038 filter_type |= ETH_TUNNEL_FILTER_IVLAN; 4039 } 4040 break; 4041 case RTE_FLOW_ITEM_TYPE_IPV4: 4042 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 4043 /* IPv4 is used to describe protocol, 4044 * spec and mask should be NULL. 4045 */ 4046 if (item->spec || item->mask) { 4047 rte_flow_error_set(error, EINVAL, 4048 RTE_FLOW_ERROR_TYPE_ITEM, 4049 item, 4050 "Invalid IPv4 item"); 4051 return -rte_errno; 4052 } 4053 break; 4054 case RTE_FLOW_ITEM_TYPE_IPV6: 4055 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6; 4056 /* IPv6 is used to describe protocol, 4057 * spec and mask should be NULL. 4058 */ 4059 if (item->spec || item->mask) { 4060 rte_flow_error_set(error, EINVAL, 4061 RTE_FLOW_ERROR_TYPE_ITEM, 4062 item, 4063 "Invalid IPv6 item"); 4064 return -rte_errno; 4065 } 4066 break; 4067 case RTE_FLOW_ITEM_TYPE_NVGRE: 4068 nvgre_spec = item->spec; 4069 nvgre_mask = item->mask; 4070 /* Check if NVGRE item is used to describe protocol. 4071 * If yes, both spec and mask should be NULL. 4072 * If no, both spec and mask shouldn't be NULL. 4073 */ 4074 if ((!nvgre_spec && nvgre_mask) || 4075 (nvgre_spec && !nvgre_mask)) { 4076 rte_flow_error_set(error, EINVAL, 4077 RTE_FLOW_ERROR_TYPE_ITEM, 4078 item, 4079 "Invalid NVGRE item"); 4080 return -rte_errno; 4081 } 4082 4083 if (nvgre_spec && nvgre_mask) { 4084 is_tni_masked = 4085 !!memcmp(nvgre_mask->tni, tni_mask, 4086 RTE_DIM(tni_mask)); 4087 if (is_tni_masked) { 4088 rte_flow_error_set(error, EINVAL, 4089 RTE_FLOW_ERROR_TYPE_ITEM, 4090 item, 4091 "Invalid TNI mask"); 4092 return -rte_errno; 4093 } 4094 if (nvgre_mask->protocol && 4095 nvgre_mask->protocol != 0xFFFF) { 4096 rte_flow_error_set(error, EINVAL, 4097 RTE_FLOW_ERROR_TYPE_ITEM, 4098 item, 4099 "Invalid NVGRE item"); 4100 return -rte_errno; 4101 } 4102 if (nvgre_mask->c_k_s_rsvd0_ver && 4103 nvgre_mask->c_k_s_rsvd0_ver != 4104 rte_cpu_to_be_16(0xFFFF)) { 4105 rte_flow_error_set(error, EINVAL, 4106 RTE_FLOW_ERROR_TYPE_ITEM, 4107 item, 4108 "Invalid NVGRE item"); 4109 return -rte_errno; 4110 } 4111 if (nvgre_spec->c_k_s_rsvd0_ver != 4112 rte_cpu_to_be_16(0x2000) && 4113 nvgre_mask->c_k_s_rsvd0_ver) { 4114 rte_flow_error_set(error, EINVAL, 4115 RTE_FLOW_ERROR_TYPE_ITEM, 4116 item, 4117 "Invalid NVGRE item"); 4118 return -rte_errno; 4119 } 4120 if (nvgre_mask->protocol && 4121 nvgre_spec->protocol != 4122 rte_cpu_to_be_16(0x6558)) { 4123 rte_flow_error_set(error, EINVAL, 4124 RTE_FLOW_ERROR_TYPE_ITEM, 4125 item, 4126 "Invalid NVGRE item"); 4127 return -rte_errno; 4128 } 4129 rte_memcpy(((uint8_t *)&tenant_id_be + 1), 4130 nvgre_spec->tni, 3); 4131 filter->tenant_id = 4132 rte_be_to_cpu_32(tenant_id_be); 4133 filter_type |= ETH_TUNNEL_FILTER_TENID; 4134 } 4135 4136 nvgre_flag = 1; 4137 break; 4138 default: 4139 break; 4140 } 4141 } 4142 4143 ret = i40e_check_tunnel_filter_type(filter_type); 4144 if (ret < 0) { 4145 rte_flow_error_set(error, EINVAL, 4146 RTE_FLOW_ERROR_TYPE_ITEM, 4147 NULL, 4148 "Invalid filter type"); 4149 return -rte_errno; 4150 } 4151 filter->filter_type = filter_type; 4152 4153 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE; 4154 4155 return 0; 4156 } 4157 4158 static int 4159 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev, 4160 const struct rte_flow_attr *attr, 4161 const struct rte_flow_item pattern[], 4162 const struct rte_flow_action actions[], 4163 struct rte_flow_error *error, 4164 union i40e_filter_t *filter) 4165 { 4166 struct i40e_tunnel_filter_conf *tunnel_filter = 4167 &filter->consistent_tunnel_filter; 4168 int ret; 4169 4170 ret = i40e_flow_parse_nvgre_pattern(dev, pattern, 4171 error, tunnel_filter); 4172 if (ret) 4173 return ret; 4174 4175 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 4176 if (ret) 4177 return ret; 4178 4179 ret = i40e_flow_parse_attr(attr, error); 4180 if (ret) 4181 return ret; 4182 4183 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 4184 4185 return ret; 4186 } 4187 4188 /* 1. Last in item should be NULL as range is not supported. 4189 * 2. Supported filter types: MPLS label. 4190 * 3. Mask of fields which need to be matched should be 4191 * filled with 1. 4192 * 4. Mask of fields which needn't to be matched should be 4193 * filled with 0. 4194 */ 4195 static int 4196 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev, 4197 const struct rte_flow_item *pattern, 4198 struct rte_flow_error *error, 4199 struct i40e_tunnel_filter_conf *filter) 4200 { 4201 const struct rte_flow_item *item = pattern; 4202 const struct rte_flow_item_mpls *mpls_spec; 4203 const struct rte_flow_item_mpls *mpls_mask; 4204 enum rte_flow_item_type item_type; 4205 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */ 4206 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0}; 4207 uint32_t label_be = 0; 4208 4209 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 4210 if (item->last) { 4211 rte_flow_error_set(error, EINVAL, 4212 RTE_FLOW_ERROR_TYPE_ITEM, 4213 item, 4214 "Not support range"); 4215 return -rte_errno; 4216 } 4217 item_type = item->type; 4218 switch (item_type) { 4219 case RTE_FLOW_ITEM_TYPE_ETH: 4220 if (item->spec || item->mask) { 4221 rte_flow_error_set(error, EINVAL, 4222 RTE_FLOW_ERROR_TYPE_ITEM, 4223 item, 4224 "Invalid ETH item"); 4225 return -rte_errno; 4226 } 4227 break; 4228 case RTE_FLOW_ITEM_TYPE_IPV4: 4229 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 4230 /* IPv4 is used to describe protocol, 4231 * spec and mask should be NULL. 4232 */ 4233 if (item->spec || item->mask) { 4234 rte_flow_error_set(error, EINVAL, 4235 RTE_FLOW_ERROR_TYPE_ITEM, 4236 item, 4237 "Invalid IPv4 item"); 4238 return -rte_errno; 4239 } 4240 break; 4241 case RTE_FLOW_ITEM_TYPE_IPV6: 4242 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6; 4243 /* IPv6 is used to describe protocol, 4244 * spec and mask should be NULL. 4245 */ 4246 if (item->spec || item->mask) { 4247 rte_flow_error_set(error, EINVAL, 4248 RTE_FLOW_ERROR_TYPE_ITEM, 4249 item, 4250 "Invalid IPv6 item"); 4251 return -rte_errno; 4252 } 4253 break; 4254 case RTE_FLOW_ITEM_TYPE_UDP: 4255 /* UDP is used to describe protocol, 4256 * spec and mask should be NULL. 4257 */ 4258 if (item->spec || item->mask) { 4259 rte_flow_error_set(error, EINVAL, 4260 RTE_FLOW_ERROR_TYPE_ITEM, 4261 item, 4262 "Invalid UDP item"); 4263 return -rte_errno; 4264 } 4265 is_mplsoudp = 1; 4266 break; 4267 case RTE_FLOW_ITEM_TYPE_GRE: 4268 /* GRE is used to describe protocol, 4269 * spec and mask should be NULL. 4270 */ 4271 if (item->spec || item->mask) { 4272 rte_flow_error_set(error, EINVAL, 4273 RTE_FLOW_ERROR_TYPE_ITEM, 4274 item, 4275 "Invalid GRE item"); 4276 return -rte_errno; 4277 } 4278 break; 4279 case RTE_FLOW_ITEM_TYPE_MPLS: 4280 mpls_spec = item->spec; 4281 mpls_mask = item->mask; 4282 4283 if (!mpls_spec || !mpls_mask) { 4284 rte_flow_error_set(error, EINVAL, 4285 RTE_FLOW_ERROR_TYPE_ITEM, 4286 item, 4287 "Invalid MPLS item"); 4288 return -rte_errno; 4289 } 4290 4291 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) { 4292 rte_flow_error_set(error, EINVAL, 4293 RTE_FLOW_ERROR_TYPE_ITEM, 4294 item, 4295 "Invalid MPLS label mask"); 4296 return -rte_errno; 4297 } 4298 rte_memcpy(((uint8_t *)&label_be + 1), 4299 mpls_spec->label_tc_s, 3); 4300 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4; 4301 break; 4302 default: 4303 break; 4304 } 4305 } 4306 4307 if (is_mplsoudp) 4308 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP; 4309 else 4310 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE; 4311 4312 return 0; 4313 } 4314 4315 static int 4316 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev, 4317 const struct rte_flow_attr *attr, 4318 const struct rte_flow_item pattern[], 4319 const struct rte_flow_action actions[], 4320 struct rte_flow_error *error, 4321 union i40e_filter_t *filter) 4322 { 4323 struct i40e_tunnel_filter_conf *tunnel_filter = 4324 &filter->consistent_tunnel_filter; 4325 int ret; 4326 4327 ret = i40e_flow_parse_mpls_pattern(dev, pattern, 4328 error, tunnel_filter); 4329 if (ret) 4330 return ret; 4331 4332 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 4333 if (ret) 4334 return ret; 4335 4336 ret = i40e_flow_parse_attr(attr, error); 4337 if (ret) 4338 return ret; 4339 4340 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 4341 4342 return ret; 4343 } 4344 4345 /* 1. Last in item should be NULL as range is not supported. 4346 * 2. Supported filter types: GTP TEID. 4347 * 3. Mask of fields which need to be matched should be 4348 * filled with 1. 4349 * 4. Mask of fields which needn't to be matched should be 4350 * filled with 0. 4351 * 5. GTP profile supports GTPv1 only. 4352 * 6. GTP-C response message ('source_port' = 2123) is not supported. 4353 */ 4354 static int 4355 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev, 4356 const struct rte_flow_item *pattern, 4357 struct rte_flow_error *error, 4358 struct i40e_tunnel_filter_conf *filter) 4359 { 4360 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4361 const struct rte_flow_item *item = pattern; 4362 const struct rte_flow_item_gtp *gtp_spec; 4363 const struct rte_flow_item_gtp *gtp_mask; 4364 enum rte_flow_item_type item_type; 4365 4366 if (!pf->gtp_support) { 4367 rte_flow_error_set(error, EINVAL, 4368 RTE_FLOW_ERROR_TYPE_ITEM, 4369 item, 4370 "GTP is not supported by default."); 4371 return -rte_errno; 4372 } 4373 4374 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 4375 if (item->last) { 4376 rte_flow_error_set(error, EINVAL, 4377 RTE_FLOW_ERROR_TYPE_ITEM, 4378 item, 4379 "Not support range"); 4380 return -rte_errno; 4381 } 4382 item_type = item->type; 4383 switch (item_type) { 4384 case RTE_FLOW_ITEM_TYPE_ETH: 4385 if (item->spec || item->mask) { 4386 rte_flow_error_set(error, EINVAL, 4387 RTE_FLOW_ERROR_TYPE_ITEM, 4388 item, 4389 "Invalid ETH item"); 4390 return -rte_errno; 4391 } 4392 break; 4393 case RTE_FLOW_ITEM_TYPE_IPV4: 4394 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 4395 /* IPv4 is used to describe protocol, 4396 * spec and mask should be NULL. 4397 */ 4398 if (item->spec || item->mask) { 4399 rte_flow_error_set(error, EINVAL, 4400 RTE_FLOW_ERROR_TYPE_ITEM, 4401 item, 4402 "Invalid IPv4 item"); 4403 return -rte_errno; 4404 } 4405 break; 4406 case RTE_FLOW_ITEM_TYPE_UDP: 4407 if (item->spec || item->mask) { 4408 rte_flow_error_set(error, EINVAL, 4409 RTE_FLOW_ERROR_TYPE_ITEM, 4410 item, 4411 "Invalid UDP item"); 4412 return -rte_errno; 4413 } 4414 break; 4415 case RTE_FLOW_ITEM_TYPE_GTPC: 4416 case RTE_FLOW_ITEM_TYPE_GTPU: 4417 gtp_spec = item->spec; 4418 gtp_mask = item->mask; 4419 4420 if (!gtp_spec || !gtp_mask) { 4421 rte_flow_error_set(error, EINVAL, 4422 RTE_FLOW_ERROR_TYPE_ITEM, 4423 item, 4424 "Invalid GTP item"); 4425 return -rte_errno; 4426 } 4427 4428 if (gtp_mask->v_pt_rsv_flags || 4429 gtp_mask->msg_type || 4430 gtp_mask->msg_len || 4431 gtp_mask->teid != UINT32_MAX) { 4432 rte_flow_error_set(error, EINVAL, 4433 RTE_FLOW_ERROR_TYPE_ITEM, 4434 item, 4435 "Invalid GTP mask"); 4436 return -rte_errno; 4437 } 4438 4439 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC) 4440 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC; 4441 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU) 4442 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU; 4443 4444 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid); 4445 4446 break; 4447 default: 4448 break; 4449 } 4450 } 4451 4452 return 0; 4453 } 4454 4455 static int 4456 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev, 4457 const struct rte_flow_attr *attr, 4458 const struct rte_flow_item pattern[], 4459 const struct rte_flow_action actions[], 4460 struct rte_flow_error *error, 4461 union i40e_filter_t *filter) 4462 { 4463 struct i40e_tunnel_filter_conf *tunnel_filter = 4464 &filter->consistent_tunnel_filter; 4465 int ret; 4466 4467 ret = i40e_flow_parse_gtp_pattern(dev, pattern, 4468 error, tunnel_filter); 4469 if (ret) 4470 return ret; 4471 4472 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 4473 if (ret) 4474 return ret; 4475 4476 ret = i40e_flow_parse_attr(attr, error); 4477 if (ret) 4478 return ret; 4479 4480 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 4481 4482 return ret; 4483 } 4484 4485 /* 1. Last in item should be NULL as range is not supported. 4486 * 2. Supported filter types: QINQ. 4487 * 3. Mask of fields which need to be matched should be 4488 * filled with 1. 4489 * 4. Mask of fields which needn't to be matched should be 4490 * filled with 0. 4491 */ 4492 static int 4493 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev, 4494 const struct rte_flow_item *pattern, 4495 struct rte_flow_error *error, 4496 struct i40e_tunnel_filter_conf *filter) 4497 { 4498 const struct rte_flow_item *item = pattern; 4499 const struct rte_flow_item_vlan *vlan_spec = NULL; 4500 const struct rte_flow_item_vlan *vlan_mask = NULL; 4501 const struct rte_flow_item_vlan *i_vlan_spec = NULL; 4502 const struct rte_flow_item_vlan *i_vlan_mask = NULL; 4503 const struct rte_flow_item_vlan *o_vlan_spec = NULL; 4504 const struct rte_flow_item_vlan *o_vlan_mask = NULL; 4505 4506 enum rte_flow_item_type item_type; 4507 bool vlan_flag = 0; 4508 4509 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 4510 if (item->last) { 4511 rte_flow_error_set(error, EINVAL, 4512 RTE_FLOW_ERROR_TYPE_ITEM, 4513 item, 4514 "Not support range"); 4515 return -rte_errno; 4516 } 4517 item_type = item->type; 4518 switch (item_type) { 4519 case RTE_FLOW_ITEM_TYPE_ETH: 4520 if (item->spec || item->mask) { 4521 rte_flow_error_set(error, EINVAL, 4522 RTE_FLOW_ERROR_TYPE_ITEM, 4523 item, 4524 "Invalid ETH item"); 4525 return -rte_errno; 4526 } 4527 break; 4528 case RTE_FLOW_ITEM_TYPE_VLAN: 4529 vlan_spec = item->spec; 4530 vlan_mask = item->mask; 4531 4532 if (!(vlan_spec && vlan_mask) || 4533 vlan_mask->inner_type) { 4534 rte_flow_error_set(error, EINVAL, 4535 RTE_FLOW_ERROR_TYPE_ITEM, 4536 item, 4537 "Invalid vlan item"); 4538 return -rte_errno; 4539 } 4540 4541 if (!vlan_flag) { 4542 o_vlan_spec = vlan_spec; 4543 o_vlan_mask = vlan_mask; 4544 vlan_flag = 1; 4545 } else { 4546 i_vlan_spec = vlan_spec; 4547 i_vlan_mask = vlan_mask; 4548 vlan_flag = 0; 4549 } 4550 break; 4551 4552 default: 4553 break; 4554 } 4555 } 4556 4557 /* Get filter specification */ 4558 if (o_vlan_mask != NULL && i_vlan_mask != NULL) { 4559 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci); 4560 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci); 4561 } else { 4562 rte_flow_error_set(error, EINVAL, 4563 RTE_FLOW_ERROR_TYPE_ITEM, 4564 NULL, 4565 "Invalid filter type"); 4566 return -rte_errno; 4567 } 4568 4569 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ; 4570 return 0; 4571 } 4572 4573 static int 4574 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev, 4575 const struct rte_flow_attr *attr, 4576 const struct rte_flow_item pattern[], 4577 const struct rte_flow_action actions[], 4578 struct rte_flow_error *error, 4579 union i40e_filter_t *filter) 4580 { 4581 struct i40e_tunnel_filter_conf *tunnel_filter = 4582 &filter->consistent_tunnel_filter; 4583 int ret; 4584 4585 ret = i40e_flow_parse_qinq_pattern(dev, pattern, 4586 error, tunnel_filter); 4587 if (ret) 4588 return ret; 4589 4590 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 4591 if (ret) 4592 return ret; 4593 4594 ret = i40e_flow_parse_attr(attr, error); 4595 if (ret) 4596 return ret; 4597 4598 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 4599 4600 return ret; 4601 } 4602 4603 static int 4604 i40e_flow_validate(struct rte_eth_dev *dev, 4605 const struct rte_flow_attr *attr, 4606 const struct rte_flow_item pattern[], 4607 const struct rte_flow_action actions[], 4608 struct rte_flow_error *error) 4609 { 4610 struct rte_flow_item *items; /* internal pattern w/o VOID items */ 4611 parse_filter_t parse_filter; 4612 uint32_t item_num = 0; /* non-void item number of pattern*/ 4613 uint32_t i = 0; 4614 bool flag = false; 4615 int ret = I40E_NOT_SUPPORTED; 4616 4617 if (!pattern) { 4618 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM, 4619 NULL, "NULL pattern."); 4620 return -rte_errno; 4621 } 4622 4623 if (!actions) { 4624 rte_flow_error_set(error, EINVAL, 4625 RTE_FLOW_ERROR_TYPE_ACTION_NUM, 4626 NULL, "NULL action."); 4627 return -rte_errno; 4628 } 4629 4630 if (!attr) { 4631 rte_flow_error_set(error, EINVAL, 4632 RTE_FLOW_ERROR_TYPE_ATTR, 4633 NULL, "NULL attribute."); 4634 return -rte_errno; 4635 } 4636 memset(&cons_filter, 0, sizeof(cons_filter)); 4637 4638 /* Get the non-void item of action */ 4639 while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID) 4640 i++; 4641 4642 if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) { 4643 ret = i40e_flow_parse_attr(attr, error); 4644 if (ret) 4645 return ret; 4646 4647 cons_filter_type = RTE_ETH_FILTER_HASH; 4648 return i40e_hash_parse(dev, pattern, actions + i, 4649 &cons_filter.rss_conf, error); 4650 } 4651 4652 i = 0; 4653 /* Get the non-void item number of pattern */ 4654 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) { 4655 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID) 4656 item_num++; 4657 i++; 4658 } 4659 item_num++; 4660 4661 if (item_num <= ARRAY_SIZE(g_items)) { 4662 items = g_items; 4663 } else { 4664 items = rte_zmalloc("i40e_pattern", 4665 item_num * sizeof(struct rte_flow_item), 0); 4666 if (!items) { 4667 rte_flow_error_set(error, ENOMEM, 4668 RTE_FLOW_ERROR_TYPE_ITEM_NUM, 4669 NULL, 4670 "No memory for PMD internal items."); 4671 return -ENOMEM; 4672 } 4673 } 4674 4675 i40e_pattern_skip_void_item(items, pattern); 4676 4677 i = 0; 4678 do { 4679 parse_filter = i40e_find_parse_filter_func(items, &i); 4680 if (!parse_filter && !flag) { 4681 rte_flow_error_set(error, EINVAL, 4682 RTE_FLOW_ERROR_TYPE_ITEM, 4683 pattern, "Unsupported pattern"); 4684 4685 if (items != g_items) 4686 rte_free(items); 4687 return -rte_errno; 4688 } 4689 4690 if (parse_filter) 4691 ret = parse_filter(dev, attr, items, actions, 4692 error, &cons_filter); 4693 4694 flag = true; 4695 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns))); 4696 4697 if (items != g_items) 4698 rte_free(items); 4699 4700 return ret; 4701 } 4702 4703 static struct rte_flow * 4704 i40e_flow_create(struct rte_eth_dev *dev, 4705 const struct rte_flow_attr *attr, 4706 const struct rte_flow_item pattern[], 4707 const struct rte_flow_action actions[], 4708 struct rte_flow_error *error) 4709 { 4710 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4711 struct rte_flow *flow = NULL; 4712 struct i40e_fdir_info *fdir_info = &pf->fdir; 4713 int ret; 4714 4715 ret = i40e_flow_validate(dev, attr, pattern, actions, error); 4716 if (ret < 0) 4717 return NULL; 4718 4719 if (cons_filter_type == RTE_ETH_FILTER_FDIR) { 4720 flow = i40e_fdir_entry_pool_get(fdir_info); 4721 if (flow == NULL) { 4722 rte_flow_error_set(error, ENOBUFS, 4723 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4724 "Fdir space full"); 4725 4726 return flow; 4727 } 4728 } else { 4729 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0); 4730 if (!flow) { 4731 rte_flow_error_set(error, ENOMEM, 4732 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4733 "Failed to allocate memory"); 4734 return flow; 4735 } 4736 } 4737 4738 switch (cons_filter_type) { 4739 case RTE_ETH_FILTER_ETHERTYPE: 4740 ret = i40e_ethertype_filter_set(pf, 4741 &cons_filter.ethertype_filter, 1); 4742 if (ret) 4743 goto free_flow; 4744 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list, 4745 i40e_ethertype_filter_list); 4746 break; 4747 case RTE_ETH_FILTER_FDIR: 4748 ret = i40e_flow_add_del_fdir_filter(dev, 4749 &cons_filter.fdir_filter, 1); 4750 if (ret) 4751 goto free_flow; 4752 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list, 4753 i40e_fdir_filter_list); 4754 break; 4755 case RTE_ETH_FILTER_TUNNEL: 4756 ret = i40e_dev_consistent_tunnel_filter_set(pf, 4757 &cons_filter.consistent_tunnel_filter, 1); 4758 if (ret) 4759 goto free_flow; 4760 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list, 4761 i40e_tunnel_filter_list); 4762 break; 4763 case RTE_ETH_FILTER_HASH: 4764 ret = i40e_hash_filter_create(pf, &cons_filter.rss_conf); 4765 if (ret) 4766 goto free_flow; 4767 flow->rule = TAILQ_LAST(&pf->rss_config_list, 4768 i40e_rss_conf_list); 4769 break; 4770 default: 4771 goto free_flow; 4772 } 4773 4774 flow->filter_type = cons_filter_type; 4775 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node); 4776 return flow; 4777 4778 free_flow: 4779 rte_flow_error_set(error, -ret, 4780 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4781 "Failed to create flow."); 4782 4783 if (cons_filter_type != RTE_ETH_FILTER_FDIR) 4784 rte_free(flow); 4785 else 4786 i40e_fdir_entry_pool_put(fdir_info, flow); 4787 4788 return NULL; 4789 } 4790 4791 static int 4792 i40e_flow_destroy(struct rte_eth_dev *dev, 4793 struct rte_flow *flow, 4794 struct rte_flow_error *error) 4795 { 4796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4797 enum rte_filter_type filter_type = flow->filter_type; 4798 struct i40e_fdir_info *fdir_info = &pf->fdir; 4799 int ret = 0; 4800 4801 switch (filter_type) { 4802 case RTE_ETH_FILTER_ETHERTYPE: 4803 ret = i40e_flow_destroy_ethertype_filter(pf, 4804 (struct i40e_ethertype_filter *)flow->rule); 4805 break; 4806 case RTE_ETH_FILTER_TUNNEL: 4807 ret = i40e_flow_destroy_tunnel_filter(pf, 4808 (struct i40e_tunnel_filter *)flow->rule); 4809 break; 4810 case RTE_ETH_FILTER_FDIR: 4811 ret = i40e_flow_add_del_fdir_filter(dev, 4812 &((struct i40e_fdir_filter *)flow->rule)->fdir, 4813 0); 4814 4815 /* If the last flow is destroyed, disable fdir. */ 4816 if (!ret && TAILQ_EMPTY(&pf->fdir.fdir_list)) { 4817 i40e_fdir_rx_proc_enable(dev, 0); 4818 } 4819 break; 4820 case RTE_ETH_FILTER_HASH: 4821 ret = i40e_hash_filter_destroy(pf, flow->rule); 4822 break; 4823 default: 4824 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 4825 filter_type); 4826 ret = -EINVAL; 4827 break; 4828 } 4829 4830 if (!ret) { 4831 TAILQ_REMOVE(&pf->flow_list, flow, node); 4832 if (filter_type == RTE_ETH_FILTER_FDIR) 4833 i40e_fdir_entry_pool_put(fdir_info, flow); 4834 else 4835 rte_free(flow); 4836 4837 } else 4838 rte_flow_error_set(error, -ret, 4839 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4840 "Failed to destroy flow."); 4841 4842 return ret; 4843 } 4844 4845 static int 4846 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf, 4847 struct i40e_ethertype_filter *filter) 4848 { 4849 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4850 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 4851 struct i40e_ethertype_filter *node; 4852 struct i40e_control_filter_stats stats; 4853 uint16_t flags = 0; 4854 int ret = 0; 4855 4856 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC)) 4857 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 4858 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) 4859 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 4860 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 4861 4862 memset(&stats, 0, sizeof(stats)); 4863 ret = i40e_aq_add_rem_control_packet_filter(hw, 4864 filter->input.mac_addr.addr_bytes, 4865 filter->input.ether_type, 4866 flags, pf->main_vsi->seid, 4867 filter->queue, 0, &stats, NULL); 4868 if (ret < 0) 4869 return ret; 4870 4871 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input); 4872 if (!node) 4873 return -EINVAL; 4874 4875 ret = i40e_sw_ethertype_filter_del(pf, &node->input); 4876 4877 return ret; 4878 } 4879 4880 static int 4881 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf, 4882 struct i40e_tunnel_filter *filter) 4883 { 4884 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4885 struct i40e_vsi *vsi; 4886 struct i40e_pf_vf *vf; 4887 struct i40e_aqc_cloud_filters_element_bb cld_filter; 4888 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 4889 struct i40e_tunnel_filter *node; 4890 bool big_buffer = 0; 4891 int ret = 0; 4892 4893 memset(&cld_filter, 0, sizeof(cld_filter)); 4894 rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac, 4895 (struct rte_ether_addr *)&cld_filter.element.outer_mac); 4896 rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac, 4897 (struct rte_ether_addr *)&cld_filter.element.inner_mac); 4898 cld_filter.element.inner_vlan = filter->input.inner_vlan; 4899 cld_filter.element.flags = filter->input.flags; 4900 cld_filter.element.tenant_id = filter->input.tenant_id; 4901 cld_filter.element.queue_number = filter->queue; 4902 rte_memcpy(cld_filter.general_fields, 4903 filter->input.general_fields, 4904 sizeof(cld_filter.general_fields)); 4905 4906 if (!filter->is_to_vf) 4907 vsi = pf->main_vsi; 4908 else { 4909 vf = &pf->vfs[filter->vf_id]; 4910 vsi = vf->vsi; 4911 } 4912 4913 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) == 4914 I40E_AQC_ADD_CLOUD_FILTER_0X11) || 4915 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) == 4916 I40E_AQC_ADD_CLOUD_FILTER_0X12) || 4917 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) == 4918 I40E_AQC_ADD_CLOUD_FILTER_0X10)) 4919 big_buffer = 1; 4920 4921 if (big_buffer) 4922 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid, 4923 &cld_filter, 1); 4924 else 4925 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 4926 &cld_filter.element, 1); 4927 if (ret < 0) 4928 return -ENOTSUP; 4929 4930 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input); 4931 if (!node) 4932 return -EINVAL; 4933 4934 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 4935 4936 return ret; 4937 } 4938 4939 static int 4940 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error) 4941 { 4942 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4943 int ret; 4944 4945 ret = i40e_flow_flush_fdir_filter(pf); 4946 if (ret) { 4947 rte_flow_error_set(error, -ret, 4948 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4949 "Failed to flush FDIR flows."); 4950 return -rte_errno; 4951 } 4952 4953 ret = i40e_flow_flush_ethertype_filter(pf); 4954 if (ret) { 4955 rte_flow_error_set(error, -ret, 4956 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4957 "Failed to ethertype flush flows."); 4958 return -rte_errno; 4959 } 4960 4961 ret = i40e_flow_flush_tunnel_filter(pf); 4962 if (ret) { 4963 rte_flow_error_set(error, -ret, 4964 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4965 "Failed to flush tunnel flows."); 4966 return -rte_errno; 4967 } 4968 4969 ret = i40e_hash_filter_flush(pf); 4970 if (ret) 4971 rte_flow_error_set(error, -ret, 4972 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4973 "Failed to flush RSS flows."); 4974 return ret; 4975 } 4976 4977 static int 4978 i40e_flow_flush_fdir_filter(struct i40e_pf *pf) 4979 { 4980 struct rte_eth_dev *dev = pf->adapter->eth_dev; 4981 struct i40e_fdir_info *fdir_info = &pf->fdir; 4982 struct i40e_fdir_filter *fdir_filter; 4983 enum i40e_filter_pctype pctype; 4984 struct rte_flow *flow; 4985 void *temp; 4986 int ret; 4987 uint32_t i = 0; 4988 4989 ret = i40e_fdir_flush(dev); 4990 if (!ret) { 4991 /* Delete FDIR filters in FDIR list. */ 4992 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 4993 ret = i40e_sw_fdir_filter_del(pf, 4994 &fdir_filter->fdir.input); 4995 if (ret < 0) 4996 return ret; 4997 } 4998 4999 /* Delete FDIR flows in flow list. */ 5000 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) { 5001 if (flow->filter_type == RTE_ETH_FILTER_FDIR) { 5002 TAILQ_REMOVE(&pf->flow_list, flow, node); 5003 } 5004 } 5005 5006 /* reset bitmap */ 5007 rte_bitmap_reset(fdir_info->fdir_flow_pool.bitmap); 5008 for (i = 0; i < fdir_info->fdir_space_size; i++) { 5009 fdir_info->fdir_flow_pool.pool[i].idx = i; 5010 rte_bitmap_set(fdir_info->fdir_flow_pool.bitmap, i); 5011 } 5012 5013 fdir_info->fdir_actual_cnt = 0; 5014 fdir_info->fdir_guarantee_free_space = 5015 fdir_info->fdir_guarantee_total_space; 5016 memset(fdir_info->fdir_filter_array, 5017 0, 5018 sizeof(struct i40e_fdir_filter) * 5019 I40E_MAX_FDIR_FILTER_NUM); 5020 5021 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 5022 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) { 5023 pf->fdir.inset_flag[pctype] = 0; 5024 pf->fdir.flex_mask_flag[pctype] = 0; 5025 } 5026 5027 for (i = 0; i < I40E_MAX_FLXPLD_LAYER; i++) 5028 pf->fdir.flex_pit_flag[i] = 0; 5029 5030 /* Disable FDIR processing as all FDIR rules are now flushed */ 5031 i40e_fdir_rx_proc_enable(dev, 0); 5032 } 5033 5034 return ret; 5035 } 5036 5037 /* Flush all ethertype filters */ 5038 static int 5039 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf) 5040 { 5041 struct i40e_ethertype_filter_list 5042 *ethertype_list = &pf->ethertype.ethertype_list; 5043 struct i40e_ethertype_filter *filter; 5044 struct rte_flow *flow; 5045 void *temp; 5046 int ret = 0; 5047 5048 while ((filter = TAILQ_FIRST(ethertype_list))) { 5049 ret = i40e_flow_destroy_ethertype_filter(pf, filter); 5050 if (ret) 5051 return ret; 5052 } 5053 5054 /* Delete ethertype flows in flow list. */ 5055 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) { 5056 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) { 5057 TAILQ_REMOVE(&pf->flow_list, flow, node); 5058 rte_free(flow); 5059 } 5060 } 5061 5062 return ret; 5063 } 5064 5065 /* Flush all tunnel filters */ 5066 static int 5067 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf) 5068 { 5069 struct i40e_tunnel_filter_list 5070 *tunnel_list = &pf->tunnel.tunnel_list; 5071 struct i40e_tunnel_filter *filter; 5072 struct rte_flow *flow; 5073 void *temp; 5074 int ret = 0; 5075 5076 while ((filter = TAILQ_FIRST(tunnel_list))) { 5077 ret = i40e_flow_destroy_tunnel_filter(pf, filter); 5078 if (ret) 5079 return ret; 5080 } 5081 5082 /* Delete tunnel flows in flow list. */ 5083 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) { 5084 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) { 5085 TAILQ_REMOVE(&pf->flow_list, flow, node); 5086 rte_free(flow); 5087 } 5088 } 5089 5090 return ret; 5091 } 5092 5093 static int 5094 i40e_flow_query(struct rte_eth_dev *dev __rte_unused, 5095 struct rte_flow *flow, 5096 const struct rte_flow_action *actions, 5097 void *data, struct rte_flow_error *error) 5098 { 5099 struct i40e_rss_filter *rss_rule = (struct i40e_rss_filter *)flow->rule; 5100 enum rte_filter_type filter_type = flow->filter_type; 5101 struct rte_flow_action_rss *rss_conf = data; 5102 5103 if (!rss_rule) { 5104 rte_flow_error_set(error, EINVAL, 5105 RTE_FLOW_ERROR_TYPE_HANDLE, 5106 NULL, "Invalid rule"); 5107 return -rte_errno; 5108 } 5109 5110 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5111 switch (actions->type) { 5112 case RTE_FLOW_ACTION_TYPE_VOID: 5113 break; 5114 case RTE_FLOW_ACTION_TYPE_RSS: 5115 if (filter_type != RTE_ETH_FILTER_HASH) { 5116 rte_flow_error_set(error, ENOTSUP, 5117 RTE_FLOW_ERROR_TYPE_ACTION, 5118 actions, 5119 "action not supported"); 5120 return -rte_errno; 5121 } 5122 rte_memcpy(rss_conf, 5123 &rss_rule->rss_filter_info.conf, 5124 sizeof(struct rte_flow_action_rss)); 5125 break; 5126 default: 5127 return rte_flow_error_set(error, ENOTSUP, 5128 RTE_FLOW_ERROR_TYPE_ACTION, 5129 actions, 5130 "action not supported"); 5131 } 5132 } 5133 5134 return 0; 5135 } 5136