1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_time.h> 11 #include <rte_kvargs.h> 12 #include <rte_hash.h> 13 #include <rte_flow.h> 14 #include <rte_flow_driver.h> 15 #include <rte_tm_driver.h> 16 #include "rte_pmd_i40e.h" 17 18 #include "base/i40e_register.h" 19 #include "base/i40e_type.h" 20 #include "base/virtchnl.h" 21 22 #define I40E_VLAN_TAG_SIZE 4 23 24 #define I40E_AQ_LEN 32 25 #define I40E_AQ_BUF_SZ 4096 26 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 27 #define I40E_MAX_Q_PER_TC 64 28 #define I40E_NUM_DESC_DEFAULT 512 29 #define I40E_NUM_DESC_ALIGN 32 30 #define I40E_BUF_SIZE_MIN 1024 31 #define I40E_FRAME_SIZE_MAX 9728 32 #define I40E_TSO_FRAME_SIZE_MAX 262144 33 #define I40E_QUEUE_BASE_ADDR_UNIT 128 34 /* number of VSIs and queue default setting */ 35 #define I40E_MAX_QP_NUM_PER_VF 16 36 #define I40E_DEFAULT_QP_NUM_FDIR 1 37 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 38 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 39 /* Maximun number of MAC addresses */ 40 #define I40E_NUM_MACADDR_MAX 64 41 /* Maximum number of VFs */ 42 #define I40E_MAX_VF 128 43 /*flag of no loopback*/ 44 #define I40E_AQ_LB_MODE_NONE 0x0 45 /* 46 * vlan_id is a 12 bit number. 47 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 48 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 49 * The higher 7 bit val specifies VFTA array index. 50 */ 51 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 52 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 53 54 /* Default TC traffic in case DCB is not enabled */ 55 #define I40E_DEFAULT_TCMAP 0x1 56 #define I40E_FDIR_QUEUE_ID 0 57 58 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 59 #define I40E_VMDQ_POOL_BASE 1 60 61 #define I40E_DEFAULT_RX_FREE_THRESH 32 62 #define I40E_DEFAULT_RX_PTHRESH 8 63 #define I40E_DEFAULT_RX_HTHRESH 8 64 #define I40E_DEFAULT_RX_WTHRESH 0 65 66 #define I40E_DEFAULT_TX_FREE_THRESH 32 67 #define I40E_DEFAULT_TX_PTHRESH 32 68 #define I40E_DEFAULT_TX_HTHRESH 0 69 #define I40E_DEFAULT_TX_WTHRESH 0 70 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 71 72 /* Bit shift and mask */ 73 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 74 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 75 #define I40E_8_BIT_WIDTH CHAR_BIT 76 #define I40E_8_BIT_MASK UINT8_MAX 77 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 78 #define I40E_16_BIT_MASK UINT16_MAX 79 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 80 #define I40E_32_BIT_MASK UINT32_MAX 81 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 82 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 83 84 /* Linux PF host with virtchnl version 1.1 */ 85 #define PF_IS_V11(vf) \ 86 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 87 ((vf)->version_minor == 1)) 88 89 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 90 do { \ 91 uint32_t ori_val; \ 92 struct rte_eth_dev *dev; \ 93 struct rte_eth_dev_data *dev_data; \ 94 ori_val = I40E_READ_REG((hw), (reg)); \ 95 dev_data = ((struct i40e_adapter *)hw->back)->pf.dev_data; \ 96 dev = &rte_eth_devices[dev_data->port_id]; \ 97 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 98 (reg)), (value)); \ 99 if (ori_val != value) \ 100 PMD_DRV_LOG(WARNING, \ 101 "i40e device %s changed global " \ 102 "register [0x%08x]. original: 0x%08x, " \ 103 "new: 0x%08x ", \ 104 (dev->device->name), (reg), \ 105 (ori_val), (value)); \ 106 } while (0) 107 108 /* index flex payload per layer */ 109 enum i40e_flxpld_layer_idx { 110 I40E_FLXPLD_L2_IDX = 0, 111 I40E_FLXPLD_L3_IDX = 1, 112 I40E_FLXPLD_L4_IDX = 2, 113 I40E_MAX_FLXPLD_LAYER = 3, 114 }; 115 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 116 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 117 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 118 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 119 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 120 121 /* i40e flags */ 122 #define I40E_FLAG_RSS (1ULL << 0) 123 #define I40E_FLAG_DCB (1ULL << 1) 124 #define I40E_FLAG_VMDQ (1ULL << 2) 125 #define I40E_FLAG_SRIOV (1ULL << 3) 126 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 127 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 128 #define I40E_FLAG_FDIR (1ULL << 6) 129 #define I40E_FLAG_VXLAN (1ULL << 7) 130 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 131 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 132 I40E_FLAG_DCB | \ 133 I40E_FLAG_VMDQ | \ 134 I40E_FLAG_SRIOV | \ 135 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 136 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 137 I40E_FLAG_FDIR | \ 138 I40E_FLAG_VXLAN | \ 139 I40E_FLAG_RSS_AQ_CAPABLE) 140 141 #define I40E_RSS_OFFLOAD_ALL ( \ 142 ETH_RSS_FRAG_IPV4 | \ 143 ETH_RSS_NONFRAG_IPV4_TCP | \ 144 ETH_RSS_NONFRAG_IPV4_UDP | \ 145 ETH_RSS_NONFRAG_IPV4_SCTP | \ 146 ETH_RSS_NONFRAG_IPV4_OTHER | \ 147 ETH_RSS_FRAG_IPV6 | \ 148 ETH_RSS_NONFRAG_IPV6_TCP | \ 149 ETH_RSS_NONFRAG_IPV6_UDP | \ 150 ETH_RSS_NONFRAG_IPV6_SCTP | \ 151 ETH_RSS_NONFRAG_IPV6_OTHER | \ 152 ETH_RSS_L2_PAYLOAD) 153 154 /* All bits of RSS hash enable for X722*/ 155 #define I40E_RSS_HENA_ALL_X722 ( \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 158 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 159 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 160 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 161 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 162 I40E_RSS_HENA_ALL) 163 164 /* All bits of RSS hash enable */ 165 #define I40E_RSS_HENA_ALL ( \ 166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 170 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 175 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 176 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 177 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 178 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 179 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 180 181 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 182 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 183 184 /* Default queue interrupt throttling time in microseconds */ 185 #define I40E_ITR_INDEX_DEFAULT 0 186 #define I40E_ITR_INDEX_NONE 3 187 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 188 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 189 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 190 /* Special FW support this floating VEB feature */ 191 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 192 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 193 194 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 195 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 196 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 197 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 198 199 #define I40E_RSS_TYPE_NONE 0ULL 200 #define I40E_RSS_TYPE_INVALID 1ULL 201 202 #define I40E_INSET_NONE 0x00000000000000000ULL 203 204 /* bit0 ~ bit 7 */ 205 #define I40E_INSET_DMAC 0x0000000000000001ULL 206 #define I40E_INSET_SMAC 0x0000000000000002ULL 207 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 208 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 209 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 210 211 /* bit 8 ~ bit 15 */ 212 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 213 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 214 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 215 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 216 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 217 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 218 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 219 220 /* bit 16 ~ bit 31 */ 221 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 222 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 223 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 224 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 225 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 226 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 227 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 228 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 229 230 /* bit 32 ~ bit 47, tunnel fields */ 231 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 232 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 233 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 234 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 235 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 236 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 237 238 /* bit 48 ~ bit 55 */ 239 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 240 241 /* bit 56 ~ bit 63, Flex Payload */ 242 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 243 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 244 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 245 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 246 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 247 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 248 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 249 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 250 #define I40E_INSET_FLEX_PAYLOAD \ 251 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 252 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 253 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 254 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 255 256 /* The max bandwidth of i40e is 40Gbps. */ 257 #define I40E_QOS_BW_MAX 40000 258 /* The bandwidth should be the multiple of 50Mbps. */ 259 #define I40E_QOS_BW_GRANULARITY 50 260 /* The min bandwidth weight is 1. */ 261 #define I40E_QOS_BW_WEIGHT_MIN 1 262 /* The max bandwidth weight is 127. */ 263 #define I40E_QOS_BW_WEIGHT_MAX 127 264 /* The max queue region index is 7. */ 265 #define I40E_REGION_MAX_INDEX 7 266 267 #define I40E_MAX_PERCENT 100 268 #define I40E_DEFAULT_DCB_APP_NUM 1 269 #define I40E_DEFAULT_DCB_APP_PRIO 3 270 271 #define I40E_FDIR_PRG_PKT_CNT 128 272 273 /* 274 * Struct to store flow created. 275 */ 276 struct rte_flow { 277 TAILQ_ENTRY(rte_flow) node; 278 enum rte_filter_type filter_type; 279 void *rule; 280 }; 281 282 /** 283 * The overhead from MTU to max frame size. 284 * Considering QinQ packet, the VLAN tag needs to be counted twice. 285 */ 286 #define I40E_ETH_OVERHEAD \ 287 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 288 #define I40E_ETH_MAX_LEN (RTE_ETHER_MTU + I40E_ETH_OVERHEAD) 289 290 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) 291 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) 292 293 struct i40e_adapter; 294 struct rte_pci_driver; 295 296 /** 297 * MAC filter type 298 */ 299 enum i40e_mac_filter_type { 300 I40E_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */ 301 I40E_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */ 302 I40E_MAC_HASH_MATCH, /**< hash match of MAC addr. */ 303 /** hash match of MAC addr and exact match of VLAN ID. */ 304 I40E_MACVLAN_HASH_MATCH, 305 }; 306 307 /** 308 * MAC filter structure 309 */ 310 struct i40e_mac_filter_info { 311 enum i40e_mac_filter_type filter_type; 312 struct rte_ether_addr mac_addr; 313 }; 314 315 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 316 317 /* MAC filter list structure */ 318 struct i40e_mac_filter { 319 TAILQ_ENTRY(i40e_mac_filter) next; 320 struct i40e_mac_filter_info mac_info; 321 }; 322 323 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 324 325 struct i40e_vsi; 326 327 /* VSI list structure */ 328 struct i40e_vsi_list { 329 TAILQ_ENTRY(i40e_vsi_list) list; 330 struct i40e_vsi *vsi; 331 }; 332 333 struct i40e_rx_queue; 334 struct i40e_tx_queue; 335 336 /* Bandwidth limit information */ 337 struct i40e_bw_info { 338 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 339 uint8_t bw_max; /* Max BW limit if enabled */ 340 341 /* Relative credits within same TC with respect to other VSIs or Comps */ 342 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 343 /* Bandwidth limit per TC */ 344 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 345 /* Max bandwidth limit per TC */ 346 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 347 }; 348 349 /* Structure that defines a VEB */ 350 struct i40e_veb { 351 struct i40e_vsi_list_head head; 352 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 353 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 354 uint16_t seid; /* The seid of VEB itself */ 355 uint16_t uplink_seid; /* The uplink seid of this VEB */ 356 uint16_t stats_idx; 357 struct i40e_eth_stats stats; 358 uint8_t enabled_tc; /* The traffic class enabled */ 359 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 360 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 361 }; 362 363 /* i40e MACVLAN filter structure */ 364 struct i40e_macvlan_filter { 365 struct rte_ether_addr macaddr; 366 enum i40e_mac_filter_type filter_type; 367 uint16_t vlan_id; 368 }; 369 370 /* 371 * Structure that defines a VSI, associated with a adapter. 372 */ 373 struct i40e_vsi { 374 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 375 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 376 377 struct i40e_eth_stats eth_stats_offset; 378 struct i40e_eth_stats eth_stats; 379 /* 380 * When drivers loaded, only a default main VSI exists. In case new VSI 381 * needs to add, HW needs to know the layout that VSIs are organized. 382 * Besides that, VSI isan element and can't switch packets, which needs 383 * to add new component VEB to perform switching. So, a new VSI needs 384 * to specify the uplink VSI (Parent VSI) before created. The 385 * uplink VSI will check whether it had a VEB to switch packets. If no, 386 * it will try to create one. Then, uplink VSI will move the new VSI 387 * into its' sib_vsi_list to manage all the downlink VSI. 388 * sib_vsi_list: the VSI list that shared the same uplink VSI. 389 * parent_vsi : the uplink VSI. It's NULL for main VSI. 390 * veb : the VEB associates with the VSI. 391 */ 392 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 393 struct i40e_vsi *parent_vsi; 394 struct i40e_veb *veb; /* Associated veb, could be null */ 395 struct i40e_veb *floating_veb; /* Associated floating veb */ 396 bool offset_loaded; 397 enum i40e_vsi_type type; /* VSI types */ 398 uint16_t vlan_num; /* Total VLAN number */ 399 uint16_t mac_num; /* Total mac number */ 400 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 401 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 402 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 403 uint32_t user_param; 404 uint16_t seid; /* The seid of VSI itself */ 405 uint16_t uplink_seid; /* The uplink seid of this VSI */ 406 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 407 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 408 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 409 uint16_t base_queue; /* The first queue index of this VSI */ 410 /* 411 * The offset to visit VSI related register, assigned by HW when 412 * creating VSI 413 */ 414 uint16_t vsi_id; 415 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 416 uint16_t nb_msix; /* The max number of msix vector */ 417 uint8_t enabled_tc; /* The traffic class enabled */ 418 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 419 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 420 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 421 uint64_t prev_rx_bytes; 422 uint64_t prev_tx_bytes; 423 }; 424 425 struct pool_entry { 426 LIST_ENTRY(pool_entry) next; 427 uint16_t base; 428 uint16_t len; 429 }; 430 431 LIST_HEAD(res_list, pool_entry); 432 433 struct i40e_res_pool_info { 434 uint32_t base; /* Resource start index */ 435 uint32_t num_alloc; /* Allocated resource number */ 436 uint32_t num_free; /* Total available resource number */ 437 struct res_list alloc_list; /* Allocated resource list */ 438 struct res_list free_list; /* Available resource list */ 439 }; 440 441 enum I40E_VF_STATE { 442 I40E_VF_INACTIVE = 0, 443 I40E_VF_INRESET, 444 I40E_VF_ININIT, 445 I40E_VF_ACTIVE, 446 }; 447 448 /* 449 * Structure to store private data for PF host. 450 */ 451 struct i40e_pf_vf { 452 struct i40e_pf *pf; 453 struct i40e_vsi *vsi; 454 enum I40E_VF_STATE state; /* The number of queue pairs available */ 455 uint16_t vf_idx; /* VF index in pf->vfs */ 456 uint16_t lan_nb_qps; /* Actual queues allocated */ 457 uint16_t reset_cnt; /* Total vf reset times */ 458 struct rte_ether_addr mac_addr; /* Default MAC address */ 459 /* version of the virtchnl from VF */ 460 struct virtchnl_version_info version; 461 uint32_t request_caps; /* offload caps requested from VF */ 462 uint64_t num_mdd_events; /* num of mdd events detected */ 463 464 /* 465 * Variables for store the arrival timestamp of VF messages. 466 * If the timestamp of latest message stored at 467 * `msg_timestamps[index % max]` then the timestamp of 468 * earliest message stored at `msg_time[(index + 1) % max]`. 469 * When a new message come, the timestamp of this message 470 * will be stored at `msg_timestamps[(index + 1) % max]` and the 471 * earliest message timestamp is at 472 * `msg_timestamps[(index + 2) % max]` now... 473 */ 474 uint32_t msg_index; 475 uint64_t *msg_timestamps; 476 477 /* cycle of stop ignoring VF message */ 478 uint64_t ignore_end_cycle; 479 }; 480 481 /* 482 * Structure to store private data for flow control. 483 */ 484 struct i40e_fc_conf { 485 uint16_t pause_time; /* Flow control pause timer */ 486 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 487 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 488 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 489 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 490 }; 491 492 /* 493 * Structure to store private data for VMDQ instance 494 */ 495 struct i40e_vmdq_info { 496 struct i40e_pf *pf; 497 struct i40e_vsi *vsi; 498 }; 499 500 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 501 #define I40E_MAX_FLX_SOURCE_OFF 480 502 #define NONUSE_FLX_PIT_DEST_OFF 63 503 #define NONUSE_FLX_PIT_FSIZE 1 504 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 505 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 506 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 507 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 508 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 509 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 510 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 511 NONUSE_FLX_PIT_DEST_OFF : \ 512 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 513 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 514 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 515 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 516 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 517 #define I40E_FDIR_IPv6_TC_OFFSET 20 518 519 /* A structure used to define the input for GTP flow */ 520 struct i40e_gtp_flow { 521 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 522 uint8_t msg_type; /* Message type. */ 523 uint32_t teid; /* TEID in big endian. */ 524 }; 525 526 /* A structure used to define the input for GTP IPV4 flow */ 527 struct i40e_gtp_ipv4_flow { 528 struct i40e_gtp_flow gtp; 529 struct rte_eth_ipv4_flow ip4; 530 }; 531 532 /* A structure used to define the input for GTP IPV6 flow */ 533 struct i40e_gtp_ipv6_flow { 534 struct i40e_gtp_flow gtp; 535 struct rte_eth_ipv6_flow ip6; 536 }; 537 538 /* A structure used to define the input for ESP IPV4 flow */ 539 struct i40e_esp_ipv4_flow { 540 struct rte_eth_ipv4_flow ipv4; 541 uint32_t spi; /* SPI in big endian. */ 542 }; 543 544 /* A structure used to define the input for ESP IPV6 flow */ 545 struct i40e_esp_ipv6_flow { 546 struct rte_eth_ipv6_flow ipv6; 547 uint32_t spi; /* SPI in big endian. */ 548 }; 549 /* A structure used to define the input for ESP IPV4 UDP flow */ 550 struct i40e_esp_ipv4_udp_flow { 551 struct rte_eth_udpv4_flow udp; 552 uint32_t spi; /* SPI in big endian. */ 553 }; 554 555 /* A structure used to define the input for ESP IPV6 UDP flow */ 556 struct i40e_esp_ipv6_udp_flow { 557 struct rte_eth_udpv6_flow udp; 558 uint32_t spi; /* SPI in big endian. */ 559 }; 560 561 /* A structure used to define the input for raw type flow */ 562 struct i40e_raw_flow { 563 uint16_t pctype; 564 void *packet; 565 uint32_t length; 566 }; 567 568 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 569 struct i40e_ipv4_l2tpv3oip_flow { 570 struct rte_eth_ipv4_flow ip4; 571 uint32_t session_id; /* Session ID in big endian. */ 572 }; 573 574 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 575 struct i40e_ipv6_l2tpv3oip_flow { 576 struct rte_eth_ipv6_flow ip6; 577 uint32_t session_id; /* Session ID in big endian. */ 578 }; 579 580 /* A structure used to define the input for l2 dst type flow */ 581 struct i40e_l2_flow { 582 struct rte_ether_addr dst; 583 struct rte_ether_addr src; 584 uint16_t ether_type; /**< Ether type in big endian */ 585 }; 586 587 /* 588 * A union contains the inputs for all types of flow 589 * items in flows need to be in big endian 590 */ 591 union i40e_fdir_flow { 592 struct i40e_l2_flow l2_flow; 593 struct rte_eth_udpv4_flow udp4_flow; 594 struct rte_eth_tcpv4_flow tcp4_flow; 595 struct rte_eth_sctpv4_flow sctp4_flow; 596 struct rte_eth_ipv4_flow ip4_flow; 597 struct rte_eth_udpv6_flow udp6_flow; 598 struct rte_eth_tcpv6_flow tcp6_flow; 599 struct rte_eth_sctpv6_flow sctp6_flow; 600 struct rte_eth_ipv6_flow ipv6_flow; 601 struct i40e_gtp_flow gtp_flow; 602 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 603 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 604 struct i40e_raw_flow raw_flow; 605 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 606 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 607 struct i40e_esp_ipv4_flow esp_ipv4_flow; 608 struct i40e_esp_ipv6_flow esp_ipv6_flow; 609 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 610 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 611 }; 612 613 enum i40e_fdir_ip_type { 614 I40E_FDIR_IPTYPE_IPV4, 615 I40E_FDIR_IPTYPE_IPV6, 616 }; 617 618 /** 619 * Structure to store flex pit for flow diretor. 620 */ 621 struct i40e_fdir_flex_pit { 622 uint8_t src_offset; /* offset in words from the beginning of payload */ 623 uint8_t size; /* size in words */ 624 uint8_t dst_offset; /* offset in words of flexible payload */ 625 }; 626 627 /* A structure used to contain extend input of flow */ 628 struct i40e_fdir_flow_ext { 629 uint16_t vlan_tci; 630 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 631 /* It is filled by the flexible payload to match. */ 632 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN]; 633 uint8_t raw_id; 634 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 635 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 636 uint64_t input_set; 637 bool inner_ip; /* If there is inner ip */ 638 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 639 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 640 bool customized_pctype; /* If customized pctype is used */ 641 bool pkt_template; /* If raw packet template is used */ 642 bool is_udp; /* ipv4|ipv6 udp flow */ 643 enum i40e_flxpld_layer_idx layer_idx; 644 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 645 bool is_flex_flow; 646 }; 647 648 /* A structure used to define the input for a flow director filter entry */ 649 struct i40e_fdir_input { 650 enum i40e_filter_pctype pctype; 651 union i40e_fdir_flow flow; 652 /* Flow fields to match, dependent on flow_type */ 653 struct i40e_fdir_flow_ext flow_ext; 654 /* Additional fields to match */ 655 }; 656 657 /* Behavior will be taken if FDIR match */ 658 enum i40e_fdir_behavior { 659 I40E_FDIR_ACCEPT = 0, 660 I40E_FDIR_REJECT, 661 I40E_FDIR_PASSTHRU, 662 }; 663 664 /* Flow director report status 665 * It defines what will be reported if FDIR entry is matched. 666 */ 667 enum i40e_fdir_status { 668 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 669 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 670 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 671 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 672 }; 673 674 /* A structure used to define an action when match FDIR packet filter. */ 675 struct i40e_fdir_action { 676 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 677 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 678 enum i40e_fdir_status report_status; /* Status report option */ 679 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 680 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 681 * flex bytes start from in flexible payload. 682 */ 683 uint8_t flex_off; 684 }; 685 686 /* A structure used to define the flow director filter entry by filter_ctrl API 687 * It supports RTE_ETH_FILTER_FDIR data representation. 688 */ 689 struct i40e_fdir_filter_conf { 690 uint32_t soft_id; 691 /* ID, an unique value is required when deal with FDIR entry */ 692 struct i40e_fdir_input input; /* Input set */ 693 struct i40e_fdir_action action; /* Action taken when match */ 694 }; 695 696 struct i40e_fdir_flex_mask { 697 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 698 uint8_t nb_bitmask; 699 struct { 700 uint8_t offset; 701 uint16_t mask; 702 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 703 }; 704 705 #define I40E_FILTER_PCTYPE_INVALID 0 706 #define I40E_FILTER_PCTYPE_MAX 64 707 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 708 709 struct i40e_fdir_filter { 710 TAILQ_ENTRY(i40e_fdir_filter) rules; 711 struct i40e_fdir_filter_conf fdir; 712 }; 713 714 /* fdir memory pool entry */ 715 struct i40e_fdir_entry { 716 struct rte_flow flow; 717 uint32_t idx; 718 }; 719 720 /* pre-allocated fdir memory pool */ 721 struct i40e_fdir_flow_pool { 722 /* a bitmap to manage the fdir pool */ 723 struct rte_bitmap *bitmap; 724 /* the size the pool is pf->fdir->fdir_space_size */ 725 struct i40e_fdir_entry *pool; 726 }; 727 728 #define FLOW_TO_FLOW_BITMAP(f) \ 729 container_of((f), struct i40e_fdir_entry, flow) 730 731 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 732 /* 733 * A structure used to define fields of a FDIR related info. 734 */ 735 struct i40e_fdir_info { 736 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 737 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 738 struct i40e_tx_queue *txq; 739 struct i40e_rx_queue *rxq; 740 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 741 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 742 /* 743 * txq available buffer counter, indicates how many available buffers 744 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 745 */ 746 int txq_available_buf_count; 747 748 /* input set bits for each pctype */ 749 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 750 /* 751 * the rule how bytes stream is extracted as flexible payload 752 * for each payload layer, the setting can up to three elements 753 */ 754 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 755 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 756 757 struct i40e_fdir_filter_list fdir_list; 758 struct i40e_fdir_filter **hash_map; 759 struct rte_hash *hash_table; 760 /* An array to store the inserted rules input */ 761 struct i40e_fdir_filter *fdir_filter_array; 762 763 /* 764 * Priority ordering at filter invalidation(destroying a flow) between 765 * "best effort" space and "guaranteed" space. 766 * 767 * 0 = At filter invalidation, the hardware first tries to increment the 768 * "best effort" space. The "guaranteed" space is incremented only when 769 * the global "best effort" space is at it max value or the "best effort" 770 * space of the PF is at its max value. 771 * 1 = At filter invalidation, the hardware first tries to increment its 772 * "guaranteed" space. The "best effort" space is incremented only when 773 * it is already at its max value. 774 */ 775 uint32_t fdir_invalprio; 776 /* the total size of the fdir, this number is the sum of the guaranteed + 777 * shared space 778 */ 779 uint32_t fdir_space_size; 780 /* the actual number of the fdir rules in hardware, initialized as 0 */ 781 uint32_t fdir_actual_cnt; 782 /* the free guaranteed space of the fdir */ 783 uint32_t fdir_guarantee_free_space; 784 /* the fdir total guaranteed space */ 785 uint32_t fdir_guarantee_total_space; 786 /* the pre-allocated pool of the rte_flow */ 787 struct i40e_fdir_flow_pool fdir_flow_pool; 788 789 /* Mark if flex pit and mask is set */ 790 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 791 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 792 793 uint32_t flow_count[I40E_FILTER_PCTYPE_MAX]; 794 795 uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER]; 796 }; 797 798 /* Ethertype filter number HW supports */ 799 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 800 801 /* Ethertype filter struct */ 802 struct i40e_ethertype_filter_input { 803 struct rte_ether_addr mac_addr; /* Mac address to match */ 804 uint16_t ether_type; /* Ether type to match */ 805 }; 806 807 struct i40e_ethertype_filter { 808 TAILQ_ENTRY(i40e_ethertype_filter) rules; 809 struct i40e_ethertype_filter_input input; 810 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 811 uint16_t queue; /* Queue assigned to when match */ 812 }; 813 814 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 815 816 struct i40e_ethertype_rule { 817 struct i40e_ethertype_filter_list ethertype_list; 818 struct i40e_ethertype_filter **hash_map; 819 struct rte_hash *hash_table; 820 }; 821 822 /* queue region info */ 823 struct i40e_queue_region_info { 824 /* the region id for this configuration */ 825 uint8_t region_id; 826 /* the start queue index for this region */ 827 uint8_t queue_start_index; 828 /* the total queue number of this queue region */ 829 uint8_t queue_num; 830 /* the total number of user priority for this region */ 831 uint8_t user_priority_num; 832 /* the packet's user priority for this region */ 833 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 834 /* the total number of flowtype for this region */ 835 uint8_t flowtype_num; 836 /** 837 * the pctype or hardware flowtype of packet, 838 * the specific index for each type has been defined 839 * in file i40e_type.h as enum i40e_filter_pctype. 840 */ 841 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 842 }; 843 844 struct i40e_queue_regions { 845 /* the total number of queue region for this port */ 846 uint16_t queue_region_number; 847 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 848 }; 849 850 struct i40e_rss_pattern_info { 851 uint8_t action_flag; 852 uint64_t types; 853 }; 854 855 /* Tunnel filter number HW supports */ 856 #define I40E_MAX_TUNNEL_FILTER_NUM 400 857 858 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 859 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 860 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 861 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 862 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 863 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 864 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 865 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 866 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 867 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 868 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 869 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 870 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 871 #define I40E_AQC_NEW_TR_21 21 872 #define I40E_AQC_NEW_TR_22 22 873 874 enum i40e_tunnel_iptype { 875 I40E_TUNNEL_IPTYPE_IPV4, 876 I40E_TUNNEL_IPTYPE_IPV6, 877 }; 878 879 /* Tunnel filter struct */ 880 struct i40e_tunnel_filter_input { 881 uint8_t outer_mac[6]; /* Outer mac address to match */ 882 uint8_t inner_mac[6]; /* Inner mac address to match */ 883 uint16_t inner_vlan; /* Inner vlan address to match */ 884 enum i40e_tunnel_iptype ip_type; 885 uint16_t flags; /* Filter type flag */ 886 uint32_t tenant_id; /* Tenant id to match */ 887 uint16_t general_fields[32]; /* Big buffer */ 888 }; 889 890 struct i40e_tunnel_filter { 891 TAILQ_ENTRY(i40e_tunnel_filter) rules; 892 struct i40e_tunnel_filter_input input; 893 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 894 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 895 uint16_t queue; /* Queue assigned to when match */ 896 }; 897 898 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 899 900 struct i40e_tunnel_rule { 901 struct i40e_tunnel_filter_list tunnel_list; 902 struct i40e_tunnel_filter **hash_map; 903 struct rte_hash *hash_table; 904 }; 905 906 /** 907 * Tunnel type. 908 */ 909 enum i40e_tunnel_type { 910 I40E_TUNNEL_TYPE_NONE = 0, 911 I40E_TUNNEL_TYPE_VXLAN, 912 I40E_TUNNEL_TYPE_GENEVE, 913 I40E_TUNNEL_TYPE_TEREDO, 914 I40E_TUNNEL_TYPE_NVGRE, 915 I40E_TUNNEL_TYPE_IP_IN_GRE, 916 I40E_L2_TUNNEL_TYPE_E_TAG, 917 I40E_TUNNEL_TYPE_MPLSoUDP, 918 I40E_TUNNEL_TYPE_MPLSoGRE, 919 I40E_TUNNEL_TYPE_QINQ, 920 I40E_TUNNEL_TYPE_GTPC, 921 I40E_TUNNEL_TYPE_GTPU, 922 I40E_TUNNEL_TYPE_ESPoUDP, 923 I40E_TUNNEL_TYPE_ESPoIP, 924 I40E_CLOUD_TYPE_UDP, 925 I40E_CLOUD_TYPE_TCP, 926 I40E_CLOUD_TYPE_SCTP, 927 I40E_TUNNEL_TYPE_MAX, 928 }; 929 930 /** 931 * L4 port type. 932 */ 933 enum i40e_l4_port_type { 934 I40E_L4_PORT_TYPE_SRC = 0, 935 I40E_L4_PORT_TYPE_DST, 936 }; 937 938 /** 939 * Tunneling Packet filter configuration. 940 */ 941 struct i40e_tunnel_filter_conf { 942 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 943 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 944 uint16_t inner_vlan; /**< Inner VLAN to match. */ 945 uint32_t outer_vlan; /**< Outer VLAN to match */ 946 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 947 /** 948 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 949 * is set in filter_type, or inner destination IP address to match 950 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 951 */ 952 union { 953 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 954 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 955 } ip_addr; 956 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 957 uint16_t filter_type; 958 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 959 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 960 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 961 uint16_t queue_id; /**< Queue assigned to if match. */ 962 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 963 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 964 }; 965 966 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 967 #define I40E_MAX_MIRROR_RULES 64 968 /* 969 * Mirror rule structure 970 */ 971 struct i40e_mirror_rule { 972 TAILQ_ENTRY(i40e_mirror_rule) rules; 973 uint8_t rule_type; 974 uint16_t index; /* the sw index of mirror rule */ 975 uint16_t id; /* the rule id assigned by firmware */ 976 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 977 uint16_t num_entries; 978 /* the info stores depend on the rule type. 979 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 980 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 981 */ 982 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 983 }; 984 985 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 986 987 TAILQ_HEAD(i40e_flow_list, rte_flow); 988 989 /* Struct to store Traffic Manager shaper profile. */ 990 struct i40e_tm_shaper_profile { 991 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 992 uint32_t shaper_profile_id; 993 uint32_t reference_count; 994 struct rte_tm_shaper_params profile; 995 }; 996 997 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 998 999 /* node type of Traffic Manager */ 1000 enum i40e_tm_node_type { 1001 I40E_TM_NODE_TYPE_PORT, 1002 I40E_TM_NODE_TYPE_TC, 1003 I40E_TM_NODE_TYPE_QUEUE, 1004 I40E_TM_NODE_TYPE_MAX, 1005 }; 1006 1007 /* Struct to store Traffic Manager node configuration. */ 1008 struct i40e_tm_node { 1009 TAILQ_ENTRY(i40e_tm_node) node; 1010 uint32_t id; 1011 uint32_t priority; 1012 uint32_t weight; 1013 uint32_t reference_count; 1014 struct i40e_tm_node *parent; 1015 struct i40e_tm_shaper_profile *shaper_profile; 1016 struct rte_tm_node_params params; 1017 }; 1018 1019 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 1020 1021 /* Struct to store all the Traffic Manager configuration. */ 1022 struct i40e_tm_conf { 1023 struct i40e_shaper_profile_list shaper_profile_list; 1024 struct i40e_tm_node *root; /* root node - port */ 1025 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 1026 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 1027 /** 1028 * The number of added TC nodes. 1029 * It should be no more than the TC number of this port. 1030 */ 1031 uint32_t nb_tc_node; 1032 /** 1033 * The number of added queue nodes. 1034 * It should be no more than the queue number of this port. 1035 */ 1036 uint32_t nb_queue_node; 1037 /** 1038 * This flag is used to check if APP can change the TM node 1039 * configuration. 1040 * When it's true, means the configuration is applied to HW, 1041 * APP should not change the configuration. 1042 * As we don't support on-the-fly configuration, when starting 1043 * the port, APP should call the hierarchy_commit API to set this 1044 * flag to true. When stopping the port, this flag should be set 1045 * to false. 1046 */ 1047 bool committed; 1048 }; 1049 1050 enum i40e_new_pctype { 1051 I40E_CUSTOMIZED_GTPC = 0, 1052 I40E_CUSTOMIZED_GTPU_IPV4, 1053 I40E_CUSTOMIZED_GTPU_IPV6, 1054 I40E_CUSTOMIZED_GTPU, 1055 I40E_CUSTOMIZED_IPV4_L2TPV3, 1056 I40E_CUSTOMIZED_IPV6_L2TPV3, 1057 I40E_CUSTOMIZED_ESP_IPV4, 1058 I40E_CUSTOMIZED_ESP_IPV6, 1059 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1060 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1061 I40E_CUSTOMIZED_AH_IPV4, 1062 I40E_CUSTOMIZED_AH_IPV6, 1063 I40E_CUSTOMIZED_MAX, 1064 }; 1065 1066 #define I40E_FILTER_PCTYPE_INVALID 0 1067 struct i40e_customized_pctype { 1068 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1069 uint8_t pctype; /* New pctype value */ 1070 bool valid; /* Check if it's valid */ 1071 }; 1072 1073 struct i40e_rte_flow_rss_conf { 1074 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1075 1076 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1077 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1078 sizeof(uint32_t)]; /**< Hash key. */ 1079 uint16_t queue[ETH_RSS_RETA_SIZE_512]; /**< Queues indices to use. */ 1080 1081 bool symmetric_enable; /**< true, if enable symmetric */ 1082 uint64_t config_pctypes; /**< All PCTYPES with the flow */ 1083 uint64_t inset; /**< input sets */ 1084 1085 uint8_t region_priority; /**< queue region priority */ 1086 uint8_t region_queue_num; /**< region queue number */ 1087 uint16_t region_queue_start; /**< region queue start */ 1088 1089 uint32_t misc_reset_flags; 1090 #define I40E_HASH_FLOW_RESET_FLAG_FUNC 0x01UL 1091 #define I40E_HASH_FLOW_RESET_FLAG_KEY 0x02UL 1092 #define I40E_HASH_FLOW_RESET_FLAG_QUEUE 0x04UL 1093 #define I40E_HASH_FLOW_RESET_FLAG_REGION 0x08UL 1094 1095 /**< All PCTYPES that reset with the flow */ 1096 uint64_t reset_config_pctypes; 1097 /**< Symmetric function should reset on PCTYPES */ 1098 uint64_t reset_symmetric_pctypes; 1099 }; 1100 1101 /* RSS filter list structure */ 1102 struct i40e_rss_filter { 1103 TAILQ_ENTRY(i40e_rss_filter) next; 1104 struct i40e_rte_flow_rss_conf rss_filter_info; 1105 }; 1106 1107 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1108 1109 struct i40e_vf_msg_cfg { 1110 /* maximal VF message during a statistic period */ 1111 uint32_t max_msg; 1112 1113 /* statistic period, in second */ 1114 uint32_t period; 1115 /* 1116 * If message statistics from a VF exceed the maximal limitation, 1117 * the PF will ignore any new message from that VF for 1118 * 'ignor_second' time. 1119 */ 1120 uint32_t ignore_second; 1121 }; 1122 1123 /* 1124 * Structure to store private data specific for PF instance. 1125 */ 1126 struct i40e_pf { 1127 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1128 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1129 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1130 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1131 uint16_t max_num_vsi; 1132 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1133 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1134 1135 struct i40e_hw_port_stats stats_offset; 1136 struct i40e_hw_port_stats stats; 1137 /* internal packet statistics, it should be excluded from the total */ 1138 struct i40e_eth_stats internal_stats_offset; 1139 struct i40e_eth_stats internal_stats; 1140 bool offset_loaded; 1141 1142 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1143 struct rte_ether_addr dev_addr; /* PF device mac address */ 1144 uint64_t flags; /* PF feature flags */ 1145 /* All kinds of queue pair setting for different VSIs */ 1146 struct i40e_pf_vf *vfs; 1147 uint16_t vf_num; 1148 /* Each of below queue pairs should be power of 2 since it's the 1149 precondition after TC configuration applied */ 1150 uint16_t lan_nb_qp_max; 1151 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1152 uint16_t lan_qp_offset; 1153 uint16_t vmdq_nb_qp_max; 1154 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1155 uint16_t vmdq_qp_offset; 1156 uint16_t vf_nb_qp_max; 1157 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1158 uint16_t vf_qp_offset; 1159 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1160 uint16_t fdir_qp_offset; 1161 1162 uint16_t hash_lut_size; /* The size of hash lookup table */ 1163 bool hash_filter_enabled; 1164 uint64_t hash_enabled_queues; 1165 /* input set bits for each pctype */ 1166 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1167 /* store VXLAN UDP ports */ 1168 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1169 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1170 1171 /* VMDQ related info */ 1172 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1173 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1174 struct i40e_vmdq_info *vmdq; 1175 1176 struct i40e_fdir_info fdir; /* flow director info */ 1177 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1178 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1179 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1180 struct i40e_queue_regions queue_region; /* queue region info */ 1181 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1182 struct i40e_mirror_rule_list mirror_list; 1183 uint16_t nb_mirror_rule; /* The number of mirror rules */ 1184 bool floating_veb; /* The flag to use the floating VEB */ 1185 /* The floating enable flag for the specific VF */ 1186 bool floating_veb_list[I40E_MAX_VF]; 1187 struct i40e_flow_list flow_list; 1188 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1189 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1190 bool qinq_replace_flag; /* QINQ filter replace is done */ 1191 /* l4 port flag */ 1192 bool sport_replace_flag; /* Source port replace is done */ 1193 bool dport_replace_flag; /* Destination port replace is done */ 1194 struct i40e_tm_conf tm_conf; 1195 bool support_multi_driver; /* 1 - support multiple driver */ 1196 1197 /* Dynamic Device Personalization */ 1198 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1199 bool esp_support; /* 1 - support ESP SPI */ 1200 /* customer customized pctype */ 1201 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1202 /* Switch Domain Id */ 1203 uint16_t switch_domain_id; 1204 1205 struct i40e_vf_msg_cfg vf_msg_cfg; 1206 uint64_t prev_rx_bytes; 1207 uint64_t prev_tx_bytes; 1208 uint64_t internal_prev_rx_bytes; 1209 uint64_t internal_prev_tx_bytes; 1210 }; 1211 1212 enum pending_msg { 1213 PFMSG_LINK_CHANGE = 0x1, 1214 PFMSG_RESET_IMPENDING = 0x2, 1215 PFMSG_DRIVER_CLOSE = 0x4, 1216 }; 1217 1218 struct i40e_vsi_vlan_pvid_info { 1219 uint16_t on; /* Enable or disable pvid */ 1220 union { 1221 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1222 struct { 1223 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1224 * while 'untagged' will reject untagged packets. 1225 */ 1226 uint8_t tagged; 1227 uint8_t untagged; 1228 } reject; 1229 } config; 1230 }; 1231 1232 struct i40e_vf_rx_queues { 1233 uint64_t rx_dma_addr; 1234 uint32_t rx_ring_len; 1235 uint32_t buff_size; 1236 }; 1237 1238 struct i40e_vf_tx_queues { 1239 uint64_t tx_dma_addr; 1240 uint32_t tx_ring_len; 1241 }; 1242 1243 /* 1244 * Structure to store private data specific for VF instance. 1245 */ 1246 struct i40e_vf { 1247 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 1248 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1249 uint16_t num_queue_pairs; 1250 uint16_t max_pkt_len; /* Maximum packet length */ 1251 bool promisc_unicast_enabled; 1252 bool promisc_multicast_enabled; 1253 1254 rte_spinlock_t cmd_send_lock; 1255 uint32_t version_major; /* Major version number */ 1256 uint32_t version_minor; /* Minor version number */ 1257 uint16_t promisc_flags; /* Promiscuous setting */ 1258 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1259 1260 /* Multicast addrs */ 1261 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; 1262 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1263 1264 /* Event from pf */ 1265 bool dev_closed; 1266 bool link_up; 1267 enum virtchnl_link_speed link_speed; 1268 bool vf_reset; 1269 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1270 int32_t cmd_retval; /* return value of the cmd response from PF */ 1271 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1272 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1273 1274 /* VSI info */ 1275 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1276 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1277 struct i40e_vsi vsi; 1278 uint64_t flags; 1279 }; 1280 1281 #define I40E_MAX_PKT_TYPE 256 1282 #define I40E_FLOW_TYPE_MAX 64 1283 1284 /* 1285 * Structure to store private data for each PF/VF instance. 1286 */ 1287 struct i40e_adapter { 1288 /* Common for both PF and VF */ 1289 struct i40e_hw hw; 1290 1291 /* Specific for PF or VF */ 1292 union { 1293 struct i40e_pf pf; 1294 struct i40e_vf vf; 1295 }; 1296 1297 /* For vector PMD */ 1298 bool rx_bulk_alloc_allowed; 1299 bool rx_vec_allowed; 1300 bool tx_simple_allowed; 1301 bool tx_vec_allowed; 1302 1303 /* For PTP */ 1304 struct rte_timecounter systime_tc; 1305 struct rte_timecounter rx_tstamp_tc; 1306 struct rte_timecounter tx_tstamp_tc; 1307 1308 /* ptype mapping table */ 1309 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1310 /* flow type to pctype mapping table */ 1311 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1312 uint64_t flow_types_mask; 1313 uint64_t pctypes_mask; 1314 1315 /* For RSS reta table update */ 1316 uint8_t rss_reta_updated; 1317 #ifdef RTE_ARCH_X86 1318 bool rx_use_avx2; 1319 bool rx_use_avx512; 1320 bool tx_use_avx2; 1321 bool tx_use_avx512; 1322 #endif 1323 }; 1324 1325 /** 1326 * Strucute to store private data for each VF representor instance 1327 */ 1328 struct i40e_vf_representor { 1329 uint16_t switch_domain_id; 1330 /**< Virtual Function ID */ 1331 uint16_t vf_id; 1332 /**< Virtual Function ID */ 1333 struct i40e_adapter *adapter; 1334 /**< Private data store of assocaiated physical function */ 1335 struct i40e_eth_stats stats_offset; 1336 /**< Zero-point of VF statistics*/ 1337 }; 1338 1339 extern const struct rte_flow_ops i40e_flow_ops; 1340 1341 union i40e_filter_t { 1342 struct rte_eth_ethertype_filter ethertype_filter; 1343 struct i40e_fdir_filter_conf fdir_filter; 1344 struct rte_eth_tunnel_filter_conf tunnel_filter; 1345 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1346 struct i40e_rte_flow_rss_conf rss_conf; 1347 }; 1348 1349 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1350 const struct rte_flow_attr *attr, 1351 const struct rte_flow_item pattern[], 1352 const struct rte_flow_action actions[], 1353 struct rte_flow_error *error, 1354 union i40e_filter_t *filter); 1355 struct i40e_valid_pattern { 1356 enum rte_flow_item_type *items; 1357 parse_filter_t parse_filter; 1358 }; 1359 1360 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1361 int i40e_vsi_release(struct i40e_vsi *vsi); 1362 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1363 enum i40e_vsi_type type, 1364 struct i40e_vsi *uplink_vsi, 1365 uint16_t user_param); 1366 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1367 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1368 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1369 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1370 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1371 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1372 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1373 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1374 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1375 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1376 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1377 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1378 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1379 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1380 struct i40e_vsi_vlan_pvid_info *info); 1381 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1382 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1383 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1384 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1385 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1386 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1387 int i40e_fdir_setup(struct i40e_pf *pf); 1388 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1389 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1390 uint32_t len, 1391 int socket_id); 1392 int i40e_fdir_configure(struct rte_eth_dev *dev); 1393 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1394 void i40e_fdir_teardown(struct i40e_pf *pf); 1395 enum i40e_filter_pctype 1396 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1397 uint16_t flow_type); 1398 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1399 enum i40e_filter_pctype pctype); 1400 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1401 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1402 struct rte_eth_fdir_info *fdir); 1403 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1404 struct rte_eth_fdir_stats *stat); 1405 int i40e_select_filter_input_set(struct i40e_hw *hw, 1406 struct rte_eth_input_set_conf *conf, 1407 enum rte_filter_type filter); 1408 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1409 int i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set, 1410 uint32_t pctype, bool add); 1411 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1412 uint32_t retval, uint8_t *msg, 1413 uint16_t msglen); 1414 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1415 struct rte_eth_rxq_info *qinfo); 1416 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1417 struct rte_eth_txq_info *qinfo); 1418 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1419 struct rte_eth_burst_mode *mode); 1420 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1421 struct rte_eth_burst_mode *mode); 1422 struct i40e_ethertype_filter * 1423 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1424 const struct i40e_ethertype_filter_input *input); 1425 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1426 struct i40e_ethertype_filter_input *input); 1427 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1428 struct i40e_fdir_input *input); 1429 struct i40e_tunnel_filter * 1430 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1431 const struct i40e_tunnel_filter_input *input); 1432 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1433 struct i40e_tunnel_filter_input *input); 1434 uint64_t i40e_get_default_input_set(uint16_t pctype); 1435 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1436 struct rte_eth_ethertype_filter *filter, 1437 bool add); 1438 struct rte_flow * 1439 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1440 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1441 struct rte_flow *flow); 1442 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1443 const struct i40e_fdir_filter_conf *filter, 1444 bool add); 1445 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1446 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1447 uint8_t add); 1448 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1449 struct i40e_tunnel_filter_conf *tunnel_filter, 1450 uint8_t add); 1451 int i40e_fdir_flush(struct rte_eth_dev *dev); 1452 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1453 struct i40e_macvlan_filter *mv_f, 1454 int num, struct rte_ether_addr *addr); 1455 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1456 struct i40e_macvlan_filter *filter, 1457 int total); 1458 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1459 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1460 struct i40e_macvlan_filter *filter, 1461 int total); 1462 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1463 bool is_i40e_supported(struct rte_eth_dev *dev); 1464 bool is_i40evf_supported(struct rte_eth_dev *dev); 1465 void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, 1466 uint8_t enable); 1467 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1468 enum rte_filter_type filter, uint64_t inset); 1469 int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset, 1470 uint32_t *mask, uint8_t nb_elem); 1471 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1472 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1473 void i40e_check_write_global_reg(struct i40e_hw *hw, 1474 uint32_t addr, uint32_t val); 1475 1476 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1477 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1478 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1479 struct i40e_customized_pctype* 1480 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1481 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1482 uint32_t pkg_size, 1483 enum rte_pmd_i40e_package_op op); 1484 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1485 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1486 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1487 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1488 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1489 void i40e_pf_disable_rss(struct i40e_pf *pf); 1490 int i40e_pf_calc_configured_queues_num(struct i40e_pf *pf); 1491 int i40e_pf_reset_rss_reta(struct i40e_pf *pf); 1492 int i40e_pf_reset_rss_key(struct i40e_pf *pf); 1493 int i40e_pf_config_rss(struct i40e_pf *pf); 1494 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1495 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1496 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1497 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1498 1499 #define I40E_DEV_TO_PCI(eth_dev) \ 1500 RTE_DEV_TO_PCI((eth_dev)->device) 1501 1502 /* I40E_DEV_PRIVATE_TO */ 1503 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1504 (&((struct i40e_adapter *)adapter)->pf) 1505 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1506 (&((struct i40e_adapter *)adapter)->hw) 1507 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1508 ((struct i40e_adapter *)adapter) 1509 1510 /* I40EVF_DEV_PRIVATE_TO */ 1511 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1512 (&((struct i40e_adapter *)adapter)->vf) 1513 1514 static inline struct i40e_vsi * 1515 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1516 { 1517 struct i40e_hw *hw; 1518 1519 if (!adapter) 1520 return NULL; 1521 1522 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1523 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1524 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1525 return &vf->vsi; 1526 } else { 1527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1528 return pf->main_vsi; 1529 } 1530 } 1531 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1532 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1533 1534 /* I40E_VSI_TO */ 1535 #define I40E_VSI_TO_HW(vsi) \ 1536 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1537 #define I40E_VSI_TO_PF(vsi) \ 1538 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1539 #define I40E_VSI_TO_VF(vsi) \ 1540 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1541 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1542 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1543 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1544 (&rte_eth_devices[((struct i40e_vsi *)vsi)->adapter->pf.dev_data->port_id]) 1545 1546 /* I40E_PF_TO */ 1547 #define I40E_PF_TO_HW(pf) \ 1548 (&(((struct i40e_pf *)pf)->adapter->hw)) 1549 #define I40E_PF_TO_ADAPTER(pf) \ 1550 ((struct i40e_adapter *)pf->adapter) 1551 1552 /* I40E_VF_TO */ 1553 #define I40E_VF_TO_HW(vf) \ 1554 (&(((struct i40e_vf *)vf)->adapter->hw)) 1555 1556 static inline void 1557 i40e_init_adminq_parameter(struct i40e_hw *hw) 1558 { 1559 hw->aq.num_arq_entries = I40E_AQ_LEN; 1560 hw->aq.num_asq_entries = I40E_AQ_LEN; 1561 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1562 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1563 } 1564 1565 static inline int 1566 i40e_align_floor(int n) 1567 { 1568 if (n == 0) 1569 return 0; 1570 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1571 } 1572 1573 static inline uint16_t 1574 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1575 { 1576 uint16_t interval = 0; 1577 1578 if (is_multi_drv) { 1579 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1580 } else { 1581 if (is_pf) 1582 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1583 else 1584 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1585 } 1586 1587 /* Convert to hardware count, as writing each 1 represents 2 us */ 1588 return interval / 2; 1589 } 1590 1591 #define I40E_VALID_FLOW(flow_type) \ 1592 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1593 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1594 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1595 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1596 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1597 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1598 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1599 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1600 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1601 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1602 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1603 1604 #define I40E_VALID_PCTYPE_X722(pctype) \ 1605 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1606 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1607 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1608 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1609 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1610 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1611 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1612 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1613 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1614 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1615 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1616 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1617 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1618 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1619 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1620 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1621 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1622 1623 #define I40E_VALID_PCTYPE(pctype) \ 1624 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1625 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1626 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1627 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1628 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1629 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1630 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1631 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1632 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1633 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1634 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1635 1636 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1637 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1638 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1639 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1640 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1641 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1642 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1643 1644 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1645 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1646 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1647 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1648 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1649 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1650 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1651 1652 #endif /* _I40E_ETHDEV_H_ */ 1653