1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_time.h> 11 #include <rte_kvargs.h> 12 #include <rte_hash.h> 13 #include <rte_flow.h> 14 #include <rte_flow_driver.h> 15 #include <rte_tm_driver.h> 16 #include "rte_pmd_i40e.h" 17 18 #include "base/i40e_register.h" 19 #include "base/i40e_type.h" 20 #include "base/virtchnl.h" 21 22 #define I40E_VLAN_TAG_SIZE 4 23 24 #define I40E_AQ_LEN 32 25 #define I40E_AQ_BUF_SZ 4096 26 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 27 #define I40E_MAX_Q_PER_TC 64 28 #define I40E_NUM_DESC_DEFAULT 512 29 #define I40E_NUM_DESC_ALIGN 32 30 #define I40E_BUF_SIZE_MIN 1024 31 #define I40E_FRAME_SIZE_MAX 9728 32 #define I40E_TSO_FRAME_SIZE_MAX 262144 33 #define I40E_QUEUE_BASE_ADDR_UNIT 128 34 /* number of VSIs and queue default setting */ 35 #define I40E_MAX_QP_NUM_PER_VF 16 36 #define I40E_DEFAULT_QP_NUM_FDIR 1 37 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 38 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 39 /* Maximun number of MAC addresses */ 40 #define I40E_NUM_MACADDR_MAX 64 41 /* Maximum number of VFs */ 42 #define I40E_MAX_VF 128 43 /*flag of no loopback*/ 44 #define I40E_AQ_LB_MODE_NONE 0x0 45 /* 46 * vlan_id is a 12 bit number. 47 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 48 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 49 * The higher 7 bit val specifies VFTA array index. 50 */ 51 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 52 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 53 54 /* Default TC traffic in case DCB is not enabled */ 55 #define I40E_DEFAULT_TCMAP 0x1 56 #define I40E_FDIR_QUEUE_ID 0 57 58 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 59 #define I40E_VMDQ_POOL_BASE 1 60 61 #define I40E_DEFAULT_RX_FREE_THRESH 32 62 #define I40E_DEFAULT_RX_PTHRESH 8 63 #define I40E_DEFAULT_RX_HTHRESH 8 64 #define I40E_DEFAULT_RX_WTHRESH 0 65 66 #define I40E_DEFAULT_TX_FREE_THRESH 32 67 #define I40E_DEFAULT_TX_PTHRESH 32 68 #define I40E_DEFAULT_TX_HTHRESH 0 69 #define I40E_DEFAULT_TX_WTHRESH 0 70 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 71 72 /* Bit shift and mask */ 73 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 74 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 75 #define I40E_8_BIT_WIDTH CHAR_BIT 76 #define I40E_8_BIT_MASK UINT8_MAX 77 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 78 #define I40E_16_BIT_MASK UINT16_MAX 79 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 80 #define I40E_32_BIT_MASK UINT32_MAX 81 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 82 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 83 84 /* Linux PF host with virtchnl version 1.1 */ 85 #define PF_IS_V11(vf) \ 86 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 87 ((vf)->version_minor == 1)) 88 89 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 90 do { \ 91 uint32_t ori_val; \ 92 struct rte_eth_dev *dev; \ 93 ori_val = I40E_READ_REG((hw), (reg)); \ 94 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \ 95 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 96 (reg)), (value)); \ 97 if (ori_val != value) \ 98 PMD_DRV_LOG(WARNING, \ 99 "i40e device %s changed global " \ 100 "register [0x%08x]. original: 0x%08x, " \ 101 "new: 0x%08x ", \ 102 (dev->device->name), (reg), \ 103 (ori_val), (value)); \ 104 } while (0) 105 106 /* index flex payload per layer */ 107 enum i40e_flxpld_layer_idx { 108 I40E_FLXPLD_L2_IDX = 0, 109 I40E_FLXPLD_L3_IDX = 1, 110 I40E_FLXPLD_L4_IDX = 2, 111 I40E_MAX_FLXPLD_LAYER = 3, 112 }; 113 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 114 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 115 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 116 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 117 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 118 119 /* i40e flags */ 120 #define I40E_FLAG_RSS (1ULL << 0) 121 #define I40E_FLAG_DCB (1ULL << 1) 122 #define I40E_FLAG_VMDQ (1ULL << 2) 123 #define I40E_FLAG_SRIOV (1ULL << 3) 124 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 125 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 126 #define I40E_FLAG_FDIR (1ULL << 6) 127 #define I40E_FLAG_VXLAN (1ULL << 7) 128 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 129 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 130 I40E_FLAG_DCB | \ 131 I40E_FLAG_VMDQ | \ 132 I40E_FLAG_SRIOV | \ 133 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 134 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 135 I40E_FLAG_FDIR | \ 136 I40E_FLAG_VXLAN | \ 137 I40E_FLAG_RSS_AQ_CAPABLE) 138 139 #define I40E_RSS_OFFLOAD_ALL ( \ 140 ETH_RSS_FRAG_IPV4 | \ 141 ETH_RSS_NONFRAG_IPV4_TCP | \ 142 ETH_RSS_NONFRAG_IPV4_UDP | \ 143 ETH_RSS_NONFRAG_IPV4_SCTP | \ 144 ETH_RSS_NONFRAG_IPV4_OTHER | \ 145 ETH_RSS_FRAG_IPV6 | \ 146 ETH_RSS_NONFRAG_IPV6_TCP | \ 147 ETH_RSS_NONFRAG_IPV6_UDP | \ 148 ETH_RSS_NONFRAG_IPV6_SCTP | \ 149 ETH_RSS_NONFRAG_IPV6_OTHER | \ 150 ETH_RSS_L2_PAYLOAD) 151 152 /* All bits of RSS hash enable for X722*/ 153 #define I40E_RSS_HENA_ALL_X722 ( \ 154 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 155 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 158 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 160 I40E_RSS_HENA_ALL) 161 162 /* All bits of RSS hash enable */ 163 #define I40E_RSS_HENA_ALL ( \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 168 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 173 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 175 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 176 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 177 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 178 179 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 180 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 181 182 /* Default queue interrupt throttling time in microseconds */ 183 #define I40E_ITR_INDEX_DEFAULT 0 184 #define I40E_ITR_INDEX_NONE 3 185 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 186 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 187 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 188 /* Special FW support this floating VEB feature */ 189 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 190 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 191 192 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 193 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 194 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 195 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 196 197 #define I40E_RSS_TYPE_NONE 0ULL 198 #define I40E_RSS_TYPE_INVALID 1ULL 199 200 #define I40E_INSET_NONE 0x00000000000000000ULL 201 202 /* bit0 ~ bit 7 */ 203 #define I40E_INSET_DMAC 0x0000000000000001ULL 204 #define I40E_INSET_SMAC 0x0000000000000002ULL 205 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 206 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 207 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 208 209 /* bit 8 ~ bit 15 */ 210 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 211 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 212 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 213 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 214 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 215 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 216 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 217 218 /* bit 16 ~ bit 31 */ 219 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 220 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 221 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 222 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 223 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 224 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 225 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 226 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 227 228 /* bit 32 ~ bit 47, tunnel fields */ 229 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 230 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 231 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 232 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 233 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 234 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 235 236 /* bit 48 ~ bit 55 */ 237 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 238 239 /* bit 56 ~ bit 63, Flex Payload */ 240 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 241 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 242 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 243 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 244 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 245 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 246 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 247 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 248 #define I40E_INSET_FLEX_PAYLOAD \ 249 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 250 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 251 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 252 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 253 254 /* The max bandwidth of i40e is 40Gbps. */ 255 #define I40E_QOS_BW_MAX 40000 256 /* The bandwidth should be the multiple of 50Mbps. */ 257 #define I40E_QOS_BW_GRANULARITY 50 258 /* The min bandwidth weight is 1. */ 259 #define I40E_QOS_BW_WEIGHT_MIN 1 260 /* The max bandwidth weight is 127. */ 261 #define I40E_QOS_BW_WEIGHT_MAX 127 262 /* The max queue region index is 7. */ 263 #define I40E_REGION_MAX_INDEX 7 264 265 #define I40E_MAX_PERCENT 100 266 #define I40E_DEFAULT_DCB_APP_NUM 1 267 #define I40E_DEFAULT_DCB_APP_PRIO 3 268 269 #define I40E_FDIR_PRG_PKT_CNT 128 270 271 /* 272 * Struct to store flow created. 273 */ 274 struct rte_flow { 275 TAILQ_ENTRY(rte_flow) node; 276 enum rte_filter_type filter_type; 277 void *rule; 278 }; 279 280 /** 281 * The overhead from MTU to max frame size. 282 * Considering QinQ packet, the VLAN tag needs to be counted twice. 283 */ 284 #define I40E_ETH_OVERHEAD \ 285 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 286 #define I40E_ETH_MAX_LEN (RTE_ETHER_MTU + I40E_ETH_OVERHEAD) 287 288 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) 289 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) 290 291 struct i40e_adapter; 292 struct rte_pci_driver; 293 294 /** 295 * MAC filter type 296 */ 297 enum i40e_mac_filter_type { 298 I40E_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */ 299 I40E_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */ 300 I40E_MAC_HASH_MATCH, /**< hash match of MAC addr. */ 301 /** hash match of MAC addr and exact match of VLAN ID. */ 302 I40E_MACVLAN_HASH_MATCH, 303 }; 304 305 /** 306 * MAC filter structure 307 */ 308 struct i40e_mac_filter_info { 309 enum i40e_mac_filter_type filter_type; 310 struct rte_ether_addr mac_addr; 311 }; 312 313 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 314 315 /* MAC filter list structure */ 316 struct i40e_mac_filter { 317 TAILQ_ENTRY(i40e_mac_filter) next; 318 struct i40e_mac_filter_info mac_info; 319 }; 320 321 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 322 323 struct i40e_vsi; 324 325 /* VSI list structure */ 326 struct i40e_vsi_list { 327 TAILQ_ENTRY(i40e_vsi_list) list; 328 struct i40e_vsi *vsi; 329 }; 330 331 struct i40e_rx_queue; 332 struct i40e_tx_queue; 333 334 /* Bandwidth limit information */ 335 struct i40e_bw_info { 336 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 337 uint8_t bw_max; /* Max BW limit if enabled */ 338 339 /* Relative credits within same TC with respect to other VSIs or Comps */ 340 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 341 /* Bandwidth limit per TC */ 342 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 343 /* Max bandwidth limit per TC */ 344 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 345 }; 346 347 /* Structure that defines a VEB */ 348 struct i40e_veb { 349 struct i40e_vsi_list_head head; 350 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 351 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 352 uint16_t seid; /* The seid of VEB itself */ 353 uint16_t uplink_seid; /* The uplink seid of this VEB */ 354 uint16_t stats_idx; 355 struct i40e_eth_stats stats; 356 uint8_t enabled_tc; /* The traffic class enabled */ 357 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 358 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 359 }; 360 361 /* i40e MACVLAN filter structure */ 362 struct i40e_macvlan_filter { 363 struct rte_ether_addr macaddr; 364 enum i40e_mac_filter_type filter_type; 365 uint16_t vlan_id; 366 }; 367 368 /* 369 * Structure that defines a VSI, associated with a adapter. 370 */ 371 struct i40e_vsi { 372 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 373 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 374 375 struct i40e_eth_stats eth_stats_offset; 376 struct i40e_eth_stats eth_stats; 377 /* 378 * When drivers loaded, only a default main VSI exists. In case new VSI 379 * needs to add, HW needs to know the layout that VSIs are organized. 380 * Besides that, VSI isan element and can't switch packets, which needs 381 * to add new component VEB to perform switching. So, a new VSI needs 382 * to specify the uplink VSI (Parent VSI) before created. The 383 * uplink VSI will check whether it had a VEB to switch packets. If no, 384 * it will try to create one. Then, uplink VSI will move the new VSI 385 * into its' sib_vsi_list to manage all the downlink VSI. 386 * sib_vsi_list: the VSI list that shared the same uplink VSI. 387 * parent_vsi : the uplink VSI. It's NULL for main VSI. 388 * veb : the VEB associates with the VSI. 389 */ 390 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 391 struct i40e_vsi *parent_vsi; 392 struct i40e_veb *veb; /* Associated veb, could be null */ 393 struct i40e_veb *floating_veb; /* Associated floating veb */ 394 bool offset_loaded; 395 enum i40e_vsi_type type; /* VSI types */ 396 uint16_t vlan_num; /* Total VLAN number */ 397 uint16_t mac_num; /* Total mac number */ 398 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 399 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 400 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 401 uint32_t user_param; 402 uint16_t seid; /* The seid of VSI itself */ 403 uint16_t uplink_seid; /* The uplink seid of this VSI */ 404 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 405 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 406 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 407 uint16_t base_queue; /* The first queue index of this VSI */ 408 /* 409 * The offset to visit VSI related register, assigned by HW when 410 * creating VSI 411 */ 412 uint16_t vsi_id; 413 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 414 uint16_t nb_msix; /* The max number of msix vector */ 415 uint8_t enabled_tc; /* The traffic class enabled */ 416 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 417 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 418 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 419 uint64_t prev_rx_bytes; 420 uint64_t prev_tx_bytes; 421 }; 422 423 struct pool_entry { 424 LIST_ENTRY(pool_entry) next; 425 uint16_t base; 426 uint16_t len; 427 }; 428 429 LIST_HEAD(res_list, pool_entry); 430 431 struct i40e_res_pool_info { 432 uint32_t base; /* Resource start index */ 433 uint32_t num_alloc; /* Allocated resource number */ 434 uint32_t num_free; /* Total available resource number */ 435 struct res_list alloc_list; /* Allocated resource list */ 436 struct res_list free_list; /* Available resource list */ 437 }; 438 439 enum I40E_VF_STATE { 440 I40E_VF_INACTIVE = 0, 441 I40E_VF_INRESET, 442 I40E_VF_ININIT, 443 I40E_VF_ACTIVE, 444 }; 445 446 /* 447 * Structure to store private data for PF host. 448 */ 449 struct i40e_pf_vf { 450 struct i40e_pf *pf; 451 struct i40e_vsi *vsi; 452 enum I40E_VF_STATE state; /* The number of queue pairs available */ 453 uint16_t vf_idx; /* VF index in pf->vfs */ 454 uint16_t lan_nb_qps; /* Actual queues allocated */ 455 uint16_t reset_cnt; /* Total vf reset times */ 456 struct rte_ether_addr mac_addr; /* Default MAC address */ 457 /* version of the virtchnl from VF */ 458 struct virtchnl_version_info version; 459 uint32_t request_caps; /* offload caps requested from VF */ 460 uint64_t num_mdd_events; /* num of mdd events detected */ 461 462 /* 463 * Variables for store the arrival timestamp of VF messages. 464 * If the timestamp of latest message stored at 465 * `msg_timestamps[index % max]` then the timestamp of 466 * earliest message stored at `msg_time[(index + 1) % max]`. 467 * When a new message come, the timestamp of this message 468 * will be stored at `msg_timestamps[(index + 1) % max]` and the 469 * earliest message timestamp is at 470 * `msg_timestamps[(index + 2) % max]` now... 471 */ 472 uint32_t msg_index; 473 uint64_t *msg_timestamps; 474 475 /* cycle of stop ignoring VF message */ 476 uint64_t ignore_end_cycle; 477 }; 478 479 /* 480 * Structure to store private data for flow control. 481 */ 482 struct i40e_fc_conf { 483 uint16_t pause_time; /* Flow control pause timer */ 484 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 485 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 486 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 487 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 488 }; 489 490 /* 491 * Structure to store private data for VMDQ instance 492 */ 493 struct i40e_vmdq_info { 494 struct i40e_pf *pf; 495 struct i40e_vsi *vsi; 496 }; 497 498 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 499 #define I40E_MAX_FLX_SOURCE_OFF 480 500 #define NONUSE_FLX_PIT_DEST_OFF 63 501 #define NONUSE_FLX_PIT_FSIZE 1 502 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 503 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 504 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 505 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 506 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 507 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 508 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 509 NONUSE_FLX_PIT_DEST_OFF : \ 510 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 511 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 512 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 513 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 514 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 515 #define I40E_FDIR_IPv6_TC_OFFSET 20 516 517 /* A structure used to define the input for GTP flow */ 518 struct i40e_gtp_flow { 519 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 520 uint8_t msg_type; /* Message type. */ 521 uint32_t teid; /* TEID in big endian. */ 522 }; 523 524 /* A structure used to define the input for GTP IPV4 flow */ 525 struct i40e_gtp_ipv4_flow { 526 struct i40e_gtp_flow gtp; 527 struct rte_eth_ipv4_flow ip4; 528 }; 529 530 /* A structure used to define the input for GTP IPV6 flow */ 531 struct i40e_gtp_ipv6_flow { 532 struct i40e_gtp_flow gtp; 533 struct rte_eth_ipv6_flow ip6; 534 }; 535 536 /* A structure used to define the input for ESP IPV4 flow */ 537 struct i40e_esp_ipv4_flow { 538 struct rte_eth_ipv4_flow ipv4; 539 uint32_t spi; /* SPI in big endian. */ 540 }; 541 542 /* A structure used to define the input for ESP IPV6 flow */ 543 struct i40e_esp_ipv6_flow { 544 struct rte_eth_ipv6_flow ipv6; 545 uint32_t spi; /* SPI in big endian. */ 546 }; 547 /* A structure used to define the input for ESP IPV4 UDP flow */ 548 struct i40e_esp_ipv4_udp_flow { 549 struct rte_eth_udpv4_flow udp; 550 uint32_t spi; /* SPI in big endian. */ 551 }; 552 553 /* A structure used to define the input for ESP IPV6 UDP flow */ 554 struct i40e_esp_ipv6_udp_flow { 555 struct rte_eth_udpv6_flow udp; 556 uint32_t spi; /* SPI in big endian. */ 557 }; 558 559 /* A structure used to define the input for raw type flow */ 560 struct i40e_raw_flow { 561 uint16_t pctype; 562 void *packet; 563 uint32_t length; 564 }; 565 566 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 567 struct i40e_ipv4_l2tpv3oip_flow { 568 struct rte_eth_ipv4_flow ip4; 569 uint32_t session_id; /* Session ID in big endian. */ 570 }; 571 572 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 573 struct i40e_ipv6_l2tpv3oip_flow { 574 struct rte_eth_ipv6_flow ip6; 575 uint32_t session_id; /* Session ID in big endian. */ 576 }; 577 578 /* A structure used to define the input for l2 dst type flow */ 579 struct i40e_l2_flow { 580 struct rte_ether_addr dst; 581 struct rte_ether_addr src; 582 uint16_t ether_type; /**< Ether type in big endian */ 583 }; 584 585 /* 586 * A union contains the inputs for all types of flow 587 * items in flows need to be in big endian 588 */ 589 union i40e_fdir_flow { 590 struct i40e_l2_flow l2_flow; 591 struct rte_eth_udpv4_flow udp4_flow; 592 struct rte_eth_tcpv4_flow tcp4_flow; 593 struct rte_eth_sctpv4_flow sctp4_flow; 594 struct rte_eth_ipv4_flow ip4_flow; 595 struct rte_eth_udpv6_flow udp6_flow; 596 struct rte_eth_tcpv6_flow tcp6_flow; 597 struct rte_eth_sctpv6_flow sctp6_flow; 598 struct rte_eth_ipv6_flow ipv6_flow; 599 struct i40e_gtp_flow gtp_flow; 600 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 601 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 602 struct i40e_raw_flow raw_flow; 603 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 604 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 605 struct i40e_esp_ipv4_flow esp_ipv4_flow; 606 struct i40e_esp_ipv6_flow esp_ipv6_flow; 607 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 608 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 609 }; 610 611 enum i40e_fdir_ip_type { 612 I40E_FDIR_IPTYPE_IPV4, 613 I40E_FDIR_IPTYPE_IPV6, 614 }; 615 616 /** 617 * Structure to store flex pit for flow diretor. 618 */ 619 struct i40e_fdir_flex_pit { 620 uint8_t src_offset; /* offset in words from the beginning of payload */ 621 uint8_t size; /* size in words */ 622 uint8_t dst_offset; /* offset in words of flexible payload */ 623 }; 624 625 /* A structure used to contain extend input of flow */ 626 struct i40e_fdir_flow_ext { 627 uint16_t vlan_tci; 628 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 629 /* It is filled by the flexible payload to match. */ 630 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN]; 631 uint8_t raw_id; 632 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 633 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 634 bool inner_ip; /* If there is inner ip */ 635 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 636 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 637 bool customized_pctype; /* If customized pctype is used */ 638 bool pkt_template; /* If raw packet template is used */ 639 bool is_udp; /* ipv4|ipv6 udp flow */ 640 enum i40e_flxpld_layer_idx layer_idx; 641 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 642 bool is_flex_flow; 643 }; 644 645 /* A structure used to define the input for a flow director filter entry */ 646 struct i40e_fdir_input { 647 enum i40e_filter_pctype pctype; 648 union i40e_fdir_flow flow; 649 /* Flow fields to match, dependent on flow_type */ 650 struct i40e_fdir_flow_ext flow_ext; 651 /* Additional fields to match */ 652 }; 653 654 /* Behavior will be taken if FDIR match */ 655 enum i40e_fdir_behavior { 656 I40E_FDIR_ACCEPT = 0, 657 I40E_FDIR_REJECT, 658 I40E_FDIR_PASSTHRU, 659 }; 660 661 /* Flow director report status 662 * It defines what will be reported if FDIR entry is matched. 663 */ 664 enum i40e_fdir_status { 665 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 666 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 667 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 668 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 669 }; 670 671 /* A structure used to define an action when match FDIR packet filter. */ 672 struct i40e_fdir_action { 673 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 674 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 675 enum i40e_fdir_status report_status; /* Status report option */ 676 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 677 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 678 * flex bytes start from in flexible payload. 679 */ 680 uint8_t flex_off; 681 }; 682 683 /* A structure used to define the flow director filter entry by filter_ctrl API 684 * It supports RTE_ETH_FILTER_FDIR data representation. 685 */ 686 struct i40e_fdir_filter_conf { 687 uint32_t soft_id; 688 /* ID, an unique value is required when deal with FDIR entry */ 689 struct i40e_fdir_input input; /* Input set */ 690 struct i40e_fdir_action action; /* Action taken when match */ 691 }; 692 693 struct i40e_fdir_flex_mask { 694 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 695 uint8_t nb_bitmask; 696 struct { 697 uint8_t offset; 698 uint16_t mask; 699 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 700 }; 701 702 #define I40E_FILTER_PCTYPE_INVALID 0 703 #define I40E_FILTER_PCTYPE_MAX 64 704 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 705 706 struct i40e_fdir_filter { 707 TAILQ_ENTRY(i40e_fdir_filter) rules; 708 struct i40e_fdir_filter_conf fdir; 709 }; 710 711 /* fdir memory pool entry */ 712 struct i40e_fdir_entry { 713 struct rte_flow flow; 714 uint32_t idx; 715 }; 716 717 /* pre-allocated fdir memory pool */ 718 struct i40e_fdir_flow_pool { 719 /* a bitmap to manage the fdir pool */ 720 struct rte_bitmap *bitmap; 721 /* the size the pool is pf->fdir->fdir_space_size */ 722 struct i40e_fdir_entry *pool; 723 }; 724 725 #define FLOW_TO_FLOW_BITMAP(f) \ 726 container_of((f), struct i40e_fdir_entry, flow) 727 728 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 729 /* 730 * A structure used to define fields of a FDIR related info. 731 */ 732 struct i40e_fdir_info { 733 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 734 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 735 struct i40e_tx_queue *txq; 736 struct i40e_rx_queue *rxq; 737 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 738 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 739 /* 740 * txq available buffer counter, indicates how many available buffers 741 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 742 */ 743 int txq_available_buf_count; 744 745 /* input set bits for each pctype */ 746 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 747 /* 748 * the rule how bytes stream is extracted as flexible payload 749 * for each payload layer, the setting can up to three elements 750 */ 751 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 752 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 753 754 struct i40e_fdir_filter_list fdir_list; 755 struct i40e_fdir_filter **hash_map; 756 struct rte_hash *hash_table; 757 /* An array to store the inserted rules input */ 758 struct i40e_fdir_filter *fdir_filter_array; 759 760 /* 761 * Priority ordering at filter invalidation(destroying a flow) between 762 * "best effort" space and "guaranteed" space. 763 * 764 * 0 = At filter invalidation, the hardware first tries to increment the 765 * "best effort" space. The "guaranteed" space is incremented only when 766 * the global "best effort" space is at it max value or the "best effort" 767 * space of the PF is at its max value. 768 * 1 = At filter invalidation, the hardware first tries to increment its 769 * "guaranteed" space. The "best effort" space is incremented only when 770 * it is already at its max value. 771 */ 772 uint32_t fdir_invalprio; 773 /* the total size of the fdir, this number is the sum of the guaranteed + 774 * shared space 775 */ 776 uint32_t fdir_space_size; 777 /* the actual number of the fdir rules in hardware, initialized as 0 */ 778 uint32_t fdir_actual_cnt; 779 /* the free guaranteed space of the fdir */ 780 uint32_t fdir_guarantee_free_space; 781 /* the fdir total guaranteed space */ 782 uint32_t fdir_guarantee_total_space; 783 /* the pre-allocated pool of the rte_flow */ 784 struct i40e_fdir_flow_pool fdir_flow_pool; 785 786 /* Mark if flex pit and mask is set */ 787 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 788 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 789 790 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */ 791 792 uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER]; 793 }; 794 795 /* Ethertype filter number HW supports */ 796 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 797 798 /* Ethertype filter struct */ 799 struct i40e_ethertype_filter_input { 800 struct rte_ether_addr mac_addr; /* Mac address to match */ 801 uint16_t ether_type; /* Ether type to match */ 802 }; 803 804 struct i40e_ethertype_filter { 805 TAILQ_ENTRY(i40e_ethertype_filter) rules; 806 struct i40e_ethertype_filter_input input; 807 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 808 uint16_t queue; /* Queue assigned to when match */ 809 }; 810 811 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 812 813 struct i40e_ethertype_rule { 814 struct i40e_ethertype_filter_list ethertype_list; 815 struct i40e_ethertype_filter **hash_map; 816 struct rte_hash *hash_table; 817 }; 818 819 /* queue region info */ 820 struct i40e_queue_region_info { 821 /* the region id for this configuration */ 822 uint8_t region_id; 823 /* the start queue index for this region */ 824 uint8_t queue_start_index; 825 /* the total queue number of this queue region */ 826 uint8_t queue_num; 827 /* the total number of user priority for this region */ 828 uint8_t user_priority_num; 829 /* the packet's user priority for this region */ 830 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 831 /* the total number of flowtype for this region */ 832 uint8_t flowtype_num; 833 /** 834 * the pctype or hardware flowtype of packet, 835 * the specific index for each type has been defined 836 * in file i40e_type.h as enum i40e_filter_pctype. 837 */ 838 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 839 }; 840 841 struct i40e_queue_regions { 842 /* the total number of queue region for this port */ 843 uint16_t queue_region_number; 844 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 845 }; 846 847 struct i40e_rss_pattern_info { 848 uint8_t action_flag; 849 uint64_t types; 850 }; 851 852 /* Tunnel filter number HW supports */ 853 #define I40E_MAX_TUNNEL_FILTER_NUM 400 854 855 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 856 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 857 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 858 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 859 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 860 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 861 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 862 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 863 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 864 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 865 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 866 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 867 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 868 #define I40E_AQC_NEW_TR_21 21 869 #define I40E_AQC_NEW_TR_22 22 870 871 enum i40e_tunnel_iptype { 872 I40E_TUNNEL_IPTYPE_IPV4, 873 I40E_TUNNEL_IPTYPE_IPV6, 874 }; 875 876 /* Tunnel filter struct */ 877 struct i40e_tunnel_filter_input { 878 uint8_t outer_mac[6]; /* Outer mac address to match */ 879 uint8_t inner_mac[6]; /* Inner mac address to match */ 880 uint16_t inner_vlan; /* Inner vlan address to match */ 881 enum i40e_tunnel_iptype ip_type; 882 uint16_t flags; /* Filter type flag */ 883 uint32_t tenant_id; /* Tenant id to match */ 884 uint16_t general_fields[32]; /* Big buffer */ 885 }; 886 887 struct i40e_tunnel_filter { 888 TAILQ_ENTRY(i40e_tunnel_filter) rules; 889 struct i40e_tunnel_filter_input input; 890 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 891 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 892 uint16_t queue; /* Queue assigned to when match */ 893 }; 894 895 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 896 897 struct i40e_tunnel_rule { 898 struct i40e_tunnel_filter_list tunnel_list; 899 struct i40e_tunnel_filter **hash_map; 900 struct rte_hash *hash_table; 901 }; 902 903 /** 904 * Tunnel type. 905 */ 906 enum i40e_tunnel_type { 907 I40E_TUNNEL_TYPE_NONE = 0, 908 I40E_TUNNEL_TYPE_VXLAN, 909 I40E_TUNNEL_TYPE_GENEVE, 910 I40E_TUNNEL_TYPE_TEREDO, 911 I40E_TUNNEL_TYPE_NVGRE, 912 I40E_TUNNEL_TYPE_IP_IN_GRE, 913 I40E_L2_TUNNEL_TYPE_E_TAG, 914 I40E_TUNNEL_TYPE_MPLSoUDP, 915 I40E_TUNNEL_TYPE_MPLSoGRE, 916 I40E_TUNNEL_TYPE_QINQ, 917 I40E_TUNNEL_TYPE_GTPC, 918 I40E_TUNNEL_TYPE_GTPU, 919 I40E_TUNNEL_TYPE_ESPoUDP, 920 I40E_TUNNEL_TYPE_ESPoIP, 921 I40E_CLOUD_TYPE_UDP, 922 I40E_CLOUD_TYPE_TCP, 923 I40E_CLOUD_TYPE_SCTP, 924 I40E_TUNNEL_TYPE_MAX, 925 }; 926 927 /** 928 * L4 port type. 929 */ 930 enum i40e_l4_port_type { 931 I40E_L4_PORT_TYPE_SRC = 0, 932 I40E_L4_PORT_TYPE_DST, 933 }; 934 935 /** 936 * Tunneling Packet filter configuration. 937 */ 938 struct i40e_tunnel_filter_conf { 939 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 940 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 941 uint16_t inner_vlan; /**< Inner VLAN to match. */ 942 uint32_t outer_vlan; /**< Outer VLAN to match */ 943 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 944 /** 945 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 946 * is set in filter_type, or inner destination IP address to match 947 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 948 */ 949 union { 950 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 951 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 952 } ip_addr; 953 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 954 uint16_t filter_type; 955 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 956 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 957 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 958 uint16_t queue_id; /**< Queue assigned to if match. */ 959 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 960 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 961 }; 962 963 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 964 #define I40E_MAX_MIRROR_RULES 64 965 /* 966 * Mirror rule structure 967 */ 968 struct i40e_mirror_rule { 969 TAILQ_ENTRY(i40e_mirror_rule) rules; 970 uint8_t rule_type; 971 uint16_t index; /* the sw index of mirror rule */ 972 uint16_t id; /* the rule id assigned by firmware */ 973 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 974 uint16_t num_entries; 975 /* the info stores depend on the rule type. 976 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 977 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 978 */ 979 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 980 }; 981 982 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 983 984 TAILQ_HEAD(i40e_flow_list, rte_flow); 985 986 /* Struct to store Traffic Manager shaper profile. */ 987 struct i40e_tm_shaper_profile { 988 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 989 uint32_t shaper_profile_id; 990 uint32_t reference_count; 991 struct rte_tm_shaper_params profile; 992 }; 993 994 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 995 996 /* node type of Traffic Manager */ 997 enum i40e_tm_node_type { 998 I40E_TM_NODE_TYPE_PORT, 999 I40E_TM_NODE_TYPE_TC, 1000 I40E_TM_NODE_TYPE_QUEUE, 1001 I40E_TM_NODE_TYPE_MAX, 1002 }; 1003 1004 /* Struct to store Traffic Manager node configuration. */ 1005 struct i40e_tm_node { 1006 TAILQ_ENTRY(i40e_tm_node) node; 1007 uint32_t id; 1008 uint32_t priority; 1009 uint32_t weight; 1010 uint32_t reference_count; 1011 struct i40e_tm_node *parent; 1012 struct i40e_tm_shaper_profile *shaper_profile; 1013 struct rte_tm_node_params params; 1014 }; 1015 1016 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 1017 1018 /* Struct to store all the Traffic Manager configuration. */ 1019 struct i40e_tm_conf { 1020 struct i40e_shaper_profile_list shaper_profile_list; 1021 struct i40e_tm_node *root; /* root node - port */ 1022 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 1023 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 1024 /** 1025 * The number of added TC nodes. 1026 * It should be no more than the TC number of this port. 1027 */ 1028 uint32_t nb_tc_node; 1029 /** 1030 * The number of added queue nodes. 1031 * It should be no more than the queue number of this port. 1032 */ 1033 uint32_t nb_queue_node; 1034 /** 1035 * This flag is used to check if APP can change the TM node 1036 * configuration. 1037 * When it's true, means the configuration is applied to HW, 1038 * APP should not change the configuration. 1039 * As we don't support on-the-fly configuration, when starting 1040 * the port, APP should call the hierarchy_commit API to set this 1041 * flag to true. When stopping the port, this flag should be set 1042 * to false. 1043 */ 1044 bool committed; 1045 }; 1046 1047 enum i40e_new_pctype { 1048 I40E_CUSTOMIZED_GTPC = 0, 1049 I40E_CUSTOMIZED_GTPU_IPV4, 1050 I40E_CUSTOMIZED_GTPU_IPV6, 1051 I40E_CUSTOMIZED_GTPU, 1052 I40E_CUSTOMIZED_IPV4_L2TPV3, 1053 I40E_CUSTOMIZED_IPV6_L2TPV3, 1054 I40E_CUSTOMIZED_ESP_IPV4, 1055 I40E_CUSTOMIZED_ESP_IPV6, 1056 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1057 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1058 I40E_CUSTOMIZED_AH_IPV4, 1059 I40E_CUSTOMIZED_AH_IPV6, 1060 I40E_CUSTOMIZED_MAX, 1061 }; 1062 1063 #define I40E_FILTER_PCTYPE_INVALID 0 1064 struct i40e_customized_pctype { 1065 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1066 uint8_t pctype; /* New pctype value */ 1067 bool valid; /* Check if it's valid */ 1068 }; 1069 1070 struct i40e_rte_flow_rss_conf { 1071 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1072 1073 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1074 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1075 sizeof(uint32_t)]; /**< Hash key. */ 1076 uint16_t queue[ETH_RSS_RETA_SIZE_512]; /**< Queues indices to use. */ 1077 1078 bool symmetric_enable; /**< true, if enable symmetric */ 1079 uint64_t config_pctypes; /**< All PCTYPES with the flow */ 1080 uint64_t inset; /**< input sets */ 1081 1082 uint8_t region_priority; /**< queue region priority */ 1083 uint8_t region_queue_num; /**< region queue number */ 1084 uint16_t region_queue_start; /**< region queue start */ 1085 1086 uint32_t misc_reset_flags; 1087 #define I40E_HASH_FLOW_RESET_FLAG_FUNC 0x01UL 1088 #define I40E_HASH_FLOW_RESET_FLAG_KEY 0x02UL 1089 #define I40E_HASH_FLOW_RESET_FLAG_QUEUE 0x04UL 1090 #define I40E_HASH_FLOW_RESET_FLAG_REGION 0x08UL 1091 1092 /**< All PCTYPES that reset with the flow */ 1093 uint64_t reset_config_pctypes; 1094 /**< Symmetric function should reset on PCTYPES */ 1095 uint64_t reset_symmetric_pctypes; 1096 }; 1097 1098 /* RSS filter list structure */ 1099 struct i40e_rss_filter { 1100 TAILQ_ENTRY(i40e_rss_filter) next; 1101 struct i40e_rte_flow_rss_conf rss_filter_info; 1102 }; 1103 1104 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1105 1106 struct i40e_vf_msg_cfg { 1107 /* maximal VF message during a statistic period */ 1108 uint32_t max_msg; 1109 1110 /* statistic period, in second */ 1111 uint32_t period; 1112 /* 1113 * If message statistics from a VF exceed the maximal limitation, 1114 * the PF will ignore any new message from that VF for 1115 * 'ignor_second' time. 1116 */ 1117 uint32_t ignore_second; 1118 }; 1119 1120 /* 1121 * Structure to store private data specific for PF instance. 1122 */ 1123 struct i40e_pf { 1124 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1125 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1126 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1127 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1128 uint16_t max_num_vsi; 1129 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1130 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1131 1132 struct i40e_hw_port_stats stats_offset; 1133 struct i40e_hw_port_stats stats; 1134 /* internal packet statistics, it should be excluded from the total */ 1135 struct i40e_eth_stats internal_stats_offset; 1136 struct i40e_eth_stats internal_stats; 1137 bool offset_loaded; 1138 1139 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1140 struct rte_ether_addr dev_addr; /* PF device mac address */ 1141 uint64_t flags; /* PF feature flags */ 1142 /* All kinds of queue pair setting for different VSIs */ 1143 struct i40e_pf_vf *vfs; 1144 uint16_t vf_num; 1145 /* Each of below queue pairs should be power of 2 since it's the 1146 precondition after TC configuration applied */ 1147 uint16_t lan_nb_qp_max; 1148 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1149 uint16_t lan_qp_offset; 1150 uint16_t vmdq_nb_qp_max; 1151 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1152 uint16_t vmdq_qp_offset; 1153 uint16_t vf_nb_qp_max; 1154 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1155 uint16_t vf_qp_offset; 1156 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1157 uint16_t fdir_qp_offset; 1158 1159 uint16_t hash_lut_size; /* The size of hash lookup table */ 1160 bool hash_filter_enabled; 1161 uint64_t hash_enabled_queues; 1162 /* input set bits for each pctype */ 1163 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1164 /* store VXLAN UDP ports */ 1165 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1166 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1167 1168 /* VMDQ related info */ 1169 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1170 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1171 struct i40e_vmdq_info *vmdq; 1172 1173 struct i40e_fdir_info fdir; /* flow director info */ 1174 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1175 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1176 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1177 struct i40e_queue_regions queue_region; /* queue region info */ 1178 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1179 struct i40e_mirror_rule_list mirror_list; 1180 uint16_t nb_mirror_rule; /* The number of mirror rules */ 1181 bool floating_veb; /* The flag to use the floating VEB */ 1182 /* The floating enable flag for the specific VF */ 1183 bool floating_veb_list[I40E_MAX_VF]; 1184 struct i40e_flow_list flow_list; 1185 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1186 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1187 bool qinq_replace_flag; /* QINQ filter replace is done */ 1188 /* l4 port flag */ 1189 bool sport_replace_flag; /* Source port replace is done */ 1190 bool dport_replace_flag; /* Destination port replace is done */ 1191 struct i40e_tm_conf tm_conf; 1192 bool support_multi_driver; /* 1 - support multiple driver */ 1193 1194 /* Dynamic Device Personalization */ 1195 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1196 bool esp_support; /* 1 - support ESP SPI */ 1197 /* customer customized pctype */ 1198 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1199 /* Switch Domain Id */ 1200 uint16_t switch_domain_id; 1201 1202 struct i40e_vf_msg_cfg vf_msg_cfg; 1203 uint64_t prev_rx_bytes; 1204 uint64_t prev_tx_bytes; 1205 uint64_t internal_prev_rx_bytes; 1206 uint64_t internal_prev_tx_bytes; 1207 }; 1208 1209 enum pending_msg { 1210 PFMSG_LINK_CHANGE = 0x1, 1211 PFMSG_RESET_IMPENDING = 0x2, 1212 PFMSG_DRIVER_CLOSE = 0x4, 1213 }; 1214 1215 struct i40e_vsi_vlan_pvid_info { 1216 uint16_t on; /* Enable or disable pvid */ 1217 union { 1218 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1219 struct { 1220 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1221 * while 'untagged' will reject untagged packets. 1222 */ 1223 uint8_t tagged; 1224 uint8_t untagged; 1225 } reject; 1226 } config; 1227 }; 1228 1229 struct i40e_vf_rx_queues { 1230 uint64_t rx_dma_addr; 1231 uint32_t rx_ring_len; 1232 uint32_t buff_size; 1233 }; 1234 1235 struct i40e_vf_tx_queues { 1236 uint64_t tx_dma_addr; 1237 uint32_t tx_ring_len; 1238 }; 1239 1240 /* 1241 * Structure to store private data specific for VF instance. 1242 */ 1243 struct i40e_vf { 1244 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 1245 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1246 uint16_t num_queue_pairs; 1247 uint16_t max_pkt_len; /* Maximum packet length */ 1248 bool promisc_unicast_enabled; 1249 bool promisc_multicast_enabled; 1250 1251 rte_spinlock_t cmd_send_lock; 1252 uint32_t version_major; /* Major version number */ 1253 uint32_t version_minor; /* Minor version number */ 1254 uint16_t promisc_flags; /* Promiscuous setting */ 1255 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1256 1257 /* Multicast addrs */ 1258 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; 1259 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1260 1261 /* Event from pf */ 1262 bool dev_closed; 1263 bool link_up; 1264 enum virtchnl_link_speed link_speed; 1265 bool vf_reset; 1266 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1267 int32_t cmd_retval; /* return value of the cmd response from PF */ 1268 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1269 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1270 1271 /* VSI info */ 1272 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1273 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1274 struct i40e_vsi vsi; 1275 uint64_t flags; 1276 }; 1277 1278 #define I40E_MAX_PKT_TYPE 256 1279 #define I40E_FLOW_TYPE_MAX 64 1280 1281 /* 1282 * Structure to store private data for each PF/VF instance. 1283 */ 1284 struct i40e_adapter { 1285 /* Common for both PF and VF */ 1286 struct i40e_hw hw; 1287 struct rte_eth_dev *eth_dev; 1288 1289 /* Specific for PF or VF */ 1290 union { 1291 struct i40e_pf pf; 1292 struct i40e_vf vf; 1293 }; 1294 1295 /* For vector PMD */ 1296 bool rx_bulk_alloc_allowed; 1297 bool rx_vec_allowed; 1298 bool tx_simple_allowed; 1299 bool tx_vec_allowed; 1300 1301 /* For PTP */ 1302 struct rte_timecounter systime_tc; 1303 struct rte_timecounter rx_tstamp_tc; 1304 struct rte_timecounter tx_tstamp_tc; 1305 1306 /* ptype mapping table */ 1307 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1308 /* flow type to pctype mapping table */ 1309 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1310 uint64_t flow_types_mask; 1311 uint64_t pctypes_mask; 1312 1313 /* For RSS reta table update */ 1314 uint8_t rss_reta_updated; 1315 }; 1316 1317 /** 1318 * Strucute to store private data for each VF representor instance 1319 */ 1320 struct i40e_vf_representor { 1321 uint16_t switch_domain_id; 1322 /**< Virtual Function ID */ 1323 uint16_t vf_id; 1324 /**< Virtual Function ID */ 1325 struct i40e_adapter *adapter; 1326 /**< Private data store of assocaiated physical function */ 1327 struct i40e_eth_stats stats_offset; 1328 /**< Zero-point of VF statistics*/ 1329 }; 1330 1331 extern const struct rte_flow_ops i40e_flow_ops; 1332 1333 union i40e_filter_t { 1334 struct rte_eth_ethertype_filter ethertype_filter; 1335 struct i40e_fdir_filter_conf fdir_filter; 1336 struct rte_eth_tunnel_filter_conf tunnel_filter; 1337 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1338 struct i40e_rte_flow_rss_conf rss_conf; 1339 }; 1340 1341 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1342 const struct rte_flow_attr *attr, 1343 const struct rte_flow_item pattern[], 1344 const struct rte_flow_action actions[], 1345 struct rte_flow_error *error, 1346 union i40e_filter_t *filter); 1347 struct i40e_valid_pattern { 1348 enum rte_flow_item_type *items; 1349 parse_filter_t parse_filter; 1350 }; 1351 1352 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1353 int i40e_vsi_release(struct i40e_vsi *vsi); 1354 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1355 enum i40e_vsi_type type, 1356 struct i40e_vsi *uplink_vsi, 1357 uint16_t user_param); 1358 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1359 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1360 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1361 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1362 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1363 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1364 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1365 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1366 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1367 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1368 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1369 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1370 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1371 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1372 struct i40e_vsi_vlan_pvid_info *info); 1373 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1374 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1375 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1376 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1377 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1378 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1379 int i40e_fdir_setup(struct i40e_pf *pf); 1380 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1381 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1382 uint32_t len, 1383 int socket_id); 1384 int i40e_fdir_configure(struct rte_eth_dev *dev); 1385 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1386 void i40e_fdir_teardown(struct i40e_pf *pf); 1387 enum i40e_filter_pctype 1388 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1389 uint16_t flow_type); 1390 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1391 enum i40e_filter_pctype pctype); 1392 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1393 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1394 struct rte_eth_fdir_info *fdir); 1395 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1396 struct rte_eth_fdir_stats *stat); 1397 int i40e_select_filter_input_set(struct i40e_hw *hw, 1398 struct rte_eth_input_set_conf *conf, 1399 enum rte_filter_type filter); 1400 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1401 int i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set, 1402 uint32_t pctype, bool add); 1403 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1404 uint32_t retval, uint8_t *msg, 1405 uint16_t msglen); 1406 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1407 struct rte_eth_rxq_info *qinfo); 1408 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1409 struct rte_eth_txq_info *qinfo); 1410 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1411 struct rte_eth_burst_mode *mode); 1412 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1413 struct rte_eth_burst_mode *mode); 1414 struct i40e_ethertype_filter * 1415 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1416 const struct i40e_ethertype_filter_input *input); 1417 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1418 struct i40e_ethertype_filter_input *input); 1419 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1420 struct i40e_fdir_input *input); 1421 struct i40e_tunnel_filter * 1422 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1423 const struct i40e_tunnel_filter_input *input); 1424 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1425 struct i40e_tunnel_filter_input *input); 1426 uint64_t i40e_get_default_input_set(uint16_t pctype); 1427 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1428 struct rte_eth_ethertype_filter *filter, 1429 bool add); 1430 struct rte_flow * 1431 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1432 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1433 struct rte_flow *flow); 1434 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1435 const struct i40e_fdir_filter_conf *filter, 1436 bool add); 1437 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1438 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1439 uint8_t add); 1440 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1441 struct i40e_tunnel_filter_conf *tunnel_filter, 1442 uint8_t add); 1443 int i40e_fdir_flush(struct rte_eth_dev *dev); 1444 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1445 struct i40e_macvlan_filter *mv_f, 1446 int num, struct rte_ether_addr *addr); 1447 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1448 struct i40e_macvlan_filter *filter, 1449 int total); 1450 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1451 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1452 struct i40e_macvlan_filter *filter, 1453 int total); 1454 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1455 bool is_i40e_supported(struct rte_eth_dev *dev); 1456 bool is_i40evf_supported(struct rte_eth_dev *dev); 1457 void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, 1458 uint8_t enable); 1459 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1460 enum rte_filter_type filter, uint64_t inset); 1461 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, 1462 uint8_t nb_elem); 1463 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1464 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1465 void i40e_check_write_global_reg(struct i40e_hw *hw, 1466 uint32_t addr, uint32_t val); 1467 1468 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1469 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1470 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1471 struct i40e_customized_pctype* 1472 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1473 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1474 uint32_t pkg_size, 1475 enum rte_pmd_i40e_package_op op); 1476 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1477 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1478 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1479 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1480 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1481 void i40e_pf_disable_rss(struct i40e_pf *pf); 1482 int i40e_pf_calc_configured_queues_num(struct i40e_pf *pf); 1483 int i40e_pf_reset_rss_reta(struct i40e_pf *pf); 1484 int i40e_pf_reset_rss_key(struct i40e_pf *pf); 1485 int i40e_pf_config_rss(struct i40e_pf *pf); 1486 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1487 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1488 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1489 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1490 1491 #define I40E_DEV_TO_PCI(eth_dev) \ 1492 RTE_DEV_TO_PCI((eth_dev)->device) 1493 1494 /* I40E_DEV_PRIVATE_TO */ 1495 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1496 (&((struct i40e_adapter *)adapter)->pf) 1497 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1498 (&((struct i40e_adapter *)adapter)->hw) 1499 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1500 ((struct i40e_adapter *)adapter) 1501 1502 /* I40EVF_DEV_PRIVATE_TO */ 1503 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1504 (&((struct i40e_adapter *)adapter)->vf) 1505 1506 static inline struct i40e_vsi * 1507 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1508 { 1509 struct i40e_hw *hw; 1510 1511 if (!adapter) 1512 return NULL; 1513 1514 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1515 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1516 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1517 return &vf->vsi; 1518 } else { 1519 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1520 return pf->main_vsi; 1521 } 1522 } 1523 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1524 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1525 1526 /* I40E_VSI_TO */ 1527 #define I40E_VSI_TO_HW(vsi) \ 1528 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1529 #define I40E_VSI_TO_PF(vsi) \ 1530 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1531 #define I40E_VSI_TO_VF(vsi) \ 1532 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1533 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1534 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1535 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1536 (((struct i40e_vsi *)vsi)->adapter->eth_dev) 1537 1538 /* I40E_PF_TO */ 1539 #define I40E_PF_TO_HW(pf) \ 1540 (&(((struct i40e_pf *)pf)->adapter->hw)) 1541 #define I40E_PF_TO_ADAPTER(pf) \ 1542 ((struct i40e_adapter *)pf->adapter) 1543 1544 /* I40E_VF_TO */ 1545 #define I40E_VF_TO_HW(vf) \ 1546 (&(((struct i40e_vf *)vf)->adapter->hw)) 1547 1548 static inline void 1549 i40e_init_adminq_parameter(struct i40e_hw *hw) 1550 { 1551 hw->aq.num_arq_entries = I40E_AQ_LEN; 1552 hw->aq.num_asq_entries = I40E_AQ_LEN; 1553 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1554 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1555 } 1556 1557 static inline int 1558 i40e_align_floor(int n) 1559 { 1560 if (n == 0) 1561 return 0; 1562 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1563 } 1564 1565 static inline uint16_t 1566 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1567 { 1568 uint16_t interval = 0; 1569 1570 if (is_multi_drv) { 1571 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1572 } else { 1573 if (is_pf) 1574 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1575 else 1576 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1577 } 1578 1579 /* Convert to hardware count, as writing each 1 represents 2 us */ 1580 return interval / 2; 1581 } 1582 1583 #define I40E_VALID_FLOW(flow_type) \ 1584 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1585 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1586 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1587 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1588 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1589 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1590 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1591 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1592 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1593 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1594 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1595 1596 #define I40E_VALID_PCTYPE_X722(pctype) \ 1597 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1598 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1599 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1600 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1601 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1602 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1603 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1604 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1605 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1606 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1607 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1608 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1609 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1610 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1611 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1612 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1613 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1614 1615 #define I40E_VALID_PCTYPE(pctype) \ 1616 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1617 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1618 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1619 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1620 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1621 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1622 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1623 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1624 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1625 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1626 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1627 1628 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1629 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1630 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1631 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1632 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1633 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1634 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1635 1636 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1637 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1638 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1639 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1640 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1641 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1642 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1643 1644 #endif /* _I40E_ETHDEV_H_ */ 1645