1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_time.h> 11 #include <rte_kvargs.h> 12 #include <rte_hash.h> 13 #include <rte_flow.h> 14 #include <rte_flow_driver.h> 15 #include <rte_tm_driver.h> 16 #include "rte_pmd_i40e.h" 17 18 #include "base/i40e_register.h" 19 20 #define I40E_VLAN_TAG_SIZE 4 21 22 #define I40E_AQ_LEN 32 23 #define I40E_AQ_BUF_SZ 4096 24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 25 #define I40E_MAX_Q_PER_TC 64 26 #define I40E_NUM_DESC_DEFAULT 512 27 #define I40E_NUM_DESC_ALIGN 32 28 #define I40E_BUF_SIZE_MIN 1024 29 #define I40E_FRAME_SIZE_MAX 9728 30 #define I40E_TSO_FRAME_SIZE_MAX 262144 31 #define I40E_QUEUE_BASE_ADDR_UNIT 128 32 /* number of VSIs and queue default setting */ 33 #define I40E_MAX_QP_NUM_PER_VF 16 34 #define I40E_DEFAULT_QP_NUM_FDIR 1 35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 37 /* Maximun number of MAC addresses */ 38 #define I40E_NUM_MACADDR_MAX 64 39 /* Maximum number of VFs */ 40 #define I40E_MAX_VF 128 41 /*flag of no loopback*/ 42 #define I40E_AQ_LB_MODE_NONE 0x0 43 /* 44 * vlan_id is a 12 bit number. 45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 47 * The higher 7 bit val specifies VFTA array index. 48 */ 49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 51 52 /* Default TC traffic in case DCB is not enabled */ 53 #define I40E_DEFAULT_TCMAP 0x1 54 #define I40E_FDIR_QUEUE_ID 0 55 56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 57 #define I40E_VMDQ_POOL_BASE 1 58 59 #define I40E_DEFAULT_RX_FREE_THRESH 32 60 #define I40E_DEFAULT_RX_PTHRESH 8 61 #define I40E_DEFAULT_RX_HTHRESH 8 62 #define I40E_DEFAULT_RX_WTHRESH 0 63 64 #define I40E_DEFAULT_TX_FREE_THRESH 32 65 #define I40E_DEFAULT_TX_PTHRESH 32 66 #define I40E_DEFAULT_TX_HTHRESH 0 67 #define I40E_DEFAULT_TX_WTHRESH 0 68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 69 70 /* Bit shift and mask */ 71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 73 #define I40E_8_BIT_WIDTH CHAR_BIT 74 #define I40E_8_BIT_MASK UINT8_MAX 75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 76 #define I40E_16_BIT_MASK UINT16_MAX 77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 78 #define I40E_32_BIT_MASK UINT32_MAX 79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 81 82 /* Linux PF host with virtchnl version 1.1 */ 83 #define PF_IS_V11(vf) \ 84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 85 ((vf)->version_minor == 1)) 86 87 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 88 do { \ 89 uint32_t ori_val; \ 90 struct rte_eth_dev *dev; \ 91 ori_val = I40E_READ_REG((hw), (reg)); \ 92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \ 93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 94 (reg)), (value)); \ 95 if (ori_val != value) \ 96 PMD_DRV_LOG(WARNING, \ 97 "i40e device %s changed global " \ 98 "register [0x%08x]. original: 0x%08x, " \ 99 "new: 0x%08x ", \ 100 (dev->device->name), (reg), \ 101 (ori_val), (value)); \ 102 } while (0) 103 104 /* index flex payload per layer */ 105 enum i40e_flxpld_layer_idx { 106 I40E_FLXPLD_L2_IDX = 0, 107 I40E_FLXPLD_L3_IDX = 1, 108 I40E_FLXPLD_L4_IDX = 2, 109 I40E_MAX_FLXPLD_LAYER = 3, 110 }; 111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 116 117 /* i40e flags */ 118 #define I40E_FLAG_RSS (1ULL << 0) 119 #define I40E_FLAG_DCB (1ULL << 1) 120 #define I40E_FLAG_VMDQ (1ULL << 2) 121 #define I40E_FLAG_SRIOV (1ULL << 3) 122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 124 #define I40E_FLAG_FDIR (1ULL << 6) 125 #define I40E_FLAG_VXLAN (1ULL << 7) 126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 127 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 128 I40E_FLAG_DCB | \ 129 I40E_FLAG_VMDQ | \ 130 I40E_FLAG_SRIOV | \ 131 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 132 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 133 I40E_FLAG_FDIR | \ 134 I40E_FLAG_VXLAN | \ 135 I40E_FLAG_RSS_AQ_CAPABLE) 136 137 #define I40E_RSS_OFFLOAD_ALL ( \ 138 ETH_RSS_FRAG_IPV4 | \ 139 ETH_RSS_NONFRAG_IPV4_TCP | \ 140 ETH_RSS_NONFRAG_IPV4_UDP | \ 141 ETH_RSS_NONFRAG_IPV4_SCTP | \ 142 ETH_RSS_NONFRAG_IPV4_OTHER | \ 143 ETH_RSS_FRAG_IPV6 | \ 144 ETH_RSS_NONFRAG_IPV6_TCP | \ 145 ETH_RSS_NONFRAG_IPV6_UDP | \ 146 ETH_RSS_NONFRAG_IPV6_SCTP | \ 147 ETH_RSS_NONFRAG_IPV6_OTHER | \ 148 ETH_RSS_L2_PAYLOAD) 149 150 /* All bits of RSS hash enable for X722*/ 151 #define I40E_RSS_HENA_ALL_X722 ( \ 152 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 153 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 158 I40E_RSS_HENA_ALL) 159 160 /* All bits of RSS hash enable */ 161 #define I40E_RSS_HENA_ALL ( \ 162 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 166 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 171 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 172 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 173 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 175 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 176 177 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 178 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 179 180 /* Default queue interrupt throttling time in microseconds */ 181 #define I40E_ITR_INDEX_DEFAULT 0 182 #define I40E_ITR_INDEX_NONE 3 183 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 184 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 185 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 186 /* Special FW support this floating VEB feature */ 187 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 188 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 189 190 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 191 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 192 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 193 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 194 195 #define I40E_RSS_TYPE_NONE 0ULL 196 #define I40E_RSS_TYPE_INVALID 1ULL 197 198 #define I40E_INSET_NONE 0x00000000000000000ULL 199 200 /* bit0 ~ bit 7 */ 201 #define I40E_INSET_DMAC 0x0000000000000001ULL 202 #define I40E_INSET_SMAC 0x0000000000000002ULL 203 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 204 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 205 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 206 207 /* bit 8 ~ bit 15 */ 208 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 209 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 210 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 211 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 212 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 213 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 214 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 215 216 /* bit 16 ~ bit 31 */ 217 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 218 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 219 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 220 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 221 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 222 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 223 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 224 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 225 226 /* bit 32 ~ bit 47, tunnel fields */ 227 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 228 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 229 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 230 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 231 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 232 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 233 234 /* bit 48 ~ bit 55 */ 235 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 236 237 /* bit 56 ~ bit 63, Flex Payload */ 238 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 239 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 240 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 241 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 242 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 243 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 244 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 245 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 246 #define I40E_INSET_FLEX_PAYLOAD \ 247 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 248 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 249 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 250 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 251 252 /* The max bandwidth of i40e is 40Gbps. */ 253 #define I40E_QOS_BW_MAX 40000 254 /* The bandwidth should be the multiple of 50Mbps. */ 255 #define I40E_QOS_BW_GRANULARITY 50 256 /* The min bandwidth weight is 1. */ 257 #define I40E_QOS_BW_WEIGHT_MIN 1 258 /* The max bandwidth weight is 127. */ 259 #define I40E_QOS_BW_WEIGHT_MAX 127 260 /* The max queue region index is 7. */ 261 #define I40E_REGION_MAX_INDEX 7 262 263 #define I40E_MAX_PERCENT 100 264 #define I40E_DEFAULT_DCB_APP_NUM 1 265 #define I40E_DEFAULT_DCB_APP_PRIO 3 266 267 #define I40E_FDIR_PRG_PKT_CNT 128 268 269 /* 270 * Struct to store flow created. 271 */ 272 struct rte_flow { 273 TAILQ_ENTRY(rte_flow) node; 274 enum rte_filter_type filter_type; 275 void *rule; 276 }; 277 278 /** 279 * The overhead from MTU to max frame size. 280 * Considering QinQ packet, the VLAN tag needs to be counted twice. 281 */ 282 #define I40E_ETH_OVERHEAD \ 283 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 284 285 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) 286 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) 287 288 struct i40e_adapter; 289 struct rte_pci_driver; 290 291 /** 292 * MAC filter type 293 */ 294 enum i40e_mac_filter_type { 295 I40E_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */ 296 I40E_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */ 297 I40E_MAC_HASH_MATCH, /**< hash match of MAC addr. */ 298 /** hash match of MAC addr and exact match of VLAN ID. */ 299 I40E_MACVLAN_HASH_MATCH, 300 }; 301 302 /** 303 * MAC filter structure 304 */ 305 struct i40e_mac_filter_info { 306 enum i40e_mac_filter_type filter_type; 307 struct rte_ether_addr mac_addr; 308 }; 309 310 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 311 312 /* MAC filter list structure */ 313 struct i40e_mac_filter { 314 TAILQ_ENTRY(i40e_mac_filter) next; 315 struct i40e_mac_filter_info mac_info; 316 }; 317 318 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 319 320 struct i40e_vsi; 321 322 /* VSI list structure */ 323 struct i40e_vsi_list { 324 TAILQ_ENTRY(i40e_vsi_list) list; 325 struct i40e_vsi *vsi; 326 }; 327 328 struct i40e_rx_queue; 329 struct i40e_tx_queue; 330 331 /* Bandwidth limit information */ 332 struct i40e_bw_info { 333 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 334 uint8_t bw_max; /* Max BW limit if enabled */ 335 336 /* Relative credits within same TC with respect to other VSIs or Comps */ 337 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 338 /* Bandwidth limit per TC */ 339 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 340 /* Max bandwidth limit per TC */ 341 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 342 }; 343 344 /* Structure that defines a VEB */ 345 struct i40e_veb { 346 struct i40e_vsi_list_head head; 347 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 348 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 349 uint16_t seid; /* The seid of VEB itself */ 350 uint16_t uplink_seid; /* The uplink seid of this VEB */ 351 uint16_t stats_idx; 352 struct i40e_eth_stats stats; 353 uint8_t enabled_tc; /* The traffic class enabled */ 354 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 355 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 356 }; 357 358 /* i40e MACVLAN filter structure */ 359 struct i40e_macvlan_filter { 360 struct rte_ether_addr macaddr; 361 enum i40e_mac_filter_type filter_type; 362 uint16_t vlan_id; 363 }; 364 365 /* 366 * Structure that defines a VSI, associated with a adapter. 367 */ 368 struct i40e_vsi { 369 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 370 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 371 372 struct i40e_eth_stats eth_stats_offset; 373 struct i40e_eth_stats eth_stats; 374 /* 375 * When drivers loaded, only a default main VSI exists. In case new VSI 376 * needs to add, HW needs to know the layout that VSIs are organized. 377 * Besides that, VSI isan element and can't switch packets, which needs 378 * to add new component VEB to perform switching. So, a new VSI needs 379 * to specify the uplink VSI (Parent VSI) before created. The 380 * uplink VSI will check whether it had a VEB to switch packets. If no, 381 * it will try to create one. Then, uplink VSI will move the new VSI 382 * into its' sib_vsi_list to manage all the downlink VSI. 383 * sib_vsi_list: the VSI list that shared the same uplink VSI. 384 * parent_vsi : the uplink VSI. It's NULL for main VSI. 385 * veb : the VEB associates with the VSI. 386 */ 387 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 388 struct i40e_vsi *parent_vsi; 389 struct i40e_veb *veb; /* Associated veb, could be null */ 390 struct i40e_veb *floating_veb; /* Associated floating veb */ 391 bool offset_loaded; 392 enum i40e_vsi_type type; /* VSI types */ 393 uint16_t vlan_num; /* Total VLAN number */ 394 uint16_t mac_num; /* Total mac number */ 395 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 396 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 397 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 398 uint32_t user_param; 399 uint16_t seid; /* The seid of VSI itself */ 400 uint16_t uplink_seid; /* The uplink seid of this VSI */ 401 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 402 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 403 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 404 uint16_t base_queue; /* The first queue index of this VSI */ 405 /* 406 * The offset to visit VSI related register, assigned by HW when 407 * creating VSI 408 */ 409 uint16_t vsi_id; 410 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 411 uint16_t nb_msix; /* The max number of msix vector */ 412 uint8_t enabled_tc; /* The traffic class enabled */ 413 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 414 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 415 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 416 uint64_t prev_rx_bytes; 417 uint64_t prev_tx_bytes; 418 }; 419 420 struct pool_entry { 421 LIST_ENTRY(pool_entry) next; 422 uint16_t base; 423 uint16_t len; 424 }; 425 426 LIST_HEAD(res_list, pool_entry); 427 428 struct i40e_res_pool_info { 429 uint32_t base; /* Resource start index */ 430 uint32_t num_alloc; /* Allocated resource number */ 431 uint32_t num_free; /* Total available resource number */ 432 struct res_list alloc_list; /* Allocated resource list */ 433 struct res_list free_list; /* Available resource list */ 434 }; 435 436 enum I40E_VF_STATE { 437 I40E_VF_INACTIVE = 0, 438 I40E_VF_INRESET, 439 I40E_VF_ININIT, 440 I40E_VF_ACTIVE, 441 }; 442 443 /* 444 * Structure to store private data for PF host. 445 */ 446 struct i40e_pf_vf { 447 struct i40e_pf *pf; 448 struct i40e_vsi *vsi; 449 enum I40E_VF_STATE state; /* The number of queue pairs available */ 450 uint16_t vf_idx; /* VF index in pf->vfs */ 451 uint16_t lan_nb_qps; /* Actual queues allocated */ 452 uint16_t reset_cnt; /* Total vf reset times */ 453 struct rte_ether_addr mac_addr; /* Default MAC address */ 454 /* version of the virtchnl from VF */ 455 struct virtchnl_version_info version; 456 uint32_t request_caps; /* offload caps requested from VF */ 457 uint64_t num_mdd_events; /* num of mdd events detected */ 458 459 /* 460 * Variables for store the arrival timestamp of VF messages. 461 * If the timestamp of latest message stored at 462 * `msg_timestamps[index % max]` then the timestamp of 463 * earliest message stored at `msg_time[(index + 1) % max]`. 464 * When a new message come, the timestamp of this message 465 * will be stored at `msg_timestamps[(index + 1) % max]` and the 466 * earliest message timestamp is at 467 * `msg_timestamps[(index + 2) % max]` now... 468 */ 469 uint32_t msg_index; 470 uint64_t *msg_timestamps; 471 472 /* cycle of stop ignoring VF message */ 473 uint64_t ignore_end_cycle; 474 }; 475 476 /* 477 * Structure to store private data for flow control. 478 */ 479 struct i40e_fc_conf { 480 uint16_t pause_time; /* Flow control pause timer */ 481 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 482 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 483 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 484 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 485 }; 486 487 /* 488 * Structure to store private data for VMDQ instance 489 */ 490 struct i40e_vmdq_info { 491 struct i40e_pf *pf; 492 struct i40e_vsi *vsi; 493 }; 494 495 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 496 #define I40E_MAX_FLX_SOURCE_OFF 480 497 #define NONUSE_FLX_PIT_DEST_OFF 63 498 #define NONUSE_FLX_PIT_FSIZE 1 499 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 500 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 501 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 502 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 503 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 504 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 505 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 506 NONUSE_FLX_PIT_DEST_OFF : \ 507 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 508 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 509 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 510 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 511 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 512 #define I40E_FDIR_IPv6_TC_OFFSET 20 513 514 /* A structure used to define the input for GTP flow */ 515 struct i40e_gtp_flow { 516 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 517 uint8_t msg_type; /* Message type. */ 518 uint32_t teid; /* TEID in big endian. */ 519 }; 520 521 /* A structure used to define the input for GTP IPV4 flow */ 522 struct i40e_gtp_ipv4_flow { 523 struct i40e_gtp_flow gtp; 524 struct rte_eth_ipv4_flow ip4; 525 }; 526 527 /* A structure used to define the input for GTP IPV6 flow */ 528 struct i40e_gtp_ipv6_flow { 529 struct i40e_gtp_flow gtp; 530 struct rte_eth_ipv6_flow ip6; 531 }; 532 533 /* A structure used to define the input for ESP IPV4 flow */ 534 struct i40e_esp_ipv4_flow { 535 struct rte_eth_ipv4_flow ipv4; 536 uint32_t spi; /* SPI in big endian. */ 537 }; 538 539 /* A structure used to define the input for ESP IPV6 flow */ 540 struct i40e_esp_ipv6_flow { 541 struct rte_eth_ipv6_flow ipv6; 542 uint32_t spi; /* SPI in big endian. */ 543 }; 544 /* A structure used to define the input for ESP IPV4 UDP flow */ 545 struct i40e_esp_ipv4_udp_flow { 546 struct rte_eth_udpv4_flow udp; 547 uint32_t spi; /* SPI in big endian. */ 548 }; 549 550 /* A structure used to define the input for ESP IPV6 UDP flow */ 551 struct i40e_esp_ipv6_udp_flow { 552 struct rte_eth_udpv6_flow udp; 553 uint32_t spi; /* SPI in big endian. */ 554 }; 555 556 /* A structure used to define the input for raw type flow */ 557 struct i40e_raw_flow { 558 uint16_t pctype; 559 void *packet; 560 uint32_t length; 561 }; 562 563 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 564 struct i40e_ipv4_l2tpv3oip_flow { 565 struct rte_eth_ipv4_flow ip4; 566 uint32_t session_id; /* Session ID in big endian. */ 567 }; 568 569 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 570 struct i40e_ipv6_l2tpv3oip_flow { 571 struct rte_eth_ipv6_flow ip6; 572 uint32_t session_id; /* Session ID in big endian. */ 573 }; 574 575 /* A structure used to define the input for l2 dst type flow */ 576 struct i40e_l2_flow { 577 struct rte_ether_addr dst; 578 struct rte_ether_addr src; 579 uint16_t ether_type; /**< Ether type in big endian */ 580 }; 581 582 /* 583 * A union contains the inputs for all types of flow 584 * items in flows need to be in big endian 585 */ 586 union i40e_fdir_flow { 587 struct i40e_l2_flow l2_flow; 588 struct rte_eth_udpv4_flow udp4_flow; 589 struct rte_eth_tcpv4_flow tcp4_flow; 590 struct rte_eth_sctpv4_flow sctp4_flow; 591 struct rte_eth_ipv4_flow ip4_flow; 592 struct rte_eth_udpv6_flow udp6_flow; 593 struct rte_eth_tcpv6_flow tcp6_flow; 594 struct rte_eth_sctpv6_flow sctp6_flow; 595 struct rte_eth_ipv6_flow ipv6_flow; 596 struct i40e_gtp_flow gtp_flow; 597 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 598 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 599 struct i40e_raw_flow raw_flow; 600 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 601 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 602 struct i40e_esp_ipv4_flow esp_ipv4_flow; 603 struct i40e_esp_ipv6_flow esp_ipv6_flow; 604 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 605 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 606 }; 607 608 enum i40e_fdir_ip_type { 609 I40E_FDIR_IPTYPE_IPV4, 610 I40E_FDIR_IPTYPE_IPV6, 611 }; 612 613 /** 614 * Structure to store flex pit for flow diretor. 615 */ 616 struct i40e_fdir_flex_pit { 617 uint8_t src_offset; /* offset in words from the beginning of payload */ 618 uint8_t size; /* size in words */ 619 uint8_t dst_offset; /* offset in words of flexible payload */ 620 }; 621 622 /* A structure used to contain extend input of flow */ 623 struct i40e_fdir_flow_ext { 624 uint16_t vlan_tci; 625 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 626 /* It is filled by the flexible payload to match. */ 627 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN]; 628 uint8_t raw_id; 629 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 630 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 631 bool inner_ip; /* If there is inner ip */ 632 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 633 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 634 bool customized_pctype; /* If customized pctype is used */ 635 bool pkt_template; /* If raw packet template is used */ 636 bool is_udp; /* ipv4|ipv6 udp flow */ 637 enum i40e_flxpld_layer_idx layer_idx; 638 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 639 bool is_flex_flow; 640 }; 641 642 /* A structure used to define the input for a flow director filter entry */ 643 struct i40e_fdir_input { 644 enum i40e_filter_pctype pctype; 645 union i40e_fdir_flow flow; 646 /* Flow fields to match, dependent on flow_type */ 647 struct i40e_fdir_flow_ext flow_ext; 648 /* Additional fields to match */ 649 }; 650 651 /* Behavior will be taken if FDIR match */ 652 enum i40e_fdir_behavior { 653 I40E_FDIR_ACCEPT = 0, 654 I40E_FDIR_REJECT, 655 I40E_FDIR_PASSTHRU, 656 }; 657 658 /* Flow director report status 659 * It defines what will be reported if FDIR entry is matched. 660 */ 661 enum i40e_fdir_status { 662 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 663 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 664 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 665 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 666 }; 667 668 /* A structure used to define an action when match FDIR packet filter. */ 669 struct i40e_fdir_action { 670 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 671 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 672 enum i40e_fdir_status report_status; /* Status report option */ 673 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 674 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 675 * flex bytes start from in flexible payload. 676 */ 677 uint8_t flex_off; 678 }; 679 680 /* A structure used to define the flow director filter entry by filter_ctrl API 681 * It supports RTE_ETH_FILTER_FDIR data representation. 682 */ 683 struct i40e_fdir_filter_conf { 684 uint32_t soft_id; 685 /* ID, an unique value is required when deal with FDIR entry */ 686 struct i40e_fdir_input input; /* Input set */ 687 struct i40e_fdir_action action; /* Action taken when match */ 688 }; 689 690 struct i40e_fdir_flex_mask { 691 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 692 uint8_t nb_bitmask; 693 struct { 694 uint8_t offset; 695 uint16_t mask; 696 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 697 }; 698 699 #define I40E_FILTER_PCTYPE_INVALID 0 700 #define I40E_FILTER_PCTYPE_MAX 64 701 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 702 703 struct i40e_fdir_filter { 704 TAILQ_ENTRY(i40e_fdir_filter) rules; 705 struct i40e_fdir_filter_conf fdir; 706 }; 707 708 /* fdir memory pool entry */ 709 struct i40e_fdir_entry { 710 struct rte_flow flow; 711 uint32_t idx; 712 }; 713 714 /* pre-allocated fdir memory pool */ 715 struct i40e_fdir_flow_pool { 716 /* a bitmap to manage the fdir pool */ 717 struct rte_bitmap *bitmap; 718 /* the size the pool is pf->fdir->fdir_space_size */ 719 struct i40e_fdir_entry *pool; 720 }; 721 722 #define FLOW_TO_FLOW_BITMAP(f) \ 723 container_of((f), struct i40e_fdir_entry, flow) 724 725 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 726 /* 727 * A structure used to define fields of a FDIR related info. 728 */ 729 struct i40e_fdir_info { 730 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 731 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 732 struct i40e_tx_queue *txq; 733 struct i40e_rx_queue *rxq; 734 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 735 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 736 /* 737 * txq available buffer counter, indicates how many available buffers 738 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 739 */ 740 int txq_available_buf_count; 741 742 /* input set bits for each pctype */ 743 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 744 /* 745 * the rule how bytes stream is extracted as flexible payload 746 * for each payload layer, the setting can up to three elements 747 */ 748 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 749 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 750 751 struct i40e_fdir_filter_list fdir_list; 752 struct i40e_fdir_filter **hash_map; 753 struct rte_hash *hash_table; 754 /* An array to store the inserted rules input */ 755 struct i40e_fdir_filter *fdir_filter_array; 756 757 /* 758 * Priority ordering at filter invalidation(destroying a flow) between 759 * "best effort" space and "guaranteed" space. 760 * 761 * 0 = At filter invalidation, the hardware first tries to increment the 762 * "best effort" space. The "guaranteed" space is incremented only when 763 * the global "best effort" space is at it max value or the "best effort" 764 * space of the PF is at its max value. 765 * 1 = At filter invalidation, the hardware first tries to increment its 766 * "guaranteed" space. The "best effort" space is incremented only when 767 * it is already at its max value. 768 */ 769 uint32_t fdir_invalprio; 770 /* the total size of the fdir, this number is the sum of the guaranteed + 771 * shared space 772 */ 773 uint32_t fdir_space_size; 774 /* the actual number of the fdir rules in hardware, initialized as 0 */ 775 uint32_t fdir_actual_cnt; 776 /* the free guaranteed space of the fdir */ 777 uint32_t fdir_guarantee_free_space; 778 /* the fdir total guaranteed space */ 779 uint32_t fdir_guarantee_total_space; 780 /* the pre-allocated pool of the rte_flow */ 781 struct i40e_fdir_flow_pool fdir_flow_pool; 782 783 /* Mark if flex pit and mask is set */ 784 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 785 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 786 787 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */ 788 789 uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER]; 790 }; 791 792 /* Ethertype filter number HW supports */ 793 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 794 795 /* Ethertype filter struct */ 796 struct i40e_ethertype_filter_input { 797 struct rte_ether_addr mac_addr; /* Mac address to match */ 798 uint16_t ether_type; /* Ether type to match */ 799 }; 800 801 struct i40e_ethertype_filter { 802 TAILQ_ENTRY(i40e_ethertype_filter) rules; 803 struct i40e_ethertype_filter_input input; 804 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 805 uint16_t queue; /* Queue assigned to when match */ 806 }; 807 808 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 809 810 struct i40e_ethertype_rule { 811 struct i40e_ethertype_filter_list ethertype_list; 812 struct i40e_ethertype_filter **hash_map; 813 struct rte_hash *hash_table; 814 }; 815 816 /* queue region info */ 817 struct i40e_queue_region_info { 818 /* the region id for this configuration */ 819 uint8_t region_id; 820 /* the start queue index for this region */ 821 uint8_t queue_start_index; 822 /* the total queue number of this queue region */ 823 uint8_t queue_num; 824 /* the total number of user priority for this region */ 825 uint8_t user_priority_num; 826 /* the packet's user priority for this region */ 827 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 828 /* the total number of flowtype for this region */ 829 uint8_t flowtype_num; 830 /** 831 * the pctype or hardware flowtype of packet, 832 * the specific index for each type has been defined 833 * in file i40e_type.h as enum i40e_filter_pctype. 834 */ 835 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 836 }; 837 838 struct i40e_queue_regions { 839 /* the total number of queue region for this port */ 840 uint16_t queue_region_number; 841 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 842 }; 843 844 struct i40e_rss_pattern_info { 845 uint8_t action_flag; 846 uint64_t types; 847 }; 848 849 /* Tunnel filter number HW supports */ 850 #define I40E_MAX_TUNNEL_FILTER_NUM 400 851 852 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 853 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 854 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 855 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 856 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 857 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 858 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 859 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 860 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 861 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 862 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 863 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 864 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 865 #define I40E_AQC_NEW_TR_21 21 866 #define I40E_AQC_NEW_TR_22 22 867 868 enum i40e_tunnel_iptype { 869 I40E_TUNNEL_IPTYPE_IPV4, 870 I40E_TUNNEL_IPTYPE_IPV6, 871 }; 872 873 /* Tunnel filter struct */ 874 struct i40e_tunnel_filter_input { 875 uint8_t outer_mac[6]; /* Outer mac address to match */ 876 uint8_t inner_mac[6]; /* Inner mac address to match */ 877 uint16_t inner_vlan; /* Inner vlan address to match */ 878 enum i40e_tunnel_iptype ip_type; 879 uint16_t flags; /* Filter type flag */ 880 uint32_t tenant_id; /* Tenant id to match */ 881 uint16_t general_fields[32]; /* Big buffer */ 882 }; 883 884 struct i40e_tunnel_filter { 885 TAILQ_ENTRY(i40e_tunnel_filter) rules; 886 struct i40e_tunnel_filter_input input; 887 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 888 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 889 uint16_t queue; /* Queue assigned to when match */ 890 }; 891 892 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 893 894 struct i40e_tunnel_rule { 895 struct i40e_tunnel_filter_list tunnel_list; 896 struct i40e_tunnel_filter **hash_map; 897 struct rte_hash *hash_table; 898 }; 899 900 /** 901 * Tunnel type. 902 */ 903 enum i40e_tunnel_type { 904 I40E_TUNNEL_TYPE_NONE = 0, 905 I40E_TUNNEL_TYPE_VXLAN, 906 I40E_TUNNEL_TYPE_GENEVE, 907 I40E_TUNNEL_TYPE_TEREDO, 908 I40E_TUNNEL_TYPE_NVGRE, 909 I40E_TUNNEL_TYPE_IP_IN_GRE, 910 I40E_L2_TUNNEL_TYPE_E_TAG, 911 I40E_TUNNEL_TYPE_MPLSoUDP, 912 I40E_TUNNEL_TYPE_MPLSoGRE, 913 I40E_TUNNEL_TYPE_QINQ, 914 I40E_TUNNEL_TYPE_GTPC, 915 I40E_TUNNEL_TYPE_GTPU, 916 I40E_TUNNEL_TYPE_ESPoUDP, 917 I40E_TUNNEL_TYPE_ESPoIP, 918 I40E_CLOUD_TYPE_UDP, 919 I40E_CLOUD_TYPE_TCP, 920 I40E_CLOUD_TYPE_SCTP, 921 I40E_TUNNEL_TYPE_MAX, 922 }; 923 924 /** 925 * L4 port type. 926 */ 927 enum i40e_l4_port_type { 928 I40E_L4_PORT_TYPE_SRC = 0, 929 I40E_L4_PORT_TYPE_DST, 930 }; 931 932 /** 933 * Tunneling Packet filter configuration. 934 */ 935 struct i40e_tunnel_filter_conf { 936 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 937 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 938 uint16_t inner_vlan; /**< Inner VLAN to match. */ 939 uint32_t outer_vlan; /**< Outer VLAN to match */ 940 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 941 /** 942 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 943 * is set in filter_type, or inner destination IP address to match 944 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 945 */ 946 union { 947 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 948 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 949 } ip_addr; 950 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 951 uint16_t filter_type; 952 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 953 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 954 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 955 uint16_t queue_id; /**< Queue assigned to if match. */ 956 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 957 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 958 }; 959 960 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 961 #define I40E_MAX_MIRROR_RULES 64 962 /* 963 * Mirror rule structure 964 */ 965 struct i40e_mirror_rule { 966 TAILQ_ENTRY(i40e_mirror_rule) rules; 967 uint8_t rule_type; 968 uint16_t index; /* the sw index of mirror rule */ 969 uint16_t id; /* the rule id assigned by firmware */ 970 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 971 uint16_t num_entries; 972 /* the info stores depend on the rule type. 973 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 974 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 975 */ 976 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 977 }; 978 979 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 980 981 TAILQ_HEAD(i40e_flow_list, rte_flow); 982 983 /* Struct to store Traffic Manager shaper profile. */ 984 struct i40e_tm_shaper_profile { 985 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 986 uint32_t shaper_profile_id; 987 uint32_t reference_count; 988 struct rte_tm_shaper_params profile; 989 }; 990 991 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 992 993 /* node type of Traffic Manager */ 994 enum i40e_tm_node_type { 995 I40E_TM_NODE_TYPE_PORT, 996 I40E_TM_NODE_TYPE_TC, 997 I40E_TM_NODE_TYPE_QUEUE, 998 I40E_TM_NODE_TYPE_MAX, 999 }; 1000 1001 /* Struct to store Traffic Manager node configuration. */ 1002 struct i40e_tm_node { 1003 TAILQ_ENTRY(i40e_tm_node) node; 1004 uint32_t id; 1005 uint32_t priority; 1006 uint32_t weight; 1007 uint32_t reference_count; 1008 struct i40e_tm_node *parent; 1009 struct i40e_tm_shaper_profile *shaper_profile; 1010 struct rte_tm_node_params params; 1011 }; 1012 1013 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 1014 1015 /* Struct to store all the Traffic Manager configuration. */ 1016 struct i40e_tm_conf { 1017 struct i40e_shaper_profile_list shaper_profile_list; 1018 struct i40e_tm_node *root; /* root node - port */ 1019 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 1020 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 1021 /** 1022 * The number of added TC nodes. 1023 * It should be no more than the TC number of this port. 1024 */ 1025 uint32_t nb_tc_node; 1026 /** 1027 * The number of added queue nodes. 1028 * It should be no more than the queue number of this port. 1029 */ 1030 uint32_t nb_queue_node; 1031 /** 1032 * This flag is used to check if APP can change the TM node 1033 * configuration. 1034 * When it's true, means the configuration is applied to HW, 1035 * APP should not change the configuration. 1036 * As we don't support on-the-fly configuration, when starting 1037 * the port, APP should call the hierarchy_commit API to set this 1038 * flag to true. When stopping the port, this flag should be set 1039 * to false. 1040 */ 1041 bool committed; 1042 }; 1043 1044 enum i40e_new_pctype { 1045 I40E_CUSTOMIZED_GTPC = 0, 1046 I40E_CUSTOMIZED_GTPU_IPV4, 1047 I40E_CUSTOMIZED_GTPU_IPV6, 1048 I40E_CUSTOMIZED_GTPU, 1049 I40E_CUSTOMIZED_IPV4_L2TPV3, 1050 I40E_CUSTOMIZED_IPV6_L2TPV3, 1051 I40E_CUSTOMIZED_ESP_IPV4, 1052 I40E_CUSTOMIZED_ESP_IPV6, 1053 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1054 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1055 I40E_CUSTOMIZED_AH_IPV4, 1056 I40E_CUSTOMIZED_AH_IPV6, 1057 I40E_CUSTOMIZED_MAX, 1058 }; 1059 1060 #define I40E_FILTER_PCTYPE_INVALID 0 1061 struct i40e_customized_pctype { 1062 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1063 uint8_t pctype; /* New pctype value */ 1064 bool valid; /* Check if it's valid */ 1065 }; 1066 1067 struct i40e_rte_flow_rss_conf { 1068 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1069 uint16_t queue_region_conf; /**< Queue region config flag */ 1070 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1071 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1072 sizeof(uint32_t)]; /* Hash key. */ 1073 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */ 1074 bool valid; /* Check if it's valid */ 1075 }; 1076 1077 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1078 1079 /* RSS filter list structure */ 1080 struct i40e_rss_filter { 1081 TAILQ_ENTRY(i40e_rss_filter) next; 1082 struct i40e_rte_flow_rss_conf rss_filter_info; 1083 }; 1084 1085 struct i40e_vf_msg_cfg { 1086 /* maximal VF message during a statistic period */ 1087 uint32_t max_msg; 1088 1089 /* statistic period, in second */ 1090 uint32_t period; 1091 /* 1092 * If message statistics from a VF exceed the maximal limitation, 1093 * the PF will ignore any new message from that VF for 1094 * 'ignor_second' time. 1095 */ 1096 uint32_t ignore_second; 1097 }; 1098 1099 /* 1100 * Structure to store private data specific for PF instance. 1101 */ 1102 struct i40e_pf { 1103 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1104 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1105 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1106 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1107 uint16_t max_num_vsi; 1108 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1109 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1110 1111 struct i40e_hw_port_stats stats_offset; 1112 struct i40e_hw_port_stats stats; 1113 /* internal packet statistics, it should be excluded from the total */ 1114 struct i40e_eth_stats internal_stats_offset; 1115 struct i40e_eth_stats internal_stats; 1116 bool offset_loaded; 1117 1118 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1119 struct rte_ether_addr dev_addr; /* PF device mac address */ 1120 uint64_t flags; /* PF feature flags */ 1121 /* All kinds of queue pair setting for different VSIs */ 1122 struct i40e_pf_vf *vfs; 1123 uint16_t vf_num; 1124 /* Each of below queue pairs should be power of 2 since it's the 1125 precondition after TC configuration applied */ 1126 uint16_t lan_nb_qp_max; 1127 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1128 uint16_t lan_qp_offset; 1129 uint16_t vmdq_nb_qp_max; 1130 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1131 uint16_t vmdq_qp_offset; 1132 uint16_t vf_nb_qp_max; 1133 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1134 uint16_t vf_qp_offset; 1135 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1136 uint16_t fdir_qp_offset; 1137 1138 uint16_t hash_lut_size; /* The size of hash lookup table */ 1139 /* input set bits for each pctype */ 1140 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1141 /* store VXLAN UDP ports */ 1142 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1143 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1144 1145 /* VMDQ related info */ 1146 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1147 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1148 struct i40e_vmdq_info *vmdq; 1149 1150 struct i40e_fdir_info fdir; /* flow director info */ 1151 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1152 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1153 struct i40e_rte_flow_rss_conf rss_info; /* RSS info */ 1154 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1155 struct i40e_queue_regions queue_region; /* queue region info */ 1156 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1157 struct i40e_mirror_rule_list mirror_list; 1158 uint16_t nb_mirror_rule; /* The number of mirror rules */ 1159 bool floating_veb; /* The flag to use the floating VEB */ 1160 /* The floating enable flag for the specific VF */ 1161 bool floating_veb_list[I40E_MAX_VF]; 1162 struct i40e_flow_list flow_list; 1163 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1164 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1165 bool qinq_replace_flag; /* QINQ filter replace is done */ 1166 /* l4 port flag */ 1167 bool sport_replace_flag; /* Source port replace is done */ 1168 bool dport_replace_flag; /* Destination port replace is done */ 1169 struct i40e_tm_conf tm_conf; 1170 bool support_multi_driver; /* 1 - support multiple driver */ 1171 1172 /* Dynamic Device Personalization */ 1173 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1174 bool esp_support; /* 1 - support ESP SPI */ 1175 /* customer customized pctype */ 1176 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1177 /* Switch Domain Id */ 1178 uint16_t switch_domain_id; 1179 1180 struct i40e_vf_msg_cfg vf_msg_cfg; 1181 uint64_t prev_rx_bytes; 1182 uint64_t prev_tx_bytes; 1183 uint64_t internal_prev_rx_bytes; 1184 uint64_t internal_prev_tx_bytes; 1185 }; 1186 1187 enum pending_msg { 1188 PFMSG_LINK_CHANGE = 0x1, 1189 PFMSG_RESET_IMPENDING = 0x2, 1190 PFMSG_DRIVER_CLOSE = 0x4, 1191 }; 1192 1193 struct i40e_vsi_vlan_pvid_info { 1194 uint16_t on; /* Enable or disable pvid */ 1195 union { 1196 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1197 struct { 1198 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1199 * while 'untagged' will reject untagged packets. 1200 */ 1201 uint8_t tagged; 1202 uint8_t untagged; 1203 } reject; 1204 } config; 1205 }; 1206 1207 struct i40e_vf_rx_queues { 1208 uint64_t rx_dma_addr; 1209 uint32_t rx_ring_len; 1210 uint32_t buff_size; 1211 }; 1212 1213 struct i40e_vf_tx_queues { 1214 uint64_t tx_dma_addr; 1215 uint32_t tx_ring_len; 1216 }; 1217 1218 /* 1219 * Structure to store private data specific for VF instance. 1220 */ 1221 struct i40e_vf { 1222 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 1223 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1224 uint16_t num_queue_pairs; 1225 uint16_t max_pkt_len; /* Maximum packet length */ 1226 bool promisc_unicast_enabled; 1227 bool promisc_multicast_enabled; 1228 1229 rte_spinlock_t cmd_send_lock; 1230 uint32_t version_major; /* Major version number */ 1231 uint32_t version_minor; /* Minor version number */ 1232 uint16_t promisc_flags; /* Promiscuous setting */ 1233 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1234 1235 /* Multicast addrs */ 1236 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; 1237 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1238 1239 /* Event from pf */ 1240 bool dev_closed; 1241 bool link_up; 1242 enum virtchnl_link_speed link_speed; 1243 bool vf_reset; 1244 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1245 int32_t cmd_retval; /* return value of the cmd response from PF */ 1246 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1247 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1248 1249 /* VSI info */ 1250 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1251 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1252 struct i40e_vsi vsi; 1253 uint64_t flags; 1254 }; 1255 1256 #define I40E_MAX_PKT_TYPE 256 1257 #define I40E_FLOW_TYPE_MAX 64 1258 1259 /* 1260 * Structure to store private data for each PF/VF instance. 1261 */ 1262 struct i40e_adapter { 1263 /* Common for both PF and VF */ 1264 struct i40e_hw hw; 1265 struct rte_eth_dev *eth_dev; 1266 1267 /* Specific for PF or VF */ 1268 union { 1269 struct i40e_pf pf; 1270 struct i40e_vf vf; 1271 }; 1272 1273 /* For vector PMD */ 1274 bool rx_bulk_alloc_allowed; 1275 bool rx_vec_allowed; 1276 bool tx_simple_allowed; 1277 bool tx_vec_allowed; 1278 1279 /* For PTP */ 1280 struct rte_timecounter systime_tc; 1281 struct rte_timecounter rx_tstamp_tc; 1282 struct rte_timecounter tx_tstamp_tc; 1283 1284 /* ptype mapping table */ 1285 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1286 /* flow type to pctype mapping table */ 1287 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1288 uint64_t flow_types_mask; 1289 uint64_t pctypes_mask; 1290 1291 /* For devargs */ 1292 uint8_t use_latest_vec; 1293 1294 /* For RSS reta table update */ 1295 uint8_t rss_reta_updated; 1296 }; 1297 1298 /** 1299 * Strucute to store private data for each VF representor instance 1300 */ 1301 struct i40e_vf_representor { 1302 uint16_t switch_domain_id; 1303 /**< Virtual Function ID */ 1304 uint16_t vf_id; 1305 /**< Virtual Function ID */ 1306 struct i40e_adapter *adapter; 1307 /**< Private data store of assocaiated physical function */ 1308 struct i40e_eth_stats stats_offset; 1309 /**< Zero-point of VF statistics*/ 1310 }; 1311 1312 extern const struct rte_flow_ops i40e_flow_ops; 1313 1314 union i40e_filter_t { 1315 struct rte_eth_ethertype_filter ethertype_filter; 1316 struct i40e_fdir_filter_conf fdir_filter; 1317 struct rte_eth_tunnel_filter_conf tunnel_filter; 1318 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1319 struct i40e_rte_flow_rss_conf rss_conf; 1320 }; 1321 1322 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1323 const struct rte_flow_attr *attr, 1324 const struct rte_flow_item pattern[], 1325 const struct rte_flow_action actions[], 1326 struct rte_flow_error *error, 1327 union i40e_filter_t *filter); 1328 struct i40e_valid_pattern { 1329 enum rte_flow_item_type *items; 1330 parse_filter_t parse_filter; 1331 }; 1332 1333 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1334 int i40e_vsi_release(struct i40e_vsi *vsi); 1335 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1336 enum i40e_vsi_type type, 1337 struct i40e_vsi *uplink_vsi, 1338 uint16_t user_param); 1339 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1340 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1341 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1342 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1343 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1344 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1345 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1346 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1347 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1348 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1349 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1350 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1351 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1352 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1353 struct i40e_vsi_vlan_pvid_info *info); 1354 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1355 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1356 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1357 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1358 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1359 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1360 int i40e_fdir_setup(struct i40e_pf *pf); 1361 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1362 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1363 uint32_t len, 1364 int socket_id); 1365 int i40e_fdir_configure(struct rte_eth_dev *dev); 1366 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1367 void i40e_fdir_teardown(struct i40e_pf *pf); 1368 enum i40e_filter_pctype 1369 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1370 uint16_t flow_type); 1371 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1372 enum i40e_filter_pctype pctype); 1373 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1374 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1375 struct rte_eth_fdir_info *fdir); 1376 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1377 struct rte_eth_fdir_stats *stat); 1378 int i40e_select_filter_input_set(struct i40e_hw *hw, 1379 struct rte_eth_input_set_conf *conf, 1380 enum rte_filter_type filter); 1381 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1382 int i40e_hash_filter_inset_select(struct i40e_hw *hw, 1383 struct rte_eth_input_set_conf *conf); 1384 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1385 uint32_t retval, uint8_t *msg, 1386 uint16_t msglen); 1387 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1388 struct rte_eth_rxq_info *qinfo); 1389 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1390 struct rte_eth_txq_info *qinfo); 1391 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1392 struct rte_eth_burst_mode *mode); 1393 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1394 struct rte_eth_burst_mode *mode); 1395 struct i40e_ethertype_filter * 1396 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1397 const struct i40e_ethertype_filter_input *input); 1398 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1399 struct i40e_ethertype_filter_input *input); 1400 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1401 struct i40e_fdir_input *input); 1402 struct i40e_tunnel_filter * 1403 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1404 const struct i40e_tunnel_filter_input *input); 1405 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1406 struct i40e_tunnel_filter_input *input); 1407 uint64_t i40e_get_default_input_set(uint16_t pctype); 1408 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1409 struct rte_eth_ethertype_filter *filter, 1410 bool add); 1411 struct rte_flow * 1412 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1413 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1414 struct rte_flow *flow); 1415 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1416 const struct i40e_fdir_filter_conf *filter, 1417 bool add); 1418 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1419 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1420 uint8_t add); 1421 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1422 struct i40e_tunnel_filter_conf *tunnel_filter, 1423 uint8_t add); 1424 int i40e_fdir_flush(struct rte_eth_dev *dev); 1425 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1426 struct i40e_macvlan_filter *mv_f, 1427 int num, struct rte_ether_addr *addr); 1428 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1429 struct i40e_macvlan_filter *filter, 1430 int total); 1431 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1432 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1433 struct i40e_macvlan_filter *filter, 1434 int total); 1435 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1436 bool is_i40e_supported(struct rte_eth_dev *dev); 1437 bool is_i40evf_supported(struct rte_eth_dev *dev); 1438 1439 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1440 enum rte_filter_type filter, uint64_t inset); 1441 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, 1442 uint8_t nb_elem); 1443 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1444 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1445 void i40e_check_write_global_reg(struct i40e_hw *hw, 1446 uint32_t addr, uint32_t val); 1447 1448 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1449 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1450 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1451 struct i40e_customized_pctype* 1452 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1453 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1454 uint32_t pkg_size, 1455 enum rte_pmd_i40e_package_op op); 1456 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1457 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1458 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1459 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1460 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1461 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1462 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1463 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, 1464 const struct rte_flow_action_rss *in); 1465 int i40e_config_rss_filter(struct i40e_pf *pf, 1466 struct i40e_rte_flow_rss_conf *conf, bool add); 1467 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1468 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1469 1470 #define I40E_DEV_TO_PCI(eth_dev) \ 1471 RTE_DEV_TO_PCI((eth_dev)->device) 1472 1473 /* I40E_DEV_PRIVATE_TO */ 1474 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1475 (&((struct i40e_adapter *)adapter)->pf) 1476 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1477 (&((struct i40e_adapter *)adapter)->hw) 1478 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1479 ((struct i40e_adapter *)adapter) 1480 1481 /* I40EVF_DEV_PRIVATE_TO */ 1482 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1483 (&((struct i40e_adapter *)adapter)->vf) 1484 1485 static inline struct i40e_vsi * 1486 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1487 { 1488 struct i40e_hw *hw; 1489 1490 if (!adapter) 1491 return NULL; 1492 1493 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1494 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1495 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1496 return &vf->vsi; 1497 } else { 1498 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1499 return pf->main_vsi; 1500 } 1501 } 1502 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1503 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1504 1505 /* I40E_VSI_TO */ 1506 #define I40E_VSI_TO_HW(vsi) \ 1507 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1508 #define I40E_VSI_TO_PF(vsi) \ 1509 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1510 #define I40E_VSI_TO_VF(vsi) \ 1511 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1512 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1513 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1514 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1515 (((struct i40e_vsi *)vsi)->adapter->eth_dev) 1516 1517 /* I40E_PF_TO */ 1518 #define I40E_PF_TO_HW(pf) \ 1519 (&(((struct i40e_pf *)pf)->adapter->hw)) 1520 #define I40E_PF_TO_ADAPTER(pf) \ 1521 ((struct i40e_adapter *)pf->adapter) 1522 1523 /* I40E_VF_TO */ 1524 #define I40E_VF_TO_HW(vf) \ 1525 (&(((struct i40e_vf *)vf)->adapter->hw)) 1526 1527 static inline void 1528 i40e_init_adminq_parameter(struct i40e_hw *hw) 1529 { 1530 hw->aq.num_arq_entries = I40E_AQ_LEN; 1531 hw->aq.num_asq_entries = I40E_AQ_LEN; 1532 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1533 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1534 } 1535 1536 static inline int 1537 i40e_align_floor(int n) 1538 { 1539 if (n == 0) 1540 return 0; 1541 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1542 } 1543 1544 static inline uint16_t 1545 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1546 { 1547 uint16_t interval = 0; 1548 1549 if (is_multi_drv) { 1550 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1551 } else { 1552 if (is_pf) 1553 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1554 else 1555 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1556 } 1557 1558 /* Convert to hardware count, as writing each 1 represents 2 us */ 1559 return interval / 2; 1560 } 1561 1562 #define I40E_VALID_FLOW(flow_type) \ 1563 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1564 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1565 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1566 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1567 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1568 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1569 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1570 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1571 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1572 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1573 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1574 1575 #define I40E_VALID_PCTYPE_X722(pctype) \ 1576 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1577 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1578 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1579 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1580 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1581 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1582 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1583 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1584 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1585 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1586 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1587 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1588 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1589 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1590 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1591 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1592 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1593 1594 #define I40E_VALID_PCTYPE(pctype) \ 1595 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1596 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1597 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1598 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1599 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1600 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1601 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1602 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1603 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1604 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1605 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1606 1607 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1608 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1609 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1610 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1611 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1612 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1613 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1614 1615 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1616 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1617 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1618 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1619 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1620 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1621 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1622 1623 #endif /* _I40E_ETHDEV_H_ */ 1624