1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_time.h> 11 #include <rte_kvargs.h> 12 #include <rte_hash.h> 13 #include <rte_flow.h> 14 #include <rte_flow_driver.h> 15 #include <rte_tm_driver.h> 16 #include "rte_pmd_i40e.h" 17 18 #include "base/i40e_register.h" 19 20 #define I40E_VLAN_TAG_SIZE 4 21 22 #define I40E_AQ_LEN 32 23 #define I40E_AQ_BUF_SZ 4096 24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 25 #define I40E_MAX_Q_PER_TC 64 26 #define I40E_NUM_DESC_DEFAULT 512 27 #define I40E_NUM_DESC_ALIGN 32 28 #define I40E_BUF_SIZE_MIN 1024 29 #define I40E_FRAME_SIZE_MAX 9728 30 #define I40E_TSO_FRAME_SIZE_MAX 262144 31 #define I40E_QUEUE_BASE_ADDR_UNIT 128 32 /* number of VSIs and queue default setting */ 33 #define I40E_MAX_QP_NUM_PER_VF 16 34 #define I40E_DEFAULT_QP_NUM_FDIR 1 35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 37 /* Maximun number of MAC addresses */ 38 #define I40E_NUM_MACADDR_MAX 64 39 /* Maximum number of VFs */ 40 #define I40E_MAX_VF 128 41 /*flag of no loopback*/ 42 #define I40E_AQ_LB_MODE_NONE 0x0 43 /* 44 * vlan_id is a 12 bit number. 45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 47 * The higher 7 bit val specifies VFTA array index. 48 */ 49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 51 52 /* Default TC traffic in case DCB is not enabled */ 53 #define I40E_DEFAULT_TCMAP 0x1 54 #define I40E_FDIR_QUEUE_ID 0 55 56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 57 #define I40E_VMDQ_POOL_BASE 1 58 59 #define I40E_DEFAULT_RX_FREE_THRESH 32 60 #define I40E_DEFAULT_RX_PTHRESH 8 61 #define I40E_DEFAULT_RX_HTHRESH 8 62 #define I40E_DEFAULT_RX_WTHRESH 0 63 64 #define I40E_DEFAULT_TX_FREE_THRESH 32 65 #define I40E_DEFAULT_TX_PTHRESH 32 66 #define I40E_DEFAULT_TX_HTHRESH 0 67 #define I40E_DEFAULT_TX_WTHRESH 0 68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 69 70 /* Bit shift and mask */ 71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 73 #define I40E_8_BIT_WIDTH CHAR_BIT 74 #define I40E_8_BIT_MASK UINT8_MAX 75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 76 #define I40E_16_BIT_MASK UINT16_MAX 77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 78 #define I40E_32_BIT_MASK UINT32_MAX 79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 81 82 /* Linux PF host with virtchnl version 1.1 */ 83 #define PF_IS_V11(vf) \ 84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 85 ((vf)->version_minor == 1)) 86 87 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 88 do { \ 89 uint32_t ori_val; \ 90 struct rte_eth_dev *dev; \ 91 ori_val = I40E_READ_REG((hw), (reg)); \ 92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \ 93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 94 (reg)), (value)); \ 95 if (ori_val != value) \ 96 PMD_DRV_LOG(WARNING, \ 97 "i40e device %s changed global " \ 98 "register [0x%08x]. original: 0x%08x, " \ 99 "new: 0x%08x ", \ 100 (dev->device->name), (reg), \ 101 (ori_val), (value)); \ 102 } while (0) 103 104 /* index flex payload per layer */ 105 enum i40e_flxpld_layer_idx { 106 I40E_FLXPLD_L2_IDX = 0, 107 I40E_FLXPLD_L3_IDX = 1, 108 I40E_FLXPLD_L4_IDX = 2, 109 I40E_MAX_FLXPLD_LAYER = 3, 110 }; 111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 116 117 /* i40e flags */ 118 #define I40E_FLAG_RSS (1ULL << 0) 119 #define I40E_FLAG_DCB (1ULL << 1) 120 #define I40E_FLAG_VMDQ (1ULL << 2) 121 #define I40E_FLAG_SRIOV (1ULL << 3) 122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 124 #define I40E_FLAG_FDIR (1ULL << 6) 125 #define I40E_FLAG_VXLAN (1ULL << 7) 126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 127 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 128 I40E_FLAG_DCB | \ 129 I40E_FLAG_VMDQ | \ 130 I40E_FLAG_SRIOV | \ 131 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 132 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 133 I40E_FLAG_FDIR | \ 134 I40E_FLAG_VXLAN | \ 135 I40E_FLAG_RSS_AQ_CAPABLE) 136 137 #define I40E_RSS_OFFLOAD_ALL ( \ 138 ETH_RSS_FRAG_IPV4 | \ 139 ETH_RSS_NONFRAG_IPV4_TCP | \ 140 ETH_RSS_NONFRAG_IPV4_UDP | \ 141 ETH_RSS_NONFRAG_IPV4_SCTP | \ 142 ETH_RSS_NONFRAG_IPV4_OTHER | \ 143 ETH_RSS_FRAG_IPV6 | \ 144 ETH_RSS_NONFRAG_IPV6_TCP | \ 145 ETH_RSS_NONFRAG_IPV6_UDP | \ 146 ETH_RSS_NONFRAG_IPV6_SCTP | \ 147 ETH_RSS_NONFRAG_IPV6_OTHER | \ 148 ETH_RSS_L2_PAYLOAD) 149 150 /* All bits of RSS hash enable for X722*/ 151 #define I40E_RSS_HENA_ALL_X722 ( \ 152 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 153 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 158 I40E_RSS_HENA_ALL) 159 160 /* All bits of RSS hash enable */ 161 #define I40E_RSS_HENA_ALL ( \ 162 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 166 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 171 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 172 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 173 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 175 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 176 177 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 178 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 179 180 /* Default queue interrupt throttling time in microseconds */ 181 #define I40E_ITR_INDEX_DEFAULT 0 182 #define I40E_ITR_INDEX_NONE 3 183 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 184 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 185 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 186 /* Special FW support this floating VEB feature */ 187 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 188 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 189 190 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 191 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 192 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 193 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 194 195 #define I40E_RSS_TYPE_NONE 0ULL 196 #define I40E_RSS_TYPE_INVALID 1ULL 197 198 #define I40E_INSET_NONE 0x00000000000000000ULL 199 200 /* bit0 ~ bit 7 */ 201 #define I40E_INSET_DMAC 0x0000000000000001ULL 202 #define I40E_INSET_SMAC 0x0000000000000002ULL 203 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 204 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 205 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 206 207 /* bit 8 ~ bit 15 */ 208 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 209 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 210 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 211 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 212 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 213 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 214 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 215 216 /* bit 16 ~ bit 31 */ 217 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 218 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 219 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 220 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 221 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 222 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 223 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 224 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 225 226 /* bit 32 ~ bit 47, tunnel fields */ 227 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 228 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 229 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 230 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 231 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 232 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 233 234 /* bit 48 ~ bit 55 */ 235 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 236 237 /* bit 56 ~ bit 63, Flex Payload */ 238 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 239 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 240 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 241 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 242 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 243 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 244 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 245 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 246 #define I40E_INSET_FLEX_PAYLOAD \ 247 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 248 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 249 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 250 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 251 252 /* The max bandwidth of i40e is 40Gbps. */ 253 #define I40E_QOS_BW_MAX 40000 254 /* The bandwidth should be the multiple of 50Mbps. */ 255 #define I40E_QOS_BW_GRANULARITY 50 256 /* The min bandwidth weight is 1. */ 257 #define I40E_QOS_BW_WEIGHT_MIN 1 258 /* The max bandwidth weight is 127. */ 259 #define I40E_QOS_BW_WEIGHT_MAX 127 260 /* The max queue region index is 7. */ 261 #define I40E_REGION_MAX_INDEX 7 262 263 #define I40E_MAX_PERCENT 100 264 #define I40E_DEFAULT_DCB_APP_NUM 1 265 #define I40E_DEFAULT_DCB_APP_PRIO 3 266 267 /** 268 * The overhead from MTU to max frame size. 269 * Considering QinQ packet, the VLAN tag needs to be counted twice. 270 */ 271 #define I40E_ETH_OVERHEAD \ 272 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 273 274 struct i40e_adapter; 275 struct rte_pci_driver; 276 277 /** 278 * MAC filter structure 279 */ 280 struct i40e_mac_filter_info { 281 enum rte_mac_filter_type filter_type; 282 struct rte_ether_addr mac_addr; 283 }; 284 285 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 286 287 /* MAC filter list structure */ 288 struct i40e_mac_filter { 289 TAILQ_ENTRY(i40e_mac_filter) next; 290 struct i40e_mac_filter_info mac_info; 291 }; 292 293 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 294 295 struct i40e_vsi; 296 297 /* VSI list structure */ 298 struct i40e_vsi_list { 299 TAILQ_ENTRY(i40e_vsi_list) list; 300 struct i40e_vsi *vsi; 301 }; 302 303 struct i40e_rx_queue; 304 struct i40e_tx_queue; 305 306 /* Bandwidth limit information */ 307 struct i40e_bw_info { 308 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 309 uint8_t bw_max; /* Max BW limit if enabled */ 310 311 /* Relative credits within same TC with respect to other VSIs or Comps */ 312 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 313 /* Bandwidth limit per TC */ 314 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 315 /* Max bandwidth limit per TC */ 316 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 317 }; 318 319 /* Structure that defines a VEB */ 320 struct i40e_veb { 321 struct i40e_vsi_list_head head; 322 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 323 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 324 uint16_t seid; /* The seid of VEB itself */ 325 uint16_t uplink_seid; /* The uplink seid of this VEB */ 326 uint16_t stats_idx; 327 struct i40e_eth_stats stats; 328 uint8_t enabled_tc; /* The traffic class enabled */ 329 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 330 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 331 }; 332 333 /* i40e MACVLAN filter structure */ 334 struct i40e_macvlan_filter { 335 struct rte_ether_addr macaddr; 336 enum rte_mac_filter_type filter_type; 337 uint16_t vlan_id; 338 }; 339 340 /* 341 * Structure that defines a VSI, associated with a adapter. 342 */ 343 struct i40e_vsi { 344 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 345 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 346 347 struct i40e_eth_stats eth_stats_offset; 348 struct i40e_eth_stats eth_stats; 349 /* 350 * When drivers loaded, only a default main VSI exists. In case new VSI 351 * needs to add, HW needs to know the layout that VSIs are organized. 352 * Besides that, VSI isan element and can't switch packets, which needs 353 * to add new component VEB to perform switching. So, a new VSI needs 354 * to specify the uplink VSI (Parent VSI) before created. The 355 * uplink VSI will check whether it had a VEB to switch packets. If no, 356 * it will try to create one. Then, uplink VSI will move the new VSI 357 * into its' sib_vsi_list to manage all the downlink VSI. 358 * sib_vsi_list: the VSI list that shared the same uplink VSI. 359 * parent_vsi : the uplink VSI. It's NULL for main VSI. 360 * veb : the VEB associates with the VSI. 361 */ 362 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 363 struct i40e_vsi *parent_vsi; 364 struct i40e_veb *veb; /* Associated veb, could be null */ 365 struct i40e_veb *floating_veb; /* Associated floating veb */ 366 bool offset_loaded; 367 enum i40e_vsi_type type; /* VSI types */ 368 uint16_t vlan_num; /* Total VLAN number */ 369 uint16_t mac_num; /* Total mac number */ 370 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 371 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 372 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 373 uint32_t user_param; 374 uint16_t seid; /* The seid of VSI itself */ 375 uint16_t uplink_seid; /* The uplink seid of this VSI */ 376 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 377 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 378 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 379 uint16_t base_queue; /* The first queue index of this VSI */ 380 /* 381 * The offset to visit VSI related register, assigned by HW when 382 * creating VSI 383 */ 384 uint16_t vsi_id; 385 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 386 uint16_t nb_msix; /* The max number of msix vector */ 387 uint8_t enabled_tc; /* The traffic class enabled */ 388 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 389 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 390 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 391 }; 392 393 struct pool_entry { 394 LIST_ENTRY(pool_entry) next; 395 uint16_t base; 396 uint16_t len; 397 }; 398 399 LIST_HEAD(res_list, pool_entry); 400 401 struct i40e_res_pool_info { 402 uint32_t base; /* Resource start index */ 403 uint32_t num_alloc; /* Allocated resource number */ 404 uint32_t num_free; /* Total available resource number */ 405 struct res_list alloc_list; /* Allocated resource list */ 406 struct res_list free_list; /* Available resource list */ 407 }; 408 409 enum I40E_VF_STATE { 410 I40E_VF_INACTIVE = 0, 411 I40E_VF_INRESET, 412 I40E_VF_ININIT, 413 I40E_VF_ACTIVE, 414 }; 415 416 /* 417 * Structure to store private data for PF host. 418 */ 419 struct i40e_pf_vf { 420 struct i40e_pf *pf; 421 struct i40e_vsi *vsi; 422 enum I40E_VF_STATE state; /* The number of queue pairs available */ 423 uint16_t vf_idx; /* VF index in pf->vfs */ 424 uint16_t lan_nb_qps; /* Actual queues allocated */ 425 uint16_t reset_cnt; /* Total vf reset times */ 426 struct rte_ether_addr mac_addr; /* Default MAC address */ 427 /* version of the virtchnl from VF */ 428 struct virtchnl_version_info version; 429 uint32_t request_caps; /* offload caps requested from VF */ 430 uint64_t num_mdd_events; /* num of mdd events detected */ 431 432 /* 433 * Variables for store the arrival timestamp of VF messages. 434 * If the timestamp of latest message stored at 435 * `msg_timestamps[index % max]` then the timestamp of 436 * earliest message stored at `msg_time[(index + 1) % max]`. 437 * When a new message come, the timestamp of this message 438 * will be stored at `msg_timestamps[(index + 1) % max]` and the 439 * earliest message timestamp is at 440 * `msg_timestamps[(index + 2) % max]` now... 441 */ 442 uint32_t msg_index; 443 uint64_t *msg_timestamps; 444 445 /* cycle of stop ignoring VF message */ 446 uint64_t ignore_end_cycle; 447 }; 448 449 /* 450 * Structure to store private data for flow control. 451 */ 452 struct i40e_fc_conf { 453 uint16_t pause_time; /* Flow control pause timer */ 454 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 455 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 456 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 457 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 458 }; 459 460 /* 461 * Structure to store private data for VMDQ instance 462 */ 463 struct i40e_vmdq_info { 464 struct i40e_pf *pf; 465 struct i40e_vsi *vsi; 466 }; 467 468 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 469 #define I40E_MAX_FLX_SOURCE_OFF 480 470 #define NONUSE_FLX_PIT_DEST_OFF 63 471 #define NONUSE_FLX_PIT_FSIZE 1 472 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 473 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 474 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 475 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 476 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 477 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 478 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 479 NONUSE_FLX_PIT_DEST_OFF : \ 480 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 481 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 482 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 483 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 484 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 485 #define I40E_FDIR_IPv6_TC_OFFSET 20 486 487 /* A structure used to define the input for GTP flow */ 488 struct i40e_gtp_flow { 489 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 490 uint8_t msg_type; /* Message type. */ 491 uint32_t teid; /* TEID in big endian. */ 492 }; 493 494 /* A structure used to define the input for GTP IPV4 flow */ 495 struct i40e_gtp_ipv4_flow { 496 struct i40e_gtp_flow gtp; 497 struct rte_eth_ipv4_flow ip4; 498 }; 499 500 /* A structure used to define the input for GTP IPV6 flow */ 501 struct i40e_gtp_ipv6_flow { 502 struct i40e_gtp_flow gtp; 503 struct rte_eth_ipv6_flow ip6; 504 }; 505 506 /* A structure used to define the input for ESP IPV4 flow */ 507 struct i40e_esp_ipv4_flow { 508 struct rte_eth_ipv4_flow ipv4; 509 uint32_t spi; /* SPI in big endian. */ 510 }; 511 512 /* A structure used to define the input for ESP IPV6 flow */ 513 struct i40e_esp_ipv6_flow { 514 struct rte_eth_ipv6_flow ipv6; 515 uint32_t spi; /* SPI in big endian. */ 516 }; 517 /* A structure used to define the input for ESP IPV4 UDP flow */ 518 struct i40e_esp_ipv4_udp_flow { 519 struct rte_eth_udpv4_flow udp; 520 uint32_t spi; /* SPI in big endian. */ 521 }; 522 523 /* A structure used to define the input for ESP IPV6 UDP flow */ 524 struct i40e_esp_ipv6_udp_flow { 525 struct rte_eth_udpv6_flow udp; 526 uint32_t spi; /* SPI in big endian. */ 527 }; 528 529 /* A structure used to define the input for raw type flow */ 530 struct i40e_raw_flow { 531 uint16_t pctype; 532 void *packet; 533 uint32_t length; 534 }; 535 536 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 537 struct i40e_ipv4_l2tpv3oip_flow { 538 struct rte_eth_ipv4_flow ip4; 539 uint32_t session_id; /* Session ID in big endian. */ 540 }; 541 542 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 543 struct i40e_ipv6_l2tpv3oip_flow { 544 struct rte_eth_ipv6_flow ip6; 545 uint32_t session_id; /* Session ID in big endian. */ 546 }; 547 548 /* A structure used to define the input for l2 dst type flow */ 549 struct i40e_l2_flow { 550 struct rte_ether_addr dst; 551 struct rte_ether_addr src; 552 uint16_t ether_type; /**< Ether type in big endian */ 553 }; 554 555 /* 556 * A union contains the inputs for all types of flow 557 * items in flows need to be in big endian 558 */ 559 union i40e_fdir_flow { 560 struct i40e_l2_flow l2_flow; 561 struct rte_eth_udpv4_flow udp4_flow; 562 struct rte_eth_tcpv4_flow tcp4_flow; 563 struct rte_eth_sctpv4_flow sctp4_flow; 564 struct rte_eth_ipv4_flow ip4_flow; 565 struct rte_eth_udpv6_flow udp6_flow; 566 struct rte_eth_tcpv6_flow tcp6_flow; 567 struct rte_eth_sctpv6_flow sctp6_flow; 568 struct rte_eth_ipv6_flow ipv6_flow; 569 struct i40e_gtp_flow gtp_flow; 570 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 571 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 572 struct i40e_raw_flow raw_flow; 573 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 574 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 575 struct i40e_esp_ipv4_flow esp_ipv4_flow; 576 struct i40e_esp_ipv6_flow esp_ipv6_flow; 577 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 578 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 579 }; 580 581 enum i40e_fdir_ip_type { 582 I40E_FDIR_IPTYPE_IPV4, 583 I40E_FDIR_IPTYPE_IPV6, 584 }; 585 586 /* A structure used to contain extend input of flow */ 587 struct i40e_fdir_flow_ext { 588 uint16_t vlan_tci; 589 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 590 /* It is filled by the flexible payload to match. */ 591 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 592 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 593 bool inner_ip; /* If there is inner ip */ 594 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 595 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 596 bool customized_pctype; /* If customized pctype is used */ 597 bool pkt_template; /* If raw packet template is used */ 598 bool is_udp; /* ipv4|ipv6 udp flow */ 599 }; 600 601 /* A structure used to define the input for a flow director filter entry */ 602 struct i40e_fdir_input { 603 enum i40e_filter_pctype pctype; 604 union i40e_fdir_flow flow; 605 /* Flow fields to match, dependent on flow_type */ 606 struct i40e_fdir_flow_ext flow_ext; 607 /* Additional fields to match */ 608 }; 609 610 /* Behavior will be taken if FDIR match */ 611 enum i40e_fdir_behavior { 612 I40E_FDIR_ACCEPT = 0, 613 I40E_FDIR_REJECT, 614 I40E_FDIR_PASSTHRU, 615 }; 616 617 /* Flow director report status 618 * It defines what will be reported if FDIR entry is matched. 619 */ 620 enum i40e_fdir_status { 621 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 622 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 623 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 624 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 625 }; 626 627 /* A structure used to define an action when match FDIR packet filter. */ 628 struct i40e_fdir_action { 629 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 630 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 631 enum i40e_fdir_status report_status; /* Status report option */ 632 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 633 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 634 * flex bytes start from in flexible payload. 635 */ 636 uint8_t flex_off; 637 }; 638 639 /* A structure used to define the flow director filter entry by filter_ctrl API 640 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and 641 * RTE_ETH_FILTER_DELETE operations. 642 */ 643 struct i40e_fdir_filter_conf { 644 uint32_t soft_id; 645 /* ID, an unique value is required when deal with FDIR entry */ 646 struct i40e_fdir_input input; /* Input set */ 647 struct i40e_fdir_action action; /* Action taken when match */ 648 }; 649 650 /* 651 * Structure to store flex pit for flow diretor. 652 */ 653 struct i40e_fdir_flex_pit { 654 uint8_t src_offset; /* offset in words from the beginning of payload */ 655 uint8_t size; /* size in words */ 656 uint8_t dst_offset; /* offset in words of flexible payload */ 657 }; 658 659 struct i40e_fdir_flex_mask { 660 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 661 uint8_t nb_bitmask; 662 struct { 663 uint8_t offset; 664 uint16_t mask; 665 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 666 }; 667 668 #define I40E_FILTER_PCTYPE_INVALID 0 669 #define I40E_FILTER_PCTYPE_MAX 64 670 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 671 672 struct i40e_fdir_filter { 673 TAILQ_ENTRY(i40e_fdir_filter) rules; 674 struct i40e_fdir_filter_conf fdir; 675 }; 676 677 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 678 /* 679 * A structure used to define fields of a FDIR related info. 680 */ 681 struct i40e_fdir_info { 682 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 683 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 684 struct i40e_tx_queue *txq; 685 struct i40e_rx_queue *rxq; 686 void *prg_pkt; /* memory for fdir program packet */ 687 uint64_t dma_addr; /* physic address of packet memory*/ 688 /* input set bits for each pctype */ 689 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 690 /* 691 * the rule how bytes stream is extracted as flexible payload 692 * for each payload layer, the setting can up to three elements 693 */ 694 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 695 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 696 697 struct i40e_fdir_filter_list fdir_list; 698 struct i40e_fdir_filter **hash_map; 699 struct rte_hash *hash_table; 700 701 /* Mark if flex pit and mask is set */ 702 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 703 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 704 705 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */ 706 }; 707 708 /* Ethertype filter number HW supports */ 709 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 710 711 /* Ethertype filter struct */ 712 struct i40e_ethertype_filter_input { 713 struct rte_ether_addr mac_addr; /* Mac address to match */ 714 uint16_t ether_type; /* Ether type to match */ 715 }; 716 717 struct i40e_ethertype_filter { 718 TAILQ_ENTRY(i40e_ethertype_filter) rules; 719 struct i40e_ethertype_filter_input input; 720 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 721 uint16_t queue; /* Queue assigned to when match */ 722 }; 723 724 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 725 726 struct i40e_ethertype_rule { 727 struct i40e_ethertype_filter_list ethertype_list; 728 struct i40e_ethertype_filter **hash_map; 729 struct rte_hash *hash_table; 730 }; 731 732 /* queue region info */ 733 struct i40e_queue_region_info { 734 /* the region id for this configuration */ 735 uint8_t region_id; 736 /* the start queue index for this region */ 737 uint8_t queue_start_index; 738 /* the total queue number of this queue region */ 739 uint8_t queue_num; 740 /* the total number of user priority for this region */ 741 uint8_t user_priority_num; 742 /* the packet's user priority for this region */ 743 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 744 /* the total number of flowtype for this region */ 745 uint8_t flowtype_num; 746 /** 747 * the pctype or hardware flowtype of packet, 748 * the specific index for each type has been defined 749 * in file i40e_type.h as enum i40e_filter_pctype. 750 */ 751 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 752 }; 753 754 struct i40e_queue_regions { 755 /* the total number of queue region for this port */ 756 uint16_t queue_region_number; 757 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 758 }; 759 760 struct i40e_rss_pattern_info { 761 uint8_t action_flag; 762 uint64_t types; 763 }; 764 765 /* Tunnel filter number HW supports */ 766 #define I40E_MAX_TUNNEL_FILTER_NUM 400 767 768 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 769 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 770 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 771 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 772 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 773 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 774 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 775 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 776 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 777 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 778 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 779 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 780 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 781 #define I40E_AQC_NEW_TR_21 21 782 #define I40E_AQC_NEW_TR_22 22 783 784 enum i40e_tunnel_iptype { 785 I40E_TUNNEL_IPTYPE_IPV4, 786 I40E_TUNNEL_IPTYPE_IPV6, 787 }; 788 789 /* Tunnel filter struct */ 790 struct i40e_tunnel_filter_input { 791 uint8_t outer_mac[6]; /* Outer mac address to match */ 792 uint8_t inner_mac[6]; /* Inner mac address to match */ 793 uint16_t inner_vlan; /* Inner vlan address to match */ 794 enum i40e_tunnel_iptype ip_type; 795 uint16_t flags; /* Filter type flag */ 796 uint32_t tenant_id; /* Tenant id to match */ 797 uint16_t general_fields[32]; /* Big buffer */ 798 }; 799 800 struct i40e_tunnel_filter { 801 TAILQ_ENTRY(i40e_tunnel_filter) rules; 802 struct i40e_tunnel_filter_input input; 803 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 804 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 805 uint16_t queue; /* Queue assigned to when match */ 806 }; 807 808 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 809 810 struct i40e_tunnel_rule { 811 struct i40e_tunnel_filter_list tunnel_list; 812 struct i40e_tunnel_filter **hash_map; 813 struct rte_hash *hash_table; 814 }; 815 816 /** 817 * Tunnel type. 818 */ 819 enum i40e_tunnel_type { 820 I40E_TUNNEL_TYPE_NONE = 0, 821 I40E_TUNNEL_TYPE_VXLAN, 822 I40E_TUNNEL_TYPE_GENEVE, 823 I40E_TUNNEL_TYPE_TEREDO, 824 I40E_TUNNEL_TYPE_NVGRE, 825 I40E_TUNNEL_TYPE_IP_IN_GRE, 826 I40E_L2_TUNNEL_TYPE_E_TAG, 827 I40E_TUNNEL_TYPE_MPLSoUDP, 828 I40E_TUNNEL_TYPE_MPLSoGRE, 829 I40E_TUNNEL_TYPE_QINQ, 830 I40E_TUNNEL_TYPE_GTPC, 831 I40E_TUNNEL_TYPE_GTPU, 832 I40E_TUNNEL_TYPE_ESPoUDP, 833 I40E_TUNNEL_TYPE_ESPoIP, 834 I40E_CLOUD_TYPE_UDP, 835 I40E_CLOUD_TYPE_TCP, 836 I40E_CLOUD_TYPE_SCTP, 837 I40E_TUNNEL_TYPE_MAX, 838 }; 839 840 /** 841 * L4 port type. 842 */ 843 enum i40e_l4_port_type { 844 I40E_L4_PORT_TYPE_SRC = 0, 845 I40E_L4_PORT_TYPE_DST, 846 }; 847 848 /** 849 * Tunneling Packet filter configuration. 850 */ 851 struct i40e_tunnel_filter_conf { 852 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 853 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 854 uint16_t inner_vlan; /**< Inner VLAN to match. */ 855 uint32_t outer_vlan; /**< Outer VLAN to match */ 856 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 857 /** 858 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 859 * is set in filter_type, or inner destination IP address to match 860 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 861 */ 862 union { 863 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 864 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 865 } ip_addr; 866 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 867 uint16_t filter_type; 868 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 869 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 870 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 871 uint16_t queue_id; /**< Queue assigned to if match. */ 872 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 873 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 874 }; 875 876 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 877 #define I40E_MAX_MIRROR_RULES 64 878 /* 879 * Mirror rule structure 880 */ 881 struct i40e_mirror_rule { 882 TAILQ_ENTRY(i40e_mirror_rule) rules; 883 uint8_t rule_type; 884 uint16_t index; /* the sw index of mirror rule */ 885 uint16_t id; /* the rule id assigned by firmware */ 886 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 887 uint16_t num_entries; 888 /* the info stores depend on the rule type. 889 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 890 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 891 */ 892 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 893 }; 894 895 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 896 897 /* 898 * Struct to store flow created. 899 */ 900 struct rte_flow { 901 TAILQ_ENTRY(rte_flow) node; 902 enum rte_filter_type filter_type; 903 void *rule; 904 }; 905 906 TAILQ_HEAD(i40e_flow_list, rte_flow); 907 908 /* Struct to store Traffic Manager shaper profile. */ 909 struct i40e_tm_shaper_profile { 910 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 911 uint32_t shaper_profile_id; 912 uint32_t reference_count; 913 struct rte_tm_shaper_params profile; 914 }; 915 916 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 917 918 /* node type of Traffic Manager */ 919 enum i40e_tm_node_type { 920 I40E_TM_NODE_TYPE_PORT, 921 I40E_TM_NODE_TYPE_TC, 922 I40E_TM_NODE_TYPE_QUEUE, 923 I40E_TM_NODE_TYPE_MAX, 924 }; 925 926 /* Struct to store Traffic Manager node configuration. */ 927 struct i40e_tm_node { 928 TAILQ_ENTRY(i40e_tm_node) node; 929 uint32_t id; 930 uint32_t priority; 931 uint32_t weight; 932 uint32_t reference_count; 933 struct i40e_tm_node *parent; 934 struct i40e_tm_shaper_profile *shaper_profile; 935 struct rte_tm_node_params params; 936 }; 937 938 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 939 940 /* Struct to store all the Traffic Manager configuration. */ 941 struct i40e_tm_conf { 942 struct i40e_shaper_profile_list shaper_profile_list; 943 struct i40e_tm_node *root; /* root node - port */ 944 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 945 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 946 /** 947 * The number of added TC nodes. 948 * It should be no more than the TC number of this port. 949 */ 950 uint32_t nb_tc_node; 951 /** 952 * The number of added queue nodes. 953 * It should be no more than the queue number of this port. 954 */ 955 uint32_t nb_queue_node; 956 /** 957 * This flag is used to check if APP can change the TM node 958 * configuration. 959 * When it's true, means the configuration is applied to HW, 960 * APP should not change the configuration. 961 * As we don't support on-the-fly configuration, when starting 962 * the port, APP should call the hierarchy_commit API to set this 963 * flag to true. When stopping the port, this flag should be set 964 * to false. 965 */ 966 bool committed; 967 }; 968 969 enum i40e_new_pctype { 970 I40E_CUSTOMIZED_GTPC = 0, 971 I40E_CUSTOMIZED_GTPU_IPV4, 972 I40E_CUSTOMIZED_GTPU_IPV6, 973 I40E_CUSTOMIZED_GTPU, 974 I40E_CUSTOMIZED_IPV4_L2TPV3, 975 I40E_CUSTOMIZED_IPV6_L2TPV3, 976 I40E_CUSTOMIZED_ESP_IPV4, 977 I40E_CUSTOMIZED_ESP_IPV6, 978 I40E_CUSTOMIZED_ESP_IPV4_UDP, 979 I40E_CUSTOMIZED_ESP_IPV6_UDP, 980 I40E_CUSTOMIZED_AH_IPV4, 981 I40E_CUSTOMIZED_AH_IPV6, 982 I40E_CUSTOMIZED_MAX, 983 }; 984 985 #define I40E_FILTER_PCTYPE_INVALID 0 986 struct i40e_customized_pctype { 987 enum i40e_new_pctype index; /* Indicate which customized pctype */ 988 uint8_t pctype; /* New pctype value */ 989 bool valid; /* Check if it's valid */ 990 }; 991 992 struct i40e_rte_flow_rss_conf { 993 struct rte_flow_action_rss conf; /**< RSS parameters. */ 994 uint16_t queue_region_conf; /**< Queue region config flag */ 995 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 996 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 997 sizeof(uint32_t)]; /* Hash key. */ 998 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */ 999 bool valid; /* Check if it's valid */ 1000 }; 1001 1002 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1003 1004 /* RSS filter list structure */ 1005 struct i40e_rss_filter { 1006 TAILQ_ENTRY(i40e_rss_filter) next; 1007 struct i40e_rte_flow_rss_conf rss_filter_info; 1008 }; 1009 1010 struct i40e_vf_msg_cfg { 1011 /* maximal VF message during a statistic period */ 1012 uint32_t max_msg; 1013 1014 /* statistic period, in second */ 1015 uint32_t period; 1016 /* 1017 * If message statistics from a VF exceed the maximal limitation, 1018 * the PF will ignore any new message from that VF for 1019 * 'ignor_second' time. 1020 */ 1021 uint32_t ignore_second; 1022 }; 1023 1024 /* 1025 * Structure to store private data specific for PF instance. 1026 */ 1027 struct i40e_pf { 1028 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1029 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1030 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1031 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1032 uint16_t max_num_vsi; 1033 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1034 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1035 1036 struct i40e_hw_port_stats stats_offset; 1037 struct i40e_hw_port_stats stats; 1038 /* internal packet statistics, it should be excluded from the total */ 1039 struct i40e_eth_stats internal_stats_offset; 1040 struct i40e_eth_stats internal_stats; 1041 bool offset_loaded; 1042 1043 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1044 struct rte_ether_addr dev_addr; /* PF device mac address */ 1045 uint64_t flags; /* PF feature flags */ 1046 /* All kinds of queue pair setting for different VSIs */ 1047 struct i40e_pf_vf *vfs; 1048 uint16_t vf_num; 1049 /* Each of below queue pairs should be power of 2 since it's the 1050 precondition after TC configuration applied */ 1051 uint16_t lan_nb_qp_max; 1052 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1053 uint16_t lan_qp_offset; 1054 uint16_t vmdq_nb_qp_max; 1055 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1056 uint16_t vmdq_qp_offset; 1057 uint16_t vf_nb_qp_max; 1058 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1059 uint16_t vf_qp_offset; 1060 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1061 uint16_t fdir_qp_offset; 1062 1063 uint16_t hash_lut_size; /* The size of hash lookup table */ 1064 /* input set bits for each pctype */ 1065 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1066 /* store VXLAN UDP ports */ 1067 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1068 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1069 1070 /* VMDQ related info */ 1071 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1072 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1073 struct i40e_vmdq_info *vmdq; 1074 1075 struct i40e_fdir_info fdir; /* flow director info */ 1076 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1077 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1078 struct i40e_rte_flow_rss_conf rss_info; /* RSS info */ 1079 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1080 struct i40e_queue_regions queue_region; /* queue region info */ 1081 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1082 struct i40e_mirror_rule_list mirror_list; 1083 uint16_t nb_mirror_rule; /* The number of mirror rules */ 1084 bool floating_veb; /* The flag to use the floating VEB */ 1085 /* The floating enable flag for the specific VF */ 1086 bool floating_veb_list[I40E_MAX_VF]; 1087 struct i40e_flow_list flow_list; 1088 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1089 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1090 bool qinq_replace_flag; /* QINQ filter replace is done */ 1091 /* l4 port flag */ 1092 bool sport_replace_flag; /* Source port replace is done */ 1093 bool dport_replace_flag; /* Destination port replace is done */ 1094 struct i40e_tm_conf tm_conf; 1095 bool support_multi_driver; /* 1 - support multiple driver */ 1096 1097 /* Dynamic Device Personalization */ 1098 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1099 bool esp_support; /* 1 - support ESP SPI */ 1100 /* customer customized pctype */ 1101 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1102 /* Switch Domain Id */ 1103 uint16_t switch_domain_id; 1104 1105 struct i40e_vf_msg_cfg vf_msg_cfg; 1106 }; 1107 1108 enum pending_msg { 1109 PFMSG_LINK_CHANGE = 0x1, 1110 PFMSG_RESET_IMPENDING = 0x2, 1111 PFMSG_DRIVER_CLOSE = 0x4, 1112 }; 1113 1114 struct i40e_vsi_vlan_pvid_info { 1115 uint16_t on; /* Enable or disable pvid */ 1116 union { 1117 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1118 struct { 1119 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1120 * while 'untagged' will reject untagged packets. 1121 */ 1122 uint8_t tagged; 1123 uint8_t untagged; 1124 } reject; 1125 } config; 1126 }; 1127 1128 struct i40e_vf_rx_queues { 1129 uint64_t rx_dma_addr; 1130 uint32_t rx_ring_len; 1131 uint32_t buff_size; 1132 }; 1133 1134 struct i40e_vf_tx_queues { 1135 uint64_t tx_dma_addr; 1136 uint32_t tx_ring_len; 1137 }; 1138 1139 /* 1140 * Structure to store private data specific for VF instance. 1141 */ 1142 struct i40e_vf { 1143 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 1144 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1145 uint16_t num_queue_pairs; 1146 uint16_t max_pkt_len; /* Maximum packet length */ 1147 bool promisc_unicast_enabled; 1148 bool promisc_multicast_enabled; 1149 1150 uint32_t version_major; /* Major version number */ 1151 uint32_t version_minor; /* Minor version number */ 1152 uint16_t promisc_flags; /* Promiscuous setting */ 1153 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1154 1155 /* Multicast addrs */ 1156 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; 1157 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1158 1159 /* Event from pf */ 1160 bool dev_closed; 1161 bool link_up; 1162 enum virtchnl_link_speed link_speed; 1163 bool vf_reset; 1164 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1165 int32_t cmd_retval; /* return value of the cmd response from PF */ 1166 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1167 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1168 1169 /* VSI info */ 1170 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1171 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1172 struct i40e_vsi vsi; 1173 uint64_t flags; 1174 }; 1175 1176 #define I40E_MAX_PKT_TYPE 256 1177 #define I40E_FLOW_TYPE_MAX 64 1178 1179 /* 1180 * Structure to store private data for each PF/VF instance. 1181 */ 1182 struct i40e_adapter { 1183 /* Common for both PF and VF */ 1184 struct i40e_hw hw; 1185 struct rte_eth_dev *eth_dev; 1186 1187 /* Specific for PF or VF */ 1188 union { 1189 struct i40e_pf pf; 1190 struct i40e_vf vf; 1191 }; 1192 1193 /* For vector PMD */ 1194 bool rx_bulk_alloc_allowed; 1195 bool rx_vec_allowed; 1196 bool tx_simple_allowed; 1197 bool tx_vec_allowed; 1198 1199 /* For PTP */ 1200 struct rte_timecounter systime_tc; 1201 struct rte_timecounter rx_tstamp_tc; 1202 struct rte_timecounter tx_tstamp_tc; 1203 1204 /* ptype mapping table */ 1205 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1206 /* flow type to pctype mapping table */ 1207 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1208 uint64_t flow_types_mask; 1209 uint64_t pctypes_mask; 1210 1211 /* For devargs */ 1212 uint8_t use_latest_vec; 1213 1214 /* For RSS reta table update */ 1215 uint8_t rss_reta_updated; 1216 }; 1217 1218 /** 1219 * Strucute to store private data for each VF representor instance 1220 */ 1221 struct i40e_vf_representor { 1222 uint16_t switch_domain_id; 1223 /**< Virtual Function ID */ 1224 uint16_t vf_id; 1225 /**< Virtual Function ID */ 1226 struct i40e_adapter *adapter; 1227 /**< Private data store of assocaiated physical function */ 1228 struct i40e_eth_stats stats_offset; 1229 /**< Zero-point of VF statistics*/ 1230 }; 1231 1232 extern const struct rte_flow_ops i40e_flow_ops; 1233 1234 union i40e_filter_t { 1235 struct rte_eth_ethertype_filter ethertype_filter; 1236 struct i40e_fdir_filter_conf fdir_filter; 1237 struct rte_eth_tunnel_filter_conf tunnel_filter; 1238 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1239 struct i40e_rte_flow_rss_conf rss_conf; 1240 }; 1241 1242 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1243 const struct rte_flow_attr *attr, 1244 const struct rte_flow_item pattern[], 1245 const struct rte_flow_action actions[], 1246 struct rte_flow_error *error, 1247 union i40e_filter_t *filter); 1248 struct i40e_valid_pattern { 1249 enum rte_flow_item_type *items; 1250 parse_filter_t parse_filter; 1251 }; 1252 1253 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1254 int i40e_vsi_release(struct i40e_vsi *vsi); 1255 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1256 enum i40e_vsi_type type, 1257 struct i40e_vsi *uplink_vsi, 1258 uint16_t user_param); 1259 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1260 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1261 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1262 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1263 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1264 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1265 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1266 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1267 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1268 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1269 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1270 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1271 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1272 struct i40e_vsi_vlan_pvid_info *info); 1273 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1274 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1275 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1276 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1277 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1278 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1279 int i40e_fdir_setup(struct i40e_pf *pf); 1280 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1281 uint32_t len, 1282 int socket_id); 1283 int i40e_fdir_configure(struct rte_eth_dev *dev); 1284 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1285 void i40e_fdir_teardown(struct i40e_pf *pf); 1286 enum i40e_filter_pctype 1287 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1288 uint16_t flow_type); 1289 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1290 enum i40e_filter_pctype pctype); 1291 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1292 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1293 struct rte_eth_fdir_info *fdir); 1294 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1295 struct rte_eth_fdir_stats *stat); 1296 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev, 1297 enum rte_filter_op filter_op, 1298 void *arg); 1299 int i40e_select_filter_input_set(struct i40e_hw *hw, 1300 struct rte_eth_input_set_conf *conf, 1301 enum rte_filter_type filter); 1302 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1303 int i40e_hash_filter_inset_select(struct i40e_hw *hw, 1304 struct rte_eth_input_set_conf *conf); 1305 int i40e_fdir_filter_inset_select(struct i40e_pf *pf, 1306 struct rte_eth_input_set_conf *conf); 1307 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1308 uint32_t retval, uint8_t *msg, 1309 uint16_t msglen); 1310 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1311 struct rte_eth_rxq_info *qinfo); 1312 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1313 struct rte_eth_txq_info *qinfo); 1314 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1315 struct rte_eth_burst_mode *mode); 1316 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1317 struct rte_eth_burst_mode *mode); 1318 struct i40e_ethertype_filter * 1319 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1320 const struct i40e_ethertype_filter_input *input); 1321 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1322 struct i40e_ethertype_filter_input *input); 1323 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1324 struct i40e_fdir_input *input); 1325 struct i40e_tunnel_filter * 1326 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1327 const struct i40e_tunnel_filter_input *input); 1328 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1329 struct i40e_tunnel_filter_input *input); 1330 uint64_t i40e_get_default_input_set(uint16_t pctype); 1331 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1332 struct rte_eth_ethertype_filter *filter, 1333 bool add); 1334 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev, 1335 const struct rte_eth_fdir_filter *filter, 1336 bool add); 1337 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1338 const struct i40e_fdir_filter_conf *filter, 1339 bool add); 1340 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1341 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1342 uint8_t add); 1343 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1344 struct i40e_tunnel_filter_conf *tunnel_filter, 1345 uint8_t add); 1346 int i40e_fdir_flush(struct rte_eth_dev *dev); 1347 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1348 struct i40e_macvlan_filter *mv_f, 1349 int num, struct rte_ether_addr *addr); 1350 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1351 struct i40e_macvlan_filter *filter, 1352 int total); 1353 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1354 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1355 struct i40e_macvlan_filter *filter, 1356 int total); 1357 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1358 bool is_i40e_supported(struct rte_eth_dev *dev); 1359 bool is_i40evf_supported(struct rte_eth_dev *dev); 1360 1361 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1362 enum rte_filter_type filter, uint64_t inset); 1363 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, 1364 uint8_t nb_elem); 1365 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1366 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1367 void i40e_check_write_global_reg(struct i40e_hw *hw, 1368 uint32_t addr, uint32_t val); 1369 1370 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1371 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1372 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1373 struct i40e_customized_pctype* 1374 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1375 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1376 uint32_t pkg_size, 1377 enum rte_pmd_i40e_package_op op); 1378 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1379 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1380 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1381 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1382 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1383 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1384 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1385 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, 1386 const struct rte_flow_action_rss *in); 1387 int i40e_config_rss_filter(struct i40e_pf *pf, 1388 struct i40e_rte_flow_rss_conf *conf, bool add); 1389 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1390 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1391 1392 #define I40E_DEV_TO_PCI(eth_dev) \ 1393 RTE_DEV_TO_PCI((eth_dev)->device) 1394 1395 /* I40E_DEV_PRIVATE_TO */ 1396 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1397 (&((struct i40e_adapter *)adapter)->pf) 1398 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1399 (&((struct i40e_adapter *)adapter)->hw) 1400 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1401 ((struct i40e_adapter *)adapter) 1402 1403 /* I40EVF_DEV_PRIVATE_TO */ 1404 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1405 (&((struct i40e_adapter *)adapter)->vf) 1406 1407 static inline struct i40e_vsi * 1408 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1409 { 1410 struct i40e_hw *hw; 1411 1412 if (!adapter) 1413 return NULL; 1414 1415 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1416 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1417 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1418 return &vf->vsi; 1419 } else { 1420 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1421 return pf->main_vsi; 1422 } 1423 } 1424 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1425 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1426 1427 /* I40E_VSI_TO */ 1428 #define I40E_VSI_TO_HW(vsi) \ 1429 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1430 #define I40E_VSI_TO_PF(vsi) \ 1431 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1432 #define I40E_VSI_TO_VF(vsi) \ 1433 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1434 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1435 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1436 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1437 (((struct i40e_vsi *)vsi)->adapter->eth_dev) 1438 1439 /* I40E_PF_TO */ 1440 #define I40E_PF_TO_HW(pf) \ 1441 (&(((struct i40e_pf *)pf)->adapter->hw)) 1442 #define I40E_PF_TO_ADAPTER(pf) \ 1443 ((struct i40e_adapter *)pf->adapter) 1444 1445 /* I40E_VF_TO */ 1446 #define I40E_VF_TO_HW(vf) \ 1447 (&(((struct i40e_vf *)vf)->adapter->hw)) 1448 1449 static inline void 1450 i40e_init_adminq_parameter(struct i40e_hw *hw) 1451 { 1452 hw->aq.num_arq_entries = I40E_AQ_LEN; 1453 hw->aq.num_asq_entries = I40E_AQ_LEN; 1454 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1455 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1456 } 1457 1458 static inline int 1459 i40e_align_floor(int n) 1460 { 1461 if (n == 0) 1462 return 0; 1463 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1464 } 1465 1466 static inline uint16_t 1467 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1468 { 1469 uint16_t interval = 0; 1470 1471 if (is_multi_drv) { 1472 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1473 } else { 1474 if (is_pf) 1475 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1476 else 1477 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1478 } 1479 1480 /* Convert to hardware count, as writing each 1 represents 2 us */ 1481 return interval / 2; 1482 } 1483 1484 #define I40E_VALID_FLOW(flow_type) \ 1485 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1486 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1487 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1488 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1489 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1490 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1491 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1492 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1493 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1494 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1495 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1496 1497 #define I40E_VALID_PCTYPE_X722(pctype) \ 1498 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1499 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1500 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1501 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1502 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1503 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1504 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1505 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1506 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1507 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1508 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1509 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1510 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1511 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1512 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1513 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1514 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1515 1516 #define I40E_VALID_PCTYPE(pctype) \ 1517 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1518 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1519 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1520 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1521 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1522 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1523 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1524 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1525 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1526 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1527 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1528 1529 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1530 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1531 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1532 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1533 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1534 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1535 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1536 1537 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1538 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1539 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1540 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1541 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1542 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1543 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1544 1545 #endif /* _I40E_ETHDEV_H_ */ 1546