1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _I40E_ETHDEV_H_ 35 #define _I40E_ETHDEV_H_ 36 37 #include <rte_eth_ctrl.h> 38 #include <rte_time.h> 39 #include <rte_kvargs.h> 40 41 #define I40E_VLAN_TAG_SIZE 4 42 43 #define I40E_AQ_LEN 32 44 #define I40E_AQ_BUF_SZ 4096 45 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 46 #define I40E_MAX_Q_PER_TC 64 47 #define I40E_NUM_DESC_DEFAULT 512 48 #define I40E_NUM_DESC_ALIGN 32 49 #define I40E_BUF_SIZE_MIN 1024 50 #define I40E_FRAME_SIZE_MAX 9728 51 #define I40E_QUEUE_BASE_ADDR_UNIT 128 52 /* number of VSIs and queue default setting */ 53 #define I40E_MAX_QP_NUM_PER_VF 16 54 #define I40E_DEFAULT_QP_NUM_FDIR 1 55 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 56 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 57 /* Maximun number of MAC addresses */ 58 #define I40E_NUM_MACADDR_MAX 64 59 /* Maximum number of VFs */ 60 #define I40E_MAX_VF 128 61 62 /* 63 * vlan_id is a 12 bit number. 64 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 65 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 66 * The higher 7 bit val specifies VFTA array index. 67 */ 68 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 69 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 70 71 /* Default TC traffic in case DCB is not enabled */ 72 #define I40E_DEFAULT_TCMAP 0x1 73 #define I40E_FDIR_QUEUE_ID 0 74 75 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 76 #define I40E_VMDQ_POOL_BASE 1 77 78 #define I40E_DEFAULT_RX_FREE_THRESH 32 79 #define I40E_DEFAULT_RX_PTHRESH 8 80 #define I40E_DEFAULT_RX_HTHRESH 8 81 #define I40E_DEFAULT_RX_WTHRESH 0 82 83 #define I40E_DEFAULT_TX_FREE_THRESH 32 84 #define I40E_DEFAULT_TX_PTHRESH 32 85 #define I40E_DEFAULT_TX_HTHRESH 0 86 #define I40E_DEFAULT_TX_WTHRESH 0 87 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 88 89 /* Bit shift and mask */ 90 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 91 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 92 #define I40E_8_BIT_WIDTH CHAR_BIT 93 #define I40E_8_BIT_MASK UINT8_MAX 94 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 95 #define I40E_16_BIT_MASK UINT16_MAX 96 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 97 #define I40E_32_BIT_MASK UINT32_MAX 98 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 99 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 100 101 /* Linux PF host with virtchnl version 1.1 */ 102 #define PF_IS_V11(vf) \ 103 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \ 104 ((vf)->version_minor == 1)) 105 106 /* index flex payload per layer */ 107 enum i40e_flxpld_layer_idx { 108 I40E_FLXPLD_L2_IDX = 0, 109 I40E_FLXPLD_L3_IDX = 1, 110 I40E_FLXPLD_L4_IDX = 2, 111 I40E_MAX_FLXPLD_LAYER = 3, 112 }; 113 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 114 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 115 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 116 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 117 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 118 119 /* i40e flags */ 120 #define I40E_FLAG_RSS (1ULL << 0) 121 #define I40E_FLAG_DCB (1ULL << 1) 122 #define I40E_FLAG_VMDQ (1ULL << 2) 123 #define I40E_FLAG_SRIOV (1ULL << 3) 124 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 125 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 126 #define I40E_FLAG_FDIR (1ULL << 6) 127 #define I40E_FLAG_VXLAN (1ULL << 7) 128 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 129 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 130 I40E_FLAG_DCB | \ 131 I40E_FLAG_VMDQ | \ 132 I40E_FLAG_SRIOV | \ 133 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 134 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 135 I40E_FLAG_FDIR | \ 136 I40E_FLAG_VXLAN | \ 137 I40E_FLAG_RSS_AQ_CAPABLE) 138 139 #define I40E_RSS_OFFLOAD_ALL ( \ 140 ETH_RSS_FRAG_IPV4 | \ 141 ETH_RSS_NONFRAG_IPV4_TCP | \ 142 ETH_RSS_NONFRAG_IPV4_UDP | \ 143 ETH_RSS_NONFRAG_IPV4_SCTP | \ 144 ETH_RSS_NONFRAG_IPV4_OTHER | \ 145 ETH_RSS_FRAG_IPV6 | \ 146 ETH_RSS_NONFRAG_IPV6_TCP | \ 147 ETH_RSS_NONFRAG_IPV6_UDP | \ 148 ETH_RSS_NONFRAG_IPV6_SCTP | \ 149 ETH_RSS_NONFRAG_IPV6_OTHER | \ 150 ETH_RSS_L2_PAYLOAD) 151 152 /* All bits of RSS hash enable */ 153 #ifdef X722_SUPPORT 154 #define I40E_RSS_HENA_ALL ( \ 155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 158 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 160 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 161 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 162 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 163 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 170 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 171 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 172 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 173 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 174 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 175 #else 176 #define I40E_RSS_HENA_ALL ( \ 177 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 178 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 179 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 180 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 181 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 182 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 183 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 184 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 185 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 186 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 187 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 188 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 189 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 190 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 191 #endif 192 193 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 194 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 195 196 /* Default queue interrupt throttling time in microseconds */ 197 #define I40E_ITR_INDEX_DEFAULT 0 198 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 199 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 200 201 /* Special FW support this floating VEB feature */ 202 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 203 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 204 205 struct i40e_adapter; 206 207 /** 208 * MAC filter structure 209 */ 210 struct i40e_mac_filter_info { 211 enum rte_mac_filter_type filter_type; 212 struct ether_addr mac_addr; 213 }; 214 215 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 216 217 /* MAC filter list structure */ 218 struct i40e_mac_filter { 219 TAILQ_ENTRY(i40e_mac_filter) next; 220 struct i40e_mac_filter_info mac_info; 221 }; 222 223 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 224 225 struct i40e_vsi; 226 227 /* VSI list structure */ 228 struct i40e_vsi_list { 229 TAILQ_ENTRY(i40e_vsi_list) list; 230 struct i40e_vsi *vsi; 231 }; 232 233 struct i40e_rx_queue; 234 struct i40e_tx_queue; 235 236 /* Bandwidth limit information */ 237 struct i40e_bw_info { 238 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 239 uint8_t bw_max; /* Max BW limit if enabled */ 240 241 /* Relative credits within same TC with respect to other VSIs or Comps */ 242 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 243 /* Bandwidth limit per TC */ 244 uint8_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 245 /* Max bandwidth limit per TC */ 246 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 247 }; 248 249 /* Structure that defines a VEB */ 250 struct i40e_veb { 251 struct i40e_vsi_list_head head; 252 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 253 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 254 uint16_t seid; /* The seid of VEB itself */ 255 uint16_t uplink_seid; /* The uplink seid of this VEB */ 256 uint16_t stats_idx; 257 struct i40e_eth_stats stats; 258 uint8_t enabled_tc; /* The traffic class enabled */ 259 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 260 }; 261 262 /* i40e MACVLAN filter structure */ 263 struct i40e_macvlan_filter { 264 struct ether_addr macaddr; 265 enum rte_mac_filter_type filter_type; 266 uint16_t vlan_id; 267 }; 268 269 /* 270 * Structure that defines a VSI, associated with a adapter. 271 */ 272 struct i40e_vsi { 273 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 274 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 275 276 struct i40e_eth_stats eth_stats_offset; 277 struct i40e_eth_stats eth_stats; 278 /* 279 * When drivers loaded, only a default main VSI exists. In case new VSI 280 * needs to add, HW needs to know the layout that VSIs are organized. 281 * Besides that, VSI isan element and can't switch packets, which needs 282 * to add new component VEB to perform switching. So, a new VSI needs 283 * to specify the the uplink VSI (Parent VSI) before created. The 284 * uplink VSI will check whether it had a VEB to switch packets. If no, 285 * it will try to create one. Then, uplink VSI will move the new VSI 286 * into its' sib_vsi_list to manage all the downlink VSI. 287 * sib_vsi_list: the VSI list that shared the same uplink VSI. 288 * parent_vsi : the uplink VSI. It's NULL for main VSI. 289 * veb : the VEB associates with the VSI. 290 */ 291 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 292 struct i40e_vsi *parent_vsi; 293 struct i40e_veb *veb; /* Associated veb, could be null */ 294 struct i40e_veb *floating_veb; /* Associated floating veb */ 295 bool offset_loaded; 296 enum i40e_vsi_type type; /* VSI types */ 297 uint16_t vlan_num; /* Total VLAN number */ 298 uint16_t mac_num; /* Total mac number */ 299 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 300 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 301 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 302 uint32_t user_param; 303 uint16_t seid; /* The seid of VSI itself */ 304 uint16_t uplink_seid; /* The uplink seid of this VSI */ 305 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 306 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 307 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 308 uint16_t base_queue; /* The first queue index of this VSI */ 309 /* 310 * The offset to visit VSI related register, assigned by HW when 311 * creating VSI 312 */ 313 uint16_t vsi_id; 314 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 315 uint16_t nb_msix; /* The max number of msix vector */ 316 uint8_t enabled_tc; /* The traffic class enabled */ 317 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 318 }; 319 320 struct pool_entry { 321 LIST_ENTRY(pool_entry) next; 322 uint16_t base; 323 uint16_t len; 324 }; 325 326 LIST_HEAD(res_list, pool_entry); 327 328 struct i40e_res_pool_info { 329 uint32_t base; /* Resource start index */ 330 uint32_t num_alloc; /* Allocated resource number */ 331 uint32_t num_free; /* Total available resource number */ 332 struct res_list alloc_list; /* Allocated resource list */ 333 struct res_list free_list; /* Available resource list */ 334 }; 335 336 enum I40E_VF_STATE { 337 I40E_VF_INACTIVE = 0, 338 I40E_VF_INRESET, 339 I40E_VF_ININIT, 340 I40E_VF_ACTIVE, 341 }; 342 343 /* 344 * Structure to store private data for PF host. 345 */ 346 struct i40e_pf_vf { 347 struct i40e_pf *pf; 348 struct i40e_vsi *vsi; 349 enum I40E_VF_STATE state; /* The number of queue pairs availiable */ 350 uint16_t vf_idx; /* VF index in pf->vfs */ 351 uint16_t lan_nb_qps; /* Actual queues allocated */ 352 uint16_t reset_cnt; /* Total vf reset times */ 353 struct ether_addr mac_addr; /* Default MAC address */ 354 }; 355 356 /* 357 * Structure to store private data for flow control. 358 */ 359 struct i40e_fc_conf { 360 uint16_t pause_time; /* Flow control pause timer */ 361 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 362 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 363 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 364 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 365 }; 366 367 /* 368 * Structure to store private data for VMDQ instance 369 */ 370 struct i40e_vmdq_info { 371 struct i40e_pf *pf; 372 struct i40e_vsi *vsi; 373 }; 374 375 /* 376 * Structure to store flex pit for flow diretor. 377 */ 378 struct i40e_fdir_flex_pit { 379 uint8_t src_offset; /* offset in words from the beginning of payload */ 380 uint8_t size; /* size in words */ 381 uint8_t dst_offset; /* offset in words of flexible payload */ 382 }; 383 384 struct i40e_fdir_flex_mask { 385 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 386 struct { 387 uint8_t offset; 388 uint16_t mask; 389 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 390 }; 391 392 #define I40E_FILTER_PCTYPE_MAX 64 393 /* 394 * A structure used to define fields of a FDIR related info. 395 */ 396 struct i40e_fdir_info { 397 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 398 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 399 struct i40e_tx_queue *txq; 400 struct i40e_rx_queue *rxq; 401 void *prg_pkt; /* memory for fdir program packet */ 402 uint64_t dma_addr; /* physic address of packet memory*/ 403 /* input set bits for each pctype */ 404 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 405 /* 406 * the rule how bytes stream is extracted as flexible payload 407 * for each payload layer, the setting can up to three elements 408 */ 409 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 410 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 411 }; 412 413 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 414 #define I40E_MAX_MIRROR_RULES 64 415 /* 416 * Mirror rule structure 417 */ 418 struct i40e_mirror_rule { 419 TAILQ_ENTRY(i40e_mirror_rule) rules; 420 uint8_t rule_type; 421 uint16_t index; /* the sw index of mirror rule */ 422 uint16_t id; /* the rule id assigned by firmware */ 423 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 424 uint16_t num_entries; 425 /* the info stores depend on the rule type. 426 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 427 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 428 */ 429 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 430 }; 431 432 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 433 434 /* 435 * Structure to store private data specific for PF instance. 436 */ 437 struct i40e_pf { 438 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 439 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 440 uint16_t mac_seid; /* The seid of the MAC of this PF */ 441 uint16_t main_vsi_seid; /* The seid of the main VSI */ 442 uint16_t max_num_vsi; 443 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 444 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 445 446 struct i40e_hw_port_stats stats_offset; 447 struct i40e_hw_port_stats stats; 448 bool offset_loaded; 449 450 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 451 struct ether_addr dev_addr; /* PF device mac address */ 452 uint64_t flags; /* PF feature flags */ 453 /* All kinds of queue pair setting for different VSIs */ 454 struct i40e_pf_vf *vfs; 455 uint16_t vf_num; 456 /* Each of below queue pairs should be power of 2 since it's the 457 precondition after TC configuration applied */ 458 uint16_t lan_nb_qp_max; 459 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 460 uint16_t lan_qp_offset; 461 uint16_t vmdq_nb_qp_max; 462 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 463 uint16_t vmdq_qp_offset; 464 uint16_t vf_nb_qp_max; 465 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 466 uint16_t vf_qp_offset; 467 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 468 uint16_t fdir_qp_offset; 469 470 uint16_t hash_lut_size; /* The size of hash lookup table */ 471 /* input set bits for each pctype */ 472 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 473 /* store VXLAN UDP ports */ 474 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 475 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 476 477 /* VMDQ related info */ 478 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 479 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 480 struct i40e_vmdq_info *vmdq; 481 482 struct i40e_fdir_info fdir; /* flow director info */ 483 struct i40e_fc_conf fc_conf; /* Flow control conf */ 484 struct i40e_mirror_rule_list mirror_list; 485 uint16_t nb_mirror_rule; /* The number of mirror rules */ 486 bool floating_veb; /* The flag to use the floating VEB */ 487 /* The floating enable flag for the specific VF */ 488 bool floating_veb_list[I40E_MAX_VF]; 489 }; 490 491 enum pending_msg { 492 PFMSG_LINK_CHANGE = 0x1, 493 PFMSG_RESET_IMPENDING = 0x2, 494 PFMSG_DRIVER_CLOSE = 0x4, 495 }; 496 497 struct i40e_vsi_vlan_pvid_info { 498 uint16_t on; /* Enable or disable pvid */ 499 union { 500 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 501 struct { 502 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 503 * while 'untagged' will reject untagged packets. 504 */ 505 uint8_t tagged; 506 uint8_t untagged; 507 } reject; 508 } config; 509 }; 510 511 struct i40e_vf_rx_queues { 512 uint64_t rx_dma_addr; 513 uint32_t rx_ring_len; 514 uint32_t buff_size; 515 }; 516 517 struct i40e_vf_tx_queues { 518 uint64_t tx_dma_addr; 519 uint32_t tx_ring_len; 520 }; 521 522 /* 523 * Structure to store private data specific for VF instance. 524 */ 525 struct i40e_vf { 526 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 527 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 528 uint16_t num_queue_pairs; 529 uint16_t max_pkt_len; /* Maximum packet length */ 530 bool promisc_unicast_enabled; 531 bool promisc_multicast_enabled; 532 533 uint32_t version_major; /* Major version number */ 534 uint32_t version_minor; /* Minor version number */ 535 uint16_t promisc_flags; /* Promiscuous setting */ 536 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 537 538 /* Event from pf */ 539 bool dev_closed; 540 bool link_up; 541 enum i40e_aq_link_speed link_speed; 542 bool vf_reset; 543 volatile uint32_t pend_cmd; /* pending command not finished yet */ 544 uint32_t cmd_retval; /* return value of the cmd response from PF */ 545 u16 pend_msg; /* flags indicates events from pf not handled yet */ 546 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 547 548 /* VSI info */ 549 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */ 550 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 551 struct i40e_vsi vsi; 552 uint64_t flags; 553 }; 554 555 /* 556 * Structure to store private data for each PF/VF instance. 557 */ 558 struct i40e_adapter { 559 /* Common for both PF and VF */ 560 struct i40e_hw hw; 561 struct rte_eth_dev *eth_dev; 562 563 /* Specific for PF or VF */ 564 union { 565 struct i40e_pf pf; 566 struct i40e_vf vf; 567 }; 568 569 /* For vector PMD */ 570 bool rx_bulk_alloc_allowed; 571 bool rx_vec_allowed; 572 bool tx_simple_allowed; 573 bool tx_vec_allowed; 574 575 /* For PTP */ 576 struct rte_timecounter systime_tc; 577 struct rte_timecounter rx_tstamp_tc; 578 struct rte_timecounter tx_tstamp_tc; 579 }; 580 581 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 582 int i40e_vsi_release(struct i40e_vsi *vsi); 583 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 584 enum i40e_vsi_type type, 585 struct i40e_vsi *uplink_vsi, 586 uint16_t user_param); 587 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 588 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 589 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 590 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 591 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 592 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr); 593 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 594 void i40e_pf_disable_irq0(struct i40e_hw *hw); 595 void i40e_pf_enable_irq0(struct i40e_hw *hw); 596 int i40e_dev_link_update(struct rte_eth_dev *dev, 597 __rte_unused int wait_to_complete); 598 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi); 599 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 600 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 601 struct i40e_vsi_vlan_pvid_info *info); 602 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 603 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 604 uint64_t i40e_config_hena(uint64_t flags); 605 uint64_t i40e_parse_hena(uint64_t flags); 606 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 607 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 608 int i40e_fdir_setup(struct i40e_pf *pf); 609 const struct rte_memzone *i40e_memzone_reserve(const char *name, 610 uint32_t len, 611 int socket_id); 612 int i40e_fdir_configure(struct rte_eth_dev *dev); 613 void i40e_fdir_teardown(struct i40e_pf *pf); 614 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type); 615 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype); 616 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev, 617 enum rte_filter_op filter_op, 618 void *arg); 619 int i40e_select_filter_input_set(struct i40e_hw *hw, 620 struct rte_eth_input_set_conf *conf, 621 enum rte_filter_type filter); 622 int i40e_hash_filter_inset_select(struct i40e_hw *hw, 623 struct rte_eth_input_set_conf *conf); 624 int i40e_fdir_filter_inset_select(struct i40e_pf *pf, 625 struct rte_eth_input_set_conf *conf); 626 627 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 628 struct rte_eth_rxq_info *qinfo); 629 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 630 struct rte_eth_txq_info *qinfo); 631 632 /* I40E_DEV_PRIVATE_TO */ 633 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 634 (&((struct i40e_adapter *)adapter)->pf) 635 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 636 (&((struct i40e_adapter *)adapter)->hw) 637 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 638 ((struct i40e_adapter *)adapter) 639 640 /* I40EVF_DEV_PRIVATE_TO */ 641 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 642 (&((struct i40e_adapter *)adapter)->vf) 643 644 static inline struct i40e_vsi * 645 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 646 { 647 struct i40e_hw *hw; 648 649 if (!adapter) 650 return NULL; 651 652 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 653 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 654 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 655 return &vf->vsi; 656 } else { 657 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 658 return pf->main_vsi; 659 } 660 } 661 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 662 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 663 664 /* I40E_VSI_TO */ 665 #define I40E_VSI_TO_HW(vsi) \ 666 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 667 #define I40E_VSI_TO_PF(vsi) \ 668 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 669 #define I40E_VSI_TO_VF(vsi) \ 670 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 671 #define I40E_VSI_TO_DEV_DATA(vsi) \ 672 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 673 #define I40E_VSI_TO_ETH_DEV(vsi) \ 674 (((struct i40e_vsi *)vsi)->adapter->eth_dev) 675 676 /* I40E_PF_TO */ 677 #define I40E_PF_TO_HW(pf) \ 678 (&(((struct i40e_pf *)pf)->adapter->hw)) 679 #define I40E_PF_TO_ADAPTER(pf) \ 680 ((struct i40e_adapter *)pf->adapter) 681 682 /* I40E_VF_TO */ 683 #define I40E_VF_TO_HW(vf) \ 684 (&(((struct i40e_vf *)vf)->adapter->hw)) 685 686 static inline void 687 i40e_init_adminq_parameter(struct i40e_hw *hw) 688 { 689 hw->aq.num_arq_entries = I40E_AQ_LEN; 690 hw->aq.num_asq_entries = I40E_AQ_LEN; 691 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 692 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 693 } 694 695 static inline int 696 i40e_align_floor(int n) 697 { 698 if (n == 0) 699 return 0; 700 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 701 } 702 703 static inline uint16_t 704 i40e_calc_itr_interval(int16_t interval) 705 { 706 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) 707 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 708 709 /* Convert to hardware count, as writing each 1 represents 2 us */ 710 return interval / 2; 711 } 712 713 #define I40E_VALID_FLOW(flow_type) \ 714 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 715 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 716 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 717 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 718 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 719 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 720 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 721 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 722 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 723 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 724 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 725 726 #ifdef X722_SUPPORT 727 #define I40E_VALID_PCTYPE(pctype) \ 728 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 729 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 730 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 731 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 732 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 733 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 734 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 735 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 736 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 737 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 738 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 739 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 740 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 741 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 742 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 743 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 744 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 745 #else 746 #define I40E_VALID_PCTYPE(pctype) \ 747 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 748 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 749 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 750 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 751 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 752 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 753 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 754 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 755 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 756 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 757 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 758 #endif 759 760 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 761 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 762 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 763 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 764 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 765 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 766 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 767 768 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 769 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 770 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 771 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 772 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR)) 773 774 #endif /* _I40E_ETHDEV_H_ */ 775