1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <rte_eth_ctrl.h> 9 #include <rte_time.h> 10 #include <rte_kvargs.h> 11 #include <rte_hash.h> 12 #include <rte_flow_driver.h> 13 #include <rte_tm_driver.h> 14 15 #define I40E_VLAN_TAG_SIZE 4 16 17 #define I40E_AQ_LEN 32 18 #define I40E_AQ_BUF_SZ 4096 19 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 20 #define I40E_MAX_Q_PER_TC 64 21 #define I40E_NUM_DESC_DEFAULT 512 22 #define I40E_NUM_DESC_ALIGN 32 23 #define I40E_BUF_SIZE_MIN 1024 24 #define I40E_FRAME_SIZE_MAX 9728 25 #define I40E_QUEUE_BASE_ADDR_UNIT 128 26 /* number of VSIs and queue default setting */ 27 #define I40E_MAX_QP_NUM_PER_VF 16 28 #define I40E_DEFAULT_QP_NUM_FDIR 1 29 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 30 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 31 /* Maximun number of MAC addresses */ 32 #define I40E_NUM_MACADDR_MAX 64 33 /* Maximum number of VFs */ 34 #define I40E_MAX_VF 128 35 /*flag of no loopback*/ 36 #define I40E_AQ_LB_MODE_NONE 0x0 37 /* 38 * vlan_id is a 12 bit number. 39 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 40 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 41 * The higher 7 bit val specifies VFTA array index. 42 */ 43 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 44 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 45 46 /* Default TC traffic in case DCB is not enabled */ 47 #define I40E_DEFAULT_TCMAP 0x1 48 #define I40E_FDIR_QUEUE_ID 0 49 50 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 51 #define I40E_VMDQ_POOL_BASE 1 52 53 #define I40E_DEFAULT_RX_FREE_THRESH 32 54 #define I40E_DEFAULT_RX_PTHRESH 8 55 #define I40E_DEFAULT_RX_HTHRESH 8 56 #define I40E_DEFAULT_RX_WTHRESH 0 57 58 #define I40E_DEFAULT_TX_FREE_THRESH 32 59 #define I40E_DEFAULT_TX_PTHRESH 32 60 #define I40E_DEFAULT_TX_HTHRESH 0 61 #define I40E_DEFAULT_TX_WTHRESH 0 62 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 63 64 /* Bit shift and mask */ 65 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 66 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 67 #define I40E_8_BIT_WIDTH CHAR_BIT 68 #define I40E_8_BIT_MASK UINT8_MAX 69 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 70 #define I40E_16_BIT_MASK UINT16_MAX 71 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 72 #define I40E_32_BIT_MASK UINT32_MAX 73 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 74 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 75 76 /* Linux PF host with virtchnl version 1.1 */ 77 #define PF_IS_V11(vf) \ 78 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 79 ((vf)->version_minor == 1)) 80 81 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 82 do { \ 83 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 84 (reg)), (value)); \ 85 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \ 86 "with value 0x%08x", \ 87 (reg), (value)); \ 88 } while (0) 89 90 /* index flex payload per layer */ 91 enum i40e_flxpld_layer_idx { 92 I40E_FLXPLD_L2_IDX = 0, 93 I40E_FLXPLD_L3_IDX = 1, 94 I40E_FLXPLD_L4_IDX = 2, 95 I40E_MAX_FLXPLD_LAYER = 3, 96 }; 97 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 98 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 99 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 100 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 101 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 102 103 /* i40e flags */ 104 #define I40E_FLAG_RSS (1ULL << 0) 105 #define I40E_FLAG_DCB (1ULL << 1) 106 #define I40E_FLAG_VMDQ (1ULL << 2) 107 #define I40E_FLAG_SRIOV (1ULL << 3) 108 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 109 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 110 #define I40E_FLAG_FDIR (1ULL << 6) 111 #define I40E_FLAG_VXLAN (1ULL << 7) 112 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 113 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9) 114 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 115 I40E_FLAG_DCB | \ 116 I40E_FLAG_VMDQ | \ 117 I40E_FLAG_SRIOV | \ 118 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 119 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 120 I40E_FLAG_FDIR | \ 121 I40E_FLAG_VXLAN | \ 122 I40E_FLAG_RSS_AQ_CAPABLE | \ 123 I40E_FLAG_VF_MAC_BY_PF) 124 125 #define I40E_RSS_OFFLOAD_ALL ( \ 126 ETH_RSS_FRAG_IPV4 | \ 127 ETH_RSS_NONFRAG_IPV4_TCP | \ 128 ETH_RSS_NONFRAG_IPV4_UDP | \ 129 ETH_RSS_NONFRAG_IPV4_SCTP | \ 130 ETH_RSS_NONFRAG_IPV4_OTHER | \ 131 ETH_RSS_FRAG_IPV6 | \ 132 ETH_RSS_NONFRAG_IPV6_TCP | \ 133 ETH_RSS_NONFRAG_IPV6_UDP | \ 134 ETH_RSS_NONFRAG_IPV6_SCTP | \ 135 ETH_RSS_NONFRAG_IPV6_OTHER | \ 136 ETH_RSS_L2_PAYLOAD) 137 138 /* All bits of RSS hash enable for X722*/ 139 #define I40E_RSS_HENA_ALL_X722 ( \ 140 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 141 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 142 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 143 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 144 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 145 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 146 I40E_RSS_HENA_ALL) 147 148 /* All bits of RSS hash enable */ 149 #define I40E_RSS_HENA_ALL ( \ 150 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 151 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 152 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 153 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 154 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 155 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 158 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 159 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 160 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 161 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 162 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 163 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 164 165 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 166 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 167 168 /* Default queue interrupt throttling time in microseconds */ 169 #define I40E_ITR_INDEX_DEFAULT 0 170 #define I40E_ITR_INDEX_NONE 3 171 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 172 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 173 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 8160 /* 8160 us */ 174 /* Special FW support this floating VEB feature */ 175 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 176 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 177 178 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 179 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 180 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 181 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 182 183 #define I40E_INSET_NONE 0x00000000000000000ULL 184 185 /* bit0 ~ bit 7 */ 186 #define I40E_INSET_DMAC 0x0000000000000001ULL 187 #define I40E_INSET_SMAC 0x0000000000000002ULL 188 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 189 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 190 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 191 192 /* bit 8 ~ bit 15 */ 193 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 194 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 195 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 196 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 197 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 198 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 199 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 200 201 /* bit 16 ~ bit 31 */ 202 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 203 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 204 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 205 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 206 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 207 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 208 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 209 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 210 211 /* bit 32 ~ bit 47, tunnel fields */ 212 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 213 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 214 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 215 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 216 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 217 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 218 219 /* bit 48 ~ bit 55 */ 220 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 221 222 /* bit 56 ~ bit 63, Flex Payload */ 223 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 224 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 225 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 226 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 227 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 228 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 229 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 230 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 231 #define I40E_INSET_FLEX_PAYLOAD \ 232 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 233 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 234 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 235 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 236 237 /* The max bandwidth of i40e is 40Gbps. */ 238 #define I40E_QOS_BW_MAX 40000 239 /* The bandwidth should be the multiple of 50Mbps. */ 240 #define I40E_QOS_BW_GRANULARITY 50 241 /* The min bandwidth weight is 1. */ 242 #define I40E_QOS_BW_WEIGHT_MIN 1 243 /* The max bandwidth weight is 127. */ 244 #define I40E_QOS_BW_WEIGHT_MAX 127 245 /* The max queue region index is 7. */ 246 #define I40E_REGION_MAX_INDEX 7 247 248 #define I40E_MAX_PERCENT 100 249 #define I40E_DEFAULT_DCB_APP_NUM 1 250 #define I40E_DEFAULT_DCB_APP_PRIO 3 251 252 /** 253 * The overhead from MTU to max frame size. 254 * Considering QinQ packet, the VLAN tag needs to be counted twice. 255 */ 256 #define I40E_ETH_OVERHEAD \ 257 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 258 259 struct i40e_adapter; 260 261 /** 262 * MAC filter structure 263 */ 264 struct i40e_mac_filter_info { 265 enum rte_mac_filter_type filter_type; 266 struct ether_addr mac_addr; 267 }; 268 269 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 270 271 /* MAC filter list structure */ 272 struct i40e_mac_filter { 273 TAILQ_ENTRY(i40e_mac_filter) next; 274 struct i40e_mac_filter_info mac_info; 275 }; 276 277 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 278 279 struct i40e_vsi; 280 281 /* VSI list structure */ 282 struct i40e_vsi_list { 283 TAILQ_ENTRY(i40e_vsi_list) list; 284 struct i40e_vsi *vsi; 285 }; 286 287 struct i40e_rx_queue; 288 struct i40e_tx_queue; 289 290 /* Bandwidth limit information */ 291 struct i40e_bw_info { 292 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 293 uint8_t bw_max; /* Max BW limit if enabled */ 294 295 /* Relative credits within same TC with respect to other VSIs or Comps */ 296 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 297 /* Bandwidth limit per TC */ 298 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 299 /* Max bandwidth limit per TC */ 300 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 301 }; 302 303 /* Structure that defines a VEB */ 304 struct i40e_veb { 305 struct i40e_vsi_list_head head; 306 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 307 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 308 uint16_t seid; /* The seid of VEB itself */ 309 uint16_t uplink_seid; /* The uplink seid of this VEB */ 310 uint16_t stats_idx; 311 struct i40e_eth_stats stats; 312 uint8_t enabled_tc; /* The traffic class enabled */ 313 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 314 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 315 }; 316 317 /* i40e MACVLAN filter structure */ 318 struct i40e_macvlan_filter { 319 struct ether_addr macaddr; 320 enum rte_mac_filter_type filter_type; 321 uint16_t vlan_id; 322 }; 323 324 /* 325 * Structure that defines a VSI, associated with a adapter. 326 */ 327 struct i40e_vsi { 328 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 329 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 330 331 struct i40e_eth_stats eth_stats_offset; 332 struct i40e_eth_stats eth_stats; 333 /* 334 * When drivers loaded, only a default main VSI exists. In case new VSI 335 * needs to add, HW needs to know the layout that VSIs are organized. 336 * Besides that, VSI isan element and can't switch packets, which needs 337 * to add new component VEB to perform switching. So, a new VSI needs 338 * to specify the uplink VSI (Parent VSI) before created. The 339 * uplink VSI will check whether it had a VEB to switch packets. If no, 340 * it will try to create one. Then, uplink VSI will move the new VSI 341 * into its' sib_vsi_list to manage all the downlink VSI. 342 * sib_vsi_list: the VSI list that shared the same uplink VSI. 343 * parent_vsi : the uplink VSI. It's NULL for main VSI. 344 * veb : the VEB associates with the VSI. 345 */ 346 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 347 struct i40e_vsi *parent_vsi; 348 struct i40e_veb *veb; /* Associated veb, could be null */ 349 struct i40e_veb *floating_veb; /* Associated floating veb */ 350 bool offset_loaded; 351 enum i40e_vsi_type type; /* VSI types */ 352 uint16_t vlan_num; /* Total VLAN number */ 353 uint16_t mac_num; /* Total mac number */ 354 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 355 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 356 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 357 uint32_t user_param; 358 uint16_t seid; /* The seid of VSI itself */ 359 uint16_t uplink_seid; /* The uplink seid of this VSI */ 360 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 361 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 362 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 363 uint16_t base_queue; /* The first queue index of this VSI */ 364 /* 365 * The offset to visit VSI related register, assigned by HW when 366 * creating VSI 367 */ 368 uint16_t vsi_id; 369 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 370 uint16_t nb_msix; /* The max number of msix vector */ 371 uint8_t enabled_tc; /* The traffic class enabled */ 372 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 373 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 374 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 375 }; 376 377 struct pool_entry { 378 LIST_ENTRY(pool_entry) next; 379 uint16_t base; 380 uint16_t len; 381 }; 382 383 LIST_HEAD(res_list, pool_entry); 384 385 struct i40e_res_pool_info { 386 uint32_t base; /* Resource start index */ 387 uint32_t num_alloc; /* Allocated resource number */ 388 uint32_t num_free; /* Total available resource number */ 389 struct res_list alloc_list; /* Allocated resource list */ 390 struct res_list free_list; /* Available resource list */ 391 }; 392 393 enum I40E_VF_STATE { 394 I40E_VF_INACTIVE = 0, 395 I40E_VF_INRESET, 396 I40E_VF_ININIT, 397 I40E_VF_ACTIVE, 398 }; 399 400 /* 401 * Structure to store private data for PF host. 402 */ 403 struct i40e_pf_vf { 404 struct i40e_pf *pf; 405 struct i40e_vsi *vsi; 406 enum I40E_VF_STATE state; /* The number of queue pairs available */ 407 uint16_t vf_idx; /* VF index in pf->vfs */ 408 uint16_t lan_nb_qps; /* Actual queues allocated */ 409 uint16_t reset_cnt; /* Total vf reset times */ 410 struct ether_addr mac_addr; /* Default MAC address */ 411 /* version of the virtchnl from VF */ 412 struct virtchnl_version_info version; 413 uint32_t request_caps; /* offload caps requested from VF */ 414 }; 415 416 /* 417 * Structure to store private data for flow control. 418 */ 419 struct i40e_fc_conf { 420 uint16_t pause_time; /* Flow control pause timer */ 421 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 422 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 423 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 424 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 425 }; 426 427 /* 428 * Structure to store private data for VMDQ instance 429 */ 430 struct i40e_vmdq_info { 431 struct i40e_pf *pf; 432 struct i40e_vsi *vsi; 433 }; 434 435 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 436 #define I40E_MAX_FLX_SOURCE_OFF 480 437 #define NONUSE_FLX_PIT_DEST_OFF 63 438 #define NONUSE_FLX_PIT_FSIZE 1 439 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 440 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 441 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 442 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 443 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 444 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 445 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 446 NONUSE_FLX_PIT_DEST_OFF : \ 447 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 448 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 449 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 450 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 451 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 452 #define I40E_FDIR_IPv6_TC_OFFSET 20 453 454 /* A structure used to define the input for GTP flow */ 455 struct i40e_gtp_flow { 456 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 457 uint8_t msg_type; /* Message type. */ 458 uint32_t teid; /* TEID in big endian. */ 459 }; 460 461 /* A structure used to define the input for GTP IPV4 flow */ 462 struct i40e_gtp_ipv4_flow { 463 struct i40e_gtp_flow gtp; 464 struct rte_eth_ipv4_flow ip4; 465 }; 466 467 /* A structure used to define the input for GTP IPV6 flow */ 468 struct i40e_gtp_ipv6_flow { 469 struct i40e_gtp_flow gtp; 470 struct rte_eth_ipv6_flow ip6; 471 }; 472 473 /* A structure used to define the input for raw type flow */ 474 struct i40e_raw_flow { 475 uint16_t pctype; 476 void *packet; 477 uint32_t length; 478 }; 479 480 /* 481 * A union contains the inputs for all types of flow 482 * items in flows need to be in big endian 483 */ 484 union i40e_fdir_flow { 485 struct rte_eth_l2_flow l2_flow; 486 struct rte_eth_udpv4_flow udp4_flow; 487 struct rte_eth_tcpv4_flow tcp4_flow; 488 struct rte_eth_sctpv4_flow sctp4_flow; 489 struct rte_eth_ipv4_flow ip4_flow; 490 struct rte_eth_udpv6_flow udp6_flow; 491 struct rte_eth_tcpv6_flow tcp6_flow; 492 struct rte_eth_sctpv6_flow sctp6_flow; 493 struct rte_eth_ipv6_flow ipv6_flow; 494 struct i40e_gtp_flow gtp_flow; 495 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 496 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 497 struct i40e_raw_flow raw_flow; 498 }; 499 500 enum i40e_fdir_ip_type { 501 I40E_FDIR_IPTYPE_IPV4, 502 I40E_FDIR_IPTYPE_IPV6, 503 }; 504 505 /* A structure used to contain extend input of flow */ 506 struct i40e_fdir_flow_ext { 507 uint16_t vlan_tci; 508 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 509 /* It is filled by the flexible payload to match. */ 510 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 511 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 512 bool inner_ip; /* If there is inner ip */ 513 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 514 bool customized_pctype; /* If customized pctype is used */ 515 bool pkt_template; /* If raw packet template is used */ 516 }; 517 518 /* A structure used to define the input for a flow director filter entry */ 519 struct i40e_fdir_input { 520 enum i40e_filter_pctype pctype; 521 union i40e_fdir_flow flow; 522 /* Flow fields to match, dependent on flow_type */ 523 struct i40e_fdir_flow_ext flow_ext; 524 /* Additional fields to match */ 525 }; 526 527 /* Behavior will be taken if FDIR match */ 528 enum i40e_fdir_behavior { 529 I40E_FDIR_ACCEPT = 0, 530 I40E_FDIR_REJECT, 531 I40E_FDIR_PASSTHRU, 532 }; 533 534 /* Flow director report status 535 * It defines what will be reported if FDIR entry is matched. 536 */ 537 enum i40e_fdir_status { 538 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 539 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 540 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 541 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 542 }; 543 544 /* A structure used to define an action when match FDIR packet filter. */ 545 struct i40e_fdir_action { 546 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 547 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 548 enum i40e_fdir_status report_status; /* Status report option */ 549 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 550 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 551 * flex bytes start from in flexible payload. 552 */ 553 uint8_t flex_off; 554 }; 555 556 /* A structure used to define the flow director filter entry by filter_ctrl API 557 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and 558 * RTE_ETH_FILTER_DELETE operations. 559 */ 560 struct i40e_fdir_filter_conf { 561 uint32_t soft_id; 562 /* ID, an unique value is required when deal with FDIR entry */ 563 struct i40e_fdir_input input; /* Input set */ 564 struct i40e_fdir_action action; /* Action taken when match */ 565 }; 566 567 /* 568 * Structure to store flex pit for flow diretor. 569 */ 570 struct i40e_fdir_flex_pit { 571 uint8_t src_offset; /* offset in words from the beginning of payload */ 572 uint8_t size; /* size in words */ 573 uint8_t dst_offset; /* offset in words of flexible payload */ 574 }; 575 576 struct i40e_fdir_flex_mask { 577 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 578 uint8_t nb_bitmask; 579 struct { 580 uint8_t offset; 581 uint16_t mask; 582 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 583 }; 584 585 #define I40E_FILTER_PCTYPE_INVALID 0 586 #define I40E_FILTER_PCTYPE_MAX 64 587 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 588 589 struct i40e_fdir_filter { 590 TAILQ_ENTRY(i40e_fdir_filter) rules; 591 struct i40e_fdir_filter_conf fdir; 592 }; 593 594 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 595 /* 596 * A structure used to define fields of a FDIR related info. 597 */ 598 struct i40e_fdir_info { 599 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 600 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 601 struct i40e_tx_queue *txq; 602 struct i40e_rx_queue *rxq; 603 void *prg_pkt; /* memory for fdir program packet */ 604 uint64_t dma_addr; /* physic address of packet memory*/ 605 /* input set bits for each pctype */ 606 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 607 /* 608 * the rule how bytes stream is extracted as flexible payload 609 * for each payload layer, the setting can up to three elements 610 */ 611 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 612 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 613 614 struct i40e_fdir_filter_list fdir_list; 615 struct i40e_fdir_filter **hash_map; 616 struct rte_hash *hash_table; 617 618 /* Mark if flex pit and mask is set */ 619 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 620 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 621 622 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */ 623 }; 624 625 /* Ethertype filter number HW supports */ 626 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 627 628 /* Ethertype filter struct */ 629 struct i40e_ethertype_filter_input { 630 struct ether_addr mac_addr; /* Mac address to match */ 631 uint16_t ether_type; /* Ether type to match */ 632 }; 633 634 struct i40e_ethertype_filter { 635 TAILQ_ENTRY(i40e_ethertype_filter) rules; 636 struct i40e_ethertype_filter_input input; 637 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 638 uint16_t queue; /* Queue assigned to when match */ 639 }; 640 641 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 642 643 struct i40e_ethertype_rule { 644 struct i40e_ethertype_filter_list ethertype_list; 645 struct i40e_ethertype_filter **hash_map; 646 struct rte_hash *hash_table; 647 }; 648 649 /* queue region info */ 650 struct i40e_queue_region_info { 651 /* the region id for this configuration */ 652 uint8_t region_id; 653 /* the start queue index for this region */ 654 uint8_t queue_start_index; 655 /* the total queue number of this queue region */ 656 uint8_t queue_num; 657 /* the total number of user priority for this region */ 658 uint8_t user_priority_num; 659 /* the packet's user priority for this region */ 660 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 661 /* the total number of flowtype for this region */ 662 uint8_t flowtype_num; 663 /** 664 * the pctype or hardware flowtype of packet, 665 * the specific index for each type has been defined 666 * in file i40e_type.h as enum i40e_filter_pctype. 667 */ 668 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 669 }; 670 671 struct i40e_queue_regions { 672 /* the total number of queue region for this port */ 673 uint16_t queue_region_number; 674 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 675 }; 676 677 /* Tunnel filter number HW supports */ 678 #define I40E_MAX_TUNNEL_FILTER_NUM 400 679 680 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 681 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 682 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 683 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 684 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 685 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 686 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 687 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 688 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 689 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 690 #define I40E_AQC_NEW_TR_21 21 691 #define I40E_AQC_NEW_TR_22 22 692 693 enum i40e_tunnel_iptype { 694 I40E_TUNNEL_IPTYPE_IPV4, 695 I40E_TUNNEL_IPTYPE_IPV6, 696 }; 697 698 /* Tunnel filter struct */ 699 struct i40e_tunnel_filter_input { 700 uint8_t outer_mac[6]; /* Outer mac address to match */ 701 uint8_t inner_mac[6]; /* Inner mac address to match */ 702 uint16_t inner_vlan; /* Inner vlan address to match */ 703 enum i40e_tunnel_iptype ip_type; 704 uint16_t flags; /* Filter type flag */ 705 uint32_t tenant_id; /* Tenant id to match */ 706 uint16_t general_fields[32]; /* Big buffer */ 707 }; 708 709 struct i40e_tunnel_filter { 710 TAILQ_ENTRY(i40e_tunnel_filter) rules; 711 struct i40e_tunnel_filter_input input; 712 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 713 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 714 uint16_t queue; /* Queue assigned to when match */ 715 }; 716 717 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 718 719 struct i40e_tunnel_rule { 720 struct i40e_tunnel_filter_list tunnel_list; 721 struct i40e_tunnel_filter **hash_map; 722 struct rte_hash *hash_table; 723 }; 724 725 /** 726 * Tunnel type. 727 */ 728 enum i40e_tunnel_type { 729 I40E_TUNNEL_TYPE_NONE = 0, 730 I40E_TUNNEL_TYPE_VXLAN, 731 I40E_TUNNEL_TYPE_GENEVE, 732 I40E_TUNNEL_TYPE_TEREDO, 733 I40E_TUNNEL_TYPE_NVGRE, 734 I40E_TUNNEL_TYPE_IP_IN_GRE, 735 I40E_L2_TUNNEL_TYPE_E_TAG, 736 I40E_TUNNEL_TYPE_MPLSoUDP, 737 I40E_TUNNEL_TYPE_MPLSoGRE, 738 I40E_TUNNEL_TYPE_QINQ, 739 I40E_TUNNEL_TYPE_GTPC, 740 I40E_TUNNEL_TYPE_GTPU, 741 I40E_TUNNEL_TYPE_MAX, 742 }; 743 744 /** 745 * Tunneling Packet filter configuration. 746 */ 747 struct i40e_tunnel_filter_conf { 748 struct ether_addr outer_mac; /**< Outer MAC address to match. */ 749 struct ether_addr inner_mac; /**< Inner MAC address to match. */ 750 uint16_t inner_vlan; /**< Inner VLAN to match. */ 751 uint32_t outer_vlan; /**< Outer VLAN to match */ 752 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 753 /** 754 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 755 * is set in filter_type, or inner destination IP address to match 756 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 757 */ 758 union { 759 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 760 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 761 } ip_addr; 762 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 763 uint16_t filter_type; 764 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 765 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 766 uint16_t queue_id; /**< Queue assigned to if match. */ 767 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 768 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 769 }; 770 771 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 772 #define I40E_MAX_MIRROR_RULES 64 773 /* 774 * Mirror rule structure 775 */ 776 struct i40e_mirror_rule { 777 TAILQ_ENTRY(i40e_mirror_rule) rules; 778 uint8_t rule_type; 779 uint16_t index; /* the sw index of mirror rule */ 780 uint16_t id; /* the rule id assigned by firmware */ 781 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 782 uint16_t num_entries; 783 /* the info stores depend on the rule type. 784 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 785 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 786 */ 787 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 788 }; 789 790 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 791 792 /* 793 * Struct to store flow created. 794 */ 795 struct rte_flow { 796 TAILQ_ENTRY(rte_flow) node; 797 enum rte_filter_type filter_type; 798 void *rule; 799 }; 800 801 TAILQ_HEAD(i40e_flow_list, rte_flow); 802 803 /* Struct to store Traffic Manager shaper profile. */ 804 struct i40e_tm_shaper_profile { 805 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 806 uint32_t shaper_profile_id; 807 uint32_t reference_count; 808 struct rte_tm_shaper_params profile; 809 }; 810 811 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 812 813 /* node type of Traffic Manager */ 814 enum i40e_tm_node_type { 815 I40E_TM_NODE_TYPE_PORT, 816 I40E_TM_NODE_TYPE_TC, 817 I40E_TM_NODE_TYPE_QUEUE, 818 I40E_TM_NODE_TYPE_MAX, 819 }; 820 821 /* Struct to store Traffic Manager node configuration. */ 822 struct i40e_tm_node { 823 TAILQ_ENTRY(i40e_tm_node) node; 824 uint32_t id; 825 uint32_t priority; 826 uint32_t weight; 827 uint32_t reference_count; 828 struct i40e_tm_node *parent; 829 struct i40e_tm_shaper_profile *shaper_profile; 830 struct rte_tm_node_params params; 831 }; 832 833 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 834 835 /* Struct to store all the Traffic Manager configuration. */ 836 struct i40e_tm_conf { 837 struct i40e_shaper_profile_list shaper_profile_list; 838 struct i40e_tm_node *root; /* root node - port */ 839 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 840 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 841 /** 842 * The number of added TC nodes. 843 * It should be no more than the TC number of this port. 844 */ 845 uint32_t nb_tc_node; 846 /** 847 * The number of added queue nodes. 848 * It should be no more than the queue number of this port. 849 */ 850 uint32_t nb_queue_node; 851 /** 852 * This flag is used to check if APP can change the TM node 853 * configuration. 854 * When it's true, means the configuration is applied to HW, 855 * APP should not change the configuration. 856 * As we don't support on-the-fly configuration, when starting 857 * the port, APP should call the hierarchy_commit API to set this 858 * flag to true. When stopping the port, this flag should be set 859 * to false. 860 */ 861 bool committed; 862 }; 863 864 enum i40e_new_pctype { 865 I40E_CUSTOMIZED_GTPC = 0, 866 I40E_CUSTOMIZED_GTPU_IPV4, 867 I40E_CUSTOMIZED_GTPU_IPV6, 868 I40E_CUSTOMIZED_GTPU, 869 I40E_CUSTOMIZED_MAX, 870 }; 871 872 #define I40E_FILTER_PCTYPE_INVALID 0 873 struct i40e_customized_pctype { 874 enum i40e_new_pctype index; /* Indicate which customized pctype */ 875 uint8_t pctype; /* New pctype value */ 876 bool valid; /* Check if it's valid */ 877 }; 878 879 struct i40e_rte_flow_rss_conf { 880 struct rte_eth_rss_conf rss_conf; /**< RSS parameters. */ 881 uint16_t queue_region_conf; /**< Queue region config flag */ 882 uint16_t num; /**< Number of entries in queue[]. */ 883 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */ 884 }; 885 886 /* 887 * Structure to store private data specific for PF instance. 888 */ 889 struct i40e_pf { 890 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 891 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 892 uint16_t mac_seid; /* The seid of the MAC of this PF */ 893 uint16_t main_vsi_seid; /* The seid of the main VSI */ 894 uint16_t max_num_vsi; 895 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 896 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 897 898 struct i40e_hw_port_stats stats_offset; 899 struct i40e_hw_port_stats stats; 900 /* internal packet statistics, it should be excluded from the total */ 901 struct i40e_eth_stats internal_stats_offset; 902 struct i40e_eth_stats internal_stats; 903 bool offset_loaded; 904 905 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 906 struct ether_addr dev_addr; /* PF device mac address */ 907 uint64_t flags; /* PF feature flags */ 908 /* All kinds of queue pair setting for different VSIs */ 909 struct i40e_pf_vf *vfs; 910 uint16_t vf_num; 911 /* Each of below queue pairs should be power of 2 since it's the 912 precondition after TC configuration applied */ 913 uint16_t lan_nb_qp_max; 914 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 915 uint16_t lan_qp_offset; 916 uint16_t vmdq_nb_qp_max; 917 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 918 uint16_t vmdq_qp_offset; 919 uint16_t vf_nb_qp_max; 920 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 921 uint16_t vf_qp_offset; 922 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 923 uint16_t fdir_qp_offset; 924 925 uint16_t hash_lut_size; /* The size of hash lookup table */ 926 /* input set bits for each pctype */ 927 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 928 /* store VXLAN UDP ports */ 929 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 930 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 931 932 /* VMDQ related info */ 933 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 934 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 935 struct i40e_vmdq_info *vmdq; 936 937 struct i40e_fdir_info fdir; /* flow director info */ 938 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 939 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 940 struct i40e_rte_flow_rss_conf rss_info; /* rss info */ 941 struct i40e_queue_regions queue_region; /* queue region info */ 942 struct i40e_fc_conf fc_conf; /* Flow control conf */ 943 struct i40e_mirror_rule_list mirror_list; 944 uint16_t nb_mirror_rule; /* The number of mirror rules */ 945 bool floating_veb; /* The flag to use the floating VEB */ 946 /* The floating enable flag for the specific VF */ 947 bool floating_veb_list[I40E_MAX_VF]; 948 struct i40e_flow_list flow_list; 949 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 950 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 951 bool qinq_replace_flag; /* QINQ filter replace is done */ 952 struct i40e_tm_conf tm_conf; 953 bool support_multi_driver; /* 1 - support multiple driver */ 954 955 /* Dynamic Device Personalization */ 956 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 957 /* customer customized pctype */ 958 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 959 }; 960 961 enum pending_msg { 962 PFMSG_LINK_CHANGE = 0x1, 963 PFMSG_RESET_IMPENDING = 0x2, 964 PFMSG_DRIVER_CLOSE = 0x4, 965 }; 966 967 struct i40e_vsi_vlan_pvid_info { 968 uint16_t on; /* Enable or disable pvid */ 969 union { 970 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 971 struct { 972 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 973 * while 'untagged' will reject untagged packets. 974 */ 975 uint8_t tagged; 976 uint8_t untagged; 977 } reject; 978 } config; 979 }; 980 981 struct i40e_vf_rx_queues { 982 uint64_t rx_dma_addr; 983 uint32_t rx_ring_len; 984 uint32_t buff_size; 985 }; 986 987 struct i40e_vf_tx_queues { 988 uint64_t tx_dma_addr; 989 uint32_t tx_ring_len; 990 }; 991 992 /* 993 * Structure to store private data specific for VF instance. 994 */ 995 struct i40e_vf { 996 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 997 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 998 uint16_t num_queue_pairs; 999 uint16_t max_pkt_len; /* Maximum packet length */ 1000 bool promisc_unicast_enabled; 1001 bool promisc_multicast_enabled; 1002 1003 uint32_t version_major; /* Major version number */ 1004 uint32_t version_minor; /* Minor version number */ 1005 uint16_t promisc_flags; /* Promiscuous setting */ 1006 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1007 1008 struct ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; /* Multicast addrs */ 1009 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1010 1011 /* Event from pf */ 1012 bool dev_closed; 1013 bool link_up; 1014 enum virtchnl_link_speed link_speed; 1015 bool vf_reset; 1016 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1017 int32_t cmd_retval; /* return value of the cmd response from PF */ 1018 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1019 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1020 1021 /* VSI info */ 1022 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1023 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1024 struct i40e_vsi vsi; 1025 uint64_t flags; 1026 }; 1027 1028 #define I40E_MAX_PKT_TYPE 256 1029 #define I40E_FLOW_TYPE_MAX 64 1030 1031 /* 1032 * Structure to store private data for each PF/VF instance. 1033 */ 1034 struct i40e_adapter { 1035 /* Common for both PF and VF */ 1036 struct i40e_hw hw; 1037 struct rte_eth_dev *eth_dev; 1038 1039 /* Specific for PF or VF */ 1040 union { 1041 struct i40e_pf pf; 1042 struct i40e_vf vf; 1043 }; 1044 1045 /* For vector PMD */ 1046 bool rx_bulk_alloc_allowed; 1047 bool rx_vec_allowed; 1048 bool tx_simple_allowed; 1049 bool tx_vec_allowed; 1050 1051 /* For PTP */ 1052 struct rte_timecounter systime_tc; 1053 struct rte_timecounter rx_tstamp_tc; 1054 struct rte_timecounter tx_tstamp_tc; 1055 1056 /* ptype mapping table */ 1057 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1058 /* flow type to pctype mapping table */ 1059 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1060 uint64_t flow_types_mask; 1061 uint64_t pctypes_mask; 1062 }; 1063 1064 extern const struct rte_flow_ops i40e_flow_ops; 1065 1066 union i40e_filter_t { 1067 struct rte_eth_ethertype_filter ethertype_filter; 1068 struct i40e_fdir_filter_conf fdir_filter; 1069 struct rte_eth_tunnel_filter_conf tunnel_filter; 1070 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1071 struct i40e_rte_flow_rss_conf rss_conf; 1072 }; 1073 1074 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1075 const struct rte_flow_attr *attr, 1076 const struct rte_flow_item pattern[], 1077 const struct rte_flow_action actions[], 1078 struct rte_flow_error *error, 1079 union i40e_filter_t *filter); 1080 struct i40e_valid_pattern { 1081 enum rte_flow_item_type *items; 1082 parse_filter_t parse_filter; 1083 }; 1084 1085 enum I40E_WARNING_IDX { 1086 I40E_WARNING_DIS_FLX_PLD, 1087 I40E_WARNING_ENA_FLX_PLD, 1088 I40E_WARNING_QINQ_PARSER, 1089 I40E_WARNING_QINQ_CLOUD_FILTER, 1090 I40E_WARNING_TPID, 1091 I40E_WARNING_FLOW_CTL, 1092 I40E_WARNING_GRE_KEY_LEN, 1093 I40E_WARNING_QF_CTL, 1094 I40E_WARNING_HASH_INSET, 1095 I40E_WARNING_HSYM, 1096 I40E_WARNING_HASH_MSK, 1097 I40E_WARNING_FD_MSK, 1098 I40E_WARNING_RPL_CLD_FILTER, 1099 }; 1100 1101 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1102 int i40e_vsi_release(struct i40e_vsi *vsi); 1103 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1104 enum i40e_vsi_type type, 1105 struct i40e_vsi *uplink_vsi, 1106 uint16_t user_param); 1107 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1108 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1109 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1110 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1111 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1112 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr); 1113 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1114 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1115 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1116 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1117 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1118 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1119 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1120 struct i40e_vsi_vlan_pvid_info *info); 1121 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1122 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1123 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1124 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1125 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1126 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1127 int i40e_fdir_setup(struct i40e_pf *pf); 1128 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1129 uint32_t len, 1130 int socket_id); 1131 int i40e_fdir_configure(struct rte_eth_dev *dev); 1132 void i40e_fdir_teardown(struct i40e_pf *pf); 1133 enum i40e_filter_pctype 1134 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1135 uint16_t flow_type); 1136 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1137 enum i40e_filter_pctype pctype); 1138 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev, 1139 enum rte_filter_op filter_op, 1140 void *arg); 1141 int i40e_select_filter_input_set(struct i40e_hw *hw, 1142 struct rte_eth_input_set_conf *conf, 1143 enum rte_filter_type filter); 1144 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1145 int i40e_hash_filter_inset_select(struct i40e_hw *hw, 1146 struct rte_eth_input_set_conf *conf); 1147 int i40e_fdir_filter_inset_select(struct i40e_pf *pf, 1148 struct rte_eth_input_set_conf *conf); 1149 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1150 uint32_t retval, uint8_t *msg, 1151 uint16_t msglen); 1152 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1153 struct rte_eth_rxq_info *qinfo); 1154 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1155 struct rte_eth_txq_info *qinfo); 1156 struct i40e_ethertype_filter * 1157 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1158 const struct i40e_ethertype_filter_input *input); 1159 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1160 struct i40e_ethertype_filter_input *input); 1161 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1162 struct i40e_fdir_input *input); 1163 struct i40e_tunnel_filter * 1164 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1165 const struct i40e_tunnel_filter_input *input); 1166 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1167 struct i40e_tunnel_filter_input *input); 1168 uint64_t i40e_get_default_input_set(uint16_t pctype); 1169 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1170 struct rte_eth_ethertype_filter *filter, 1171 bool add); 1172 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev, 1173 const struct rte_eth_fdir_filter *filter, 1174 bool add); 1175 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1176 const struct i40e_fdir_filter_conf *filter, 1177 bool add); 1178 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1179 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1180 uint8_t add); 1181 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1182 struct i40e_tunnel_filter_conf *tunnel_filter, 1183 uint8_t add); 1184 int i40e_fdir_flush(struct rte_eth_dev *dev); 1185 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1186 struct i40e_macvlan_filter *mv_f, 1187 int num, struct ether_addr *addr); 1188 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1189 struct i40e_macvlan_filter *filter, 1190 int total); 1191 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1192 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1193 struct i40e_macvlan_filter *filter, 1194 int total); 1195 bool is_i40e_supported(struct rte_eth_dev *dev); 1196 1197 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1198 enum rte_filter_type filter, uint64_t inset); 1199 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, 1200 uint8_t nb_elem); 1201 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1202 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1203 void i40e_check_write_global_reg(struct i40e_hw *hw, 1204 uint32_t addr, uint32_t val); 1205 1206 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1207 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1208 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1209 struct i40e_customized_pctype* 1210 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1211 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1212 uint32_t pkg_size); 1213 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1214 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1215 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1216 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1217 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1218 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1219 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1220 int i40e_config_rss_filter(struct i40e_pf *pf, 1221 struct i40e_rte_flow_rss_conf *conf, bool add); 1222 1223 #define I40E_DEV_TO_PCI(eth_dev) \ 1224 RTE_DEV_TO_PCI((eth_dev)->device) 1225 1226 /* I40E_DEV_PRIVATE_TO */ 1227 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1228 (&((struct i40e_adapter *)adapter)->pf) 1229 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1230 (&((struct i40e_adapter *)adapter)->hw) 1231 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1232 ((struct i40e_adapter *)adapter) 1233 1234 /* I40EVF_DEV_PRIVATE_TO */ 1235 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1236 (&((struct i40e_adapter *)adapter)->vf) 1237 1238 static inline struct i40e_vsi * 1239 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1240 { 1241 struct i40e_hw *hw; 1242 1243 if (!adapter) 1244 return NULL; 1245 1246 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1247 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1248 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1249 return &vf->vsi; 1250 } else { 1251 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1252 return pf->main_vsi; 1253 } 1254 } 1255 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1256 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1257 1258 /* I40E_VSI_TO */ 1259 #define I40E_VSI_TO_HW(vsi) \ 1260 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1261 #define I40E_VSI_TO_PF(vsi) \ 1262 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1263 #define I40E_VSI_TO_VF(vsi) \ 1264 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1265 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1266 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1267 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1268 (((struct i40e_vsi *)vsi)->adapter->eth_dev) 1269 1270 /* I40E_PF_TO */ 1271 #define I40E_PF_TO_HW(pf) \ 1272 (&(((struct i40e_pf *)pf)->adapter->hw)) 1273 #define I40E_PF_TO_ADAPTER(pf) \ 1274 ((struct i40e_adapter *)pf->adapter) 1275 1276 /* I40E_VF_TO */ 1277 #define I40E_VF_TO_HW(vf) \ 1278 (&(((struct i40e_vf *)vf)->adapter->hw)) 1279 1280 static inline void 1281 i40e_init_adminq_parameter(struct i40e_hw *hw) 1282 { 1283 hw->aq.num_arq_entries = I40E_AQ_LEN; 1284 hw->aq.num_asq_entries = I40E_AQ_LEN; 1285 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1286 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1287 } 1288 1289 static inline int 1290 i40e_align_floor(int n) 1291 { 1292 if (n == 0) 1293 return 0; 1294 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1295 } 1296 1297 static inline uint16_t 1298 i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv) 1299 { 1300 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) { 1301 if (is_multi_drv) { 1302 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1303 } else { 1304 if (is_pf) 1305 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1306 else 1307 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1308 } 1309 } 1310 1311 /* Convert to hardware count, as writing each 1 represents 2 us */ 1312 return interval / 2; 1313 } 1314 1315 static inline void 1316 i40e_global_cfg_warning(enum I40E_WARNING_IDX idx) 1317 { 1318 const char *warning; 1319 static const char *const warning_list[] = { 1320 [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload", 1321 [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload", 1322 [I40E_WARNING_QINQ_PARSER] = "support QinQ parser", 1323 [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter", 1324 [I40E_WARNING_TPID] = "support TPID configuration", 1325 [I40E_WARNING_FLOW_CTL] = "configure water marker", 1326 [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting", 1327 [I40E_WARNING_QF_CTL] = "support hash function setting", 1328 [I40E_WARNING_HASH_INSET] = "configure hash input set", 1329 [I40E_WARNING_HSYM] = "set symmetric hash", 1330 [I40E_WARNING_HASH_MSK] = "configure hash mask", 1331 [I40E_WARNING_FD_MSK] = "configure fdir mask", 1332 [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter", 1333 }; 1334 1335 warning = warning_list[idx]; 1336 1337 RTE_LOG(WARNING, PMD, 1338 "Global register is changed during %s\n", 1339 warning); 1340 } 1341 1342 #define I40E_VALID_FLOW(flow_type) \ 1343 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1344 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1345 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1346 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1347 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1348 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1349 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1350 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1351 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1352 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1353 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1354 1355 #define I40E_VALID_PCTYPE_X722(pctype) \ 1356 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1357 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1358 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1359 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1360 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1361 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1362 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1363 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1364 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1365 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1366 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1367 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1368 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1369 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1370 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1371 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1372 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1373 1374 #define I40E_VALID_PCTYPE(pctype) \ 1375 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1376 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1377 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1378 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1379 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1380 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1381 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1382 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1383 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1384 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1385 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1386 1387 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1388 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1389 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1390 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1391 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1392 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1393 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1394 1395 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1396 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1397 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1398 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1399 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR)) 1400 1401 #endif /* _I40E_ETHDEV_H_ */ 1402