1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 #include <sys/queue.h> 10 11 #include <rte_time.h> 12 #include <rte_kvargs.h> 13 #include <rte_hash.h> 14 #include <rte_flow.h> 15 #include <rte_flow_driver.h> 16 #include <rte_tm_driver.h> 17 #include "rte_pmd_i40e.h" 18 19 #include "base/i40e_register.h" 20 #include "base/i40e_type.h" 21 #include "base/virtchnl.h" 22 23 /** 24 * _i=0...143, 25 * counters 0-127 are for the 128 VFs, 26 * counters 128-143 are for the 16 PFs 27 */ 28 #define I40E_GL_RXERR1_H(_i) (0x00318004 + ((_i) * 8)) 29 30 #define I40E_VLAN_TAG_SIZE 4 31 32 #define I40E_AQ_LEN 32 33 #define I40E_AQ_BUF_SZ 4096 34 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 35 #define I40E_MAX_Q_PER_TC 64 36 #define I40E_NUM_DESC_DEFAULT 512 37 #define I40E_NUM_DESC_ALIGN 32 38 #define I40E_BUF_SIZE_MIN 1024 39 #define I40E_FRAME_SIZE_MAX 9728 40 #define I40E_TSO_FRAME_SIZE_MAX 262144 41 #define I40E_QUEUE_BASE_ADDR_UNIT 128 42 /* number of VSIs and queue default setting */ 43 #define I40E_MAX_QP_NUM_PER_VF 16 44 #define I40E_DEFAULT_QP_NUM_FDIR 1 45 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 46 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 47 /* Maximun number of MAC addresses */ 48 #define I40E_NUM_MACADDR_MAX 64 49 /* Maximum number of VFs */ 50 #define I40E_MAX_VF 128 51 /*flag of no loopback*/ 52 #define I40E_AQ_LB_MODE_NONE 0x0 53 /* 54 * vlan_id is a 12 bit number. 55 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 56 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 57 * The higher 7 bit val specifies VFTA array index. 58 */ 59 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 60 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 61 62 /* Default TC traffic in case DCB is not enabled */ 63 #define I40E_DEFAULT_TCMAP 0x1 64 #define I40E_FDIR_QUEUE_ID 0 65 66 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 67 #define I40E_VMDQ_POOL_BASE 1 68 69 #define I40E_DEFAULT_RX_FREE_THRESH 32 70 #define I40E_DEFAULT_RX_PTHRESH 8 71 #define I40E_DEFAULT_RX_HTHRESH 8 72 #define I40E_DEFAULT_RX_WTHRESH 0 73 74 #define I40E_DEFAULT_TX_FREE_THRESH 32 75 #define I40E_DEFAULT_TX_PTHRESH 32 76 #define I40E_DEFAULT_TX_HTHRESH 0 77 #define I40E_DEFAULT_TX_WTHRESH 0 78 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 79 80 /* Bit shift and mask */ 81 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 82 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 83 #define I40E_8_BIT_WIDTH CHAR_BIT 84 #define I40E_8_BIT_MASK UINT8_MAX 85 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 86 #define I40E_16_BIT_MASK UINT16_MAX 87 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 88 #define I40E_32_BIT_MASK UINT32_MAX 89 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 90 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 91 92 /* Linux PF host with virtchnl version 1.1 */ 93 #define PF_IS_V11(vf) \ 94 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 95 ((vf)->version_minor == 1)) 96 97 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 98 do { \ 99 uint32_t ori_val; \ 100 struct rte_eth_dev *dev; \ 101 struct rte_eth_dev_data *dev_data; \ 102 ori_val = I40E_READ_REG((hw), (reg)); \ 103 dev_data = ((struct i40e_adapter *)hw->back)->pf.dev_data; \ 104 dev = &rte_eth_devices[dev_data->port_id]; \ 105 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 106 (reg)), (value)); \ 107 if (ori_val != value) \ 108 PMD_DRV_LOG(WARNING, \ 109 "i40e device %s changed global " \ 110 "register [0x%08x]. original: 0x%08x, " \ 111 "new: 0x%08x ", \ 112 (dev->device->name), (reg), \ 113 (ori_val), (value)); \ 114 } while (0) 115 116 /* index flex payload per layer */ 117 enum i40e_flxpld_layer_idx { 118 I40E_FLXPLD_L2_IDX = 0, 119 I40E_FLXPLD_L3_IDX = 1, 120 I40E_FLXPLD_L4_IDX = 2, 121 I40E_MAX_FLXPLD_LAYER = 3, 122 }; 123 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 124 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 125 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 126 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 127 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 128 129 /* i40e flags */ 130 #define I40E_FLAG_RSS (1ULL << 0) 131 #define I40E_FLAG_DCB (1ULL << 1) 132 #define I40E_FLAG_VMDQ (1ULL << 2) 133 #define I40E_FLAG_SRIOV (1ULL << 3) 134 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 135 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 136 #define I40E_FLAG_FDIR (1ULL << 6) 137 #define I40E_FLAG_VXLAN (1ULL << 7) 138 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 139 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 140 I40E_FLAG_DCB | \ 141 I40E_FLAG_VMDQ | \ 142 I40E_FLAG_SRIOV | \ 143 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 144 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 145 I40E_FLAG_FDIR | \ 146 I40E_FLAG_VXLAN | \ 147 I40E_FLAG_RSS_AQ_CAPABLE) 148 149 #define I40E_RSS_OFFLOAD_ALL ( \ 150 ETH_RSS_FRAG_IPV4 | \ 151 ETH_RSS_NONFRAG_IPV4_TCP | \ 152 ETH_RSS_NONFRAG_IPV4_UDP | \ 153 ETH_RSS_NONFRAG_IPV4_SCTP | \ 154 ETH_RSS_NONFRAG_IPV4_OTHER | \ 155 ETH_RSS_FRAG_IPV6 | \ 156 ETH_RSS_NONFRAG_IPV6_TCP | \ 157 ETH_RSS_NONFRAG_IPV6_UDP | \ 158 ETH_RSS_NONFRAG_IPV6_SCTP | \ 159 ETH_RSS_NONFRAG_IPV6_OTHER | \ 160 ETH_RSS_L2_PAYLOAD) 161 162 /* All bits of RSS hash enable for X722*/ 163 #define I40E_RSS_HENA_ALL_X722 ( \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 168 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 170 I40E_RSS_HENA_ALL) 171 172 /* All bits of RSS hash enable */ 173 #define I40E_RSS_HENA_ALL ( \ 174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 176 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 177 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 178 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 179 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 180 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 181 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 182 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 183 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 184 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 185 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 186 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 187 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 188 189 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 190 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 191 192 /* Default queue interrupt throttling time in microseconds */ 193 #define I40E_ITR_INDEX_DEFAULT 0 194 #define I40E_ITR_INDEX_NONE 3 195 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 196 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 197 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 198 /* Special FW support this floating VEB feature */ 199 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 200 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 201 202 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 203 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 204 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 205 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 206 207 #define I40E_RSS_TYPE_NONE 0ULL 208 #define I40E_RSS_TYPE_INVALID 1ULL 209 210 #define I40E_INSET_NONE 0x00000000000000000ULL 211 212 /* bit0 ~ bit 7 */ 213 #define I40E_INSET_DMAC 0x0000000000000001ULL 214 #define I40E_INSET_SMAC 0x0000000000000002ULL 215 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 216 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 217 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 218 219 /* bit 8 ~ bit 15 */ 220 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 221 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 222 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 223 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 224 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 225 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 226 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 227 228 /* bit 16 ~ bit 31 */ 229 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 230 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 231 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 232 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 233 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 234 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 235 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 236 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 237 238 /* bit 32 ~ bit 47, tunnel fields */ 239 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 240 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 241 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 242 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 243 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 244 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 245 246 /* bit 48 ~ bit 55 */ 247 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 248 249 /* bit 56 ~ bit 63, Flex Payload */ 250 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 251 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 252 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 253 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 254 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 255 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 256 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 257 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 258 #define I40E_INSET_FLEX_PAYLOAD \ 259 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 260 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 261 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 262 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 263 264 /* The max bandwidth of i40e is 40Gbps. */ 265 #define I40E_QOS_BW_MAX 40000 266 /* The bandwidth should be the multiple of 50Mbps. */ 267 #define I40E_QOS_BW_GRANULARITY 50 268 /* The min bandwidth weight is 1. */ 269 #define I40E_QOS_BW_WEIGHT_MIN 1 270 /* The max bandwidth weight is 127. */ 271 #define I40E_QOS_BW_WEIGHT_MAX 127 272 /* The max queue region index is 7. */ 273 #define I40E_REGION_MAX_INDEX 7 274 275 #define I40E_MAX_PERCENT 100 276 #define I40E_DEFAULT_DCB_APP_NUM 1 277 #define I40E_DEFAULT_DCB_APP_PRIO 3 278 279 #define I40E_FDIR_PRG_PKT_CNT 128 280 281 /* 282 * Struct to store flow created. 283 */ 284 struct rte_flow { 285 TAILQ_ENTRY(rte_flow) node; 286 enum rte_filter_type filter_type; 287 void *rule; 288 }; 289 290 /** 291 * The overhead from MTU to max frame size. 292 * Considering QinQ packet, the VLAN tag needs to be counted twice. 293 */ 294 #define I40E_ETH_OVERHEAD \ 295 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 296 #define I40E_ETH_MAX_LEN (RTE_ETHER_MTU + I40E_ETH_OVERHEAD) 297 298 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) 299 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) 300 301 struct i40e_adapter; 302 struct rte_pci_driver; 303 304 /** 305 * MAC filter type 306 */ 307 enum i40e_mac_filter_type { 308 I40E_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */ 309 I40E_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */ 310 I40E_MAC_HASH_MATCH, /**< hash match of MAC addr. */ 311 /** hash match of MAC addr and exact match of VLAN ID. */ 312 I40E_MACVLAN_HASH_MATCH, 313 }; 314 315 /** 316 * MAC filter structure 317 */ 318 struct i40e_mac_filter_info { 319 enum i40e_mac_filter_type filter_type; 320 struct rte_ether_addr mac_addr; 321 }; 322 323 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 324 325 /* MAC filter list structure */ 326 struct i40e_mac_filter { 327 TAILQ_ENTRY(i40e_mac_filter) next; 328 struct i40e_mac_filter_info mac_info; 329 }; 330 331 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 332 333 struct i40e_vsi; 334 335 /* VSI list structure */ 336 struct i40e_vsi_list { 337 TAILQ_ENTRY(i40e_vsi_list) list; 338 struct i40e_vsi *vsi; 339 }; 340 341 struct i40e_rx_queue; 342 struct i40e_tx_queue; 343 344 /* Bandwidth limit information */ 345 struct i40e_bw_info { 346 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 347 uint8_t bw_max; /* Max BW limit if enabled */ 348 349 /* Relative credits within same TC with respect to other VSIs or Comps */ 350 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 351 /* Bandwidth limit per TC */ 352 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 353 /* Max bandwidth limit per TC */ 354 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 355 }; 356 357 /* Structure that defines a VEB */ 358 struct i40e_veb { 359 struct i40e_vsi_list_head head; 360 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 361 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 362 uint16_t seid; /* The seid of VEB itself */ 363 uint16_t uplink_seid; /* The uplink seid of this VEB */ 364 uint16_t stats_idx; 365 struct i40e_eth_stats stats; 366 uint8_t enabled_tc; /* The traffic class enabled */ 367 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 368 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 369 }; 370 371 /* i40e MACVLAN filter structure */ 372 struct i40e_macvlan_filter { 373 struct rte_ether_addr macaddr; 374 enum i40e_mac_filter_type filter_type; 375 uint16_t vlan_id; 376 }; 377 378 /* 379 * Structure that defines a VSI, associated with a adapter. 380 */ 381 struct i40e_vsi { 382 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 383 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 384 385 struct i40e_eth_stats eth_stats_offset; 386 struct i40e_eth_stats eth_stats; 387 /* 388 * When drivers loaded, only a default main VSI exists. In case new VSI 389 * needs to add, HW needs to know the layout that VSIs are organized. 390 * Besides that, VSI isan element and can't switch packets, which needs 391 * to add new component VEB to perform switching. So, a new VSI needs 392 * to specify the uplink VSI (Parent VSI) before created. The 393 * uplink VSI will check whether it had a VEB to switch packets. If no, 394 * it will try to create one. Then, uplink VSI will move the new VSI 395 * into its' sib_vsi_list to manage all the downlink VSI. 396 * sib_vsi_list: the VSI list that shared the same uplink VSI. 397 * parent_vsi : the uplink VSI. It's NULL for main VSI. 398 * veb : the VEB associates with the VSI. 399 */ 400 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 401 struct i40e_vsi *parent_vsi; 402 struct i40e_veb *veb; /* Associated veb, could be null */ 403 struct i40e_veb *floating_veb; /* Associated floating veb */ 404 bool offset_loaded; 405 enum i40e_vsi_type type; /* VSI types */ 406 uint16_t vlan_num; /* Total VLAN number */ 407 uint16_t mac_num; /* Total mac number */ 408 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 409 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 410 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 411 uint32_t user_param; 412 uint16_t seid; /* The seid of VSI itself */ 413 uint16_t uplink_seid; /* The uplink seid of this VSI */ 414 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 415 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 416 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 417 uint16_t base_queue; /* The first queue index of this VSI */ 418 /* 419 * The offset to visit VSI related register, assigned by HW when 420 * creating VSI 421 */ 422 uint16_t vsi_id; 423 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 424 uint16_t nb_msix; /* The max number of msix vector */ 425 uint8_t enabled_tc; /* The traffic class enabled */ 426 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 427 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 428 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 429 uint64_t prev_rx_bytes; 430 uint64_t prev_tx_bytes; 431 }; 432 433 struct pool_entry { 434 LIST_ENTRY(pool_entry) next; 435 uint16_t base; 436 uint16_t len; 437 }; 438 439 LIST_HEAD(res_list, pool_entry); 440 441 struct i40e_res_pool_info { 442 uint32_t base; /* Resource start index */ 443 uint32_t num_alloc; /* Allocated resource number */ 444 uint32_t num_free; /* Total available resource number */ 445 struct res_list alloc_list; /* Allocated resource list */ 446 struct res_list free_list; /* Available resource list */ 447 }; 448 449 enum I40E_VF_STATE { 450 I40E_VF_INACTIVE = 0, 451 I40E_VF_INRESET, 452 I40E_VF_ININIT, 453 I40E_VF_ACTIVE, 454 }; 455 456 /* 457 * Structure to store private data for PF host. 458 */ 459 struct i40e_pf_vf { 460 struct i40e_pf *pf; 461 struct i40e_vsi *vsi; 462 enum I40E_VF_STATE state; /* The number of queue pairs available */ 463 uint16_t vf_idx; /* VF index in pf->vfs */ 464 uint16_t lan_nb_qps; /* Actual queues allocated */ 465 uint16_t reset_cnt; /* Total vf reset times */ 466 struct rte_ether_addr mac_addr; /* Default MAC address */ 467 /* version of the virtchnl from VF */ 468 struct virtchnl_version_info version; 469 uint32_t request_caps; /* offload caps requested from VF */ 470 uint64_t num_mdd_events; /* num of mdd events detected */ 471 472 /* 473 * Variables for store the arrival timestamp of VF messages. 474 * If the timestamp of latest message stored at 475 * `msg_timestamps[index % max]` then the timestamp of 476 * earliest message stored at `msg_time[(index + 1) % max]`. 477 * When a new message come, the timestamp of this message 478 * will be stored at `msg_timestamps[(index + 1) % max]` and the 479 * earliest message timestamp is at 480 * `msg_timestamps[(index + 2) % max]` now... 481 */ 482 uint32_t msg_index; 483 uint64_t *msg_timestamps; 484 485 /* cycle of stop ignoring VF message */ 486 uint64_t ignore_end_cycle; 487 }; 488 489 /* 490 * Structure to store private data for flow control. 491 */ 492 struct i40e_fc_conf { 493 uint16_t pause_time; /* Flow control pause timer */ 494 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 495 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 496 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 497 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 498 }; 499 500 /* 501 * Structure to store private data for VMDQ instance 502 */ 503 struct i40e_vmdq_info { 504 struct i40e_pf *pf; 505 struct i40e_vsi *vsi; 506 }; 507 508 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 509 #define I40E_MAX_FLX_SOURCE_OFF 480 510 #define NONUSE_FLX_PIT_DEST_OFF 63 511 #define NONUSE_FLX_PIT_FSIZE 1 512 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 513 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 514 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 515 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 516 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 517 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 518 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 519 NONUSE_FLX_PIT_DEST_OFF : \ 520 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 521 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 522 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 523 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 524 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 525 #define I40E_FDIR_IPv6_TC_OFFSET 20 526 527 /* A structure used to define the input for GTP flow */ 528 struct i40e_gtp_flow { 529 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 530 uint8_t msg_type; /* Message type. */ 531 uint32_t teid; /* TEID in big endian. */ 532 }; 533 534 /* A structure used to define the input for GTP IPV4 flow */ 535 struct i40e_gtp_ipv4_flow { 536 struct i40e_gtp_flow gtp; 537 struct rte_eth_ipv4_flow ip4; 538 }; 539 540 /* A structure used to define the input for GTP IPV6 flow */ 541 struct i40e_gtp_ipv6_flow { 542 struct i40e_gtp_flow gtp; 543 struct rte_eth_ipv6_flow ip6; 544 }; 545 546 /* A structure used to define the input for ESP IPV4 flow */ 547 struct i40e_esp_ipv4_flow { 548 struct rte_eth_ipv4_flow ipv4; 549 uint32_t spi; /* SPI in big endian. */ 550 }; 551 552 /* A structure used to define the input for ESP IPV6 flow */ 553 struct i40e_esp_ipv6_flow { 554 struct rte_eth_ipv6_flow ipv6; 555 uint32_t spi; /* SPI in big endian. */ 556 }; 557 /* A structure used to define the input for ESP IPV4 UDP flow */ 558 struct i40e_esp_ipv4_udp_flow { 559 struct rte_eth_udpv4_flow udp; 560 uint32_t spi; /* SPI in big endian. */ 561 }; 562 563 /* A structure used to define the input for ESP IPV6 UDP flow */ 564 struct i40e_esp_ipv6_udp_flow { 565 struct rte_eth_udpv6_flow udp; 566 uint32_t spi; /* SPI in big endian. */ 567 }; 568 569 /* A structure used to define the input for raw type flow */ 570 struct i40e_raw_flow { 571 uint16_t pctype; 572 void *packet; 573 uint32_t length; 574 }; 575 576 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 577 struct i40e_ipv4_l2tpv3oip_flow { 578 struct rte_eth_ipv4_flow ip4; 579 uint32_t session_id; /* Session ID in big endian. */ 580 }; 581 582 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 583 struct i40e_ipv6_l2tpv3oip_flow { 584 struct rte_eth_ipv6_flow ip6; 585 uint32_t session_id; /* Session ID in big endian. */ 586 }; 587 588 /* A structure used to define the input for l2 dst type flow */ 589 struct i40e_l2_flow { 590 struct rte_ether_addr dst; 591 struct rte_ether_addr src; 592 uint16_t ether_type; /**< Ether type in big endian */ 593 }; 594 595 /* 596 * A union contains the inputs for all types of flow 597 * items in flows need to be in big endian 598 */ 599 union i40e_fdir_flow { 600 struct i40e_l2_flow l2_flow; 601 struct rte_eth_udpv4_flow udp4_flow; 602 struct rte_eth_tcpv4_flow tcp4_flow; 603 struct rte_eth_sctpv4_flow sctp4_flow; 604 struct rte_eth_ipv4_flow ip4_flow; 605 struct rte_eth_udpv6_flow udp6_flow; 606 struct rte_eth_tcpv6_flow tcp6_flow; 607 struct rte_eth_sctpv6_flow sctp6_flow; 608 struct rte_eth_ipv6_flow ipv6_flow; 609 struct i40e_gtp_flow gtp_flow; 610 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 611 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 612 struct i40e_raw_flow raw_flow; 613 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 614 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 615 struct i40e_esp_ipv4_flow esp_ipv4_flow; 616 struct i40e_esp_ipv6_flow esp_ipv6_flow; 617 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 618 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 619 }; 620 621 enum i40e_fdir_ip_type { 622 I40E_FDIR_IPTYPE_IPV4, 623 I40E_FDIR_IPTYPE_IPV6, 624 }; 625 626 /** 627 * Structure to store flex pit for flow diretor. 628 */ 629 struct i40e_fdir_flex_pit { 630 uint8_t src_offset; /* offset in words from the beginning of payload */ 631 uint8_t size; /* size in words */ 632 uint8_t dst_offset; /* offset in words of flexible payload */ 633 }; 634 635 /* A structure used to contain extend input of flow */ 636 struct i40e_fdir_flow_ext { 637 uint16_t vlan_tci; 638 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 639 /* It is filled by the flexible payload to match. */ 640 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN]; 641 uint8_t raw_id; 642 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 643 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 644 uint64_t input_set; 645 bool inner_ip; /* If there is inner ip */ 646 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 647 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 648 bool customized_pctype; /* If customized pctype is used */ 649 bool pkt_template; /* If raw packet template is used */ 650 bool is_udp; /* ipv4|ipv6 udp flow */ 651 enum i40e_flxpld_layer_idx layer_idx; 652 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 653 bool is_flex_flow; 654 }; 655 656 /* A structure used to define the input for a flow director filter entry */ 657 struct i40e_fdir_input { 658 enum i40e_filter_pctype pctype; 659 union i40e_fdir_flow flow; 660 /* Flow fields to match, dependent on flow_type */ 661 struct i40e_fdir_flow_ext flow_ext; 662 /* Additional fields to match */ 663 }; 664 665 /* Behavior will be taken if FDIR match */ 666 enum i40e_fdir_behavior { 667 I40E_FDIR_ACCEPT = 0, 668 I40E_FDIR_REJECT, 669 I40E_FDIR_PASSTHRU, 670 }; 671 672 /* Flow director report status 673 * It defines what will be reported if FDIR entry is matched. 674 */ 675 enum i40e_fdir_status { 676 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 677 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 678 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 679 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 680 }; 681 682 /* A structure used to define an action when match FDIR packet filter. */ 683 struct i40e_fdir_action { 684 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 685 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 686 enum i40e_fdir_status report_status; /* Status report option */ 687 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 688 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 689 * flex bytes start from in flexible payload. 690 */ 691 uint8_t flex_off; 692 }; 693 694 /* A structure used to define the flow director filter entry by filter_ctrl API 695 * It supports RTE_ETH_FILTER_FDIR data representation. 696 */ 697 struct i40e_fdir_filter_conf { 698 uint32_t soft_id; 699 /* ID, an unique value is required when deal with FDIR entry */ 700 struct i40e_fdir_input input; /* Input set */ 701 struct i40e_fdir_action action; /* Action taken when match */ 702 }; 703 704 struct i40e_fdir_flex_mask { 705 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 706 uint8_t nb_bitmask; 707 struct { 708 uint8_t offset; 709 uint16_t mask; 710 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 711 }; 712 713 #define I40E_FILTER_PCTYPE_INVALID 0 714 #define I40E_FILTER_PCTYPE_MAX 64 715 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 716 717 struct i40e_fdir_filter { 718 TAILQ_ENTRY(i40e_fdir_filter) rules; 719 struct i40e_fdir_filter_conf fdir; 720 }; 721 722 /* fdir memory pool entry */ 723 struct i40e_fdir_entry { 724 struct rte_flow flow; 725 uint32_t idx; 726 }; 727 728 /* pre-allocated fdir memory pool */ 729 struct i40e_fdir_flow_pool { 730 /* a bitmap to manage the fdir pool */ 731 struct rte_bitmap *bitmap; 732 /* the size the pool is pf->fdir->fdir_space_size */ 733 struct i40e_fdir_entry *pool; 734 }; 735 736 #define FLOW_TO_FLOW_BITMAP(f) \ 737 container_of((f), struct i40e_fdir_entry, flow) 738 739 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 740 /* 741 * A structure used to define fields of a FDIR related info. 742 */ 743 struct i40e_fdir_info { 744 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 745 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 746 struct i40e_tx_queue *txq; 747 struct i40e_rx_queue *rxq; 748 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 749 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 750 /* 751 * txq available buffer counter, indicates how many available buffers 752 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 753 */ 754 int txq_available_buf_count; 755 756 /* input set bits for each pctype */ 757 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 758 /* 759 * the rule how bytes stream is extracted as flexible payload 760 * for each payload layer, the setting can up to three elements 761 */ 762 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 763 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 764 765 struct i40e_fdir_filter_list fdir_list; 766 struct i40e_fdir_filter **hash_map; 767 struct rte_hash *hash_table; 768 /* An array to store the inserted rules input */ 769 struct i40e_fdir_filter *fdir_filter_array; 770 771 /* 772 * Priority ordering at filter invalidation(destroying a flow) between 773 * "best effort" space and "guaranteed" space. 774 * 775 * 0 = At filter invalidation, the hardware first tries to increment the 776 * "best effort" space. The "guaranteed" space is incremented only when 777 * the global "best effort" space is at it max value or the "best effort" 778 * space of the PF is at its max value. 779 * 1 = At filter invalidation, the hardware first tries to increment its 780 * "guaranteed" space. The "best effort" space is incremented only when 781 * it is already at its max value. 782 */ 783 uint32_t fdir_invalprio; 784 /* the total size of the fdir, this number is the sum of the guaranteed + 785 * shared space 786 */ 787 uint32_t fdir_space_size; 788 /* the actual number of the fdir rules in hardware, initialized as 0 */ 789 uint32_t fdir_actual_cnt; 790 /* the free guaranteed space of the fdir */ 791 uint32_t fdir_guarantee_free_space; 792 /* the fdir total guaranteed space */ 793 uint32_t fdir_guarantee_total_space; 794 /* the pre-allocated pool of the rte_flow */ 795 struct i40e_fdir_flow_pool fdir_flow_pool; 796 797 /* Mark if flex pit and mask is set */ 798 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 799 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 800 801 uint32_t flow_count[I40E_FILTER_PCTYPE_MAX]; 802 803 uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER]; 804 }; 805 806 /* Ethertype filter number HW supports */ 807 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 808 809 /* Ethertype filter struct */ 810 struct i40e_ethertype_filter_input { 811 struct rte_ether_addr mac_addr; /* Mac address to match */ 812 uint16_t ether_type; /* Ether type to match */ 813 }; 814 815 struct i40e_ethertype_filter { 816 TAILQ_ENTRY(i40e_ethertype_filter) rules; 817 struct i40e_ethertype_filter_input input; 818 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 819 uint16_t queue; /* Queue assigned to when match */ 820 }; 821 822 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 823 824 struct i40e_ethertype_rule { 825 struct i40e_ethertype_filter_list ethertype_list; 826 struct i40e_ethertype_filter **hash_map; 827 struct rte_hash *hash_table; 828 }; 829 830 /* queue region info */ 831 struct i40e_queue_region_info { 832 /* the region id for this configuration */ 833 uint8_t region_id; 834 /* the start queue index for this region */ 835 uint8_t queue_start_index; 836 /* the total queue number of this queue region */ 837 uint8_t queue_num; 838 /* the total number of user priority for this region */ 839 uint8_t user_priority_num; 840 /* the packet's user priority for this region */ 841 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 842 /* the total number of flowtype for this region */ 843 uint8_t flowtype_num; 844 /** 845 * the pctype or hardware flowtype of packet, 846 * the specific index for each type has been defined 847 * in file i40e_type.h as enum i40e_filter_pctype. 848 */ 849 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 850 }; 851 852 struct i40e_queue_regions { 853 /* the total number of queue region for this port */ 854 uint16_t queue_region_number; 855 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 856 }; 857 858 struct i40e_rss_pattern_info { 859 uint8_t action_flag; 860 uint64_t types; 861 }; 862 863 /* Tunnel filter number HW supports */ 864 #define I40E_MAX_TUNNEL_FILTER_NUM 400 865 866 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 867 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 868 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 869 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 870 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 871 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 872 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 873 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 874 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 875 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 876 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 877 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 878 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 879 #define I40E_AQC_NEW_TR_21 21 880 #define I40E_AQC_NEW_TR_22 22 881 882 enum i40e_tunnel_iptype { 883 I40E_TUNNEL_IPTYPE_IPV4, 884 I40E_TUNNEL_IPTYPE_IPV6, 885 }; 886 887 /* Tunnel filter struct */ 888 struct i40e_tunnel_filter_input { 889 uint8_t outer_mac[6]; /* Outer mac address to match */ 890 uint8_t inner_mac[6]; /* Inner mac address to match */ 891 uint16_t inner_vlan; /* Inner vlan address to match */ 892 enum i40e_tunnel_iptype ip_type; 893 uint16_t flags; /* Filter type flag */ 894 uint32_t tenant_id; /* Tenant id to match */ 895 uint16_t general_fields[32]; /* Big buffer */ 896 }; 897 898 struct i40e_tunnel_filter { 899 TAILQ_ENTRY(i40e_tunnel_filter) rules; 900 struct i40e_tunnel_filter_input input; 901 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 902 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 903 uint16_t queue; /* Queue assigned to when match */ 904 }; 905 906 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 907 908 struct i40e_tunnel_rule { 909 struct i40e_tunnel_filter_list tunnel_list; 910 struct i40e_tunnel_filter **hash_map; 911 struct rte_hash *hash_table; 912 }; 913 914 /** 915 * Tunnel type. 916 */ 917 enum i40e_tunnel_type { 918 I40E_TUNNEL_TYPE_NONE = 0, 919 I40E_TUNNEL_TYPE_VXLAN, 920 I40E_TUNNEL_TYPE_GENEVE, 921 I40E_TUNNEL_TYPE_TEREDO, 922 I40E_TUNNEL_TYPE_NVGRE, 923 I40E_TUNNEL_TYPE_IP_IN_GRE, 924 I40E_L2_TUNNEL_TYPE_E_TAG, 925 I40E_TUNNEL_TYPE_MPLSoUDP, 926 I40E_TUNNEL_TYPE_MPLSoGRE, 927 I40E_TUNNEL_TYPE_QINQ, 928 I40E_TUNNEL_TYPE_GTPC, 929 I40E_TUNNEL_TYPE_GTPU, 930 I40E_TUNNEL_TYPE_ESPoUDP, 931 I40E_TUNNEL_TYPE_ESPoIP, 932 I40E_CLOUD_TYPE_UDP, 933 I40E_CLOUD_TYPE_TCP, 934 I40E_CLOUD_TYPE_SCTP, 935 I40E_TUNNEL_TYPE_MAX, 936 }; 937 938 /** 939 * L4 port type. 940 */ 941 enum i40e_l4_port_type { 942 I40E_L4_PORT_TYPE_SRC = 0, 943 I40E_L4_PORT_TYPE_DST, 944 }; 945 946 /** 947 * Tunneling Packet filter configuration. 948 */ 949 struct i40e_tunnel_filter_conf { 950 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 951 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 952 uint16_t inner_vlan; /**< Inner VLAN to match. */ 953 uint32_t outer_vlan; /**< Outer VLAN to match */ 954 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 955 /** 956 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 957 * is set in filter_type, or inner destination IP address to match 958 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 959 */ 960 union { 961 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 962 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 963 } ip_addr; 964 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 965 uint16_t filter_type; 966 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 967 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 968 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 969 uint16_t queue_id; /**< Queue assigned to if match. */ 970 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 971 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 972 }; 973 974 TAILQ_HEAD(i40e_flow_list, rte_flow); 975 976 /* Struct to store Traffic Manager shaper profile. */ 977 struct i40e_tm_shaper_profile { 978 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 979 uint32_t shaper_profile_id; 980 uint32_t reference_count; 981 struct rte_tm_shaper_params profile; 982 }; 983 984 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 985 986 /* node type of Traffic Manager */ 987 enum i40e_tm_node_type { 988 I40E_TM_NODE_TYPE_PORT, 989 I40E_TM_NODE_TYPE_TC, 990 I40E_TM_NODE_TYPE_QUEUE, 991 I40E_TM_NODE_TYPE_MAX, 992 }; 993 994 /* Struct to store Traffic Manager node configuration. */ 995 struct i40e_tm_node { 996 TAILQ_ENTRY(i40e_tm_node) node; 997 uint32_t id; 998 uint32_t priority; 999 uint32_t weight; 1000 uint32_t reference_count; 1001 struct i40e_tm_node *parent; 1002 struct i40e_tm_shaper_profile *shaper_profile; 1003 struct rte_tm_node_params params; 1004 }; 1005 1006 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 1007 1008 /* Struct to store all the Traffic Manager configuration. */ 1009 struct i40e_tm_conf { 1010 struct i40e_shaper_profile_list shaper_profile_list; 1011 struct i40e_tm_node *root; /* root node - port */ 1012 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 1013 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 1014 /** 1015 * The number of added TC nodes. 1016 * It should be no more than the TC number of this port. 1017 */ 1018 uint32_t nb_tc_node; 1019 /** 1020 * The number of added queue nodes. 1021 * It should be no more than the queue number of this port. 1022 */ 1023 uint32_t nb_queue_node; 1024 /** 1025 * This flag is used to check if APP can change the TM node 1026 * configuration. 1027 * When it's true, means the configuration is applied to HW, 1028 * APP should not change the configuration. 1029 * As we don't support on-the-fly configuration, when starting 1030 * the port, APP should call the hierarchy_commit API to set this 1031 * flag to true. When stopping the port, this flag should be set 1032 * to false. 1033 */ 1034 bool committed; 1035 }; 1036 1037 enum i40e_new_pctype { 1038 I40E_CUSTOMIZED_GTPC = 0, 1039 I40E_CUSTOMIZED_GTPU_IPV4, 1040 I40E_CUSTOMIZED_GTPU_IPV6, 1041 I40E_CUSTOMIZED_GTPU, 1042 I40E_CUSTOMIZED_IPV4_L2TPV3, 1043 I40E_CUSTOMIZED_IPV6_L2TPV3, 1044 I40E_CUSTOMIZED_ESP_IPV4, 1045 I40E_CUSTOMIZED_ESP_IPV6, 1046 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1047 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1048 I40E_CUSTOMIZED_AH_IPV4, 1049 I40E_CUSTOMIZED_AH_IPV6, 1050 I40E_CUSTOMIZED_MAX, 1051 }; 1052 1053 #define I40E_FILTER_PCTYPE_INVALID 0 1054 struct i40e_customized_pctype { 1055 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1056 uint8_t pctype; /* New pctype value */ 1057 bool valid; /* Check if it's valid */ 1058 }; 1059 1060 struct i40e_rte_flow_rss_conf { 1061 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1062 1063 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1064 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1065 sizeof(uint32_t)]; /**< Hash key. */ 1066 uint16_t queue[ETH_RSS_RETA_SIZE_512]; /**< Queues indices to use. */ 1067 1068 bool symmetric_enable; /**< true, if enable symmetric */ 1069 uint64_t config_pctypes; /**< All PCTYPES with the flow */ 1070 uint64_t inset; /**< input sets */ 1071 1072 uint8_t region_priority; /**< queue region priority */ 1073 uint8_t region_queue_num; /**< region queue number */ 1074 uint16_t region_queue_start; /**< region queue start */ 1075 1076 uint32_t misc_reset_flags; 1077 #define I40E_HASH_FLOW_RESET_FLAG_FUNC 0x01UL 1078 #define I40E_HASH_FLOW_RESET_FLAG_KEY 0x02UL 1079 #define I40E_HASH_FLOW_RESET_FLAG_QUEUE 0x04UL 1080 #define I40E_HASH_FLOW_RESET_FLAG_REGION 0x08UL 1081 1082 /**< All PCTYPES that reset with the flow */ 1083 uint64_t reset_config_pctypes; 1084 /**< Symmetric function should reset on PCTYPES */ 1085 uint64_t reset_symmetric_pctypes; 1086 }; 1087 1088 /* RSS filter list structure */ 1089 struct i40e_rss_filter { 1090 TAILQ_ENTRY(i40e_rss_filter) next; 1091 struct i40e_rte_flow_rss_conf rss_filter_info; 1092 }; 1093 1094 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1095 1096 struct i40e_vf_msg_cfg { 1097 /* maximal VF message during a statistic period */ 1098 uint32_t max_msg; 1099 1100 /* statistic period, in second */ 1101 uint32_t period; 1102 /* 1103 * If message statistics from a VF exceed the maximal limitation, 1104 * the PF will ignore any new message from that VF for 1105 * 'ignor_second' time. 1106 */ 1107 uint32_t ignore_second; 1108 }; 1109 1110 /* 1111 * Structure to store private data specific for PF instance. 1112 */ 1113 struct i40e_pf { 1114 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1115 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1116 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1117 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1118 uint16_t max_num_vsi; 1119 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1120 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1121 1122 struct i40e_hw_port_stats stats_offset; 1123 struct i40e_hw_port_stats stats; 1124 u64 rx_err1; /* rxerr1 */ 1125 u64 rx_err1_offset; 1126 1127 /* internal packet statistics, it should be excluded from the total */ 1128 struct i40e_eth_stats internal_stats_offset; 1129 struct i40e_eth_stats internal_stats; 1130 bool offset_loaded; 1131 1132 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1133 struct rte_ether_addr dev_addr; /* PF device mac address */ 1134 uint64_t flags; /* PF feature flags */ 1135 /* All kinds of queue pair setting for different VSIs */ 1136 struct i40e_pf_vf *vfs; 1137 uint16_t vf_num; 1138 /* Each of below queue pairs should be power of 2 since it's the 1139 precondition after TC configuration applied */ 1140 uint16_t lan_nb_qp_max; 1141 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1142 uint16_t lan_qp_offset; 1143 uint16_t vmdq_nb_qp_max; 1144 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1145 uint16_t vmdq_qp_offset; 1146 uint16_t vf_nb_qp_max; 1147 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1148 uint16_t vf_qp_offset; 1149 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1150 uint16_t fdir_qp_offset; 1151 1152 uint16_t hash_lut_size; /* The size of hash lookup table */ 1153 bool hash_filter_enabled; 1154 uint64_t hash_enabled_queues; 1155 /* input set bits for each pctype */ 1156 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1157 /* store VXLAN UDP ports */ 1158 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1159 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1160 1161 /* VMDQ related info */ 1162 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1163 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1164 struct i40e_vmdq_info *vmdq; 1165 1166 struct i40e_fdir_info fdir; /* flow director info */ 1167 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1168 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1169 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1170 struct i40e_queue_regions queue_region; /* queue region info */ 1171 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1172 bool floating_veb; /* The flag to use the floating VEB */ 1173 /* The floating enable flag for the specific VF */ 1174 bool floating_veb_list[I40E_MAX_VF]; 1175 struct i40e_flow_list flow_list; 1176 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1177 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1178 bool qinq_replace_flag; /* QINQ filter replace is done */ 1179 /* l4 port flag */ 1180 bool sport_replace_flag; /* Source port replace is done */ 1181 bool dport_replace_flag; /* Destination port replace is done */ 1182 struct i40e_tm_conf tm_conf; 1183 bool support_multi_driver; /* 1 - support multiple driver */ 1184 1185 /* Dynamic Device Personalization */ 1186 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1187 bool esp_support; /* 1 - support ESP SPI */ 1188 /* customer customized pctype */ 1189 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1190 /* Switch Domain Id */ 1191 uint16_t switch_domain_id; 1192 1193 struct i40e_vf_msg_cfg vf_msg_cfg; 1194 uint64_t prev_rx_bytes; 1195 uint64_t prev_tx_bytes; 1196 uint64_t internal_prev_rx_bytes; 1197 uint64_t internal_prev_tx_bytes; 1198 }; 1199 1200 enum pending_msg { 1201 PFMSG_LINK_CHANGE = 0x1, 1202 PFMSG_RESET_IMPENDING = 0x2, 1203 PFMSG_DRIVER_CLOSE = 0x4, 1204 }; 1205 1206 struct i40e_vsi_vlan_pvid_info { 1207 uint16_t on; /* Enable or disable pvid */ 1208 union { 1209 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1210 struct { 1211 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1212 * while 'untagged' will reject untagged packets. 1213 */ 1214 uint8_t tagged; 1215 uint8_t untagged; 1216 } reject; 1217 } config; 1218 }; 1219 1220 #define I40E_MAX_PKT_TYPE 256 1221 #define I40E_FLOW_TYPE_MAX 64 1222 1223 /* 1224 * Structure to store private data for each PF/VF instance. 1225 */ 1226 struct i40e_adapter { 1227 /* Common for both PF and VF */ 1228 struct i40e_hw hw; 1229 1230 /* Specific for PF */ 1231 struct i40e_pf pf; 1232 1233 /* For vector PMD */ 1234 bool rx_bulk_alloc_allowed; 1235 bool rx_vec_allowed; 1236 bool tx_simple_allowed; 1237 bool tx_vec_allowed; 1238 1239 /* For PTP */ 1240 struct rte_timecounter systime_tc; 1241 struct rte_timecounter rx_tstamp_tc; 1242 struct rte_timecounter tx_tstamp_tc; 1243 1244 /* ptype mapping table */ 1245 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1246 /* flow type to pctype mapping table */ 1247 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1248 uint64_t flow_types_mask; 1249 uint64_t pctypes_mask; 1250 1251 /* For RSS reta table update */ 1252 uint8_t rss_reta_updated; 1253 #ifdef RTE_ARCH_X86 1254 bool rx_use_avx2; 1255 bool rx_use_avx512; 1256 bool tx_use_avx2; 1257 bool tx_use_avx512; 1258 #endif 1259 }; 1260 1261 /** 1262 * Strucute to store private data for each VF representor instance 1263 */ 1264 struct i40e_vf_representor { 1265 uint16_t switch_domain_id; 1266 /**< Virtual Function ID */ 1267 uint16_t vf_id; 1268 /**< Virtual Function ID */ 1269 struct i40e_adapter *adapter; 1270 /**< Private data store of assocaiated physical function */ 1271 struct i40e_eth_stats stats_offset; 1272 /**< Zero-point of VF statistics*/ 1273 }; 1274 1275 extern const struct rte_flow_ops i40e_flow_ops; 1276 1277 union i40e_filter_t { 1278 struct rte_eth_ethertype_filter ethertype_filter; 1279 struct i40e_fdir_filter_conf fdir_filter; 1280 struct rte_eth_tunnel_filter_conf tunnel_filter; 1281 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1282 struct i40e_rte_flow_rss_conf rss_conf; 1283 }; 1284 1285 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1286 const struct rte_flow_attr *attr, 1287 const struct rte_flow_item pattern[], 1288 const struct rte_flow_action actions[], 1289 struct rte_flow_error *error, 1290 union i40e_filter_t *filter); 1291 struct i40e_valid_pattern { 1292 enum rte_flow_item_type *items; 1293 parse_filter_t parse_filter; 1294 }; 1295 1296 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1297 int i40e_vsi_release(struct i40e_vsi *vsi); 1298 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1299 enum i40e_vsi_type type, 1300 struct i40e_vsi *uplink_vsi, 1301 uint16_t user_param); 1302 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1303 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1304 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1305 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1306 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1307 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1308 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1309 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1310 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1311 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1312 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1313 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1314 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1315 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1316 struct i40e_vsi_vlan_pvid_info *info); 1317 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1318 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1319 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1320 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1321 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1322 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1323 int i40e_fdir_setup(struct i40e_pf *pf); 1324 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1325 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1326 uint32_t len, 1327 int socket_id); 1328 int i40e_fdir_configure(struct rte_eth_dev *dev); 1329 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1330 void i40e_fdir_teardown(struct i40e_pf *pf); 1331 enum i40e_filter_pctype 1332 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1333 uint16_t flow_type); 1334 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1335 enum i40e_filter_pctype pctype); 1336 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1337 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1338 struct rte_eth_fdir_info *fdir); 1339 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1340 struct rte_eth_fdir_stats *stat); 1341 int i40e_select_filter_input_set(struct i40e_hw *hw, 1342 struct rte_eth_input_set_conf *conf, 1343 enum rte_filter_type filter); 1344 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1345 int i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set, 1346 uint32_t pctype, bool add); 1347 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1348 uint32_t retval, uint8_t *msg, 1349 uint16_t msglen); 1350 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1351 struct rte_eth_rxq_info *qinfo); 1352 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1353 struct rte_eth_txq_info *qinfo); 1354 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1355 struct rte_eth_burst_mode *mode); 1356 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1357 struct rte_eth_burst_mode *mode); 1358 struct i40e_ethertype_filter * 1359 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1360 const struct i40e_ethertype_filter_input *input); 1361 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1362 struct i40e_ethertype_filter_input *input); 1363 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1364 struct i40e_fdir_input *input); 1365 struct i40e_tunnel_filter * 1366 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1367 const struct i40e_tunnel_filter_input *input); 1368 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1369 struct i40e_tunnel_filter_input *input); 1370 uint64_t i40e_get_default_input_set(uint16_t pctype); 1371 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1372 struct rte_eth_ethertype_filter *filter, 1373 bool add); 1374 struct rte_flow * 1375 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1376 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1377 struct rte_flow *flow); 1378 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1379 const struct i40e_fdir_filter_conf *filter, 1380 bool add); 1381 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1382 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1383 uint8_t add); 1384 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1385 struct i40e_tunnel_filter_conf *tunnel_filter, 1386 uint8_t add); 1387 int i40e_fdir_flush(struct rte_eth_dev *dev); 1388 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1389 struct i40e_macvlan_filter *mv_f, 1390 int num, struct rte_ether_addr *addr); 1391 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1392 struct i40e_macvlan_filter *filter, 1393 int total); 1394 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1395 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1396 struct i40e_macvlan_filter *filter, 1397 int total); 1398 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1399 bool is_i40e_supported(struct rte_eth_dev *dev); 1400 void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, 1401 uint8_t enable); 1402 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1403 enum rte_filter_type filter, uint64_t inset); 1404 int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset, 1405 uint32_t *mask, uint8_t nb_elem); 1406 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1407 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1408 void i40e_check_write_global_reg(struct i40e_hw *hw, 1409 uint32_t addr, uint32_t val); 1410 1411 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1412 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1413 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1414 struct i40e_customized_pctype* 1415 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1416 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1417 uint32_t pkg_size, 1418 enum rte_pmd_i40e_package_op op); 1419 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1420 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1421 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1422 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1423 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1424 void i40e_pf_disable_rss(struct i40e_pf *pf); 1425 int i40e_pf_calc_configured_queues_num(struct i40e_pf *pf); 1426 int i40e_pf_reset_rss_reta(struct i40e_pf *pf); 1427 int i40e_pf_reset_rss_key(struct i40e_pf *pf); 1428 int i40e_pf_config_rss(struct i40e_pf *pf); 1429 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1430 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1431 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1432 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1433 1434 #define I40E_DEV_TO_PCI(eth_dev) \ 1435 RTE_DEV_TO_PCI((eth_dev)->device) 1436 1437 /* I40E_DEV_PRIVATE_TO */ 1438 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1439 (&((struct i40e_adapter *)adapter)->pf) 1440 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1441 (&((struct i40e_adapter *)adapter)->hw) 1442 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1443 ((struct i40e_adapter *)adapter) 1444 1445 static inline struct i40e_vsi * 1446 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1447 { 1448 if (!adapter) 1449 return NULL; 1450 1451 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1452 1453 return pf->main_vsi; 1454 } 1455 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1456 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1457 1458 /* I40E_VSI_TO */ 1459 #define I40E_VSI_TO_HW(vsi) \ 1460 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1461 #define I40E_VSI_TO_PF(vsi) \ 1462 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1463 #define I40E_VSI_TO_VF(vsi) \ 1464 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1465 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1466 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1467 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1468 (&rte_eth_devices[((struct i40e_vsi *)vsi)->adapter->pf.dev_data->port_id]) 1469 1470 /* I40E_PF_TO */ 1471 #define I40E_PF_TO_HW(pf) \ 1472 (&(((struct i40e_pf *)pf)->adapter->hw)) 1473 #define I40E_PF_TO_ADAPTER(pf) \ 1474 ((struct i40e_adapter *)pf->adapter) 1475 1476 static inline void 1477 i40e_init_adminq_parameter(struct i40e_hw *hw) 1478 { 1479 hw->aq.num_arq_entries = I40E_AQ_LEN; 1480 hw->aq.num_asq_entries = I40E_AQ_LEN; 1481 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1482 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1483 } 1484 1485 static inline int 1486 i40e_align_floor(int n) 1487 { 1488 if (n == 0) 1489 return 0; 1490 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1491 } 1492 1493 static inline uint16_t 1494 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1495 { 1496 uint16_t interval = 0; 1497 1498 if (is_multi_drv) { 1499 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1500 } else { 1501 if (is_pf) 1502 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1503 else 1504 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1505 } 1506 1507 /* Convert to hardware count, as writing each 1 represents 2 us */ 1508 return interval / 2; 1509 } 1510 1511 #define I40E_VALID_FLOW(flow_type) \ 1512 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1513 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1514 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1515 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1516 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1517 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1518 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1519 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1520 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1521 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1522 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1523 1524 #define I40E_VALID_PCTYPE_X722(pctype) \ 1525 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1526 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1527 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1528 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1529 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1530 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1531 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1532 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1533 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1534 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1535 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1536 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1537 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1538 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1539 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1540 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1541 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1542 1543 #define I40E_VALID_PCTYPE(pctype) \ 1544 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1545 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1546 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1547 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1548 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1549 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1550 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1551 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1552 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1553 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1554 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1555 1556 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1557 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1558 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1559 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1560 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1561 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1562 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1563 1564 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1565 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1566 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1567 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1568 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1569 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1570 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1571 1572 #endif /* _I40E_ETHDEV_H_ */ 1573