1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_time.h> 11 #include <rte_kvargs.h> 12 #include <rte_hash.h> 13 #include <rte_flow.h> 14 #include <rte_flow_driver.h> 15 #include <rte_tm_driver.h> 16 #include "rte_pmd_i40e.h" 17 18 #include "base/i40e_register.h" 19 20 #define I40E_VLAN_TAG_SIZE 4 21 22 #define I40E_AQ_LEN 32 23 #define I40E_AQ_BUF_SZ 4096 24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 25 #define I40E_MAX_Q_PER_TC 64 26 #define I40E_NUM_DESC_DEFAULT 512 27 #define I40E_NUM_DESC_ALIGN 32 28 #define I40E_BUF_SIZE_MIN 1024 29 #define I40E_FRAME_SIZE_MAX 9728 30 #define I40E_TSO_FRAME_SIZE_MAX 262144 31 #define I40E_QUEUE_BASE_ADDR_UNIT 128 32 /* number of VSIs and queue default setting */ 33 #define I40E_MAX_QP_NUM_PER_VF 16 34 #define I40E_DEFAULT_QP_NUM_FDIR 1 35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 37 /* Maximun number of MAC addresses */ 38 #define I40E_NUM_MACADDR_MAX 64 39 /* Maximum number of VFs */ 40 #define I40E_MAX_VF 128 41 /*flag of no loopback*/ 42 #define I40E_AQ_LB_MODE_NONE 0x0 43 /* 44 * vlan_id is a 12 bit number. 45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 47 * The higher 7 bit val specifies VFTA array index. 48 */ 49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 51 52 /* Default TC traffic in case DCB is not enabled */ 53 #define I40E_DEFAULT_TCMAP 0x1 54 #define I40E_FDIR_QUEUE_ID 0 55 56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 57 #define I40E_VMDQ_POOL_BASE 1 58 59 #define I40E_DEFAULT_RX_FREE_THRESH 32 60 #define I40E_DEFAULT_RX_PTHRESH 8 61 #define I40E_DEFAULT_RX_HTHRESH 8 62 #define I40E_DEFAULT_RX_WTHRESH 0 63 64 #define I40E_DEFAULT_TX_FREE_THRESH 32 65 #define I40E_DEFAULT_TX_PTHRESH 32 66 #define I40E_DEFAULT_TX_HTHRESH 0 67 #define I40E_DEFAULT_TX_WTHRESH 0 68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 69 70 /* Bit shift and mask */ 71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 73 #define I40E_8_BIT_WIDTH CHAR_BIT 74 #define I40E_8_BIT_MASK UINT8_MAX 75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 76 #define I40E_16_BIT_MASK UINT16_MAX 77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 78 #define I40E_32_BIT_MASK UINT32_MAX 79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 81 82 /* Linux PF host with virtchnl version 1.1 */ 83 #define PF_IS_V11(vf) \ 84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 85 ((vf)->version_minor == 1)) 86 87 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 88 do { \ 89 uint32_t ori_val; \ 90 struct rte_eth_dev *dev; \ 91 ori_val = I40E_READ_REG((hw), (reg)); \ 92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \ 93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 94 (reg)), (value)); \ 95 if (ori_val != value) \ 96 PMD_DRV_LOG(WARNING, \ 97 "i40e device %s changed global " \ 98 "register [0x%08x]. original: 0x%08x, " \ 99 "new: 0x%08x ", \ 100 (dev->device->name), (reg), \ 101 (ori_val), (value)); \ 102 } while (0) 103 104 /* index flex payload per layer */ 105 enum i40e_flxpld_layer_idx { 106 I40E_FLXPLD_L2_IDX = 0, 107 I40E_FLXPLD_L3_IDX = 1, 108 I40E_FLXPLD_L4_IDX = 2, 109 I40E_MAX_FLXPLD_LAYER = 3, 110 }; 111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 116 117 /* i40e flags */ 118 #define I40E_FLAG_RSS (1ULL << 0) 119 #define I40E_FLAG_DCB (1ULL << 1) 120 #define I40E_FLAG_VMDQ (1ULL << 2) 121 #define I40E_FLAG_SRIOV (1ULL << 3) 122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 124 #define I40E_FLAG_FDIR (1ULL << 6) 125 #define I40E_FLAG_VXLAN (1ULL << 7) 126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 127 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 128 I40E_FLAG_DCB | \ 129 I40E_FLAG_VMDQ | \ 130 I40E_FLAG_SRIOV | \ 131 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 132 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 133 I40E_FLAG_FDIR | \ 134 I40E_FLAG_VXLAN | \ 135 I40E_FLAG_RSS_AQ_CAPABLE) 136 137 #define I40E_RSS_OFFLOAD_ALL ( \ 138 ETH_RSS_FRAG_IPV4 | \ 139 ETH_RSS_NONFRAG_IPV4_TCP | \ 140 ETH_RSS_NONFRAG_IPV4_UDP | \ 141 ETH_RSS_NONFRAG_IPV4_SCTP | \ 142 ETH_RSS_NONFRAG_IPV4_OTHER | \ 143 ETH_RSS_FRAG_IPV6 | \ 144 ETH_RSS_NONFRAG_IPV6_TCP | \ 145 ETH_RSS_NONFRAG_IPV6_UDP | \ 146 ETH_RSS_NONFRAG_IPV6_SCTP | \ 147 ETH_RSS_NONFRAG_IPV6_OTHER | \ 148 ETH_RSS_L2_PAYLOAD) 149 150 /* All bits of RSS hash enable for X722*/ 151 #define I40E_RSS_HENA_ALL_X722 ( \ 152 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 153 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 158 I40E_RSS_HENA_ALL) 159 160 /* All bits of RSS hash enable */ 161 #define I40E_RSS_HENA_ALL ( \ 162 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 166 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 171 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 172 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 173 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 175 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 176 177 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 178 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 179 180 /* Default queue interrupt throttling time in microseconds */ 181 #define I40E_ITR_INDEX_DEFAULT 0 182 #define I40E_ITR_INDEX_NONE 3 183 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 184 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 185 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 186 /* Special FW support this floating VEB feature */ 187 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 188 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 189 190 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 191 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 192 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 193 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 194 195 #define I40E_RSS_TYPE_NONE 0ULL 196 #define I40E_RSS_TYPE_INVALID 1ULL 197 198 #define I40E_INSET_NONE 0x00000000000000000ULL 199 200 /* bit0 ~ bit 7 */ 201 #define I40E_INSET_DMAC 0x0000000000000001ULL 202 #define I40E_INSET_SMAC 0x0000000000000002ULL 203 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 204 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 205 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 206 207 /* bit 8 ~ bit 15 */ 208 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 209 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 210 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 211 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 212 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 213 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 214 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 215 216 /* bit 16 ~ bit 31 */ 217 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 218 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 219 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 220 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 221 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 222 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 223 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 224 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 225 226 /* bit 32 ~ bit 47, tunnel fields */ 227 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 228 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 229 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 230 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 231 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 232 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 233 234 /* bit 48 ~ bit 55 */ 235 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 236 237 /* bit 56 ~ bit 63, Flex Payload */ 238 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 239 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 240 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 241 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 242 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 243 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 244 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 245 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 246 #define I40E_INSET_FLEX_PAYLOAD \ 247 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 248 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 249 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 250 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 251 252 /* The max bandwidth of i40e is 40Gbps. */ 253 #define I40E_QOS_BW_MAX 40000 254 /* The bandwidth should be the multiple of 50Mbps. */ 255 #define I40E_QOS_BW_GRANULARITY 50 256 /* The min bandwidth weight is 1. */ 257 #define I40E_QOS_BW_WEIGHT_MIN 1 258 /* The max bandwidth weight is 127. */ 259 #define I40E_QOS_BW_WEIGHT_MAX 127 260 /* The max queue region index is 7. */ 261 #define I40E_REGION_MAX_INDEX 7 262 263 #define I40E_MAX_PERCENT 100 264 #define I40E_DEFAULT_DCB_APP_NUM 1 265 #define I40E_DEFAULT_DCB_APP_PRIO 3 266 267 #define I40E_FDIR_PRG_PKT_CNT 128 268 269 /* 270 * Struct to store flow created. 271 */ 272 struct rte_flow { 273 TAILQ_ENTRY(rte_flow) node; 274 enum rte_filter_type filter_type; 275 void *rule; 276 }; 277 278 /** 279 * The overhead from MTU to max frame size. 280 * Considering QinQ packet, the VLAN tag needs to be counted twice. 281 */ 282 #define I40E_ETH_OVERHEAD \ 283 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 284 285 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) 286 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) 287 288 struct i40e_adapter; 289 struct rte_pci_driver; 290 291 /** 292 * MAC filter structure 293 */ 294 struct i40e_mac_filter_info { 295 enum rte_mac_filter_type filter_type; 296 struct rte_ether_addr mac_addr; 297 }; 298 299 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 300 301 /* MAC filter list structure */ 302 struct i40e_mac_filter { 303 TAILQ_ENTRY(i40e_mac_filter) next; 304 struct i40e_mac_filter_info mac_info; 305 }; 306 307 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 308 309 struct i40e_vsi; 310 311 /* VSI list structure */ 312 struct i40e_vsi_list { 313 TAILQ_ENTRY(i40e_vsi_list) list; 314 struct i40e_vsi *vsi; 315 }; 316 317 struct i40e_rx_queue; 318 struct i40e_tx_queue; 319 320 /* Bandwidth limit information */ 321 struct i40e_bw_info { 322 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 323 uint8_t bw_max; /* Max BW limit if enabled */ 324 325 /* Relative credits within same TC with respect to other VSIs or Comps */ 326 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 327 /* Bandwidth limit per TC */ 328 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 329 /* Max bandwidth limit per TC */ 330 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 331 }; 332 333 /* Structure that defines a VEB */ 334 struct i40e_veb { 335 struct i40e_vsi_list_head head; 336 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 337 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 338 uint16_t seid; /* The seid of VEB itself */ 339 uint16_t uplink_seid; /* The uplink seid of this VEB */ 340 uint16_t stats_idx; 341 struct i40e_eth_stats stats; 342 uint8_t enabled_tc; /* The traffic class enabled */ 343 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 344 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 345 }; 346 347 /* i40e MACVLAN filter structure */ 348 struct i40e_macvlan_filter { 349 struct rte_ether_addr macaddr; 350 enum rte_mac_filter_type filter_type; 351 uint16_t vlan_id; 352 }; 353 354 /* 355 * Structure that defines a VSI, associated with a adapter. 356 */ 357 struct i40e_vsi { 358 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 359 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 360 361 struct i40e_eth_stats eth_stats_offset; 362 struct i40e_eth_stats eth_stats; 363 /* 364 * When drivers loaded, only a default main VSI exists. In case new VSI 365 * needs to add, HW needs to know the layout that VSIs are organized. 366 * Besides that, VSI isan element and can't switch packets, which needs 367 * to add new component VEB to perform switching. So, a new VSI needs 368 * to specify the uplink VSI (Parent VSI) before created. The 369 * uplink VSI will check whether it had a VEB to switch packets. If no, 370 * it will try to create one. Then, uplink VSI will move the new VSI 371 * into its' sib_vsi_list to manage all the downlink VSI. 372 * sib_vsi_list: the VSI list that shared the same uplink VSI. 373 * parent_vsi : the uplink VSI. It's NULL for main VSI. 374 * veb : the VEB associates with the VSI. 375 */ 376 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 377 struct i40e_vsi *parent_vsi; 378 struct i40e_veb *veb; /* Associated veb, could be null */ 379 struct i40e_veb *floating_veb; /* Associated floating veb */ 380 bool offset_loaded; 381 enum i40e_vsi_type type; /* VSI types */ 382 uint16_t vlan_num; /* Total VLAN number */ 383 uint16_t mac_num; /* Total mac number */ 384 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 385 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 386 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 387 uint32_t user_param; 388 uint16_t seid; /* The seid of VSI itself */ 389 uint16_t uplink_seid; /* The uplink seid of this VSI */ 390 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 391 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 392 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 393 uint16_t base_queue; /* The first queue index of this VSI */ 394 /* 395 * The offset to visit VSI related register, assigned by HW when 396 * creating VSI 397 */ 398 uint16_t vsi_id; 399 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 400 uint16_t nb_msix; /* The max number of msix vector */ 401 uint8_t enabled_tc; /* The traffic class enabled */ 402 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 403 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 404 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 405 uint64_t prev_rx_bytes; 406 uint64_t prev_tx_bytes; 407 }; 408 409 struct pool_entry { 410 LIST_ENTRY(pool_entry) next; 411 uint16_t base; 412 uint16_t len; 413 }; 414 415 LIST_HEAD(res_list, pool_entry); 416 417 struct i40e_res_pool_info { 418 uint32_t base; /* Resource start index */ 419 uint32_t num_alloc; /* Allocated resource number */ 420 uint32_t num_free; /* Total available resource number */ 421 struct res_list alloc_list; /* Allocated resource list */ 422 struct res_list free_list; /* Available resource list */ 423 }; 424 425 enum I40E_VF_STATE { 426 I40E_VF_INACTIVE = 0, 427 I40E_VF_INRESET, 428 I40E_VF_ININIT, 429 I40E_VF_ACTIVE, 430 }; 431 432 /* 433 * Structure to store private data for PF host. 434 */ 435 struct i40e_pf_vf { 436 struct i40e_pf *pf; 437 struct i40e_vsi *vsi; 438 enum I40E_VF_STATE state; /* The number of queue pairs available */ 439 uint16_t vf_idx; /* VF index in pf->vfs */ 440 uint16_t lan_nb_qps; /* Actual queues allocated */ 441 uint16_t reset_cnt; /* Total vf reset times */ 442 struct rte_ether_addr mac_addr; /* Default MAC address */ 443 /* version of the virtchnl from VF */ 444 struct virtchnl_version_info version; 445 uint32_t request_caps; /* offload caps requested from VF */ 446 uint64_t num_mdd_events; /* num of mdd events detected */ 447 448 /* 449 * Variables for store the arrival timestamp of VF messages. 450 * If the timestamp of latest message stored at 451 * `msg_timestamps[index % max]` then the timestamp of 452 * earliest message stored at `msg_time[(index + 1) % max]`. 453 * When a new message come, the timestamp of this message 454 * will be stored at `msg_timestamps[(index + 1) % max]` and the 455 * earliest message timestamp is at 456 * `msg_timestamps[(index + 2) % max]` now... 457 */ 458 uint32_t msg_index; 459 uint64_t *msg_timestamps; 460 461 /* cycle of stop ignoring VF message */ 462 uint64_t ignore_end_cycle; 463 }; 464 465 /* 466 * Structure to store private data for flow control. 467 */ 468 struct i40e_fc_conf { 469 uint16_t pause_time; /* Flow control pause timer */ 470 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 471 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 472 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 473 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 474 }; 475 476 /* 477 * Structure to store private data for VMDQ instance 478 */ 479 struct i40e_vmdq_info { 480 struct i40e_pf *pf; 481 struct i40e_vsi *vsi; 482 }; 483 484 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 485 #define I40E_MAX_FLX_SOURCE_OFF 480 486 #define NONUSE_FLX_PIT_DEST_OFF 63 487 #define NONUSE_FLX_PIT_FSIZE 1 488 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 489 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 490 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 491 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 492 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 493 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 494 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 495 NONUSE_FLX_PIT_DEST_OFF : \ 496 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 497 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 498 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 499 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 500 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 501 #define I40E_FDIR_IPv6_TC_OFFSET 20 502 503 /* A structure used to define the input for GTP flow */ 504 struct i40e_gtp_flow { 505 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 506 uint8_t msg_type; /* Message type. */ 507 uint32_t teid; /* TEID in big endian. */ 508 }; 509 510 /* A structure used to define the input for GTP IPV4 flow */ 511 struct i40e_gtp_ipv4_flow { 512 struct i40e_gtp_flow gtp; 513 struct rte_eth_ipv4_flow ip4; 514 }; 515 516 /* A structure used to define the input for GTP IPV6 flow */ 517 struct i40e_gtp_ipv6_flow { 518 struct i40e_gtp_flow gtp; 519 struct rte_eth_ipv6_flow ip6; 520 }; 521 522 /* A structure used to define the input for ESP IPV4 flow */ 523 struct i40e_esp_ipv4_flow { 524 struct rte_eth_ipv4_flow ipv4; 525 uint32_t spi; /* SPI in big endian. */ 526 }; 527 528 /* A structure used to define the input for ESP IPV6 flow */ 529 struct i40e_esp_ipv6_flow { 530 struct rte_eth_ipv6_flow ipv6; 531 uint32_t spi; /* SPI in big endian. */ 532 }; 533 /* A structure used to define the input for ESP IPV4 UDP flow */ 534 struct i40e_esp_ipv4_udp_flow { 535 struct rte_eth_udpv4_flow udp; 536 uint32_t spi; /* SPI in big endian. */ 537 }; 538 539 /* A structure used to define the input for ESP IPV6 UDP flow */ 540 struct i40e_esp_ipv6_udp_flow { 541 struct rte_eth_udpv6_flow udp; 542 uint32_t spi; /* SPI in big endian. */ 543 }; 544 545 /* A structure used to define the input for raw type flow */ 546 struct i40e_raw_flow { 547 uint16_t pctype; 548 void *packet; 549 uint32_t length; 550 }; 551 552 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 553 struct i40e_ipv4_l2tpv3oip_flow { 554 struct rte_eth_ipv4_flow ip4; 555 uint32_t session_id; /* Session ID in big endian. */ 556 }; 557 558 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 559 struct i40e_ipv6_l2tpv3oip_flow { 560 struct rte_eth_ipv6_flow ip6; 561 uint32_t session_id; /* Session ID in big endian. */ 562 }; 563 564 /* A structure used to define the input for l2 dst type flow */ 565 struct i40e_l2_flow { 566 struct rte_ether_addr dst; 567 struct rte_ether_addr src; 568 uint16_t ether_type; /**< Ether type in big endian */ 569 }; 570 571 /* 572 * A union contains the inputs for all types of flow 573 * items in flows need to be in big endian 574 */ 575 union i40e_fdir_flow { 576 struct i40e_l2_flow l2_flow; 577 struct rte_eth_udpv4_flow udp4_flow; 578 struct rte_eth_tcpv4_flow tcp4_flow; 579 struct rte_eth_sctpv4_flow sctp4_flow; 580 struct rte_eth_ipv4_flow ip4_flow; 581 struct rte_eth_udpv6_flow udp6_flow; 582 struct rte_eth_tcpv6_flow tcp6_flow; 583 struct rte_eth_sctpv6_flow sctp6_flow; 584 struct rte_eth_ipv6_flow ipv6_flow; 585 struct i40e_gtp_flow gtp_flow; 586 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 587 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 588 struct i40e_raw_flow raw_flow; 589 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 590 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 591 struct i40e_esp_ipv4_flow esp_ipv4_flow; 592 struct i40e_esp_ipv6_flow esp_ipv6_flow; 593 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 594 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 595 }; 596 597 enum i40e_fdir_ip_type { 598 I40E_FDIR_IPTYPE_IPV4, 599 I40E_FDIR_IPTYPE_IPV6, 600 }; 601 602 /* A structure used to contain extend input of flow */ 603 struct i40e_fdir_flow_ext { 604 uint16_t vlan_tci; 605 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 606 /* It is filled by the flexible payload to match. */ 607 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 608 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 609 bool inner_ip; /* If there is inner ip */ 610 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 611 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 612 bool customized_pctype; /* If customized pctype is used */ 613 bool pkt_template; /* If raw packet template is used */ 614 bool is_udp; /* ipv4|ipv6 udp flow */ 615 }; 616 617 /* A structure used to define the input for a flow director filter entry */ 618 struct i40e_fdir_input { 619 enum i40e_filter_pctype pctype; 620 union i40e_fdir_flow flow; 621 /* Flow fields to match, dependent on flow_type */ 622 struct i40e_fdir_flow_ext flow_ext; 623 /* Additional fields to match */ 624 }; 625 626 /* Behavior will be taken if FDIR match */ 627 enum i40e_fdir_behavior { 628 I40E_FDIR_ACCEPT = 0, 629 I40E_FDIR_REJECT, 630 I40E_FDIR_PASSTHRU, 631 }; 632 633 /* Flow director report status 634 * It defines what will be reported if FDIR entry is matched. 635 */ 636 enum i40e_fdir_status { 637 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 638 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 639 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 640 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 641 }; 642 643 /* A structure used to define an action when match FDIR packet filter. */ 644 struct i40e_fdir_action { 645 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 646 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 647 enum i40e_fdir_status report_status; /* Status report option */ 648 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 649 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 650 * flex bytes start from in flexible payload. 651 */ 652 uint8_t flex_off; 653 }; 654 655 /* A structure used to define the flow director filter entry by filter_ctrl API 656 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and 657 * RTE_ETH_FILTER_DELETE operations. 658 */ 659 struct i40e_fdir_filter_conf { 660 uint32_t soft_id; 661 /* ID, an unique value is required when deal with FDIR entry */ 662 struct i40e_fdir_input input; /* Input set */ 663 struct i40e_fdir_action action; /* Action taken when match */ 664 }; 665 666 /* 667 * Structure to store flex pit for flow diretor. 668 */ 669 struct i40e_fdir_flex_pit { 670 uint8_t src_offset; /* offset in words from the beginning of payload */ 671 uint8_t size; /* size in words */ 672 uint8_t dst_offset; /* offset in words of flexible payload */ 673 }; 674 675 struct i40e_fdir_flex_mask { 676 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 677 uint8_t nb_bitmask; 678 struct { 679 uint8_t offset; 680 uint16_t mask; 681 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 682 }; 683 684 #define I40E_FILTER_PCTYPE_INVALID 0 685 #define I40E_FILTER_PCTYPE_MAX 64 686 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 687 688 struct i40e_fdir_filter { 689 TAILQ_ENTRY(i40e_fdir_filter) rules; 690 struct i40e_fdir_filter_conf fdir; 691 }; 692 693 /* fdir memory pool entry */ 694 struct i40e_fdir_entry { 695 struct rte_flow flow; 696 uint32_t idx; 697 }; 698 699 /* pre-allocated fdir memory pool */ 700 struct i40e_fdir_flow_pool { 701 /* a bitmap to manage the fdir pool */ 702 struct rte_bitmap *bitmap; 703 /* the size the pool is pf->fdir->fdir_space_size */ 704 struct i40e_fdir_entry *pool; 705 }; 706 707 #define FLOW_TO_FLOW_BITMAP(f) \ 708 container_of((f), struct i40e_fdir_entry, flow) 709 710 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 711 /* 712 * A structure used to define fields of a FDIR related info. 713 */ 714 struct i40e_fdir_info { 715 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 716 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 717 struct i40e_tx_queue *txq; 718 struct i40e_rx_queue *rxq; 719 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 720 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 721 /* 722 * txq available buffer counter, indicates how many available buffers 723 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 724 */ 725 int txq_available_buf_count; 726 727 /* input set bits for each pctype */ 728 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 729 /* 730 * the rule how bytes stream is extracted as flexible payload 731 * for each payload layer, the setting can up to three elements 732 */ 733 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 734 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 735 736 struct i40e_fdir_filter_list fdir_list; 737 struct i40e_fdir_filter **hash_map; 738 struct rte_hash *hash_table; 739 /* An array to store the inserted rules input */ 740 struct i40e_fdir_filter *fdir_filter_array; 741 742 /* 743 * Priority ordering at filter invalidation(destroying a flow) between 744 * "best effort" space and "guaranteed" space. 745 * 746 * 0 = At filter invalidation, the hardware first tries to increment the 747 * "best effort" space. The "guaranteed" space is incremented only when 748 * the global "best effort" space is at it max value or the "best effort" 749 * space of the PF is at its max value. 750 * 1 = At filter invalidation, the hardware first tries to increment its 751 * "guaranteed" space. The "best effort" space is incremented only when 752 * it is already at its max value. 753 */ 754 uint32_t fdir_invalprio; 755 /* the total size of the fdir, this number is the sum of the guaranteed + 756 * shared space 757 */ 758 uint32_t fdir_space_size; 759 /* the actual number of the fdir rules in hardware, initialized as 0 */ 760 uint32_t fdir_actual_cnt; 761 /* the free guaranteed space of the fdir */ 762 uint32_t fdir_guarantee_free_space; 763 /* the fdir total guaranteed space */ 764 uint32_t fdir_guarantee_total_space; 765 /* the pre-allocated pool of the rte_flow */ 766 struct i40e_fdir_flow_pool fdir_flow_pool; 767 768 /* Mark if flex pit and mask is set */ 769 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 770 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 771 772 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */ 773 }; 774 775 /* Ethertype filter number HW supports */ 776 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 777 778 /* Ethertype filter struct */ 779 struct i40e_ethertype_filter_input { 780 struct rte_ether_addr mac_addr; /* Mac address to match */ 781 uint16_t ether_type; /* Ether type to match */ 782 }; 783 784 struct i40e_ethertype_filter { 785 TAILQ_ENTRY(i40e_ethertype_filter) rules; 786 struct i40e_ethertype_filter_input input; 787 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 788 uint16_t queue; /* Queue assigned to when match */ 789 }; 790 791 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 792 793 struct i40e_ethertype_rule { 794 struct i40e_ethertype_filter_list ethertype_list; 795 struct i40e_ethertype_filter **hash_map; 796 struct rte_hash *hash_table; 797 }; 798 799 /* queue region info */ 800 struct i40e_queue_region_info { 801 /* the region id for this configuration */ 802 uint8_t region_id; 803 /* the start queue index for this region */ 804 uint8_t queue_start_index; 805 /* the total queue number of this queue region */ 806 uint8_t queue_num; 807 /* the total number of user priority for this region */ 808 uint8_t user_priority_num; 809 /* the packet's user priority for this region */ 810 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 811 /* the total number of flowtype for this region */ 812 uint8_t flowtype_num; 813 /** 814 * the pctype or hardware flowtype of packet, 815 * the specific index for each type has been defined 816 * in file i40e_type.h as enum i40e_filter_pctype. 817 */ 818 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 819 }; 820 821 struct i40e_queue_regions { 822 /* the total number of queue region for this port */ 823 uint16_t queue_region_number; 824 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 825 }; 826 827 struct i40e_rss_pattern_info { 828 uint8_t action_flag; 829 uint64_t types; 830 }; 831 832 /* Tunnel filter number HW supports */ 833 #define I40E_MAX_TUNNEL_FILTER_NUM 400 834 835 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 836 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 837 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 838 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 839 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 840 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 841 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 842 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 843 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 844 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 845 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 846 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 847 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 848 #define I40E_AQC_NEW_TR_21 21 849 #define I40E_AQC_NEW_TR_22 22 850 851 enum i40e_tunnel_iptype { 852 I40E_TUNNEL_IPTYPE_IPV4, 853 I40E_TUNNEL_IPTYPE_IPV6, 854 }; 855 856 /* Tunnel filter struct */ 857 struct i40e_tunnel_filter_input { 858 uint8_t outer_mac[6]; /* Outer mac address to match */ 859 uint8_t inner_mac[6]; /* Inner mac address to match */ 860 uint16_t inner_vlan; /* Inner vlan address to match */ 861 enum i40e_tunnel_iptype ip_type; 862 uint16_t flags; /* Filter type flag */ 863 uint32_t tenant_id; /* Tenant id to match */ 864 uint16_t general_fields[32]; /* Big buffer */ 865 }; 866 867 struct i40e_tunnel_filter { 868 TAILQ_ENTRY(i40e_tunnel_filter) rules; 869 struct i40e_tunnel_filter_input input; 870 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 871 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 872 uint16_t queue; /* Queue assigned to when match */ 873 }; 874 875 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 876 877 struct i40e_tunnel_rule { 878 struct i40e_tunnel_filter_list tunnel_list; 879 struct i40e_tunnel_filter **hash_map; 880 struct rte_hash *hash_table; 881 }; 882 883 /** 884 * Tunnel type. 885 */ 886 enum i40e_tunnel_type { 887 I40E_TUNNEL_TYPE_NONE = 0, 888 I40E_TUNNEL_TYPE_VXLAN, 889 I40E_TUNNEL_TYPE_GENEVE, 890 I40E_TUNNEL_TYPE_TEREDO, 891 I40E_TUNNEL_TYPE_NVGRE, 892 I40E_TUNNEL_TYPE_IP_IN_GRE, 893 I40E_L2_TUNNEL_TYPE_E_TAG, 894 I40E_TUNNEL_TYPE_MPLSoUDP, 895 I40E_TUNNEL_TYPE_MPLSoGRE, 896 I40E_TUNNEL_TYPE_QINQ, 897 I40E_TUNNEL_TYPE_GTPC, 898 I40E_TUNNEL_TYPE_GTPU, 899 I40E_TUNNEL_TYPE_ESPoUDP, 900 I40E_TUNNEL_TYPE_ESPoIP, 901 I40E_CLOUD_TYPE_UDP, 902 I40E_CLOUD_TYPE_TCP, 903 I40E_CLOUD_TYPE_SCTP, 904 I40E_TUNNEL_TYPE_MAX, 905 }; 906 907 /** 908 * L4 port type. 909 */ 910 enum i40e_l4_port_type { 911 I40E_L4_PORT_TYPE_SRC = 0, 912 I40E_L4_PORT_TYPE_DST, 913 }; 914 915 /** 916 * Tunneling Packet filter configuration. 917 */ 918 struct i40e_tunnel_filter_conf { 919 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 920 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 921 uint16_t inner_vlan; /**< Inner VLAN to match. */ 922 uint32_t outer_vlan; /**< Outer VLAN to match */ 923 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 924 /** 925 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 926 * is set in filter_type, or inner destination IP address to match 927 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 928 */ 929 union { 930 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 931 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 932 } ip_addr; 933 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 934 uint16_t filter_type; 935 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 936 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 937 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 938 uint16_t queue_id; /**< Queue assigned to if match. */ 939 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 940 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 941 }; 942 943 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 944 #define I40E_MAX_MIRROR_RULES 64 945 /* 946 * Mirror rule structure 947 */ 948 struct i40e_mirror_rule { 949 TAILQ_ENTRY(i40e_mirror_rule) rules; 950 uint8_t rule_type; 951 uint16_t index; /* the sw index of mirror rule */ 952 uint16_t id; /* the rule id assigned by firmware */ 953 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 954 uint16_t num_entries; 955 /* the info stores depend on the rule type. 956 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 957 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 958 */ 959 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 960 }; 961 962 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 963 964 TAILQ_HEAD(i40e_flow_list, rte_flow); 965 966 /* Struct to store Traffic Manager shaper profile. */ 967 struct i40e_tm_shaper_profile { 968 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 969 uint32_t shaper_profile_id; 970 uint32_t reference_count; 971 struct rte_tm_shaper_params profile; 972 }; 973 974 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 975 976 /* node type of Traffic Manager */ 977 enum i40e_tm_node_type { 978 I40E_TM_NODE_TYPE_PORT, 979 I40E_TM_NODE_TYPE_TC, 980 I40E_TM_NODE_TYPE_QUEUE, 981 I40E_TM_NODE_TYPE_MAX, 982 }; 983 984 /* Struct to store Traffic Manager node configuration. */ 985 struct i40e_tm_node { 986 TAILQ_ENTRY(i40e_tm_node) node; 987 uint32_t id; 988 uint32_t priority; 989 uint32_t weight; 990 uint32_t reference_count; 991 struct i40e_tm_node *parent; 992 struct i40e_tm_shaper_profile *shaper_profile; 993 struct rte_tm_node_params params; 994 }; 995 996 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 997 998 /* Struct to store all the Traffic Manager configuration. */ 999 struct i40e_tm_conf { 1000 struct i40e_shaper_profile_list shaper_profile_list; 1001 struct i40e_tm_node *root; /* root node - port */ 1002 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 1003 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 1004 /** 1005 * The number of added TC nodes. 1006 * It should be no more than the TC number of this port. 1007 */ 1008 uint32_t nb_tc_node; 1009 /** 1010 * The number of added queue nodes. 1011 * It should be no more than the queue number of this port. 1012 */ 1013 uint32_t nb_queue_node; 1014 /** 1015 * This flag is used to check if APP can change the TM node 1016 * configuration. 1017 * When it's true, means the configuration is applied to HW, 1018 * APP should not change the configuration. 1019 * As we don't support on-the-fly configuration, when starting 1020 * the port, APP should call the hierarchy_commit API to set this 1021 * flag to true. When stopping the port, this flag should be set 1022 * to false. 1023 */ 1024 bool committed; 1025 }; 1026 1027 enum i40e_new_pctype { 1028 I40E_CUSTOMIZED_GTPC = 0, 1029 I40E_CUSTOMIZED_GTPU_IPV4, 1030 I40E_CUSTOMIZED_GTPU_IPV6, 1031 I40E_CUSTOMIZED_GTPU, 1032 I40E_CUSTOMIZED_IPV4_L2TPV3, 1033 I40E_CUSTOMIZED_IPV6_L2TPV3, 1034 I40E_CUSTOMIZED_ESP_IPV4, 1035 I40E_CUSTOMIZED_ESP_IPV6, 1036 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1037 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1038 I40E_CUSTOMIZED_AH_IPV4, 1039 I40E_CUSTOMIZED_AH_IPV6, 1040 I40E_CUSTOMIZED_MAX, 1041 }; 1042 1043 #define I40E_FILTER_PCTYPE_INVALID 0 1044 struct i40e_customized_pctype { 1045 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1046 uint8_t pctype; /* New pctype value */ 1047 bool valid; /* Check if it's valid */ 1048 }; 1049 1050 struct i40e_rte_flow_rss_conf { 1051 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1052 uint16_t queue_region_conf; /**< Queue region config flag */ 1053 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1054 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1055 sizeof(uint32_t)]; /* Hash key. */ 1056 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */ 1057 bool valid; /* Check if it's valid */ 1058 }; 1059 1060 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1061 1062 /* RSS filter list structure */ 1063 struct i40e_rss_filter { 1064 TAILQ_ENTRY(i40e_rss_filter) next; 1065 struct i40e_rte_flow_rss_conf rss_filter_info; 1066 }; 1067 1068 struct i40e_vf_msg_cfg { 1069 /* maximal VF message during a statistic period */ 1070 uint32_t max_msg; 1071 1072 /* statistic period, in second */ 1073 uint32_t period; 1074 /* 1075 * If message statistics from a VF exceed the maximal limitation, 1076 * the PF will ignore any new message from that VF for 1077 * 'ignor_second' time. 1078 */ 1079 uint32_t ignore_second; 1080 }; 1081 1082 /* 1083 * Structure to store private data specific for PF instance. 1084 */ 1085 struct i40e_pf { 1086 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1087 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1088 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1089 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1090 uint16_t max_num_vsi; 1091 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1092 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1093 1094 struct i40e_hw_port_stats stats_offset; 1095 struct i40e_hw_port_stats stats; 1096 /* internal packet statistics, it should be excluded from the total */ 1097 struct i40e_eth_stats internal_stats_offset; 1098 struct i40e_eth_stats internal_stats; 1099 bool offset_loaded; 1100 1101 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1102 struct rte_ether_addr dev_addr; /* PF device mac address */ 1103 uint64_t flags; /* PF feature flags */ 1104 /* All kinds of queue pair setting for different VSIs */ 1105 struct i40e_pf_vf *vfs; 1106 uint16_t vf_num; 1107 /* Each of below queue pairs should be power of 2 since it's the 1108 precondition after TC configuration applied */ 1109 uint16_t lan_nb_qp_max; 1110 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1111 uint16_t lan_qp_offset; 1112 uint16_t vmdq_nb_qp_max; 1113 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1114 uint16_t vmdq_qp_offset; 1115 uint16_t vf_nb_qp_max; 1116 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1117 uint16_t vf_qp_offset; 1118 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1119 uint16_t fdir_qp_offset; 1120 1121 uint16_t hash_lut_size; /* The size of hash lookup table */ 1122 /* input set bits for each pctype */ 1123 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1124 /* store VXLAN UDP ports */ 1125 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1126 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1127 1128 /* VMDQ related info */ 1129 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1130 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1131 struct i40e_vmdq_info *vmdq; 1132 1133 struct i40e_fdir_info fdir; /* flow director info */ 1134 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1135 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1136 struct i40e_rte_flow_rss_conf rss_info; /* RSS info */ 1137 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1138 struct i40e_queue_regions queue_region; /* queue region info */ 1139 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1140 struct i40e_mirror_rule_list mirror_list; 1141 uint16_t nb_mirror_rule; /* The number of mirror rules */ 1142 bool floating_veb; /* The flag to use the floating VEB */ 1143 /* The floating enable flag for the specific VF */ 1144 bool floating_veb_list[I40E_MAX_VF]; 1145 struct i40e_flow_list flow_list; 1146 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1147 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1148 bool qinq_replace_flag; /* QINQ filter replace is done */ 1149 /* l4 port flag */ 1150 bool sport_replace_flag; /* Source port replace is done */ 1151 bool dport_replace_flag; /* Destination port replace is done */ 1152 struct i40e_tm_conf tm_conf; 1153 bool support_multi_driver; /* 1 - support multiple driver */ 1154 1155 /* Dynamic Device Personalization */ 1156 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1157 bool esp_support; /* 1 - support ESP SPI */ 1158 /* customer customized pctype */ 1159 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1160 /* Switch Domain Id */ 1161 uint16_t switch_domain_id; 1162 1163 struct i40e_vf_msg_cfg vf_msg_cfg; 1164 uint64_t prev_rx_bytes; 1165 uint64_t prev_tx_bytes; 1166 uint64_t internal_prev_rx_bytes; 1167 uint64_t internal_prev_tx_bytes; 1168 }; 1169 1170 enum pending_msg { 1171 PFMSG_LINK_CHANGE = 0x1, 1172 PFMSG_RESET_IMPENDING = 0x2, 1173 PFMSG_DRIVER_CLOSE = 0x4, 1174 }; 1175 1176 struct i40e_vsi_vlan_pvid_info { 1177 uint16_t on; /* Enable or disable pvid */ 1178 union { 1179 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1180 struct { 1181 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1182 * while 'untagged' will reject untagged packets. 1183 */ 1184 uint8_t tagged; 1185 uint8_t untagged; 1186 } reject; 1187 } config; 1188 }; 1189 1190 struct i40e_vf_rx_queues { 1191 uint64_t rx_dma_addr; 1192 uint32_t rx_ring_len; 1193 uint32_t buff_size; 1194 }; 1195 1196 struct i40e_vf_tx_queues { 1197 uint64_t tx_dma_addr; 1198 uint32_t tx_ring_len; 1199 }; 1200 1201 /* 1202 * Structure to store private data specific for VF instance. 1203 */ 1204 struct i40e_vf { 1205 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 1206 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1207 uint16_t num_queue_pairs; 1208 uint16_t max_pkt_len; /* Maximum packet length */ 1209 bool promisc_unicast_enabled; 1210 bool promisc_multicast_enabled; 1211 1212 uint32_t version_major; /* Major version number */ 1213 uint32_t version_minor; /* Minor version number */ 1214 uint16_t promisc_flags; /* Promiscuous setting */ 1215 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1216 1217 /* Multicast addrs */ 1218 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; 1219 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1220 1221 /* Event from pf */ 1222 bool dev_closed; 1223 bool link_up; 1224 enum virtchnl_link_speed link_speed; 1225 bool vf_reset; 1226 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1227 int32_t cmd_retval; /* return value of the cmd response from PF */ 1228 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1229 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1230 1231 /* VSI info */ 1232 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1233 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1234 struct i40e_vsi vsi; 1235 uint64_t flags; 1236 }; 1237 1238 #define I40E_MAX_PKT_TYPE 256 1239 #define I40E_FLOW_TYPE_MAX 64 1240 1241 /* 1242 * Structure to store private data for each PF/VF instance. 1243 */ 1244 struct i40e_adapter { 1245 /* Common for both PF and VF */ 1246 struct i40e_hw hw; 1247 struct rte_eth_dev *eth_dev; 1248 1249 /* Specific for PF or VF */ 1250 union { 1251 struct i40e_pf pf; 1252 struct i40e_vf vf; 1253 }; 1254 1255 /* For vector PMD */ 1256 bool rx_bulk_alloc_allowed; 1257 bool rx_vec_allowed; 1258 bool tx_simple_allowed; 1259 bool tx_vec_allowed; 1260 1261 /* For PTP */ 1262 struct rte_timecounter systime_tc; 1263 struct rte_timecounter rx_tstamp_tc; 1264 struct rte_timecounter tx_tstamp_tc; 1265 1266 /* ptype mapping table */ 1267 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1268 /* flow type to pctype mapping table */ 1269 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1270 uint64_t flow_types_mask; 1271 uint64_t pctypes_mask; 1272 1273 /* For devargs */ 1274 uint8_t use_latest_vec; 1275 1276 /* For RSS reta table update */ 1277 uint8_t rss_reta_updated; 1278 }; 1279 1280 /** 1281 * Strucute to store private data for each VF representor instance 1282 */ 1283 struct i40e_vf_representor { 1284 uint16_t switch_domain_id; 1285 /**< Virtual Function ID */ 1286 uint16_t vf_id; 1287 /**< Virtual Function ID */ 1288 struct i40e_adapter *adapter; 1289 /**< Private data store of assocaiated physical function */ 1290 struct i40e_eth_stats stats_offset; 1291 /**< Zero-point of VF statistics*/ 1292 }; 1293 1294 extern const struct rte_flow_ops i40e_flow_ops; 1295 1296 union i40e_filter_t { 1297 struct rte_eth_ethertype_filter ethertype_filter; 1298 struct i40e_fdir_filter_conf fdir_filter; 1299 struct rte_eth_tunnel_filter_conf tunnel_filter; 1300 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1301 struct i40e_rte_flow_rss_conf rss_conf; 1302 }; 1303 1304 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1305 const struct rte_flow_attr *attr, 1306 const struct rte_flow_item pattern[], 1307 const struct rte_flow_action actions[], 1308 struct rte_flow_error *error, 1309 union i40e_filter_t *filter); 1310 struct i40e_valid_pattern { 1311 enum rte_flow_item_type *items; 1312 parse_filter_t parse_filter; 1313 }; 1314 1315 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1316 int i40e_vsi_release(struct i40e_vsi *vsi); 1317 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1318 enum i40e_vsi_type type, 1319 struct i40e_vsi *uplink_vsi, 1320 uint16_t user_param); 1321 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1322 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1323 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1324 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1325 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1326 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1327 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1328 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1329 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1330 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1331 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1332 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1333 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1334 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1335 struct i40e_vsi_vlan_pvid_info *info); 1336 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1337 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1338 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1339 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1340 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1341 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1342 int i40e_fdir_setup(struct i40e_pf *pf); 1343 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1344 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1345 uint32_t len, 1346 int socket_id); 1347 int i40e_fdir_configure(struct rte_eth_dev *dev); 1348 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1349 void i40e_fdir_teardown(struct i40e_pf *pf); 1350 enum i40e_filter_pctype 1351 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1352 uint16_t flow_type); 1353 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1354 enum i40e_filter_pctype pctype); 1355 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1356 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1357 struct rte_eth_fdir_info *fdir); 1358 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1359 struct rte_eth_fdir_stats *stat); 1360 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev, 1361 enum rte_filter_op filter_op, 1362 void *arg); 1363 int i40e_select_filter_input_set(struct i40e_hw *hw, 1364 struct rte_eth_input_set_conf *conf, 1365 enum rte_filter_type filter); 1366 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1367 int i40e_hash_filter_inset_select(struct i40e_hw *hw, 1368 struct rte_eth_input_set_conf *conf); 1369 int i40e_fdir_filter_inset_select(struct i40e_pf *pf, 1370 struct rte_eth_input_set_conf *conf); 1371 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1372 uint32_t retval, uint8_t *msg, 1373 uint16_t msglen); 1374 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1375 struct rte_eth_rxq_info *qinfo); 1376 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1377 struct rte_eth_txq_info *qinfo); 1378 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1379 struct rte_eth_burst_mode *mode); 1380 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1381 struct rte_eth_burst_mode *mode); 1382 struct i40e_ethertype_filter * 1383 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1384 const struct i40e_ethertype_filter_input *input); 1385 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1386 struct i40e_ethertype_filter_input *input); 1387 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1388 struct i40e_fdir_input *input); 1389 struct i40e_tunnel_filter * 1390 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1391 const struct i40e_tunnel_filter_input *input); 1392 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1393 struct i40e_tunnel_filter_input *input); 1394 uint64_t i40e_get_default_input_set(uint16_t pctype); 1395 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1396 struct rte_eth_ethertype_filter *filter, 1397 bool add); 1398 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev, 1399 const struct rte_eth_fdir_filter *filter, 1400 bool add); 1401 struct rte_flow * 1402 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1403 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1404 struct rte_flow *flow); 1405 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1406 const struct i40e_fdir_filter_conf *filter, 1407 bool add); 1408 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1409 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1410 uint8_t add); 1411 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1412 struct i40e_tunnel_filter_conf *tunnel_filter, 1413 uint8_t add); 1414 int i40e_fdir_flush(struct rte_eth_dev *dev); 1415 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1416 struct i40e_macvlan_filter *mv_f, 1417 int num, struct rte_ether_addr *addr); 1418 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1419 struct i40e_macvlan_filter *filter, 1420 int total); 1421 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1422 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1423 struct i40e_macvlan_filter *filter, 1424 int total); 1425 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1426 bool is_i40e_supported(struct rte_eth_dev *dev); 1427 bool is_i40evf_supported(struct rte_eth_dev *dev); 1428 1429 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1430 enum rte_filter_type filter, uint64_t inset); 1431 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, 1432 uint8_t nb_elem); 1433 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1434 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1435 void i40e_check_write_global_reg(struct i40e_hw *hw, 1436 uint32_t addr, uint32_t val); 1437 1438 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1439 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1440 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1441 struct i40e_customized_pctype* 1442 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1443 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1444 uint32_t pkg_size, 1445 enum rte_pmd_i40e_package_op op); 1446 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1447 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1448 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1449 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1450 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1451 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1452 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1453 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, 1454 const struct rte_flow_action_rss *in); 1455 int i40e_config_rss_filter(struct i40e_pf *pf, 1456 struct i40e_rte_flow_rss_conf *conf, bool add); 1457 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1458 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1459 1460 #define I40E_DEV_TO_PCI(eth_dev) \ 1461 RTE_DEV_TO_PCI((eth_dev)->device) 1462 1463 /* I40E_DEV_PRIVATE_TO */ 1464 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1465 (&((struct i40e_adapter *)adapter)->pf) 1466 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1467 (&((struct i40e_adapter *)adapter)->hw) 1468 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1469 ((struct i40e_adapter *)adapter) 1470 1471 /* I40EVF_DEV_PRIVATE_TO */ 1472 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1473 (&((struct i40e_adapter *)adapter)->vf) 1474 1475 static inline struct i40e_vsi * 1476 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1477 { 1478 struct i40e_hw *hw; 1479 1480 if (!adapter) 1481 return NULL; 1482 1483 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1484 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1485 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1486 return &vf->vsi; 1487 } else { 1488 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1489 return pf->main_vsi; 1490 } 1491 } 1492 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1493 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1494 1495 /* I40E_VSI_TO */ 1496 #define I40E_VSI_TO_HW(vsi) \ 1497 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1498 #define I40E_VSI_TO_PF(vsi) \ 1499 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1500 #define I40E_VSI_TO_VF(vsi) \ 1501 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1502 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1503 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1504 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1505 (((struct i40e_vsi *)vsi)->adapter->eth_dev) 1506 1507 /* I40E_PF_TO */ 1508 #define I40E_PF_TO_HW(pf) \ 1509 (&(((struct i40e_pf *)pf)->adapter->hw)) 1510 #define I40E_PF_TO_ADAPTER(pf) \ 1511 ((struct i40e_adapter *)pf->adapter) 1512 1513 /* I40E_VF_TO */ 1514 #define I40E_VF_TO_HW(vf) \ 1515 (&(((struct i40e_vf *)vf)->adapter->hw)) 1516 1517 static inline void 1518 i40e_init_adminq_parameter(struct i40e_hw *hw) 1519 { 1520 hw->aq.num_arq_entries = I40E_AQ_LEN; 1521 hw->aq.num_asq_entries = I40E_AQ_LEN; 1522 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1523 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1524 } 1525 1526 static inline int 1527 i40e_align_floor(int n) 1528 { 1529 if (n == 0) 1530 return 0; 1531 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1532 } 1533 1534 static inline uint16_t 1535 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1536 { 1537 uint16_t interval = 0; 1538 1539 if (is_multi_drv) { 1540 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1541 } else { 1542 if (is_pf) 1543 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1544 else 1545 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1546 } 1547 1548 /* Convert to hardware count, as writing each 1 represents 2 us */ 1549 return interval / 2; 1550 } 1551 1552 #define I40E_VALID_FLOW(flow_type) \ 1553 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1554 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1555 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1556 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1557 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1558 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1559 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1560 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1561 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1562 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1563 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1564 1565 #define I40E_VALID_PCTYPE_X722(pctype) \ 1566 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1567 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1568 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1569 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1570 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1571 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1572 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1573 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1574 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1575 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1576 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1577 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1578 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1579 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1580 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1581 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1582 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1583 1584 #define I40E_VALID_PCTYPE(pctype) \ 1585 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1586 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1587 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1588 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1589 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1590 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1591 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1592 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1593 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1594 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1595 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1596 1597 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1598 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1599 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1600 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1601 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1602 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1603 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1604 1605 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1606 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1607 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1608 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1609 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1610 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1611 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1612 1613 #endif /* _I40E_ETHDEV_H_ */ 1614