1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 #include <sys/queue.h> 10 11 #include <rte_time.h> 12 #include <rte_kvargs.h> 13 #include <rte_hash.h> 14 #include <rte_flow.h> 15 #include <rte_flow_driver.h> 16 #include <rte_tm_driver.h> 17 #include "rte_pmd_i40e.h" 18 19 #include "base/i40e_register.h" 20 #include "base/i40e_type.h" 21 #include "base/virtchnl.h" 22 23 #define I40E_VLAN_TAG_SIZE 4 24 25 #define I40E_AQ_LEN 32 26 #define I40E_AQ_BUF_SZ 4096 27 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 28 #define I40E_MAX_Q_PER_TC 64 29 #define I40E_NUM_DESC_DEFAULT 512 30 #define I40E_NUM_DESC_ALIGN 32 31 #define I40E_BUF_SIZE_MIN 1024 32 #define I40E_FRAME_SIZE_MAX 9728 33 #define I40E_TSO_FRAME_SIZE_MAX 262144 34 #define I40E_QUEUE_BASE_ADDR_UNIT 128 35 /* number of VSIs and queue default setting */ 36 #define I40E_MAX_QP_NUM_PER_VF 16 37 #define I40E_DEFAULT_QP_NUM_FDIR 1 38 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 39 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 40 /* Maximun number of MAC addresses */ 41 #define I40E_NUM_MACADDR_MAX 64 42 /* Maximum number of VFs */ 43 #define I40E_MAX_VF 128 44 /*flag of no loopback*/ 45 #define I40E_AQ_LB_MODE_NONE 0x0 46 /* 47 * vlan_id is a 12 bit number. 48 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 49 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 50 * The higher 7 bit val specifies VFTA array index. 51 */ 52 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 53 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 54 55 /* Default TC traffic in case DCB is not enabled */ 56 #define I40E_DEFAULT_TCMAP 0x1 57 #define I40E_FDIR_QUEUE_ID 0 58 59 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 60 #define I40E_VMDQ_POOL_BASE 1 61 62 #define I40E_DEFAULT_RX_FREE_THRESH 32 63 #define I40E_DEFAULT_RX_PTHRESH 8 64 #define I40E_DEFAULT_RX_HTHRESH 8 65 #define I40E_DEFAULT_RX_WTHRESH 0 66 67 #define I40E_DEFAULT_TX_FREE_THRESH 32 68 #define I40E_DEFAULT_TX_PTHRESH 32 69 #define I40E_DEFAULT_TX_HTHRESH 0 70 #define I40E_DEFAULT_TX_WTHRESH 0 71 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 72 73 /* Bit shift and mask */ 74 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 75 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 76 #define I40E_8_BIT_WIDTH CHAR_BIT 77 #define I40E_8_BIT_MASK UINT8_MAX 78 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 79 #define I40E_16_BIT_MASK UINT16_MAX 80 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 81 #define I40E_32_BIT_MASK UINT32_MAX 82 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 83 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 84 85 /* Linux PF host with virtchnl version 1.1 */ 86 #define PF_IS_V11(vf) \ 87 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 88 ((vf)->version_minor == 1)) 89 90 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 91 do { \ 92 uint32_t ori_val; \ 93 struct rte_eth_dev *dev; \ 94 struct rte_eth_dev_data *dev_data; \ 95 ori_val = I40E_READ_REG((hw), (reg)); \ 96 dev_data = ((struct i40e_adapter *)hw->back)->pf.dev_data; \ 97 dev = &rte_eth_devices[dev_data->port_id]; \ 98 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 99 (reg)), (value)); \ 100 if (ori_val != value) \ 101 PMD_DRV_LOG(WARNING, \ 102 "i40e device %s changed global " \ 103 "register [0x%08x]. original: 0x%08x, " \ 104 "new: 0x%08x ", \ 105 (dev->device->name), (reg), \ 106 (ori_val), (value)); \ 107 } while (0) 108 109 /* index flex payload per layer */ 110 enum i40e_flxpld_layer_idx { 111 I40E_FLXPLD_L2_IDX = 0, 112 I40E_FLXPLD_L3_IDX = 1, 113 I40E_FLXPLD_L4_IDX = 2, 114 I40E_MAX_FLXPLD_LAYER = 3, 115 }; 116 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 117 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 118 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 119 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 120 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 121 122 /* i40e flags */ 123 #define I40E_FLAG_RSS (1ULL << 0) 124 #define I40E_FLAG_DCB (1ULL << 1) 125 #define I40E_FLAG_VMDQ (1ULL << 2) 126 #define I40E_FLAG_SRIOV (1ULL << 3) 127 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 128 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 129 #define I40E_FLAG_FDIR (1ULL << 6) 130 #define I40E_FLAG_VXLAN (1ULL << 7) 131 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 132 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 133 I40E_FLAG_DCB | \ 134 I40E_FLAG_VMDQ | \ 135 I40E_FLAG_SRIOV | \ 136 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 137 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 138 I40E_FLAG_FDIR | \ 139 I40E_FLAG_VXLAN | \ 140 I40E_FLAG_RSS_AQ_CAPABLE) 141 142 #define I40E_RSS_OFFLOAD_ALL ( \ 143 ETH_RSS_FRAG_IPV4 | \ 144 ETH_RSS_NONFRAG_IPV4_TCP | \ 145 ETH_RSS_NONFRAG_IPV4_UDP | \ 146 ETH_RSS_NONFRAG_IPV4_SCTP | \ 147 ETH_RSS_NONFRAG_IPV4_OTHER | \ 148 ETH_RSS_FRAG_IPV6 | \ 149 ETH_RSS_NONFRAG_IPV6_TCP | \ 150 ETH_RSS_NONFRAG_IPV6_UDP | \ 151 ETH_RSS_NONFRAG_IPV6_SCTP | \ 152 ETH_RSS_NONFRAG_IPV6_OTHER | \ 153 ETH_RSS_L2_PAYLOAD) 154 155 /* All bits of RSS hash enable for X722*/ 156 #define I40E_RSS_HENA_ALL_X722 ( \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 158 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 160 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 161 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 162 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 163 I40E_RSS_HENA_ALL) 164 165 /* All bits of RSS hash enable */ 166 #define I40E_RSS_HENA_ALL ( \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 171 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 176 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 177 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 178 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 179 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 180 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 181 182 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 183 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 184 185 /* Default queue interrupt throttling time in microseconds */ 186 #define I40E_ITR_INDEX_DEFAULT 0 187 #define I40E_ITR_INDEX_NONE 3 188 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 189 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 190 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 191 /* Special FW support this floating VEB feature */ 192 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 193 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 194 195 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 196 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 197 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 198 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 199 200 #define I40E_RSS_TYPE_NONE 0ULL 201 #define I40E_RSS_TYPE_INVALID 1ULL 202 203 #define I40E_INSET_NONE 0x00000000000000000ULL 204 205 /* bit0 ~ bit 7 */ 206 #define I40E_INSET_DMAC 0x0000000000000001ULL 207 #define I40E_INSET_SMAC 0x0000000000000002ULL 208 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 209 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 210 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 211 212 /* bit 8 ~ bit 15 */ 213 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 214 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 215 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 216 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 217 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 218 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 219 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 220 221 /* bit 16 ~ bit 31 */ 222 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 223 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 224 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 225 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 226 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 227 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 228 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 229 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 230 231 /* bit 32 ~ bit 47, tunnel fields */ 232 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 233 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 234 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 235 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 236 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 237 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 238 239 /* bit 48 ~ bit 55 */ 240 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 241 242 /* bit 56 ~ bit 63, Flex Payload */ 243 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 244 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 245 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 246 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 247 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 248 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 249 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 250 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 251 #define I40E_INSET_FLEX_PAYLOAD \ 252 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 253 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 254 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 255 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 256 257 /* The max bandwidth of i40e is 40Gbps. */ 258 #define I40E_QOS_BW_MAX 40000 259 /* The bandwidth should be the multiple of 50Mbps. */ 260 #define I40E_QOS_BW_GRANULARITY 50 261 /* The min bandwidth weight is 1. */ 262 #define I40E_QOS_BW_WEIGHT_MIN 1 263 /* The max bandwidth weight is 127. */ 264 #define I40E_QOS_BW_WEIGHT_MAX 127 265 /* The max queue region index is 7. */ 266 #define I40E_REGION_MAX_INDEX 7 267 268 #define I40E_MAX_PERCENT 100 269 #define I40E_DEFAULT_DCB_APP_NUM 1 270 #define I40E_DEFAULT_DCB_APP_PRIO 3 271 272 #define I40E_FDIR_PRG_PKT_CNT 128 273 274 /* 275 * Struct to store flow created. 276 */ 277 struct rte_flow { 278 TAILQ_ENTRY(rte_flow) node; 279 enum rte_filter_type filter_type; 280 void *rule; 281 }; 282 283 /** 284 * The overhead from MTU to max frame size. 285 * Considering QinQ packet, the VLAN tag needs to be counted twice. 286 */ 287 #define I40E_ETH_OVERHEAD \ 288 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 289 #define I40E_ETH_MAX_LEN (RTE_ETHER_MTU + I40E_ETH_OVERHEAD) 290 291 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) 292 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) 293 294 struct i40e_adapter; 295 struct rte_pci_driver; 296 297 /** 298 * MAC filter type 299 */ 300 enum i40e_mac_filter_type { 301 I40E_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */ 302 I40E_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */ 303 I40E_MAC_HASH_MATCH, /**< hash match of MAC addr. */ 304 /** hash match of MAC addr and exact match of VLAN ID. */ 305 I40E_MACVLAN_HASH_MATCH, 306 }; 307 308 /** 309 * MAC filter structure 310 */ 311 struct i40e_mac_filter_info { 312 enum i40e_mac_filter_type filter_type; 313 struct rte_ether_addr mac_addr; 314 }; 315 316 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 317 318 /* MAC filter list structure */ 319 struct i40e_mac_filter { 320 TAILQ_ENTRY(i40e_mac_filter) next; 321 struct i40e_mac_filter_info mac_info; 322 }; 323 324 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 325 326 struct i40e_vsi; 327 328 /* VSI list structure */ 329 struct i40e_vsi_list { 330 TAILQ_ENTRY(i40e_vsi_list) list; 331 struct i40e_vsi *vsi; 332 }; 333 334 struct i40e_rx_queue; 335 struct i40e_tx_queue; 336 337 /* Bandwidth limit information */ 338 struct i40e_bw_info { 339 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 340 uint8_t bw_max; /* Max BW limit if enabled */ 341 342 /* Relative credits within same TC with respect to other VSIs or Comps */ 343 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 344 /* Bandwidth limit per TC */ 345 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 346 /* Max bandwidth limit per TC */ 347 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 348 }; 349 350 /* Structure that defines a VEB */ 351 struct i40e_veb { 352 struct i40e_vsi_list_head head; 353 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 354 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 355 uint16_t seid; /* The seid of VEB itself */ 356 uint16_t uplink_seid; /* The uplink seid of this VEB */ 357 uint16_t stats_idx; 358 struct i40e_eth_stats stats; 359 uint8_t enabled_tc; /* The traffic class enabled */ 360 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 361 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 362 }; 363 364 /* i40e MACVLAN filter structure */ 365 struct i40e_macvlan_filter { 366 struct rte_ether_addr macaddr; 367 enum i40e_mac_filter_type filter_type; 368 uint16_t vlan_id; 369 }; 370 371 /* 372 * Structure that defines a VSI, associated with a adapter. 373 */ 374 struct i40e_vsi { 375 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 376 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 377 378 struct i40e_eth_stats eth_stats_offset; 379 struct i40e_eth_stats eth_stats; 380 /* 381 * When drivers loaded, only a default main VSI exists. In case new VSI 382 * needs to add, HW needs to know the layout that VSIs are organized. 383 * Besides that, VSI isan element and can't switch packets, which needs 384 * to add new component VEB to perform switching. So, a new VSI needs 385 * to specify the uplink VSI (Parent VSI) before created. The 386 * uplink VSI will check whether it had a VEB to switch packets. If no, 387 * it will try to create one. Then, uplink VSI will move the new VSI 388 * into its' sib_vsi_list to manage all the downlink VSI. 389 * sib_vsi_list: the VSI list that shared the same uplink VSI. 390 * parent_vsi : the uplink VSI. It's NULL for main VSI. 391 * veb : the VEB associates with the VSI. 392 */ 393 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 394 struct i40e_vsi *parent_vsi; 395 struct i40e_veb *veb; /* Associated veb, could be null */ 396 struct i40e_veb *floating_veb; /* Associated floating veb */ 397 bool offset_loaded; 398 enum i40e_vsi_type type; /* VSI types */ 399 uint16_t vlan_num; /* Total VLAN number */ 400 uint16_t mac_num; /* Total mac number */ 401 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 402 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 403 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 404 uint32_t user_param; 405 uint16_t seid; /* The seid of VSI itself */ 406 uint16_t uplink_seid; /* The uplink seid of this VSI */ 407 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 408 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 409 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 410 uint16_t base_queue; /* The first queue index of this VSI */ 411 /* 412 * The offset to visit VSI related register, assigned by HW when 413 * creating VSI 414 */ 415 uint16_t vsi_id; 416 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 417 uint16_t nb_msix; /* The max number of msix vector */ 418 uint8_t enabled_tc; /* The traffic class enabled */ 419 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 420 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 421 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 422 uint64_t prev_rx_bytes; 423 uint64_t prev_tx_bytes; 424 }; 425 426 struct pool_entry { 427 LIST_ENTRY(pool_entry) next; 428 uint16_t base; 429 uint16_t len; 430 }; 431 432 LIST_HEAD(res_list, pool_entry); 433 434 struct i40e_res_pool_info { 435 uint32_t base; /* Resource start index */ 436 uint32_t num_alloc; /* Allocated resource number */ 437 uint32_t num_free; /* Total available resource number */ 438 struct res_list alloc_list; /* Allocated resource list */ 439 struct res_list free_list; /* Available resource list */ 440 }; 441 442 enum I40E_VF_STATE { 443 I40E_VF_INACTIVE = 0, 444 I40E_VF_INRESET, 445 I40E_VF_ININIT, 446 I40E_VF_ACTIVE, 447 }; 448 449 /* 450 * Structure to store private data for PF host. 451 */ 452 struct i40e_pf_vf { 453 struct i40e_pf *pf; 454 struct i40e_vsi *vsi; 455 enum I40E_VF_STATE state; /* The number of queue pairs available */ 456 uint16_t vf_idx; /* VF index in pf->vfs */ 457 uint16_t lan_nb_qps; /* Actual queues allocated */ 458 uint16_t reset_cnt; /* Total vf reset times */ 459 struct rte_ether_addr mac_addr; /* Default MAC address */ 460 /* version of the virtchnl from VF */ 461 struct virtchnl_version_info version; 462 uint32_t request_caps; /* offload caps requested from VF */ 463 uint64_t num_mdd_events; /* num of mdd events detected */ 464 465 /* 466 * Variables for store the arrival timestamp of VF messages. 467 * If the timestamp of latest message stored at 468 * `msg_timestamps[index % max]` then the timestamp of 469 * earliest message stored at `msg_time[(index + 1) % max]`. 470 * When a new message come, the timestamp of this message 471 * will be stored at `msg_timestamps[(index + 1) % max]` and the 472 * earliest message timestamp is at 473 * `msg_timestamps[(index + 2) % max]` now... 474 */ 475 uint32_t msg_index; 476 uint64_t *msg_timestamps; 477 478 /* cycle of stop ignoring VF message */ 479 uint64_t ignore_end_cycle; 480 }; 481 482 /* 483 * Structure to store private data for flow control. 484 */ 485 struct i40e_fc_conf { 486 uint16_t pause_time; /* Flow control pause timer */ 487 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 488 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 489 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 490 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 491 }; 492 493 /* 494 * Structure to store private data for VMDQ instance 495 */ 496 struct i40e_vmdq_info { 497 struct i40e_pf *pf; 498 struct i40e_vsi *vsi; 499 }; 500 501 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 502 #define I40E_MAX_FLX_SOURCE_OFF 480 503 #define NONUSE_FLX_PIT_DEST_OFF 63 504 #define NONUSE_FLX_PIT_FSIZE 1 505 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 506 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 507 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 508 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 509 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 510 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 511 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 512 NONUSE_FLX_PIT_DEST_OFF : \ 513 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 514 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 515 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 516 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 517 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 518 #define I40E_FDIR_IPv6_TC_OFFSET 20 519 520 /* A structure used to define the input for GTP flow */ 521 struct i40e_gtp_flow { 522 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 523 uint8_t msg_type; /* Message type. */ 524 uint32_t teid; /* TEID in big endian. */ 525 }; 526 527 /* A structure used to define the input for GTP IPV4 flow */ 528 struct i40e_gtp_ipv4_flow { 529 struct i40e_gtp_flow gtp; 530 struct rte_eth_ipv4_flow ip4; 531 }; 532 533 /* A structure used to define the input for GTP IPV6 flow */ 534 struct i40e_gtp_ipv6_flow { 535 struct i40e_gtp_flow gtp; 536 struct rte_eth_ipv6_flow ip6; 537 }; 538 539 /* A structure used to define the input for ESP IPV4 flow */ 540 struct i40e_esp_ipv4_flow { 541 struct rte_eth_ipv4_flow ipv4; 542 uint32_t spi; /* SPI in big endian. */ 543 }; 544 545 /* A structure used to define the input for ESP IPV6 flow */ 546 struct i40e_esp_ipv6_flow { 547 struct rte_eth_ipv6_flow ipv6; 548 uint32_t spi; /* SPI in big endian. */ 549 }; 550 /* A structure used to define the input for ESP IPV4 UDP flow */ 551 struct i40e_esp_ipv4_udp_flow { 552 struct rte_eth_udpv4_flow udp; 553 uint32_t spi; /* SPI in big endian. */ 554 }; 555 556 /* A structure used to define the input for ESP IPV6 UDP flow */ 557 struct i40e_esp_ipv6_udp_flow { 558 struct rte_eth_udpv6_flow udp; 559 uint32_t spi; /* SPI in big endian. */ 560 }; 561 562 /* A structure used to define the input for raw type flow */ 563 struct i40e_raw_flow { 564 uint16_t pctype; 565 void *packet; 566 uint32_t length; 567 }; 568 569 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 570 struct i40e_ipv4_l2tpv3oip_flow { 571 struct rte_eth_ipv4_flow ip4; 572 uint32_t session_id; /* Session ID in big endian. */ 573 }; 574 575 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 576 struct i40e_ipv6_l2tpv3oip_flow { 577 struct rte_eth_ipv6_flow ip6; 578 uint32_t session_id; /* Session ID in big endian. */ 579 }; 580 581 /* A structure used to define the input for l2 dst type flow */ 582 struct i40e_l2_flow { 583 struct rte_ether_addr dst; 584 struct rte_ether_addr src; 585 uint16_t ether_type; /**< Ether type in big endian */ 586 }; 587 588 /* 589 * A union contains the inputs for all types of flow 590 * items in flows need to be in big endian 591 */ 592 union i40e_fdir_flow { 593 struct i40e_l2_flow l2_flow; 594 struct rte_eth_udpv4_flow udp4_flow; 595 struct rte_eth_tcpv4_flow tcp4_flow; 596 struct rte_eth_sctpv4_flow sctp4_flow; 597 struct rte_eth_ipv4_flow ip4_flow; 598 struct rte_eth_udpv6_flow udp6_flow; 599 struct rte_eth_tcpv6_flow tcp6_flow; 600 struct rte_eth_sctpv6_flow sctp6_flow; 601 struct rte_eth_ipv6_flow ipv6_flow; 602 struct i40e_gtp_flow gtp_flow; 603 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 604 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 605 struct i40e_raw_flow raw_flow; 606 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 607 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 608 struct i40e_esp_ipv4_flow esp_ipv4_flow; 609 struct i40e_esp_ipv6_flow esp_ipv6_flow; 610 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 611 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 612 }; 613 614 enum i40e_fdir_ip_type { 615 I40E_FDIR_IPTYPE_IPV4, 616 I40E_FDIR_IPTYPE_IPV6, 617 }; 618 619 /** 620 * Structure to store flex pit for flow diretor. 621 */ 622 struct i40e_fdir_flex_pit { 623 uint8_t src_offset; /* offset in words from the beginning of payload */ 624 uint8_t size; /* size in words */ 625 uint8_t dst_offset; /* offset in words of flexible payload */ 626 }; 627 628 /* A structure used to contain extend input of flow */ 629 struct i40e_fdir_flow_ext { 630 uint16_t vlan_tci; 631 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 632 /* It is filled by the flexible payload to match. */ 633 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN]; 634 uint8_t raw_id; 635 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 636 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 637 uint64_t input_set; 638 bool inner_ip; /* If there is inner ip */ 639 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 640 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 641 bool customized_pctype; /* If customized pctype is used */ 642 bool pkt_template; /* If raw packet template is used */ 643 bool is_udp; /* ipv4|ipv6 udp flow */ 644 enum i40e_flxpld_layer_idx layer_idx; 645 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 646 bool is_flex_flow; 647 }; 648 649 /* A structure used to define the input for a flow director filter entry */ 650 struct i40e_fdir_input { 651 enum i40e_filter_pctype pctype; 652 union i40e_fdir_flow flow; 653 /* Flow fields to match, dependent on flow_type */ 654 struct i40e_fdir_flow_ext flow_ext; 655 /* Additional fields to match */ 656 }; 657 658 /* Behavior will be taken if FDIR match */ 659 enum i40e_fdir_behavior { 660 I40E_FDIR_ACCEPT = 0, 661 I40E_FDIR_REJECT, 662 I40E_FDIR_PASSTHRU, 663 }; 664 665 /* Flow director report status 666 * It defines what will be reported if FDIR entry is matched. 667 */ 668 enum i40e_fdir_status { 669 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 670 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 671 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 672 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 673 }; 674 675 /* A structure used to define an action when match FDIR packet filter. */ 676 struct i40e_fdir_action { 677 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 678 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 679 enum i40e_fdir_status report_status; /* Status report option */ 680 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 681 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 682 * flex bytes start from in flexible payload. 683 */ 684 uint8_t flex_off; 685 }; 686 687 /* A structure used to define the flow director filter entry by filter_ctrl API 688 * It supports RTE_ETH_FILTER_FDIR data representation. 689 */ 690 struct i40e_fdir_filter_conf { 691 uint32_t soft_id; 692 /* ID, an unique value is required when deal with FDIR entry */ 693 struct i40e_fdir_input input; /* Input set */ 694 struct i40e_fdir_action action; /* Action taken when match */ 695 }; 696 697 struct i40e_fdir_flex_mask { 698 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 699 uint8_t nb_bitmask; 700 struct { 701 uint8_t offset; 702 uint16_t mask; 703 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 704 }; 705 706 #define I40E_FILTER_PCTYPE_INVALID 0 707 #define I40E_FILTER_PCTYPE_MAX 64 708 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 709 710 struct i40e_fdir_filter { 711 TAILQ_ENTRY(i40e_fdir_filter) rules; 712 struct i40e_fdir_filter_conf fdir; 713 }; 714 715 /* fdir memory pool entry */ 716 struct i40e_fdir_entry { 717 struct rte_flow flow; 718 uint32_t idx; 719 }; 720 721 /* pre-allocated fdir memory pool */ 722 struct i40e_fdir_flow_pool { 723 /* a bitmap to manage the fdir pool */ 724 struct rte_bitmap *bitmap; 725 /* the size the pool is pf->fdir->fdir_space_size */ 726 struct i40e_fdir_entry *pool; 727 }; 728 729 #define FLOW_TO_FLOW_BITMAP(f) \ 730 container_of((f), struct i40e_fdir_entry, flow) 731 732 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 733 /* 734 * A structure used to define fields of a FDIR related info. 735 */ 736 struct i40e_fdir_info { 737 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 738 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 739 struct i40e_tx_queue *txq; 740 struct i40e_rx_queue *rxq; 741 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 742 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 743 /* 744 * txq available buffer counter, indicates how many available buffers 745 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 746 */ 747 int txq_available_buf_count; 748 749 /* input set bits for each pctype */ 750 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 751 /* 752 * the rule how bytes stream is extracted as flexible payload 753 * for each payload layer, the setting can up to three elements 754 */ 755 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 756 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 757 758 struct i40e_fdir_filter_list fdir_list; 759 struct i40e_fdir_filter **hash_map; 760 struct rte_hash *hash_table; 761 /* An array to store the inserted rules input */ 762 struct i40e_fdir_filter *fdir_filter_array; 763 764 /* 765 * Priority ordering at filter invalidation(destroying a flow) between 766 * "best effort" space and "guaranteed" space. 767 * 768 * 0 = At filter invalidation, the hardware first tries to increment the 769 * "best effort" space. The "guaranteed" space is incremented only when 770 * the global "best effort" space is at it max value or the "best effort" 771 * space of the PF is at its max value. 772 * 1 = At filter invalidation, the hardware first tries to increment its 773 * "guaranteed" space. The "best effort" space is incremented only when 774 * it is already at its max value. 775 */ 776 uint32_t fdir_invalprio; 777 /* the total size of the fdir, this number is the sum of the guaranteed + 778 * shared space 779 */ 780 uint32_t fdir_space_size; 781 /* the actual number of the fdir rules in hardware, initialized as 0 */ 782 uint32_t fdir_actual_cnt; 783 /* the free guaranteed space of the fdir */ 784 uint32_t fdir_guarantee_free_space; 785 /* the fdir total guaranteed space */ 786 uint32_t fdir_guarantee_total_space; 787 /* the pre-allocated pool of the rte_flow */ 788 struct i40e_fdir_flow_pool fdir_flow_pool; 789 790 /* Mark if flex pit and mask is set */ 791 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 792 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 793 794 uint32_t flow_count[I40E_FILTER_PCTYPE_MAX]; 795 796 uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER]; 797 }; 798 799 /* Ethertype filter number HW supports */ 800 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 801 802 /* Ethertype filter struct */ 803 struct i40e_ethertype_filter_input { 804 struct rte_ether_addr mac_addr; /* Mac address to match */ 805 uint16_t ether_type; /* Ether type to match */ 806 }; 807 808 struct i40e_ethertype_filter { 809 TAILQ_ENTRY(i40e_ethertype_filter) rules; 810 struct i40e_ethertype_filter_input input; 811 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 812 uint16_t queue; /* Queue assigned to when match */ 813 }; 814 815 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 816 817 struct i40e_ethertype_rule { 818 struct i40e_ethertype_filter_list ethertype_list; 819 struct i40e_ethertype_filter **hash_map; 820 struct rte_hash *hash_table; 821 }; 822 823 /* queue region info */ 824 struct i40e_queue_region_info { 825 /* the region id for this configuration */ 826 uint8_t region_id; 827 /* the start queue index for this region */ 828 uint8_t queue_start_index; 829 /* the total queue number of this queue region */ 830 uint8_t queue_num; 831 /* the total number of user priority for this region */ 832 uint8_t user_priority_num; 833 /* the packet's user priority for this region */ 834 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 835 /* the total number of flowtype for this region */ 836 uint8_t flowtype_num; 837 /** 838 * the pctype or hardware flowtype of packet, 839 * the specific index for each type has been defined 840 * in file i40e_type.h as enum i40e_filter_pctype. 841 */ 842 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 843 }; 844 845 struct i40e_queue_regions { 846 /* the total number of queue region for this port */ 847 uint16_t queue_region_number; 848 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 849 }; 850 851 struct i40e_rss_pattern_info { 852 uint8_t action_flag; 853 uint64_t types; 854 }; 855 856 /* Tunnel filter number HW supports */ 857 #define I40E_MAX_TUNNEL_FILTER_NUM 400 858 859 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 860 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 861 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 862 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 863 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 864 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 865 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 866 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 867 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 868 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 869 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 870 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 871 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 872 #define I40E_AQC_NEW_TR_21 21 873 #define I40E_AQC_NEW_TR_22 22 874 875 enum i40e_tunnel_iptype { 876 I40E_TUNNEL_IPTYPE_IPV4, 877 I40E_TUNNEL_IPTYPE_IPV6, 878 }; 879 880 /* Tunnel filter struct */ 881 struct i40e_tunnel_filter_input { 882 uint8_t outer_mac[6]; /* Outer mac address to match */ 883 uint8_t inner_mac[6]; /* Inner mac address to match */ 884 uint16_t inner_vlan; /* Inner vlan address to match */ 885 enum i40e_tunnel_iptype ip_type; 886 uint16_t flags; /* Filter type flag */ 887 uint32_t tenant_id; /* Tenant id to match */ 888 uint16_t general_fields[32]; /* Big buffer */ 889 }; 890 891 struct i40e_tunnel_filter { 892 TAILQ_ENTRY(i40e_tunnel_filter) rules; 893 struct i40e_tunnel_filter_input input; 894 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 895 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 896 uint16_t queue; /* Queue assigned to when match */ 897 }; 898 899 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 900 901 struct i40e_tunnel_rule { 902 struct i40e_tunnel_filter_list tunnel_list; 903 struct i40e_tunnel_filter **hash_map; 904 struct rte_hash *hash_table; 905 }; 906 907 /** 908 * Tunnel type. 909 */ 910 enum i40e_tunnel_type { 911 I40E_TUNNEL_TYPE_NONE = 0, 912 I40E_TUNNEL_TYPE_VXLAN, 913 I40E_TUNNEL_TYPE_GENEVE, 914 I40E_TUNNEL_TYPE_TEREDO, 915 I40E_TUNNEL_TYPE_NVGRE, 916 I40E_TUNNEL_TYPE_IP_IN_GRE, 917 I40E_L2_TUNNEL_TYPE_E_TAG, 918 I40E_TUNNEL_TYPE_MPLSoUDP, 919 I40E_TUNNEL_TYPE_MPLSoGRE, 920 I40E_TUNNEL_TYPE_QINQ, 921 I40E_TUNNEL_TYPE_GTPC, 922 I40E_TUNNEL_TYPE_GTPU, 923 I40E_TUNNEL_TYPE_ESPoUDP, 924 I40E_TUNNEL_TYPE_ESPoIP, 925 I40E_CLOUD_TYPE_UDP, 926 I40E_CLOUD_TYPE_TCP, 927 I40E_CLOUD_TYPE_SCTP, 928 I40E_TUNNEL_TYPE_MAX, 929 }; 930 931 /** 932 * L4 port type. 933 */ 934 enum i40e_l4_port_type { 935 I40E_L4_PORT_TYPE_SRC = 0, 936 I40E_L4_PORT_TYPE_DST, 937 }; 938 939 /** 940 * Tunneling Packet filter configuration. 941 */ 942 struct i40e_tunnel_filter_conf { 943 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 944 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 945 uint16_t inner_vlan; /**< Inner VLAN to match. */ 946 uint32_t outer_vlan; /**< Outer VLAN to match */ 947 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 948 /** 949 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 950 * is set in filter_type, or inner destination IP address to match 951 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 952 */ 953 union { 954 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 955 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 956 } ip_addr; 957 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 958 uint16_t filter_type; 959 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 960 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 961 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 962 uint16_t queue_id; /**< Queue assigned to if match. */ 963 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 964 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 965 }; 966 967 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 968 #define I40E_MAX_MIRROR_RULES 64 969 /* 970 * Mirror rule structure 971 */ 972 struct i40e_mirror_rule { 973 TAILQ_ENTRY(i40e_mirror_rule) rules; 974 uint8_t rule_type; 975 uint16_t index; /* the sw index of mirror rule */ 976 uint16_t id; /* the rule id assigned by firmware */ 977 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 978 uint16_t num_entries; 979 /* the info stores depend on the rule type. 980 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 981 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 982 */ 983 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 984 }; 985 986 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 987 988 TAILQ_HEAD(i40e_flow_list, rte_flow); 989 990 /* Struct to store Traffic Manager shaper profile. */ 991 struct i40e_tm_shaper_profile { 992 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 993 uint32_t shaper_profile_id; 994 uint32_t reference_count; 995 struct rte_tm_shaper_params profile; 996 }; 997 998 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 999 1000 /* node type of Traffic Manager */ 1001 enum i40e_tm_node_type { 1002 I40E_TM_NODE_TYPE_PORT, 1003 I40E_TM_NODE_TYPE_TC, 1004 I40E_TM_NODE_TYPE_QUEUE, 1005 I40E_TM_NODE_TYPE_MAX, 1006 }; 1007 1008 /* Struct to store Traffic Manager node configuration. */ 1009 struct i40e_tm_node { 1010 TAILQ_ENTRY(i40e_tm_node) node; 1011 uint32_t id; 1012 uint32_t priority; 1013 uint32_t weight; 1014 uint32_t reference_count; 1015 struct i40e_tm_node *parent; 1016 struct i40e_tm_shaper_profile *shaper_profile; 1017 struct rte_tm_node_params params; 1018 }; 1019 1020 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 1021 1022 /* Struct to store all the Traffic Manager configuration. */ 1023 struct i40e_tm_conf { 1024 struct i40e_shaper_profile_list shaper_profile_list; 1025 struct i40e_tm_node *root; /* root node - port */ 1026 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 1027 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 1028 /** 1029 * The number of added TC nodes. 1030 * It should be no more than the TC number of this port. 1031 */ 1032 uint32_t nb_tc_node; 1033 /** 1034 * The number of added queue nodes. 1035 * It should be no more than the queue number of this port. 1036 */ 1037 uint32_t nb_queue_node; 1038 /** 1039 * This flag is used to check if APP can change the TM node 1040 * configuration. 1041 * When it's true, means the configuration is applied to HW, 1042 * APP should not change the configuration. 1043 * As we don't support on-the-fly configuration, when starting 1044 * the port, APP should call the hierarchy_commit API to set this 1045 * flag to true. When stopping the port, this flag should be set 1046 * to false. 1047 */ 1048 bool committed; 1049 }; 1050 1051 enum i40e_new_pctype { 1052 I40E_CUSTOMIZED_GTPC = 0, 1053 I40E_CUSTOMIZED_GTPU_IPV4, 1054 I40E_CUSTOMIZED_GTPU_IPV6, 1055 I40E_CUSTOMIZED_GTPU, 1056 I40E_CUSTOMIZED_IPV4_L2TPV3, 1057 I40E_CUSTOMIZED_IPV6_L2TPV3, 1058 I40E_CUSTOMIZED_ESP_IPV4, 1059 I40E_CUSTOMIZED_ESP_IPV6, 1060 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1061 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1062 I40E_CUSTOMIZED_AH_IPV4, 1063 I40E_CUSTOMIZED_AH_IPV6, 1064 I40E_CUSTOMIZED_MAX, 1065 }; 1066 1067 #define I40E_FILTER_PCTYPE_INVALID 0 1068 struct i40e_customized_pctype { 1069 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1070 uint8_t pctype; /* New pctype value */ 1071 bool valid; /* Check if it's valid */ 1072 }; 1073 1074 struct i40e_rte_flow_rss_conf { 1075 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1076 1077 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1078 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1079 sizeof(uint32_t)]; /**< Hash key. */ 1080 uint16_t queue[ETH_RSS_RETA_SIZE_512]; /**< Queues indices to use. */ 1081 1082 bool symmetric_enable; /**< true, if enable symmetric */ 1083 uint64_t config_pctypes; /**< All PCTYPES with the flow */ 1084 uint64_t inset; /**< input sets */ 1085 1086 uint8_t region_priority; /**< queue region priority */ 1087 uint8_t region_queue_num; /**< region queue number */ 1088 uint16_t region_queue_start; /**< region queue start */ 1089 1090 uint32_t misc_reset_flags; 1091 #define I40E_HASH_FLOW_RESET_FLAG_FUNC 0x01UL 1092 #define I40E_HASH_FLOW_RESET_FLAG_KEY 0x02UL 1093 #define I40E_HASH_FLOW_RESET_FLAG_QUEUE 0x04UL 1094 #define I40E_HASH_FLOW_RESET_FLAG_REGION 0x08UL 1095 1096 /**< All PCTYPES that reset with the flow */ 1097 uint64_t reset_config_pctypes; 1098 /**< Symmetric function should reset on PCTYPES */ 1099 uint64_t reset_symmetric_pctypes; 1100 }; 1101 1102 /* RSS filter list structure */ 1103 struct i40e_rss_filter { 1104 TAILQ_ENTRY(i40e_rss_filter) next; 1105 struct i40e_rte_flow_rss_conf rss_filter_info; 1106 }; 1107 1108 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1109 1110 struct i40e_vf_msg_cfg { 1111 /* maximal VF message during a statistic period */ 1112 uint32_t max_msg; 1113 1114 /* statistic period, in second */ 1115 uint32_t period; 1116 /* 1117 * If message statistics from a VF exceed the maximal limitation, 1118 * the PF will ignore any new message from that VF for 1119 * 'ignor_second' time. 1120 */ 1121 uint32_t ignore_second; 1122 }; 1123 1124 /* 1125 * Structure to store private data specific for PF instance. 1126 */ 1127 struct i40e_pf { 1128 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1129 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1130 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1131 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1132 uint16_t max_num_vsi; 1133 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1134 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1135 1136 struct i40e_hw_port_stats stats_offset; 1137 struct i40e_hw_port_stats stats; 1138 /* internal packet statistics, it should be excluded from the total */ 1139 struct i40e_eth_stats internal_stats_offset; 1140 struct i40e_eth_stats internal_stats; 1141 bool offset_loaded; 1142 1143 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1144 struct rte_ether_addr dev_addr; /* PF device mac address */ 1145 uint64_t flags; /* PF feature flags */ 1146 /* All kinds of queue pair setting for different VSIs */ 1147 struct i40e_pf_vf *vfs; 1148 uint16_t vf_num; 1149 /* Each of below queue pairs should be power of 2 since it's the 1150 precondition after TC configuration applied */ 1151 uint16_t lan_nb_qp_max; 1152 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1153 uint16_t lan_qp_offset; 1154 uint16_t vmdq_nb_qp_max; 1155 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1156 uint16_t vmdq_qp_offset; 1157 uint16_t vf_nb_qp_max; 1158 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1159 uint16_t vf_qp_offset; 1160 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1161 uint16_t fdir_qp_offset; 1162 1163 uint16_t hash_lut_size; /* The size of hash lookup table */ 1164 bool hash_filter_enabled; 1165 uint64_t hash_enabled_queues; 1166 /* input set bits for each pctype */ 1167 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1168 /* store VXLAN UDP ports */ 1169 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1170 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1171 1172 /* VMDQ related info */ 1173 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1174 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1175 struct i40e_vmdq_info *vmdq; 1176 1177 struct i40e_fdir_info fdir; /* flow director info */ 1178 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1179 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1180 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1181 struct i40e_queue_regions queue_region; /* queue region info */ 1182 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1183 struct i40e_mirror_rule_list mirror_list; 1184 uint16_t nb_mirror_rule; /* The number of mirror rules */ 1185 bool floating_veb; /* The flag to use the floating VEB */ 1186 /* The floating enable flag for the specific VF */ 1187 bool floating_veb_list[I40E_MAX_VF]; 1188 struct i40e_flow_list flow_list; 1189 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1190 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1191 bool qinq_replace_flag; /* QINQ filter replace is done */ 1192 /* l4 port flag */ 1193 bool sport_replace_flag; /* Source port replace is done */ 1194 bool dport_replace_flag; /* Destination port replace is done */ 1195 struct i40e_tm_conf tm_conf; 1196 bool support_multi_driver; /* 1 - support multiple driver */ 1197 1198 /* Dynamic Device Personalization */ 1199 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1200 bool esp_support; /* 1 - support ESP SPI */ 1201 /* customer customized pctype */ 1202 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1203 /* Switch Domain Id */ 1204 uint16_t switch_domain_id; 1205 1206 struct i40e_vf_msg_cfg vf_msg_cfg; 1207 uint64_t prev_rx_bytes; 1208 uint64_t prev_tx_bytes; 1209 uint64_t internal_prev_rx_bytes; 1210 uint64_t internal_prev_tx_bytes; 1211 }; 1212 1213 enum pending_msg { 1214 PFMSG_LINK_CHANGE = 0x1, 1215 PFMSG_RESET_IMPENDING = 0x2, 1216 PFMSG_DRIVER_CLOSE = 0x4, 1217 }; 1218 1219 struct i40e_vsi_vlan_pvid_info { 1220 uint16_t on; /* Enable or disable pvid */ 1221 union { 1222 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1223 struct { 1224 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1225 * while 'untagged' will reject untagged packets. 1226 */ 1227 uint8_t tagged; 1228 uint8_t untagged; 1229 } reject; 1230 } config; 1231 }; 1232 1233 struct i40e_vf_rx_queues { 1234 uint64_t rx_dma_addr; 1235 uint32_t rx_ring_len; 1236 uint32_t buff_size; 1237 }; 1238 1239 struct i40e_vf_tx_queues { 1240 uint64_t tx_dma_addr; 1241 uint32_t tx_ring_len; 1242 }; 1243 1244 /* 1245 * Structure to store private data specific for VF instance. 1246 */ 1247 struct i40e_vf { 1248 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 1249 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1250 uint16_t num_queue_pairs; 1251 uint16_t max_pkt_len; /* Maximum packet length */ 1252 bool promisc_unicast_enabled; 1253 bool promisc_multicast_enabled; 1254 1255 rte_spinlock_t cmd_send_lock; 1256 uint32_t version_major; /* Major version number */ 1257 uint32_t version_minor; /* Minor version number */ 1258 uint16_t promisc_flags; /* Promiscuous setting */ 1259 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1260 1261 /* Multicast addrs */ 1262 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; 1263 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1264 1265 /* Event from pf */ 1266 bool dev_closed; 1267 bool link_up; 1268 enum virtchnl_link_speed link_speed; 1269 bool vf_reset; 1270 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1271 int32_t cmd_retval; /* return value of the cmd response from PF */ 1272 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1273 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1274 1275 /* VSI info */ 1276 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1277 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1278 struct i40e_vsi vsi; 1279 uint64_t flags; 1280 }; 1281 1282 #define I40E_MAX_PKT_TYPE 256 1283 #define I40E_FLOW_TYPE_MAX 64 1284 1285 /* 1286 * Structure to store private data for each PF/VF instance. 1287 */ 1288 struct i40e_adapter { 1289 /* Common for both PF and VF */ 1290 struct i40e_hw hw; 1291 1292 /* Specific for PF or VF */ 1293 union { 1294 struct i40e_pf pf; 1295 struct i40e_vf vf; 1296 }; 1297 1298 /* For vector PMD */ 1299 bool rx_bulk_alloc_allowed; 1300 bool rx_vec_allowed; 1301 bool tx_simple_allowed; 1302 bool tx_vec_allowed; 1303 1304 /* For PTP */ 1305 struct rte_timecounter systime_tc; 1306 struct rte_timecounter rx_tstamp_tc; 1307 struct rte_timecounter tx_tstamp_tc; 1308 1309 /* ptype mapping table */ 1310 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1311 /* flow type to pctype mapping table */ 1312 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1313 uint64_t flow_types_mask; 1314 uint64_t pctypes_mask; 1315 1316 /* For RSS reta table update */ 1317 uint8_t rss_reta_updated; 1318 #ifdef RTE_ARCH_X86 1319 bool rx_use_avx2; 1320 bool rx_use_avx512; 1321 bool tx_use_avx2; 1322 bool tx_use_avx512; 1323 #endif 1324 }; 1325 1326 /** 1327 * Strucute to store private data for each VF representor instance 1328 */ 1329 struct i40e_vf_representor { 1330 uint16_t switch_domain_id; 1331 /**< Virtual Function ID */ 1332 uint16_t vf_id; 1333 /**< Virtual Function ID */ 1334 struct i40e_adapter *adapter; 1335 /**< Private data store of assocaiated physical function */ 1336 struct i40e_eth_stats stats_offset; 1337 /**< Zero-point of VF statistics*/ 1338 }; 1339 1340 extern const struct rte_flow_ops i40e_flow_ops; 1341 1342 union i40e_filter_t { 1343 struct rte_eth_ethertype_filter ethertype_filter; 1344 struct i40e_fdir_filter_conf fdir_filter; 1345 struct rte_eth_tunnel_filter_conf tunnel_filter; 1346 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1347 struct i40e_rte_flow_rss_conf rss_conf; 1348 }; 1349 1350 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1351 const struct rte_flow_attr *attr, 1352 const struct rte_flow_item pattern[], 1353 const struct rte_flow_action actions[], 1354 struct rte_flow_error *error, 1355 union i40e_filter_t *filter); 1356 struct i40e_valid_pattern { 1357 enum rte_flow_item_type *items; 1358 parse_filter_t parse_filter; 1359 }; 1360 1361 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1362 int i40e_vsi_release(struct i40e_vsi *vsi); 1363 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1364 enum i40e_vsi_type type, 1365 struct i40e_vsi *uplink_vsi, 1366 uint16_t user_param); 1367 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1368 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1369 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1370 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1371 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1372 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1373 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1374 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1375 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1376 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1377 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1378 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1379 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1380 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1381 struct i40e_vsi_vlan_pvid_info *info); 1382 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1383 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1384 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1385 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1386 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1387 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1388 int i40e_fdir_setup(struct i40e_pf *pf); 1389 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1390 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1391 uint32_t len, 1392 int socket_id); 1393 int i40e_fdir_configure(struct rte_eth_dev *dev); 1394 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1395 void i40e_fdir_teardown(struct i40e_pf *pf); 1396 enum i40e_filter_pctype 1397 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1398 uint16_t flow_type); 1399 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1400 enum i40e_filter_pctype pctype); 1401 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1402 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1403 struct rte_eth_fdir_info *fdir); 1404 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1405 struct rte_eth_fdir_stats *stat); 1406 int i40e_select_filter_input_set(struct i40e_hw *hw, 1407 struct rte_eth_input_set_conf *conf, 1408 enum rte_filter_type filter); 1409 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1410 int i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set, 1411 uint32_t pctype, bool add); 1412 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1413 uint32_t retval, uint8_t *msg, 1414 uint16_t msglen); 1415 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1416 struct rte_eth_rxq_info *qinfo); 1417 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1418 struct rte_eth_txq_info *qinfo); 1419 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1420 struct rte_eth_burst_mode *mode); 1421 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1422 struct rte_eth_burst_mode *mode); 1423 struct i40e_ethertype_filter * 1424 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1425 const struct i40e_ethertype_filter_input *input); 1426 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1427 struct i40e_ethertype_filter_input *input); 1428 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1429 struct i40e_fdir_input *input); 1430 struct i40e_tunnel_filter * 1431 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1432 const struct i40e_tunnel_filter_input *input); 1433 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1434 struct i40e_tunnel_filter_input *input); 1435 uint64_t i40e_get_default_input_set(uint16_t pctype); 1436 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1437 struct rte_eth_ethertype_filter *filter, 1438 bool add); 1439 struct rte_flow * 1440 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1441 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1442 struct rte_flow *flow); 1443 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1444 const struct i40e_fdir_filter_conf *filter, 1445 bool add); 1446 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1447 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1448 uint8_t add); 1449 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1450 struct i40e_tunnel_filter_conf *tunnel_filter, 1451 uint8_t add); 1452 int i40e_fdir_flush(struct rte_eth_dev *dev); 1453 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1454 struct i40e_macvlan_filter *mv_f, 1455 int num, struct rte_ether_addr *addr); 1456 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1457 struct i40e_macvlan_filter *filter, 1458 int total); 1459 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1460 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1461 struct i40e_macvlan_filter *filter, 1462 int total); 1463 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1464 bool is_i40e_supported(struct rte_eth_dev *dev); 1465 bool is_i40evf_supported(struct rte_eth_dev *dev); 1466 void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, 1467 uint8_t enable); 1468 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1469 enum rte_filter_type filter, uint64_t inset); 1470 int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset, 1471 uint32_t *mask, uint8_t nb_elem); 1472 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1473 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1474 void i40e_check_write_global_reg(struct i40e_hw *hw, 1475 uint32_t addr, uint32_t val); 1476 1477 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1478 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1479 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1480 struct i40e_customized_pctype* 1481 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1482 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1483 uint32_t pkg_size, 1484 enum rte_pmd_i40e_package_op op); 1485 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1486 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1487 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1488 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1489 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1490 void i40e_pf_disable_rss(struct i40e_pf *pf); 1491 int i40e_pf_calc_configured_queues_num(struct i40e_pf *pf); 1492 int i40e_pf_reset_rss_reta(struct i40e_pf *pf); 1493 int i40e_pf_reset_rss_key(struct i40e_pf *pf); 1494 int i40e_pf_config_rss(struct i40e_pf *pf); 1495 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1496 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1497 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1498 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1499 1500 #define I40E_DEV_TO_PCI(eth_dev) \ 1501 RTE_DEV_TO_PCI((eth_dev)->device) 1502 1503 /* I40E_DEV_PRIVATE_TO */ 1504 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1505 (&((struct i40e_adapter *)adapter)->pf) 1506 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1507 (&((struct i40e_adapter *)adapter)->hw) 1508 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1509 ((struct i40e_adapter *)adapter) 1510 1511 /* I40EVF_DEV_PRIVATE_TO */ 1512 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1513 (&((struct i40e_adapter *)adapter)->vf) 1514 1515 static inline struct i40e_vsi * 1516 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1517 { 1518 struct i40e_hw *hw; 1519 1520 if (!adapter) 1521 return NULL; 1522 1523 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1524 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1525 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1526 return &vf->vsi; 1527 } else { 1528 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1529 return pf->main_vsi; 1530 } 1531 } 1532 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1533 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1534 1535 /* I40E_VSI_TO */ 1536 #define I40E_VSI_TO_HW(vsi) \ 1537 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1538 #define I40E_VSI_TO_PF(vsi) \ 1539 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1540 #define I40E_VSI_TO_VF(vsi) \ 1541 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1542 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1543 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1544 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1545 (&rte_eth_devices[((struct i40e_vsi *)vsi)->adapter->pf.dev_data->port_id]) 1546 1547 /* I40E_PF_TO */ 1548 #define I40E_PF_TO_HW(pf) \ 1549 (&(((struct i40e_pf *)pf)->adapter->hw)) 1550 #define I40E_PF_TO_ADAPTER(pf) \ 1551 ((struct i40e_adapter *)pf->adapter) 1552 1553 /* I40E_VF_TO */ 1554 #define I40E_VF_TO_HW(vf) \ 1555 (&(((struct i40e_vf *)vf)->adapter->hw)) 1556 1557 static inline void 1558 i40e_init_adminq_parameter(struct i40e_hw *hw) 1559 { 1560 hw->aq.num_arq_entries = I40E_AQ_LEN; 1561 hw->aq.num_asq_entries = I40E_AQ_LEN; 1562 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1563 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1564 } 1565 1566 static inline int 1567 i40e_align_floor(int n) 1568 { 1569 if (n == 0) 1570 return 0; 1571 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1572 } 1573 1574 static inline uint16_t 1575 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1576 { 1577 uint16_t interval = 0; 1578 1579 if (is_multi_drv) { 1580 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1581 } else { 1582 if (is_pf) 1583 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1584 else 1585 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1586 } 1587 1588 /* Convert to hardware count, as writing each 1 represents 2 us */ 1589 return interval / 2; 1590 } 1591 1592 #define I40E_VALID_FLOW(flow_type) \ 1593 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1594 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1595 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1596 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1597 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1598 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1599 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1600 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1601 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1602 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1603 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1604 1605 #define I40E_VALID_PCTYPE_X722(pctype) \ 1606 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1607 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1608 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1609 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1610 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1611 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1612 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1613 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1614 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1615 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1616 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1617 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1618 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1619 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1620 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1621 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1622 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1623 1624 #define I40E_VALID_PCTYPE(pctype) \ 1625 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1626 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1627 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1628 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1629 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1630 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1631 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1632 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1633 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1634 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1635 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1636 1637 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1638 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1639 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1640 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1641 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1642 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1643 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1644 1645 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1646 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1647 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1648 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1649 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1650 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1651 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1652 1653 #endif /* _I40E_ETHDEV_H_ */ 1654