1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 #include <sys/queue.h> 10 11 #include <rte_time.h> 12 #include <rte_kvargs.h> 13 #include <rte_hash.h> 14 #include <rte_flow.h> 15 #include <rte_flow_driver.h> 16 #include <rte_tm_driver.h> 17 #include "rte_pmd_i40e.h" 18 19 #include "base/i40e_register.h" 20 #include "base/i40e_type.h" 21 #include "base/virtchnl.h" 22 23 /** 24 * _i=0...143, 25 * counters 0-127 are for the 128 VFs, 26 * counters 128-143 are for the 16 PFs 27 */ 28 #define I40E_GL_RXERR1_H(_i) (0x00318004 + ((_i) * 8)) 29 30 #define I40E_AQ_LEN 32 31 #define I40E_AQ_BUF_SZ 4096 32 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 33 #define I40E_MAX_Q_PER_TC 64 34 #define I40E_NUM_DESC_DEFAULT 512 35 #define I40E_NUM_DESC_ALIGN 32 36 #define I40E_BUF_SIZE_MIN 1024 37 #define I40E_FRAME_SIZE_MAX 9728 38 #define I40E_TSO_FRAME_SIZE_MAX 262144 39 #define I40E_QUEUE_BASE_ADDR_UNIT 128 40 /* number of VSIs and queue default setting */ 41 #define I40E_MAX_QP_NUM_PER_VF 16 42 #define I40E_DEFAULT_QP_NUM_FDIR 1 43 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 44 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 45 /* Maximun number of MAC addresses */ 46 #define I40E_NUM_MACADDR_MAX 64 47 /* Maximum number of VFs */ 48 #define I40E_MAX_VF 128 49 /*flag of no loopback*/ 50 #define I40E_AQ_LB_MODE_NONE 0x0 51 /* 52 * vlan_id is a 12 bit number. 53 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 54 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 55 * The higher 7 bit val specifies VFTA array index. 56 */ 57 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 58 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 59 60 /* Default TC traffic in case DCB is not enabled */ 61 #define I40E_DEFAULT_TCMAP 0x1 62 #define I40E_FDIR_QUEUE_ID 0 63 64 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 65 #define I40E_VMDQ_POOL_BASE 1 66 67 #define I40E_DEFAULT_RX_FREE_THRESH 32 68 #define I40E_DEFAULT_RX_PTHRESH 8 69 #define I40E_DEFAULT_RX_HTHRESH 8 70 #define I40E_DEFAULT_RX_WTHRESH 0 71 72 #define I40E_DEFAULT_TX_FREE_THRESH 32 73 #define I40E_DEFAULT_TX_PTHRESH 32 74 #define I40E_DEFAULT_TX_HTHRESH 0 75 #define I40E_DEFAULT_TX_WTHRESH 0 76 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 77 78 /* Bit shift and mask */ 79 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 80 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 81 #define I40E_8_BIT_WIDTH CHAR_BIT 82 #define I40E_8_BIT_MASK UINT8_MAX 83 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 84 #define I40E_16_BIT_MASK UINT16_MAX 85 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 86 #define I40E_32_BIT_MASK UINT32_MAX 87 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 88 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 89 90 /* Linux PF host with virtchnl version 1.1 */ 91 #define PF_IS_V11(vf) \ 92 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 93 ((vf)->version_minor == 1)) 94 95 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 96 do { \ 97 uint32_t ori_val; \ 98 struct rte_eth_dev *dev; \ 99 struct rte_eth_dev_data *dev_data; \ 100 ori_val = I40E_READ_REG((hw), (reg)); \ 101 dev_data = ((struct i40e_adapter *)hw->back)->pf.dev_data; \ 102 dev = &rte_eth_devices[dev_data->port_id]; \ 103 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 104 (reg)), (value)); \ 105 if (ori_val != value) \ 106 PMD_DRV_LOG(WARNING, \ 107 "i40e device %s changed global " \ 108 "register [0x%08x]. original: 0x%08x, " \ 109 "new: 0x%08x ", \ 110 (dev->device->name), (reg), \ 111 (ori_val), (value)); \ 112 } while (0) 113 114 /* index flex payload per layer */ 115 enum i40e_flxpld_layer_idx { 116 I40E_FLXPLD_L2_IDX = 0, 117 I40E_FLXPLD_L3_IDX = 1, 118 I40E_FLXPLD_L4_IDX = 2, 119 I40E_MAX_FLXPLD_LAYER = 3, 120 }; 121 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 122 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 123 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 124 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 125 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 126 127 /* i40e flags */ 128 #define I40E_FLAG_RSS (1ULL << 0) 129 #define I40E_FLAG_DCB (1ULL << 1) 130 #define I40E_FLAG_VMDQ (1ULL << 2) 131 #define I40E_FLAG_SRIOV (1ULL << 3) 132 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 133 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 134 #define I40E_FLAG_FDIR (1ULL << 6) 135 #define I40E_FLAG_VXLAN (1ULL << 7) 136 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 137 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 138 I40E_FLAG_DCB | \ 139 I40E_FLAG_VMDQ | \ 140 I40E_FLAG_SRIOV | \ 141 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 142 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 143 I40E_FLAG_FDIR | \ 144 I40E_FLAG_VXLAN | \ 145 I40E_FLAG_RSS_AQ_CAPABLE) 146 147 #define I40E_RSS_OFFLOAD_ALL ( \ 148 RTE_ETH_RSS_FRAG_IPV4 | \ 149 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ 150 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 151 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \ 152 RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \ 153 RTE_ETH_RSS_FRAG_IPV6 | \ 154 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 155 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ 156 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \ 157 RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \ 158 RTE_ETH_RSS_L2_PAYLOAD) 159 160 /* All bits of RSS hash enable for X722*/ 161 #define I40E_RSS_HENA_ALL_X722 ( \ 162 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 163 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 166 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 168 I40E_RSS_HENA_ALL) 169 170 /* All bits of RSS hash enable */ 171 #define I40E_RSS_HENA_ALL ( \ 172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 176 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 177 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 178 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 179 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 180 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 181 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 182 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 183 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 184 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 185 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 186 187 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 188 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 189 190 /* Default queue interrupt throttling time in microseconds */ 191 #define I40E_ITR_INDEX_DEFAULT 0 192 #define I40E_ITR_INDEX_NONE 3 193 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 194 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 195 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 196 /* Special FW support this floating VEB feature */ 197 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 198 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 199 200 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 201 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 202 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 203 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 204 205 #define I40E_RSS_TYPE_NONE 0ULL 206 #define I40E_RSS_TYPE_INVALID 1ULL 207 208 #define I40E_INSET_NONE 0x00000000000000000ULL 209 210 /* bit0 ~ bit 7 */ 211 #define I40E_INSET_DMAC 0x0000000000000001ULL 212 #define I40E_INSET_SMAC 0x0000000000000002ULL 213 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 214 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 215 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 216 217 /* bit 8 ~ bit 15 */ 218 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 219 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 220 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 221 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 222 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 223 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 224 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 225 226 /* bit 16 ~ bit 31 */ 227 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 228 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 229 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 230 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 231 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 232 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 233 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 234 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 235 236 /* bit 32 ~ bit 47, tunnel fields */ 237 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 238 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 239 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 240 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 241 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 242 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 243 244 /* bit 48 ~ bit 55 */ 245 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 246 247 /* bit 56 ~ bit 63, Flex Payload */ 248 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 249 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 250 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 251 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 252 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 253 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 254 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 255 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 256 #define I40E_INSET_FLEX_PAYLOAD \ 257 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 258 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 259 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 260 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 261 262 /* The max bandwidth of i40e is 40Gbps. */ 263 #define I40E_QOS_BW_MAX 40000 264 /* The bandwidth should be the multiple of 50Mbps. */ 265 #define I40E_QOS_BW_GRANULARITY 50 266 /* The min bandwidth weight is 1. */ 267 #define I40E_QOS_BW_WEIGHT_MIN 1 268 /* The max bandwidth weight is 127. */ 269 #define I40E_QOS_BW_WEIGHT_MAX 127 270 /* The max queue region index is 7. */ 271 #define I40E_REGION_MAX_INDEX 7 272 273 #define I40E_MAX_PERCENT 100 274 #define I40E_DEFAULT_DCB_APP_NUM 1 275 #define I40E_DEFAULT_DCB_APP_PRIO 3 276 277 #define I40E_FDIR_PRG_PKT_CNT 128 278 279 /* 280 * Struct to store flow created. 281 */ 282 struct rte_flow { 283 TAILQ_ENTRY(rte_flow) node; 284 enum rte_filter_type filter_type; 285 void *rule; 286 }; 287 288 /** 289 * The overhead from MTU to max frame size. 290 * Considering QinQ packet, the VLAN tag needs to be counted twice. 291 */ 292 #define I40E_ETH_OVERHEAD \ 293 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN * 2) 294 #define I40E_ETH_MAX_LEN (RTE_ETHER_MTU + I40E_ETH_OVERHEAD) 295 296 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) 297 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) 298 299 struct i40e_adapter; 300 struct rte_pci_driver; 301 302 /** 303 * MAC filter type 304 */ 305 enum i40e_mac_filter_type { 306 I40E_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */ 307 I40E_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */ 308 I40E_MAC_HASH_MATCH, /**< hash match of MAC addr. */ 309 /** hash match of MAC addr and exact match of VLAN ID. */ 310 I40E_MACVLAN_HASH_MATCH, 311 }; 312 313 /** 314 * MAC filter structure 315 */ 316 struct i40e_mac_filter_info { 317 enum i40e_mac_filter_type filter_type; 318 struct rte_ether_addr mac_addr; 319 }; 320 321 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 322 323 /* MAC filter list structure */ 324 struct i40e_mac_filter { 325 TAILQ_ENTRY(i40e_mac_filter) next; 326 struct i40e_mac_filter_info mac_info; 327 }; 328 329 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 330 331 struct i40e_vsi; 332 333 /* VSI list structure */ 334 struct i40e_vsi_list { 335 TAILQ_ENTRY(i40e_vsi_list) list; 336 struct i40e_vsi *vsi; 337 }; 338 339 struct i40e_rx_queue; 340 struct i40e_tx_queue; 341 342 /* Bandwidth limit information */ 343 struct i40e_bw_info { 344 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 345 uint8_t bw_max; /* Max BW limit if enabled */ 346 347 /* Relative credits within same TC with respect to other VSIs or Comps */ 348 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 349 /* Bandwidth limit per TC */ 350 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 351 /* Max bandwidth limit per TC */ 352 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 353 }; 354 355 /* Structure that defines a VEB */ 356 struct i40e_veb { 357 struct i40e_vsi_list_head head; 358 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 359 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 360 uint16_t seid; /* The seid of VEB itself */ 361 uint16_t uplink_seid; /* The uplink seid of this VEB */ 362 uint16_t stats_idx; 363 struct i40e_eth_stats stats; 364 uint8_t enabled_tc; /* The traffic class enabled */ 365 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 366 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 367 }; 368 369 /* i40e MACVLAN filter structure */ 370 struct i40e_macvlan_filter { 371 struct rte_ether_addr macaddr; 372 enum i40e_mac_filter_type filter_type; 373 uint16_t vlan_id; 374 }; 375 376 /* 377 * Structure that defines a VSI, associated with a adapter. 378 */ 379 struct i40e_vsi { 380 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 381 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 382 383 struct i40e_eth_stats eth_stats_offset; 384 struct i40e_eth_stats eth_stats; 385 /* 386 * When drivers loaded, only a default main VSI exists. In case new VSI 387 * needs to add, HW needs to know the layout that VSIs are organized. 388 * Besides that, VSI isan element and can't switch packets, which needs 389 * to add new component VEB to perform switching. So, a new VSI needs 390 * to specify the uplink VSI (Parent VSI) before created. The 391 * uplink VSI will check whether it had a VEB to switch packets. If no, 392 * it will try to create one. Then, uplink VSI will move the new VSI 393 * into its' sib_vsi_list to manage all the downlink VSI. 394 * sib_vsi_list: the VSI list that shared the same uplink VSI. 395 * parent_vsi : the uplink VSI. It's NULL for main VSI. 396 * veb : the VEB associates with the VSI. 397 */ 398 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 399 struct i40e_vsi *parent_vsi; 400 struct i40e_veb *veb; /* Associated veb, could be null */ 401 struct i40e_veb *floating_veb; /* Associated floating veb */ 402 bool offset_loaded; 403 enum i40e_vsi_type type; /* VSI types */ 404 uint16_t vlan_num; /* Total VLAN number */ 405 uint16_t mac_num; /* Total mac number */ 406 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 407 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 408 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 409 uint32_t user_param; 410 uint16_t seid; /* The seid of VSI itself */ 411 uint16_t uplink_seid; /* The uplink seid of this VSI */ 412 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 413 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 414 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 415 uint16_t base_queue; /* The first queue index of this VSI */ 416 /* 417 * The offset to visit VSI related register, assigned by HW when 418 * creating VSI 419 */ 420 uint16_t vsi_id; 421 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 422 uint16_t nb_msix; /* The max number of msix vector */ 423 uint8_t enabled_tc; /* The traffic class enabled */ 424 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 425 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 426 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 427 uint64_t prev_rx_bytes; 428 uint64_t prev_tx_bytes; 429 }; 430 431 struct pool_entry { 432 LIST_ENTRY(pool_entry) next; 433 uint16_t base; 434 uint16_t len; 435 }; 436 437 LIST_HEAD(res_list, pool_entry); 438 439 struct i40e_res_pool_info { 440 uint32_t base; /* Resource start index */ 441 uint32_t num_alloc; /* Allocated resource number */ 442 uint32_t num_free; /* Total available resource number */ 443 struct res_list alloc_list; /* Allocated resource list */ 444 struct res_list free_list; /* Available resource list */ 445 }; 446 447 enum I40E_VF_STATE { 448 I40E_VF_INACTIVE = 0, 449 I40E_VF_INRESET, 450 I40E_VF_ININIT, 451 I40E_VF_ACTIVE, 452 }; 453 454 /* 455 * Structure to store private data for PF host. 456 */ 457 struct i40e_pf_vf { 458 struct i40e_pf *pf; 459 struct i40e_vsi *vsi; 460 enum I40E_VF_STATE state; /* The number of queue pairs available */ 461 uint16_t vf_idx; /* VF index in pf->vfs */ 462 uint16_t lan_nb_qps; /* Actual queues allocated */ 463 uint16_t reset_cnt; /* Total vf reset times */ 464 struct rte_ether_addr mac_addr; /* Default MAC address */ 465 /* version of the virtchnl from VF */ 466 struct virtchnl_version_info version; 467 uint32_t request_caps; /* offload caps requested from VF */ 468 uint64_t num_mdd_events; /* num of mdd events detected */ 469 470 /* 471 * Variables for store the arrival timestamp of VF messages. 472 * If the timestamp of latest message stored at 473 * `msg_timestamps[index % max]` then the timestamp of 474 * earliest message stored at `msg_time[(index + 1) % max]`. 475 * When a new message come, the timestamp of this message 476 * will be stored at `msg_timestamps[(index + 1) % max]` and the 477 * earliest message timestamp is at 478 * `msg_timestamps[(index + 2) % max]` now... 479 */ 480 uint32_t msg_index; 481 uint64_t *msg_timestamps; 482 483 /* cycle of stop ignoring VF message */ 484 uint64_t ignore_end_cycle; 485 }; 486 487 /* 488 * Structure to store private data for flow control. 489 */ 490 struct i40e_fc_conf { 491 uint16_t pause_time; /* Flow control pause timer */ 492 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 493 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 494 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 495 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 496 }; 497 498 /* 499 * Structure to store private data for VMDQ instance 500 */ 501 struct i40e_vmdq_info { 502 struct i40e_pf *pf; 503 struct i40e_vsi *vsi; 504 }; 505 506 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 507 #define I40E_MAX_FLX_SOURCE_OFF 480 508 #define NONUSE_FLX_PIT_DEST_OFF 63 509 #define NONUSE_FLX_PIT_FSIZE 1 510 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 511 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 512 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 513 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 514 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 515 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 516 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 517 NONUSE_FLX_PIT_DEST_OFF : \ 518 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 519 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 520 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 521 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 522 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 523 #define I40E_FDIR_IPv6_TC_OFFSET 20 524 525 /* A structure used to define the input for GTP flow */ 526 struct i40e_gtp_flow { 527 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 528 uint8_t msg_type; /* Message type. */ 529 uint32_t teid; /* TEID in big endian. */ 530 }; 531 532 /* A structure used to define the input for GTP IPV4 flow */ 533 struct i40e_gtp_ipv4_flow { 534 struct i40e_gtp_flow gtp; 535 struct rte_eth_ipv4_flow ip4; 536 }; 537 538 /* A structure used to define the input for GTP IPV6 flow */ 539 struct i40e_gtp_ipv6_flow { 540 struct i40e_gtp_flow gtp; 541 struct rte_eth_ipv6_flow ip6; 542 }; 543 544 /* A structure used to define the input for ESP IPV4 flow */ 545 struct i40e_esp_ipv4_flow { 546 struct rte_eth_ipv4_flow ipv4; 547 uint32_t spi; /* SPI in big endian. */ 548 }; 549 550 /* A structure used to define the input for ESP IPV6 flow */ 551 struct i40e_esp_ipv6_flow { 552 struct rte_eth_ipv6_flow ipv6; 553 uint32_t spi; /* SPI in big endian. */ 554 }; 555 /* A structure used to define the input for ESP IPV4 UDP flow */ 556 struct i40e_esp_ipv4_udp_flow { 557 struct rte_eth_udpv4_flow udp; 558 uint32_t spi; /* SPI in big endian. */ 559 }; 560 561 /* A structure used to define the input for ESP IPV6 UDP flow */ 562 struct i40e_esp_ipv6_udp_flow { 563 struct rte_eth_udpv6_flow udp; 564 uint32_t spi; /* SPI in big endian. */ 565 }; 566 567 /* A structure used to define the input for raw type flow */ 568 struct i40e_raw_flow { 569 uint16_t pctype; 570 void *packet; 571 uint32_t length; 572 }; 573 574 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 575 struct i40e_ipv4_l2tpv3oip_flow { 576 struct rte_eth_ipv4_flow ip4; 577 uint32_t session_id; /* Session ID in big endian. */ 578 }; 579 580 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 581 struct i40e_ipv6_l2tpv3oip_flow { 582 struct rte_eth_ipv6_flow ip6; 583 uint32_t session_id; /* Session ID in big endian. */ 584 }; 585 586 /* A structure used to define the input for l2 dst type flow */ 587 struct i40e_l2_flow { 588 struct rte_ether_addr dst; 589 struct rte_ether_addr src; 590 uint16_t ether_type; /**< Ether type in big endian */ 591 }; 592 593 /* 594 * A union contains the inputs for all types of flow 595 * items in flows need to be in big endian 596 */ 597 union i40e_fdir_flow { 598 struct i40e_l2_flow l2_flow; 599 struct rte_eth_udpv4_flow udp4_flow; 600 struct rte_eth_tcpv4_flow tcp4_flow; 601 struct rte_eth_sctpv4_flow sctp4_flow; 602 struct rte_eth_ipv4_flow ip4_flow; 603 struct rte_eth_udpv6_flow udp6_flow; 604 struct rte_eth_tcpv6_flow tcp6_flow; 605 struct rte_eth_sctpv6_flow sctp6_flow; 606 struct rte_eth_ipv6_flow ipv6_flow; 607 struct i40e_gtp_flow gtp_flow; 608 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 609 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 610 struct i40e_raw_flow raw_flow; 611 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 612 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 613 struct i40e_esp_ipv4_flow esp_ipv4_flow; 614 struct i40e_esp_ipv6_flow esp_ipv6_flow; 615 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 616 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 617 }; 618 619 enum i40e_fdir_ip_type { 620 I40E_FDIR_IPTYPE_IPV4, 621 I40E_FDIR_IPTYPE_IPV6, 622 }; 623 624 /** 625 * Structure to store flex pit for flow diretor. 626 */ 627 struct i40e_fdir_flex_pit { 628 uint8_t src_offset; /* offset in words from the beginning of payload */ 629 uint8_t size; /* size in words */ 630 uint8_t dst_offset; /* offset in words of flexible payload */ 631 }; 632 633 /* A structure used to contain extend input of flow */ 634 struct i40e_fdir_flow_ext { 635 uint16_t vlan_tci; 636 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 637 /* It is filled by the flexible payload to match. */ 638 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN]; 639 uint8_t raw_id; 640 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 641 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 642 uint64_t input_set; 643 bool inner_ip; /* If there is inner ip */ 644 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 645 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 646 bool customized_pctype; /* If customized pctype is used */ 647 bool pkt_template; /* If raw packet template is used */ 648 bool is_udp; /* ipv4|ipv6 udp flow */ 649 enum i40e_flxpld_layer_idx layer_idx; 650 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 651 bool is_flex_flow; 652 }; 653 654 /* A structure used to define the input for a flow director filter entry */ 655 struct i40e_fdir_input { 656 enum i40e_filter_pctype pctype; 657 union i40e_fdir_flow flow; 658 /* Flow fields to match, dependent on flow_type */ 659 struct i40e_fdir_flow_ext flow_ext; 660 /* Additional fields to match */ 661 }; 662 663 /* Behavior will be taken if FDIR match */ 664 enum i40e_fdir_behavior { 665 I40E_FDIR_ACCEPT = 0, 666 I40E_FDIR_REJECT, 667 I40E_FDIR_PASSTHRU, 668 }; 669 670 /* Flow director report status 671 * It defines what will be reported if FDIR entry is matched. 672 */ 673 enum i40e_fdir_status { 674 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 675 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 676 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 677 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 678 }; 679 680 /* A structure used to define an action when match FDIR packet filter. */ 681 struct i40e_fdir_action { 682 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 683 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 684 enum i40e_fdir_status report_status; /* Status report option */ 685 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 686 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 687 * flex bytes start from in flexible payload. 688 */ 689 uint8_t flex_off; 690 }; 691 692 /* A structure used to define the flow director filter entry by filter_ctrl API 693 * It supports RTE_ETH_FILTER_FDIR data representation. 694 */ 695 struct i40e_fdir_filter_conf { 696 uint32_t soft_id; 697 /* ID, an unique value is required when deal with FDIR entry */ 698 struct i40e_fdir_input input; /* Input set */ 699 struct i40e_fdir_action action; /* Action taken when match */ 700 }; 701 702 struct i40e_fdir_flex_mask { 703 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 704 uint8_t nb_bitmask; 705 struct { 706 uint8_t offset; 707 uint16_t mask; 708 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 709 }; 710 711 #define I40E_FILTER_PCTYPE_INVALID 0 712 #define I40E_FILTER_PCTYPE_MAX 64 713 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 714 715 struct i40e_fdir_filter { 716 TAILQ_ENTRY(i40e_fdir_filter) rules; 717 struct i40e_fdir_filter_conf fdir; 718 }; 719 720 /* fdir memory pool entry */ 721 struct i40e_fdir_entry { 722 struct rte_flow flow; 723 uint32_t idx; 724 }; 725 726 /* pre-allocated fdir memory pool */ 727 struct i40e_fdir_flow_pool { 728 /* a bitmap to manage the fdir pool */ 729 struct rte_bitmap *bitmap; 730 /* the size the pool is pf->fdir->fdir_space_size */ 731 struct i40e_fdir_entry *pool; 732 }; 733 734 #define FLOW_TO_FLOW_BITMAP(f) \ 735 container_of((f), struct i40e_fdir_entry, flow) 736 737 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 738 /* 739 * A structure used to define fields of a FDIR related info. 740 */ 741 struct i40e_fdir_info { 742 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 743 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 744 struct i40e_tx_queue *txq; 745 struct i40e_rx_queue *rxq; 746 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 747 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 748 /* 749 * txq available buffer counter, indicates how many available buffers 750 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 751 */ 752 int txq_available_buf_count; 753 754 /* input set bits for each pctype */ 755 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 756 /* 757 * the rule how bytes stream is extracted as flexible payload 758 * for each payload layer, the setting can up to three elements 759 */ 760 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 761 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 762 763 struct i40e_fdir_filter_list fdir_list; 764 struct i40e_fdir_filter **hash_map; 765 struct rte_hash *hash_table; 766 /* An array to store the inserted rules input */ 767 struct i40e_fdir_filter *fdir_filter_array; 768 769 /* 770 * Priority ordering at filter invalidation(destroying a flow) between 771 * "best effort" space and "guaranteed" space. 772 * 773 * 0 = At filter invalidation, the hardware first tries to increment the 774 * "best effort" space. The "guaranteed" space is incremented only when 775 * the global "best effort" space is at it max value or the "best effort" 776 * space of the PF is at its max value. 777 * 1 = At filter invalidation, the hardware first tries to increment its 778 * "guaranteed" space. The "best effort" space is incremented only when 779 * it is already at its max value. 780 */ 781 uint32_t fdir_invalprio; 782 /* the total size of the fdir, this number is the sum of the guaranteed + 783 * shared space 784 */ 785 uint32_t fdir_space_size; 786 /* the actual number of the fdir rules in hardware, initialized as 0 */ 787 uint32_t fdir_actual_cnt; 788 /* the free guaranteed space of the fdir */ 789 uint32_t fdir_guarantee_free_space; 790 /* the fdir total guaranteed space */ 791 uint32_t fdir_guarantee_total_space; 792 /* the pre-allocated pool of the rte_flow */ 793 struct i40e_fdir_flow_pool fdir_flow_pool; 794 795 /* Mark if flex pit and mask is set */ 796 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 797 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 798 799 uint32_t flow_count[I40E_FILTER_PCTYPE_MAX]; 800 801 uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER]; 802 }; 803 804 /* Ethertype filter number HW supports */ 805 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 806 807 /* Ethertype filter struct */ 808 struct i40e_ethertype_filter_input { 809 struct rte_ether_addr mac_addr; /* Mac address to match */ 810 uint16_t ether_type; /* Ether type to match */ 811 }; 812 813 struct i40e_ethertype_filter { 814 TAILQ_ENTRY(i40e_ethertype_filter) rules; 815 struct i40e_ethertype_filter_input input; 816 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 817 uint16_t queue; /* Queue assigned to when match */ 818 }; 819 820 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 821 822 struct i40e_ethertype_rule { 823 struct i40e_ethertype_filter_list ethertype_list; 824 struct i40e_ethertype_filter **hash_map; 825 struct rte_hash *hash_table; 826 }; 827 828 /* queue region info */ 829 struct i40e_queue_region_info { 830 /* the region id for this configuration */ 831 uint8_t region_id; 832 /* the start queue index for this region */ 833 uint8_t queue_start_index; 834 /* the total queue number of this queue region */ 835 uint8_t queue_num; 836 /* the total number of user priority for this region */ 837 uint8_t user_priority_num; 838 /* the packet's user priority for this region */ 839 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 840 /* the total number of flowtype for this region */ 841 uint8_t flowtype_num; 842 /** 843 * the pctype or hardware flowtype of packet, 844 * the specific index for each type has been defined 845 * in file i40e_type.h as enum i40e_filter_pctype. 846 */ 847 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 848 }; 849 850 struct i40e_queue_regions { 851 /* the total number of queue region for this port */ 852 uint16_t queue_region_number; 853 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 854 }; 855 856 struct i40e_rss_pattern_info { 857 uint8_t action_flag; 858 uint64_t types; 859 }; 860 861 /* Tunnel filter number HW supports */ 862 #define I40E_MAX_TUNNEL_FILTER_NUM 400 863 864 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 865 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 866 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 867 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 868 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 869 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 870 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 871 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 872 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 873 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 874 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 875 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 876 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 877 #define I40E_AQC_NEW_TR_21 21 878 #define I40E_AQC_NEW_TR_22 22 879 880 enum i40e_tunnel_iptype { 881 I40E_TUNNEL_IPTYPE_IPV4, 882 I40E_TUNNEL_IPTYPE_IPV6, 883 }; 884 885 /* Tunnel filter struct */ 886 struct i40e_tunnel_filter_input { 887 uint8_t outer_mac[6]; /* Outer mac address to match */ 888 uint8_t inner_mac[6]; /* Inner mac address to match */ 889 uint16_t inner_vlan; /* Inner vlan address to match */ 890 enum i40e_tunnel_iptype ip_type; 891 uint16_t flags; /* Filter type flag */ 892 uint32_t tenant_id; /* Tenant id to match */ 893 uint16_t general_fields[32]; /* Big buffer */ 894 }; 895 896 struct i40e_tunnel_filter { 897 TAILQ_ENTRY(i40e_tunnel_filter) rules; 898 struct i40e_tunnel_filter_input input; 899 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 900 uint16_t vf_id; /* VF id, available when is_to_vf is 1. */ 901 uint16_t queue; /* Queue assigned to when match */ 902 }; 903 904 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 905 906 struct i40e_tunnel_rule { 907 struct i40e_tunnel_filter_list tunnel_list; 908 struct i40e_tunnel_filter **hash_map; 909 struct rte_hash *hash_table; 910 }; 911 912 /** 913 * Tunnel type. 914 */ 915 enum i40e_tunnel_type { 916 I40E_TUNNEL_TYPE_NONE = 0, 917 I40E_TUNNEL_TYPE_VXLAN, 918 I40E_TUNNEL_TYPE_GENEVE, 919 I40E_TUNNEL_TYPE_TEREDO, 920 I40E_TUNNEL_TYPE_NVGRE, 921 I40E_TUNNEL_TYPE_IP_IN_GRE, 922 I40E_L2_TUNNEL_TYPE_E_TAG, 923 I40E_TUNNEL_TYPE_MPLSoUDP, 924 I40E_TUNNEL_TYPE_MPLSoGRE, 925 I40E_TUNNEL_TYPE_QINQ, 926 I40E_TUNNEL_TYPE_GTPC, 927 I40E_TUNNEL_TYPE_GTPU, 928 I40E_TUNNEL_TYPE_ESPoUDP, 929 I40E_TUNNEL_TYPE_ESPoIP, 930 I40E_CLOUD_TYPE_UDP, 931 I40E_CLOUD_TYPE_TCP, 932 I40E_CLOUD_TYPE_SCTP, 933 I40E_TUNNEL_TYPE_MAX, 934 }; 935 936 /** 937 * L4 port type. 938 */ 939 enum i40e_l4_port_type { 940 I40E_L4_PORT_TYPE_SRC = 0, 941 I40E_L4_PORT_TYPE_DST, 942 }; 943 944 /** 945 * Tunneling Packet filter configuration. 946 */ 947 struct i40e_tunnel_filter_conf { 948 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 949 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 950 uint16_t inner_vlan; /**< Inner VLAN to match. */ 951 uint32_t outer_vlan; /**< Outer VLAN to match */ 952 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 953 /** 954 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 955 * is set in filter_type, or inner destination IP address to match 956 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 957 */ 958 union { 959 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 960 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 961 } ip_addr; 962 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 963 uint16_t filter_type; 964 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 965 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 966 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 967 uint16_t queue_id; /**< Queue assigned to if match. */ 968 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 969 uint16_t vf_id; /**< VF id, available when is_to_vf is 1. */ 970 }; 971 972 TAILQ_HEAD(i40e_flow_list, rte_flow); 973 974 /* Struct to store Traffic Manager shaper profile. */ 975 struct i40e_tm_shaper_profile { 976 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 977 uint32_t shaper_profile_id; 978 uint32_t reference_count; 979 struct rte_tm_shaper_params profile; 980 }; 981 982 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 983 984 /* node type of Traffic Manager */ 985 enum i40e_tm_node_type { 986 I40E_TM_NODE_TYPE_PORT, 987 I40E_TM_NODE_TYPE_TC, 988 I40E_TM_NODE_TYPE_QUEUE, 989 I40E_TM_NODE_TYPE_MAX, 990 }; 991 992 /* Struct to store Traffic Manager node configuration. */ 993 struct i40e_tm_node { 994 TAILQ_ENTRY(i40e_tm_node) node; 995 uint32_t id; 996 uint32_t priority; 997 uint32_t weight; 998 uint32_t reference_count; 999 struct i40e_tm_node *parent; 1000 struct i40e_tm_shaper_profile *shaper_profile; 1001 struct rte_tm_node_params params; 1002 }; 1003 1004 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 1005 1006 /* Struct to store all the Traffic Manager configuration. */ 1007 struct i40e_tm_conf { 1008 struct i40e_shaper_profile_list shaper_profile_list; 1009 struct i40e_tm_node *root; /* root node - port */ 1010 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 1011 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 1012 /** 1013 * The number of added TC nodes. 1014 * It should be no more than the TC number of this port. 1015 */ 1016 uint32_t nb_tc_node; 1017 /** 1018 * The number of added queue nodes. 1019 * It should be no more than the queue number of this port. 1020 */ 1021 uint32_t nb_queue_node; 1022 /** 1023 * This flag is used to check if APP can change the TM node 1024 * configuration. 1025 * When it's true, means the configuration is applied to HW, 1026 * APP should not change the configuration. 1027 * As we don't support on-the-fly configuration, when starting 1028 * the port, APP should call the hierarchy_commit API to set this 1029 * flag to true. When stopping the port, this flag should be set 1030 * to false. 1031 */ 1032 bool committed; 1033 }; 1034 1035 enum i40e_new_pctype { 1036 I40E_CUSTOMIZED_GTPC = 0, 1037 I40E_CUSTOMIZED_GTPU_IPV4, 1038 I40E_CUSTOMIZED_GTPU_IPV6, 1039 I40E_CUSTOMIZED_GTPU, 1040 I40E_CUSTOMIZED_IPV4_L2TPV3, 1041 I40E_CUSTOMIZED_IPV6_L2TPV3, 1042 I40E_CUSTOMIZED_ESP_IPV4, 1043 I40E_CUSTOMIZED_ESP_IPV6, 1044 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1045 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1046 I40E_CUSTOMIZED_AH_IPV4, 1047 I40E_CUSTOMIZED_AH_IPV6, 1048 I40E_CUSTOMIZED_MAX, 1049 }; 1050 1051 #define I40E_FILTER_PCTYPE_INVALID 0 1052 struct i40e_customized_pctype { 1053 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1054 uint8_t pctype; /* New pctype value */ 1055 bool valid; /* Check if it's valid */ 1056 }; 1057 1058 struct i40e_rte_flow_rss_conf { 1059 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1060 1061 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1062 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1063 sizeof(uint32_t)]; /**< Hash key. */ 1064 uint16_t queue[RTE_ETH_RSS_RETA_SIZE_512]; /**< Queues indices to use. */ 1065 1066 bool symmetric_enable; /**< true, if enable symmetric */ 1067 uint64_t config_pctypes; /**< All PCTYPES with the flow */ 1068 uint64_t inset; /**< input sets */ 1069 1070 uint8_t region_priority; /**< queue region priority */ 1071 uint8_t region_queue_num; /**< region queue number */ 1072 uint16_t region_queue_start; /**< region queue start */ 1073 1074 uint32_t misc_reset_flags; 1075 #define I40E_HASH_FLOW_RESET_FLAG_FUNC 0x01UL 1076 #define I40E_HASH_FLOW_RESET_FLAG_KEY 0x02UL 1077 #define I40E_HASH_FLOW_RESET_FLAG_QUEUE 0x04UL 1078 #define I40E_HASH_FLOW_RESET_FLAG_REGION 0x08UL 1079 1080 /**< All PCTYPES that reset with the flow */ 1081 uint64_t reset_config_pctypes; 1082 /**< Symmetric function should reset on PCTYPES */ 1083 uint64_t reset_symmetric_pctypes; 1084 }; 1085 1086 /* RSS filter list structure */ 1087 struct i40e_rss_filter { 1088 TAILQ_ENTRY(i40e_rss_filter) next; 1089 struct i40e_rte_flow_rss_conf rss_filter_info; 1090 }; 1091 1092 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1093 1094 struct i40e_vf_msg_cfg { 1095 /* maximal VF message during a statistic period */ 1096 uint32_t max_msg; 1097 1098 /* statistic period, in second */ 1099 uint32_t period; 1100 /* 1101 * If message statistics from a VF exceed the maximal limitation, 1102 * the PF will ignore any new message from that VF for 1103 * 'ignore_second' time. 1104 */ 1105 uint32_t ignore_second; 1106 }; 1107 1108 /* 1109 * Structure to store private data specific for PF instance. 1110 */ 1111 struct i40e_pf { 1112 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1113 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1114 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1115 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1116 uint16_t max_num_vsi; 1117 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1118 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1119 1120 struct i40e_hw_port_stats stats_offset; 1121 struct i40e_hw_port_stats stats; 1122 u64 rx_err1; /* rxerr1 */ 1123 u64 rx_err1_offset; 1124 1125 /* internal packet statistics, it should be excluded from the total */ 1126 struct i40e_eth_stats internal_stats_offset; 1127 struct i40e_eth_stats internal_stats; 1128 bool offset_loaded; 1129 1130 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1131 struct rte_ether_addr dev_addr; /* PF device mac address */ 1132 uint64_t flags; /* PF feature flags */ 1133 /* All kinds of queue pair setting for different VSIs */ 1134 struct i40e_pf_vf *vfs; 1135 uint16_t vf_num; 1136 /* Each of below queue pairs should be power of 2 since it's the 1137 precondition after TC configuration applied */ 1138 uint16_t lan_nb_qp_max; 1139 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1140 uint16_t lan_qp_offset; 1141 uint16_t vmdq_nb_qp_max; 1142 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1143 uint16_t vmdq_qp_offset; 1144 uint16_t vf_nb_qp_max; 1145 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1146 uint16_t vf_qp_offset; 1147 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1148 uint16_t fdir_qp_offset; 1149 1150 uint16_t hash_lut_size; /* The size of hash lookup table */ 1151 bool hash_filter_enabled; 1152 uint64_t hash_enabled_queues; 1153 /* input set bits for each pctype */ 1154 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1155 /* store VXLAN UDP ports */ 1156 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1157 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1158 1159 /* VMDQ related info */ 1160 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1161 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1162 struct i40e_vmdq_info *vmdq; 1163 1164 struct i40e_fdir_info fdir; /* flow director info */ 1165 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1166 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1167 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1168 struct i40e_queue_regions queue_region; /* queue region info */ 1169 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1170 bool floating_veb; /* The flag to use the floating VEB */ 1171 /* The floating enable flag for the specific VF */ 1172 bool floating_veb_list[I40E_MAX_VF]; 1173 struct i40e_flow_list flow_list; 1174 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1175 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1176 bool qinq_replace_flag; /* QINQ filter replace is done */ 1177 /* l4 port flag */ 1178 bool sport_replace_flag; /* Source port replace is done */ 1179 bool dport_replace_flag; /* Destination port replace is done */ 1180 struct i40e_tm_conf tm_conf; 1181 bool support_multi_driver; /* 1 - support multiple driver */ 1182 1183 /* Dynamic Device Personalization */ 1184 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1185 bool esp_support; /* 1 - support ESP SPI */ 1186 /* customer customized pctype */ 1187 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1188 /* Switch Domain Id */ 1189 uint16_t switch_domain_id; 1190 1191 struct i40e_vf_msg_cfg vf_msg_cfg; 1192 uint64_t prev_rx_bytes; 1193 uint64_t prev_tx_bytes; 1194 uint64_t internal_prev_rx_bytes; 1195 uint64_t internal_prev_tx_bytes; 1196 }; 1197 1198 enum pending_msg { 1199 PFMSG_LINK_CHANGE = 0x1, 1200 PFMSG_RESET_IMPENDING = 0x2, 1201 PFMSG_DRIVER_CLOSE = 0x4, 1202 }; 1203 1204 struct i40e_vsi_vlan_pvid_info { 1205 uint16_t on; /* Enable or disable pvid */ 1206 union { 1207 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1208 struct { 1209 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1210 * while 'untagged' will reject untagged packets. 1211 */ 1212 uint8_t tagged; 1213 uint8_t untagged; 1214 } reject; 1215 } config; 1216 }; 1217 1218 #define I40E_MAX_PKT_TYPE 256 1219 #define I40E_FLOW_TYPE_MAX 64 1220 1221 /* 1222 * Structure to store private data for each PF/VF instance. 1223 */ 1224 struct i40e_adapter { 1225 /* Common for both PF and VF */ 1226 struct i40e_hw hw; 1227 1228 /* Specific for PF */ 1229 struct i40e_pf pf; 1230 1231 /* For vector PMD */ 1232 bool rx_bulk_alloc_allowed; 1233 bool rx_vec_allowed; 1234 bool tx_simple_allowed; 1235 bool tx_vec_allowed; 1236 1237 /* For PTP */ 1238 struct rte_timecounter systime_tc; 1239 struct rte_timecounter rx_tstamp_tc; 1240 struct rte_timecounter tx_tstamp_tc; 1241 1242 /* ptype mapping table */ 1243 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1244 /* flow type to pctype mapping table */ 1245 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1246 uint64_t flow_types_mask; 1247 uint64_t pctypes_mask; 1248 1249 /* For RSS reta table update */ 1250 uint8_t rss_reta_updated; 1251 #ifdef RTE_ARCH_X86 1252 bool rx_use_avx2; 1253 bool rx_use_avx512; 1254 bool tx_use_avx2; 1255 bool tx_use_avx512; 1256 #endif 1257 }; 1258 1259 /** 1260 * Structure to store private data for each VF representor instance 1261 */ 1262 struct i40e_vf_representor { 1263 uint16_t switch_domain_id; 1264 /**< Virtual Function ID */ 1265 uint16_t vf_id; 1266 /**< Virtual Function ID */ 1267 struct i40e_adapter *adapter; 1268 /**< Private data store of associated physical function */ 1269 struct i40e_eth_stats stats_offset; 1270 /**< Zero-point of VF statistics*/ 1271 }; 1272 1273 extern const struct rte_flow_ops i40e_flow_ops; 1274 1275 union i40e_filter_t { 1276 struct rte_eth_ethertype_filter ethertype_filter; 1277 struct i40e_fdir_filter_conf fdir_filter; 1278 struct rte_eth_tunnel_filter_conf tunnel_filter; 1279 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1280 struct i40e_rte_flow_rss_conf rss_conf; 1281 }; 1282 1283 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1284 const struct rte_flow_attr *attr, 1285 const struct rte_flow_item pattern[], 1286 const struct rte_flow_action actions[], 1287 struct rte_flow_error *error, 1288 union i40e_filter_t *filter); 1289 struct i40e_valid_pattern { 1290 enum rte_flow_item_type *items; 1291 parse_filter_t parse_filter; 1292 }; 1293 1294 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1295 int i40e_vsi_release(struct i40e_vsi *vsi); 1296 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1297 enum i40e_vsi_type type, 1298 struct i40e_vsi *uplink_vsi, 1299 uint16_t user_param); 1300 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1301 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1302 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1303 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1304 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1305 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1306 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1307 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1308 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1309 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1310 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1311 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1312 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1313 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1314 struct i40e_vsi_vlan_pvid_info *info); 1315 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1316 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1317 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1318 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1319 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1320 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1321 int i40e_fdir_setup(struct i40e_pf *pf); 1322 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1323 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1324 uint32_t len, 1325 int socket_id); 1326 int i40e_fdir_configure(struct rte_eth_dev *dev); 1327 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1328 void i40e_fdir_teardown(struct i40e_pf *pf); 1329 enum i40e_filter_pctype 1330 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1331 uint16_t flow_type); 1332 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1333 enum i40e_filter_pctype pctype); 1334 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1335 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1336 struct rte_eth_fdir_info *fdir); 1337 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1338 struct rte_eth_fdir_stats *stat); 1339 int i40e_select_filter_input_set(struct i40e_hw *hw, 1340 struct rte_eth_input_set_conf *conf, 1341 enum rte_filter_type filter); 1342 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1343 int i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set, 1344 uint32_t pctype, bool add); 1345 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1346 uint32_t retval, uint8_t *msg, 1347 uint16_t msglen); 1348 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1349 struct rte_eth_rxq_info *qinfo); 1350 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1351 struct rte_eth_txq_info *qinfo); 1352 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1353 struct rte_eth_burst_mode *mode); 1354 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1355 struct rte_eth_burst_mode *mode); 1356 struct i40e_ethertype_filter * 1357 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1358 const struct i40e_ethertype_filter_input *input); 1359 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1360 struct i40e_ethertype_filter_input *input); 1361 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1362 struct i40e_fdir_input *input); 1363 struct i40e_tunnel_filter * 1364 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1365 const struct i40e_tunnel_filter_input *input); 1366 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1367 struct i40e_tunnel_filter_input *input); 1368 uint64_t i40e_get_default_input_set(uint16_t pctype); 1369 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1370 struct rte_eth_ethertype_filter *filter, 1371 bool add); 1372 struct rte_flow * 1373 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1374 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1375 struct rte_flow *flow); 1376 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1377 const struct i40e_fdir_filter_conf *filter, 1378 bool add); 1379 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1380 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1381 uint8_t add); 1382 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1383 struct i40e_tunnel_filter_conf *tunnel_filter, 1384 uint8_t add); 1385 int i40e_fdir_flush(struct rte_eth_dev *dev); 1386 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1387 struct i40e_macvlan_filter *mv_f, 1388 int num, struct rte_ether_addr *addr); 1389 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1390 struct i40e_macvlan_filter *filter, 1391 int total); 1392 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1393 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1394 struct i40e_macvlan_filter *filter, 1395 int total); 1396 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1397 bool is_i40e_supported(struct rte_eth_dev *dev); 1398 void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, 1399 uint8_t enable); 1400 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1401 enum rte_filter_type filter, uint64_t inset); 1402 int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset, 1403 uint32_t *mask, uint8_t nb_elem); 1404 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1405 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1406 void i40e_check_write_global_reg(struct i40e_hw *hw, 1407 uint32_t addr, uint32_t val); 1408 1409 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1410 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1411 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1412 struct i40e_customized_pctype* 1413 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1414 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1415 uint32_t pkg_size, 1416 enum rte_pmd_i40e_package_op op); 1417 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1418 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1419 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1420 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1421 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1422 void i40e_pf_disable_rss(struct i40e_pf *pf); 1423 int i40e_pf_calc_configured_queues_num(struct i40e_pf *pf); 1424 int i40e_pf_reset_rss_reta(struct i40e_pf *pf); 1425 int i40e_pf_reset_rss_key(struct i40e_pf *pf); 1426 int i40e_pf_config_rss(struct i40e_pf *pf); 1427 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1428 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1429 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1430 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1431 1432 #define I40E_DEV_TO_PCI(eth_dev) \ 1433 RTE_DEV_TO_PCI((eth_dev)->device) 1434 1435 /* I40E_DEV_PRIVATE_TO */ 1436 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1437 (&((struct i40e_adapter *)adapter)->pf) 1438 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1439 (&((struct i40e_adapter *)adapter)->hw) 1440 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1441 ((struct i40e_adapter *)adapter) 1442 1443 static inline struct i40e_vsi * 1444 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1445 { 1446 if (!adapter) 1447 return NULL; 1448 1449 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1450 1451 return pf->main_vsi; 1452 } 1453 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1454 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1455 1456 /* I40E_VSI_TO */ 1457 #define I40E_VSI_TO_HW(vsi) \ 1458 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1459 #define I40E_VSI_TO_PF(vsi) \ 1460 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1461 #define I40E_VSI_TO_VF(vsi) \ 1462 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1463 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1464 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1465 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1466 (&rte_eth_devices[((struct i40e_vsi *)vsi)->adapter->pf.dev_data->port_id]) 1467 1468 /* I40E_PF_TO */ 1469 #define I40E_PF_TO_HW(pf) \ 1470 (&(((struct i40e_pf *)pf)->adapter->hw)) 1471 #define I40E_PF_TO_ADAPTER(pf) \ 1472 ((struct i40e_adapter *)pf->adapter) 1473 1474 static inline void 1475 i40e_init_adminq_parameter(struct i40e_hw *hw) 1476 { 1477 hw->aq.num_arq_entries = I40E_AQ_LEN; 1478 hw->aq.num_asq_entries = I40E_AQ_LEN; 1479 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1480 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1481 } 1482 1483 static inline int 1484 i40e_align_floor(int n) 1485 { 1486 if (n == 0) 1487 return 0; 1488 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1489 } 1490 1491 static inline uint16_t 1492 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1493 { 1494 uint16_t interval = 0; 1495 1496 if (is_multi_drv) { 1497 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1498 } else { 1499 if (is_pf) 1500 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1501 else 1502 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1503 } 1504 1505 /* Convert to hardware count, as writing each 1 represents 2 us */ 1506 return interval / 2; 1507 } 1508 1509 #define I40E_VALID_FLOW(flow_type) \ 1510 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1511 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1512 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1513 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1514 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1515 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1516 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1517 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1518 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1519 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1520 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1521 1522 #define I40E_VALID_PCTYPE_X722(pctype) \ 1523 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1524 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1525 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1526 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1527 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1528 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1529 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1530 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1531 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1532 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1533 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1534 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1535 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1536 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1537 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1538 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1539 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1540 1541 #define I40E_VALID_PCTYPE(pctype) \ 1542 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1543 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1544 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1545 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1546 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1547 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1548 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1549 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1550 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1551 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1552 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1553 1554 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1555 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1556 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1557 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1558 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1559 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1560 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1561 1562 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1563 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1564 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1565 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1566 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1567 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1568 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1569 1570 #endif /* _I40E_ETHDEV_H_ */ 1571