1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_time.h> 11 #include <rte_kvargs.h> 12 #include <rte_hash.h> 13 #include <rte_flow.h> 14 #include <rte_flow_driver.h> 15 #include <rte_tm_driver.h> 16 #include "rte_pmd_i40e.h" 17 18 #include "base/i40e_register.h" 19 20 #define I40E_VLAN_TAG_SIZE 4 21 22 #define I40E_AQ_LEN 32 23 #define I40E_AQ_BUF_SZ 4096 24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 25 #define I40E_MAX_Q_PER_TC 64 26 #define I40E_NUM_DESC_DEFAULT 512 27 #define I40E_NUM_DESC_ALIGN 32 28 #define I40E_BUF_SIZE_MIN 1024 29 #define I40E_FRAME_SIZE_MAX 9728 30 #define I40E_TSO_FRAME_SIZE_MAX 262144 31 #define I40E_QUEUE_BASE_ADDR_UNIT 128 32 /* number of VSIs and queue default setting */ 33 #define I40E_MAX_QP_NUM_PER_VF 16 34 #define I40E_DEFAULT_QP_NUM_FDIR 1 35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 37 /* Maximun number of MAC addresses */ 38 #define I40E_NUM_MACADDR_MAX 64 39 /* Maximum number of VFs */ 40 #define I40E_MAX_VF 128 41 /*flag of no loopback*/ 42 #define I40E_AQ_LB_MODE_NONE 0x0 43 /* 44 * vlan_id is a 12 bit number. 45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 47 * The higher 7 bit val specifies VFTA array index. 48 */ 49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 51 52 /* Default TC traffic in case DCB is not enabled */ 53 #define I40E_DEFAULT_TCMAP 0x1 54 #define I40E_FDIR_QUEUE_ID 0 55 56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 57 #define I40E_VMDQ_POOL_BASE 1 58 59 #define I40E_DEFAULT_RX_FREE_THRESH 32 60 #define I40E_DEFAULT_RX_PTHRESH 8 61 #define I40E_DEFAULT_RX_HTHRESH 8 62 #define I40E_DEFAULT_RX_WTHRESH 0 63 64 #define I40E_DEFAULT_TX_FREE_THRESH 32 65 #define I40E_DEFAULT_TX_PTHRESH 32 66 #define I40E_DEFAULT_TX_HTHRESH 0 67 #define I40E_DEFAULT_TX_WTHRESH 0 68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 69 70 /* Bit shift and mask */ 71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 73 #define I40E_8_BIT_WIDTH CHAR_BIT 74 #define I40E_8_BIT_MASK UINT8_MAX 75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 76 #define I40E_16_BIT_MASK UINT16_MAX 77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 78 #define I40E_32_BIT_MASK UINT32_MAX 79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 81 82 /* Linux PF host with virtchnl version 1.1 */ 83 #define PF_IS_V11(vf) \ 84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 85 ((vf)->version_minor == 1)) 86 87 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 88 do { \ 89 uint32_t ori_val; \ 90 struct rte_eth_dev *dev; \ 91 ori_val = I40E_READ_REG((hw), (reg)); \ 92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \ 93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 94 (reg)), (value)); \ 95 if (ori_val != value) \ 96 PMD_DRV_LOG(WARNING, \ 97 "i40e device %s changed global " \ 98 "register [0x%08x]. original: 0x%08x, " \ 99 "new: 0x%08x ", \ 100 (dev->device->name), (reg), \ 101 (ori_val), (value)); \ 102 } while (0) 103 104 /* index flex payload per layer */ 105 enum i40e_flxpld_layer_idx { 106 I40E_FLXPLD_L2_IDX = 0, 107 I40E_FLXPLD_L3_IDX = 1, 108 I40E_FLXPLD_L4_IDX = 2, 109 I40E_MAX_FLXPLD_LAYER = 3, 110 }; 111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 116 117 /* i40e flags */ 118 #define I40E_FLAG_RSS (1ULL << 0) 119 #define I40E_FLAG_DCB (1ULL << 1) 120 #define I40E_FLAG_VMDQ (1ULL << 2) 121 #define I40E_FLAG_SRIOV (1ULL << 3) 122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 124 #define I40E_FLAG_FDIR (1ULL << 6) 125 #define I40E_FLAG_VXLAN (1ULL << 7) 126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 127 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 128 I40E_FLAG_DCB | \ 129 I40E_FLAG_VMDQ | \ 130 I40E_FLAG_SRIOV | \ 131 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 132 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 133 I40E_FLAG_FDIR | \ 134 I40E_FLAG_VXLAN | \ 135 I40E_FLAG_RSS_AQ_CAPABLE) 136 137 #define I40E_RSS_OFFLOAD_ALL ( \ 138 ETH_RSS_FRAG_IPV4 | \ 139 ETH_RSS_NONFRAG_IPV4_TCP | \ 140 ETH_RSS_NONFRAG_IPV4_UDP | \ 141 ETH_RSS_NONFRAG_IPV4_SCTP | \ 142 ETH_RSS_NONFRAG_IPV4_OTHER | \ 143 ETH_RSS_FRAG_IPV6 | \ 144 ETH_RSS_NONFRAG_IPV6_TCP | \ 145 ETH_RSS_NONFRAG_IPV6_UDP | \ 146 ETH_RSS_NONFRAG_IPV6_SCTP | \ 147 ETH_RSS_NONFRAG_IPV6_OTHER | \ 148 ETH_RSS_L2_PAYLOAD) 149 150 /* All bits of RSS hash enable for X722*/ 151 #define I40E_RSS_HENA_ALL_X722 ( \ 152 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 153 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 158 I40E_RSS_HENA_ALL) 159 160 /* All bits of RSS hash enable */ 161 #define I40E_RSS_HENA_ALL ( \ 162 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 166 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 171 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 172 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 173 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 175 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 176 177 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 178 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 179 180 /* Default queue interrupt throttling time in microseconds */ 181 #define I40E_ITR_INDEX_DEFAULT 0 182 #define I40E_ITR_INDEX_NONE 3 183 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 184 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 185 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 186 /* Special FW support this floating VEB feature */ 187 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 188 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 189 190 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 191 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 192 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 193 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 194 195 #define I40E_RSS_TYPE_NONE 0ULL 196 #define I40E_RSS_TYPE_INVALID 1ULL 197 198 #define I40E_INSET_NONE 0x00000000000000000ULL 199 200 /* bit0 ~ bit 7 */ 201 #define I40E_INSET_DMAC 0x0000000000000001ULL 202 #define I40E_INSET_SMAC 0x0000000000000002ULL 203 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 204 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 205 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 206 207 /* bit 8 ~ bit 15 */ 208 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 209 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 210 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 211 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 212 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 213 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 214 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 215 216 /* bit 16 ~ bit 31 */ 217 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 218 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 219 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 220 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 221 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 222 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 223 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 224 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 225 226 /* bit 32 ~ bit 47, tunnel fields */ 227 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 228 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 229 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 230 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 231 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 232 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 233 234 /* bit 48 ~ bit 55 */ 235 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 236 237 /* bit 56 ~ bit 63, Flex Payload */ 238 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 239 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 240 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 241 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 242 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 243 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 244 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 245 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 246 #define I40E_INSET_FLEX_PAYLOAD \ 247 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 248 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 249 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 250 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 251 252 /* The max bandwidth of i40e is 40Gbps. */ 253 #define I40E_QOS_BW_MAX 40000 254 /* The bandwidth should be the multiple of 50Mbps. */ 255 #define I40E_QOS_BW_GRANULARITY 50 256 /* The min bandwidth weight is 1. */ 257 #define I40E_QOS_BW_WEIGHT_MIN 1 258 /* The max bandwidth weight is 127. */ 259 #define I40E_QOS_BW_WEIGHT_MAX 127 260 /* The max queue region index is 7. */ 261 #define I40E_REGION_MAX_INDEX 7 262 263 #define I40E_MAX_PERCENT 100 264 #define I40E_DEFAULT_DCB_APP_NUM 1 265 #define I40E_DEFAULT_DCB_APP_PRIO 3 266 267 #define I40E_FDIR_PRG_PKT_CNT 128 268 269 /* 270 * Struct to store flow created. 271 */ 272 struct rte_flow { 273 TAILQ_ENTRY(rte_flow) node; 274 enum rte_filter_type filter_type; 275 void *rule; 276 }; 277 278 /** 279 * The overhead from MTU to max frame size. 280 * Considering QinQ packet, the VLAN tag needs to be counted twice. 281 */ 282 #define I40E_ETH_OVERHEAD \ 283 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 284 285 struct i40e_adapter; 286 struct rte_pci_driver; 287 288 /** 289 * MAC filter structure 290 */ 291 struct i40e_mac_filter_info { 292 enum rte_mac_filter_type filter_type; 293 struct rte_ether_addr mac_addr; 294 }; 295 296 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 297 298 /* MAC filter list structure */ 299 struct i40e_mac_filter { 300 TAILQ_ENTRY(i40e_mac_filter) next; 301 struct i40e_mac_filter_info mac_info; 302 }; 303 304 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 305 306 struct i40e_vsi; 307 308 /* VSI list structure */ 309 struct i40e_vsi_list { 310 TAILQ_ENTRY(i40e_vsi_list) list; 311 struct i40e_vsi *vsi; 312 }; 313 314 struct i40e_rx_queue; 315 struct i40e_tx_queue; 316 317 /* Bandwidth limit information */ 318 struct i40e_bw_info { 319 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 320 uint8_t bw_max; /* Max BW limit if enabled */ 321 322 /* Relative credits within same TC with respect to other VSIs or Comps */ 323 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 324 /* Bandwidth limit per TC */ 325 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 326 /* Max bandwidth limit per TC */ 327 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 328 }; 329 330 /* Structure that defines a VEB */ 331 struct i40e_veb { 332 struct i40e_vsi_list_head head; 333 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 334 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 335 uint16_t seid; /* The seid of VEB itself */ 336 uint16_t uplink_seid; /* The uplink seid of this VEB */ 337 uint16_t stats_idx; 338 struct i40e_eth_stats stats; 339 uint8_t enabled_tc; /* The traffic class enabled */ 340 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 341 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 342 }; 343 344 /* i40e MACVLAN filter structure */ 345 struct i40e_macvlan_filter { 346 struct rte_ether_addr macaddr; 347 enum rte_mac_filter_type filter_type; 348 uint16_t vlan_id; 349 }; 350 351 /* 352 * Structure that defines a VSI, associated with a adapter. 353 */ 354 struct i40e_vsi { 355 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 356 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 357 358 struct i40e_eth_stats eth_stats_offset; 359 struct i40e_eth_stats eth_stats; 360 /* 361 * When drivers loaded, only a default main VSI exists. In case new VSI 362 * needs to add, HW needs to know the layout that VSIs are organized. 363 * Besides that, VSI isan element and can't switch packets, which needs 364 * to add new component VEB to perform switching. So, a new VSI needs 365 * to specify the uplink VSI (Parent VSI) before created. The 366 * uplink VSI will check whether it had a VEB to switch packets. If no, 367 * it will try to create one. Then, uplink VSI will move the new VSI 368 * into its' sib_vsi_list to manage all the downlink VSI. 369 * sib_vsi_list: the VSI list that shared the same uplink VSI. 370 * parent_vsi : the uplink VSI. It's NULL for main VSI. 371 * veb : the VEB associates with the VSI. 372 */ 373 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 374 struct i40e_vsi *parent_vsi; 375 struct i40e_veb *veb; /* Associated veb, could be null */ 376 struct i40e_veb *floating_veb; /* Associated floating veb */ 377 bool offset_loaded; 378 enum i40e_vsi_type type; /* VSI types */ 379 uint16_t vlan_num; /* Total VLAN number */ 380 uint16_t mac_num; /* Total mac number */ 381 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 382 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 383 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 384 uint32_t user_param; 385 uint16_t seid; /* The seid of VSI itself */ 386 uint16_t uplink_seid; /* The uplink seid of this VSI */ 387 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 388 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 389 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 390 uint16_t base_queue; /* The first queue index of this VSI */ 391 /* 392 * The offset to visit VSI related register, assigned by HW when 393 * creating VSI 394 */ 395 uint16_t vsi_id; 396 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 397 uint16_t nb_msix; /* The max number of msix vector */ 398 uint8_t enabled_tc; /* The traffic class enabled */ 399 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 400 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 401 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 402 }; 403 404 struct pool_entry { 405 LIST_ENTRY(pool_entry) next; 406 uint16_t base; 407 uint16_t len; 408 }; 409 410 LIST_HEAD(res_list, pool_entry); 411 412 struct i40e_res_pool_info { 413 uint32_t base; /* Resource start index */ 414 uint32_t num_alloc; /* Allocated resource number */ 415 uint32_t num_free; /* Total available resource number */ 416 struct res_list alloc_list; /* Allocated resource list */ 417 struct res_list free_list; /* Available resource list */ 418 }; 419 420 enum I40E_VF_STATE { 421 I40E_VF_INACTIVE = 0, 422 I40E_VF_INRESET, 423 I40E_VF_ININIT, 424 I40E_VF_ACTIVE, 425 }; 426 427 /* 428 * Structure to store private data for PF host. 429 */ 430 struct i40e_pf_vf { 431 struct i40e_pf *pf; 432 struct i40e_vsi *vsi; 433 enum I40E_VF_STATE state; /* The number of queue pairs available */ 434 uint16_t vf_idx; /* VF index in pf->vfs */ 435 uint16_t lan_nb_qps; /* Actual queues allocated */ 436 uint16_t reset_cnt; /* Total vf reset times */ 437 struct rte_ether_addr mac_addr; /* Default MAC address */ 438 /* version of the virtchnl from VF */ 439 struct virtchnl_version_info version; 440 uint32_t request_caps; /* offload caps requested from VF */ 441 uint64_t num_mdd_events; /* num of mdd events detected */ 442 443 /* 444 * Variables for store the arrival timestamp of VF messages. 445 * If the timestamp of latest message stored at 446 * `msg_timestamps[index % max]` then the timestamp of 447 * earliest message stored at `msg_time[(index + 1) % max]`. 448 * When a new message come, the timestamp of this message 449 * will be stored at `msg_timestamps[(index + 1) % max]` and the 450 * earliest message timestamp is at 451 * `msg_timestamps[(index + 2) % max]` now... 452 */ 453 uint32_t msg_index; 454 uint64_t *msg_timestamps; 455 456 /* cycle of stop ignoring VF message */ 457 uint64_t ignore_end_cycle; 458 }; 459 460 /* 461 * Structure to store private data for flow control. 462 */ 463 struct i40e_fc_conf { 464 uint16_t pause_time; /* Flow control pause timer */ 465 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 466 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 467 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 468 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 469 }; 470 471 /* 472 * Structure to store private data for VMDQ instance 473 */ 474 struct i40e_vmdq_info { 475 struct i40e_pf *pf; 476 struct i40e_vsi *vsi; 477 }; 478 479 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 480 #define I40E_MAX_FLX_SOURCE_OFF 480 481 #define NONUSE_FLX_PIT_DEST_OFF 63 482 #define NONUSE_FLX_PIT_FSIZE 1 483 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 484 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 485 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 486 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 487 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 488 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 489 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 490 NONUSE_FLX_PIT_DEST_OFF : \ 491 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 492 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 493 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 494 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 495 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 496 #define I40E_FDIR_IPv6_TC_OFFSET 20 497 498 /* A structure used to define the input for GTP flow */ 499 struct i40e_gtp_flow { 500 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 501 uint8_t msg_type; /* Message type. */ 502 uint32_t teid; /* TEID in big endian. */ 503 }; 504 505 /* A structure used to define the input for GTP IPV4 flow */ 506 struct i40e_gtp_ipv4_flow { 507 struct i40e_gtp_flow gtp; 508 struct rte_eth_ipv4_flow ip4; 509 }; 510 511 /* A structure used to define the input for GTP IPV6 flow */ 512 struct i40e_gtp_ipv6_flow { 513 struct i40e_gtp_flow gtp; 514 struct rte_eth_ipv6_flow ip6; 515 }; 516 517 /* A structure used to define the input for ESP IPV4 flow */ 518 struct i40e_esp_ipv4_flow { 519 struct rte_eth_ipv4_flow ipv4; 520 uint32_t spi; /* SPI in big endian. */ 521 }; 522 523 /* A structure used to define the input for ESP IPV6 flow */ 524 struct i40e_esp_ipv6_flow { 525 struct rte_eth_ipv6_flow ipv6; 526 uint32_t spi; /* SPI in big endian. */ 527 }; 528 /* A structure used to define the input for ESP IPV4 UDP flow */ 529 struct i40e_esp_ipv4_udp_flow { 530 struct rte_eth_udpv4_flow udp; 531 uint32_t spi; /* SPI in big endian. */ 532 }; 533 534 /* A structure used to define the input for ESP IPV6 UDP flow */ 535 struct i40e_esp_ipv6_udp_flow { 536 struct rte_eth_udpv6_flow udp; 537 uint32_t spi; /* SPI in big endian. */ 538 }; 539 540 /* A structure used to define the input for raw type flow */ 541 struct i40e_raw_flow { 542 uint16_t pctype; 543 void *packet; 544 uint32_t length; 545 }; 546 547 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 548 struct i40e_ipv4_l2tpv3oip_flow { 549 struct rte_eth_ipv4_flow ip4; 550 uint32_t session_id; /* Session ID in big endian. */ 551 }; 552 553 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 554 struct i40e_ipv6_l2tpv3oip_flow { 555 struct rte_eth_ipv6_flow ip6; 556 uint32_t session_id; /* Session ID in big endian. */ 557 }; 558 559 /* A structure used to define the input for l2 dst type flow */ 560 struct i40e_l2_flow { 561 struct rte_ether_addr dst; 562 struct rte_ether_addr src; 563 uint16_t ether_type; /**< Ether type in big endian */ 564 }; 565 566 /* 567 * A union contains the inputs for all types of flow 568 * items in flows need to be in big endian 569 */ 570 union i40e_fdir_flow { 571 struct i40e_l2_flow l2_flow; 572 struct rte_eth_udpv4_flow udp4_flow; 573 struct rte_eth_tcpv4_flow tcp4_flow; 574 struct rte_eth_sctpv4_flow sctp4_flow; 575 struct rte_eth_ipv4_flow ip4_flow; 576 struct rte_eth_udpv6_flow udp6_flow; 577 struct rte_eth_tcpv6_flow tcp6_flow; 578 struct rte_eth_sctpv6_flow sctp6_flow; 579 struct rte_eth_ipv6_flow ipv6_flow; 580 struct i40e_gtp_flow gtp_flow; 581 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 582 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 583 struct i40e_raw_flow raw_flow; 584 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 585 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 586 struct i40e_esp_ipv4_flow esp_ipv4_flow; 587 struct i40e_esp_ipv6_flow esp_ipv6_flow; 588 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 589 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 590 }; 591 592 enum i40e_fdir_ip_type { 593 I40E_FDIR_IPTYPE_IPV4, 594 I40E_FDIR_IPTYPE_IPV6, 595 }; 596 597 /* A structure used to contain extend input of flow */ 598 struct i40e_fdir_flow_ext { 599 uint16_t vlan_tci; 600 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 601 /* It is filled by the flexible payload to match. */ 602 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 603 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 604 bool inner_ip; /* If there is inner ip */ 605 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 606 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 607 bool customized_pctype; /* If customized pctype is used */ 608 bool pkt_template; /* If raw packet template is used */ 609 bool is_udp; /* ipv4|ipv6 udp flow */ 610 }; 611 612 /* A structure used to define the input for a flow director filter entry */ 613 struct i40e_fdir_input { 614 enum i40e_filter_pctype pctype; 615 union i40e_fdir_flow flow; 616 /* Flow fields to match, dependent on flow_type */ 617 struct i40e_fdir_flow_ext flow_ext; 618 /* Additional fields to match */ 619 }; 620 621 /* Behavior will be taken if FDIR match */ 622 enum i40e_fdir_behavior { 623 I40E_FDIR_ACCEPT = 0, 624 I40E_FDIR_REJECT, 625 I40E_FDIR_PASSTHRU, 626 }; 627 628 /* Flow director report status 629 * It defines what will be reported if FDIR entry is matched. 630 */ 631 enum i40e_fdir_status { 632 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 633 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 634 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 635 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 636 }; 637 638 /* A structure used to define an action when match FDIR packet filter. */ 639 struct i40e_fdir_action { 640 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 641 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 642 enum i40e_fdir_status report_status; /* Status report option */ 643 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 644 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 645 * flex bytes start from in flexible payload. 646 */ 647 uint8_t flex_off; 648 }; 649 650 /* A structure used to define the flow director filter entry by filter_ctrl API 651 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and 652 * RTE_ETH_FILTER_DELETE operations. 653 */ 654 struct i40e_fdir_filter_conf { 655 uint32_t soft_id; 656 /* ID, an unique value is required when deal with FDIR entry */ 657 struct i40e_fdir_input input; /* Input set */ 658 struct i40e_fdir_action action; /* Action taken when match */ 659 }; 660 661 /* 662 * Structure to store flex pit for flow diretor. 663 */ 664 struct i40e_fdir_flex_pit { 665 uint8_t src_offset; /* offset in words from the beginning of payload */ 666 uint8_t size; /* size in words */ 667 uint8_t dst_offset; /* offset in words of flexible payload */ 668 }; 669 670 struct i40e_fdir_flex_mask { 671 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 672 uint8_t nb_bitmask; 673 struct { 674 uint8_t offset; 675 uint16_t mask; 676 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 677 }; 678 679 #define I40E_FILTER_PCTYPE_INVALID 0 680 #define I40E_FILTER_PCTYPE_MAX 64 681 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 682 683 struct i40e_fdir_filter { 684 TAILQ_ENTRY(i40e_fdir_filter) rules; 685 struct i40e_fdir_filter_conf fdir; 686 }; 687 688 /* fdir memory pool entry */ 689 struct i40e_fdir_entry { 690 struct rte_flow flow; 691 uint32_t idx; 692 }; 693 694 /* pre-allocated fdir memory pool */ 695 struct i40e_fdir_flow_pool { 696 /* a bitmap to manage the fdir pool */ 697 struct rte_bitmap *bitmap; 698 /* the size the pool is pf->fdir->fdir_space_size */ 699 struct i40e_fdir_entry *pool; 700 }; 701 702 #define FLOW_TO_FLOW_BITMAP(f) \ 703 container_of((f), struct i40e_fdir_entry, flow) 704 705 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 706 /* 707 * A structure used to define fields of a FDIR related info. 708 */ 709 struct i40e_fdir_info { 710 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 711 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 712 struct i40e_tx_queue *txq; 713 struct i40e_rx_queue *rxq; 714 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 715 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 716 /* 717 * txq available buffer counter, indicates how many available buffers 718 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 719 */ 720 int txq_available_buf_count; 721 722 /* input set bits for each pctype */ 723 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 724 /* 725 * the rule how bytes stream is extracted as flexible payload 726 * for each payload layer, the setting can up to three elements 727 */ 728 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 729 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 730 731 struct i40e_fdir_filter_list fdir_list; 732 struct i40e_fdir_filter **hash_map; 733 struct rte_hash *hash_table; 734 /* An array to store the inserted rules input */ 735 struct i40e_fdir_filter *fdir_filter_array; 736 737 /* 738 * Priority ordering at filter invalidation(destroying a flow) between 739 * "best effort" space and "guaranteed" space. 740 * 741 * 0 = At filter invalidation, the hardware first tries to increment the 742 * "best effort" space. The "guaranteed" space is incremented only when 743 * the global "best effort" space is at it max value or the "best effort" 744 * space of the PF is at its max value. 745 * 1 = At filter invalidation, the hardware first tries to increment its 746 * "guaranteed" space. The "best effort" space is incremented only when 747 * it is already at its max value. 748 */ 749 uint32_t fdir_invalprio; 750 /* the total size of the fdir, this number is the sum of the guaranteed + 751 * shared space 752 */ 753 uint32_t fdir_space_size; 754 /* the actual number of the fdir rules in hardware, initialized as 0 */ 755 uint32_t fdir_actual_cnt; 756 /* the free guaranteed space of the fdir */ 757 uint32_t fdir_guarantee_free_space; 758 /* the fdir total guaranteed space */ 759 uint32_t fdir_guarantee_total_space; 760 /* the pre-allocated pool of the rte_flow */ 761 struct i40e_fdir_flow_pool fdir_flow_pool; 762 763 /* Mark if flex pit and mask is set */ 764 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 765 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 766 767 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */ 768 }; 769 770 /* Ethertype filter number HW supports */ 771 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 772 773 /* Ethertype filter struct */ 774 struct i40e_ethertype_filter_input { 775 struct rte_ether_addr mac_addr; /* Mac address to match */ 776 uint16_t ether_type; /* Ether type to match */ 777 }; 778 779 struct i40e_ethertype_filter { 780 TAILQ_ENTRY(i40e_ethertype_filter) rules; 781 struct i40e_ethertype_filter_input input; 782 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 783 uint16_t queue; /* Queue assigned to when match */ 784 }; 785 786 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 787 788 struct i40e_ethertype_rule { 789 struct i40e_ethertype_filter_list ethertype_list; 790 struct i40e_ethertype_filter **hash_map; 791 struct rte_hash *hash_table; 792 }; 793 794 /* queue region info */ 795 struct i40e_queue_region_info { 796 /* the region id for this configuration */ 797 uint8_t region_id; 798 /* the start queue index for this region */ 799 uint8_t queue_start_index; 800 /* the total queue number of this queue region */ 801 uint8_t queue_num; 802 /* the total number of user priority for this region */ 803 uint8_t user_priority_num; 804 /* the packet's user priority for this region */ 805 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 806 /* the total number of flowtype for this region */ 807 uint8_t flowtype_num; 808 /** 809 * the pctype or hardware flowtype of packet, 810 * the specific index for each type has been defined 811 * in file i40e_type.h as enum i40e_filter_pctype. 812 */ 813 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 814 }; 815 816 struct i40e_queue_regions { 817 /* the total number of queue region for this port */ 818 uint16_t queue_region_number; 819 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 820 }; 821 822 struct i40e_rss_pattern_info { 823 uint8_t action_flag; 824 uint64_t types; 825 }; 826 827 /* Tunnel filter number HW supports */ 828 #define I40E_MAX_TUNNEL_FILTER_NUM 400 829 830 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 831 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 832 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 833 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 834 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 835 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 836 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 837 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 838 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 839 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 840 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 841 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 842 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 843 #define I40E_AQC_NEW_TR_21 21 844 #define I40E_AQC_NEW_TR_22 22 845 846 enum i40e_tunnel_iptype { 847 I40E_TUNNEL_IPTYPE_IPV4, 848 I40E_TUNNEL_IPTYPE_IPV6, 849 }; 850 851 /* Tunnel filter struct */ 852 struct i40e_tunnel_filter_input { 853 uint8_t outer_mac[6]; /* Outer mac address to match */ 854 uint8_t inner_mac[6]; /* Inner mac address to match */ 855 uint16_t inner_vlan; /* Inner vlan address to match */ 856 enum i40e_tunnel_iptype ip_type; 857 uint16_t flags; /* Filter type flag */ 858 uint32_t tenant_id; /* Tenant id to match */ 859 uint16_t general_fields[32]; /* Big buffer */ 860 }; 861 862 struct i40e_tunnel_filter { 863 TAILQ_ENTRY(i40e_tunnel_filter) rules; 864 struct i40e_tunnel_filter_input input; 865 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 866 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 867 uint16_t queue; /* Queue assigned to when match */ 868 }; 869 870 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 871 872 struct i40e_tunnel_rule { 873 struct i40e_tunnel_filter_list tunnel_list; 874 struct i40e_tunnel_filter **hash_map; 875 struct rte_hash *hash_table; 876 }; 877 878 /** 879 * Tunnel type. 880 */ 881 enum i40e_tunnel_type { 882 I40E_TUNNEL_TYPE_NONE = 0, 883 I40E_TUNNEL_TYPE_VXLAN, 884 I40E_TUNNEL_TYPE_GENEVE, 885 I40E_TUNNEL_TYPE_TEREDO, 886 I40E_TUNNEL_TYPE_NVGRE, 887 I40E_TUNNEL_TYPE_IP_IN_GRE, 888 I40E_L2_TUNNEL_TYPE_E_TAG, 889 I40E_TUNNEL_TYPE_MPLSoUDP, 890 I40E_TUNNEL_TYPE_MPLSoGRE, 891 I40E_TUNNEL_TYPE_QINQ, 892 I40E_TUNNEL_TYPE_GTPC, 893 I40E_TUNNEL_TYPE_GTPU, 894 I40E_TUNNEL_TYPE_ESPoUDP, 895 I40E_TUNNEL_TYPE_ESPoIP, 896 I40E_CLOUD_TYPE_UDP, 897 I40E_CLOUD_TYPE_TCP, 898 I40E_CLOUD_TYPE_SCTP, 899 I40E_TUNNEL_TYPE_MAX, 900 }; 901 902 /** 903 * L4 port type. 904 */ 905 enum i40e_l4_port_type { 906 I40E_L4_PORT_TYPE_SRC = 0, 907 I40E_L4_PORT_TYPE_DST, 908 }; 909 910 /** 911 * Tunneling Packet filter configuration. 912 */ 913 struct i40e_tunnel_filter_conf { 914 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 915 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 916 uint16_t inner_vlan; /**< Inner VLAN to match. */ 917 uint32_t outer_vlan; /**< Outer VLAN to match */ 918 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 919 /** 920 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 921 * is set in filter_type, or inner destination IP address to match 922 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 923 */ 924 union { 925 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 926 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 927 } ip_addr; 928 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 929 uint16_t filter_type; 930 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 931 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 932 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 933 uint16_t queue_id; /**< Queue assigned to if match. */ 934 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 935 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 936 }; 937 938 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 939 #define I40E_MAX_MIRROR_RULES 64 940 /* 941 * Mirror rule structure 942 */ 943 struct i40e_mirror_rule { 944 TAILQ_ENTRY(i40e_mirror_rule) rules; 945 uint8_t rule_type; 946 uint16_t index; /* the sw index of mirror rule */ 947 uint16_t id; /* the rule id assigned by firmware */ 948 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 949 uint16_t num_entries; 950 /* the info stores depend on the rule type. 951 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 952 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 953 */ 954 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 955 }; 956 957 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 958 959 TAILQ_HEAD(i40e_flow_list, rte_flow); 960 961 /* Struct to store Traffic Manager shaper profile. */ 962 struct i40e_tm_shaper_profile { 963 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 964 uint32_t shaper_profile_id; 965 uint32_t reference_count; 966 struct rte_tm_shaper_params profile; 967 }; 968 969 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 970 971 /* node type of Traffic Manager */ 972 enum i40e_tm_node_type { 973 I40E_TM_NODE_TYPE_PORT, 974 I40E_TM_NODE_TYPE_TC, 975 I40E_TM_NODE_TYPE_QUEUE, 976 I40E_TM_NODE_TYPE_MAX, 977 }; 978 979 /* Struct to store Traffic Manager node configuration. */ 980 struct i40e_tm_node { 981 TAILQ_ENTRY(i40e_tm_node) node; 982 uint32_t id; 983 uint32_t priority; 984 uint32_t weight; 985 uint32_t reference_count; 986 struct i40e_tm_node *parent; 987 struct i40e_tm_shaper_profile *shaper_profile; 988 struct rte_tm_node_params params; 989 }; 990 991 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 992 993 /* Struct to store all the Traffic Manager configuration. */ 994 struct i40e_tm_conf { 995 struct i40e_shaper_profile_list shaper_profile_list; 996 struct i40e_tm_node *root; /* root node - port */ 997 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 998 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 999 /** 1000 * The number of added TC nodes. 1001 * It should be no more than the TC number of this port. 1002 */ 1003 uint32_t nb_tc_node; 1004 /** 1005 * The number of added queue nodes. 1006 * It should be no more than the queue number of this port. 1007 */ 1008 uint32_t nb_queue_node; 1009 /** 1010 * This flag is used to check if APP can change the TM node 1011 * configuration. 1012 * When it's true, means the configuration is applied to HW, 1013 * APP should not change the configuration. 1014 * As we don't support on-the-fly configuration, when starting 1015 * the port, APP should call the hierarchy_commit API to set this 1016 * flag to true. When stopping the port, this flag should be set 1017 * to false. 1018 */ 1019 bool committed; 1020 }; 1021 1022 enum i40e_new_pctype { 1023 I40E_CUSTOMIZED_GTPC = 0, 1024 I40E_CUSTOMIZED_GTPU_IPV4, 1025 I40E_CUSTOMIZED_GTPU_IPV6, 1026 I40E_CUSTOMIZED_GTPU, 1027 I40E_CUSTOMIZED_IPV4_L2TPV3, 1028 I40E_CUSTOMIZED_IPV6_L2TPV3, 1029 I40E_CUSTOMIZED_ESP_IPV4, 1030 I40E_CUSTOMIZED_ESP_IPV6, 1031 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1032 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1033 I40E_CUSTOMIZED_AH_IPV4, 1034 I40E_CUSTOMIZED_AH_IPV6, 1035 I40E_CUSTOMIZED_MAX, 1036 }; 1037 1038 #define I40E_FILTER_PCTYPE_INVALID 0 1039 struct i40e_customized_pctype { 1040 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1041 uint8_t pctype; /* New pctype value */ 1042 bool valid; /* Check if it's valid */ 1043 }; 1044 1045 struct i40e_rte_flow_rss_conf { 1046 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1047 uint16_t queue_region_conf; /**< Queue region config flag */ 1048 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1049 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1050 sizeof(uint32_t)]; /* Hash key. */ 1051 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */ 1052 bool valid; /* Check if it's valid */ 1053 }; 1054 1055 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1056 1057 /* RSS filter list structure */ 1058 struct i40e_rss_filter { 1059 TAILQ_ENTRY(i40e_rss_filter) next; 1060 struct i40e_rte_flow_rss_conf rss_filter_info; 1061 }; 1062 1063 struct i40e_vf_msg_cfg { 1064 /* maximal VF message during a statistic period */ 1065 uint32_t max_msg; 1066 1067 /* statistic period, in second */ 1068 uint32_t period; 1069 /* 1070 * If message statistics from a VF exceed the maximal limitation, 1071 * the PF will ignore any new message from that VF for 1072 * 'ignor_second' time. 1073 */ 1074 uint32_t ignore_second; 1075 }; 1076 1077 /* 1078 * Structure to store private data specific for PF instance. 1079 */ 1080 struct i40e_pf { 1081 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1082 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1083 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1084 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1085 uint16_t max_num_vsi; 1086 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1087 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1088 1089 struct i40e_hw_port_stats stats_offset; 1090 struct i40e_hw_port_stats stats; 1091 /* internal packet statistics, it should be excluded from the total */ 1092 struct i40e_eth_stats internal_stats_offset; 1093 struct i40e_eth_stats internal_stats; 1094 bool offset_loaded; 1095 1096 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1097 struct rte_ether_addr dev_addr; /* PF device mac address */ 1098 uint64_t flags; /* PF feature flags */ 1099 /* All kinds of queue pair setting for different VSIs */ 1100 struct i40e_pf_vf *vfs; 1101 uint16_t vf_num; 1102 /* Each of below queue pairs should be power of 2 since it's the 1103 precondition after TC configuration applied */ 1104 uint16_t lan_nb_qp_max; 1105 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1106 uint16_t lan_qp_offset; 1107 uint16_t vmdq_nb_qp_max; 1108 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1109 uint16_t vmdq_qp_offset; 1110 uint16_t vf_nb_qp_max; 1111 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1112 uint16_t vf_qp_offset; 1113 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1114 uint16_t fdir_qp_offset; 1115 1116 uint16_t hash_lut_size; /* The size of hash lookup table */ 1117 /* input set bits for each pctype */ 1118 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1119 /* store VXLAN UDP ports */ 1120 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1121 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1122 1123 /* VMDQ related info */ 1124 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1125 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1126 struct i40e_vmdq_info *vmdq; 1127 1128 struct i40e_fdir_info fdir; /* flow director info */ 1129 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1130 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1131 struct i40e_rte_flow_rss_conf rss_info; /* RSS info */ 1132 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1133 struct i40e_queue_regions queue_region; /* queue region info */ 1134 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1135 struct i40e_mirror_rule_list mirror_list; 1136 uint16_t nb_mirror_rule; /* The number of mirror rules */ 1137 bool floating_veb; /* The flag to use the floating VEB */ 1138 /* The floating enable flag for the specific VF */ 1139 bool floating_veb_list[I40E_MAX_VF]; 1140 struct i40e_flow_list flow_list; 1141 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1142 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1143 bool qinq_replace_flag; /* QINQ filter replace is done */ 1144 /* l4 port flag */ 1145 bool sport_replace_flag; /* Source port replace is done */ 1146 bool dport_replace_flag; /* Destination port replace is done */ 1147 struct i40e_tm_conf tm_conf; 1148 bool support_multi_driver; /* 1 - support multiple driver */ 1149 1150 /* Dynamic Device Personalization */ 1151 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1152 bool esp_support; /* 1 - support ESP SPI */ 1153 /* customer customized pctype */ 1154 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1155 /* Switch Domain Id */ 1156 uint16_t switch_domain_id; 1157 1158 struct i40e_vf_msg_cfg vf_msg_cfg; 1159 }; 1160 1161 enum pending_msg { 1162 PFMSG_LINK_CHANGE = 0x1, 1163 PFMSG_RESET_IMPENDING = 0x2, 1164 PFMSG_DRIVER_CLOSE = 0x4, 1165 }; 1166 1167 struct i40e_vsi_vlan_pvid_info { 1168 uint16_t on; /* Enable or disable pvid */ 1169 union { 1170 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1171 struct { 1172 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1173 * while 'untagged' will reject untagged packets. 1174 */ 1175 uint8_t tagged; 1176 uint8_t untagged; 1177 } reject; 1178 } config; 1179 }; 1180 1181 struct i40e_vf_rx_queues { 1182 uint64_t rx_dma_addr; 1183 uint32_t rx_ring_len; 1184 uint32_t buff_size; 1185 }; 1186 1187 struct i40e_vf_tx_queues { 1188 uint64_t tx_dma_addr; 1189 uint32_t tx_ring_len; 1190 }; 1191 1192 /* 1193 * Structure to store private data specific for VF instance. 1194 */ 1195 struct i40e_vf { 1196 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 1197 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1198 uint16_t num_queue_pairs; 1199 uint16_t max_pkt_len; /* Maximum packet length */ 1200 bool promisc_unicast_enabled; 1201 bool promisc_multicast_enabled; 1202 1203 uint32_t version_major; /* Major version number */ 1204 uint32_t version_minor; /* Minor version number */ 1205 uint16_t promisc_flags; /* Promiscuous setting */ 1206 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1207 1208 /* Multicast addrs */ 1209 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; 1210 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1211 1212 /* Event from pf */ 1213 bool dev_closed; 1214 bool link_up; 1215 enum virtchnl_link_speed link_speed; 1216 bool vf_reset; 1217 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1218 int32_t cmd_retval; /* return value of the cmd response from PF */ 1219 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1220 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1221 1222 /* VSI info */ 1223 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1224 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1225 struct i40e_vsi vsi; 1226 uint64_t flags; 1227 }; 1228 1229 #define I40E_MAX_PKT_TYPE 256 1230 #define I40E_FLOW_TYPE_MAX 64 1231 1232 /* 1233 * Structure to store private data for each PF/VF instance. 1234 */ 1235 struct i40e_adapter { 1236 /* Common for both PF and VF */ 1237 struct i40e_hw hw; 1238 struct rte_eth_dev *eth_dev; 1239 1240 /* Specific for PF or VF */ 1241 union { 1242 struct i40e_pf pf; 1243 struct i40e_vf vf; 1244 }; 1245 1246 /* For vector PMD */ 1247 bool rx_bulk_alloc_allowed; 1248 bool rx_vec_allowed; 1249 bool tx_simple_allowed; 1250 bool tx_vec_allowed; 1251 1252 /* For PTP */ 1253 struct rte_timecounter systime_tc; 1254 struct rte_timecounter rx_tstamp_tc; 1255 struct rte_timecounter tx_tstamp_tc; 1256 1257 /* ptype mapping table */ 1258 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1259 /* flow type to pctype mapping table */ 1260 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1261 uint64_t flow_types_mask; 1262 uint64_t pctypes_mask; 1263 1264 /* For devargs */ 1265 uint8_t use_latest_vec; 1266 1267 /* For RSS reta table update */ 1268 uint8_t rss_reta_updated; 1269 }; 1270 1271 /** 1272 * Strucute to store private data for each VF representor instance 1273 */ 1274 struct i40e_vf_representor { 1275 uint16_t switch_domain_id; 1276 /**< Virtual Function ID */ 1277 uint16_t vf_id; 1278 /**< Virtual Function ID */ 1279 struct i40e_adapter *adapter; 1280 /**< Private data store of assocaiated physical function */ 1281 struct i40e_eth_stats stats_offset; 1282 /**< Zero-point of VF statistics*/ 1283 }; 1284 1285 extern const struct rte_flow_ops i40e_flow_ops; 1286 1287 union i40e_filter_t { 1288 struct rte_eth_ethertype_filter ethertype_filter; 1289 struct i40e_fdir_filter_conf fdir_filter; 1290 struct rte_eth_tunnel_filter_conf tunnel_filter; 1291 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1292 struct i40e_rte_flow_rss_conf rss_conf; 1293 }; 1294 1295 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1296 const struct rte_flow_attr *attr, 1297 const struct rte_flow_item pattern[], 1298 const struct rte_flow_action actions[], 1299 struct rte_flow_error *error, 1300 union i40e_filter_t *filter); 1301 struct i40e_valid_pattern { 1302 enum rte_flow_item_type *items; 1303 parse_filter_t parse_filter; 1304 }; 1305 1306 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1307 int i40e_vsi_release(struct i40e_vsi *vsi); 1308 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1309 enum i40e_vsi_type type, 1310 struct i40e_vsi *uplink_vsi, 1311 uint16_t user_param); 1312 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1313 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1314 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1315 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1316 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1317 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1318 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1319 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1320 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1321 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1322 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1323 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1324 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1325 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1326 struct i40e_vsi_vlan_pvid_info *info); 1327 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1328 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1329 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1330 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1331 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1332 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1333 int i40e_fdir_setup(struct i40e_pf *pf); 1334 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1335 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1336 uint32_t len, 1337 int socket_id); 1338 int i40e_fdir_configure(struct rte_eth_dev *dev); 1339 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1340 void i40e_fdir_teardown(struct i40e_pf *pf); 1341 enum i40e_filter_pctype 1342 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1343 uint16_t flow_type); 1344 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1345 enum i40e_filter_pctype pctype); 1346 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1347 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1348 struct rte_eth_fdir_info *fdir); 1349 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1350 struct rte_eth_fdir_stats *stat); 1351 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev, 1352 enum rte_filter_op filter_op, 1353 void *arg); 1354 int i40e_select_filter_input_set(struct i40e_hw *hw, 1355 struct rte_eth_input_set_conf *conf, 1356 enum rte_filter_type filter); 1357 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1358 int i40e_hash_filter_inset_select(struct i40e_hw *hw, 1359 struct rte_eth_input_set_conf *conf); 1360 int i40e_fdir_filter_inset_select(struct i40e_pf *pf, 1361 struct rte_eth_input_set_conf *conf); 1362 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1363 uint32_t retval, uint8_t *msg, 1364 uint16_t msglen); 1365 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1366 struct rte_eth_rxq_info *qinfo); 1367 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1368 struct rte_eth_txq_info *qinfo); 1369 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1370 struct rte_eth_burst_mode *mode); 1371 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1372 struct rte_eth_burst_mode *mode); 1373 struct i40e_ethertype_filter * 1374 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1375 const struct i40e_ethertype_filter_input *input); 1376 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1377 struct i40e_ethertype_filter_input *input); 1378 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1379 struct i40e_fdir_input *input); 1380 struct i40e_tunnel_filter * 1381 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1382 const struct i40e_tunnel_filter_input *input); 1383 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1384 struct i40e_tunnel_filter_input *input); 1385 uint64_t i40e_get_default_input_set(uint16_t pctype); 1386 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1387 struct rte_eth_ethertype_filter *filter, 1388 bool add); 1389 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev, 1390 const struct rte_eth_fdir_filter *filter, 1391 bool add); 1392 struct rte_flow * 1393 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1394 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1395 struct rte_flow *flow); 1396 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1397 const struct i40e_fdir_filter_conf *filter, 1398 bool add); 1399 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1400 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1401 uint8_t add); 1402 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1403 struct i40e_tunnel_filter_conf *tunnel_filter, 1404 uint8_t add); 1405 int i40e_fdir_flush(struct rte_eth_dev *dev); 1406 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1407 struct i40e_macvlan_filter *mv_f, 1408 int num, struct rte_ether_addr *addr); 1409 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1410 struct i40e_macvlan_filter *filter, 1411 int total); 1412 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1413 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1414 struct i40e_macvlan_filter *filter, 1415 int total); 1416 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1417 bool is_i40e_supported(struct rte_eth_dev *dev); 1418 bool is_i40evf_supported(struct rte_eth_dev *dev); 1419 1420 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1421 enum rte_filter_type filter, uint64_t inset); 1422 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, 1423 uint8_t nb_elem); 1424 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1425 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1426 void i40e_check_write_global_reg(struct i40e_hw *hw, 1427 uint32_t addr, uint32_t val); 1428 1429 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1430 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1431 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1432 struct i40e_customized_pctype* 1433 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1434 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1435 uint32_t pkg_size, 1436 enum rte_pmd_i40e_package_op op); 1437 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1438 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1439 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1440 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1441 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1442 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1443 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1444 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, 1445 const struct rte_flow_action_rss *in); 1446 int i40e_config_rss_filter(struct i40e_pf *pf, 1447 struct i40e_rte_flow_rss_conf *conf, bool add); 1448 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1449 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1450 1451 #define I40E_DEV_TO_PCI(eth_dev) \ 1452 RTE_DEV_TO_PCI((eth_dev)->device) 1453 1454 /* I40E_DEV_PRIVATE_TO */ 1455 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1456 (&((struct i40e_adapter *)adapter)->pf) 1457 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1458 (&((struct i40e_adapter *)adapter)->hw) 1459 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1460 ((struct i40e_adapter *)adapter) 1461 1462 /* I40EVF_DEV_PRIVATE_TO */ 1463 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1464 (&((struct i40e_adapter *)adapter)->vf) 1465 1466 static inline struct i40e_vsi * 1467 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1468 { 1469 struct i40e_hw *hw; 1470 1471 if (!adapter) 1472 return NULL; 1473 1474 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1475 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1476 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1477 return &vf->vsi; 1478 } else { 1479 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1480 return pf->main_vsi; 1481 } 1482 } 1483 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1484 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1485 1486 /* I40E_VSI_TO */ 1487 #define I40E_VSI_TO_HW(vsi) \ 1488 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1489 #define I40E_VSI_TO_PF(vsi) \ 1490 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1491 #define I40E_VSI_TO_VF(vsi) \ 1492 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1493 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1494 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1495 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1496 (((struct i40e_vsi *)vsi)->adapter->eth_dev) 1497 1498 /* I40E_PF_TO */ 1499 #define I40E_PF_TO_HW(pf) \ 1500 (&(((struct i40e_pf *)pf)->adapter->hw)) 1501 #define I40E_PF_TO_ADAPTER(pf) \ 1502 ((struct i40e_adapter *)pf->adapter) 1503 1504 /* I40E_VF_TO */ 1505 #define I40E_VF_TO_HW(vf) \ 1506 (&(((struct i40e_vf *)vf)->adapter->hw)) 1507 1508 static inline void 1509 i40e_init_adminq_parameter(struct i40e_hw *hw) 1510 { 1511 hw->aq.num_arq_entries = I40E_AQ_LEN; 1512 hw->aq.num_asq_entries = I40E_AQ_LEN; 1513 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1514 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1515 } 1516 1517 static inline int 1518 i40e_align_floor(int n) 1519 { 1520 if (n == 0) 1521 return 0; 1522 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1523 } 1524 1525 static inline uint16_t 1526 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1527 { 1528 uint16_t interval = 0; 1529 1530 if (is_multi_drv) { 1531 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1532 } else { 1533 if (is_pf) 1534 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1535 else 1536 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1537 } 1538 1539 /* Convert to hardware count, as writing each 1 represents 2 us */ 1540 return interval / 2; 1541 } 1542 1543 #define I40E_VALID_FLOW(flow_type) \ 1544 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1545 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1546 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1547 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1548 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1549 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1550 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1551 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1552 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1553 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1554 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1555 1556 #define I40E_VALID_PCTYPE_X722(pctype) \ 1557 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1558 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1559 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1560 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1561 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1562 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1563 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1564 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1565 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1566 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1567 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1568 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1569 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1570 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1571 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1572 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1573 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1574 1575 #define I40E_VALID_PCTYPE(pctype) \ 1576 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1577 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1578 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1579 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1580 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1581 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1582 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1583 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1584 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1585 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1586 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1587 1588 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1589 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1590 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1591 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1592 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1593 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1594 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1595 1596 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1597 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1598 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1599 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1600 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1601 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1602 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1603 1604 #endif /* _I40E_ETHDEV_H_ */ 1605