1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #ifndef _I40E_ETHDEV_H_ 6 #define _I40E_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_time.h> 11 #include <rte_kvargs.h> 12 #include <rte_hash.h> 13 #include <rte_flow.h> 14 #include <rte_flow_driver.h> 15 #include <rte_tm_driver.h> 16 #include "rte_pmd_i40e.h" 17 18 #include "base/i40e_register.h" 19 #include "base/i40e_type.h" 20 #include "base/virtchnl.h" 21 22 #define I40E_VLAN_TAG_SIZE 4 23 24 #define I40E_AQ_LEN 32 25 #define I40E_AQ_BUF_SZ 4096 26 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ 27 #define I40E_MAX_Q_PER_TC 64 28 #define I40E_NUM_DESC_DEFAULT 512 29 #define I40E_NUM_DESC_ALIGN 32 30 #define I40E_BUF_SIZE_MIN 1024 31 #define I40E_FRAME_SIZE_MAX 9728 32 #define I40E_TSO_FRAME_SIZE_MAX 262144 33 #define I40E_QUEUE_BASE_ADDR_UNIT 128 34 /* number of VSIs and queue default setting */ 35 #define I40E_MAX_QP_NUM_PER_VF 16 36 #define I40E_DEFAULT_QP_NUM_FDIR 1 37 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) 38 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) 39 /* Maximun number of MAC addresses */ 40 #define I40E_NUM_MACADDR_MAX 64 41 /* Maximum number of VFs */ 42 #define I40E_MAX_VF 128 43 /*flag of no loopback*/ 44 #define I40E_AQ_LB_MODE_NONE 0x0 45 /* 46 * vlan_id is a 12 bit number. 47 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 48 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 49 * The higher 7 bit val specifies VFTA array index. 50 */ 51 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 52 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 53 54 /* Default TC traffic in case DCB is not enabled */ 55 #define I40E_DEFAULT_TCMAP 0x1 56 #define I40E_FDIR_QUEUE_ID 0 57 58 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ 59 #define I40E_VMDQ_POOL_BASE 1 60 61 #define I40E_DEFAULT_RX_FREE_THRESH 32 62 #define I40E_DEFAULT_RX_PTHRESH 8 63 #define I40E_DEFAULT_RX_HTHRESH 8 64 #define I40E_DEFAULT_RX_WTHRESH 0 65 66 #define I40E_DEFAULT_TX_FREE_THRESH 32 67 #define I40E_DEFAULT_TX_PTHRESH 32 68 #define I40E_DEFAULT_TX_HTHRESH 0 69 #define I40E_DEFAULT_TX_WTHRESH 0 70 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 71 72 /* Bit shift and mask */ 73 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) 74 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) 75 #define I40E_8_BIT_WIDTH CHAR_BIT 76 #define I40E_8_BIT_MASK UINT8_MAX 77 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) 78 #define I40E_16_BIT_MASK UINT16_MAX 79 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) 80 #define I40E_32_BIT_MASK UINT32_MAX 81 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) 82 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) 83 84 /* Linux PF host with virtchnl version 1.1 */ 85 #define PF_IS_V11(vf) \ 86 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \ 87 ((vf)->version_minor == 1)) 88 89 #define I40E_WRITE_GLB_REG(hw, reg, value) \ 90 do { \ 91 uint32_t ori_val; \ 92 struct rte_eth_dev *dev; \ 93 ori_val = I40E_READ_REG((hw), (reg)); \ 94 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \ 95 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ 96 (reg)), (value)); \ 97 if (ori_val != value) \ 98 PMD_DRV_LOG(WARNING, \ 99 "i40e device %s changed global " \ 100 "register [0x%08x]. original: 0x%08x, " \ 101 "new: 0x%08x ", \ 102 (dev->device->name), (reg), \ 103 (ori_val), (value)); \ 104 } while (0) 105 106 /* index flex payload per layer */ 107 enum i40e_flxpld_layer_idx { 108 I40E_FLXPLD_L2_IDX = 0, 109 I40E_FLXPLD_L3_IDX = 1, 110 I40E_FLXPLD_L4_IDX = 2, 111 I40E_MAX_FLXPLD_LAYER = 3, 112 }; 113 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ 114 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ 115 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ 116 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ 117 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ 118 119 /* i40e flags */ 120 #define I40E_FLAG_RSS (1ULL << 0) 121 #define I40E_FLAG_DCB (1ULL << 1) 122 #define I40E_FLAG_VMDQ (1ULL << 2) 123 #define I40E_FLAG_SRIOV (1ULL << 3) 124 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) 125 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) 126 #define I40E_FLAG_FDIR (1ULL << 6) 127 #define I40E_FLAG_VXLAN (1ULL << 7) 128 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) 129 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ 130 I40E_FLAG_DCB | \ 131 I40E_FLAG_VMDQ | \ 132 I40E_FLAG_SRIOV | \ 133 I40E_FLAG_HEADER_SPLIT_DISABLED | \ 134 I40E_FLAG_HEADER_SPLIT_ENABLED | \ 135 I40E_FLAG_FDIR | \ 136 I40E_FLAG_VXLAN | \ 137 I40E_FLAG_RSS_AQ_CAPABLE) 138 139 #define I40E_RSS_OFFLOAD_ALL ( \ 140 ETH_RSS_FRAG_IPV4 | \ 141 ETH_RSS_NONFRAG_IPV4_TCP | \ 142 ETH_RSS_NONFRAG_IPV4_UDP | \ 143 ETH_RSS_NONFRAG_IPV4_SCTP | \ 144 ETH_RSS_NONFRAG_IPV4_OTHER | \ 145 ETH_RSS_FRAG_IPV6 | \ 146 ETH_RSS_NONFRAG_IPV6_TCP | \ 147 ETH_RSS_NONFRAG_IPV6_UDP | \ 148 ETH_RSS_NONFRAG_IPV6_SCTP | \ 149 ETH_RSS_NONFRAG_IPV6_OTHER | \ 150 ETH_RSS_L2_PAYLOAD) 151 152 /* All bits of RSS hash enable for X722*/ 153 #define I40E_RSS_HENA_ALL_X722 ( \ 154 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 155 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 157 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 158 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 160 I40E_RSS_HENA_ALL) 161 162 /* All bits of RSS hash enable */ 163 #define I40E_RSS_HENA_ALL ( \ 164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 168 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 173 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ 175 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ 176 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ 177 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 178 179 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 180 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 181 182 /* Default queue interrupt throttling time in microseconds */ 183 #define I40E_ITR_INDEX_DEFAULT 0 184 #define I40E_ITR_INDEX_NONE 3 185 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 186 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ 187 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ 188 /* Special FW support this floating VEB feature */ 189 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 190 #define FLOATING_VEB_SUPPORTED_FW_MIN 0 191 192 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4)) 193 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16 194 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \ 195 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) 196 197 #define I40E_RSS_TYPE_NONE 0ULL 198 #define I40E_RSS_TYPE_INVALID 1ULL 199 200 #define I40E_INSET_NONE 0x00000000000000000ULL 201 202 /* bit0 ~ bit 7 */ 203 #define I40E_INSET_DMAC 0x0000000000000001ULL 204 #define I40E_INSET_SMAC 0x0000000000000002ULL 205 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL 206 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL 207 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL 208 209 /* bit 8 ~ bit 15 */ 210 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL 211 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL 212 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL 213 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL 214 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL 215 #define I40E_INSET_DST_PORT 0x0000000000002000ULL 216 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL 217 218 /* bit 16 ~ bit 31 */ 219 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL 220 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL 221 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL 222 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL 223 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL 224 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL 225 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL 226 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL 227 228 /* bit 32 ~ bit 47, tunnel fields */ 229 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL 230 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL 231 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL 232 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL 233 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL 234 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL 235 236 /* bit 48 ~ bit 55 */ 237 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL 238 239 /* bit 56 ~ bit 63, Flex Payload */ 240 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL 241 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL 242 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL 243 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL 244 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL 245 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL 246 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL 247 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL 248 #define I40E_INSET_FLEX_PAYLOAD \ 249 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \ 250 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \ 251 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \ 252 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8) 253 254 /* The max bandwidth of i40e is 40Gbps. */ 255 #define I40E_QOS_BW_MAX 40000 256 /* The bandwidth should be the multiple of 50Mbps. */ 257 #define I40E_QOS_BW_GRANULARITY 50 258 /* The min bandwidth weight is 1. */ 259 #define I40E_QOS_BW_WEIGHT_MIN 1 260 /* The max bandwidth weight is 127. */ 261 #define I40E_QOS_BW_WEIGHT_MAX 127 262 /* The max queue region index is 7. */ 263 #define I40E_REGION_MAX_INDEX 7 264 265 #define I40E_MAX_PERCENT 100 266 #define I40E_DEFAULT_DCB_APP_NUM 1 267 #define I40E_DEFAULT_DCB_APP_PRIO 3 268 269 #define I40E_FDIR_PRG_PKT_CNT 128 270 271 /* 272 * Struct to store flow created. 273 */ 274 struct rte_flow { 275 TAILQ_ENTRY(rte_flow) node; 276 enum rte_filter_type filter_type; 277 void *rule; 278 }; 279 280 /** 281 * The overhead from MTU to max frame size. 282 * Considering QinQ packet, the VLAN tag needs to be counted twice. 283 */ 284 #define I40E_ETH_OVERHEAD \ 285 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) 286 287 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) 288 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) 289 290 struct i40e_adapter; 291 struct rte_pci_driver; 292 293 /** 294 * MAC filter type 295 */ 296 enum i40e_mac_filter_type { 297 I40E_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */ 298 I40E_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */ 299 I40E_MAC_HASH_MATCH, /**< hash match of MAC addr. */ 300 /** hash match of MAC addr and exact match of VLAN ID. */ 301 I40E_MACVLAN_HASH_MATCH, 302 }; 303 304 /** 305 * MAC filter structure 306 */ 307 struct i40e_mac_filter_info { 308 enum i40e_mac_filter_type filter_type; 309 struct rte_ether_addr mac_addr; 310 }; 311 312 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); 313 314 /* MAC filter list structure */ 315 struct i40e_mac_filter { 316 TAILQ_ENTRY(i40e_mac_filter) next; 317 struct i40e_mac_filter_info mac_info; 318 }; 319 320 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); 321 322 struct i40e_vsi; 323 324 /* VSI list structure */ 325 struct i40e_vsi_list { 326 TAILQ_ENTRY(i40e_vsi_list) list; 327 struct i40e_vsi *vsi; 328 }; 329 330 struct i40e_rx_queue; 331 struct i40e_tx_queue; 332 333 /* Bandwidth limit information */ 334 struct i40e_bw_info { 335 uint16_t bw_limit; /* BW Limit (0 = disabled) */ 336 uint8_t bw_max; /* Max BW limit if enabled */ 337 338 /* Relative credits within same TC with respect to other VSIs or Comps */ 339 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 340 /* Bandwidth limit per TC */ 341 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; 342 /* Max bandwidth limit per TC */ 343 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; 344 }; 345 346 /* Structure that defines a VEB */ 347 struct i40e_veb { 348 struct i40e_vsi_list_head head; 349 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ 350 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ 351 uint16_t seid; /* The seid of VEB itself */ 352 uint16_t uplink_seid; /* The uplink seid of this VEB */ 353 uint16_t stats_idx; 354 struct i40e_eth_stats stats; 355 uint8_t enabled_tc; /* The traffic class enabled */ 356 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */ 357 struct i40e_bw_info bw_info; /* VEB bandwidth information */ 358 }; 359 360 /* i40e MACVLAN filter structure */ 361 struct i40e_macvlan_filter { 362 struct rte_ether_addr macaddr; 363 enum i40e_mac_filter_type filter_type; 364 uint16_t vlan_id; 365 }; 366 367 /* 368 * Structure that defines a VSI, associated with a adapter. 369 */ 370 struct i40e_vsi { 371 struct i40e_adapter *adapter; /* Backreference to associated adapter */ 372 struct i40e_aqc_vsi_properties_data info; /* VSI properties */ 373 374 struct i40e_eth_stats eth_stats_offset; 375 struct i40e_eth_stats eth_stats; 376 /* 377 * When drivers loaded, only a default main VSI exists. In case new VSI 378 * needs to add, HW needs to know the layout that VSIs are organized. 379 * Besides that, VSI isan element and can't switch packets, which needs 380 * to add new component VEB to perform switching. So, a new VSI needs 381 * to specify the uplink VSI (Parent VSI) before created. The 382 * uplink VSI will check whether it had a VEB to switch packets. If no, 383 * it will try to create one. Then, uplink VSI will move the new VSI 384 * into its' sib_vsi_list to manage all the downlink VSI. 385 * sib_vsi_list: the VSI list that shared the same uplink VSI. 386 * parent_vsi : the uplink VSI. It's NULL for main VSI. 387 * veb : the VEB associates with the VSI. 388 */ 389 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ 390 struct i40e_vsi *parent_vsi; 391 struct i40e_veb *veb; /* Associated veb, could be null */ 392 struct i40e_veb *floating_veb; /* Associated floating veb */ 393 bool offset_loaded; 394 enum i40e_vsi_type type; /* VSI types */ 395 uint16_t vlan_num; /* Total VLAN number */ 396 uint16_t mac_num; /* Total mac number */ 397 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ 398 struct i40e_mac_filter_list mac_list; /* macvlan filter list */ 399 /* specific VSI-defined parameters, SRIOV stored the vf_id */ 400 uint32_t user_param; 401 uint16_t seid; /* The seid of VSI itself */ 402 uint16_t uplink_seid; /* The uplink seid of this VSI */ 403 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ 404 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ 405 uint16_t max_macaddrs; /* Maximum number of MAC addresses */ 406 uint16_t base_queue; /* The first queue index of this VSI */ 407 /* 408 * The offset to visit VSI related register, assigned by HW when 409 * creating VSI 410 */ 411 uint16_t vsi_id; 412 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ 413 uint16_t nb_msix; /* The max number of msix vector */ 414 uint8_t enabled_tc; /* The traffic class enabled */ 415 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ 416 uint8_t vlan_filter_on; /* The VLAN filter enabled */ 417 struct i40e_bw_info bw_info; /* VSI bandwidth information */ 418 uint64_t prev_rx_bytes; 419 uint64_t prev_tx_bytes; 420 }; 421 422 struct pool_entry { 423 LIST_ENTRY(pool_entry) next; 424 uint16_t base; 425 uint16_t len; 426 }; 427 428 LIST_HEAD(res_list, pool_entry); 429 430 struct i40e_res_pool_info { 431 uint32_t base; /* Resource start index */ 432 uint32_t num_alloc; /* Allocated resource number */ 433 uint32_t num_free; /* Total available resource number */ 434 struct res_list alloc_list; /* Allocated resource list */ 435 struct res_list free_list; /* Available resource list */ 436 }; 437 438 enum I40E_VF_STATE { 439 I40E_VF_INACTIVE = 0, 440 I40E_VF_INRESET, 441 I40E_VF_ININIT, 442 I40E_VF_ACTIVE, 443 }; 444 445 /* 446 * Structure to store private data for PF host. 447 */ 448 struct i40e_pf_vf { 449 struct i40e_pf *pf; 450 struct i40e_vsi *vsi; 451 enum I40E_VF_STATE state; /* The number of queue pairs available */ 452 uint16_t vf_idx; /* VF index in pf->vfs */ 453 uint16_t lan_nb_qps; /* Actual queues allocated */ 454 uint16_t reset_cnt; /* Total vf reset times */ 455 struct rte_ether_addr mac_addr; /* Default MAC address */ 456 /* version of the virtchnl from VF */ 457 struct virtchnl_version_info version; 458 uint32_t request_caps; /* offload caps requested from VF */ 459 uint64_t num_mdd_events; /* num of mdd events detected */ 460 461 /* 462 * Variables for store the arrival timestamp of VF messages. 463 * If the timestamp of latest message stored at 464 * `msg_timestamps[index % max]` then the timestamp of 465 * earliest message stored at `msg_time[(index + 1) % max]`. 466 * When a new message come, the timestamp of this message 467 * will be stored at `msg_timestamps[(index + 1) % max]` and the 468 * earliest message timestamp is at 469 * `msg_timestamps[(index + 2) % max]` now... 470 */ 471 uint32_t msg_index; 472 uint64_t *msg_timestamps; 473 474 /* cycle of stop ignoring VF message */ 475 uint64_t ignore_end_cycle; 476 }; 477 478 /* 479 * Structure to store private data for flow control. 480 */ 481 struct i40e_fc_conf { 482 uint16_t pause_time; /* Flow control pause timer */ 483 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ 484 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; 485 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ 486 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; 487 }; 488 489 /* 490 * Structure to store private data for VMDQ instance 491 */ 492 struct i40e_vmdq_info { 493 struct i40e_pf *pf; 494 struct i40e_vsi *vsi; 495 }; 496 497 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 498 #define I40E_MAX_FLX_SOURCE_OFF 480 499 #define NONUSE_FLX_PIT_DEST_OFF 63 500 #define NONUSE_FLX_PIT_FSIZE 1 501 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50 502 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \ 503 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 504 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \ 505 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 506 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \ 507 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \ 508 NONUSE_FLX_PIT_DEST_OFF : \ 509 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \ 510 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 511 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)) 512 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF)) 513 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off)) 514 #define I40E_FDIR_IPv6_TC_OFFSET 20 515 516 /* A structure used to define the input for GTP flow */ 517 struct i40e_gtp_flow { 518 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */ 519 uint8_t msg_type; /* Message type. */ 520 uint32_t teid; /* TEID in big endian. */ 521 }; 522 523 /* A structure used to define the input for GTP IPV4 flow */ 524 struct i40e_gtp_ipv4_flow { 525 struct i40e_gtp_flow gtp; 526 struct rte_eth_ipv4_flow ip4; 527 }; 528 529 /* A structure used to define the input for GTP IPV6 flow */ 530 struct i40e_gtp_ipv6_flow { 531 struct i40e_gtp_flow gtp; 532 struct rte_eth_ipv6_flow ip6; 533 }; 534 535 /* A structure used to define the input for ESP IPV4 flow */ 536 struct i40e_esp_ipv4_flow { 537 struct rte_eth_ipv4_flow ipv4; 538 uint32_t spi; /* SPI in big endian. */ 539 }; 540 541 /* A structure used to define the input for ESP IPV6 flow */ 542 struct i40e_esp_ipv6_flow { 543 struct rte_eth_ipv6_flow ipv6; 544 uint32_t spi; /* SPI in big endian. */ 545 }; 546 /* A structure used to define the input for ESP IPV4 UDP flow */ 547 struct i40e_esp_ipv4_udp_flow { 548 struct rte_eth_udpv4_flow udp; 549 uint32_t spi; /* SPI in big endian. */ 550 }; 551 552 /* A structure used to define the input for ESP IPV6 UDP flow */ 553 struct i40e_esp_ipv6_udp_flow { 554 struct rte_eth_udpv6_flow udp; 555 uint32_t spi; /* SPI in big endian. */ 556 }; 557 558 /* A structure used to define the input for raw type flow */ 559 struct i40e_raw_flow { 560 uint16_t pctype; 561 void *packet; 562 uint32_t length; 563 }; 564 565 /* A structure used to define the input for L2TPv3 over IPv4 flow */ 566 struct i40e_ipv4_l2tpv3oip_flow { 567 struct rte_eth_ipv4_flow ip4; 568 uint32_t session_id; /* Session ID in big endian. */ 569 }; 570 571 /* A structure used to define the input for L2TPv3 over IPv6 flow */ 572 struct i40e_ipv6_l2tpv3oip_flow { 573 struct rte_eth_ipv6_flow ip6; 574 uint32_t session_id; /* Session ID in big endian. */ 575 }; 576 577 /* A structure used to define the input for l2 dst type flow */ 578 struct i40e_l2_flow { 579 struct rte_ether_addr dst; 580 struct rte_ether_addr src; 581 uint16_t ether_type; /**< Ether type in big endian */ 582 }; 583 584 /* 585 * A union contains the inputs for all types of flow 586 * items in flows need to be in big endian 587 */ 588 union i40e_fdir_flow { 589 struct i40e_l2_flow l2_flow; 590 struct rte_eth_udpv4_flow udp4_flow; 591 struct rte_eth_tcpv4_flow tcp4_flow; 592 struct rte_eth_sctpv4_flow sctp4_flow; 593 struct rte_eth_ipv4_flow ip4_flow; 594 struct rte_eth_udpv6_flow udp6_flow; 595 struct rte_eth_tcpv6_flow tcp6_flow; 596 struct rte_eth_sctpv6_flow sctp6_flow; 597 struct rte_eth_ipv6_flow ipv6_flow; 598 struct i40e_gtp_flow gtp_flow; 599 struct i40e_gtp_ipv4_flow gtp_ipv4_flow; 600 struct i40e_gtp_ipv6_flow gtp_ipv6_flow; 601 struct i40e_raw_flow raw_flow; 602 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow; 603 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow; 604 struct i40e_esp_ipv4_flow esp_ipv4_flow; 605 struct i40e_esp_ipv6_flow esp_ipv6_flow; 606 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow; 607 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow; 608 }; 609 610 enum i40e_fdir_ip_type { 611 I40E_FDIR_IPTYPE_IPV4, 612 I40E_FDIR_IPTYPE_IPV6, 613 }; 614 615 /** 616 * Structure to store flex pit for flow diretor. 617 */ 618 struct i40e_fdir_flex_pit { 619 uint8_t src_offset; /* offset in words from the beginning of payload */ 620 uint8_t size; /* size in words */ 621 uint8_t dst_offset; /* offset in words of flexible payload */ 622 }; 623 624 /* A structure used to contain extend input of flow */ 625 struct i40e_fdir_flow_ext { 626 uint16_t vlan_tci; 627 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 628 /* It is filled by the flexible payload to match. */ 629 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN]; 630 uint8_t raw_id; 631 uint8_t is_vf; /* 1 for VF, 0 for port dev */ 632 uint16_t dst_id; /* VF ID, available when is_vf is 1*/ 633 bool inner_ip; /* If there is inner ip */ 634 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ 635 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */ 636 bool customized_pctype; /* If customized pctype is used */ 637 bool pkt_template; /* If raw packet template is used */ 638 bool is_udp; /* ipv4|ipv6 udp flow */ 639 enum i40e_flxpld_layer_idx layer_idx; 640 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 641 bool is_flex_flow; 642 }; 643 644 /* A structure used to define the input for a flow director filter entry */ 645 struct i40e_fdir_input { 646 enum i40e_filter_pctype pctype; 647 union i40e_fdir_flow flow; 648 /* Flow fields to match, dependent on flow_type */ 649 struct i40e_fdir_flow_ext flow_ext; 650 /* Additional fields to match */ 651 }; 652 653 /* Behavior will be taken if FDIR match */ 654 enum i40e_fdir_behavior { 655 I40E_FDIR_ACCEPT = 0, 656 I40E_FDIR_REJECT, 657 I40E_FDIR_PASSTHRU, 658 }; 659 660 /* Flow director report status 661 * It defines what will be reported if FDIR entry is matched. 662 */ 663 enum i40e_fdir_status { 664 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */ 665 I40E_FDIR_REPORT_ID, /* Only report FD ID. */ 666 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */ 667 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */ 668 }; 669 670 /* A structure used to define an action when match FDIR packet filter. */ 671 struct i40e_fdir_action { 672 uint16_t rx_queue; /* Queue assigned to if FDIR match. */ 673 enum i40e_fdir_behavior behavior; /* Behavior will be taken */ 674 enum i40e_fdir_status report_status; /* Status report option */ 675 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or 676 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 677 * flex bytes start from in flexible payload. 678 */ 679 uint8_t flex_off; 680 }; 681 682 /* A structure used to define the flow director filter entry by filter_ctrl API 683 * It supports RTE_ETH_FILTER_FDIR data representation. 684 */ 685 struct i40e_fdir_filter_conf { 686 uint32_t soft_id; 687 /* ID, an unique value is required when deal with FDIR entry */ 688 struct i40e_fdir_input input; /* Input set */ 689 struct i40e_fdir_action action; /* Action taken when match */ 690 }; 691 692 struct i40e_fdir_flex_mask { 693 uint8_t word_mask; /**< Bit i enables word i of flexible payload */ 694 uint8_t nb_bitmask; 695 struct { 696 uint8_t offset; 697 uint16_t mask; 698 } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; 699 }; 700 701 #define I40E_FILTER_PCTYPE_INVALID 0 702 #define I40E_FILTER_PCTYPE_MAX 64 703 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8) 704 705 struct i40e_fdir_filter { 706 TAILQ_ENTRY(i40e_fdir_filter) rules; 707 struct i40e_fdir_filter_conf fdir; 708 }; 709 710 /* fdir memory pool entry */ 711 struct i40e_fdir_entry { 712 struct rte_flow flow; 713 uint32_t idx; 714 }; 715 716 /* pre-allocated fdir memory pool */ 717 struct i40e_fdir_flow_pool { 718 /* a bitmap to manage the fdir pool */ 719 struct rte_bitmap *bitmap; 720 /* the size the pool is pf->fdir->fdir_space_size */ 721 struct i40e_fdir_entry *pool; 722 }; 723 724 #define FLOW_TO_FLOW_BITMAP(f) \ 725 container_of((f), struct i40e_fdir_entry, flow) 726 727 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter); 728 /* 729 * A structure used to define fields of a FDIR related info. 730 */ 731 struct i40e_fdir_info { 732 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ 733 uint16_t match_counter_index; /* Statistic counter index used for fdir*/ 734 struct i40e_tx_queue *txq; 735 struct i40e_rx_queue *rxq; 736 void *prg_pkt[I40E_FDIR_PRG_PKT_CNT]; /* memory for fdir program packet */ 737 uint64_t dma_addr[I40E_FDIR_PRG_PKT_CNT]; /* physic address of packet memory*/ 738 /* 739 * txq available buffer counter, indicates how many available buffers 740 * for fdir programming, initialized as I40E_FDIR_PRG_PKT_CNT 741 */ 742 int txq_available_buf_count; 743 744 /* input set bits for each pctype */ 745 uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; 746 /* 747 * the rule how bytes stream is extracted as flexible payload 748 * for each payload layer, the setting can up to three elements 749 */ 750 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; 751 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; 752 753 struct i40e_fdir_filter_list fdir_list; 754 struct i40e_fdir_filter **hash_map; 755 struct rte_hash *hash_table; 756 /* An array to store the inserted rules input */ 757 struct i40e_fdir_filter *fdir_filter_array; 758 759 /* 760 * Priority ordering at filter invalidation(destroying a flow) between 761 * "best effort" space and "guaranteed" space. 762 * 763 * 0 = At filter invalidation, the hardware first tries to increment the 764 * "best effort" space. The "guaranteed" space is incremented only when 765 * the global "best effort" space is at it max value or the "best effort" 766 * space of the PF is at its max value. 767 * 1 = At filter invalidation, the hardware first tries to increment its 768 * "guaranteed" space. The "best effort" space is incremented only when 769 * it is already at its max value. 770 */ 771 uint32_t fdir_invalprio; 772 /* the total size of the fdir, this number is the sum of the guaranteed + 773 * shared space 774 */ 775 uint32_t fdir_space_size; 776 /* the actual number of the fdir rules in hardware, initialized as 0 */ 777 uint32_t fdir_actual_cnt; 778 /* the free guaranteed space of the fdir */ 779 uint32_t fdir_guarantee_free_space; 780 /* the fdir total guaranteed space */ 781 uint32_t fdir_guarantee_total_space; 782 /* the pre-allocated pool of the rte_flow */ 783 struct i40e_fdir_flow_pool fdir_flow_pool; 784 785 /* Mark if flex pit and mask is set */ 786 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER]; 787 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; 788 789 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */ 790 791 uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER]; 792 }; 793 794 /* Ethertype filter number HW supports */ 795 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768 796 797 /* Ethertype filter struct */ 798 struct i40e_ethertype_filter_input { 799 struct rte_ether_addr mac_addr; /* Mac address to match */ 800 uint16_t ether_type; /* Ether type to match */ 801 }; 802 803 struct i40e_ethertype_filter { 804 TAILQ_ENTRY(i40e_ethertype_filter) rules; 805 struct i40e_ethertype_filter_input input; 806 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */ 807 uint16_t queue; /* Queue assigned to when match */ 808 }; 809 810 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter); 811 812 struct i40e_ethertype_rule { 813 struct i40e_ethertype_filter_list ethertype_list; 814 struct i40e_ethertype_filter **hash_map; 815 struct rte_hash *hash_table; 816 }; 817 818 /* queue region info */ 819 struct i40e_queue_region_info { 820 /* the region id for this configuration */ 821 uint8_t region_id; 822 /* the start queue index for this region */ 823 uint8_t queue_start_index; 824 /* the total queue number of this queue region */ 825 uint8_t queue_num; 826 /* the total number of user priority for this region */ 827 uint8_t user_priority_num; 828 /* the packet's user priority for this region */ 829 uint8_t user_priority[I40E_MAX_USER_PRIORITY]; 830 /* the total number of flowtype for this region */ 831 uint8_t flowtype_num; 832 /** 833 * the pctype or hardware flowtype of packet, 834 * the specific index for each type has been defined 835 * in file i40e_type.h as enum i40e_filter_pctype. 836 */ 837 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX]; 838 }; 839 840 struct i40e_queue_regions { 841 /* the total number of queue region for this port */ 842 uint16_t queue_region_number; 843 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1]; 844 }; 845 846 struct i40e_rss_pattern_info { 847 uint8_t action_flag; 848 uint64_t types; 849 }; 850 851 /* Tunnel filter number HW supports */ 852 #define I40E_MAX_TUNNEL_FILTER_NUM 400 853 854 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 855 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 856 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29 857 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30 858 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8 859 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9 860 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10 861 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11 862 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12 863 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10 864 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11 865 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12 866 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13 867 #define I40E_AQC_NEW_TR_21 21 868 #define I40E_AQC_NEW_TR_22 22 869 870 enum i40e_tunnel_iptype { 871 I40E_TUNNEL_IPTYPE_IPV4, 872 I40E_TUNNEL_IPTYPE_IPV6, 873 }; 874 875 /* Tunnel filter struct */ 876 struct i40e_tunnel_filter_input { 877 uint8_t outer_mac[6]; /* Outer mac address to match */ 878 uint8_t inner_mac[6]; /* Inner mac address to match */ 879 uint16_t inner_vlan; /* Inner vlan address to match */ 880 enum i40e_tunnel_iptype ip_type; 881 uint16_t flags; /* Filter type flag */ 882 uint32_t tenant_id; /* Tenant id to match */ 883 uint16_t general_fields[32]; /* Big buffer */ 884 }; 885 886 struct i40e_tunnel_filter { 887 TAILQ_ENTRY(i40e_tunnel_filter) rules; 888 struct i40e_tunnel_filter_input input; 889 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */ 890 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */ 891 uint16_t queue; /* Queue assigned to when match */ 892 }; 893 894 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter); 895 896 struct i40e_tunnel_rule { 897 struct i40e_tunnel_filter_list tunnel_list; 898 struct i40e_tunnel_filter **hash_map; 899 struct rte_hash *hash_table; 900 }; 901 902 /** 903 * Tunnel type. 904 */ 905 enum i40e_tunnel_type { 906 I40E_TUNNEL_TYPE_NONE = 0, 907 I40E_TUNNEL_TYPE_VXLAN, 908 I40E_TUNNEL_TYPE_GENEVE, 909 I40E_TUNNEL_TYPE_TEREDO, 910 I40E_TUNNEL_TYPE_NVGRE, 911 I40E_TUNNEL_TYPE_IP_IN_GRE, 912 I40E_L2_TUNNEL_TYPE_E_TAG, 913 I40E_TUNNEL_TYPE_MPLSoUDP, 914 I40E_TUNNEL_TYPE_MPLSoGRE, 915 I40E_TUNNEL_TYPE_QINQ, 916 I40E_TUNNEL_TYPE_GTPC, 917 I40E_TUNNEL_TYPE_GTPU, 918 I40E_TUNNEL_TYPE_ESPoUDP, 919 I40E_TUNNEL_TYPE_ESPoIP, 920 I40E_CLOUD_TYPE_UDP, 921 I40E_CLOUD_TYPE_TCP, 922 I40E_CLOUD_TYPE_SCTP, 923 I40E_TUNNEL_TYPE_MAX, 924 }; 925 926 /** 927 * L4 port type. 928 */ 929 enum i40e_l4_port_type { 930 I40E_L4_PORT_TYPE_SRC = 0, 931 I40E_L4_PORT_TYPE_DST, 932 }; 933 934 /** 935 * Tunneling Packet filter configuration. 936 */ 937 struct i40e_tunnel_filter_conf { 938 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */ 939 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */ 940 uint16_t inner_vlan; /**< Inner VLAN to match. */ 941 uint32_t outer_vlan; /**< Outer VLAN to match */ 942 enum i40e_tunnel_iptype ip_type; /**< IP address type. */ 943 /** 944 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP 945 * is set in filter_type, or inner destination IP address to match 946 * if ETH_TUNNEL_FILTER_IIP is set in filter_type. 947 */ 948 union { 949 uint32_t ipv4_addr; /**< IPv4 address in big endian. */ 950 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */ 951 } ip_addr; 952 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */ 953 uint16_t filter_type; 954 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */ 955 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */ 956 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */ 957 uint16_t queue_id; /**< Queue assigned to if match. */ 958 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */ 959 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */ 960 }; 961 962 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 963 #define I40E_MAX_MIRROR_RULES 64 964 /* 965 * Mirror rule structure 966 */ 967 struct i40e_mirror_rule { 968 TAILQ_ENTRY(i40e_mirror_rule) rules; 969 uint8_t rule_type; 970 uint16_t index; /* the sw index of mirror rule */ 971 uint16_t id; /* the rule id assigned by firmware */ 972 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ 973 uint16_t num_entries; 974 /* the info stores depend on the rule type. 975 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. 976 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. 977 */ 978 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; 979 }; 980 981 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); 982 983 TAILQ_HEAD(i40e_flow_list, rte_flow); 984 985 /* Struct to store Traffic Manager shaper profile. */ 986 struct i40e_tm_shaper_profile { 987 TAILQ_ENTRY(i40e_tm_shaper_profile) node; 988 uint32_t shaper_profile_id; 989 uint32_t reference_count; 990 struct rte_tm_shaper_params profile; 991 }; 992 993 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile); 994 995 /* node type of Traffic Manager */ 996 enum i40e_tm_node_type { 997 I40E_TM_NODE_TYPE_PORT, 998 I40E_TM_NODE_TYPE_TC, 999 I40E_TM_NODE_TYPE_QUEUE, 1000 I40E_TM_NODE_TYPE_MAX, 1001 }; 1002 1003 /* Struct to store Traffic Manager node configuration. */ 1004 struct i40e_tm_node { 1005 TAILQ_ENTRY(i40e_tm_node) node; 1006 uint32_t id; 1007 uint32_t priority; 1008 uint32_t weight; 1009 uint32_t reference_count; 1010 struct i40e_tm_node *parent; 1011 struct i40e_tm_shaper_profile *shaper_profile; 1012 struct rte_tm_node_params params; 1013 }; 1014 1015 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node); 1016 1017 /* Struct to store all the Traffic Manager configuration. */ 1018 struct i40e_tm_conf { 1019 struct i40e_shaper_profile_list shaper_profile_list; 1020 struct i40e_tm_node *root; /* root node - port */ 1021 struct i40e_tm_node_list tc_list; /* node list for all the TCs */ 1022 struct i40e_tm_node_list queue_list; /* node list for all the queues */ 1023 /** 1024 * The number of added TC nodes. 1025 * It should be no more than the TC number of this port. 1026 */ 1027 uint32_t nb_tc_node; 1028 /** 1029 * The number of added queue nodes. 1030 * It should be no more than the queue number of this port. 1031 */ 1032 uint32_t nb_queue_node; 1033 /** 1034 * This flag is used to check if APP can change the TM node 1035 * configuration. 1036 * When it's true, means the configuration is applied to HW, 1037 * APP should not change the configuration. 1038 * As we don't support on-the-fly configuration, when starting 1039 * the port, APP should call the hierarchy_commit API to set this 1040 * flag to true. When stopping the port, this flag should be set 1041 * to false. 1042 */ 1043 bool committed; 1044 }; 1045 1046 enum i40e_new_pctype { 1047 I40E_CUSTOMIZED_GTPC = 0, 1048 I40E_CUSTOMIZED_GTPU_IPV4, 1049 I40E_CUSTOMIZED_GTPU_IPV6, 1050 I40E_CUSTOMIZED_GTPU, 1051 I40E_CUSTOMIZED_IPV4_L2TPV3, 1052 I40E_CUSTOMIZED_IPV6_L2TPV3, 1053 I40E_CUSTOMIZED_ESP_IPV4, 1054 I40E_CUSTOMIZED_ESP_IPV6, 1055 I40E_CUSTOMIZED_ESP_IPV4_UDP, 1056 I40E_CUSTOMIZED_ESP_IPV6_UDP, 1057 I40E_CUSTOMIZED_AH_IPV4, 1058 I40E_CUSTOMIZED_AH_IPV6, 1059 I40E_CUSTOMIZED_MAX, 1060 }; 1061 1062 #define I40E_FILTER_PCTYPE_INVALID 0 1063 struct i40e_customized_pctype { 1064 enum i40e_new_pctype index; /* Indicate which customized pctype */ 1065 uint8_t pctype; /* New pctype value */ 1066 bool valid; /* Check if it's valid */ 1067 }; 1068 1069 struct i40e_rte_flow_rss_conf { 1070 struct rte_flow_action_rss conf; /**< RSS parameters. */ 1071 1072 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ? 1073 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) * 1074 sizeof(uint32_t)]; /**< Hash key. */ 1075 uint16_t queue[ETH_RSS_RETA_SIZE_512]; /**< Queues indices to use. */ 1076 1077 bool symmetric_enable; /**< true, if enable symmetric */ 1078 uint64_t config_pctypes; /**< All PCTYPES with the flow */ 1079 uint64_t inset; /**< input sets */ 1080 1081 uint8_t region_priority; /**< queue region priority */ 1082 uint8_t region_queue_num; /**< region queue number */ 1083 uint16_t region_queue_start; /**< region queue start */ 1084 1085 uint32_t misc_reset_flags; 1086 #define I40E_HASH_FLOW_RESET_FLAG_FUNC 0x01UL 1087 #define I40E_HASH_FLOW_RESET_FLAG_KEY 0x02UL 1088 #define I40E_HASH_FLOW_RESET_FLAG_QUEUE 0x04UL 1089 #define I40E_HASH_FLOW_RESET_FLAG_REGION 0x08UL 1090 1091 /**< All PCTYPES that reset with the flow */ 1092 uint64_t reset_config_pctypes; 1093 /**< Symmetric function should reset on PCTYPES */ 1094 uint64_t reset_symmetric_pctypes; 1095 }; 1096 1097 /* RSS filter list structure */ 1098 struct i40e_rss_filter { 1099 TAILQ_ENTRY(i40e_rss_filter) next; 1100 struct i40e_rte_flow_rss_conf rss_filter_info; 1101 }; 1102 1103 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter); 1104 1105 struct i40e_vf_msg_cfg { 1106 /* maximal VF message during a statistic period */ 1107 uint32_t max_msg; 1108 1109 /* statistic period, in second */ 1110 uint32_t period; 1111 /* 1112 * If message statistics from a VF exceed the maximal limitation, 1113 * the PF will ignore any new message from that VF for 1114 * 'ignor_second' time. 1115 */ 1116 uint32_t ignore_second; 1117 }; 1118 1119 /* 1120 * Structure to store private data specific for PF instance. 1121 */ 1122 struct i40e_pf { 1123 struct i40e_adapter *adapter; /* The adapter this PF associate to */ 1124 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ 1125 uint16_t mac_seid; /* The seid of the MAC of this PF */ 1126 uint16_t main_vsi_seid; /* The seid of the main VSI */ 1127 uint16_t max_num_vsi; 1128 struct i40e_res_pool_info qp_pool; /*Queue pair pool */ 1129 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ 1130 1131 struct i40e_hw_port_stats stats_offset; 1132 struct i40e_hw_port_stats stats; 1133 /* internal packet statistics, it should be excluded from the total */ 1134 struct i40e_eth_stats internal_stats_offset; 1135 struct i40e_eth_stats internal_stats; 1136 bool offset_loaded; 1137 1138 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1139 struct rte_ether_addr dev_addr; /* PF device mac address */ 1140 uint64_t flags; /* PF feature flags */ 1141 /* All kinds of queue pair setting for different VSIs */ 1142 struct i40e_pf_vf *vfs; 1143 uint16_t vf_num; 1144 /* Each of below queue pairs should be power of 2 since it's the 1145 precondition after TC configuration applied */ 1146 uint16_t lan_nb_qp_max; 1147 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ 1148 uint16_t lan_qp_offset; 1149 uint16_t vmdq_nb_qp_max; 1150 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ 1151 uint16_t vmdq_qp_offset; 1152 uint16_t vf_nb_qp_max; 1153 uint16_t vf_nb_qps; /* The number of queue pairs of VF */ 1154 uint16_t vf_qp_offset; 1155 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ 1156 uint16_t fdir_qp_offset; 1157 1158 uint16_t hash_lut_size; /* The size of hash lookup table */ 1159 bool hash_filter_enabled; 1160 uint64_t hash_enabled_queues; 1161 /* input set bits for each pctype */ 1162 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; 1163 /* store VXLAN UDP ports */ 1164 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 1165 uint16_t vxlan_bitmap; /* Vxlan bit mask */ 1166 1167 /* VMDQ related info */ 1168 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ 1169 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ 1170 struct i40e_vmdq_info *vmdq; 1171 1172 struct i40e_fdir_info fdir; /* flow director info */ 1173 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */ 1174 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */ 1175 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */ 1176 struct i40e_queue_regions queue_region; /* queue region info */ 1177 struct i40e_fc_conf fc_conf; /* Flow control conf */ 1178 struct i40e_mirror_rule_list mirror_list; 1179 uint16_t nb_mirror_rule; /* The number of mirror rules */ 1180 bool floating_veb; /* The flag to use the floating VEB */ 1181 /* The floating enable flag for the specific VF */ 1182 bool floating_veb_list[I40E_MAX_VF]; 1183 struct i40e_flow_list flow_list; 1184 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */ 1185 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */ 1186 bool qinq_replace_flag; /* QINQ filter replace is done */ 1187 /* l4 port flag */ 1188 bool sport_replace_flag; /* Source port replace is done */ 1189 bool dport_replace_flag; /* Destination port replace is done */ 1190 struct i40e_tm_conf tm_conf; 1191 bool support_multi_driver; /* 1 - support multiple driver */ 1192 1193 /* Dynamic Device Personalization */ 1194 bool gtp_support; /* 1 - support GTP-C and GTP-U */ 1195 bool esp_support; /* 1 - support ESP SPI */ 1196 /* customer customized pctype */ 1197 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX]; 1198 /* Switch Domain Id */ 1199 uint16_t switch_domain_id; 1200 1201 struct i40e_vf_msg_cfg vf_msg_cfg; 1202 uint64_t prev_rx_bytes; 1203 uint64_t prev_tx_bytes; 1204 uint64_t internal_prev_rx_bytes; 1205 uint64_t internal_prev_tx_bytes; 1206 }; 1207 1208 enum pending_msg { 1209 PFMSG_LINK_CHANGE = 0x1, 1210 PFMSG_RESET_IMPENDING = 0x2, 1211 PFMSG_DRIVER_CLOSE = 0x4, 1212 }; 1213 1214 struct i40e_vsi_vlan_pvid_info { 1215 uint16_t on; /* Enable or disable pvid */ 1216 union { 1217 uint16_t pvid; /* Valid in case 'on' is set to set pvid */ 1218 struct { 1219 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, 1220 * while 'untagged' will reject untagged packets. 1221 */ 1222 uint8_t tagged; 1223 uint8_t untagged; 1224 } reject; 1225 } config; 1226 }; 1227 1228 struct i40e_vf_rx_queues { 1229 uint64_t rx_dma_addr; 1230 uint32_t rx_ring_len; 1231 uint32_t buff_size; 1232 }; 1233 1234 struct i40e_vf_tx_queues { 1235 uint64_t tx_dma_addr; 1236 uint32_t tx_ring_len; 1237 }; 1238 1239 /* 1240 * Structure to store private data specific for VF instance. 1241 */ 1242 struct i40e_vf { 1243 struct i40e_adapter *adapter; /* The adapter this VF associate to */ 1244 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ 1245 uint16_t num_queue_pairs; 1246 uint16_t max_pkt_len; /* Maximum packet length */ 1247 bool promisc_unicast_enabled; 1248 bool promisc_multicast_enabled; 1249 1250 rte_spinlock_t cmd_send_lock; 1251 uint32_t version_major; /* Major version number */ 1252 uint32_t version_minor; /* Minor version number */ 1253 uint16_t promisc_flags; /* Promiscuous setting */ 1254 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ 1255 1256 /* Multicast addrs */ 1257 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; 1258 uint16_t mc_addrs_num; /* Multicast mac addresses number */ 1259 1260 /* Event from pf */ 1261 bool dev_closed; 1262 bool link_up; 1263 enum virtchnl_link_speed link_speed; 1264 bool vf_reset; 1265 volatile uint32_t pend_cmd; /* pending command not finished yet */ 1266 int32_t cmd_retval; /* return value of the cmd response from PF */ 1267 u16 pend_msg; /* flags indicates events from pf not handled yet */ 1268 uint8_t *aq_resp; /* buffer to store the adminq response from PF */ 1269 1270 /* VSI info */ 1271 struct virtchnl_vf_resource *vf_res; /* All VSIs */ 1272 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */ 1273 struct i40e_vsi vsi; 1274 uint64_t flags; 1275 }; 1276 1277 #define I40E_MAX_PKT_TYPE 256 1278 #define I40E_FLOW_TYPE_MAX 64 1279 1280 /* 1281 * Structure to store private data for each PF/VF instance. 1282 */ 1283 struct i40e_adapter { 1284 /* Common for both PF and VF */ 1285 struct i40e_hw hw; 1286 struct rte_eth_dev *eth_dev; 1287 1288 /* Specific for PF or VF */ 1289 union { 1290 struct i40e_pf pf; 1291 struct i40e_vf vf; 1292 }; 1293 1294 /* For vector PMD */ 1295 bool rx_bulk_alloc_allowed; 1296 bool rx_vec_allowed; 1297 bool tx_simple_allowed; 1298 bool tx_vec_allowed; 1299 1300 /* For PTP */ 1301 struct rte_timecounter systime_tc; 1302 struct rte_timecounter rx_tstamp_tc; 1303 struct rte_timecounter tx_tstamp_tc; 1304 1305 /* ptype mapping table */ 1306 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned; 1307 /* flow type to pctype mapping table */ 1308 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned; 1309 uint64_t flow_types_mask; 1310 uint64_t pctypes_mask; 1311 1312 /* For devargs */ 1313 uint8_t use_latest_vec; 1314 1315 /* For RSS reta table update */ 1316 uint8_t rss_reta_updated; 1317 }; 1318 1319 /** 1320 * Strucute to store private data for each VF representor instance 1321 */ 1322 struct i40e_vf_representor { 1323 uint16_t switch_domain_id; 1324 /**< Virtual Function ID */ 1325 uint16_t vf_id; 1326 /**< Virtual Function ID */ 1327 struct i40e_adapter *adapter; 1328 /**< Private data store of assocaiated physical function */ 1329 struct i40e_eth_stats stats_offset; 1330 /**< Zero-point of VF statistics*/ 1331 }; 1332 1333 extern const struct rte_flow_ops i40e_flow_ops; 1334 1335 union i40e_filter_t { 1336 struct rte_eth_ethertype_filter ethertype_filter; 1337 struct i40e_fdir_filter_conf fdir_filter; 1338 struct rte_eth_tunnel_filter_conf tunnel_filter; 1339 struct i40e_tunnel_filter_conf consistent_tunnel_filter; 1340 struct i40e_rte_flow_rss_conf rss_conf; 1341 }; 1342 1343 typedef int (*parse_filter_t)(struct rte_eth_dev *dev, 1344 const struct rte_flow_attr *attr, 1345 const struct rte_flow_item pattern[], 1346 const struct rte_flow_action actions[], 1347 struct rte_flow_error *error, 1348 union i40e_filter_t *filter); 1349 struct i40e_valid_pattern { 1350 enum rte_flow_item_type *items; 1351 parse_filter_t parse_filter; 1352 }; 1353 1354 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); 1355 int i40e_vsi_release(struct i40e_vsi *vsi); 1356 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, 1357 enum i40e_vsi_type type, 1358 struct i40e_vsi *uplink_vsi, 1359 uint16_t user_param); 1360 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1361 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); 1362 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1363 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); 1364 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); 1365 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr); 1366 void i40e_update_vsi_stats(struct i40e_vsi *vsi); 1367 void i40e_pf_disable_irq0(struct i40e_hw *hw); 1368 void i40e_pf_enable_irq0(struct i40e_hw *hw); 1369 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1370 int i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx); 1371 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); 1372 void i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi); 1373 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 1374 struct i40e_vsi_vlan_pvid_info *info); 1375 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); 1376 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); 1377 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags); 1378 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags); 1379 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); 1380 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); 1381 int i40e_fdir_setup(struct i40e_pf *pf); 1382 void i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi); 1383 const struct rte_memzone *i40e_memzone_reserve(const char *name, 1384 uint32_t len, 1385 int socket_id); 1386 int i40e_fdir_configure(struct rte_eth_dev *dev); 1387 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on); 1388 void i40e_fdir_teardown(struct i40e_pf *pf); 1389 enum i40e_filter_pctype 1390 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, 1391 uint16_t flow_type); 1392 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 1393 enum i40e_filter_pctype pctype); 1394 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len); 1395 void i40e_fdir_info_get(struct rte_eth_dev *dev, 1396 struct rte_eth_fdir_info *fdir); 1397 void i40e_fdir_stats_get(struct rte_eth_dev *dev, 1398 struct rte_eth_fdir_stats *stat); 1399 int i40e_select_filter_input_set(struct i40e_hw *hw, 1400 struct rte_eth_input_set_conf *conf, 1401 enum rte_filter_type filter); 1402 void i40e_fdir_filter_restore(struct i40e_pf *pf); 1403 int i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set, 1404 uint32_t pctype, bool add); 1405 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, 1406 uint32_t retval, uint8_t *msg, 1407 uint16_t msglen); 1408 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1409 struct rte_eth_rxq_info *qinfo); 1410 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1411 struct rte_eth_txq_info *qinfo); 1412 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1413 struct rte_eth_burst_mode *mode); 1414 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id, 1415 struct rte_eth_burst_mode *mode); 1416 struct i40e_ethertype_filter * 1417 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 1418 const struct i40e_ethertype_filter_input *input); 1419 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 1420 struct i40e_ethertype_filter_input *input); 1421 int i40e_sw_fdir_filter_del(struct i40e_pf *pf, 1422 struct i40e_fdir_input *input); 1423 struct i40e_tunnel_filter * 1424 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 1425 const struct i40e_tunnel_filter_input *input); 1426 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 1427 struct i40e_tunnel_filter_input *input); 1428 uint64_t i40e_get_default_input_set(uint16_t pctype); 1429 int i40e_ethertype_filter_set(struct i40e_pf *pf, 1430 struct rte_eth_ethertype_filter *filter, 1431 bool add); 1432 struct rte_flow * 1433 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info); 1434 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info, 1435 struct rte_flow *flow); 1436 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, 1437 const struct i40e_fdir_filter_conf *filter, 1438 bool add); 1439 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 1440 struct rte_eth_tunnel_filter_conf *tunnel_filter, 1441 uint8_t add); 1442 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 1443 struct i40e_tunnel_filter_conf *tunnel_filter, 1444 uint8_t add); 1445 int i40e_fdir_flush(struct rte_eth_dev *dev); 1446 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 1447 struct i40e_macvlan_filter *mv_f, 1448 int num, struct rte_ether_addr *addr); 1449 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 1450 struct i40e_macvlan_filter *filter, 1451 int total); 1452 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on); 1453 int i40e_add_macvlan_filters(struct i40e_vsi *vsi, 1454 struct i40e_macvlan_filter *filter, 1455 int total); 1456 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv); 1457 bool is_i40e_supported(struct rte_eth_dev *dev); 1458 bool is_i40evf_supported(struct rte_eth_dev *dev); 1459 void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, 1460 uint8_t enable); 1461 int i40e_validate_input_set(enum i40e_filter_pctype pctype, 1462 enum rte_filter_type filter, uint64_t inset); 1463 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, 1464 uint8_t nb_elem); 1465 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input); 1466 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val); 1467 void i40e_check_write_global_reg(struct i40e_hw *hw, 1468 uint32_t addr, uint32_t val); 1469 1470 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops); 1471 void i40e_tm_conf_init(struct rte_eth_dev *dev); 1472 void i40e_tm_conf_uninit(struct rte_eth_dev *dev); 1473 struct i40e_customized_pctype* 1474 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index); 1475 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 1476 uint32_t pkg_size, 1477 enum rte_pmd_i40e_package_op op); 1478 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb); 1479 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, 1480 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on); 1481 void i40e_init_queue_region_conf(struct rte_eth_dev *dev); 1482 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw); 1483 void i40e_pf_disable_rss(struct i40e_pf *pf); 1484 int i40e_pf_calc_configured_queues_num(struct i40e_pf *pf); 1485 int i40e_pf_reset_rss_reta(struct i40e_pf *pf); 1486 int i40e_pf_reset_rss_key(struct i40e_pf *pf); 1487 int i40e_pf_config_rss(struct i40e_pf *pf); 1488 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len); 1489 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size); 1490 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params); 1491 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev); 1492 1493 #define I40E_DEV_TO_PCI(eth_dev) \ 1494 RTE_DEV_TO_PCI((eth_dev)->device) 1495 1496 /* I40E_DEV_PRIVATE_TO */ 1497 #define I40E_DEV_PRIVATE_TO_PF(adapter) \ 1498 (&((struct i40e_adapter *)adapter)->pf) 1499 #define I40E_DEV_PRIVATE_TO_HW(adapter) \ 1500 (&((struct i40e_adapter *)adapter)->hw) 1501 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ 1502 ((struct i40e_adapter *)adapter) 1503 1504 /* I40EVF_DEV_PRIVATE_TO */ 1505 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ 1506 (&((struct i40e_adapter *)adapter)->vf) 1507 1508 static inline struct i40e_vsi * 1509 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) 1510 { 1511 struct i40e_hw *hw; 1512 1513 if (!adapter) 1514 return NULL; 1515 1516 hw = I40E_DEV_PRIVATE_TO_HW(adapter); 1517 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { 1518 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); 1519 return &vf->vsi; 1520 } else { 1521 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); 1522 return pf->main_vsi; 1523 } 1524 } 1525 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ 1526 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) 1527 1528 /* I40E_VSI_TO */ 1529 #define I40E_VSI_TO_HW(vsi) \ 1530 (&(((struct i40e_vsi *)vsi)->adapter->hw)) 1531 #define I40E_VSI_TO_PF(vsi) \ 1532 (&(((struct i40e_vsi *)vsi)->adapter->pf)) 1533 #define I40E_VSI_TO_VF(vsi) \ 1534 (&(((struct i40e_vsi *)vsi)->adapter->vf)) 1535 #define I40E_VSI_TO_DEV_DATA(vsi) \ 1536 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) 1537 #define I40E_VSI_TO_ETH_DEV(vsi) \ 1538 (((struct i40e_vsi *)vsi)->adapter->eth_dev) 1539 1540 /* I40E_PF_TO */ 1541 #define I40E_PF_TO_HW(pf) \ 1542 (&(((struct i40e_pf *)pf)->adapter->hw)) 1543 #define I40E_PF_TO_ADAPTER(pf) \ 1544 ((struct i40e_adapter *)pf->adapter) 1545 1546 /* I40E_VF_TO */ 1547 #define I40E_VF_TO_HW(vf) \ 1548 (&(((struct i40e_vf *)vf)->adapter->hw)) 1549 1550 static inline void 1551 i40e_init_adminq_parameter(struct i40e_hw *hw) 1552 { 1553 hw->aq.num_arq_entries = I40E_AQ_LEN; 1554 hw->aq.num_asq_entries = I40E_AQ_LEN; 1555 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; 1556 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; 1557 } 1558 1559 static inline int 1560 i40e_align_floor(int n) 1561 { 1562 if (n == 0) 1563 return 0; 1564 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); 1565 } 1566 1567 static inline uint16_t 1568 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv) 1569 { 1570 uint16_t interval = 0; 1571 1572 if (is_multi_drv) { 1573 interval = I40E_QUEUE_ITR_INTERVAL_MAX; 1574 } else { 1575 if (is_pf) 1576 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; 1577 else 1578 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT; 1579 } 1580 1581 /* Convert to hardware count, as writing each 1 represents 2 us */ 1582 return interval / 2; 1583 } 1584 1585 #define I40E_VALID_FLOW(flow_type) \ 1586 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ 1587 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ 1588 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ 1589 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ 1590 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ 1591 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ 1592 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ 1593 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ 1594 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ 1595 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ 1596 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) 1597 1598 #define I40E_VALID_PCTYPE_X722(pctype) \ 1599 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1600 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1601 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ 1602 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1603 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ 1604 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ 1605 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1606 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1607 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1608 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1609 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ 1610 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ 1611 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1612 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ 1613 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1614 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1615 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1616 1617 #define I40E_VALID_PCTYPE(pctype) \ 1618 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ 1619 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ 1620 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ 1621 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ 1622 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ 1623 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ 1624 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ 1625 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ 1626 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ 1627 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ 1628 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) 1629 1630 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ 1631 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ 1632 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ 1633 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ 1634 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ 1635 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ 1636 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) 1637 1638 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ 1639 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ 1640 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ 1641 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ 1642 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \ 1643 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \ 1644 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC)) 1645 1646 #endif /* _I40E_ETHDEV_H_ */ 1647