1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <unistd.h> 10 #include <stdarg.h> 11 #include <inttypes.h> 12 #include <assert.h> 13 14 #include <rte_common.h> 15 #include <rte_eal.h> 16 #include <rte_string_fns.h> 17 #include <rte_pci.h> 18 #include <rte_bus_pci.h> 19 #include <rte_ether.h> 20 #include <rte_ethdev_driver.h> 21 #include <rte_ethdev_pci.h> 22 #include <rte_memzone.h> 23 #include <rte_malloc.h> 24 #include <rte_memcpy.h> 25 #include <rte_alarm.h> 26 #include <rte_dev.h> 27 #include <rte_tailq.h> 28 #include <rte_hash_crc.h> 29 30 #include "i40e_logs.h" 31 #include "base/i40e_prototype.h" 32 #include "base/i40e_adminq_cmd.h" 33 #include "base/i40e_type.h" 34 #include "base/i40e_register.h" 35 #include "base/i40e_dcb.h" 36 #include "i40e_ethdev.h" 37 #include "i40e_rxtx.h" 38 #include "i40e_pf.h" 39 #include "i40e_regs.h" 40 #include "rte_pmd_i40e.h" 41 42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" 43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" 44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" 45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" 46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" 47 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg" 48 49 #define I40E_CLEAR_PXE_WAIT_MS 200 50 51 /* Maximun number of capability elements */ 52 #define I40E_MAX_CAP_ELE_NUM 128 53 54 /* Wait count and interval */ 55 #define I40E_CHK_Q_ENA_COUNT 1000 56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000 57 58 /* Maximun number of VSI */ 59 #define I40E_MAX_NUM_VSIS (384UL) 60 61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */ 62 63 /* Flow control default timer */ 64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU 65 66 /* Flow control enable fwd bit */ 67 #define I40E_PRTMAC_FWD_CTRL 0x00000001 68 69 /* Receive Packet Buffer size */ 70 #define I40E_RXPBSIZE (968 * 1024) 71 72 /* Kilobytes shift */ 73 #define I40E_KILOSHIFT 10 74 75 /* Flow control default high water */ 76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT) 77 78 /* Flow control default low water */ 79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT) 80 81 /* Receive Average Packet Size in Byte*/ 82 #define I40E_PACKET_AVERAGE_SIZE 128 83 84 /* Mask of PF interrupt causes */ 85 #define I40E_PFINT_ICR0_ENA_MASK ( \ 86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \ 87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \ 88 I40E_PFINT_ICR0_ENA_GRST_MASK | \ 89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \ 90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \ 91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \ 92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \ 93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \ 94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK) 95 96 #define I40E_FLOW_TYPES ( \ 97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \ 98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ 99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ 100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ 101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ 102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \ 103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ 104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ 105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ 106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \ 107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD)) 108 109 /* Additional timesync values. */ 110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 113 #define I40E_PRTTSYN_TSYNENA 0x80000000 114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000 115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL 116 117 /** 118 * Below are values for writing un-exposed registers suggested 119 * by silicon experts 120 */ 121 /* Destination MAC address */ 122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL 123 /* Source MAC address */ 124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */ 126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */ 128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL 129 /* Single VLAN tag in the inner L2 header */ 130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL 131 /* Source IPv4 address */ 132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL 133 /* Destination IPv4 address */ 134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL 135 /* Source IPv4 address for X722 */ 136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL 137 /* Destination IPv4 address for X722 */ 138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL 139 /* IPv4 Protocol for X722 */ 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL 141 /* IPv4 Time to Live for X722 */ 142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL 143 /* IPv4 Type of Service (TOS) */ 144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL 145 /* IPv4 Protocol */ 146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL 147 /* IPv4 Time to Live */ 148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL 149 /* Source IPv6 address */ 150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL 151 /* Destination IPv6 address */ 152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL 153 /* IPv6 Traffic Class (TC) */ 154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL 155 /* IPv6 Next Header */ 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL 157 /* IPv6 Hop Limit */ 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL 159 /* Source L4 port */ 160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL 161 /* Destination L4 port */ 162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL 163 /* SCTP verification tag */ 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/ 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL 167 /* Source port of tunneling UDP */ 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL 169 /* Destination port of tunneling UDP */ 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL 171 /* UDP Tunneling ID, NVGRE/GRE key */ 172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL 173 /* Last ether type */ 174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL 175 /* Tunneling outer destination IPv4 address */ 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL 177 /* Tunneling outer destination IPv6 address */ 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL 179 /* 1st word of flex payload */ 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL 181 /* 2nd word of flex payload */ 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL 183 /* 3rd word of flex payload */ 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL 185 /* 4th word of flex payload */ 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL 187 /* 5th word of flex payload */ 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL 189 /* 6th word of flex payload */ 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL 191 /* 7th word of flex payload */ 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL 193 /* 8th word of flex payload */ 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL 195 /* all 8 words flex payload */ 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL 197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL 198 199 #define I40E_TRANSLATE_INSET 0 200 #define I40E_TRANSLATE_REG 1 201 202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL 203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL 204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL 205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL 208 209 /* PCI offset for querying capability */ 210 #define PCI_DEV_CAP_REG 0xA4 211 /* PCI offset for enabling/disabling Extended Tag */ 212 #define PCI_DEV_CTRL_REG 0xA8 213 /* Bit mask of Extended Tag capability */ 214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20 215 /* Bit shift of Extended Tag enable/disable */ 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 217 /* Bit mask of Extended Tag enable/disable */ 218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) 219 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); 222 static int i40e_dev_configure(struct rte_eth_dev *dev); 223 static int i40e_dev_start(struct rte_eth_dev *dev); 224 static void i40e_dev_stop(struct rte_eth_dev *dev); 225 static void i40e_dev_close(struct rte_eth_dev *dev); 226 static int i40e_dev_reset(struct rte_eth_dev *dev); 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev); 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev); 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev); 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev); 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev); 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev); 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev, 234 struct rte_eth_stats *stats); 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev, 236 struct rte_eth_xstat *xstats, unsigned n); 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev, 238 struct rte_eth_xstat_name *xstats_names, 239 unsigned limit); 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev); 241 static int i40e_fw_version_get(struct rte_eth_dev *dev, 242 char *fw_version, size_t fw_size); 243 static int i40e_dev_info_get(struct rte_eth_dev *dev, 244 struct rte_eth_dev_info *dev_info); 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev, 246 uint16_t vlan_id, 247 int on); 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev, 249 enum rte_vlan_type vlan_type, 250 uint16_t tpid); 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask); 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev, 253 uint16_t queue, 254 int on); 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on); 256 static int i40e_dev_led_on(struct rte_eth_dev *dev); 257 static int i40e_dev_led_off(struct rte_eth_dev *dev); 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev, 259 struct rte_eth_fc_conf *fc_conf); 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev, 261 struct rte_eth_fc_conf *fc_conf); 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev, 263 struct rte_eth_pfc_conf *pfc_conf); 264 static int i40e_macaddr_add(struct rte_eth_dev *dev, 265 struct rte_ether_addr *mac_addr, 266 uint32_t index, 267 uint32_t pool); 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev, 270 struct rte_eth_rss_reta_entry64 *reta_conf, 271 uint16_t reta_size); 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev, 273 struct rte_eth_rss_reta_entry64 *reta_conf, 274 uint16_t reta_size); 275 276 static int i40e_get_cap(struct i40e_hw *hw); 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev); 278 static int i40e_pf_setup(struct i40e_pf *pf); 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf); 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev); 281 static int i40e_dcb_setup(struct rte_eth_dev *dev); 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg, 283 bool offset_loaded, uint64_t *offset, uint64_t *stat); 284 static void i40e_stat_update_48(struct i40e_hw *hw, 285 uint32_t hireg, 286 uint32_t loreg, 287 bool offset_loaded, 288 uint64_t *offset, 289 uint64_t *stat); 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue); 291 static void i40e_dev_interrupt_handler(void *param); 292 static void i40e_dev_alarm_handler(void *param); 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool, 294 uint32_t base, uint32_t num); 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool); 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool, 297 uint32_t base); 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool, 299 uint16_t num); 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev); 301 static int i40e_veb_release(struct i40e_veb *veb); 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, 303 struct i40e_vsi *vsi); 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf); 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on); 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi, 307 struct i40e_macvlan_filter *mv_f, 308 int num, 309 uint16_t vlan); 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi); 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev, 312 struct rte_eth_rss_conf *rss_conf); 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 314 struct rte_eth_rss_conf *rss_conf); 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 316 struct rte_eth_udp_tunnel *udp_tunnel); 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 318 struct rte_eth_udp_tunnel *udp_tunnel); 319 static void i40e_filter_input_set_init(struct i40e_pf *pf); 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev, 321 enum rte_filter_op filter_op, 322 void *arg); 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, 324 enum rte_filter_type filter_type, 325 enum rte_filter_op filter_op, 326 void *arg); 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, 328 struct rte_eth_dcb_info *dcb_info); 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw); 330 static void i40e_configure_registers(struct i40e_hw *hw); 331 static void i40e_hw_init(struct rte_eth_dev *dev); 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw, 334 uint16_t seid, 335 uint16_t rule_type, 336 uint16_t *entries, 337 uint16_t count, 338 uint16_t rule_id); 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev, 340 struct rte_eth_mirror_conf *mirror_conf, 341 uint8_t sw_id, uint8_t on); 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id); 343 344 static int i40e_timesync_enable(struct rte_eth_dev *dev); 345 static int i40e_timesync_disable(struct rte_eth_dev *dev); 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 347 struct timespec *timestamp, 348 uint32_t flags); 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 350 struct timespec *timestamp); 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw); 352 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 354 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev, 356 struct timespec *timestamp); 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev, 358 const struct timespec *timestamp); 359 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 361 uint16_t queue_id); 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 363 uint16_t queue_id); 364 365 static int i40e_get_regs(struct rte_eth_dev *dev, 366 struct rte_dev_reg_info *regs); 367 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev); 369 370 static int i40e_get_eeprom(struct rte_eth_dev *dev, 371 struct rte_dev_eeprom_info *eeprom); 372 373 static int i40e_get_module_info(struct rte_eth_dev *dev, 374 struct rte_eth_dev_module_info *modinfo); 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev, 376 struct rte_dev_eeprom_info *info); 377 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, 379 struct rte_ether_addr *mac_addr); 380 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 382 383 static int i40e_ethertype_filter_convert( 384 const struct rte_eth_ethertype_filter *input, 385 struct i40e_ethertype_filter *filter); 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf, 387 struct i40e_ethertype_filter *filter); 388 389 static int i40e_tunnel_filter_convert( 390 struct i40e_aqc_cloud_filters_element_bb *cld_filter, 391 struct i40e_tunnel_filter *tunnel_filter); 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, 393 struct i40e_tunnel_filter *tunnel_filter); 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf); 395 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf); 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf); 398 static void i40e_filter_restore(struct i40e_pf *pf); 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev); 400 401 int i40e_logtype_init; 402 int i40e_logtype_driver; 403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX 404 int i40e_logtype_rx; 405 #endif 406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX 407 int i40e_logtype_tx; 408 #endif 409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE 410 int i40e_logtype_tx_free; 411 #endif 412 413 static const char *const valid_keys[] = { 414 ETH_I40E_FLOATING_VEB_ARG, 415 ETH_I40E_FLOATING_VEB_LIST_ARG, 416 ETH_I40E_SUPPORT_MULTI_DRIVER, 417 ETH_I40E_QUEUE_NUM_PER_VF_ARG, 418 ETH_I40E_USE_LATEST_VEC, 419 ETH_I40E_VF_MSG_CFG, 420 NULL}; 421 422 static const struct rte_pci_id pci_id_i40e_map[] = { 423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) }, 424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) }, 425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) }, 426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) }, 427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) }, 428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) }, 429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) }, 430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) }, 431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) }, 432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) }, 433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) }, 434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) }, 435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) }, 436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) }, 437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) }, 438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) }, 439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) }, 440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) }, 441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) }, 442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) }, 443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) }, 444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) }, 445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) }, 446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) }, 447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) }, 448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) }, 449 { .vendor_id = 0, /* sentinel */ }, 450 }; 451 452 static const struct eth_dev_ops i40e_eth_dev_ops = { 453 .dev_configure = i40e_dev_configure, 454 .dev_start = i40e_dev_start, 455 .dev_stop = i40e_dev_stop, 456 .dev_close = i40e_dev_close, 457 .dev_reset = i40e_dev_reset, 458 .promiscuous_enable = i40e_dev_promiscuous_enable, 459 .promiscuous_disable = i40e_dev_promiscuous_disable, 460 .allmulticast_enable = i40e_dev_allmulticast_enable, 461 .allmulticast_disable = i40e_dev_allmulticast_disable, 462 .dev_set_link_up = i40e_dev_set_link_up, 463 .dev_set_link_down = i40e_dev_set_link_down, 464 .link_update = i40e_dev_link_update, 465 .stats_get = i40e_dev_stats_get, 466 .xstats_get = i40e_dev_xstats_get, 467 .xstats_get_names = i40e_dev_xstats_get_names, 468 .stats_reset = i40e_dev_stats_reset, 469 .xstats_reset = i40e_dev_stats_reset, 470 .fw_version_get = i40e_fw_version_get, 471 .dev_infos_get = i40e_dev_info_get, 472 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get, 473 .vlan_filter_set = i40e_vlan_filter_set, 474 .vlan_tpid_set = i40e_vlan_tpid_set, 475 .vlan_offload_set = i40e_vlan_offload_set, 476 .vlan_strip_queue_set = i40e_vlan_strip_queue_set, 477 .vlan_pvid_set = i40e_vlan_pvid_set, 478 .rx_queue_start = i40e_dev_rx_queue_start, 479 .rx_queue_stop = i40e_dev_rx_queue_stop, 480 .tx_queue_start = i40e_dev_tx_queue_start, 481 .tx_queue_stop = i40e_dev_tx_queue_stop, 482 .rx_queue_setup = i40e_dev_rx_queue_setup, 483 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable, 484 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable, 485 .rx_queue_release = i40e_dev_rx_queue_release, 486 .rx_queue_count = i40e_dev_rx_queue_count, 487 .rx_descriptor_done = i40e_dev_rx_descriptor_done, 488 .rx_descriptor_status = i40e_dev_rx_descriptor_status, 489 .tx_descriptor_status = i40e_dev_tx_descriptor_status, 490 .tx_queue_setup = i40e_dev_tx_queue_setup, 491 .tx_queue_release = i40e_dev_tx_queue_release, 492 .dev_led_on = i40e_dev_led_on, 493 .dev_led_off = i40e_dev_led_off, 494 .flow_ctrl_get = i40e_flow_ctrl_get, 495 .flow_ctrl_set = i40e_flow_ctrl_set, 496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set, 497 .mac_addr_add = i40e_macaddr_add, 498 .mac_addr_remove = i40e_macaddr_remove, 499 .reta_update = i40e_dev_rss_reta_update, 500 .reta_query = i40e_dev_rss_reta_query, 501 .rss_hash_update = i40e_dev_rss_hash_update, 502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get, 503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add, 504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del, 505 .filter_ctrl = i40e_dev_filter_ctrl, 506 .rxq_info_get = i40e_rxq_info_get, 507 .txq_info_get = i40e_txq_info_get, 508 .rx_burst_mode_get = i40e_rx_burst_mode_get, 509 .tx_burst_mode_get = i40e_tx_burst_mode_get, 510 .mirror_rule_set = i40e_mirror_rule_set, 511 .mirror_rule_reset = i40e_mirror_rule_reset, 512 .timesync_enable = i40e_timesync_enable, 513 .timesync_disable = i40e_timesync_disable, 514 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp, 515 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp, 516 .get_dcb_info = i40e_dev_get_dcb_info, 517 .timesync_adjust_time = i40e_timesync_adjust_time, 518 .timesync_read_time = i40e_timesync_read_time, 519 .timesync_write_time = i40e_timesync_write_time, 520 .get_reg = i40e_get_regs, 521 .get_eeprom_length = i40e_get_eeprom_length, 522 .get_eeprom = i40e_get_eeprom, 523 .get_module_info = i40e_get_module_info, 524 .get_module_eeprom = i40e_get_module_eeprom, 525 .mac_addr_set = i40e_set_default_mac_addr, 526 .mtu_set = i40e_dev_mtu_set, 527 .tm_ops_get = i40e_tm_ops_get, 528 .tx_done_cleanup = i40e_tx_done_cleanup, 529 }; 530 531 /* store statistics names and its offset in stats structure */ 532 struct rte_i40e_xstats_name_off { 533 char name[RTE_ETH_XSTATS_NAME_SIZE]; 534 unsigned offset; 535 }; 536 537 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = { 538 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)}, 539 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)}, 540 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)}, 541 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)}, 542 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats, 543 rx_unknown_protocol)}, 544 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)}, 545 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)}, 546 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)}, 547 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)}, 548 }; 549 550 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \ 551 sizeof(rte_i40e_stats_strings[0])) 552 553 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = { 554 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats, 555 tx_dropped_link_down)}, 556 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)}, 557 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats, 558 illegal_bytes)}, 559 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)}, 560 {"mac_local_errors", offsetof(struct i40e_hw_port_stats, 561 mac_local_faults)}, 562 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats, 563 mac_remote_faults)}, 564 {"rx_length_errors", offsetof(struct i40e_hw_port_stats, 565 rx_length_errors)}, 566 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)}, 567 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)}, 568 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)}, 569 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)}, 570 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)}, 571 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats, 572 rx_size_127)}, 573 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats, 574 rx_size_255)}, 575 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats, 576 rx_size_511)}, 577 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats, 578 rx_size_1023)}, 579 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats, 580 rx_size_1522)}, 581 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats, 582 rx_size_big)}, 583 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats, 584 rx_undersize)}, 585 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats, 586 rx_oversize)}, 587 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats, 588 mac_short_packet_dropped)}, 589 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats, 590 rx_fragments)}, 591 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)}, 592 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)}, 593 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats, 594 tx_size_127)}, 595 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats, 596 tx_size_255)}, 597 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats, 598 tx_size_511)}, 599 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats, 600 tx_size_1023)}, 601 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats, 602 tx_size_1522)}, 603 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats, 604 tx_size_big)}, 605 {"rx_flow_director_atr_match_packets", 606 offsetof(struct i40e_hw_port_stats, fd_atr_match)}, 607 {"rx_flow_director_sb_match_packets", 608 offsetof(struct i40e_hw_port_stats, fd_sb_match)}, 609 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats, 610 tx_lpi_status)}, 611 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats, 612 rx_lpi_status)}, 613 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats, 614 tx_lpi_count)}, 615 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats, 616 rx_lpi_count)}, 617 }; 618 619 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \ 620 sizeof(rte_i40e_hw_port_strings[0])) 621 622 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = { 623 {"xon_packets", offsetof(struct i40e_hw_port_stats, 624 priority_xon_rx)}, 625 {"xoff_packets", offsetof(struct i40e_hw_port_stats, 626 priority_xoff_rx)}, 627 }; 628 629 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \ 630 sizeof(rte_i40e_rxq_prio_strings[0])) 631 632 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = { 633 {"xon_packets", offsetof(struct i40e_hw_port_stats, 634 priority_xon_tx)}, 635 {"xoff_packets", offsetof(struct i40e_hw_port_stats, 636 priority_xoff_tx)}, 637 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats, 638 priority_xon_2_xoff)}, 639 }; 640 641 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \ 642 sizeof(rte_i40e_txq_prio_strings[0])) 643 644 static int 645 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 646 struct rte_pci_device *pci_dev) 647 { 648 char name[RTE_ETH_NAME_MAX_LEN]; 649 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 650 int i, retval; 651 652 if (pci_dev->device.devargs) { 653 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 654 ð_da); 655 if (retval) 656 return retval; 657 } 658 659 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 660 sizeof(struct i40e_adapter), 661 eth_dev_pci_specific_init, pci_dev, 662 eth_i40e_dev_init, NULL); 663 664 if (retval || eth_da.nb_representor_ports < 1) 665 return retval; 666 667 /* probe VF representor ports */ 668 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated( 669 pci_dev->device.name); 670 671 if (pf_ethdev == NULL) 672 return -ENODEV; 673 674 for (i = 0; i < eth_da.nb_representor_ports; i++) { 675 struct i40e_vf_representor representor = { 676 .vf_id = eth_da.representor_ports[i], 677 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF( 678 pf_ethdev->data->dev_private)->switch_domain_id, 679 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER( 680 pf_ethdev->data->dev_private) 681 }; 682 683 /* representor port net_bdf_port */ 684 snprintf(name, sizeof(name), "net_%s_representor_%d", 685 pci_dev->device.name, eth_da.representor_ports[i]); 686 687 retval = rte_eth_dev_create(&pci_dev->device, name, 688 sizeof(struct i40e_vf_representor), NULL, NULL, 689 i40e_vf_representor_init, &representor); 690 691 if (retval) 692 PMD_DRV_LOG(ERR, "failed to create i40e vf " 693 "representor %s.", name); 694 } 695 696 return 0; 697 } 698 699 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev) 700 { 701 struct rte_eth_dev *ethdev; 702 703 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 704 if (!ethdev) 705 return 0; 706 707 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 708 return rte_eth_dev_pci_generic_remove(pci_dev, 709 i40e_vf_representor_uninit); 710 else 711 return rte_eth_dev_pci_generic_remove(pci_dev, 712 eth_i40e_dev_uninit); 713 } 714 715 static struct rte_pci_driver rte_i40e_pmd = { 716 .id_table = pci_id_i40e_map, 717 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 718 .probe = eth_i40e_pci_probe, 719 .remove = eth_i40e_pci_remove, 720 }; 721 722 static inline void 723 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr, 724 uint32_t reg_val) 725 { 726 uint32_t ori_reg_val; 727 struct rte_eth_dev *dev; 728 729 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr); 730 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 731 i40e_write_rx_ctl(hw, reg_addr, reg_val); 732 if (ori_reg_val != reg_val) 733 PMD_DRV_LOG(WARNING, 734 "i40e device %s changed global register [0x%08x]." 735 " original: 0x%08x, new: 0x%08x", 736 dev->device->name, reg_addr, ori_reg_val, reg_val); 737 } 738 739 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd); 740 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map); 741 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci"); 742 743 #ifndef I40E_GLQF_ORT 744 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) 745 #endif 746 #ifndef I40E_GLQF_PIT 747 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) 748 #endif 749 #ifndef I40E_GLQF_L3_MAP 750 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4)) 751 #endif 752 753 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) 754 { 755 /* 756 * Initialize registers for parsing packet type of QinQ 757 * This should be removed from code once proper 758 * configuration API is added to avoid configuration conflicts 759 * between ports of the same device. 760 */ 761 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029); 762 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420); 763 } 764 765 static inline void i40e_config_automask(struct i40e_pf *pf) 766 { 767 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 768 uint32_t val; 769 770 /* INTENA flag is not auto-cleared for interrupt */ 771 val = I40E_READ_REG(hw, I40E_GLINT_CTL); 772 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK | 773 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK; 774 775 /* If support multi-driver, PF will use INT0. */ 776 if (!pf->support_multi_driver) 777 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK; 778 779 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val); 780 } 781 782 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808 783 784 /* 785 * Add a ethertype filter to drop all flow control frames transmitted 786 * from VSIs. 787 */ 788 static void 789 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf) 790 { 791 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 792 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 793 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 794 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 795 int ret; 796 797 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL, 798 I40E_FLOW_CONTROL_ETHERTYPE, flags, 799 pf->main_vsi_seid, 0, 800 TRUE, NULL, NULL); 801 if (ret) 802 PMD_INIT_LOG(ERR, 803 "Failed to add filter to drop flow control frames from VSIs."); 804 } 805 806 static int 807 floating_veb_list_handler(__rte_unused const char *key, 808 const char *floating_veb_value, 809 void *opaque) 810 { 811 int idx = 0; 812 unsigned int count = 0; 813 char *end = NULL; 814 int min, max; 815 bool *vf_floating_veb = opaque; 816 817 while (isblank(*floating_veb_value)) 818 floating_veb_value++; 819 820 /* Reset floating VEB configuration for VFs */ 821 for (idx = 0; idx < I40E_MAX_VF; idx++) 822 vf_floating_veb[idx] = false; 823 824 min = I40E_MAX_VF; 825 do { 826 while (isblank(*floating_veb_value)) 827 floating_veb_value++; 828 if (*floating_veb_value == '\0') 829 return -1; 830 errno = 0; 831 idx = strtoul(floating_veb_value, &end, 10); 832 if (errno || end == NULL) 833 return -1; 834 while (isblank(*end)) 835 end++; 836 if (*end == '-') { 837 min = idx; 838 } else if ((*end == ';') || (*end == '\0')) { 839 max = idx; 840 if (min == I40E_MAX_VF) 841 min = idx; 842 if (max >= I40E_MAX_VF) 843 max = I40E_MAX_VF - 1; 844 for (idx = min; idx <= max; idx++) { 845 vf_floating_veb[idx] = true; 846 count++; 847 } 848 min = I40E_MAX_VF; 849 } else { 850 return -1; 851 } 852 floating_veb_value = end + 1; 853 } while (*end != '\0'); 854 855 if (count == 0) 856 return -1; 857 858 return 0; 859 } 860 861 static void 862 config_vf_floating_veb(struct rte_devargs *devargs, 863 uint16_t floating_veb, 864 bool *vf_floating_veb) 865 { 866 struct rte_kvargs *kvlist; 867 int i; 868 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG; 869 870 if (!floating_veb) 871 return; 872 /* All the VFs attach to the floating VEB by default 873 * when the floating VEB is enabled. 874 */ 875 for (i = 0; i < I40E_MAX_VF; i++) 876 vf_floating_veb[i] = true; 877 878 if (devargs == NULL) 879 return; 880 881 kvlist = rte_kvargs_parse(devargs->args, valid_keys); 882 if (kvlist == NULL) 883 return; 884 885 if (!rte_kvargs_count(kvlist, floating_veb_list)) { 886 rte_kvargs_free(kvlist); 887 return; 888 } 889 /* When the floating_veb_list parameter exists, all the VFs 890 * will attach to the legacy VEB firstly, then configure VFs 891 * to the floating VEB according to the floating_veb_list. 892 */ 893 if (rte_kvargs_process(kvlist, floating_veb_list, 894 floating_veb_list_handler, 895 vf_floating_veb) < 0) { 896 rte_kvargs_free(kvlist); 897 return; 898 } 899 rte_kvargs_free(kvlist); 900 } 901 902 static int 903 i40e_check_floating_handler(__rte_unused const char *key, 904 const char *value, 905 __rte_unused void *opaque) 906 { 907 if (strcmp(value, "1")) 908 return -1; 909 910 return 0; 911 } 912 913 static int 914 is_floating_veb_supported(struct rte_devargs *devargs) 915 { 916 struct rte_kvargs *kvlist; 917 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG; 918 919 if (devargs == NULL) 920 return 0; 921 922 kvlist = rte_kvargs_parse(devargs->args, valid_keys); 923 if (kvlist == NULL) 924 return 0; 925 926 if (!rte_kvargs_count(kvlist, floating_veb_key)) { 927 rte_kvargs_free(kvlist); 928 return 0; 929 } 930 /* Floating VEB is enabled when there's key-value: 931 * enable_floating_veb=1 932 */ 933 if (rte_kvargs_process(kvlist, floating_veb_key, 934 i40e_check_floating_handler, NULL) < 0) { 935 rte_kvargs_free(kvlist); 936 return 0; 937 } 938 rte_kvargs_free(kvlist); 939 940 return 1; 941 } 942 943 static void 944 config_floating_veb(struct rte_eth_dev *dev) 945 { 946 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 947 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 948 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 949 950 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list)); 951 952 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) { 953 pf->floating_veb = 954 is_floating_veb_supported(pci_dev->device.devargs); 955 config_vf_floating_veb(pci_dev->device.devargs, 956 pf->floating_veb, 957 pf->floating_veb_list); 958 } else { 959 pf->floating_veb = false; 960 } 961 } 962 963 #define I40E_L2_TAGS_S_TAG_SHIFT 1 964 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT) 965 966 static int 967 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev) 968 { 969 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 970 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 971 char ethertype_hash_name[RTE_HASH_NAMESIZE]; 972 int ret; 973 974 struct rte_hash_parameters ethertype_hash_params = { 975 .name = ethertype_hash_name, 976 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM, 977 .key_len = sizeof(struct i40e_ethertype_filter_input), 978 .hash_func = rte_hash_crc, 979 .hash_func_init_val = 0, 980 .socket_id = rte_socket_id(), 981 }; 982 983 /* Initialize ethertype filter rule list and hash */ 984 TAILQ_INIT(ðertype_rule->ethertype_list); 985 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE, 986 "ethertype_%s", dev->device->name); 987 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params); 988 if (!ethertype_rule->hash_table) { 989 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!"); 990 return -EINVAL; 991 } 992 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map", 993 sizeof(struct i40e_ethertype_filter *) * 994 I40E_MAX_ETHERTYPE_FILTER_NUM, 995 0); 996 if (!ethertype_rule->hash_map) { 997 PMD_INIT_LOG(ERR, 998 "Failed to allocate memory for ethertype hash map!"); 999 ret = -ENOMEM; 1000 goto err_ethertype_hash_map_alloc; 1001 } 1002 1003 return 0; 1004 1005 err_ethertype_hash_map_alloc: 1006 rte_hash_free(ethertype_rule->hash_table); 1007 1008 return ret; 1009 } 1010 1011 static int 1012 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev) 1013 { 1014 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1015 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 1016 char tunnel_hash_name[RTE_HASH_NAMESIZE]; 1017 int ret; 1018 1019 struct rte_hash_parameters tunnel_hash_params = { 1020 .name = tunnel_hash_name, 1021 .entries = I40E_MAX_TUNNEL_FILTER_NUM, 1022 .key_len = sizeof(struct i40e_tunnel_filter_input), 1023 .hash_func = rte_hash_crc, 1024 .hash_func_init_val = 0, 1025 .socket_id = rte_socket_id(), 1026 }; 1027 1028 /* Initialize tunnel filter rule list and hash */ 1029 TAILQ_INIT(&tunnel_rule->tunnel_list); 1030 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE, 1031 "tunnel_%s", dev->device->name); 1032 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params); 1033 if (!tunnel_rule->hash_table) { 1034 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!"); 1035 return -EINVAL; 1036 } 1037 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map", 1038 sizeof(struct i40e_tunnel_filter *) * 1039 I40E_MAX_TUNNEL_FILTER_NUM, 1040 0); 1041 if (!tunnel_rule->hash_map) { 1042 PMD_INIT_LOG(ERR, 1043 "Failed to allocate memory for tunnel hash map!"); 1044 ret = -ENOMEM; 1045 goto err_tunnel_hash_map_alloc; 1046 } 1047 1048 return 0; 1049 1050 err_tunnel_hash_map_alloc: 1051 rte_hash_free(tunnel_rule->hash_table); 1052 1053 return ret; 1054 } 1055 1056 static int 1057 i40e_init_fdir_filter_list(struct rte_eth_dev *dev) 1058 { 1059 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1060 struct i40e_fdir_info *fdir_info = &pf->fdir; 1061 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1062 int ret; 1063 1064 struct rte_hash_parameters fdir_hash_params = { 1065 .name = fdir_hash_name, 1066 .entries = I40E_MAX_FDIR_FILTER_NUM, 1067 .key_len = sizeof(struct i40e_fdir_input), 1068 .hash_func = rte_hash_crc, 1069 .hash_func_init_val = 0, 1070 .socket_id = rte_socket_id(), 1071 }; 1072 1073 /* Initialize flow director filter rule list and hash */ 1074 TAILQ_INIT(&fdir_info->fdir_list); 1075 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1076 "fdir_%s", dev->device->name); 1077 fdir_info->hash_table = rte_hash_create(&fdir_hash_params); 1078 if (!fdir_info->hash_table) { 1079 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1080 return -EINVAL; 1081 } 1082 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map", 1083 sizeof(struct i40e_fdir_filter *) * 1084 I40E_MAX_FDIR_FILTER_NUM, 1085 0); 1086 if (!fdir_info->hash_map) { 1087 PMD_INIT_LOG(ERR, 1088 "Failed to allocate memory for fdir hash map!"); 1089 ret = -ENOMEM; 1090 goto err_fdir_hash_map_alloc; 1091 } 1092 return 0; 1093 1094 err_fdir_hash_map_alloc: 1095 rte_hash_free(fdir_info->hash_table); 1096 1097 return ret; 1098 } 1099 1100 static void 1101 i40e_init_customized_info(struct i40e_pf *pf) 1102 { 1103 int i; 1104 1105 /* Initialize customized pctype */ 1106 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) { 1107 pf->customized_pctype[i].index = i; 1108 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID; 1109 pf->customized_pctype[i].valid = false; 1110 } 1111 1112 pf->gtp_support = false; 1113 pf->esp_support = false; 1114 } 1115 1116 void 1117 i40e_init_queue_region_conf(struct rte_eth_dev *dev) 1118 { 1119 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1120 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1121 struct i40e_queue_regions *info = &pf->queue_region; 1122 uint16_t i; 1123 1124 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++) 1125 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0); 1126 1127 memset(info, 0, sizeof(struct i40e_queue_regions)); 1128 } 1129 1130 static int 1131 i40e_parse_multi_drv_handler(__rte_unused const char *key, 1132 const char *value, 1133 void *opaque) 1134 { 1135 struct i40e_pf *pf; 1136 unsigned long support_multi_driver; 1137 char *end; 1138 1139 pf = (struct i40e_pf *)opaque; 1140 1141 errno = 0; 1142 support_multi_driver = strtoul(value, &end, 10); 1143 if (errno != 0 || end == value || *end != 0) { 1144 PMD_DRV_LOG(WARNING, "Wrong global configuration"); 1145 return -(EINVAL); 1146 } 1147 1148 if (support_multi_driver == 1 || support_multi_driver == 0) 1149 pf->support_multi_driver = (bool)support_multi_driver; 1150 else 1151 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,", 1152 "enable global configuration by default." 1153 ETH_I40E_SUPPORT_MULTI_DRIVER); 1154 return 0; 1155 } 1156 1157 static int 1158 i40e_support_multi_driver(struct rte_eth_dev *dev) 1159 { 1160 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1161 struct rte_kvargs *kvlist; 1162 int kvargs_count; 1163 1164 /* Enable global configuration by default */ 1165 pf->support_multi_driver = false; 1166 1167 if (!dev->device->devargs) 1168 return 0; 1169 1170 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1171 if (!kvlist) 1172 return -EINVAL; 1173 1174 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER); 1175 if (!kvargs_count) { 1176 rte_kvargs_free(kvlist); 1177 return 0; 1178 } 1179 1180 if (kvargs_count > 1) 1181 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 1182 "the first invalid or last valid one is used !", 1183 ETH_I40E_SUPPORT_MULTI_DRIVER); 1184 1185 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER, 1186 i40e_parse_multi_drv_handler, pf) < 0) { 1187 rte_kvargs_free(kvlist); 1188 return -EINVAL; 1189 } 1190 1191 rte_kvargs_free(kvlist); 1192 return 0; 1193 } 1194 1195 static int 1196 i40e_aq_debug_write_global_register(struct i40e_hw *hw, 1197 uint32_t reg_addr, uint64_t reg_val, 1198 struct i40e_asq_cmd_details *cmd_details) 1199 { 1200 uint64_t ori_reg_val; 1201 struct rte_eth_dev *dev; 1202 int ret; 1203 1204 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL); 1205 if (ret != I40E_SUCCESS) { 1206 PMD_DRV_LOG(ERR, 1207 "Fail to debug read from 0x%08x", 1208 reg_addr); 1209 return -EIO; 1210 } 1211 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 1212 1213 if (ori_reg_val != reg_val) 1214 PMD_DRV_LOG(WARNING, 1215 "i40e device %s changed global register [0x%08x]." 1216 " original: 0x%"PRIx64", after: 0x%"PRIx64, 1217 dev->device->name, reg_addr, ori_reg_val, reg_val); 1218 1219 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details); 1220 } 1221 1222 static int 1223 i40e_parse_latest_vec_handler(__rte_unused const char *key, 1224 const char *value, 1225 void *opaque) 1226 { 1227 struct i40e_adapter *ad = opaque; 1228 int use_latest_vec; 1229 1230 use_latest_vec = atoi(value); 1231 1232 if (use_latest_vec != 0 && use_latest_vec != 1) 1233 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!"); 1234 1235 ad->use_latest_vec = (uint8_t)use_latest_vec; 1236 1237 return 0; 1238 } 1239 1240 static int 1241 i40e_use_latest_vec(struct rte_eth_dev *dev) 1242 { 1243 struct i40e_adapter *ad = 1244 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1245 struct rte_kvargs *kvlist; 1246 int kvargs_count; 1247 1248 ad->use_latest_vec = false; 1249 1250 if (!dev->device->devargs) 1251 return 0; 1252 1253 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1254 if (!kvlist) 1255 return -EINVAL; 1256 1257 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC); 1258 if (!kvargs_count) { 1259 rte_kvargs_free(kvlist); 1260 return 0; 1261 } 1262 1263 if (kvargs_count > 1) 1264 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 1265 "the first invalid or last valid one is used !", 1266 ETH_I40E_USE_LATEST_VEC); 1267 1268 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC, 1269 i40e_parse_latest_vec_handler, ad) < 0) { 1270 rte_kvargs_free(kvlist); 1271 return -EINVAL; 1272 } 1273 1274 rte_kvargs_free(kvlist); 1275 return 0; 1276 } 1277 1278 static int 1279 read_vf_msg_config(__rte_unused const char *key, 1280 const char *value, 1281 void *opaque) 1282 { 1283 struct i40e_vf_msg_cfg *cfg = opaque; 1284 1285 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period, 1286 &cfg->ignore_second) != 3) { 1287 memset(cfg, 0, sizeof(*cfg)); 1288 PMD_DRV_LOG(ERR, "format error! example: " 1289 "%s=60@120:180", ETH_I40E_VF_MSG_CFG); 1290 return -EINVAL; 1291 } 1292 1293 /* 1294 * If the message validation function been enabled, the 'period' 1295 * and 'ignore_second' must greater than 0. 1296 */ 1297 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) { 1298 memset(cfg, 0, sizeof(*cfg)); 1299 PMD_DRV_LOG(ERR, "%s error! the second and third" 1300 " number must be greater than 0!", 1301 ETH_I40E_VF_MSG_CFG); 1302 return -EINVAL; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static int 1309 i40e_parse_vf_msg_config(struct rte_eth_dev *dev, 1310 struct i40e_vf_msg_cfg *msg_cfg) 1311 { 1312 struct rte_kvargs *kvlist; 1313 int kvargs_count; 1314 int ret = 0; 1315 1316 memset(msg_cfg, 0, sizeof(*msg_cfg)); 1317 1318 if (!dev->device->devargs) 1319 return ret; 1320 1321 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1322 if (!kvlist) 1323 return -EINVAL; 1324 1325 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG); 1326 if (!kvargs_count) 1327 goto free_end; 1328 1329 if (kvargs_count > 1) { 1330 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!", 1331 ETH_I40E_VF_MSG_CFG); 1332 ret = -EINVAL; 1333 goto free_end; 1334 } 1335 1336 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG, 1337 read_vf_msg_config, msg_cfg) < 0) 1338 ret = -EINVAL; 1339 1340 free_end: 1341 rte_kvargs_free(kvlist); 1342 return ret; 1343 } 1344 1345 #define I40E_ALARM_INTERVAL 50000 /* us */ 1346 1347 static int 1348 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) 1349 { 1350 struct rte_pci_device *pci_dev; 1351 struct rte_intr_handle *intr_handle; 1352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1353 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1354 struct i40e_vsi *vsi; 1355 int ret; 1356 uint32_t len, val; 1357 uint8_t aq_fail = 0; 1358 1359 PMD_INIT_FUNC_TRACE(); 1360 1361 dev->dev_ops = &i40e_eth_dev_ops; 1362 dev->rx_pkt_burst = i40e_recv_pkts; 1363 dev->tx_pkt_burst = i40e_xmit_pkts; 1364 dev->tx_pkt_prepare = i40e_prep_pkts; 1365 1366 /* for secondary processes, we don't initialise any further as primary 1367 * has already done this work. Only check we don't need a different 1368 * RX function */ 1369 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 1370 i40e_set_rx_function(dev); 1371 i40e_set_tx_function(dev); 1372 return 0; 1373 } 1374 i40e_set_default_ptype_table(dev); 1375 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1376 intr_handle = &pci_dev->intr_handle; 1377 1378 rte_eth_copy_pci_info(dev, pci_dev); 1379 1380 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1381 pf->adapter->eth_dev = dev; 1382 pf->dev_data = dev->data; 1383 1384 hw->back = I40E_PF_TO_ADAPTER(pf); 1385 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr); 1386 if (!hw->hw_addr) { 1387 PMD_INIT_LOG(ERR, 1388 "Hardware is not available, as address is NULL"); 1389 return -ENODEV; 1390 } 1391 1392 hw->vendor_id = pci_dev->id.vendor_id; 1393 hw->device_id = pci_dev->id.device_id; 1394 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1395 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1396 hw->bus.device = pci_dev->addr.devid; 1397 hw->bus.func = pci_dev->addr.function; 1398 hw->adapter_stopped = 0; 1399 hw->adapter_closed = 0; 1400 1401 /* Init switch device pointer */ 1402 hw->switch_dev = NULL; 1403 1404 /* 1405 * Switch Tag value should not be identical to either the First Tag 1406 * or Second Tag values. So set something other than common Ethertype 1407 * for internal switching. 1408 */ 1409 hw->switch_tag = 0xffff; 1410 1411 val = I40E_READ_REG(hw, I40E_GL_FWSTS); 1412 if (val & I40E_GL_FWSTS_FWS1B_MASK) { 1413 PMD_INIT_LOG(ERR, "\nERROR: " 1414 "Firmware recovery mode detected. Limiting functionality.\n" 1415 "Refer to the Intel(R) Ethernet Adapters and Devices " 1416 "User Guide for details on firmware recovery mode."); 1417 return -EIO; 1418 } 1419 1420 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg); 1421 /* Check if need to support multi-driver */ 1422 i40e_support_multi_driver(dev); 1423 /* Check if users want the latest supported vec path */ 1424 i40e_use_latest_vec(dev); 1425 1426 /* Make sure all is clean before doing PF reset */ 1427 i40e_clear_hw(hw); 1428 1429 /* Reset here to make sure all is clean for each PF */ 1430 ret = i40e_pf_reset(hw); 1431 if (ret) { 1432 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret); 1433 return ret; 1434 } 1435 1436 /* Initialize the shared code (base driver) */ 1437 ret = i40e_init_shared_code(hw); 1438 if (ret) { 1439 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret); 1440 return ret; 1441 } 1442 1443 /* Initialize the parameters for adminq */ 1444 i40e_init_adminq_parameter(hw); 1445 ret = i40e_init_adminq(hw); 1446 if (ret != I40E_SUCCESS) { 1447 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret); 1448 return -EIO; 1449 } 1450 /* Firmware of SFP x722 does not support adminq option */ 1451 if (hw->device_id == I40E_DEV_ID_SFP_X722) 1452 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE; 1453 1454 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x", 1455 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 1456 hw->aq.api_maj_ver, hw->aq.api_min_ver, 1457 ((hw->nvm.version >> 12) & 0xf), 1458 ((hw->nvm.version >> 4) & 0xff), 1459 (hw->nvm.version & 0xf), hw->nvm.eetrack); 1460 1461 /* Initialize the hardware */ 1462 i40e_hw_init(dev); 1463 1464 i40e_config_automask(pf); 1465 1466 i40e_set_default_pctype_table(dev); 1467 1468 /* 1469 * To work around the NVM issue, initialize registers 1470 * for packet type of QinQ by software. 1471 * It should be removed once issues are fixed in NVM. 1472 */ 1473 if (!pf->support_multi_driver) 1474 i40e_GLQF_reg_init(hw); 1475 1476 /* Initialize the input set for filters (hash and fd) to default value */ 1477 i40e_filter_input_set_init(pf); 1478 1479 /* initialise the L3_MAP register */ 1480 if (!pf->support_multi_driver) { 1481 ret = i40e_aq_debug_write_global_register(hw, 1482 I40E_GLQF_L3_MAP(40), 1483 0x00000028, NULL); 1484 if (ret) 1485 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", 1486 ret); 1487 PMD_INIT_LOG(DEBUG, 1488 "Global register 0x%08x is changed with 0x28", 1489 I40E_GLQF_L3_MAP(40)); 1490 } 1491 1492 /* Need the special FW version to support floating VEB */ 1493 config_floating_veb(dev); 1494 /* Clear PXE mode */ 1495 i40e_clear_pxe_mode(hw); 1496 i40e_dev_sync_phy_type(hw); 1497 1498 /* 1499 * On X710, performance number is far from the expectation on recent 1500 * firmware versions. The fix for this issue may not be integrated in 1501 * the following firmware version. So the workaround in software driver 1502 * is needed. It needs to modify the initial values of 3 internal only 1503 * registers. Note that the workaround can be removed when it is fixed 1504 * in firmware in the future. 1505 */ 1506 i40e_configure_registers(hw); 1507 1508 /* Get hw capabilities */ 1509 ret = i40e_get_cap(hw); 1510 if (ret != I40E_SUCCESS) { 1511 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret); 1512 goto err_get_capabilities; 1513 } 1514 1515 /* Initialize parameters for PF */ 1516 ret = i40e_pf_parameter_init(dev); 1517 if (ret != 0) { 1518 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret); 1519 goto err_parameter_init; 1520 } 1521 1522 /* Initialize the queue management */ 1523 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp); 1524 if (ret < 0) { 1525 PMD_INIT_LOG(ERR, "Failed to init queue pool"); 1526 goto err_qp_pool_init; 1527 } 1528 ret = i40e_res_pool_init(&pf->msix_pool, 1, 1529 hw->func_caps.num_msix_vectors - 1); 1530 if (ret < 0) { 1531 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 1532 goto err_msix_pool_init; 1533 } 1534 1535 /* Initialize lan hmc */ 1536 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 1537 hw->func_caps.num_rx_qp, 0, 0); 1538 if (ret != I40E_SUCCESS) { 1539 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret); 1540 goto err_init_lan_hmc; 1541 } 1542 1543 /* Configure lan hmc */ 1544 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 1545 if (ret != I40E_SUCCESS) { 1546 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret); 1547 goto err_configure_lan_hmc; 1548 } 1549 1550 /* Get and check the mac address */ 1551 i40e_get_mac_addr(hw, hw->mac.addr); 1552 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) { 1553 PMD_INIT_LOG(ERR, "mac address is not valid"); 1554 ret = -EIO; 1555 goto err_get_mac_addr; 1556 } 1557 /* Copy the permanent MAC address */ 1558 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, 1559 (struct rte_ether_addr *)hw->mac.perm_addr); 1560 1561 /* Disable flow control */ 1562 hw->fc.requested_mode = I40E_FC_NONE; 1563 i40e_set_fc(hw, &aq_fail, TRUE); 1564 1565 /* Set the global registers with default ether type value */ 1566 if (!pf->support_multi_driver) { 1567 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 1568 RTE_ETHER_TYPE_VLAN); 1569 if (ret != I40E_SUCCESS) { 1570 PMD_INIT_LOG(ERR, 1571 "Failed to set the default outer " 1572 "VLAN ether type"); 1573 goto err_setup_pf_switch; 1574 } 1575 } 1576 1577 /* PF setup, which includes VSI setup */ 1578 ret = i40e_pf_setup(pf); 1579 if (ret) { 1580 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret); 1581 goto err_setup_pf_switch; 1582 } 1583 1584 vsi = pf->main_vsi; 1585 1586 /* Disable double vlan by default */ 1587 i40e_vsi_config_double_vlan(vsi, FALSE); 1588 1589 /* Disable S-TAG identification when floating_veb is disabled */ 1590 if (!pf->floating_veb) { 1591 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN); 1592 if (ret & I40E_L2_TAGS_S_TAG_MASK) { 1593 ret &= ~I40E_L2_TAGS_S_TAG_MASK; 1594 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret); 1595 } 1596 } 1597 1598 if (!vsi->max_macaddrs) 1599 len = RTE_ETHER_ADDR_LEN; 1600 else 1601 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs; 1602 1603 /* Should be after VSI initialized */ 1604 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0); 1605 if (!dev->data->mac_addrs) { 1606 PMD_INIT_LOG(ERR, 1607 "Failed to allocated memory for storing mac address"); 1608 goto err_mac_alloc; 1609 } 1610 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1611 &dev->data->mac_addrs[0]); 1612 1613 /* Pass the information to the rte_eth_dev_close() that it should also 1614 * release the private port resources. 1615 */ 1616 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1617 1618 /* Init dcb to sw mode by default */ 1619 ret = i40e_dcb_init_configure(dev, TRUE); 1620 if (ret != I40E_SUCCESS) { 1621 PMD_INIT_LOG(INFO, "Failed to init dcb."); 1622 pf->flags &= ~I40E_FLAG_DCB; 1623 } 1624 /* Update HW struct after DCB configuration */ 1625 i40e_get_cap(hw); 1626 1627 /* initialize pf host driver to setup SRIOV resource if applicable */ 1628 i40e_pf_host_init(dev); 1629 1630 /* register callback func to eal lib */ 1631 rte_intr_callback_register(intr_handle, 1632 i40e_dev_interrupt_handler, dev); 1633 1634 /* configure and enable device interrupt */ 1635 i40e_pf_config_irq0(hw, TRUE); 1636 i40e_pf_enable_irq0(hw); 1637 1638 /* enable uio intr after callback register */ 1639 rte_intr_enable(intr_handle); 1640 1641 /* By default disable flexible payload in global configuration */ 1642 if (!pf->support_multi_driver) 1643 i40e_flex_payload_reg_set_default(hw); 1644 1645 /* 1646 * Add an ethertype filter to drop all flow control frames transmitted 1647 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC 1648 * frames to wire. 1649 */ 1650 i40e_add_tx_flow_control_drop_filter(pf); 1651 1652 /* Set the max frame size to 0x2600 by default, 1653 * in case other drivers changed the default value. 1654 */ 1655 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL); 1656 1657 /* initialize mirror rule list */ 1658 TAILQ_INIT(&pf->mirror_list); 1659 1660 /* initialize RSS rule list */ 1661 TAILQ_INIT(&pf->rss_config_list); 1662 1663 /* initialize Traffic Manager configuration */ 1664 i40e_tm_conf_init(dev); 1665 1666 /* Initialize customized information */ 1667 i40e_init_customized_info(pf); 1668 1669 ret = i40e_init_ethtype_filter_list(dev); 1670 if (ret < 0) 1671 goto err_init_ethtype_filter_list; 1672 ret = i40e_init_tunnel_filter_list(dev); 1673 if (ret < 0) 1674 goto err_init_tunnel_filter_list; 1675 ret = i40e_init_fdir_filter_list(dev); 1676 if (ret < 0) 1677 goto err_init_fdir_filter_list; 1678 1679 /* initialize queue region configuration */ 1680 i40e_init_queue_region_conf(dev); 1681 1682 /* initialize RSS configuration from rte_flow */ 1683 memset(&pf->rss_info, 0, 1684 sizeof(struct i40e_rte_flow_rss_conf)); 1685 1686 /* reset all stats of the device, including pf and main vsi */ 1687 i40e_dev_stats_reset(dev); 1688 1689 return 0; 1690 1691 err_init_fdir_filter_list: 1692 rte_free(pf->tunnel.hash_table); 1693 rte_free(pf->tunnel.hash_map); 1694 err_init_tunnel_filter_list: 1695 rte_free(pf->ethertype.hash_table); 1696 rte_free(pf->ethertype.hash_map); 1697 err_init_ethtype_filter_list: 1698 rte_free(dev->data->mac_addrs); 1699 dev->data->mac_addrs = NULL; 1700 err_mac_alloc: 1701 i40e_vsi_release(pf->main_vsi); 1702 err_setup_pf_switch: 1703 err_get_mac_addr: 1704 err_configure_lan_hmc: 1705 (void)i40e_shutdown_lan_hmc(hw); 1706 err_init_lan_hmc: 1707 i40e_res_pool_destroy(&pf->msix_pool); 1708 err_msix_pool_init: 1709 i40e_res_pool_destroy(&pf->qp_pool); 1710 err_qp_pool_init: 1711 err_parameter_init: 1712 err_get_capabilities: 1713 (void)i40e_shutdown_adminq(hw); 1714 1715 return ret; 1716 } 1717 1718 static void 1719 i40e_rm_ethtype_filter_list(struct i40e_pf *pf) 1720 { 1721 struct i40e_ethertype_filter *p_ethertype; 1722 struct i40e_ethertype_rule *ethertype_rule; 1723 1724 ethertype_rule = &pf->ethertype; 1725 /* Remove all ethertype filter rules and hash */ 1726 if (ethertype_rule->hash_map) 1727 rte_free(ethertype_rule->hash_map); 1728 if (ethertype_rule->hash_table) 1729 rte_hash_free(ethertype_rule->hash_table); 1730 1731 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) { 1732 TAILQ_REMOVE(ðertype_rule->ethertype_list, 1733 p_ethertype, rules); 1734 rte_free(p_ethertype); 1735 } 1736 } 1737 1738 static void 1739 i40e_rm_tunnel_filter_list(struct i40e_pf *pf) 1740 { 1741 struct i40e_tunnel_filter *p_tunnel; 1742 struct i40e_tunnel_rule *tunnel_rule; 1743 1744 tunnel_rule = &pf->tunnel; 1745 /* Remove all tunnel director rules and hash */ 1746 if (tunnel_rule->hash_map) 1747 rte_free(tunnel_rule->hash_map); 1748 if (tunnel_rule->hash_table) 1749 rte_hash_free(tunnel_rule->hash_table); 1750 1751 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) { 1752 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules); 1753 rte_free(p_tunnel); 1754 } 1755 } 1756 1757 static void 1758 i40e_rm_fdir_filter_list(struct i40e_pf *pf) 1759 { 1760 struct i40e_fdir_filter *p_fdir; 1761 struct i40e_fdir_info *fdir_info; 1762 1763 fdir_info = &pf->fdir; 1764 /* Remove all flow director rules and hash */ 1765 if (fdir_info->hash_map) 1766 rte_free(fdir_info->hash_map); 1767 if (fdir_info->hash_table) 1768 rte_hash_free(fdir_info->hash_table); 1769 1770 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) { 1771 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules); 1772 rte_free(p_fdir); 1773 } 1774 } 1775 1776 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw) 1777 { 1778 /* 1779 * Disable by default flexible payload 1780 * for corresponding L2/L3/L4 layers. 1781 */ 1782 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000); 1783 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000); 1784 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000); 1785 } 1786 1787 static int 1788 eth_i40e_dev_uninit(struct rte_eth_dev *dev) 1789 { 1790 struct i40e_hw *hw; 1791 1792 PMD_INIT_FUNC_TRACE(); 1793 1794 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1795 return 0; 1796 1797 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1798 1799 if (hw->adapter_closed == 0) 1800 i40e_dev_close(dev); 1801 1802 return 0; 1803 } 1804 1805 static int 1806 i40e_dev_configure(struct rte_eth_dev *dev) 1807 { 1808 struct i40e_adapter *ad = 1809 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1812 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1813 int i, ret; 1814 1815 ret = i40e_dev_sync_phy_type(hw); 1816 if (ret) 1817 return ret; 1818 1819 /* Initialize to TRUE. If any of Rx queues doesn't meet the 1820 * bulk allocation or vector Rx preconditions we will reset it. 1821 */ 1822 ad->rx_bulk_alloc_allowed = true; 1823 ad->rx_vec_allowed = true; 1824 ad->tx_simple_allowed = true; 1825 ad->tx_vec_allowed = true; 1826 1827 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1828 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1829 1830 /* Only legacy filter API needs the following fdir config. So when the 1831 * legacy filter API is deprecated, the following codes should also be 1832 * removed. 1833 */ 1834 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) { 1835 ret = i40e_fdir_setup(pf); 1836 if (ret != I40E_SUCCESS) { 1837 PMD_DRV_LOG(ERR, "Failed to setup flow director."); 1838 return -ENOTSUP; 1839 } 1840 ret = i40e_fdir_configure(dev); 1841 if (ret < 0) { 1842 PMD_DRV_LOG(ERR, "failed to configure fdir."); 1843 goto err; 1844 } 1845 } else 1846 i40e_fdir_teardown(pf); 1847 1848 ret = i40e_dev_init_vlan(dev); 1849 if (ret < 0) 1850 goto err; 1851 1852 /* VMDQ setup. 1853 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and 1854 * RSS setting have different requirements. 1855 * General PMD driver call sequence are NIC init, configure, 1856 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it 1857 * will try to lookup the VSI that specific queue belongs to if VMDQ 1858 * applicable. So, VMDQ setting has to be done before 1859 * rx/tx_queue_setup(). This function is good to place vmdq_setup. 1860 * For RSS setting, it will try to calculate actual configured RX queue 1861 * number, which will be available after rx_queue_setup(). dev_start() 1862 * function is good to place RSS setup. 1863 */ 1864 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) { 1865 ret = i40e_vmdq_setup(dev); 1866 if (ret) 1867 goto err; 1868 } 1869 1870 if (mq_mode & ETH_MQ_RX_DCB_FLAG) { 1871 ret = i40e_dcb_setup(dev); 1872 if (ret) { 1873 PMD_DRV_LOG(ERR, "failed to configure DCB."); 1874 goto err_dcb; 1875 } 1876 } 1877 1878 TAILQ_INIT(&pf->flow_list); 1879 1880 return 0; 1881 1882 err_dcb: 1883 /* need to release vmdq resource if exists */ 1884 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 1885 i40e_vsi_release(pf->vmdq[i].vsi); 1886 pf->vmdq[i].vsi = NULL; 1887 } 1888 rte_free(pf->vmdq); 1889 pf->vmdq = NULL; 1890 err: 1891 /* Need to release fdir resource if exists. 1892 * Only legacy filter API needs the following fdir config. So when the 1893 * legacy filter API is deprecated, the following code should also be 1894 * removed. 1895 */ 1896 i40e_fdir_teardown(pf); 1897 return ret; 1898 } 1899 1900 void 1901 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi) 1902 { 1903 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1904 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1905 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1906 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1907 uint16_t msix_vect = vsi->msix_intr; 1908 uint16_t i; 1909 1910 for (i = 0; i < vsi->nb_qps; i++) { 1911 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); 1912 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); 1913 rte_wmb(); 1914 } 1915 1916 if (vsi->type != I40E_VSI_SRIOV) { 1917 if (!rte_intr_allow_others(intr_handle)) { 1918 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 1919 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); 1920 I40E_WRITE_REG(hw, 1921 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), 1922 0); 1923 } else { 1924 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 1925 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); 1926 I40E_WRITE_REG(hw, 1927 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, 1928 msix_vect - 1), 0); 1929 } 1930 } else { 1931 uint32_t reg; 1932 reg = (hw->func_caps.num_msix_vectors_vf - 1) * 1933 vsi->user_param + (msix_vect - 1); 1934 1935 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 1936 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK); 1937 } 1938 I40E_WRITE_FLUSH(hw); 1939 } 1940 1941 static void 1942 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect, 1943 int base_queue, int nb_queue, 1944 uint16_t itr_idx) 1945 { 1946 int i; 1947 uint32_t val; 1948 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1949 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 1950 1951 /* Bind all RX queues to allocated MSIX interrupt */ 1952 for (i = 0; i < nb_queue; i++) { 1953 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 1954 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT | 1955 ((base_queue + i + 1) << 1956 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 1957 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 1958 I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1959 1960 if (i == nb_queue - 1) 1961 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK; 1962 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val); 1963 } 1964 1965 /* Write first RX queue to Link list register as the head element */ 1966 if (vsi->type != I40E_VSI_SRIOV) { 1967 uint16_t interval = 1968 i40e_calc_itr_interval(1, pf->support_multi_driver); 1969 1970 if (msix_vect == I40E_MISC_VEC_ID) { 1971 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 1972 (base_queue << 1973 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 1974 (0x0 << 1975 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 1976 I40E_WRITE_REG(hw, 1977 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), 1978 interval); 1979 } else { 1980 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 1981 (base_queue << 1982 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 1983 (0x0 << 1984 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 1985 I40E_WRITE_REG(hw, 1986 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, 1987 msix_vect - 1), 1988 interval); 1989 } 1990 } else { 1991 uint32_t reg; 1992 1993 if (msix_vect == I40E_MISC_VEC_ID) { 1994 I40E_WRITE_REG(hw, 1995 I40E_VPINT_LNKLST0(vsi->user_param), 1996 (base_queue << 1997 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 1998 (0x0 << 1999 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 2000 } else { 2001 /* num_msix_vectors_vf needs to minus irq0 */ 2002 reg = (hw->func_caps.num_msix_vectors_vf - 1) * 2003 vsi->user_param + (msix_vect - 1); 2004 2005 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 2006 (base_queue << 2007 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 2008 (0x0 << 2009 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2010 } 2011 } 2012 2013 I40E_WRITE_FLUSH(hw); 2014 } 2015 2016 void 2017 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx) 2018 { 2019 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2020 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2021 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2022 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2023 uint16_t msix_vect = vsi->msix_intr; 2024 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 2025 uint16_t queue_idx = 0; 2026 int record = 0; 2027 int i; 2028 2029 for (i = 0; i < vsi->nb_qps; i++) { 2030 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); 2031 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); 2032 } 2033 2034 /* VF bind interrupt */ 2035 if (vsi->type == I40E_VSI_SRIOV) { 2036 __vsi_queues_bind_intr(vsi, msix_vect, 2037 vsi->base_queue, vsi->nb_qps, 2038 itr_idx); 2039 return; 2040 } 2041 2042 /* PF & VMDq bind interrupt */ 2043 if (rte_intr_dp_is_en(intr_handle)) { 2044 if (vsi->type == I40E_VSI_MAIN) { 2045 queue_idx = 0; 2046 record = 1; 2047 } else if (vsi->type == I40E_VSI_VMDQ2) { 2048 struct i40e_vsi *main_vsi = 2049 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter); 2050 queue_idx = vsi->base_queue - main_vsi->nb_qps; 2051 record = 1; 2052 } 2053 } 2054 2055 for (i = 0; i < vsi->nb_used_qps; i++) { 2056 if (nb_msix <= 1) { 2057 if (!rte_intr_allow_others(intr_handle)) 2058 /* allow to share MISC_VEC_ID */ 2059 msix_vect = I40E_MISC_VEC_ID; 2060 2061 /* no enough msix_vect, map all to one */ 2062 __vsi_queues_bind_intr(vsi, msix_vect, 2063 vsi->base_queue + i, 2064 vsi->nb_used_qps - i, 2065 itr_idx); 2066 for (; !!record && i < vsi->nb_used_qps; i++) 2067 intr_handle->intr_vec[queue_idx + i] = 2068 msix_vect; 2069 break; 2070 } 2071 /* 1:1 queue/msix_vect mapping */ 2072 __vsi_queues_bind_intr(vsi, msix_vect, 2073 vsi->base_queue + i, 1, 2074 itr_idx); 2075 if (!!record) 2076 intr_handle->intr_vec[queue_idx + i] = msix_vect; 2077 2078 msix_vect++; 2079 nb_msix--; 2080 } 2081 } 2082 2083 static void 2084 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi) 2085 { 2086 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2087 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2088 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2089 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2090 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 2091 uint16_t msix_intr, i; 2092 2093 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) 2094 for (i = 0; i < vsi->nb_msix; i++) { 2095 msix_intr = vsi->msix_intr + i; 2096 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), 2097 I40E_PFINT_DYN_CTLN_INTENA_MASK | 2098 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 2099 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 2100 } 2101 else 2102 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 2103 I40E_PFINT_DYN_CTL0_INTENA_MASK | 2104 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 2105 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 2106 2107 I40E_WRITE_FLUSH(hw); 2108 } 2109 2110 static void 2111 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi) 2112 { 2113 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2114 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2115 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2116 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2117 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 2118 uint16_t msix_intr, i; 2119 2120 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) 2121 for (i = 0; i < vsi->nb_msix; i++) { 2122 msix_intr = vsi->msix_intr + i; 2123 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), 2124 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 2125 } 2126 else 2127 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 2128 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 2129 2130 I40E_WRITE_FLUSH(hw); 2131 } 2132 2133 static inline uint8_t 2134 i40e_parse_link_speeds(uint16_t link_speeds) 2135 { 2136 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN; 2137 2138 if (link_speeds & ETH_LINK_SPEED_40G) 2139 link_speed |= I40E_LINK_SPEED_40GB; 2140 if (link_speeds & ETH_LINK_SPEED_25G) 2141 link_speed |= I40E_LINK_SPEED_25GB; 2142 if (link_speeds & ETH_LINK_SPEED_20G) 2143 link_speed |= I40E_LINK_SPEED_20GB; 2144 if (link_speeds & ETH_LINK_SPEED_10G) 2145 link_speed |= I40E_LINK_SPEED_10GB; 2146 if (link_speeds & ETH_LINK_SPEED_1G) 2147 link_speed |= I40E_LINK_SPEED_1GB; 2148 if (link_speeds & ETH_LINK_SPEED_100M) 2149 link_speed |= I40E_LINK_SPEED_100MB; 2150 2151 return link_speed; 2152 } 2153 2154 static int 2155 i40e_phy_conf_link(struct i40e_hw *hw, 2156 uint8_t abilities, 2157 uint8_t force_speed, 2158 bool is_up) 2159 { 2160 enum i40e_status_code status; 2161 struct i40e_aq_get_phy_abilities_resp phy_ab; 2162 struct i40e_aq_set_phy_config phy_conf; 2163 enum i40e_aq_phy_type cnt; 2164 uint8_t avail_speed; 2165 uint32_t phy_type_mask = 0; 2166 2167 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX | 2168 I40E_AQ_PHY_FLAG_PAUSE_RX | 2169 I40E_AQ_PHY_FLAG_PAUSE_RX | 2170 I40E_AQ_PHY_FLAG_LOW_POWER; 2171 int ret = -ENOTSUP; 2172 2173 /* To get phy capabilities of available speeds. */ 2174 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, 2175 NULL); 2176 if (status) { 2177 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n", 2178 status); 2179 return ret; 2180 } 2181 avail_speed = phy_ab.link_speed; 2182 2183 /* To get the current phy config. */ 2184 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab, 2185 NULL); 2186 if (status) { 2187 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n", 2188 status); 2189 return ret; 2190 } 2191 2192 /* If link needs to go up and it is in autoneg mode the speed is OK, 2193 * no need to set up again. 2194 */ 2195 if (is_up && phy_ab.phy_type != 0 && 2196 abilities & I40E_AQ_PHY_AN_ENABLED && 2197 phy_ab.link_speed != 0) 2198 return I40E_SUCCESS; 2199 2200 memset(&phy_conf, 0, sizeof(phy_conf)); 2201 2202 /* bits 0-2 use the values from get_phy_abilities_resp */ 2203 abilities &= ~mask; 2204 abilities |= phy_ab.abilities & mask; 2205 2206 phy_conf.abilities = abilities; 2207 2208 /* If link needs to go up, but the force speed is not supported, 2209 * Warn users and config the default available speeds. 2210 */ 2211 if (is_up && !(force_speed & avail_speed)) { 2212 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n"); 2213 phy_conf.link_speed = avail_speed; 2214 } else { 2215 phy_conf.link_speed = is_up ? force_speed : avail_speed; 2216 } 2217 2218 /* PHY type mask needs to include each type except PHY type extension */ 2219 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++) 2220 phy_type_mask |= 1 << cnt; 2221 2222 /* use get_phy_abilities_resp value for the rest */ 2223 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0; 2224 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR | 2225 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR | 2226 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0; 2227 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info; 2228 phy_conf.eee_capability = phy_ab.eee_capability; 2229 phy_conf.eeer = phy_ab.eeer_val; 2230 phy_conf.low_power_ctrl = phy_ab.d3_lpan; 2231 2232 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x", 2233 phy_ab.abilities, phy_ab.link_speed); 2234 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x", 2235 phy_conf.abilities, phy_conf.link_speed); 2236 2237 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL); 2238 if (status) 2239 return ret; 2240 2241 return I40E_SUCCESS; 2242 } 2243 2244 static int 2245 i40e_apply_link_speed(struct rte_eth_dev *dev) 2246 { 2247 uint8_t speed; 2248 uint8_t abilities = 0; 2249 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2250 struct rte_eth_conf *conf = &dev->data->dev_conf; 2251 2252 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK | 2253 I40E_AQ_PHY_LINK_ENABLED; 2254 2255 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) { 2256 conf->link_speeds = ETH_LINK_SPEED_40G | 2257 ETH_LINK_SPEED_25G | 2258 ETH_LINK_SPEED_20G | 2259 ETH_LINK_SPEED_10G | 2260 ETH_LINK_SPEED_1G | 2261 ETH_LINK_SPEED_100M; 2262 2263 abilities |= I40E_AQ_PHY_AN_ENABLED; 2264 } else { 2265 abilities &= ~I40E_AQ_PHY_AN_ENABLED; 2266 } 2267 speed = i40e_parse_link_speeds(conf->link_speeds); 2268 2269 return i40e_phy_conf_link(hw, abilities, speed, true); 2270 } 2271 2272 static int 2273 i40e_dev_start(struct rte_eth_dev *dev) 2274 { 2275 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2276 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2277 struct i40e_vsi *main_vsi = pf->main_vsi; 2278 int ret, i; 2279 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2280 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2281 uint32_t intr_vector = 0; 2282 struct i40e_vsi *vsi; 2283 uint16_t nb_rxq, nb_txq; 2284 2285 hw->adapter_stopped = 0; 2286 2287 rte_intr_disable(intr_handle); 2288 2289 if ((rte_intr_cap_multiple(intr_handle) || 2290 !RTE_ETH_DEV_SRIOV(dev).active) && 2291 dev->data->dev_conf.intr_conf.rxq != 0) { 2292 intr_vector = dev->data->nb_rx_queues; 2293 ret = rte_intr_efd_enable(intr_handle, intr_vector); 2294 if (ret) 2295 return ret; 2296 } 2297 2298 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2299 intr_handle->intr_vec = 2300 rte_zmalloc("intr_vec", 2301 dev->data->nb_rx_queues * sizeof(int), 2302 0); 2303 if (!intr_handle->intr_vec) { 2304 PMD_INIT_LOG(ERR, 2305 "Failed to allocate %d rx_queues intr_vec", 2306 dev->data->nb_rx_queues); 2307 return -ENOMEM; 2308 } 2309 } 2310 2311 /* Initialize VSI */ 2312 ret = i40e_dev_rxtx_init(pf); 2313 if (ret != I40E_SUCCESS) { 2314 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues"); 2315 return ret; 2316 } 2317 2318 /* Map queues with MSIX interrupt */ 2319 main_vsi->nb_used_qps = dev->data->nb_rx_queues - 2320 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 2321 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT); 2322 i40e_vsi_enable_queues_intr(main_vsi); 2323 2324 /* Map VMDQ VSI queues with MSIX interrupt */ 2325 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2326 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 2327 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi, 2328 I40E_ITR_INDEX_DEFAULT); 2329 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi); 2330 } 2331 2332 /* enable FDIR MSIX interrupt */ 2333 if (pf->fdir.fdir_vsi) { 2334 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi, 2335 I40E_ITR_INDEX_NONE); 2336 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi); 2337 } 2338 2339 /* Enable all queues which have been configured */ 2340 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) { 2341 ret = i40e_dev_rx_queue_start(dev, nb_rxq); 2342 if (ret) 2343 goto rx_err; 2344 } 2345 2346 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) { 2347 ret = i40e_dev_tx_queue_start(dev, nb_txq); 2348 if (ret) 2349 goto tx_err; 2350 } 2351 2352 /* Enable receiving broadcast packets */ 2353 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL); 2354 if (ret != I40E_SUCCESS) 2355 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2356 2357 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2358 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid, 2359 true, NULL); 2360 if (ret != I40E_SUCCESS) 2361 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2362 } 2363 2364 /* Enable the VLAN promiscuous mode. */ 2365 if (pf->vfs) { 2366 for (i = 0; i < pf->vf_num; i++) { 2367 vsi = pf->vfs[i].vsi; 2368 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, 2369 true, NULL); 2370 } 2371 } 2372 2373 /* Enable mac loopback mode */ 2374 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE || 2375 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) { 2376 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL); 2377 if (ret != I40E_SUCCESS) { 2378 PMD_DRV_LOG(ERR, "fail to set loopback link"); 2379 goto tx_err; 2380 } 2381 } 2382 2383 /* Apply link configure */ 2384 ret = i40e_apply_link_speed(dev); 2385 if (I40E_SUCCESS != ret) { 2386 PMD_DRV_LOG(ERR, "Fail to apply link setting"); 2387 goto tx_err; 2388 } 2389 2390 if (!rte_intr_allow_others(intr_handle)) { 2391 rte_intr_callback_unregister(intr_handle, 2392 i40e_dev_interrupt_handler, 2393 (void *)dev); 2394 /* configure and enable device interrupt */ 2395 i40e_pf_config_irq0(hw, FALSE); 2396 i40e_pf_enable_irq0(hw); 2397 2398 if (dev->data->dev_conf.intr_conf.lsc != 0) 2399 PMD_INIT_LOG(INFO, 2400 "lsc won't enable because of no intr multiplex"); 2401 } else { 2402 ret = i40e_aq_set_phy_int_mask(hw, 2403 ~(I40E_AQ_EVENT_LINK_UPDOWN | 2404 I40E_AQ_EVENT_MODULE_QUAL_FAIL | 2405 I40E_AQ_EVENT_MEDIA_NA), NULL); 2406 if (ret != I40E_SUCCESS) 2407 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 2408 2409 /* Call get_link_info aq commond to enable/disable LSE */ 2410 i40e_dev_link_update(dev, 0); 2411 } 2412 2413 if (dev->data->dev_conf.intr_conf.rxq == 0) { 2414 rte_eal_alarm_set(I40E_ALARM_INTERVAL, 2415 i40e_dev_alarm_handler, dev); 2416 } else { 2417 /* enable uio intr after callback register */ 2418 rte_intr_enable(intr_handle); 2419 } 2420 2421 i40e_filter_restore(pf); 2422 2423 if (pf->tm_conf.root && !pf->tm_conf.committed) 2424 PMD_DRV_LOG(WARNING, 2425 "please call hierarchy_commit() " 2426 "before starting the port"); 2427 2428 return I40E_SUCCESS; 2429 2430 tx_err: 2431 for (i = 0; i < nb_txq; i++) 2432 i40e_dev_tx_queue_stop(dev, i); 2433 rx_err: 2434 for (i = 0; i < nb_rxq; i++) 2435 i40e_dev_rx_queue_stop(dev, i); 2436 2437 return ret; 2438 } 2439 2440 static void 2441 i40e_dev_stop(struct rte_eth_dev *dev) 2442 { 2443 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2444 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2445 struct i40e_vsi *main_vsi = pf->main_vsi; 2446 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2447 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2448 int i; 2449 2450 if (hw->adapter_stopped == 1) 2451 return; 2452 2453 if (dev->data->dev_conf.intr_conf.rxq == 0) { 2454 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev); 2455 rte_intr_enable(intr_handle); 2456 } 2457 2458 /* Disable all queues */ 2459 for (i = 0; i < dev->data->nb_tx_queues; i++) 2460 i40e_dev_tx_queue_stop(dev, i); 2461 2462 for (i = 0; i < dev->data->nb_rx_queues; i++) 2463 i40e_dev_rx_queue_stop(dev, i); 2464 2465 /* un-map queues with interrupt registers */ 2466 i40e_vsi_disable_queues_intr(main_vsi); 2467 i40e_vsi_queues_unbind_intr(main_vsi); 2468 2469 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2470 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi); 2471 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi); 2472 } 2473 2474 if (pf->fdir.fdir_vsi) { 2475 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi); 2476 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi); 2477 } 2478 /* Clear all queues and release memory */ 2479 i40e_dev_clear_queues(dev); 2480 2481 /* Set link down */ 2482 i40e_dev_set_link_down(dev); 2483 2484 if (!rte_intr_allow_others(intr_handle)) 2485 /* resume to the default handler */ 2486 rte_intr_callback_register(intr_handle, 2487 i40e_dev_interrupt_handler, 2488 (void *)dev); 2489 2490 /* Clean datapath event and queue/vec mapping */ 2491 rte_intr_efd_disable(intr_handle); 2492 if (intr_handle->intr_vec) { 2493 rte_free(intr_handle->intr_vec); 2494 intr_handle->intr_vec = NULL; 2495 } 2496 2497 /* reset hierarchy commit */ 2498 pf->tm_conf.committed = false; 2499 2500 hw->adapter_stopped = 1; 2501 2502 pf->adapter->rss_reta_updated = 0; 2503 } 2504 2505 static void 2506 i40e_dev_close(struct rte_eth_dev *dev) 2507 { 2508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2509 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2510 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2511 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2512 struct i40e_mirror_rule *p_mirror; 2513 struct i40e_filter_control_settings settings; 2514 struct rte_flow *p_flow; 2515 uint32_t reg; 2516 int i; 2517 int ret; 2518 uint8_t aq_fail = 0; 2519 int retries = 0; 2520 2521 PMD_INIT_FUNC_TRACE(); 2522 2523 ret = rte_eth_switch_domain_free(pf->switch_domain_id); 2524 if (ret) 2525 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret); 2526 2527 2528 i40e_dev_stop(dev); 2529 2530 /* Remove all mirror rules */ 2531 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) { 2532 ret = i40e_aq_del_mirror_rule(hw, 2533 pf->main_vsi->veb->seid, 2534 p_mirror->rule_type, 2535 p_mirror->entries, 2536 p_mirror->num_entries, 2537 p_mirror->id); 2538 if (ret < 0) 2539 PMD_DRV_LOG(ERR, "failed to remove mirror rule: " 2540 "status = %d, aq_err = %d.", ret, 2541 hw->aq.asq_last_status); 2542 2543 /* remove mirror software resource anyway */ 2544 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules); 2545 rte_free(p_mirror); 2546 pf->nb_mirror_rule--; 2547 } 2548 2549 i40e_dev_free_queues(dev); 2550 2551 /* Disable interrupt */ 2552 i40e_pf_disable_irq0(hw); 2553 rte_intr_disable(intr_handle); 2554 2555 /* 2556 * Only legacy filter API needs the following fdir config. So when the 2557 * legacy filter API is deprecated, the following code should also be 2558 * removed. 2559 */ 2560 i40e_fdir_teardown(pf); 2561 2562 /* shutdown and destroy the HMC */ 2563 i40e_shutdown_lan_hmc(hw); 2564 2565 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2566 i40e_vsi_release(pf->vmdq[i].vsi); 2567 pf->vmdq[i].vsi = NULL; 2568 } 2569 rte_free(pf->vmdq); 2570 pf->vmdq = NULL; 2571 2572 /* release all the existing VSIs and VEBs */ 2573 i40e_vsi_release(pf->main_vsi); 2574 2575 /* shutdown the adminq */ 2576 i40e_aq_queue_shutdown(hw, true); 2577 i40e_shutdown_adminq(hw); 2578 2579 i40e_res_pool_destroy(&pf->qp_pool); 2580 i40e_res_pool_destroy(&pf->msix_pool); 2581 2582 /* Disable flexible payload in global configuration */ 2583 if (!pf->support_multi_driver) 2584 i40e_flex_payload_reg_set_default(hw); 2585 2586 /* force a PF reset to clean anything leftover */ 2587 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL); 2588 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL, 2589 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 2590 I40E_WRITE_FLUSH(hw); 2591 2592 dev->dev_ops = NULL; 2593 dev->rx_pkt_burst = NULL; 2594 dev->tx_pkt_burst = NULL; 2595 2596 /* Clear PXE mode */ 2597 i40e_clear_pxe_mode(hw); 2598 2599 /* Unconfigure filter control */ 2600 memset(&settings, 0, sizeof(settings)); 2601 ret = i40e_set_filter_control(hw, &settings); 2602 if (ret) 2603 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d", 2604 ret); 2605 2606 /* Disable flow control */ 2607 hw->fc.requested_mode = I40E_FC_NONE; 2608 i40e_set_fc(hw, &aq_fail, TRUE); 2609 2610 /* uninitialize pf host driver */ 2611 i40e_pf_host_uninit(dev); 2612 2613 do { 2614 ret = rte_intr_callback_unregister(intr_handle, 2615 i40e_dev_interrupt_handler, dev); 2616 if (ret >= 0 || ret == -ENOENT) { 2617 break; 2618 } else if (ret != -EAGAIN) { 2619 PMD_INIT_LOG(ERR, 2620 "intr callback unregister failed: %d", 2621 ret); 2622 } 2623 i40e_msec_delay(500); 2624 } while (retries++ < 5); 2625 2626 i40e_rm_ethtype_filter_list(pf); 2627 i40e_rm_tunnel_filter_list(pf); 2628 i40e_rm_fdir_filter_list(pf); 2629 2630 /* Remove all flows */ 2631 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) { 2632 TAILQ_REMOVE(&pf->flow_list, p_flow, node); 2633 rte_free(p_flow); 2634 } 2635 2636 /* Remove all Traffic Manager configuration */ 2637 i40e_tm_conf_uninit(dev); 2638 2639 hw->adapter_closed = 1; 2640 } 2641 2642 /* 2643 * Reset PF device only to re-initialize resources in PMD layer 2644 */ 2645 static int 2646 i40e_dev_reset(struct rte_eth_dev *dev) 2647 { 2648 int ret; 2649 2650 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2651 * its VF to make them align with it. The detailed notification 2652 * mechanism is PMD specific. As to i40e PF, it is rather complex. 2653 * To avoid unexpected behavior in VF, currently reset of PF with 2654 * SR-IOV activation is not supported. It might be supported later. 2655 */ 2656 if (dev->data->sriov.active) 2657 return -ENOTSUP; 2658 2659 ret = eth_i40e_dev_uninit(dev); 2660 if (ret) 2661 return ret; 2662 2663 ret = eth_i40e_dev_init(dev, NULL); 2664 2665 return ret; 2666 } 2667 2668 static int 2669 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev) 2670 { 2671 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2672 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2673 struct i40e_vsi *vsi = pf->main_vsi; 2674 int status; 2675 2676 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2677 true, NULL, true); 2678 if (status != I40E_SUCCESS) { 2679 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous"); 2680 return -EAGAIN; 2681 } 2682 2683 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, 2684 TRUE, NULL); 2685 if (status != I40E_SUCCESS) { 2686 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous"); 2687 /* Rollback unicast promiscuous mode */ 2688 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2689 false, NULL, true); 2690 return -EAGAIN; 2691 } 2692 2693 return 0; 2694 } 2695 2696 static int 2697 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev) 2698 { 2699 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2700 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2701 struct i40e_vsi *vsi = pf->main_vsi; 2702 int status; 2703 2704 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2705 false, NULL, true); 2706 if (status != I40E_SUCCESS) { 2707 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous"); 2708 return -EAGAIN; 2709 } 2710 2711 /* must remain in all_multicast mode */ 2712 if (dev->data->all_multicast == 1) 2713 return 0; 2714 2715 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, 2716 false, NULL); 2717 if (status != I40E_SUCCESS) { 2718 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous"); 2719 /* Rollback unicast promiscuous mode */ 2720 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2721 true, NULL, true); 2722 return -EAGAIN; 2723 } 2724 2725 return 0; 2726 } 2727 2728 static int 2729 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev) 2730 { 2731 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2732 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2733 struct i40e_vsi *vsi = pf->main_vsi; 2734 int ret; 2735 2736 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL); 2737 if (ret != I40E_SUCCESS) { 2738 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous"); 2739 return -EAGAIN; 2740 } 2741 2742 return 0; 2743 } 2744 2745 static int 2746 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev) 2747 { 2748 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2750 struct i40e_vsi *vsi = pf->main_vsi; 2751 int ret; 2752 2753 if (dev->data->promiscuous == 1) 2754 return 0; /* must remain in all_multicast mode */ 2755 2756 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, 2757 vsi->seid, FALSE, NULL); 2758 if (ret != I40E_SUCCESS) { 2759 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous"); 2760 return -EAGAIN; 2761 } 2762 2763 return 0; 2764 } 2765 2766 /* 2767 * Set device link up. 2768 */ 2769 static int 2770 i40e_dev_set_link_up(struct rte_eth_dev *dev) 2771 { 2772 /* re-apply link speed setting */ 2773 return i40e_apply_link_speed(dev); 2774 } 2775 2776 /* 2777 * Set device link down. 2778 */ 2779 static int 2780 i40e_dev_set_link_down(struct rte_eth_dev *dev) 2781 { 2782 uint8_t speed = I40E_LINK_SPEED_UNKNOWN; 2783 uint8_t abilities = 0; 2784 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2785 2786 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 2787 return i40e_phy_conf_link(hw, abilities, speed, false); 2788 } 2789 2790 static __rte_always_inline void 2791 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link) 2792 { 2793 /* Link status registers and values*/ 2794 #define I40E_PRTMAC_LINKSTA 0x001E2420 2795 #define I40E_REG_LINK_UP 0x40000080 2796 #define I40E_PRTMAC_MACC 0x001E24E0 2797 #define I40E_REG_MACC_25GB 0x00020000 2798 #define I40E_REG_SPEED_MASK 0x38000000 2799 #define I40E_REG_SPEED_0 0x00000000 2800 #define I40E_REG_SPEED_1 0x08000000 2801 #define I40E_REG_SPEED_2 0x10000000 2802 #define I40E_REG_SPEED_3 0x18000000 2803 #define I40E_REG_SPEED_4 0x20000000 2804 uint32_t link_speed; 2805 uint32_t reg_val; 2806 2807 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA); 2808 link_speed = reg_val & I40E_REG_SPEED_MASK; 2809 reg_val &= I40E_REG_LINK_UP; 2810 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0; 2811 2812 if (unlikely(link->link_status == 0)) 2813 return; 2814 2815 /* Parse the link status */ 2816 switch (link_speed) { 2817 case I40E_REG_SPEED_0: 2818 link->link_speed = ETH_SPEED_NUM_100M; 2819 break; 2820 case I40E_REG_SPEED_1: 2821 link->link_speed = ETH_SPEED_NUM_1G; 2822 break; 2823 case I40E_REG_SPEED_2: 2824 if (hw->mac.type == I40E_MAC_X722) 2825 link->link_speed = ETH_SPEED_NUM_2_5G; 2826 else 2827 link->link_speed = ETH_SPEED_NUM_10G; 2828 break; 2829 case I40E_REG_SPEED_3: 2830 if (hw->mac.type == I40E_MAC_X722) { 2831 link->link_speed = ETH_SPEED_NUM_5G; 2832 } else { 2833 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC); 2834 2835 if (reg_val & I40E_REG_MACC_25GB) 2836 link->link_speed = ETH_SPEED_NUM_25G; 2837 else 2838 link->link_speed = ETH_SPEED_NUM_40G; 2839 } 2840 break; 2841 case I40E_REG_SPEED_4: 2842 if (hw->mac.type == I40E_MAC_X722) 2843 link->link_speed = ETH_SPEED_NUM_10G; 2844 else 2845 link->link_speed = ETH_SPEED_NUM_20G; 2846 break; 2847 default: 2848 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed); 2849 break; 2850 } 2851 } 2852 2853 static __rte_always_inline void 2854 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link, 2855 bool enable_lse, int wait_to_complete) 2856 { 2857 #define CHECK_INTERVAL 100 /* 100ms */ 2858 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 2859 uint32_t rep_cnt = MAX_REPEAT_TIME; 2860 struct i40e_link_status link_status; 2861 int status; 2862 2863 memset(&link_status, 0, sizeof(link_status)); 2864 2865 do { 2866 memset(&link_status, 0, sizeof(link_status)); 2867 2868 /* Get link status information from hardware */ 2869 status = i40e_aq_get_link_info(hw, enable_lse, 2870 &link_status, NULL); 2871 if (unlikely(status != I40E_SUCCESS)) { 2872 link->link_speed = ETH_SPEED_NUM_NONE; 2873 link->link_duplex = ETH_LINK_FULL_DUPLEX; 2874 PMD_DRV_LOG(ERR, "Failed to get link info"); 2875 return; 2876 } 2877 2878 link->link_status = link_status.link_info & I40E_AQ_LINK_UP; 2879 if (!wait_to_complete || link->link_status) 2880 break; 2881 2882 rte_delay_ms(CHECK_INTERVAL); 2883 } while (--rep_cnt); 2884 2885 /* Parse the link status */ 2886 switch (link_status.link_speed) { 2887 case I40E_LINK_SPEED_100MB: 2888 link->link_speed = ETH_SPEED_NUM_100M; 2889 break; 2890 case I40E_LINK_SPEED_1GB: 2891 link->link_speed = ETH_SPEED_NUM_1G; 2892 break; 2893 case I40E_LINK_SPEED_10GB: 2894 link->link_speed = ETH_SPEED_NUM_10G; 2895 break; 2896 case I40E_LINK_SPEED_20GB: 2897 link->link_speed = ETH_SPEED_NUM_20G; 2898 break; 2899 case I40E_LINK_SPEED_25GB: 2900 link->link_speed = ETH_SPEED_NUM_25G; 2901 break; 2902 case I40E_LINK_SPEED_40GB: 2903 link->link_speed = ETH_SPEED_NUM_40G; 2904 break; 2905 default: 2906 link->link_speed = ETH_SPEED_NUM_NONE; 2907 break; 2908 } 2909 } 2910 2911 int 2912 i40e_dev_link_update(struct rte_eth_dev *dev, 2913 int wait_to_complete) 2914 { 2915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2916 struct rte_eth_link link; 2917 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2918 int ret; 2919 2920 memset(&link, 0, sizeof(link)); 2921 2922 /* i40e uses full duplex only */ 2923 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2924 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2925 ETH_LINK_SPEED_FIXED); 2926 2927 if (!wait_to_complete && !enable_lse) 2928 update_link_reg(hw, &link); 2929 else 2930 update_link_aq(hw, &link, enable_lse, wait_to_complete); 2931 2932 if (hw->switch_dev) 2933 rte_eth_linkstatus_get(hw->switch_dev, &link); 2934 2935 ret = rte_eth_linkstatus_set(dev, &link); 2936 i40e_notify_all_vfs_link_status(dev); 2937 2938 return ret; 2939 } 2940 2941 /* Get all the statistics of a VSI */ 2942 void 2943 i40e_update_vsi_stats(struct i40e_vsi *vsi) 2944 { 2945 struct i40e_eth_stats *oes = &vsi->eth_stats_offset; 2946 struct i40e_eth_stats *nes = &vsi->eth_stats; 2947 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2948 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx); 2949 2950 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx), 2951 vsi->offset_loaded, &oes->rx_bytes, 2952 &nes->rx_bytes); 2953 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx), 2954 vsi->offset_loaded, &oes->rx_unicast, 2955 &nes->rx_unicast); 2956 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx), 2957 vsi->offset_loaded, &oes->rx_multicast, 2958 &nes->rx_multicast); 2959 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx), 2960 vsi->offset_loaded, &oes->rx_broadcast, 2961 &nes->rx_broadcast); 2962 /* exclude CRC bytes */ 2963 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 2964 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 2965 2966 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded, 2967 &oes->rx_discards, &nes->rx_discards); 2968 /* GLV_REPC not supported */ 2969 /* GLV_RMPC not supported */ 2970 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded, 2971 &oes->rx_unknown_protocol, 2972 &nes->rx_unknown_protocol); 2973 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx), 2974 vsi->offset_loaded, &oes->tx_bytes, 2975 &nes->tx_bytes); 2976 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx), 2977 vsi->offset_loaded, &oes->tx_unicast, 2978 &nes->tx_unicast); 2979 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx), 2980 vsi->offset_loaded, &oes->tx_multicast, 2981 &nes->tx_multicast); 2982 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx), 2983 vsi->offset_loaded, &oes->tx_broadcast, 2984 &nes->tx_broadcast); 2985 /* GLV_TDPC not supported */ 2986 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded, 2987 &oes->tx_errors, &nes->tx_errors); 2988 vsi->offset_loaded = true; 2989 2990 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************", 2991 vsi->vsi_id); 2992 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 2993 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 2994 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 2995 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 2996 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 2997 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 2998 nes->rx_unknown_protocol); 2999 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 3000 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 3001 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 3002 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 3003 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 3004 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 3005 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************", 3006 vsi->vsi_id); 3007 } 3008 3009 static void 3010 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) 3011 { 3012 unsigned int i; 3013 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */ 3014 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */ 3015 3016 /* Get rx/tx bytes of internal transfer packets */ 3017 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port), 3018 I40E_GLV_GORCL(hw->port), 3019 pf->offset_loaded, 3020 &pf->internal_stats_offset.rx_bytes, 3021 &pf->internal_stats.rx_bytes); 3022 3023 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port), 3024 I40E_GLV_GOTCL(hw->port), 3025 pf->offset_loaded, 3026 &pf->internal_stats_offset.tx_bytes, 3027 &pf->internal_stats.tx_bytes); 3028 /* Get total internal rx packet count */ 3029 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port), 3030 I40E_GLV_UPRCL(hw->port), 3031 pf->offset_loaded, 3032 &pf->internal_stats_offset.rx_unicast, 3033 &pf->internal_stats.rx_unicast); 3034 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port), 3035 I40E_GLV_MPRCL(hw->port), 3036 pf->offset_loaded, 3037 &pf->internal_stats_offset.rx_multicast, 3038 &pf->internal_stats.rx_multicast); 3039 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port), 3040 I40E_GLV_BPRCL(hw->port), 3041 pf->offset_loaded, 3042 &pf->internal_stats_offset.rx_broadcast, 3043 &pf->internal_stats.rx_broadcast); 3044 /* Get total internal tx packet count */ 3045 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port), 3046 I40E_GLV_UPTCL(hw->port), 3047 pf->offset_loaded, 3048 &pf->internal_stats_offset.tx_unicast, 3049 &pf->internal_stats.tx_unicast); 3050 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port), 3051 I40E_GLV_MPTCL(hw->port), 3052 pf->offset_loaded, 3053 &pf->internal_stats_offset.tx_multicast, 3054 &pf->internal_stats.tx_multicast); 3055 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port), 3056 I40E_GLV_BPTCL(hw->port), 3057 pf->offset_loaded, 3058 &pf->internal_stats_offset.tx_broadcast, 3059 &pf->internal_stats.tx_broadcast); 3060 3061 /* exclude CRC size */ 3062 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast + 3063 pf->internal_stats.rx_multicast + 3064 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN; 3065 3066 /* Get statistics of struct i40e_eth_stats */ 3067 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port), 3068 I40E_GLPRT_GORCL(hw->port), 3069 pf->offset_loaded, &os->eth.rx_bytes, 3070 &ns->eth.rx_bytes); 3071 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port), 3072 I40E_GLPRT_UPRCL(hw->port), 3073 pf->offset_loaded, &os->eth.rx_unicast, 3074 &ns->eth.rx_unicast); 3075 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port), 3076 I40E_GLPRT_MPRCL(hw->port), 3077 pf->offset_loaded, &os->eth.rx_multicast, 3078 &ns->eth.rx_multicast); 3079 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port), 3080 I40E_GLPRT_BPRCL(hw->port), 3081 pf->offset_loaded, &os->eth.rx_broadcast, 3082 &ns->eth.rx_broadcast); 3083 /* Workaround: CRC size should not be included in byte statistics, 3084 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 3085 * packet. 3086 */ 3087 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 3088 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 3089 3090 /* exclude internal rx bytes 3091 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before 3092 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative 3093 * value. 3094 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L]. 3095 */ 3096 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes) 3097 ns->eth.rx_bytes = 0; 3098 else 3099 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes; 3100 3101 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast) 3102 ns->eth.rx_unicast = 0; 3103 else 3104 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast; 3105 3106 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast) 3107 ns->eth.rx_multicast = 0; 3108 else 3109 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast; 3110 3111 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast) 3112 ns->eth.rx_broadcast = 0; 3113 else 3114 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast; 3115 3116 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port), 3117 pf->offset_loaded, &os->eth.rx_discards, 3118 &ns->eth.rx_discards); 3119 /* GLPRT_REPC not supported */ 3120 /* GLPRT_RMPC not supported */ 3121 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port), 3122 pf->offset_loaded, 3123 &os->eth.rx_unknown_protocol, 3124 &ns->eth.rx_unknown_protocol); 3125 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port), 3126 I40E_GLPRT_GOTCL(hw->port), 3127 pf->offset_loaded, &os->eth.tx_bytes, 3128 &ns->eth.tx_bytes); 3129 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port), 3130 I40E_GLPRT_UPTCL(hw->port), 3131 pf->offset_loaded, &os->eth.tx_unicast, 3132 &ns->eth.tx_unicast); 3133 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port), 3134 I40E_GLPRT_MPTCL(hw->port), 3135 pf->offset_loaded, &os->eth.tx_multicast, 3136 &ns->eth.tx_multicast); 3137 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port), 3138 I40E_GLPRT_BPTCL(hw->port), 3139 pf->offset_loaded, &os->eth.tx_broadcast, 3140 &ns->eth.tx_broadcast); 3141 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 3142 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 3143 3144 /* exclude internal tx bytes 3145 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before 3146 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative 3147 * value. 3148 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L]. 3149 */ 3150 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes) 3151 ns->eth.tx_bytes = 0; 3152 else 3153 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes; 3154 3155 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast) 3156 ns->eth.tx_unicast = 0; 3157 else 3158 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast; 3159 3160 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast) 3161 ns->eth.tx_multicast = 0; 3162 else 3163 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast; 3164 3165 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast) 3166 ns->eth.tx_broadcast = 0; 3167 else 3168 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast; 3169 3170 /* GLPRT_TEPC not supported */ 3171 3172 /* additional port specific stats */ 3173 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port), 3174 pf->offset_loaded, &os->tx_dropped_link_down, 3175 &ns->tx_dropped_link_down); 3176 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port), 3177 pf->offset_loaded, &os->crc_errors, 3178 &ns->crc_errors); 3179 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port), 3180 pf->offset_loaded, &os->illegal_bytes, 3181 &ns->illegal_bytes); 3182 /* GLPRT_ERRBC not supported */ 3183 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port), 3184 pf->offset_loaded, &os->mac_local_faults, 3185 &ns->mac_local_faults); 3186 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port), 3187 pf->offset_loaded, &os->mac_remote_faults, 3188 &ns->mac_remote_faults); 3189 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port), 3190 pf->offset_loaded, &os->rx_length_errors, 3191 &ns->rx_length_errors); 3192 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port), 3193 pf->offset_loaded, &os->link_xon_rx, 3194 &ns->link_xon_rx); 3195 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 3196 pf->offset_loaded, &os->link_xoff_rx, 3197 &ns->link_xoff_rx); 3198 for (i = 0; i < 8; i++) { 3199 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i), 3200 pf->offset_loaded, 3201 &os->priority_xon_rx[i], 3202 &ns->priority_xon_rx[i]); 3203 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), 3204 pf->offset_loaded, 3205 &os->priority_xoff_rx[i], 3206 &ns->priority_xoff_rx[i]); 3207 } 3208 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port), 3209 pf->offset_loaded, &os->link_xon_tx, 3210 &ns->link_xon_tx); 3211 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 3212 pf->offset_loaded, &os->link_xoff_tx, 3213 &ns->link_xoff_tx); 3214 for (i = 0; i < 8; i++) { 3215 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i), 3216 pf->offset_loaded, 3217 &os->priority_xon_tx[i], 3218 &ns->priority_xon_tx[i]); 3219 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), 3220 pf->offset_loaded, 3221 &os->priority_xoff_tx[i], 3222 &ns->priority_xoff_tx[i]); 3223 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i), 3224 pf->offset_loaded, 3225 &os->priority_xon_2_xoff[i], 3226 &ns->priority_xon_2_xoff[i]); 3227 } 3228 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port), 3229 I40E_GLPRT_PRC64L(hw->port), 3230 pf->offset_loaded, &os->rx_size_64, 3231 &ns->rx_size_64); 3232 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port), 3233 I40E_GLPRT_PRC127L(hw->port), 3234 pf->offset_loaded, &os->rx_size_127, 3235 &ns->rx_size_127); 3236 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port), 3237 I40E_GLPRT_PRC255L(hw->port), 3238 pf->offset_loaded, &os->rx_size_255, 3239 &ns->rx_size_255); 3240 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port), 3241 I40E_GLPRT_PRC511L(hw->port), 3242 pf->offset_loaded, &os->rx_size_511, 3243 &ns->rx_size_511); 3244 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port), 3245 I40E_GLPRT_PRC1023L(hw->port), 3246 pf->offset_loaded, &os->rx_size_1023, 3247 &ns->rx_size_1023); 3248 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port), 3249 I40E_GLPRT_PRC1522L(hw->port), 3250 pf->offset_loaded, &os->rx_size_1522, 3251 &ns->rx_size_1522); 3252 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port), 3253 I40E_GLPRT_PRC9522L(hw->port), 3254 pf->offset_loaded, &os->rx_size_big, 3255 &ns->rx_size_big); 3256 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port), 3257 pf->offset_loaded, &os->rx_undersize, 3258 &ns->rx_undersize); 3259 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port), 3260 pf->offset_loaded, &os->rx_fragments, 3261 &ns->rx_fragments); 3262 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port), 3263 pf->offset_loaded, &os->rx_oversize, 3264 &ns->rx_oversize); 3265 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port), 3266 pf->offset_loaded, &os->rx_jabber, 3267 &ns->rx_jabber); 3268 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port), 3269 I40E_GLPRT_PTC64L(hw->port), 3270 pf->offset_loaded, &os->tx_size_64, 3271 &ns->tx_size_64); 3272 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port), 3273 I40E_GLPRT_PTC127L(hw->port), 3274 pf->offset_loaded, &os->tx_size_127, 3275 &ns->tx_size_127); 3276 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port), 3277 I40E_GLPRT_PTC255L(hw->port), 3278 pf->offset_loaded, &os->tx_size_255, 3279 &ns->tx_size_255); 3280 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port), 3281 I40E_GLPRT_PTC511L(hw->port), 3282 pf->offset_loaded, &os->tx_size_511, 3283 &ns->tx_size_511); 3284 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port), 3285 I40E_GLPRT_PTC1023L(hw->port), 3286 pf->offset_loaded, &os->tx_size_1023, 3287 &ns->tx_size_1023); 3288 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port), 3289 I40E_GLPRT_PTC1522L(hw->port), 3290 pf->offset_loaded, &os->tx_size_1522, 3291 &ns->tx_size_1522); 3292 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port), 3293 I40E_GLPRT_PTC9522L(hw->port), 3294 pf->offset_loaded, &os->tx_size_big, 3295 &ns->tx_size_big); 3296 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index), 3297 pf->offset_loaded, 3298 &os->fd_sb_match, &ns->fd_sb_match); 3299 /* GLPRT_MSPDC not supported */ 3300 /* GLPRT_XEC not supported */ 3301 3302 pf->offset_loaded = true; 3303 3304 if (pf->main_vsi) 3305 i40e_update_vsi_stats(pf->main_vsi); 3306 } 3307 3308 /* Get all statistics of a port */ 3309 static int 3310 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3311 { 3312 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3313 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3314 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */ 3315 struct i40e_vsi *vsi; 3316 unsigned i; 3317 3318 /* call read registers - updates values, now write them to struct */ 3319 i40e_read_stats_registers(pf, hw); 3320 3321 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 3322 pf->main_vsi->eth_stats.rx_multicast + 3323 pf->main_vsi->eth_stats.rx_broadcast - 3324 pf->main_vsi->eth_stats.rx_discards; 3325 stats->opackets = ns->eth.tx_unicast + 3326 ns->eth.tx_multicast + 3327 ns->eth.tx_broadcast; 3328 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 3329 stats->obytes = ns->eth.tx_bytes; 3330 stats->oerrors = ns->eth.tx_errors + 3331 pf->main_vsi->eth_stats.tx_errors; 3332 3333 /* Rx Errors */ 3334 stats->imissed = ns->eth.rx_discards + 3335 pf->main_vsi->eth_stats.rx_discards; 3336 stats->ierrors = ns->crc_errors + 3337 ns->rx_length_errors + ns->rx_undersize + 3338 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 3339 3340 if (pf->vfs) { 3341 for (i = 0; i < pf->vf_num; i++) { 3342 vsi = pf->vfs[i].vsi; 3343 i40e_update_vsi_stats(vsi); 3344 3345 stats->ipackets += (vsi->eth_stats.rx_unicast + 3346 vsi->eth_stats.rx_multicast + 3347 vsi->eth_stats.rx_broadcast - 3348 vsi->eth_stats.rx_discards); 3349 stats->ibytes += vsi->eth_stats.rx_bytes; 3350 stats->oerrors += vsi->eth_stats.tx_errors; 3351 stats->imissed += vsi->eth_stats.rx_discards; 3352 } 3353 } 3354 3355 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************"); 3356 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 3357 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 3358 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast); 3359 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast); 3360 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards); 3361 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3362 ns->eth.rx_unknown_protocol); 3363 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 3364 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 3365 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast); 3366 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast); 3367 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards); 3368 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 3369 3370 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 3371 ns->tx_dropped_link_down); 3372 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 3373 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 3374 ns->illegal_bytes); 3375 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 3376 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 3377 ns->mac_local_faults); 3378 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 3379 ns->mac_remote_faults); 3380 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"", 3381 ns->rx_length_errors); 3382 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 3383 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 3384 for (i = 0; i < 8; i++) { 3385 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"", 3386 i, ns->priority_xon_rx[i]); 3387 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"", 3388 i, ns->priority_xoff_rx[i]); 3389 } 3390 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 3391 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 3392 for (i = 0; i < 8; i++) { 3393 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"", 3394 i, ns->priority_xon_tx[i]); 3395 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"", 3396 i, ns->priority_xoff_tx[i]); 3397 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"", 3398 i, ns->priority_xon_2_xoff[i]); 3399 } 3400 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 3401 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 3402 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 3403 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 3404 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 3405 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 3406 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 3407 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 3408 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 3409 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 3410 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 3411 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 3412 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 3413 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 3414 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 3415 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 3416 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 3417 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 3418 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"", 3419 ns->mac_short_packet_dropped); 3420 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"", 3421 ns->checksum_error); 3422 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match); 3423 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************"); 3424 return 0; 3425 } 3426 3427 /* Reset the statistics */ 3428 static int 3429 i40e_dev_stats_reset(struct rte_eth_dev *dev) 3430 { 3431 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3432 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3433 3434 /* Mark PF and VSI stats to update the offset, aka "reset" */ 3435 pf->offset_loaded = false; 3436 if (pf->main_vsi) 3437 pf->main_vsi->offset_loaded = false; 3438 3439 /* read the stats, reading current register values into offset */ 3440 i40e_read_stats_registers(pf, hw); 3441 3442 return 0; 3443 } 3444 3445 static uint32_t 3446 i40e_xstats_calc_num(void) 3447 { 3448 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + 3449 (I40E_NB_RXQ_PRIO_XSTATS * 8) + 3450 (I40E_NB_TXQ_PRIO_XSTATS * 8); 3451 } 3452 3453 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3454 struct rte_eth_xstat_name *xstats_names, 3455 __rte_unused unsigned limit) 3456 { 3457 unsigned count = 0; 3458 unsigned i, prio; 3459 3460 if (xstats_names == NULL) 3461 return i40e_xstats_calc_num(); 3462 3463 /* Note: limit checked in rte_eth_xstats_names() */ 3464 3465 /* Get stats from i40e_eth_stats struct */ 3466 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) { 3467 strlcpy(xstats_names[count].name, 3468 rte_i40e_stats_strings[i].name, 3469 sizeof(xstats_names[count].name)); 3470 count++; 3471 } 3472 3473 /* Get individiual stats from i40e_hw_port struct */ 3474 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) { 3475 strlcpy(xstats_names[count].name, 3476 rte_i40e_hw_port_strings[i].name, 3477 sizeof(xstats_names[count].name)); 3478 count++; 3479 } 3480 3481 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) { 3482 for (prio = 0; prio < 8; prio++) { 3483 snprintf(xstats_names[count].name, 3484 sizeof(xstats_names[count].name), 3485 "rx_priority%u_%s", prio, 3486 rte_i40e_rxq_prio_strings[i].name); 3487 count++; 3488 } 3489 } 3490 3491 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) { 3492 for (prio = 0; prio < 8; prio++) { 3493 snprintf(xstats_names[count].name, 3494 sizeof(xstats_names[count].name), 3495 "tx_priority%u_%s", prio, 3496 rte_i40e_txq_prio_strings[i].name); 3497 count++; 3498 } 3499 } 3500 return count; 3501 } 3502 3503 static int 3504 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3505 unsigned n) 3506 { 3507 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3508 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3509 unsigned i, count, prio; 3510 struct i40e_hw_port_stats *hw_stats = &pf->stats; 3511 3512 count = i40e_xstats_calc_num(); 3513 if (n < count) 3514 return count; 3515 3516 i40e_read_stats_registers(pf, hw); 3517 3518 if (xstats == NULL) 3519 return 0; 3520 3521 count = 0; 3522 3523 /* Get stats from i40e_eth_stats struct */ 3524 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) { 3525 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) + 3526 rte_i40e_stats_strings[i].offset); 3527 xstats[count].id = count; 3528 count++; 3529 } 3530 3531 /* Get individiual stats from i40e_hw_port struct */ 3532 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) { 3533 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3534 rte_i40e_hw_port_strings[i].offset); 3535 xstats[count].id = count; 3536 count++; 3537 } 3538 3539 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) { 3540 for (prio = 0; prio < 8; prio++) { 3541 xstats[count].value = 3542 *(uint64_t *)(((char *)hw_stats) + 3543 rte_i40e_rxq_prio_strings[i].offset + 3544 (sizeof(uint64_t) * prio)); 3545 xstats[count].id = count; 3546 count++; 3547 } 3548 } 3549 3550 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) { 3551 for (prio = 0; prio < 8; prio++) { 3552 xstats[count].value = 3553 *(uint64_t *)(((char *)hw_stats) + 3554 rte_i40e_txq_prio_strings[i].offset + 3555 (sizeof(uint64_t) * prio)); 3556 xstats[count].id = count; 3557 count++; 3558 } 3559 } 3560 3561 return count; 3562 } 3563 3564 static int 3565 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3566 { 3567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3568 u32 full_ver; 3569 u8 ver, patch; 3570 u16 build; 3571 int ret; 3572 3573 full_ver = hw->nvm.oem_ver; 3574 ver = (u8)(full_ver >> 24); 3575 build = (u16)((full_ver >> 8) & 0xffff); 3576 patch = (u8)(full_ver & 0xff); 3577 3578 ret = snprintf(fw_version, fw_size, 3579 "%d.%d%d 0x%08x %d.%d.%d", 3580 ((hw->nvm.version >> 12) & 0xf), 3581 ((hw->nvm.version >> 4) & 0xff), 3582 (hw->nvm.version & 0xf), hw->nvm.eetrack, 3583 ver, build, patch); 3584 3585 ret += 1; /* add the size of '\0' */ 3586 if (fw_size < (u32)ret) 3587 return ret; 3588 else 3589 return 0; 3590 } 3591 3592 /* 3593 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later, 3594 * the Rx data path does not hang if the FW LLDP is stopped. 3595 * return true if lldp need to stop 3596 * return false if we cannot disable the LLDP to avoid Rx data path blocking. 3597 */ 3598 static bool 3599 i40e_need_stop_lldp(struct rte_eth_dev *dev) 3600 { 3601 double nvm_ver; 3602 char ver_str[64] = {0}; 3603 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3604 3605 i40e_fw_version_get(dev, ver_str, 64); 3606 nvm_ver = atof(ver_str); 3607 if ((hw->mac.type == I40E_MAC_X722 || 3608 hw->mac.type == I40E_MAC_X722_VF) && 3609 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000))) 3610 return true; 3611 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000)) 3612 return true; 3613 3614 return false; 3615 } 3616 3617 static int 3618 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3619 { 3620 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3621 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3622 struct i40e_vsi *vsi = pf->main_vsi; 3623 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3624 3625 dev_info->max_rx_queues = vsi->nb_qps; 3626 dev_info->max_tx_queues = vsi->nb_qps; 3627 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN; 3628 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX; 3629 dev_info->max_mac_addrs = vsi->max_macaddrs; 3630 dev_info->max_vfs = pci_dev->max_vfs; 3631 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD; 3632 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3633 dev_info->rx_queue_offload_capa = 0; 3634 dev_info->rx_offload_capa = 3635 DEV_RX_OFFLOAD_VLAN_STRIP | 3636 DEV_RX_OFFLOAD_QINQ_STRIP | 3637 DEV_RX_OFFLOAD_IPV4_CKSUM | 3638 DEV_RX_OFFLOAD_UDP_CKSUM | 3639 DEV_RX_OFFLOAD_TCP_CKSUM | 3640 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3641 DEV_RX_OFFLOAD_KEEP_CRC | 3642 DEV_RX_OFFLOAD_SCATTER | 3643 DEV_RX_OFFLOAD_VLAN_EXTEND | 3644 DEV_RX_OFFLOAD_VLAN_FILTER | 3645 DEV_RX_OFFLOAD_JUMBO_FRAME | 3646 DEV_RX_OFFLOAD_RSS_HASH; 3647 3648 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3649 dev_info->tx_offload_capa = 3650 DEV_TX_OFFLOAD_VLAN_INSERT | 3651 DEV_TX_OFFLOAD_QINQ_INSERT | 3652 DEV_TX_OFFLOAD_IPV4_CKSUM | 3653 DEV_TX_OFFLOAD_UDP_CKSUM | 3654 DEV_TX_OFFLOAD_TCP_CKSUM | 3655 DEV_TX_OFFLOAD_SCTP_CKSUM | 3656 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3657 DEV_TX_OFFLOAD_TCP_TSO | 3658 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 3659 DEV_TX_OFFLOAD_GRE_TNL_TSO | 3660 DEV_TX_OFFLOAD_IPIP_TNL_TSO | 3661 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 3662 DEV_TX_OFFLOAD_MULTI_SEGS | 3663 dev_info->tx_queue_offload_capa; 3664 dev_info->dev_capa = 3665 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 3666 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 3667 3668 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 3669 sizeof(uint32_t); 3670 dev_info->reta_size = pf->hash_lut_size; 3671 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask; 3672 3673 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3674 .rx_thresh = { 3675 .pthresh = I40E_DEFAULT_RX_PTHRESH, 3676 .hthresh = I40E_DEFAULT_RX_HTHRESH, 3677 .wthresh = I40E_DEFAULT_RX_WTHRESH, 3678 }, 3679 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH, 3680 .rx_drop_en = 0, 3681 .offloads = 0, 3682 }; 3683 3684 dev_info->default_txconf = (struct rte_eth_txconf) { 3685 .tx_thresh = { 3686 .pthresh = I40E_DEFAULT_TX_PTHRESH, 3687 .hthresh = I40E_DEFAULT_TX_HTHRESH, 3688 .wthresh = I40E_DEFAULT_TX_WTHRESH, 3689 }, 3690 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH, 3691 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH, 3692 .offloads = 0, 3693 }; 3694 3695 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3696 .nb_max = I40E_MAX_RING_DESC, 3697 .nb_min = I40E_MIN_RING_DESC, 3698 .nb_align = I40E_ALIGN_RING_DESC, 3699 }; 3700 3701 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3702 .nb_max = I40E_MAX_RING_DESC, 3703 .nb_min = I40E_MIN_RING_DESC, 3704 .nb_align = I40E_ALIGN_RING_DESC, 3705 .nb_seg_max = I40E_TX_MAX_SEG, 3706 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG, 3707 }; 3708 3709 if (pf->flags & I40E_FLAG_VMDQ) { 3710 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi; 3711 dev_info->vmdq_queue_base = dev_info->max_rx_queues; 3712 dev_info->vmdq_queue_num = pf->vmdq_nb_qps * 3713 pf->max_nb_vmdq_vsi; 3714 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE; 3715 dev_info->max_rx_queues += dev_info->vmdq_queue_num; 3716 dev_info->max_tx_queues += dev_info->vmdq_queue_num; 3717 } 3718 3719 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { 3720 /* For XL710 */ 3721 dev_info->speed_capa = ETH_LINK_SPEED_40G; 3722 dev_info->default_rxportconf.nb_queues = 2; 3723 dev_info->default_txportconf.nb_queues = 2; 3724 if (dev->data->nb_rx_queues == 1) 3725 dev_info->default_rxportconf.ring_size = 2048; 3726 else 3727 dev_info->default_rxportconf.ring_size = 1024; 3728 if (dev->data->nb_tx_queues == 1) 3729 dev_info->default_txportconf.ring_size = 1024; 3730 else 3731 dev_info->default_txportconf.ring_size = 512; 3732 3733 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) { 3734 /* For XXV710 */ 3735 dev_info->speed_capa = ETH_LINK_SPEED_25G; 3736 dev_info->default_rxportconf.nb_queues = 1; 3737 dev_info->default_txportconf.nb_queues = 1; 3738 dev_info->default_rxportconf.ring_size = 256; 3739 dev_info->default_txportconf.ring_size = 256; 3740 } else { 3741 /* For X710 */ 3742 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3743 dev_info->default_rxportconf.nb_queues = 1; 3744 dev_info->default_txportconf.nb_queues = 1; 3745 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) { 3746 dev_info->default_rxportconf.ring_size = 512; 3747 dev_info->default_txportconf.ring_size = 256; 3748 } else { 3749 dev_info->default_rxportconf.ring_size = 256; 3750 dev_info->default_txportconf.ring_size = 256; 3751 } 3752 } 3753 dev_info->default_rxportconf.burst_size = 32; 3754 dev_info->default_txportconf.burst_size = 32; 3755 3756 return 0; 3757 } 3758 3759 static int 3760 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3761 { 3762 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3763 struct i40e_vsi *vsi = pf->main_vsi; 3764 PMD_INIT_FUNC_TRACE(); 3765 3766 if (on) 3767 return i40e_vsi_add_vlan(vsi, vlan_id); 3768 else 3769 return i40e_vsi_delete_vlan(vsi, vlan_id); 3770 } 3771 3772 static int 3773 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev, 3774 enum rte_vlan_type vlan_type, 3775 uint16_t tpid, int qinq) 3776 { 3777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3778 uint64_t reg_r = 0; 3779 uint64_t reg_w = 0; 3780 uint16_t reg_id = 3; 3781 int ret; 3782 3783 if (qinq) { 3784 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3785 reg_id = 2; 3786 } 3787 3788 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), 3789 ®_r, NULL); 3790 if (ret != I40E_SUCCESS) { 3791 PMD_DRV_LOG(ERR, 3792 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]", 3793 reg_id); 3794 return -EIO; 3795 } 3796 PMD_DRV_LOG(DEBUG, 3797 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64, 3798 reg_id, reg_r); 3799 3800 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK)); 3801 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT); 3802 if (reg_r == reg_w) { 3803 PMD_DRV_LOG(DEBUG, "No need to write"); 3804 return 0; 3805 } 3806 3807 ret = i40e_aq_debug_write_global_register(hw, 3808 I40E_GL_SWT_L2TAGCTRL(reg_id), 3809 reg_w, NULL); 3810 if (ret != I40E_SUCCESS) { 3811 PMD_DRV_LOG(ERR, 3812 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]", 3813 reg_id); 3814 return -EIO; 3815 } 3816 PMD_DRV_LOG(DEBUG, 3817 "Global register 0x%08x is changed with value 0x%08x", 3818 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w); 3819 3820 return 0; 3821 } 3822 3823 static int 3824 i40e_vlan_tpid_set(struct rte_eth_dev *dev, 3825 enum rte_vlan_type vlan_type, 3826 uint16_t tpid) 3827 { 3828 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3829 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3830 int qinq = dev->data->dev_conf.rxmode.offloads & 3831 DEV_RX_OFFLOAD_VLAN_EXTEND; 3832 int ret = 0; 3833 3834 if ((vlan_type != ETH_VLAN_TYPE_INNER && 3835 vlan_type != ETH_VLAN_TYPE_OUTER) || 3836 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) { 3837 PMD_DRV_LOG(ERR, 3838 "Unsupported vlan type."); 3839 return -EINVAL; 3840 } 3841 3842 if (pf->support_multi_driver) { 3843 PMD_DRV_LOG(ERR, "Setting TPID is not supported."); 3844 return -ENOTSUP; 3845 } 3846 3847 /* 802.1ad frames ability is added in NVM API 1.7*/ 3848 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 3849 if (qinq) { 3850 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3851 hw->first_tag = rte_cpu_to_le_16(tpid); 3852 else if (vlan_type == ETH_VLAN_TYPE_INNER) 3853 hw->second_tag = rte_cpu_to_le_16(tpid); 3854 } else { 3855 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3856 hw->second_tag = rte_cpu_to_le_16(tpid); 3857 } 3858 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL); 3859 if (ret != I40E_SUCCESS) { 3860 PMD_DRV_LOG(ERR, 3861 "Set switch config failed aq_err: %d", 3862 hw->aq.asq_last_status); 3863 ret = -EIO; 3864 } 3865 } else 3866 /* If NVM API < 1.7, keep the register setting */ 3867 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type, 3868 tpid, qinq); 3869 3870 return ret; 3871 } 3872 3873 static int 3874 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) 3875 { 3876 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3877 struct i40e_vsi *vsi = pf->main_vsi; 3878 struct rte_eth_rxmode *rxmode; 3879 3880 if (mask & ETH_QINQ_STRIP_MASK) { 3881 PMD_DRV_LOG(ERR, "Strip qinq is not supported."); 3882 return -ENOTSUP; 3883 } 3884 3885 rxmode = &dev->data->dev_conf.rxmode; 3886 if (mask & ETH_VLAN_FILTER_MASK) { 3887 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 3888 i40e_vsi_config_vlan_filter(vsi, TRUE); 3889 else 3890 i40e_vsi_config_vlan_filter(vsi, FALSE); 3891 } 3892 3893 if (mask & ETH_VLAN_STRIP_MASK) { 3894 /* Enable or disable VLAN stripping */ 3895 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 3896 i40e_vsi_config_vlan_stripping(vsi, TRUE); 3897 else 3898 i40e_vsi_config_vlan_stripping(vsi, FALSE); 3899 } 3900 3901 if (mask & ETH_VLAN_EXTEND_MASK) { 3902 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) { 3903 i40e_vsi_config_double_vlan(vsi, TRUE); 3904 /* Set global registers with default ethertype. */ 3905 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 3906 RTE_ETHER_TYPE_VLAN); 3907 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, 3908 RTE_ETHER_TYPE_VLAN); 3909 } 3910 else 3911 i40e_vsi_config_double_vlan(vsi, FALSE); 3912 } 3913 3914 return 0; 3915 } 3916 3917 static void 3918 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev, 3919 __rte_unused uint16_t queue, 3920 __rte_unused int on) 3921 { 3922 PMD_INIT_FUNC_TRACE(); 3923 } 3924 3925 static int 3926 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 3927 { 3928 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3929 struct i40e_vsi *vsi = pf->main_vsi; 3930 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi); 3931 struct i40e_vsi_vlan_pvid_info info; 3932 3933 memset(&info, 0, sizeof(info)); 3934 info.on = on; 3935 if (info.on) 3936 info.config.pvid = pvid; 3937 else { 3938 info.config.reject.tagged = 3939 data->dev_conf.txmode.hw_vlan_reject_tagged; 3940 info.config.reject.untagged = 3941 data->dev_conf.txmode.hw_vlan_reject_untagged; 3942 } 3943 3944 return i40e_vsi_vlan_pvid_set(vsi, &info); 3945 } 3946 3947 static int 3948 i40e_dev_led_on(struct rte_eth_dev *dev) 3949 { 3950 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3951 uint32_t mode = i40e_led_get(hw); 3952 3953 if (mode == 0) 3954 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */ 3955 3956 return 0; 3957 } 3958 3959 static int 3960 i40e_dev_led_off(struct rte_eth_dev *dev) 3961 { 3962 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3963 uint32_t mode = i40e_led_get(hw); 3964 3965 if (mode != 0) 3966 i40e_led_set(hw, 0, false); 3967 3968 return 0; 3969 } 3970 3971 static int 3972 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3973 { 3974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3975 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3976 3977 fc_conf->pause_time = pf->fc_conf.pause_time; 3978 3979 /* read out from register, in case they are modified by other port */ 3980 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = 3981 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT; 3982 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = 3983 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT; 3984 3985 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]; 3986 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]; 3987 3988 /* Return current mode according to actual setting*/ 3989 switch (hw->fc.current_mode) { 3990 case I40E_FC_FULL: 3991 fc_conf->mode = RTE_FC_FULL; 3992 break; 3993 case I40E_FC_TX_PAUSE: 3994 fc_conf->mode = RTE_FC_TX_PAUSE; 3995 break; 3996 case I40E_FC_RX_PAUSE: 3997 fc_conf->mode = RTE_FC_RX_PAUSE; 3998 break; 3999 case I40E_FC_NONE: 4000 default: 4001 fc_conf->mode = RTE_FC_NONE; 4002 }; 4003 4004 return 0; 4005 } 4006 4007 static int 4008 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4009 { 4010 uint32_t mflcn_reg, fctrl_reg, reg; 4011 uint32_t max_high_water; 4012 uint8_t i, aq_failure; 4013 int err; 4014 struct i40e_hw *hw; 4015 struct i40e_pf *pf; 4016 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = { 4017 [RTE_FC_NONE] = I40E_FC_NONE, 4018 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE, 4019 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE, 4020 [RTE_FC_FULL] = I40E_FC_FULL 4021 }; 4022 4023 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */ 4024 4025 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT; 4026 if ((fc_conf->high_water > max_high_water) || 4027 (fc_conf->high_water < fc_conf->low_water)) { 4028 PMD_INIT_LOG(ERR, 4029 "Invalid high/low water setup value in KB, High_water must be <= %d.", 4030 max_high_water); 4031 return -EINVAL; 4032 } 4033 4034 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4035 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4036 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode]; 4037 4038 pf->fc_conf.pause_time = fc_conf->pause_time; 4039 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water; 4040 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water; 4041 4042 PMD_INIT_FUNC_TRACE(); 4043 4044 /* All the link flow control related enable/disable register 4045 * configuration is handle by the F/W 4046 */ 4047 err = i40e_set_fc(hw, &aq_failure, true); 4048 if (err < 0) 4049 return -ENOSYS; 4050 4051 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { 4052 /* Configure flow control refresh threshold, 4053 * the value for stat_tx_pause_refresh_timer[8] 4054 * is used for global pause operation. 4055 */ 4056 4057 I40E_WRITE_REG(hw, 4058 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8), 4059 pf->fc_conf.pause_time); 4060 4061 /* configure the timer value included in transmitted pause 4062 * frame, 4063 * the value for stat_tx_pause_quanta[8] is used for global 4064 * pause operation 4065 */ 4066 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8), 4067 pf->fc_conf.pause_time); 4068 4069 fctrl_reg = I40E_READ_REG(hw, 4070 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL); 4071 4072 if (fc_conf->mac_ctrl_frame_fwd != 0) 4073 fctrl_reg |= I40E_PRTMAC_FWD_CTRL; 4074 else 4075 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL; 4076 4077 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL, 4078 fctrl_reg); 4079 } else { 4080 /* Configure pause time (2 TCs per register) */ 4081 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001; 4082 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++) 4083 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg); 4084 4085 /* Configure flow control refresh threshold value */ 4086 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV, 4087 pf->fc_conf.pause_time / 2); 4088 4089 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); 4090 4091 /* set or clear MFLCN.PMCF & MFLCN.DPF bits 4092 *depending on configuration 4093 */ 4094 if (fc_conf->mac_ctrl_frame_fwd != 0) { 4095 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK; 4096 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK; 4097 } else { 4098 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK; 4099 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK; 4100 } 4101 4102 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg); 4103 } 4104 4105 if (!pf->support_multi_driver) { 4106 /* config water marker both based on the packets and bytes */ 4107 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW, 4108 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] 4109 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE); 4110 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW, 4111 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] 4112 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE); 4113 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW, 4114 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] 4115 << I40E_KILOSHIFT); 4116 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW, 4117 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] 4118 << I40E_KILOSHIFT); 4119 } else { 4120 PMD_DRV_LOG(ERR, 4121 "Water marker configuration is not supported."); 4122 } 4123 4124 I40E_WRITE_FLUSH(hw); 4125 4126 return 0; 4127 } 4128 4129 static int 4130 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev, 4131 __rte_unused struct rte_eth_pfc_conf *pfc_conf) 4132 { 4133 PMD_INIT_FUNC_TRACE(); 4134 4135 return -ENOSYS; 4136 } 4137 4138 /* Add a MAC address, and update filters */ 4139 static int 4140 i40e_macaddr_add(struct rte_eth_dev *dev, 4141 struct rte_ether_addr *mac_addr, 4142 __rte_unused uint32_t index, 4143 uint32_t pool) 4144 { 4145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4146 struct i40e_mac_filter_info mac_filter; 4147 struct i40e_vsi *vsi; 4148 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 4149 int ret; 4150 4151 /* If VMDQ not enabled or configured, return */ 4152 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) || 4153 !pf->nb_cfg_vmdq_vsi)) { 4154 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u", 4155 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled", 4156 pool); 4157 return -ENOTSUP; 4158 } 4159 4160 if (pool > pf->nb_cfg_vmdq_vsi) { 4161 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u", 4162 pool, pf->nb_cfg_vmdq_vsi); 4163 return -EINVAL; 4164 } 4165 4166 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN); 4167 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 4168 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 4169 else 4170 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH; 4171 4172 if (pool == 0) 4173 vsi = pf->main_vsi; 4174 else 4175 vsi = pf->vmdq[pool - 1].vsi; 4176 4177 ret = i40e_vsi_add_mac(vsi, &mac_filter); 4178 if (ret != I40E_SUCCESS) { 4179 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter"); 4180 return -ENODEV; 4181 } 4182 return 0; 4183 } 4184 4185 /* Remove a MAC address, and update filters */ 4186 static void 4187 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 4188 { 4189 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4190 struct i40e_vsi *vsi; 4191 struct rte_eth_dev_data *data = dev->data; 4192 struct rte_ether_addr *macaddr; 4193 int ret; 4194 uint32_t i; 4195 uint64_t pool_sel; 4196 4197 macaddr = &(data->mac_addrs[index]); 4198 4199 pool_sel = dev->data->mac_pool_sel[index]; 4200 4201 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) { 4202 if (pool_sel & (1ULL << i)) { 4203 if (i == 0) 4204 vsi = pf->main_vsi; 4205 else { 4206 /* No VMDQ pool enabled or configured */ 4207 if (!(pf->flags & I40E_FLAG_VMDQ) || 4208 (i > pf->nb_cfg_vmdq_vsi)) { 4209 PMD_DRV_LOG(ERR, 4210 "No VMDQ pool enabled/configured"); 4211 return; 4212 } 4213 vsi = pf->vmdq[i - 1].vsi; 4214 } 4215 ret = i40e_vsi_delete_mac(vsi, macaddr); 4216 4217 if (ret) { 4218 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter"); 4219 return; 4220 } 4221 } 4222 } 4223 } 4224 4225 /* Set perfect match or hash match of MAC and VLAN for a VF */ 4226 static int 4227 i40e_vf_mac_filter_set(struct i40e_pf *pf, 4228 struct rte_eth_mac_filter *filter, 4229 bool add) 4230 { 4231 struct i40e_hw *hw; 4232 struct i40e_mac_filter_info mac_filter; 4233 struct rte_ether_addr old_mac; 4234 struct rte_ether_addr *new_mac; 4235 struct i40e_pf_vf *vf = NULL; 4236 uint16_t vf_id; 4237 int ret; 4238 4239 if (pf == NULL) { 4240 PMD_DRV_LOG(ERR, "Invalid PF argument."); 4241 return -EINVAL; 4242 } 4243 hw = I40E_PF_TO_HW(pf); 4244 4245 if (filter == NULL) { 4246 PMD_DRV_LOG(ERR, "Invalid mac filter argument."); 4247 return -EINVAL; 4248 } 4249 4250 new_mac = &filter->mac_addr; 4251 4252 if (rte_is_zero_ether_addr(new_mac)) { 4253 PMD_DRV_LOG(ERR, "Invalid ethernet address."); 4254 return -EINVAL; 4255 } 4256 4257 vf_id = filter->dst_id; 4258 4259 if (vf_id > pf->vf_num - 1 || !pf->vfs) { 4260 PMD_DRV_LOG(ERR, "Invalid argument."); 4261 return -EINVAL; 4262 } 4263 vf = &pf->vfs[vf_id]; 4264 4265 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) { 4266 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address."); 4267 return -EINVAL; 4268 } 4269 4270 if (add) { 4271 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN); 4272 rte_memcpy(hw->mac.addr, new_mac->addr_bytes, 4273 RTE_ETHER_ADDR_LEN); 4274 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr, 4275 RTE_ETHER_ADDR_LEN); 4276 4277 mac_filter.filter_type = filter->filter_type; 4278 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter); 4279 if (ret != I40E_SUCCESS) { 4280 PMD_DRV_LOG(ERR, "Failed to add MAC filter."); 4281 return -1; 4282 } 4283 rte_ether_addr_copy(new_mac, &pf->dev_addr); 4284 } else { 4285 rte_memcpy(hw->mac.addr, hw->mac.perm_addr, 4286 RTE_ETHER_ADDR_LEN); 4287 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr); 4288 if (ret != I40E_SUCCESS) { 4289 PMD_DRV_LOG(ERR, "Failed to delete MAC filter."); 4290 return -1; 4291 } 4292 4293 /* Clear device address as it has been removed */ 4294 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac)) 4295 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr)); 4296 } 4297 4298 return 0; 4299 } 4300 4301 /* MAC filter handle */ 4302 static int 4303 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op, 4304 void *arg) 4305 { 4306 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4307 struct rte_eth_mac_filter *filter; 4308 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4309 int ret = I40E_NOT_SUPPORTED; 4310 4311 filter = (struct rte_eth_mac_filter *)(arg); 4312 4313 switch (filter_op) { 4314 case RTE_ETH_FILTER_NOP: 4315 ret = I40E_SUCCESS; 4316 break; 4317 case RTE_ETH_FILTER_ADD: 4318 i40e_pf_disable_irq0(hw); 4319 if (filter->is_vf) 4320 ret = i40e_vf_mac_filter_set(pf, filter, 1); 4321 i40e_pf_enable_irq0(hw); 4322 break; 4323 case RTE_ETH_FILTER_DELETE: 4324 i40e_pf_disable_irq0(hw); 4325 if (filter->is_vf) 4326 ret = i40e_vf_mac_filter_set(pf, filter, 0); 4327 i40e_pf_enable_irq0(hw); 4328 break; 4329 default: 4330 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 4331 ret = I40E_ERR_PARAM; 4332 break; 4333 } 4334 4335 return ret; 4336 } 4337 4338 static int 4339 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4340 { 4341 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 4342 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 4343 uint32_t reg; 4344 int ret; 4345 4346 if (!lut) 4347 return -EINVAL; 4348 4349 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 4350 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, 4351 vsi->type != I40E_VSI_SRIOV, 4352 lut, lut_size); 4353 if (ret) { 4354 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 4355 return ret; 4356 } 4357 } else { 4358 uint32_t *lut_dw = (uint32_t *)lut; 4359 uint16_t i, lut_size_dw = lut_size / 4; 4360 4361 if (vsi->type == I40E_VSI_SRIOV) { 4362 for (i = 0; i <= lut_size_dw; i++) { 4363 reg = I40E_VFQF_HLUT1(i, vsi->user_param); 4364 lut_dw[i] = i40e_read_rx_ctl(hw, reg); 4365 } 4366 } else { 4367 for (i = 0; i < lut_size_dw; i++) 4368 lut_dw[i] = I40E_READ_REG(hw, 4369 I40E_PFQF_HLUT(i)); 4370 } 4371 } 4372 4373 return 0; 4374 } 4375 4376 int 4377 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4378 { 4379 struct i40e_pf *pf; 4380 struct i40e_hw *hw; 4381 int ret; 4382 4383 if (!vsi || !lut) 4384 return -EINVAL; 4385 4386 pf = I40E_VSI_TO_PF(vsi); 4387 hw = I40E_VSI_TO_HW(vsi); 4388 4389 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 4390 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, 4391 vsi->type != I40E_VSI_SRIOV, 4392 lut, lut_size); 4393 if (ret) { 4394 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 4395 return ret; 4396 } 4397 } else { 4398 uint32_t *lut_dw = (uint32_t *)lut; 4399 uint16_t i, lut_size_dw = lut_size / 4; 4400 4401 if (vsi->type == I40E_VSI_SRIOV) { 4402 for (i = 0; i < lut_size_dw; i++) 4403 I40E_WRITE_REG( 4404 hw, 4405 I40E_VFQF_HLUT1(i, vsi->user_param), 4406 lut_dw[i]); 4407 } else { 4408 for (i = 0; i < lut_size_dw; i++) 4409 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), 4410 lut_dw[i]); 4411 } 4412 I40E_WRITE_FLUSH(hw); 4413 } 4414 4415 return 0; 4416 } 4417 4418 static int 4419 i40e_dev_rss_reta_update(struct rte_eth_dev *dev, 4420 struct rte_eth_rss_reta_entry64 *reta_conf, 4421 uint16_t reta_size) 4422 { 4423 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4424 uint16_t i, lut_size = pf->hash_lut_size; 4425 uint16_t idx, shift; 4426 uint8_t *lut; 4427 int ret; 4428 4429 if (reta_size != lut_size || 4430 reta_size > ETH_RSS_RETA_SIZE_512) { 4431 PMD_DRV_LOG(ERR, 4432 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)", 4433 reta_size, lut_size); 4434 return -EINVAL; 4435 } 4436 4437 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 4438 if (!lut) { 4439 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4440 return -ENOMEM; 4441 } 4442 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size); 4443 if (ret) 4444 goto out; 4445 for (i = 0; i < reta_size; i++) { 4446 idx = i / RTE_RETA_GROUP_SIZE; 4447 shift = i % RTE_RETA_GROUP_SIZE; 4448 if (reta_conf[idx].mask & (1ULL << shift)) 4449 lut[i] = reta_conf[idx].reta[shift]; 4450 } 4451 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size); 4452 4453 pf->adapter->rss_reta_updated = 1; 4454 4455 out: 4456 rte_free(lut); 4457 4458 return ret; 4459 } 4460 4461 static int 4462 i40e_dev_rss_reta_query(struct rte_eth_dev *dev, 4463 struct rte_eth_rss_reta_entry64 *reta_conf, 4464 uint16_t reta_size) 4465 { 4466 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4467 uint16_t i, lut_size = pf->hash_lut_size; 4468 uint16_t idx, shift; 4469 uint8_t *lut; 4470 int ret; 4471 4472 if (reta_size != lut_size || 4473 reta_size > ETH_RSS_RETA_SIZE_512) { 4474 PMD_DRV_LOG(ERR, 4475 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)", 4476 reta_size, lut_size); 4477 return -EINVAL; 4478 } 4479 4480 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 4481 if (!lut) { 4482 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4483 return -ENOMEM; 4484 } 4485 4486 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size); 4487 if (ret) 4488 goto out; 4489 for (i = 0; i < reta_size; i++) { 4490 idx = i / RTE_RETA_GROUP_SIZE; 4491 shift = i % RTE_RETA_GROUP_SIZE; 4492 if (reta_conf[idx].mask & (1ULL << shift)) 4493 reta_conf[idx].reta[shift] = lut[i]; 4494 } 4495 4496 out: 4497 rte_free(lut); 4498 4499 return ret; 4500 } 4501 4502 /** 4503 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver) 4504 * @hw: pointer to the HW structure 4505 * @mem: pointer to mem struct to fill out 4506 * @size: size of memory requested 4507 * @alignment: what to align the allocation to 4508 **/ 4509 enum i40e_status_code 4510 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw, 4511 struct i40e_dma_mem *mem, 4512 u64 size, 4513 u32 alignment) 4514 { 4515 const struct rte_memzone *mz = NULL; 4516 char z_name[RTE_MEMZONE_NAMESIZE]; 4517 4518 if (!mem) 4519 return I40E_ERR_PARAM; 4520 4521 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand()); 4522 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 4523 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M); 4524 if (!mz) 4525 return I40E_ERR_NO_MEMORY; 4526 4527 mem->size = size; 4528 mem->va = mz->addr; 4529 mem->pa = mz->iova; 4530 mem->zone = (const void *)mz; 4531 PMD_DRV_LOG(DEBUG, 4532 "memzone %s allocated with physical address: %"PRIu64, 4533 mz->name, mem->pa); 4534 4535 return I40E_SUCCESS; 4536 } 4537 4538 /** 4539 * i40e_free_dma_mem_d - specific memory free for shared code (base driver) 4540 * @hw: pointer to the HW structure 4541 * @mem: ptr to mem struct to free 4542 **/ 4543 enum i40e_status_code 4544 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw, 4545 struct i40e_dma_mem *mem) 4546 { 4547 if (!mem) 4548 return I40E_ERR_PARAM; 4549 4550 PMD_DRV_LOG(DEBUG, 4551 "memzone %s to be freed with physical address: %"PRIu64, 4552 ((const struct rte_memzone *)mem->zone)->name, mem->pa); 4553 rte_memzone_free((const struct rte_memzone *)mem->zone); 4554 mem->zone = NULL; 4555 mem->va = NULL; 4556 mem->pa = (u64)0; 4557 4558 return I40E_SUCCESS; 4559 } 4560 4561 /** 4562 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver) 4563 * @hw: pointer to the HW structure 4564 * @mem: pointer to mem struct to fill out 4565 * @size: size of memory requested 4566 **/ 4567 enum i40e_status_code 4568 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw, 4569 struct i40e_virt_mem *mem, 4570 u32 size) 4571 { 4572 if (!mem) 4573 return I40E_ERR_PARAM; 4574 4575 mem->size = size; 4576 mem->va = rte_zmalloc("i40e", size, 0); 4577 4578 if (mem->va) 4579 return I40E_SUCCESS; 4580 else 4581 return I40E_ERR_NO_MEMORY; 4582 } 4583 4584 /** 4585 * i40e_free_virt_mem_d - specific memory free for shared code (base driver) 4586 * @hw: pointer to the HW structure 4587 * @mem: pointer to mem struct to free 4588 **/ 4589 enum i40e_status_code 4590 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw, 4591 struct i40e_virt_mem *mem) 4592 { 4593 if (!mem) 4594 return I40E_ERR_PARAM; 4595 4596 rte_free(mem->va); 4597 mem->va = NULL; 4598 4599 return I40E_SUCCESS; 4600 } 4601 4602 void 4603 i40e_init_spinlock_d(struct i40e_spinlock *sp) 4604 { 4605 rte_spinlock_init(&sp->spinlock); 4606 } 4607 4608 void 4609 i40e_acquire_spinlock_d(struct i40e_spinlock *sp) 4610 { 4611 rte_spinlock_lock(&sp->spinlock); 4612 } 4613 4614 void 4615 i40e_release_spinlock_d(struct i40e_spinlock *sp) 4616 { 4617 rte_spinlock_unlock(&sp->spinlock); 4618 } 4619 4620 void 4621 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp) 4622 { 4623 return; 4624 } 4625 4626 /** 4627 * Get the hardware capabilities, which will be parsed 4628 * and saved into struct i40e_hw. 4629 */ 4630 static int 4631 i40e_get_cap(struct i40e_hw *hw) 4632 { 4633 struct i40e_aqc_list_capabilities_element_resp *buf; 4634 uint16_t len, size = 0; 4635 int ret; 4636 4637 /* Calculate a huge enough buff for saving response data temporarily */ 4638 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) * 4639 I40E_MAX_CAP_ELE_NUM; 4640 buf = rte_zmalloc("i40e", len, 0); 4641 if (!buf) { 4642 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 4643 return I40E_ERR_NO_MEMORY; 4644 } 4645 4646 /* Get, parse the capabilities and save it to hw */ 4647 ret = i40e_aq_discover_capabilities(hw, buf, len, &size, 4648 i40e_aqc_opc_list_func_capabilities, NULL); 4649 if (ret != I40E_SUCCESS) 4650 PMD_DRV_LOG(ERR, "Failed to discover capabilities"); 4651 4652 /* Free the temporary buffer after being used */ 4653 rte_free(buf); 4654 4655 return ret; 4656 } 4657 4658 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 4659 4660 static int i40e_pf_parse_vf_queue_number_handler(const char *key, 4661 const char *value, 4662 void *opaque) 4663 { 4664 struct i40e_pf *pf; 4665 unsigned long num; 4666 char *end; 4667 4668 pf = (struct i40e_pf *)opaque; 4669 RTE_SET_USED(key); 4670 4671 errno = 0; 4672 num = strtoul(value, &end, 0); 4673 if (errno != 0 || end == value || *end != 0) { 4674 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is " 4675 "kept the value = %hu", value, pf->vf_nb_qp_max); 4676 return -(EINVAL); 4677 } 4678 4679 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num)) 4680 pf->vf_nb_qp_max = (uint16_t)num; 4681 else 4682 /* here return 0 to make next valid same argument work */ 4683 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be " 4684 "power of 2 and equal or less than 16 !, Now it is " 4685 "kept the value = %hu", num, pf->vf_nb_qp_max); 4686 4687 return 0; 4688 } 4689 4690 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev) 4691 { 4692 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4693 struct rte_kvargs *kvlist; 4694 int kvargs_count; 4695 4696 /* set default queue number per VF as 4 */ 4697 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF; 4698 4699 if (dev->device->devargs == NULL) 4700 return 0; 4701 4702 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 4703 if (kvlist == NULL) 4704 return -(EINVAL); 4705 4706 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG); 4707 if (!kvargs_count) { 4708 rte_kvargs_free(kvlist); 4709 return 0; 4710 } 4711 4712 if (kvargs_count > 1) 4713 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 4714 "the first invalid or last valid one is used !", 4715 ETH_I40E_QUEUE_NUM_PER_VF_ARG); 4716 4717 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG, 4718 i40e_pf_parse_vf_queue_number_handler, pf); 4719 4720 rte_kvargs_free(kvlist); 4721 4722 return 0; 4723 } 4724 4725 static int 4726 i40e_pf_parameter_init(struct rte_eth_dev *dev) 4727 { 4728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4729 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4730 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4731 uint16_t qp_count = 0, vsi_count = 0; 4732 4733 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) { 4734 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV"); 4735 return -EINVAL; 4736 } 4737 4738 i40e_pf_config_vf_rxq_number(dev); 4739 4740 /* Add the parameter init for LFC */ 4741 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME; 4742 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER; 4743 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER; 4744 4745 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED; 4746 pf->max_num_vsi = hw->func_caps.num_vsis; 4747 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF; 4748 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 4749 4750 /* FDir queue/VSI allocation */ 4751 pf->fdir_qp_offset = 0; 4752 if (hw->func_caps.fd) { 4753 pf->flags |= I40E_FLAG_FDIR; 4754 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR; 4755 } else { 4756 pf->fdir_nb_qps = 0; 4757 } 4758 qp_count += pf->fdir_nb_qps; 4759 vsi_count += 1; 4760 4761 /* LAN queue/VSI allocation */ 4762 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps; 4763 if (!hw->func_caps.rss) { 4764 pf->lan_nb_qps = 1; 4765 } else { 4766 pf->flags |= I40E_FLAG_RSS; 4767 if (hw->mac.type == I40E_MAC_X722) 4768 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE; 4769 pf->lan_nb_qps = pf->lan_nb_qp_max; 4770 } 4771 qp_count += pf->lan_nb_qps; 4772 vsi_count += 1; 4773 4774 /* VF queue/VSI allocation */ 4775 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps; 4776 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) { 4777 pf->flags |= I40E_FLAG_SRIOV; 4778 pf->vf_nb_qps = pf->vf_nb_qp_max; 4779 pf->vf_num = pci_dev->max_vfs; 4780 PMD_DRV_LOG(DEBUG, 4781 "%u VF VSIs, %u queues per VF VSI, in total %u queues", 4782 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num); 4783 } else { 4784 pf->vf_nb_qps = 0; 4785 pf->vf_num = 0; 4786 } 4787 qp_count += pf->vf_nb_qps * pf->vf_num; 4788 vsi_count += pf->vf_num; 4789 4790 /* VMDq queue/VSI allocation */ 4791 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num; 4792 pf->vmdq_nb_qps = 0; 4793 pf->max_nb_vmdq_vsi = 0; 4794 if (hw->func_caps.vmdq) { 4795 if (qp_count < hw->func_caps.num_tx_qp && 4796 vsi_count < hw->func_caps.num_vsis) { 4797 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp - 4798 qp_count) / pf->vmdq_nb_qp_max; 4799 4800 /* Limit the maximum number of VMDq vsi to the maximum 4801 * ethdev can support 4802 */ 4803 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi, 4804 hw->func_caps.num_vsis - vsi_count); 4805 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi, 4806 ETH_64_POOLS); 4807 if (pf->max_nb_vmdq_vsi) { 4808 pf->flags |= I40E_FLAG_VMDQ; 4809 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max; 4810 PMD_DRV_LOG(DEBUG, 4811 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues", 4812 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps, 4813 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi); 4814 } else { 4815 PMD_DRV_LOG(INFO, 4816 "No enough queues left for VMDq"); 4817 } 4818 } else { 4819 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq"); 4820 } 4821 } 4822 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi; 4823 vsi_count += pf->max_nb_vmdq_vsi; 4824 4825 if (hw->func_caps.dcb) 4826 pf->flags |= I40E_FLAG_DCB; 4827 4828 if (qp_count > hw->func_caps.num_tx_qp) { 4829 PMD_DRV_LOG(ERR, 4830 "Failed to allocate %u queues, which exceeds the hardware maximum %u", 4831 qp_count, hw->func_caps.num_tx_qp); 4832 return -EINVAL; 4833 } 4834 if (vsi_count > hw->func_caps.num_vsis) { 4835 PMD_DRV_LOG(ERR, 4836 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u", 4837 vsi_count, hw->func_caps.num_vsis); 4838 return -EINVAL; 4839 } 4840 4841 return 0; 4842 } 4843 4844 static int 4845 i40e_pf_get_switch_config(struct i40e_pf *pf) 4846 { 4847 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4848 struct i40e_aqc_get_switch_config_resp *switch_config; 4849 struct i40e_aqc_switch_config_element_resp *element; 4850 uint16_t start_seid = 0, num_reported; 4851 int ret; 4852 4853 switch_config = (struct i40e_aqc_get_switch_config_resp *)\ 4854 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0); 4855 if (!switch_config) { 4856 PMD_DRV_LOG(ERR, "Failed to allocated memory"); 4857 return -ENOMEM; 4858 } 4859 4860 /* Get the switch configurations */ 4861 ret = i40e_aq_get_switch_config(hw, switch_config, 4862 I40E_AQ_LARGE_BUF, &start_seid, NULL); 4863 if (ret != I40E_SUCCESS) { 4864 PMD_DRV_LOG(ERR, "Failed to get switch configurations"); 4865 goto fail; 4866 } 4867 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported); 4868 if (num_reported != 1) { /* The number should be 1 */ 4869 PMD_DRV_LOG(ERR, "Wrong number of switch config reported"); 4870 goto fail; 4871 } 4872 4873 /* Parse the switch configuration elements */ 4874 element = &(switch_config->element[0]); 4875 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) { 4876 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid); 4877 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid); 4878 } else 4879 PMD_DRV_LOG(INFO, "Unknown element type"); 4880 4881 fail: 4882 rte_free(switch_config); 4883 4884 return ret; 4885 } 4886 4887 static int 4888 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base, 4889 uint32_t num) 4890 { 4891 struct pool_entry *entry; 4892 4893 if (pool == NULL || num == 0) 4894 return -EINVAL; 4895 4896 entry = rte_zmalloc("i40e", sizeof(*entry), 0); 4897 if (entry == NULL) { 4898 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool"); 4899 return -ENOMEM; 4900 } 4901 4902 /* queue heap initialize */ 4903 pool->num_free = num; 4904 pool->num_alloc = 0; 4905 pool->base = base; 4906 LIST_INIT(&pool->alloc_list); 4907 LIST_INIT(&pool->free_list); 4908 4909 /* Initialize element */ 4910 entry->base = 0; 4911 entry->len = num; 4912 4913 LIST_INSERT_HEAD(&pool->free_list, entry, next); 4914 return 0; 4915 } 4916 4917 static void 4918 i40e_res_pool_destroy(struct i40e_res_pool_info *pool) 4919 { 4920 struct pool_entry *entry, *next_entry; 4921 4922 if (pool == NULL) 4923 return; 4924 4925 for (entry = LIST_FIRST(&pool->alloc_list); 4926 entry && (next_entry = LIST_NEXT(entry, next), 1); 4927 entry = next_entry) { 4928 LIST_REMOVE(entry, next); 4929 rte_free(entry); 4930 } 4931 4932 for (entry = LIST_FIRST(&pool->free_list); 4933 entry && (next_entry = LIST_NEXT(entry, next), 1); 4934 entry = next_entry) { 4935 LIST_REMOVE(entry, next); 4936 rte_free(entry); 4937 } 4938 4939 pool->num_free = 0; 4940 pool->num_alloc = 0; 4941 pool->base = 0; 4942 LIST_INIT(&pool->alloc_list); 4943 LIST_INIT(&pool->free_list); 4944 } 4945 4946 static int 4947 i40e_res_pool_free(struct i40e_res_pool_info *pool, 4948 uint32_t base) 4949 { 4950 struct pool_entry *entry, *next, *prev, *valid_entry = NULL; 4951 uint32_t pool_offset; 4952 uint16_t len; 4953 int insert; 4954 4955 if (pool == NULL) { 4956 PMD_DRV_LOG(ERR, "Invalid parameter"); 4957 return -EINVAL; 4958 } 4959 4960 pool_offset = base - pool->base; 4961 /* Lookup in alloc list */ 4962 LIST_FOREACH(entry, &pool->alloc_list, next) { 4963 if (entry->base == pool_offset) { 4964 valid_entry = entry; 4965 LIST_REMOVE(entry, next); 4966 break; 4967 } 4968 } 4969 4970 /* Not find, return */ 4971 if (valid_entry == NULL) { 4972 PMD_DRV_LOG(ERR, "Failed to find entry"); 4973 return -EINVAL; 4974 } 4975 4976 /** 4977 * Found it, move it to free list and try to merge. 4978 * In order to make merge easier, always sort it by qbase. 4979 * Find adjacent prev and last entries. 4980 */ 4981 prev = next = NULL; 4982 LIST_FOREACH(entry, &pool->free_list, next) { 4983 if (entry->base > valid_entry->base) { 4984 next = entry; 4985 break; 4986 } 4987 prev = entry; 4988 } 4989 4990 insert = 0; 4991 len = valid_entry->len; 4992 /* Try to merge with next one*/ 4993 if (next != NULL) { 4994 /* Merge with next one */ 4995 if (valid_entry->base + len == next->base) { 4996 next->base = valid_entry->base; 4997 next->len += len; 4998 rte_free(valid_entry); 4999 valid_entry = next; 5000 insert = 1; 5001 } 5002 } 5003 5004 if (prev != NULL) { 5005 /* Merge with previous one */ 5006 if (prev->base + prev->len == valid_entry->base) { 5007 prev->len += len; 5008 /* If it merge with next one, remove next node */ 5009 if (insert == 1) { 5010 LIST_REMOVE(valid_entry, next); 5011 rte_free(valid_entry); 5012 valid_entry = NULL; 5013 } else { 5014 rte_free(valid_entry); 5015 valid_entry = NULL; 5016 insert = 1; 5017 } 5018 } 5019 } 5020 5021 /* Not find any entry to merge, insert */ 5022 if (insert == 0) { 5023 if (prev != NULL) 5024 LIST_INSERT_AFTER(prev, valid_entry, next); 5025 else if (next != NULL) 5026 LIST_INSERT_BEFORE(next, valid_entry, next); 5027 else /* It's empty list, insert to head */ 5028 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next); 5029 } 5030 5031 pool->num_free += len; 5032 pool->num_alloc -= len; 5033 5034 return 0; 5035 } 5036 5037 static int 5038 i40e_res_pool_alloc(struct i40e_res_pool_info *pool, 5039 uint16_t num) 5040 { 5041 struct pool_entry *entry, *valid_entry; 5042 5043 if (pool == NULL || num == 0) { 5044 PMD_DRV_LOG(ERR, "Invalid parameter"); 5045 return -EINVAL; 5046 } 5047 5048 if (pool->num_free < num) { 5049 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u", 5050 num, pool->num_free); 5051 return -ENOMEM; 5052 } 5053 5054 valid_entry = NULL; 5055 /* Lookup in free list and find most fit one */ 5056 LIST_FOREACH(entry, &pool->free_list, next) { 5057 if (entry->len >= num) { 5058 /* Find best one */ 5059 if (entry->len == num) { 5060 valid_entry = entry; 5061 break; 5062 } 5063 if (valid_entry == NULL || valid_entry->len > entry->len) 5064 valid_entry = entry; 5065 } 5066 } 5067 5068 /* Not find one to satisfy the request, return */ 5069 if (valid_entry == NULL) { 5070 PMD_DRV_LOG(ERR, "No valid entry found"); 5071 return -ENOMEM; 5072 } 5073 /** 5074 * The entry have equal queue number as requested, 5075 * remove it from alloc_list. 5076 */ 5077 if (valid_entry->len == num) { 5078 LIST_REMOVE(valid_entry, next); 5079 } else { 5080 /** 5081 * The entry have more numbers than requested, 5082 * create a new entry for alloc_list and minus its 5083 * queue base and number in free_list. 5084 */ 5085 entry = rte_zmalloc("res_pool", sizeof(*entry), 0); 5086 if (entry == NULL) { 5087 PMD_DRV_LOG(ERR, 5088 "Failed to allocate memory for resource pool"); 5089 return -ENOMEM; 5090 } 5091 entry->base = valid_entry->base; 5092 entry->len = num; 5093 valid_entry->base += num; 5094 valid_entry->len -= num; 5095 valid_entry = entry; 5096 } 5097 5098 /* Insert it into alloc list, not sorted */ 5099 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 5100 5101 pool->num_free -= valid_entry->len; 5102 pool->num_alloc += valid_entry->len; 5103 5104 return valid_entry->base + pool->base; 5105 } 5106 5107 /** 5108 * bitmap_is_subset - Check whether src2 is subset of src1 5109 **/ 5110 static inline int 5111 bitmap_is_subset(uint8_t src1, uint8_t src2) 5112 { 5113 return !((src1 ^ src2) & src2); 5114 } 5115 5116 static enum i40e_status_code 5117 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap) 5118 { 5119 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5120 5121 /* If DCB is not supported, only default TC is supported */ 5122 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) { 5123 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported"); 5124 return I40E_NOT_SUPPORTED; 5125 } 5126 5127 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) { 5128 PMD_DRV_LOG(ERR, 5129 "Enabled TC map 0x%x not applicable to HW support 0x%x", 5130 hw->func_caps.enabled_tcmap, enabled_tcmap); 5131 return I40E_NOT_SUPPORTED; 5132 } 5133 return I40E_SUCCESS; 5134 } 5135 5136 int 5137 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 5138 struct i40e_vsi_vlan_pvid_info *info) 5139 { 5140 struct i40e_hw *hw; 5141 struct i40e_vsi_context ctxt; 5142 uint8_t vlan_flags = 0; 5143 int ret; 5144 5145 if (vsi == NULL || info == NULL) { 5146 PMD_DRV_LOG(ERR, "invalid parameters"); 5147 return I40E_ERR_PARAM; 5148 } 5149 5150 if (info->on) { 5151 vsi->info.pvid = info->config.pvid; 5152 /** 5153 * If insert pvid is enabled, only tagged pkts are 5154 * allowed to be sent out. 5155 */ 5156 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID | 5157 I40E_AQ_VSI_PVLAN_MODE_TAGGED; 5158 } else { 5159 vsi->info.pvid = 0; 5160 if (info->config.reject.tagged == 0) 5161 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED; 5162 5163 if (info->config.reject.untagged == 0) 5164 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED; 5165 } 5166 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID | 5167 I40E_AQ_VSI_PVLAN_MODE_MASK); 5168 vsi->info.port_vlan_flags |= vlan_flags; 5169 vsi->info.valid_sections = 5170 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5171 memset(&ctxt, 0, sizeof(ctxt)); 5172 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 5173 ctxt.seid = vsi->seid; 5174 5175 hw = I40E_VSI_TO_HW(vsi); 5176 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5177 if (ret != I40E_SUCCESS) 5178 PMD_DRV_LOG(ERR, "Failed to update VSI params"); 5179 5180 return ret; 5181 } 5182 5183 static int 5184 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap) 5185 { 5186 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5187 int i, ret; 5188 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data; 5189 5190 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 5191 if (ret != I40E_SUCCESS) 5192 return ret; 5193 5194 if (!vsi->seid) { 5195 PMD_DRV_LOG(ERR, "seid not valid"); 5196 return -EINVAL; 5197 } 5198 5199 memset(&tc_bw_data, 0, sizeof(tc_bw_data)); 5200 tc_bw_data.tc_valid_bits = enabled_tcmap; 5201 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 5202 tc_bw_data.tc_bw_credits[i] = 5203 (enabled_tcmap & (1 << i)) ? 1 : 0; 5204 5205 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL); 5206 if (ret != I40E_SUCCESS) { 5207 PMD_DRV_LOG(ERR, "Failed to configure TC BW"); 5208 return ret; 5209 } 5210 5211 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles, 5212 sizeof(vsi->info.qs_handle)); 5213 return I40E_SUCCESS; 5214 } 5215 5216 static enum i40e_status_code 5217 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi, 5218 struct i40e_aqc_vsi_properties_data *info, 5219 uint8_t enabled_tcmap) 5220 { 5221 enum i40e_status_code ret; 5222 int i, total_tc = 0; 5223 uint16_t qpnum_per_tc, bsf, qp_idx; 5224 5225 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 5226 if (ret != I40E_SUCCESS) 5227 return ret; 5228 5229 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 5230 if (enabled_tcmap & (1 << i)) 5231 total_tc++; 5232 if (total_tc == 0) 5233 total_tc = 1; 5234 vsi->enabled_tc = enabled_tcmap; 5235 5236 /* Number of queues per enabled TC */ 5237 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc); 5238 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC); 5239 bsf = rte_bsf32(qpnum_per_tc); 5240 5241 /* Adjust the queue number to actual queues that can be applied */ 5242 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1)) 5243 vsi->nb_qps = qpnum_per_tc * total_tc; 5244 5245 /** 5246 * Configure TC and queue mapping parameters, for enabled TC, 5247 * allocate qpnum_per_tc queues to this traffic. For disabled TC, 5248 * default queue will serve it. 5249 */ 5250 qp_idx = 0; 5251 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 5252 if (vsi->enabled_tc & (1 << i)) { 5253 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx << 5254 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 5255 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 5256 qp_idx += qpnum_per_tc; 5257 } else 5258 info->tc_mapping[i] = 0; 5259 } 5260 5261 /* Associate queue number with VSI */ 5262 if (vsi->type == I40E_VSI_SRIOV) { 5263 info->mapping_flags |= 5264 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 5265 for (i = 0; i < vsi->nb_qps; i++) 5266 info->queue_mapping[i] = 5267 rte_cpu_to_le_16(vsi->base_queue + i); 5268 } else { 5269 info->mapping_flags |= 5270 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG); 5271 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 5272 } 5273 info->valid_sections |= 5274 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 5275 5276 return I40E_SUCCESS; 5277 } 5278 5279 static int 5280 i40e_veb_release(struct i40e_veb *veb) 5281 { 5282 struct i40e_vsi *vsi; 5283 struct i40e_hw *hw; 5284 5285 if (veb == NULL) 5286 return -EINVAL; 5287 5288 if (!TAILQ_EMPTY(&veb->head)) { 5289 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove"); 5290 return -EACCES; 5291 } 5292 /* associate_vsi field is NULL for floating VEB */ 5293 if (veb->associate_vsi != NULL) { 5294 vsi = veb->associate_vsi; 5295 hw = I40E_VSI_TO_HW(vsi); 5296 5297 vsi->uplink_seid = veb->uplink_seid; 5298 vsi->veb = NULL; 5299 } else { 5300 veb->associate_pf->main_vsi->floating_veb = NULL; 5301 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi); 5302 } 5303 5304 i40e_aq_delete_element(hw, veb->seid, NULL); 5305 rte_free(veb); 5306 return I40E_SUCCESS; 5307 } 5308 5309 /* Setup a veb */ 5310 static struct i40e_veb * 5311 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi) 5312 { 5313 struct i40e_veb *veb; 5314 int ret; 5315 struct i40e_hw *hw; 5316 5317 if (pf == NULL) { 5318 PMD_DRV_LOG(ERR, 5319 "veb setup failed, associated PF shouldn't null"); 5320 return NULL; 5321 } 5322 hw = I40E_PF_TO_HW(pf); 5323 5324 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0); 5325 if (!veb) { 5326 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb"); 5327 goto fail; 5328 } 5329 5330 veb->associate_vsi = vsi; 5331 veb->associate_pf = pf; 5332 TAILQ_INIT(&veb->head); 5333 veb->uplink_seid = vsi ? vsi->uplink_seid : 0; 5334 5335 /* create floating veb if vsi is NULL */ 5336 if (vsi != NULL) { 5337 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid, 5338 I40E_DEFAULT_TCMAP, false, 5339 &veb->seid, false, NULL); 5340 } else { 5341 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP, 5342 true, &veb->seid, false, NULL); 5343 } 5344 5345 if (ret != I40E_SUCCESS) { 5346 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d", 5347 hw->aq.asq_last_status); 5348 goto fail; 5349 } 5350 veb->enabled_tc = I40E_DEFAULT_TCMAP; 5351 5352 /* get statistics index */ 5353 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL, 5354 &veb->stats_idx, NULL, NULL, NULL); 5355 if (ret != I40E_SUCCESS) { 5356 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d", 5357 hw->aq.asq_last_status); 5358 goto fail; 5359 } 5360 /* Get VEB bandwidth, to be implemented */ 5361 /* Now associated vsi binding to the VEB, set uplink to this VEB */ 5362 if (vsi) 5363 vsi->uplink_seid = veb->seid; 5364 5365 return veb; 5366 fail: 5367 rte_free(veb); 5368 return NULL; 5369 } 5370 5371 int 5372 i40e_vsi_release(struct i40e_vsi *vsi) 5373 { 5374 struct i40e_pf *pf; 5375 struct i40e_hw *hw; 5376 struct i40e_vsi_list *vsi_list; 5377 void *temp; 5378 int ret; 5379 struct i40e_mac_filter *f; 5380 uint16_t user_param; 5381 5382 if (!vsi) 5383 return I40E_SUCCESS; 5384 5385 if (!vsi->adapter) 5386 return -EFAULT; 5387 5388 user_param = vsi->user_param; 5389 5390 pf = I40E_VSI_TO_PF(vsi); 5391 hw = I40E_VSI_TO_HW(vsi); 5392 5393 /* VSI has child to attach, release child first */ 5394 if (vsi->veb) { 5395 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) { 5396 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS) 5397 return -1; 5398 } 5399 i40e_veb_release(vsi->veb); 5400 } 5401 5402 if (vsi->floating_veb) { 5403 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) { 5404 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS) 5405 return -1; 5406 } 5407 } 5408 5409 /* Remove all macvlan filters of the VSI */ 5410 i40e_vsi_remove_all_macvlan_filter(vsi); 5411 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) 5412 rte_free(f); 5413 5414 if (vsi->type != I40E_VSI_MAIN && 5415 ((vsi->type != I40E_VSI_SRIOV) || 5416 !pf->floating_veb_list[user_param])) { 5417 /* Remove vsi from parent's sibling list */ 5418 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) { 5419 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL"); 5420 return I40E_ERR_PARAM; 5421 } 5422 TAILQ_REMOVE(&vsi->parent_vsi->veb->head, 5423 &vsi->sib_vsi_list, list); 5424 5425 /* Remove all switch element of the VSI */ 5426 ret = i40e_aq_delete_element(hw, vsi->seid, NULL); 5427 if (ret != I40E_SUCCESS) 5428 PMD_DRV_LOG(ERR, "Failed to delete element"); 5429 } 5430 5431 if ((vsi->type == I40E_VSI_SRIOV) && 5432 pf->floating_veb_list[user_param]) { 5433 /* Remove vsi from parent's sibling list */ 5434 if (vsi->parent_vsi == NULL || 5435 vsi->parent_vsi->floating_veb == NULL) { 5436 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL"); 5437 return I40E_ERR_PARAM; 5438 } 5439 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head, 5440 &vsi->sib_vsi_list, list); 5441 5442 /* Remove all switch element of the VSI */ 5443 ret = i40e_aq_delete_element(hw, vsi->seid, NULL); 5444 if (ret != I40E_SUCCESS) 5445 PMD_DRV_LOG(ERR, "Failed to delete element"); 5446 } 5447 5448 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue); 5449 5450 if (vsi->type != I40E_VSI_SRIOV) 5451 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr); 5452 rte_free(vsi); 5453 5454 return I40E_SUCCESS; 5455 } 5456 5457 static int 5458 i40e_update_default_filter_setting(struct i40e_vsi *vsi) 5459 { 5460 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5461 struct i40e_aqc_remove_macvlan_element_data def_filter; 5462 struct i40e_mac_filter_info filter; 5463 int ret; 5464 5465 if (vsi->type != I40E_VSI_MAIN) 5466 return I40E_ERR_CONFIG; 5467 memset(&def_filter, 0, sizeof(def_filter)); 5468 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr, 5469 ETH_ADDR_LEN); 5470 def_filter.vlan_tag = 0; 5471 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 5472 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 5473 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL); 5474 if (ret != I40E_SUCCESS) { 5475 struct i40e_mac_filter *f; 5476 struct rte_ether_addr *mac; 5477 5478 PMD_DRV_LOG(DEBUG, 5479 "Cannot remove the default macvlan filter"); 5480 /* It needs to add the permanent mac into mac list */ 5481 f = rte_zmalloc("macv_filter", sizeof(*f), 0); 5482 if (f == NULL) { 5483 PMD_DRV_LOG(ERR, "failed to allocate memory"); 5484 return I40E_ERR_NO_MEMORY; 5485 } 5486 mac = &f->mac_info.mac_addr; 5487 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr, 5488 ETH_ADDR_LEN); 5489 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5490 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 5491 vsi->mac_num++; 5492 5493 return ret; 5494 } 5495 rte_memcpy(&filter.mac_addr, 5496 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN); 5497 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5498 return i40e_vsi_add_mac(vsi, &filter); 5499 } 5500 5501 /* 5502 * i40e_vsi_get_bw_config - Query VSI BW Information 5503 * @vsi: the VSI to be queried 5504 * 5505 * Returns 0 on success, negative value on failure 5506 */ 5507 static enum i40e_status_code 5508 i40e_vsi_get_bw_config(struct i40e_vsi *vsi) 5509 { 5510 struct i40e_aqc_query_vsi_bw_config_resp bw_config; 5511 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config; 5512 struct i40e_hw *hw = &vsi->adapter->hw; 5513 i40e_status ret; 5514 int i; 5515 uint32_t bw_max; 5516 5517 memset(&bw_config, 0, sizeof(bw_config)); 5518 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); 5519 if (ret != I40E_SUCCESS) { 5520 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u", 5521 hw->aq.asq_last_status); 5522 return ret; 5523 } 5524 5525 memset(&ets_sla_config, 0, sizeof(ets_sla_config)); 5526 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, 5527 &ets_sla_config, NULL); 5528 if (ret != I40E_SUCCESS) { 5529 PMD_DRV_LOG(ERR, 5530 "VSI failed to get TC bandwdith configuration %u", 5531 hw->aq.asq_last_status); 5532 return ret; 5533 } 5534 5535 /* store and print out BW info */ 5536 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit); 5537 vsi->bw_info.bw_max = bw_config.max_bw; 5538 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit); 5539 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max); 5540 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) | 5541 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) << 5542 I40E_16_BIT_WIDTH); 5543 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 5544 vsi->bw_info.bw_ets_share_credits[i] = 5545 ets_sla_config.share_credits[i]; 5546 vsi->bw_info.bw_ets_credits[i] = 5547 rte_le_to_cpu_16(ets_sla_config.credits[i]); 5548 /* 4 bits per TC, 4th bit is reserved */ 5549 vsi->bw_info.bw_ets_max[i] = 5550 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) & 5551 RTE_LEN2MASK(3, uint8_t)); 5552 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i, 5553 vsi->bw_info.bw_ets_share_credits[i]); 5554 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i, 5555 vsi->bw_info.bw_ets_credits[i]); 5556 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i, 5557 vsi->bw_info.bw_ets_max[i]); 5558 } 5559 5560 return I40E_SUCCESS; 5561 } 5562 5563 /* i40e_enable_pf_lb 5564 * @pf: pointer to the pf structure 5565 * 5566 * allow loopback on pf 5567 */ 5568 static inline void 5569 i40e_enable_pf_lb(struct i40e_pf *pf) 5570 { 5571 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 5572 struct i40e_vsi_context ctxt; 5573 int ret; 5574 5575 /* Use the FW API if FW >= v5.0 */ 5576 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) { 5577 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback"); 5578 return; 5579 } 5580 5581 memset(&ctxt, 0, sizeof(ctxt)); 5582 ctxt.seid = pf->main_vsi_seid; 5583 ctxt.pf_num = hw->pf_id; 5584 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 5585 if (ret) { 5586 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d", 5587 ret, hw->aq.asq_last_status); 5588 return; 5589 } 5590 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 5591 ctxt.info.valid_sections = 5592 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5593 ctxt.info.switch_id |= 5594 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5595 5596 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5597 if (ret) 5598 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d", 5599 hw->aq.asq_last_status); 5600 } 5601 5602 /* Setup a VSI */ 5603 struct i40e_vsi * 5604 i40e_vsi_setup(struct i40e_pf *pf, 5605 enum i40e_vsi_type type, 5606 struct i40e_vsi *uplink_vsi, 5607 uint16_t user_param) 5608 { 5609 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 5610 struct i40e_vsi *vsi; 5611 struct i40e_mac_filter_info filter; 5612 int ret; 5613 struct i40e_vsi_context ctxt; 5614 struct rte_ether_addr broadcast = 5615 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; 5616 5617 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV && 5618 uplink_vsi == NULL) { 5619 PMD_DRV_LOG(ERR, 5620 "VSI setup failed, VSI link shouldn't be NULL"); 5621 return NULL; 5622 } 5623 5624 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) { 5625 PMD_DRV_LOG(ERR, 5626 "VSI setup failed, MAIN VSI uplink VSI should be NULL"); 5627 return NULL; 5628 } 5629 5630 /* two situations 5631 * 1.type is not MAIN and uplink vsi is not NULL 5632 * If uplink vsi didn't setup VEB, create one first under veb field 5633 * 2.type is SRIOV and the uplink is NULL 5634 * If floating VEB is NULL, create one veb under floating veb field 5635 */ 5636 5637 if (type != I40E_VSI_MAIN && uplink_vsi != NULL && 5638 uplink_vsi->veb == NULL) { 5639 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi); 5640 5641 if (uplink_vsi->veb == NULL) { 5642 PMD_DRV_LOG(ERR, "VEB setup failed"); 5643 return NULL; 5644 } 5645 /* set ALLOWLOOPBACk on pf, when veb is created */ 5646 i40e_enable_pf_lb(pf); 5647 } 5648 5649 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL && 5650 pf->main_vsi->floating_veb == NULL) { 5651 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi); 5652 5653 if (pf->main_vsi->floating_veb == NULL) { 5654 PMD_DRV_LOG(ERR, "VEB setup failed"); 5655 return NULL; 5656 } 5657 } 5658 5659 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0); 5660 if (!vsi) { 5661 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi"); 5662 return NULL; 5663 } 5664 TAILQ_INIT(&vsi->mac_list); 5665 vsi->type = type; 5666 vsi->adapter = I40E_PF_TO_ADAPTER(pf); 5667 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX; 5668 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi; 5669 vsi->user_param = user_param; 5670 vsi->vlan_anti_spoof_on = 0; 5671 vsi->vlan_filter_on = 0; 5672 /* Allocate queues */ 5673 switch (vsi->type) { 5674 case I40E_VSI_MAIN : 5675 vsi->nb_qps = pf->lan_nb_qps; 5676 break; 5677 case I40E_VSI_SRIOV : 5678 vsi->nb_qps = pf->vf_nb_qps; 5679 break; 5680 case I40E_VSI_VMDQ2: 5681 vsi->nb_qps = pf->vmdq_nb_qps; 5682 break; 5683 case I40E_VSI_FDIR: 5684 vsi->nb_qps = pf->fdir_nb_qps; 5685 break; 5686 default: 5687 goto fail_mem; 5688 } 5689 /* 5690 * The filter status descriptor is reported in rx queue 0, 5691 * while the tx queue for fdir filter programming has no 5692 * such constraints, can be non-zero queues. 5693 * To simplify it, choose FDIR vsi use queue 0 pair. 5694 * To make sure it will use queue 0 pair, queue allocation 5695 * need be done before this function is called 5696 */ 5697 if (type != I40E_VSI_FDIR) { 5698 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps); 5699 if (ret < 0) { 5700 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d", 5701 vsi->seid, ret); 5702 goto fail_mem; 5703 } 5704 vsi->base_queue = ret; 5705 } else 5706 vsi->base_queue = I40E_FDIR_QUEUE_ID; 5707 5708 /* VF has MSIX interrupt in VF range, don't allocate here */ 5709 if (type == I40E_VSI_MAIN) { 5710 if (pf->support_multi_driver) { 5711 /* If support multi-driver, need to use INT0 instead of 5712 * allocating from msix pool. The Msix pool is init from 5713 * INT1, so it's OK just set msix_intr to 0 and nb_msix 5714 * to 1 without calling i40e_res_pool_alloc. 5715 */ 5716 vsi->msix_intr = 0; 5717 vsi->nb_msix = 1; 5718 } else { 5719 ret = i40e_res_pool_alloc(&pf->msix_pool, 5720 RTE_MIN(vsi->nb_qps, 5721 RTE_MAX_RXTX_INTR_VEC_ID)); 5722 if (ret < 0) { 5723 PMD_DRV_LOG(ERR, 5724 "VSI MAIN %d get heap failed %d", 5725 vsi->seid, ret); 5726 goto fail_queue_alloc; 5727 } 5728 vsi->msix_intr = ret; 5729 vsi->nb_msix = RTE_MIN(vsi->nb_qps, 5730 RTE_MAX_RXTX_INTR_VEC_ID); 5731 } 5732 } else if (type != I40E_VSI_SRIOV) { 5733 ret = i40e_res_pool_alloc(&pf->msix_pool, 1); 5734 if (ret < 0) { 5735 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret); 5736 goto fail_queue_alloc; 5737 } 5738 vsi->msix_intr = ret; 5739 vsi->nb_msix = 1; 5740 } else { 5741 vsi->msix_intr = 0; 5742 vsi->nb_msix = 0; 5743 } 5744 5745 /* Add VSI */ 5746 if (type == I40E_VSI_MAIN) { 5747 /* For main VSI, no need to add since it's default one */ 5748 vsi->uplink_seid = pf->mac_seid; 5749 vsi->seid = pf->main_vsi_seid; 5750 /* Bind queues with specific MSIX interrupt */ 5751 /** 5752 * Needs 2 interrupt at least, one for misc cause which will 5753 * enabled from OS side, Another for queues binding the 5754 * interrupt from device side only. 5755 */ 5756 5757 /* Get default VSI parameters from hardware */ 5758 memset(&ctxt, 0, sizeof(ctxt)); 5759 ctxt.seid = vsi->seid; 5760 ctxt.pf_num = hw->pf_id; 5761 ctxt.uplink_seid = vsi->uplink_seid; 5762 ctxt.vf_num = 0; 5763 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 5764 if (ret != I40E_SUCCESS) { 5765 PMD_DRV_LOG(ERR, "Failed to get VSI params"); 5766 goto fail_msix_alloc; 5767 } 5768 rte_memcpy(&vsi->info, &ctxt.info, 5769 sizeof(struct i40e_aqc_vsi_properties_data)); 5770 vsi->vsi_id = ctxt.vsi_number; 5771 vsi->info.valid_sections = 0; 5772 5773 /* Configure tc, enabled TC0 only */ 5774 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) != 5775 I40E_SUCCESS) { 5776 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth"); 5777 goto fail_msix_alloc; 5778 } 5779 5780 /* TC, queue mapping */ 5781 memset(&ctxt, 0, sizeof(ctxt)); 5782 vsi->info.valid_sections |= 5783 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5784 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 5785 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 5786 rte_memcpy(&ctxt.info, &vsi->info, 5787 sizeof(struct i40e_aqc_vsi_properties_data)); 5788 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5789 I40E_DEFAULT_TCMAP); 5790 if (ret != I40E_SUCCESS) { 5791 PMD_DRV_LOG(ERR, 5792 "Failed to configure TC queue mapping"); 5793 goto fail_msix_alloc; 5794 } 5795 ctxt.seid = vsi->seid; 5796 ctxt.pf_num = hw->pf_id; 5797 ctxt.uplink_seid = vsi->uplink_seid; 5798 ctxt.vf_num = 0; 5799 5800 /* Update VSI parameters */ 5801 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5802 if (ret != I40E_SUCCESS) { 5803 PMD_DRV_LOG(ERR, "Failed to update VSI params"); 5804 goto fail_msix_alloc; 5805 } 5806 5807 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping, 5808 sizeof(vsi->info.tc_mapping)); 5809 rte_memcpy(&vsi->info.queue_mapping, 5810 &ctxt.info.queue_mapping, 5811 sizeof(vsi->info.queue_mapping)); 5812 vsi->info.mapping_flags = ctxt.info.mapping_flags; 5813 vsi->info.valid_sections = 0; 5814 5815 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr, 5816 ETH_ADDR_LEN); 5817 5818 /** 5819 * Updating default filter settings are necessary to prevent 5820 * reception of tagged packets. 5821 * Some old firmware configurations load a default macvlan 5822 * filter which accepts both tagged and untagged packets. 5823 * The updating is to use a normal filter instead if needed. 5824 * For NVM 4.2.2 or after, the updating is not needed anymore. 5825 * The firmware with correct configurations load the default 5826 * macvlan filter which is expected and cannot be removed. 5827 */ 5828 i40e_update_default_filter_setting(vsi); 5829 i40e_config_qinq(hw, vsi); 5830 } else if (type == I40E_VSI_SRIOV) { 5831 memset(&ctxt, 0, sizeof(ctxt)); 5832 /** 5833 * For other VSI, the uplink_seid equals to uplink VSI's 5834 * uplink_seid since they share same VEB 5835 */ 5836 if (uplink_vsi == NULL) 5837 vsi->uplink_seid = pf->main_vsi->floating_veb->seid; 5838 else 5839 vsi->uplink_seid = uplink_vsi->uplink_seid; 5840 ctxt.pf_num = hw->pf_id; 5841 ctxt.vf_num = hw->func_caps.vf_base_id + user_param; 5842 ctxt.uplink_seid = vsi->uplink_seid; 5843 ctxt.connection_type = 0x1; 5844 ctxt.flags = I40E_AQ_VSI_TYPE_VF; 5845 5846 /* Use the VEB configuration if FW >= v5.0 */ 5847 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) { 5848 /* Configure switch ID */ 5849 ctxt.info.valid_sections |= 5850 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5851 ctxt.info.switch_id = 5852 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5853 } 5854 5855 /* Configure port/vlan */ 5856 ctxt.info.valid_sections |= 5857 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5858 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 5859 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5860 hw->func_caps.enabled_tcmap); 5861 if (ret != I40E_SUCCESS) { 5862 PMD_DRV_LOG(ERR, 5863 "Failed to configure TC queue mapping"); 5864 goto fail_msix_alloc; 5865 } 5866 5867 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap; 5868 ctxt.info.valid_sections |= 5869 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5870 /** 5871 * Since VSI is not created yet, only configure parameter, 5872 * will add vsi below. 5873 */ 5874 5875 i40e_config_qinq(hw, vsi); 5876 } else if (type == I40E_VSI_VMDQ2) { 5877 memset(&ctxt, 0, sizeof(ctxt)); 5878 /* 5879 * For other VSI, the uplink_seid equals to uplink VSI's 5880 * uplink_seid since they share same VEB 5881 */ 5882 vsi->uplink_seid = uplink_vsi->uplink_seid; 5883 ctxt.pf_num = hw->pf_id; 5884 ctxt.vf_num = 0; 5885 ctxt.uplink_seid = vsi->uplink_seid; 5886 ctxt.connection_type = 0x1; 5887 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; 5888 5889 ctxt.info.valid_sections |= 5890 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5891 /* user_param carries flag to enable loop back */ 5892 if (user_param) { 5893 ctxt.info.switch_id = 5894 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB); 5895 ctxt.info.switch_id |= 5896 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5897 } 5898 5899 /* Configure port/vlan */ 5900 ctxt.info.valid_sections |= 5901 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5902 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 5903 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5904 I40E_DEFAULT_TCMAP); 5905 if (ret != I40E_SUCCESS) { 5906 PMD_DRV_LOG(ERR, 5907 "Failed to configure TC queue mapping"); 5908 goto fail_msix_alloc; 5909 } 5910 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP; 5911 ctxt.info.valid_sections |= 5912 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5913 } else if (type == I40E_VSI_FDIR) { 5914 memset(&ctxt, 0, sizeof(ctxt)); 5915 vsi->uplink_seid = uplink_vsi->uplink_seid; 5916 ctxt.pf_num = hw->pf_id; 5917 ctxt.vf_num = 0; 5918 ctxt.uplink_seid = vsi->uplink_seid; 5919 ctxt.connection_type = 0x1; /* regular data port */ 5920 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 5921 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5922 I40E_DEFAULT_TCMAP); 5923 if (ret != I40E_SUCCESS) { 5924 PMD_DRV_LOG(ERR, 5925 "Failed to configure TC queue mapping."); 5926 goto fail_msix_alloc; 5927 } 5928 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP; 5929 ctxt.info.valid_sections |= 5930 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5931 } else { 5932 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet"); 5933 goto fail_msix_alloc; 5934 } 5935 5936 if (vsi->type != I40E_VSI_MAIN) { 5937 ret = i40e_aq_add_vsi(hw, &ctxt, NULL); 5938 if (ret != I40E_SUCCESS) { 5939 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d", 5940 hw->aq.asq_last_status); 5941 goto fail_msix_alloc; 5942 } 5943 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 5944 vsi->info.valid_sections = 0; 5945 vsi->seid = ctxt.seid; 5946 vsi->vsi_id = ctxt.vsi_number; 5947 vsi->sib_vsi_list.vsi = vsi; 5948 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) { 5949 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head, 5950 &vsi->sib_vsi_list, list); 5951 } else { 5952 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head, 5953 &vsi->sib_vsi_list, list); 5954 } 5955 } 5956 5957 /* MAC/VLAN configuration */ 5958 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN); 5959 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5960 5961 ret = i40e_vsi_add_mac(vsi, &filter); 5962 if (ret != I40E_SUCCESS) { 5963 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter"); 5964 goto fail_msix_alloc; 5965 } 5966 5967 /* Get VSI BW information */ 5968 i40e_vsi_get_bw_config(vsi); 5969 return vsi; 5970 fail_msix_alloc: 5971 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr); 5972 fail_queue_alloc: 5973 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue); 5974 fail_mem: 5975 rte_free(vsi); 5976 return NULL; 5977 } 5978 5979 /* Configure vlan filter on or off */ 5980 int 5981 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on) 5982 { 5983 int i, num; 5984 struct i40e_mac_filter *f; 5985 void *temp; 5986 struct i40e_mac_filter_info *mac_filter; 5987 enum rte_mac_filter_type desired_filter; 5988 int ret = I40E_SUCCESS; 5989 5990 if (on) { 5991 /* Filter to match MAC and VLAN */ 5992 desired_filter = RTE_MACVLAN_PERFECT_MATCH; 5993 } else { 5994 /* Filter to match only MAC */ 5995 desired_filter = RTE_MAC_PERFECT_MATCH; 5996 } 5997 5998 num = vsi->mac_num; 5999 6000 mac_filter = rte_zmalloc("mac_filter_info_data", 6001 num * sizeof(*mac_filter), 0); 6002 if (mac_filter == NULL) { 6003 PMD_DRV_LOG(ERR, "failed to allocate memory"); 6004 return I40E_ERR_NO_MEMORY; 6005 } 6006 6007 i = 0; 6008 6009 /* Remove all existing mac */ 6010 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) { 6011 mac_filter[i] = f->mac_info; 6012 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr); 6013 if (ret) { 6014 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter", 6015 on ? "enable" : "disable"); 6016 goto DONE; 6017 } 6018 i++; 6019 } 6020 6021 /* Override with new filter */ 6022 for (i = 0; i < num; i++) { 6023 mac_filter[i].filter_type = desired_filter; 6024 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]); 6025 if (ret) { 6026 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter", 6027 on ? "enable" : "disable"); 6028 goto DONE; 6029 } 6030 } 6031 6032 DONE: 6033 rte_free(mac_filter); 6034 return ret; 6035 } 6036 6037 /* Configure vlan stripping on or off */ 6038 int 6039 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on) 6040 { 6041 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6042 struct i40e_vsi_context ctxt; 6043 uint8_t vlan_flags; 6044 int ret = I40E_SUCCESS; 6045 6046 /* Check if it has been already on or off */ 6047 if (vsi->info.valid_sections & 6048 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) { 6049 if (on) { 6050 if ((vsi->info.port_vlan_flags & 6051 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0) 6052 return 0; /* already on */ 6053 } else { 6054 if ((vsi->info.port_vlan_flags & 6055 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 6056 I40E_AQ_VSI_PVLAN_EMOD_MASK) 6057 return 0; /* already off */ 6058 } 6059 } 6060 6061 if (on) 6062 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 6063 else 6064 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 6065 vsi->info.valid_sections = 6066 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 6067 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK); 6068 vsi->info.port_vlan_flags |= vlan_flags; 6069 ctxt.seid = vsi->seid; 6070 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 6071 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 6072 if (ret) 6073 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 6074 on ? "enable" : "disable"); 6075 6076 return ret; 6077 } 6078 6079 static int 6080 i40e_dev_init_vlan(struct rte_eth_dev *dev) 6081 { 6082 struct rte_eth_dev_data *data = dev->data; 6083 int ret; 6084 int mask = 0; 6085 6086 /* Apply vlan offload setting */ 6087 mask = ETH_VLAN_STRIP_MASK | 6088 ETH_VLAN_FILTER_MASK | 6089 ETH_VLAN_EXTEND_MASK; 6090 ret = i40e_vlan_offload_set(dev, mask); 6091 if (ret) { 6092 PMD_DRV_LOG(INFO, "Failed to update vlan offload"); 6093 return ret; 6094 } 6095 6096 /* Apply pvid setting */ 6097 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid, 6098 data->dev_conf.txmode.hw_vlan_insert_pvid); 6099 if (ret) 6100 PMD_DRV_LOG(INFO, "Failed to update VSI params"); 6101 6102 return ret; 6103 } 6104 6105 static int 6106 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on) 6107 { 6108 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6109 6110 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL); 6111 } 6112 6113 static int 6114 i40e_update_flow_control(struct i40e_hw *hw) 6115 { 6116 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX) 6117 struct i40e_link_status link_status; 6118 uint32_t rxfc = 0, txfc = 0, reg; 6119 uint8_t an_info; 6120 int ret; 6121 6122 memset(&link_status, 0, sizeof(link_status)); 6123 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL); 6124 if (ret != I40E_SUCCESS) { 6125 PMD_DRV_LOG(ERR, "Failed to get link status information"); 6126 goto write_reg; /* Disable flow control */ 6127 } 6128 6129 an_info = hw->phy.link_info.an_info; 6130 if (!(an_info & I40E_AQ_AN_COMPLETED)) { 6131 PMD_DRV_LOG(INFO, "Link auto negotiation not completed"); 6132 ret = I40E_ERR_NOT_READY; 6133 goto write_reg; /* Disable flow control */ 6134 } 6135 /** 6136 * If link auto negotiation is enabled, flow control needs to 6137 * be configured according to it 6138 */ 6139 switch (an_info & I40E_LINK_PAUSE_RXTX) { 6140 case I40E_LINK_PAUSE_RXTX: 6141 rxfc = 1; 6142 txfc = 1; 6143 hw->fc.current_mode = I40E_FC_FULL; 6144 break; 6145 case I40E_AQ_LINK_PAUSE_RX: 6146 rxfc = 1; 6147 hw->fc.current_mode = I40E_FC_RX_PAUSE; 6148 break; 6149 case I40E_AQ_LINK_PAUSE_TX: 6150 txfc = 1; 6151 hw->fc.current_mode = I40E_FC_TX_PAUSE; 6152 break; 6153 default: 6154 hw->fc.current_mode = I40E_FC_NONE; 6155 break; 6156 } 6157 6158 write_reg: 6159 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG, 6160 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT); 6161 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); 6162 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK; 6163 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT; 6164 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg); 6165 6166 return ret; 6167 } 6168 6169 /* PF setup */ 6170 static int 6171 i40e_pf_setup(struct i40e_pf *pf) 6172 { 6173 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 6174 struct i40e_filter_control_settings settings; 6175 struct i40e_vsi *vsi; 6176 int ret; 6177 6178 /* Clear all stats counters */ 6179 pf->offset_loaded = FALSE; 6180 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats)); 6181 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats)); 6182 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats)); 6183 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats)); 6184 6185 ret = i40e_pf_get_switch_config(pf); 6186 if (ret != I40E_SUCCESS) { 6187 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret); 6188 return ret; 6189 } 6190 6191 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id); 6192 if (ret) 6193 PMD_INIT_LOG(WARNING, 6194 "failed to allocate switch domain for device %d", ret); 6195 6196 if (pf->flags & I40E_FLAG_FDIR) { 6197 /* make queue allocated first, let FDIR use queue pair 0*/ 6198 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR); 6199 if (ret != I40E_FDIR_QUEUE_ID) { 6200 PMD_DRV_LOG(ERR, 6201 "queue allocation fails for FDIR: ret =%d", 6202 ret); 6203 pf->flags &= ~I40E_FLAG_FDIR; 6204 } 6205 } 6206 /* main VSI setup */ 6207 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0); 6208 if (!vsi) { 6209 PMD_DRV_LOG(ERR, "Setup of main vsi failed"); 6210 return I40E_ERR_NOT_READY; 6211 } 6212 pf->main_vsi = vsi; 6213 6214 /* Configure filter control */ 6215 memset(&settings, 0, sizeof(settings)); 6216 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128) 6217 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128; 6218 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512) 6219 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512; 6220 else { 6221 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported", 6222 hw->func_caps.rss_table_size); 6223 return I40E_ERR_PARAM; 6224 } 6225 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u", 6226 hw->func_caps.rss_table_size); 6227 pf->hash_lut_size = hw->func_caps.rss_table_size; 6228 6229 /* Enable ethtype and macvlan filters */ 6230 settings.enable_ethtype = TRUE; 6231 settings.enable_macvlan = TRUE; 6232 ret = i40e_set_filter_control(hw, &settings); 6233 if (ret) 6234 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d", 6235 ret); 6236 6237 /* Update flow control according to the auto negotiation */ 6238 i40e_update_flow_control(hw); 6239 6240 return I40E_SUCCESS; 6241 } 6242 6243 int 6244 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) 6245 { 6246 uint32_t reg; 6247 uint16_t j; 6248 6249 /** 6250 * Set or clear TX Queue Disable flags, 6251 * which is required by hardware. 6252 */ 6253 i40e_pre_tx_queue_cfg(hw, q_idx, on); 6254 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US); 6255 6256 /* Wait until the request is finished */ 6257 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6258 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6259 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx)); 6260 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^ 6261 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) 6262 & 0x1))) { 6263 break; 6264 } 6265 } 6266 if (on) { 6267 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 6268 return I40E_SUCCESS; /* already on, skip next steps */ 6269 6270 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0); 6271 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 6272 } else { 6273 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6274 return I40E_SUCCESS; /* already off, skip next steps */ 6275 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 6276 } 6277 /* Write the register */ 6278 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg); 6279 /* Check the result */ 6280 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6281 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6282 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx)); 6283 if (on) { 6284 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) && 6285 (reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6286 break; 6287 } else { 6288 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) && 6289 !(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6290 break; 6291 } 6292 } 6293 /* Check if it is timeout */ 6294 if (j >= I40E_CHK_Q_ENA_COUNT) { 6295 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]", 6296 (on ? "enable" : "disable"), q_idx); 6297 return I40E_ERR_TIMEOUT; 6298 } 6299 6300 return I40E_SUCCESS; 6301 } 6302 6303 int 6304 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) 6305 { 6306 uint32_t reg; 6307 uint16_t j; 6308 6309 /* Wait until the request is finished */ 6310 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6311 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6312 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); 6313 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^ 6314 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1)) 6315 break; 6316 } 6317 6318 if (on) { 6319 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 6320 return I40E_SUCCESS; /* Already on, skip next steps */ 6321 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 6322 } else { 6323 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6324 return I40E_SUCCESS; /* Already off, skip next steps */ 6325 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 6326 } 6327 6328 /* Write the register */ 6329 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg); 6330 /* Check the result */ 6331 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6332 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6333 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); 6334 if (on) { 6335 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) && 6336 (reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6337 break; 6338 } else { 6339 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) && 6340 !(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6341 break; 6342 } 6343 } 6344 6345 /* Check if it is timeout */ 6346 if (j >= I40E_CHK_Q_ENA_COUNT) { 6347 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]", 6348 (on ? "enable" : "disable"), q_idx); 6349 return I40E_ERR_TIMEOUT; 6350 } 6351 6352 return I40E_SUCCESS; 6353 } 6354 6355 /* Initialize VSI for TX */ 6356 static int 6357 i40e_dev_tx_init(struct i40e_pf *pf) 6358 { 6359 struct rte_eth_dev_data *data = pf->dev_data; 6360 uint16_t i; 6361 uint32_t ret = I40E_SUCCESS; 6362 struct i40e_tx_queue *txq; 6363 6364 for (i = 0; i < data->nb_tx_queues; i++) { 6365 txq = data->tx_queues[i]; 6366 if (!txq || !txq->q_set) 6367 continue; 6368 ret = i40e_tx_queue_init(txq); 6369 if (ret != I40E_SUCCESS) 6370 break; 6371 } 6372 if (ret == I40E_SUCCESS) 6373 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf) 6374 ->eth_dev); 6375 6376 return ret; 6377 } 6378 6379 /* Initialize VSI for RX */ 6380 static int 6381 i40e_dev_rx_init(struct i40e_pf *pf) 6382 { 6383 struct rte_eth_dev_data *data = pf->dev_data; 6384 int ret = I40E_SUCCESS; 6385 uint16_t i; 6386 struct i40e_rx_queue *rxq; 6387 6388 i40e_pf_config_mq_rx(pf); 6389 for (i = 0; i < data->nb_rx_queues; i++) { 6390 rxq = data->rx_queues[i]; 6391 if (!rxq || !rxq->q_set) 6392 continue; 6393 6394 ret = i40e_rx_queue_init(rxq); 6395 if (ret != I40E_SUCCESS) { 6396 PMD_DRV_LOG(ERR, 6397 "Failed to do RX queue initialization"); 6398 break; 6399 } 6400 } 6401 if (ret == I40E_SUCCESS) 6402 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf) 6403 ->eth_dev); 6404 6405 return ret; 6406 } 6407 6408 static int 6409 i40e_dev_rxtx_init(struct i40e_pf *pf) 6410 { 6411 int err; 6412 6413 err = i40e_dev_tx_init(pf); 6414 if (err) { 6415 PMD_DRV_LOG(ERR, "Failed to do TX initialization"); 6416 return err; 6417 } 6418 err = i40e_dev_rx_init(pf); 6419 if (err) { 6420 PMD_DRV_LOG(ERR, "Failed to do RX initialization"); 6421 return err; 6422 } 6423 6424 return err; 6425 } 6426 6427 static int 6428 i40e_vmdq_setup(struct rte_eth_dev *dev) 6429 { 6430 struct rte_eth_conf *conf = &dev->data->dev_conf; 6431 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6432 int i, err, conf_vsis, j, loop; 6433 struct i40e_vsi *vsi; 6434 struct i40e_vmdq_info *vmdq_info; 6435 struct rte_eth_vmdq_rx_conf *vmdq_conf; 6436 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 6437 6438 /* 6439 * Disable interrupt to avoid message from VF. Furthermore, it will 6440 * avoid race condition in VSI creation/destroy. 6441 */ 6442 i40e_pf_disable_irq0(hw); 6443 6444 if ((pf->flags & I40E_FLAG_VMDQ) == 0) { 6445 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ"); 6446 return -ENOTSUP; 6447 } 6448 6449 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools; 6450 if (conf_vsis > pf->max_nb_vmdq_vsi) { 6451 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u", 6452 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools, 6453 pf->max_nb_vmdq_vsi); 6454 return -ENOTSUP; 6455 } 6456 6457 if (pf->vmdq != NULL) { 6458 PMD_INIT_LOG(INFO, "VMDQ already configured"); 6459 return 0; 6460 } 6461 6462 pf->vmdq = rte_zmalloc("vmdq_info_struct", 6463 sizeof(*vmdq_info) * conf_vsis, 0); 6464 6465 if (pf->vmdq == NULL) { 6466 PMD_INIT_LOG(ERR, "Failed to allocate memory"); 6467 return -ENOMEM; 6468 } 6469 6470 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf; 6471 6472 /* Create VMDQ VSI */ 6473 for (i = 0; i < conf_vsis; i++) { 6474 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi, 6475 vmdq_conf->enable_loop_back); 6476 if (vsi == NULL) { 6477 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI"); 6478 err = -1; 6479 goto err_vsi_setup; 6480 } 6481 vmdq_info = &pf->vmdq[i]; 6482 vmdq_info->pf = pf; 6483 vmdq_info->vsi = vsi; 6484 } 6485 pf->nb_cfg_vmdq_vsi = conf_vsis; 6486 6487 /* Configure Vlan */ 6488 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT; 6489 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) { 6490 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) { 6491 if (vmdq_conf->pool_map[i].pools & (1UL << j)) { 6492 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u", 6493 vmdq_conf->pool_map[i].vlan_id, j); 6494 6495 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi, 6496 vmdq_conf->pool_map[i].vlan_id); 6497 if (err) { 6498 PMD_INIT_LOG(ERR, "Failed to add vlan"); 6499 err = -1; 6500 goto err_vsi_setup; 6501 } 6502 } 6503 } 6504 } 6505 6506 i40e_pf_enable_irq0(hw); 6507 6508 return 0; 6509 6510 err_vsi_setup: 6511 for (i = 0; i < conf_vsis; i++) 6512 if (pf->vmdq[i].vsi == NULL) 6513 break; 6514 else 6515 i40e_vsi_release(pf->vmdq[i].vsi); 6516 6517 rte_free(pf->vmdq); 6518 pf->vmdq = NULL; 6519 i40e_pf_enable_irq0(hw); 6520 return err; 6521 } 6522 6523 static void 6524 i40e_stat_update_32(struct i40e_hw *hw, 6525 uint32_t reg, 6526 bool offset_loaded, 6527 uint64_t *offset, 6528 uint64_t *stat) 6529 { 6530 uint64_t new_data; 6531 6532 new_data = (uint64_t)I40E_READ_REG(hw, reg); 6533 if (!offset_loaded) 6534 *offset = new_data; 6535 6536 if (new_data >= *offset) 6537 *stat = (uint64_t)(new_data - *offset); 6538 else 6539 *stat = (uint64_t)((new_data + 6540 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset); 6541 } 6542 6543 static void 6544 i40e_stat_update_48(struct i40e_hw *hw, 6545 uint32_t hireg, 6546 uint32_t loreg, 6547 bool offset_loaded, 6548 uint64_t *offset, 6549 uint64_t *stat) 6550 { 6551 uint64_t new_data; 6552 6553 new_data = (uint64_t)I40E_READ_REG(hw, loreg); 6554 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & 6555 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; 6556 6557 if (!offset_loaded) 6558 *offset = new_data; 6559 6560 if (new_data >= *offset) 6561 *stat = new_data - *offset; 6562 else 6563 *stat = (uint64_t)((new_data + 6564 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset); 6565 6566 *stat &= I40E_48_BIT_MASK; 6567 } 6568 6569 /* Disable IRQ0 */ 6570 void 6571 i40e_pf_disable_irq0(struct i40e_hw *hw) 6572 { 6573 /* Disable all interrupt types */ 6574 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 6575 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 6576 I40E_WRITE_FLUSH(hw); 6577 } 6578 6579 /* Enable IRQ0 */ 6580 void 6581 i40e_pf_enable_irq0(struct i40e_hw *hw) 6582 { 6583 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 6584 I40E_PFINT_DYN_CTL0_INTENA_MASK | 6585 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 6586 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 6587 I40E_WRITE_FLUSH(hw); 6588 } 6589 6590 static void 6591 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue) 6592 { 6593 /* read pending request and disable first */ 6594 i40e_pf_disable_irq0(hw); 6595 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK); 6596 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0, 6597 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK); 6598 6599 if (no_queue) 6600 /* Link no queues with irq0 */ 6601 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 6602 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); 6603 } 6604 6605 static void 6606 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev) 6607 { 6608 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6609 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6610 int i; 6611 uint16_t abs_vf_id; 6612 uint32_t index, offset, val; 6613 6614 if (!pf->vfs) 6615 return; 6616 /** 6617 * Try to find which VF trigger a reset, use absolute VF id to access 6618 * since the reg is global register. 6619 */ 6620 for (i = 0; i < pf->vf_num; i++) { 6621 abs_vf_id = hw->func_caps.vf_base_id + i; 6622 index = abs_vf_id / I40E_UINT32_BIT_SIZE; 6623 offset = abs_vf_id % I40E_UINT32_BIT_SIZE; 6624 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index)); 6625 /* VFR event occurred */ 6626 if (val & (0x1 << offset)) { 6627 int ret; 6628 6629 /* Clear the event first */ 6630 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index), 6631 (0x1 << offset)); 6632 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id); 6633 /** 6634 * Only notify a VF reset event occurred, 6635 * don't trigger another SW reset 6636 */ 6637 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0); 6638 if (ret != I40E_SUCCESS) 6639 PMD_DRV_LOG(ERR, "Failed to do VF reset"); 6640 } 6641 } 6642 } 6643 6644 static void 6645 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev) 6646 { 6647 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6648 int i; 6649 6650 for (i = 0; i < pf->vf_num; i++) 6651 i40e_notify_vf_link_status(dev, &pf->vfs[i]); 6652 } 6653 6654 static void 6655 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev) 6656 { 6657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6658 struct i40e_arq_event_info info; 6659 uint16_t pending, opcode; 6660 int ret; 6661 6662 info.buf_len = I40E_AQ_BUF_SZ; 6663 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0); 6664 if (!info.msg_buf) { 6665 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 6666 return; 6667 } 6668 6669 pending = 1; 6670 while (pending) { 6671 ret = i40e_clean_arq_element(hw, &info, &pending); 6672 6673 if (ret != I40E_SUCCESS) { 6674 PMD_DRV_LOG(INFO, 6675 "Failed to read msg from AdminQ, aq_err: %u", 6676 hw->aq.asq_last_status); 6677 break; 6678 } 6679 opcode = rte_le_to_cpu_16(info.desc.opcode); 6680 6681 switch (opcode) { 6682 case i40e_aqc_opc_send_msg_to_pf: 6683 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/ 6684 i40e_pf_host_handle_vf_msg(dev, 6685 rte_le_to_cpu_16(info.desc.retval), 6686 rte_le_to_cpu_32(info.desc.cookie_high), 6687 rte_le_to_cpu_32(info.desc.cookie_low), 6688 info.msg_buf, 6689 info.msg_len); 6690 break; 6691 case i40e_aqc_opc_get_link_status: 6692 ret = i40e_dev_link_update(dev, 0); 6693 if (!ret) 6694 _rte_eth_dev_callback_process(dev, 6695 RTE_ETH_EVENT_INTR_LSC, NULL); 6696 break; 6697 default: 6698 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 6699 opcode); 6700 break; 6701 } 6702 } 6703 rte_free(info.msg_buf); 6704 } 6705 6706 static void 6707 i40e_handle_mdd_event(struct rte_eth_dev *dev) 6708 { 6709 #define I40E_MDD_CLEAR32 0xFFFFFFFF 6710 #define I40E_MDD_CLEAR16 0xFFFF 6711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6712 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6713 bool mdd_detected = false; 6714 struct i40e_pf_vf *vf; 6715 uint32_t reg; 6716 int i; 6717 6718 /* find what triggered the MDD event */ 6719 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX); 6720 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 6721 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> 6722 I40E_GL_MDET_TX_PF_NUM_SHIFT; 6723 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> 6724 I40E_GL_MDET_TX_VF_NUM_SHIFT; 6725 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> 6726 I40E_GL_MDET_TX_EVENT_SHIFT; 6727 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> 6728 I40E_GL_MDET_TX_QUEUE_SHIFT) - 6729 hw->func_caps.base_queue; 6730 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX " 6731 "queue %d PF number 0x%02x VF number 0x%02x device %s\n", 6732 event, queue, pf_num, vf_num, dev->data->name); 6733 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32); 6734 mdd_detected = true; 6735 } 6736 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX); 6737 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 6738 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> 6739 I40E_GL_MDET_RX_FUNCTION_SHIFT; 6740 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> 6741 I40E_GL_MDET_RX_EVENT_SHIFT; 6742 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> 6743 I40E_GL_MDET_RX_QUEUE_SHIFT) - 6744 hw->func_caps.base_queue; 6745 6746 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX " 6747 "queue %d of function 0x%02x device %s\n", 6748 event, queue, func, dev->data->name); 6749 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32); 6750 mdd_detected = true; 6751 } 6752 6753 if (mdd_detected) { 6754 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX); 6755 if (reg & I40E_PF_MDET_TX_VALID_MASK) { 6756 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16); 6757 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n"); 6758 } 6759 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX); 6760 if (reg & I40E_PF_MDET_RX_VALID_MASK) { 6761 I40E_WRITE_REG(hw, I40E_PF_MDET_RX, 6762 I40E_MDD_CLEAR16); 6763 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n"); 6764 } 6765 } 6766 6767 /* see if one of the VFs needs its hand slapped */ 6768 for (i = 0; i < pf->vf_num && mdd_detected; i++) { 6769 vf = &pf->vfs[i]; 6770 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i)); 6771 if (reg & I40E_VP_MDET_TX_VALID_MASK) { 6772 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i), 6773 I40E_MDD_CLEAR16); 6774 vf->num_mdd_events++; 6775 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-" 6776 PRIu64 "times\n", 6777 i, vf->num_mdd_events); 6778 } 6779 6780 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i)); 6781 if (reg & I40E_VP_MDET_RX_VALID_MASK) { 6782 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i), 6783 I40E_MDD_CLEAR16); 6784 vf->num_mdd_events++; 6785 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-" 6786 PRIu64 "times\n", 6787 i, vf->num_mdd_events); 6788 } 6789 } 6790 } 6791 6792 /** 6793 * Interrupt handler triggered by NIC for handling 6794 * specific interrupt. 6795 * 6796 * @param handle 6797 * Pointer to interrupt handle. 6798 * @param param 6799 * The address of parameter (struct rte_eth_dev *) regsitered before. 6800 * 6801 * @return 6802 * void 6803 */ 6804 static void 6805 i40e_dev_interrupt_handler(void *param) 6806 { 6807 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 6808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6809 uint32_t icr0; 6810 6811 /* Disable interrupt */ 6812 i40e_pf_disable_irq0(hw); 6813 6814 /* read out interrupt causes */ 6815 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); 6816 6817 /* No interrupt event indicated */ 6818 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) { 6819 PMD_DRV_LOG(INFO, "No interrupt event"); 6820 goto done; 6821 } 6822 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) 6823 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); 6824 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { 6825 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); 6826 i40e_handle_mdd_event(dev); 6827 } 6828 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) 6829 PMD_DRV_LOG(INFO, "ICR0: global reset requested"); 6830 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) 6831 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); 6832 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) 6833 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); 6834 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) 6835 PMD_DRV_LOG(ERR, "ICR0: HMC error"); 6836 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) 6837 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); 6838 6839 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 6840 PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); 6841 i40e_dev_handle_vfr_event(dev); 6842 } 6843 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 6844 PMD_DRV_LOG(INFO, "ICR0: adminq event"); 6845 i40e_dev_handle_aq_msg(dev); 6846 } 6847 6848 done: 6849 /* Enable interrupt */ 6850 i40e_pf_enable_irq0(hw); 6851 } 6852 6853 static void 6854 i40e_dev_alarm_handler(void *param) 6855 { 6856 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 6857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6858 uint32_t icr0; 6859 6860 /* Disable interrupt */ 6861 i40e_pf_disable_irq0(hw); 6862 6863 /* read out interrupt causes */ 6864 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); 6865 6866 /* No interrupt event indicated */ 6867 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) 6868 goto done; 6869 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) 6870 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); 6871 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { 6872 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); 6873 i40e_handle_mdd_event(dev); 6874 } 6875 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) 6876 PMD_DRV_LOG(INFO, "ICR0: global reset requested"); 6877 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) 6878 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); 6879 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) 6880 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); 6881 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) 6882 PMD_DRV_LOG(ERR, "ICR0: HMC error"); 6883 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) 6884 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); 6885 6886 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 6887 PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); 6888 i40e_dev_handle_vfr_event(dev); 6889 } 6890 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 6891 PMD_DRV_LOG(INFO, "ICR0: adminq event"); 6892 i40e_dev_handle_aq_msg(dev); 6893 } 6894 6895 done: 6896 /* Enable interrupt */ 6897 i40e_pf_enable_irq0(hw); 6898 rte_eal_alarm_set(I40E_ALARM_INTERVAL, 6899 i40e_dev_alarm_handler, dev); 6900 } 6901 6902 int 6903 i40e_add_macvlan_filters(struct i40e_vsi *vsi, 6904 struct i40e_macvlan_filter *filter, 6905 int total) 6906 { 6907 int ele_num, ele_buff_size; 6908 int num, actual_num, i; 6909 uint16_t flags; 6910 int ret = I40E_SUCCESS; 6911 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6912 struct i40e_aqc_add_macvlan_element_data *req_list; 6913 6914 if (filter == NULL || total == 0) 6915 return I40E_ERR_PARAM; 6916 ele_num = hw->aq.asq_buf_size / sizeof(*req_list); 6917 ele_buff_size = hw->aq.asq_buf_size; 6918 6919 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0); 6920 if (req_list == NULL) { 6921 PMD_DRV_LOG(ERR, "Fail to allocate memory"); 6922 return I40E_ERR_NO_MEMORY; 6923 } 6924 6925 num = 0; 6926 do { 6927 actual_num = (num + ele_num > total) ? (total - num) : ele_num; 6928 memset(req_list, 0, ele_buff_size); 6929 6930 for (i = 0; i < actual_num; i++) { 6931 rte_memcpy(req_list[i].mac_addr, 6932 &filter[num + i].macaddr, ETH_ADDR_LEN); 6933 req_list[i].vlan_tag = 6934 rte_cpu_to_le_16(filter[num + i].vlan_id); 6935 6936 switch (filter[num + i].filter_type) { 6937 case RTE_MAC_PERFECT_MATCH: 6938 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH | 6939 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 6940 break; 6941 case RTE_MACVLAN_PERFECT_MATCH: 6942 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 6943 break; 6944 case RTE_MAC_HASH_MATCH: 6945 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH | 6946 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 6947 break; 6948 case RTE_MACVLAN_HASH_MATCH: 6949 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH; 6950 break; 6951 default: 6952 PMD_DRV_LOG(ERR, "Invalid MAC match type"); 6953 ret = I40E_ERR_PARAM; 6954 goto DONE; 6955 } 6956 6957 req_list[i].queue_number = 0; 6958 6959 req_list[i].flags = rte_cpu_to_le_16(flags); 6960 } 6961 6962 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list, 6963 actual_num, NULL); 6964 if (ret != I40E_SUCCESS) { 6965 PMD_DRV_LOG(ERR, "Failed to add macvlan filter"); 6966 goto DONE; 6967 } 6968 num += actual_num; 6969 } while (num < total); 6970 6971 DONE: 6972 rte_free(req_list); 6973 return ret; 6974 } 6975 6976 int 6977 i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 6978 struct i40e_macvlan_filter *filter, 6979 int total) 6980 { 6981 int ele_num, ele_buff_size; 6982 int num, actual_num, i; 6983 uint16_t flags; 6984 int ret = I40E_SUCCESS; 6985 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6986 struct i40e_aqc_remove_macvlan_element_data *req_list; 6987 6988 if (filter == NULL || total == 0) 6989 return I40E_ERR_PARAM; 6990 6991 ele_num = hw->aq.asq_buf_size / sizeof(*req_list); 6992 ele_buff_size = hw->aq.asq_buf_size; 6993 6994 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0); 6995 if (req_list == NULL) { 6996 PMD_DRV_LOG(ERR, "Fail to allocate memory"); 6997 return I40E_ERR_NO_MEMORY; 6998 } 6999 7000 num = 0; 7001 do { 7002 actual_num = (num + ele_num > total) ? (total - num) : ele_num; 7003 memset(req_list, 0, ele_buff_size); 7004 7005 for (i = 0; i < actual_num; i++) { 7006 rte_memcpy(req_list[i].mac_addr, 7007 &filter[num + i].macaddr, ETH_ADDR_LEN); 7008 req_list[i].vlan_tag = 7009 rte_cpu_to_le_16(filter[num + i].vlan_id); 7010 7011 switch (filter[num + i].filter_type) { 7012 case RTE_MAC_PERFECT_MATCH: 7013 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 7014 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 7015 break; 7016 case RTE_MACVLAN_PERFECT_MATCH: 7017 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 7018 break; 7019 case RTE_MAC_HASH_MATCH: 7020 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH | 7021 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 7022 break; 7023 case RTE_MACVLAN_HASH_MATCH: 7024 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH; 7025 break; 7026 default: 7027 PMD_DRV_LOG(ERR, "Invalid MAC filter type"); 7028 ret = I40E_ERR_PARAM; 7029 goto DONE; 7030 } 7031 req_list[i].flags = rte_cpu_to_le_16(flags); 7032 } 7033 7034 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list, 7035 actual_num, NULL); 7036 if (ret != I40E_SUCCESS) { 7037 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter"); 7038 goto DONE; 7039 } 7040 num += actual_num; 7041 } while (num < total); 7042 7043 DONE: 7044 rte_free(req_list); 7045 return ret; 7046 } 7047 7048 /* Find out specific MAC filter */ 7049 static struct i40e_mac_filter * 7050 i40e_find_mac_filter(struct i40e_vsi *vsi, 7051 struct rte_ether_addr *macaddr) 7052 { 7053 struct i40e_mac_filter *f; 7054 7055 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7056 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 7057 return f; 7058 } 7059 7060 return NULL; 7061 } 7062 7063 static bool 7064 i40e_find_vlan_filter(struct i40e_vsi *vsi, 7065 uint16_t vlan_id) 7066 { 7067 uint32_t vid_idx, vid_bit; 7068 7069 if (vlan_id > ETH_VLAN_ID_MAX) 7070 return 0; 7071 7072 vid_idx = I40E_VFTA_IDX(vlan_id); 7073 vid_bit = I40E_VFTA_BIT(vlan_id); 7074 7075 if (vsi->vfta[vid_idx] & vid_bit) 7076 return 1; 7077 else 7078 return 0; 7079 } 7080 7081 static void 7082 i40e_store_vlan_filter(struct i40e_vsi *vsi, 7083 uint16_t vlan_id, bool on) 7084 { 7085 uint32_t vid_idx, vid_bit; 7086 7087 vid_idx = I40E_VFTA_IDX(vlan_id); 7088 vid_bit = I40E_VFTA_BIT(vlan_id); 7089 7090 if (on) 7091 vsi->vfta[vid_idx] |= vid_bit; 7092 else 7093 vsi->vfta[vid_idx] &= ~vid_bit; 7094 } 7095 7096 void 7097 i40e_set_vlan_filter(struct i40e_vsi *vsi, 7098 uint16_t vlan_id, bool on) 7099 { 7100 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7101 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0}; 7102 int ret; 7103 7104 if (vlan_id > ETH_VLAN_ID_MAX) 7105 return; 7106 7107 i40e_store_vlan_filter(vsi, vlan_id, on); 7108 7109 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id) 7110 return; 7111 7112 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id); 7113 7114 if (on) { 7115 ret = i40e_aq_add_vlan(hw, vsi->seid, 7116 &vlan_data, 1, NULL); 7117 if (ret != I40E_SUCCESS) 7118 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 7119 } else { 7120 ret = i40e_aq_remove_vlan(hw, vsi->seid, 7121 &vlan_data, 1, NULL); 7122 if (ret != I40E_SUCCESS) 7123 PMD_DRV_LOG(ERR, 7124 "Failed to remove vlan filter"); 7125 } 7126 } 7127 7128 /** 7129 * Find all vlan options for specific mac addr, 7130 * return with actual vlan found. 7131 */ 7132 int 7133 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 7134 struct i40e_macvlan_filter *mv_f, 7135 int num, struct rte_ether_addr *addr) 7136 { 7137 int i; 7138 uint32_t j, k; 7139 7140 /** 7141 * Not to use i40e_find_vlan_filter to decrease the loop time, 7142 * although the code looks complex. 7143 */ 7144 if (num < vsi->vlan_num) 7145 return I40E_ERR_PARAM; 7146 7147 i = 0; 7148 for (j = 0; j < I40E_VFTA_SIZE; j++) { 7149 if (vsi->vfta[j]) { 7150 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) { 7151 if (vsi->vfta[j] & (1 << k)) { 7152 if (i > num - 1) { 7153 PMD_DRV_LOG(ERR, 7154 "vlan number doesn't match"); 7155 return I40E_ERR_PARAM; 7156 } 7157 rte_memcpy(&mv_f[i].macaddr, 7158 addr, ETH_ADDR_LEN); 7159 mv_f[i].vlan_id = 7160 j * I40E_UINT32_BIT_SIZE + k; 7161 i++; 7162 } 7163 } 7164 } 7165 } 7166 return I40E_SUCCESS; 7167 } 7168 7169 static inline int 7170 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi, 7171 struct i40e_macvlan_filter *mv_f, 7172 int num, 7173 uint16_t vlan) 7174 { 7175 int i = 0; 7176 struct i40e_mac_filter *f; 7177 7178 if (num < vsi->mac_num) 7179 return I40E_ERR_PARAM; 7180 7181 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7182 if (i > num - 1) { 7183 PMD_DRV_LOG(ERR, "buffer number not match"); 7184 return I40E_ERR_PARAM; 7185 } 7186 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr, 7187 ETH_ADDR_LEN); 7188 mv_f[i].vlan_id = vlan; 7189 mv_f[i].filter_type = f->mac_info.filter_type; 7190 i++; 7191 } 7192 7193 return I40E_SUCCESS; 7194 } 7195 7196 static int 7197 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi) 7198 { 7199 int i, j, num; 7200 struct i40e_mac_filter *f; 7201 struct i40e_macvlan_filter *mv_f; 7202 int ret = I40E_SUCCESS; 7203 7204 if (vsi == NULL || vsi->mac_num == 0) 7205 return I40E_ERR_PARAM; 7206 7207 /* Case that no vlan is set */ 7208 if (vsi->vlan_num == 0) 7209 num = vsi->mac_num; 7210 else 7211 num = vsi->mac_num * vsi->vlan_num; 7212 7213 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0); 7214 if (mv_f == NULL) { 7215 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7216 return I40E_ERR_NO_MEMORY; 7217 } 7218 7219 i = 0; 7220 if (vsi->vlan_num == 0) { 7221 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7222 rte_memcpy(&mv_f[i].macaddr, 7223 &f->mac_info.mac_addr, ETH_ADDR_LEN); 7224 mv_f[i].filter_type = f->mac_info.filter_type; 7225 mv_f[i].vlan_id = 0; 7226 i++; 7227 } 7228 } else { 7229 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7230 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i], 7231 vsi->vlan_num, &f->mac_info.mac_addr); 7232 if (ret != I40E_SUCCESS) 7233 goto DONE; 7234 for (j = i; j < i + vsi->vlan_num; j++) 7235 mv_f[j].filter_type = f->mac_info.filter_type; 7236 i += vsi->vlan_num; 7237 } 7238 } 7239 7240 ret = i40e_remove_macvlan_filters(vsi, mv_f, num); 7241 DONE: 7242 rte_free(mv_f); 7243 7244 return ret; 7245 } 7246 7247 int 7248 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan) 7249 { 7250 struct i40e_macvlan_filter *mv_f; 7251 int mac_num; 7252 int ret = I40E_SUCCESS; 7253 7254 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID) 7255 return I40E_ERR_PARAM; 7256 7257 /* If it's already set, just return */ 7258 if (i40e_find_vlan_filter(vsi,vlan)) 7259 return I40E_SUCCESS; 7260 7261 mac_num = vsi->mac_num; 7262 7263 if (mac_num == 0) { 7264 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr"); 7265 return I40E_ERR_PARAM; 7266 } 7267 7268 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0); 7269 7270 if (mv_f == NULL) { 7271 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7272 return I40E_ERR_NO_MEMORY; 7273 } 7274 7275 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan); 7276 7277 if (ret != I40E_SUCCESS) 7278 goto DONE; 7279 7280 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num); 7281 7282 if (ret != I40E_SUCCESS) 7283 goto DONE; 7284 7285 i40e_set_vlan_filter(vsi, vlan, 1); 7286 7287 vsi->vlan_num++; 7288 ret = I40E_SUCCESS; 7289 DONE: 7290 rte_free(mv_f); 7291 return ret; 7292 } 7293 7294 int 7295 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan) 7296 { 7297 struct i40e_macvlan_filter *mv_f; 7298 int mac_num; 7299 int ret = I40E_SUCCESS; 7300 7301 /** 7302 * Vlan 0 is the generic filter for untagged packets 7303 * and can't be removed. 7304 */ 7305 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID) 7306 return I40E_ERR_PARAM; 7307 7308 /* If can't find it, just return */ 7309 if (!i40e_find_vlan_filter(vsi, vlan)) 7310 return I40E_ERR_PARAM; 7311 7312 mac_num = vsi->mac_num; 7313 7314 if (mac_num == 0) { 7315 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr"); 7316 return I40E_ERR_PARAM; 7317 } 7318 7319 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0); 7320 7321 if (mv_f == NULL) { 7322 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7323 return I40E_ERR_NO_MEMORY; 7324 } 7325 7326 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan); 7327 7328 if (ret != I40E_SUCCESS) 7329 goto DONE; 7330 7331 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num); 7332 7333 if (ret != I40E_SUCCESS) 7334 goto DONE; 7335 7336 /* This is last vlan to remove, replace all mac filter with vlan 0 */ 7337 if (vsi->vlan_num == 1) { 7338 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0); 7339 if (ret != I40E_SUCCESS) 7340 goto DONE; 7341 7342 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num); 7343 if (ret != I40E_SUCCESS) 7344 goto DONE; 7345 } 7346 7347 i40e_set_vlan_filter(vsi, vlan, 0); 7348 7349 vsi->vlan_num--; 7350 ret = I40E_SUCCESS; 7351 DONE: 7352 rte_free(mv_f); 7353 return ret; 7354 } 7355 7356 int 7357 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter) 7358 { 7359 struct i40e_mac_filter *f; 7360 struct i40e_macvlan_filter *mv_f; 7361 int i, vlan_num = 0; 7362 int ret = I40E_SUCCESS; 7363 7364 /* If it's add and we've config it, return */ 7365 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr); 7366 if (f != NULL) 7367 return I40E_SUCCESS; 7368 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) || 7369 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) { 7370 7371 /** 7372 * If vlan_num is 0, that's the first time to add mac, 7373 * set mask for vlan_id 0. 7374 */ 7375 if (vsi->vlan_num == 0) { 7376 i40e_set_vlan_filter(vsi, 0, 1); 7377 vsi->vlan_num = 1; 7378 } 7379 vlan_num = vsi->vlan_num; 7380 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) || 7381 (mac_filter->filter_type == RTE_MAC_HASH_MATCH)) 7382 vlan_num = 1; 7383 7384 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0); 7385 if (mv_f == NULL) { 7386 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7387 return I40E_ERR_NO_MEMORY; 7388 } 7389 7390 for (i = 0; i < vlan_num; i++) { 7391 mv_f[i].filter_type = mac_filter->filter_type; 7392 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr, 7393 ETH_ADDR_LEN); 7394 } 7395 7396 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH || 7397 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) { 7398 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, 7399 &mac_filter->mac_addr); 7400 if (ret != I40E_SUCCESS) 7401 goto DONE; 7402 } 7403 7404 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num); 7405 if (ret != I40E_SUCCESS) 7406 goto DONE; 7407 7408 /* Add the mac addr into mac list */ 7409 f = rte_zmalloc("macv_filter", sizeof(*f), 0); 7410 if (f == NULL) { 7411 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7412 ret = I40E_ERR_NO_MEMORY; 7413 goto DONE; 7414 } 7415 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr, 7416 ETH_ADDR_LEN); 7417 f->mac_info.filter_type = mac_filter->filter_type; 7418 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 7419 vsi->mac_num++; 7420 7421 ret = I40E_SUCCESS; 7422 DONE: 7423 rte_free(mv_f); 7424 7425 return ret; 7426 } 7427 7428 int 7429 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr) 7430 { 7431 struct i40e_mac_filter *f; 7432 struct i40e_macvlan_filter *mv_f; 7433 int i, vlan_num; 7434 enum rte_mac_filter_type filter_type; 7435 int ret = I40E_SUCCESS; 7436 7437 /* Can't find it, return an error */ 7438 f = i40e_find_mac_filter(vsi, addr); 7439 if (f == NULL) 7440 return I40E_ERR_PARAM; 7441 7442 vlan_num = vsi->vlan_num; 7443 filter_type = f->mac_info.filter_type; 7444 if (filter_type == RTE_MACVLAN_PERFECT_MATCH || 7445 filter_type == RTE_MACVLAN_HASH_MATCH) { 7446 if (vlan_num == 0) { 7447 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0"); 7448 return I40E_ERR_PARAM; 7449 } 7450 } else if (filter_type == RTE_MAC_PERFECT_MATCH || 7451 filter_type == RTE_MAC_HASH_MATCH) 7452 vlan_num = 1; 7453 7454 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0); 7455 if (mv_f == NULL) { 7456 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7457 return I40E_ERR_NO_MEMORY; 7458 } 7459 7460 for (i = 0; i < vlan_num; i++) { 7461 mv_f[i].filter_type = filter_type; 7462 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr, 7463 ETH_ADDR_LEN); 7464 } 7465 if (filter_type == RTE_MACVLAN_PERFECT_MATCH || 7466 filter_type == RTE_MACVLAN_HASH_MATCH) { 7467 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr); 7468 if (ret != I40E_SUCCESS) 7469 goto DONE; 7470 } 7471 7472 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num); 7473 if (ret != I40E_SUCCESS) 7474 goto DONE; 7475 7476 /* Remove the mac addr into mac list */ 7477 TAILQ_REMOVE(&vsi->mac_list, f, next); 7478 rte_free(f); 7479 vsi->mac_num--; 7480 7481 ret = I40E_SUCCESS; 7482 DONE: 7483 rte_free(mv_f); 7484 return ret; 7485 } 7486 7487 /* Configure hash enable flags for RSS */ 7488 uint64_t 7489 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags) 7490 { 7491 uint64_t hena = 0; 7492 int i; 7493 7494 if (!flags) 7495 return hena; 7496 7497 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) { 7498 if (flags & (1ULL << i)) 7499 hena |= adapter->pctypes_tbl[i]; 7500 } 7501 7502 return hena; 7503 } 7504 7505 /* Parse the hash enable flags */ 7506 uint64_t 7507 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags) 7508 { 7509 uint64_t rss_hf = 0; 7510 7511 if (!flags) 7512 return rss_hf; 7513 int i; 7514 7515 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) { 7516 if (flags & adapter->pctypes_tbl[i]) 7517 rss_hf |= (1ULL << i); 7518 } 7519 return rss_hf; 7520 } 7521 7522 /* Disable RSS */ 7523 static void 7524 i40e_pf_disable_rss(struct i40e_pf *pf) 7525 { 7526 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7527 7528 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); 7529 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); 7530 I40E_WRITE_FLUSH(hw); 7531 } 7532 7533 int 7534 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len) 7535 { 7536 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 7537 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7538 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ? 7539 I40E_VFQF_HKEY_MAX_INDEX : 7540 I40E_PFQF_HKEY_MAX_INDEX; 7541 int ret = 0; 7542 7543 if (!key || key_len == 0) { 7544 PMD_DRV_LOG(DEBUG, "No key to be configured"); 7545 return 0; 7546 } else if (key_len != (key_idx + 1) * 7547 sizeof(uint32_t)) { 7548 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 7549 return -EINVAL; 7550 } 7551 7552 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 7553 struct i40e_aqc_get_set_rss_key_data *key_dw = 7554 (struct i40e_aqc_get_set_rss_key_data *)key; 7555 7556 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw); 7557 if (ret) 7558 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ"); 7559 } else { 7560 uint32_t *hash_key = (uint32_t *)key; 7561 uint16_t i; 7562 7563 if (vsi->type == I40E_VSI_SRIOV) { 7564 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) 7565 I40E_WRITE_REG( 7566 hw, 7567 I40E_VFQF_HKEY1(i, vsi->user_param), 7568 hash_key[i]); 7569 7570 } else { 7571 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) 7572 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), 7573 hash_key[i]); 7574 } 7575 I40E_WRITE_FLUSH(hw); 7576 } 7577 7578 return ret; 7579 } 7580 7581 static int 7582 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len) 7583 { 7584 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 7585 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7586 uint32_t reg; 7587 int ret; 7588 7589 if (!key || !key_len) 7590 return 0; 7591 7592 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 7593 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id, 7594 (struct i40e_aqc_get_set_rss_key_data *)key); 7595 if (ret) { 7596 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ"); 7597 return ret; 7598 } 7599 } else { 7600 uint32_t *key_dw = (uint32_t *)key; 7601 uint16_t i; 7602 7603 if (vsi->type == I40E_VSI_SRIOV) { 7604 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) { 7605 reg = I40E_VFQF_HKEY1(i, vsi->user_param); 7606 key_dw[i] = i40e_read_rx_ctl(hw, reg); 7607 } 7608 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * 7609 sizeof(uint32_t); 7610 } else { 7611 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) { 7612 reg = I40E_PFQF_HKEY(i); 7613 key_dw[i] = i40e_read_rx_ctl(hw, reg); 7614 } 7615 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 7616 sizeof(uint32_t); 7617 } 7618 } 7619 return 0; 7620 } 7621 7622 static int 7623 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf) 7624 { 7625 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7626 uint64_t hena; 7627 int ret; 7628 7629 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key, 7630 rss_conf->rss_key_len); 7631 if (ret) 7632 return ret; 7633 7634 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf); 7635 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); 7636 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); 7637 I40E_WRITE_FLUSH(hw); 7638 7639 return 0; 7640 } 7641 7642 static int 7643 i40e_dev_rss_hash_update(struct rte_eth_dev *dev, 7644 struct rte_eth_rss_conf *rss_conf) 7645 { 7646 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7648 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask; 7649 uint64_t hena; 7650 7651 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); 7652 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; 7653 7654 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */ 7655 if (rss_hf != 0) /* Enable RSS */ 7656 return -EINVAL; 7657 return 0; /* Nothing to do */ 7658 } 7659 /* RSS enabled */ 7660 if (rss_hf == 0) /* Disable RSS */ 7661 return -EINVAL; 7662 7663 return i40e_hw_rss_hash_set(pf, rss_conf); 7664 } 7665 7666 static int 7667 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 7668 struct rte_eth_rss_conf *rss_conf) 7669 { 7670 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7671 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7672 uint64_t hena; 7673 int ret; 7674 7675 if (!rss_conf) 7676 return -EINVAL; 7677 7678 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key, 7679 &rss_conf->rss_key_len); 7680 if (ret) 7681 return ret; 7682 7683 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); 7684 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; 7685 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena); 7686 7687 return 0; 7688 } 7689 7690 static int 7691 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag) 7692 { 7693 switch (filter_type) { 7694 case RTE_TUNNEL_FILTER_IMAC_IVLAN: 7695 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN; 7696 break; 7697 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID: 7698 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID; 7699 break; 7700 case RTE_TUNNEL_FILTER_IMAC_TENID: 7701 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID; 7702 break; 7703 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC: 7704 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC; 7705 break; 7706 case ETH_TUNNEL_FILTER_IMAC: 7707 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC; 7708 break; 7709 case ETH_TUNNEL_FILTER_OIP: 7710 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP; 7711 break; 7712 case ETH_TUNNEL_FILTER_IIP: 7713 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP; 7714 break; 7715 default: 7716 PMD_DRV_LOG(ERR, "invalid tunnel filter type"); 7717 return -EINVAL; 7718 } 7719 7720 return 0; 7721 } 7722 7723 /* Convert tunnel filter structure */ 7724 static int 7725 i40e_tunnel_filter_convert( 7726 struct i40e_aqc_cloud_filters_element_bb *cld_filter, 7727 struct i40e_tunnel_filter *tunnel_filter) 7728 { 7729 rte_ether_addr_copy((struct rte_ether_addr *) 7730 &cld_filter->element.outer_mac, 7731 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac); 7732 rte_ether_addr_copy((struct rte_ether_addr *) 7733 &cld_filter->element.inner_mac, 7734 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac); 7735 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan; 7736 if ((rte_le_to_cpu_16(cld_filter->element.flags) & 7737 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) == 7738 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) 7739 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6; 7740 else 7741 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4; 7742 tunnel_filter->input.flags = cld_filter->element.flags; 7743 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id; 7744 tunnel_filter->queue = cld_filter->element.queue_number; 7745 rte_memcpy(tunnel_filter->input.general_fields, 7746 cld_filter->general_fields, 7747 sizeof(cld_filter->general_fields)); 7748 7749 return 0; 7750 } 7751 7752 /* Check if there exists the tunnel filter */ 7753 struct i40e_tunnel_filter * 7754 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 7755 const struct i40e_tunnel_filter_input *input) 7756 { 7757 int ret; 7758 7759 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input); 7760 if (ret < 0) 7761 return NULL; 7762 7763 return tunnel_rule->hash_map[ret]; 7764 } 7765 7766 /* Add a tunnel filter into the SW list */ 7767 static int 7768 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, 7769 struct i40e_tunnel_filter *tunnel_filter) 7770 { 7771 struct i40e_tunnel_rule *rule = &pf->tunnel; 7772 int ret; 7773 7774 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input); 7775 if (ret < 0) { 7776 PMD_DRV_LOG(ERR, 7777 "Failed to insert tunnel filter to hash table %d!", 7778 ret); 7779 return ret; 7780 } 7781 rule->hash_map[ret] = tunnel_filter; 7782 7783 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules); 7784 7785 return 0; 7786 } 7787 7788 /* Delete a tunnel filter from the SW list */ 7789 int 7790 i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 7791 struct i40e_tunnel_filter_input *input) 7792 { 7793 struct i40e_tunnel_rule *rule = &pf->tunnel; 7794 struct i40e_tunnel_filter *tunnel_filter; 7795 int ret; 7796 7797 ret = rte_hash_del_key(rule->hash_table, input); 7798 if (ret < 0) { 7799 PMD_DRV_LOG(ERR, 7800 "Failed to delete tunnel filter to hash table %d!", 7801 ret); 7802 return ret; 7803 } 7804 tunnel_filter = rule->hash_map[ret]; 7805 rule->hash_map[ret] = NULL; 7806 7807 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules); 7808 rte_free(tunnel_filter); 7809 7810 return 0; 7811 } 7812 7813 int 7814 i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 7815 struct rte_eth_tunnel_filter_conf *tunnel_filter, 7816 uint8_t add) 7817 { 7818 uint16_t ip_type; 7819 uint32_t ipv4_addr, ipv4_addr_le; 7820 uint8_t i, tun_type = 0; 7821 /* internal varialbe to convert ipv6 byte order */ 7822 uint32_t convert_ipv6[4]; 7823 int val, ret = 0; 7824 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7825 struct i40e_vsi *vsi = pf->main_vsi; 7826 struct i40e_aqc_cloud_filters_element_bb *cld_filter; 7827 struct i40e_aqc_cloud_filters_element_bb *pfilter; 7828 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 7829 struct i40e_tunnel_filter *tunnel, *node; 7830 struct i40e_tunnel_filter check_filter; /* Check if filter exists */ 7831 7832 cld_filter = rte_zmalloc("tunnel_filter", 7833 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), 7834 0); 7835 7836 if (NULL == cld_filter) { 7837 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 7838 return -ENOMEM; 7839 } 7840 pfilter = cld_filter; 7841 7842 rte_ether_addr_copy(&tunnel_filter->outer_mac, 7843 (struct rte_ether_addr *)&pfilter->element.outer_mac); 7844 rte_ether_addr_copy(&tunnel_filter->inner_mac, 7845 (struct rte_ether_addr *)&pfilter->element.inner_mac); 7846 7847 pfilter->element.inner_vlan = 7848 rte_cpu_to_le_16(tunnel_filter->inner_vlan); 7849 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) { 7850 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4; 7851 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr); 7852 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr); 7853 rte_memcpy(&pfilter->element.ipaddr.v4.data, 7854 &ipv4_addr_le, 7855 sizeof(pfilter->element.ipaddr.v4.data)); 7856 } else { 7857 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6; 7858 for (i = 0; i < 4; i++) { 7859 convert_ipv6[i] = 7860 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i])); 7861 } 7862 rte_memcpy(&pfilter->element.ipaddr.v6.data, 7863 &convert_ipv6, 7864 sizeof(pfilter->element.ipaddr.v6.data)); 7865 } 7866 7867 /* check tunneled type */ 7868 switch (tunnel_filter->tunnel_type) { 7869 case RTE_TUNNEL_TYPE_VXLAN: 7870 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN; 7871 break; 7872 case RTE_TUNNEL_TYPE_NVGRE: 7873 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC; 7874 break; 7875 case RTE_TUNNEL_TYPE_IP_IN_GRE: 7876 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; 7877 break; 7878 case RTE_TUNNEL_TYPE_VXLAN_GPE: 7879 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE; 7880 break; 7881 default: 7882 /* Other tunnel types is not supported. */ 7883 PMD_DRV_LOG(ERR, "tunnel type is not supported."); 7884 rte_free(cld_filter); 7885 return -EINVAL; 7886 } 7887 7888 val = i40e_dev_get_filter_type(tunnel_filter->filter_type, 7889 &pfilter->element.flags); 7890 if (val < 0) { 7891 rte_free(cld_filter); 7892 return -EINVAL; 7893 } 7894 7895 pfilter->element.flags |= rte_cpu_to_le_16( 7896 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | 7897 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)); 7898 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id); 7899 pfilter->element.queue_number = 7900 rte_cpu_to_le_16(tunnel_filter->queue_id); 7901 7902 /* Check if there is the filter in SW list */ 7903 memset(&check_filter, 0, sizeof(check_filter)); 7904 i40e_tunnel_filter_convert(cld_filter, &check_filter); 7905 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input); 7906 if (add && node) { 7907 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!"); 7908 rte_free(cld_filter); 7909 return -EINVAL; 7910 } 7911 7912 if (!add && !node) { 7913 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!"); 7914 rte_free(cld_filter); 7915 return -EINVAL; 7916 } 7917 7918 if (add) { 7919 ret = i40e_aq_add_cloud_filters(hw, 7920 vsi->seid, &cld_filter->element, 1); 7921 if (ret < 0) { 7922 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter."); 7923 rte_free(cld_filter); 7924 return -ENOTSUP; 7925 } 7926 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0); 7927 if (tunnel == NULL) { 7928 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 7929 rte_free(cld_filter); 7930 return -ENOMEM; 7931 } 7932 7933 rte_memcpy(tunnel, &check_filter, sizeof(check_filter)); 7934 ret = i40e_sw_tunnel_filter_insert(pf, tunnel); 7935 if (ret < 0) 7936 rte_free(tunnel); 7937 } else { 7938 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 7939 &cld_filter->element, 1); 7940 if (ret < 0) { 7941 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter."); 7942 rte_free(cld_filter); 7943 return -ENOTSUP; 7944 } 7945 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 7946 } 7947 7948 rte_free(cld_filter); 7949 return ret; 7950 } 7951 7952 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48 7953 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4 7954 #define I40E_TR_GENEVE_KEY_MASK 0x8 7955 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40 7956 #define I40E_TR_GRE_KEY_MASK 0x400 7957 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800 7958 #define I40E_TR_GRE_NO_KEY_MASK 0x8000 7959 7960 static enum 7961 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf) 7962 { 7963 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7964 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7965 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7966 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7967 enum i40e_status_code status = I40E_SUCCESS; 7968 7969 if (pf->support_multi_driver) { 7970 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported."); 7971 return I40E_NOT_SUPPORTED; 7972 } 7973 7974 memset(&filter_replace, 0, 7975 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7976 memset(&filter_replace_buf, 0, 7977 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7978 7979 /* create L1 filter */ 7980 filter_replace.old_filter_type = 7981 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; 7982 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11; 7983 filter_replace.tr_bit = 0; 7984 7985 /* Prepare the buffer, 3 entries */ 7986 filter_replace_buf.data[0] = 7987 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 7988 filter_replace_buf.data[0] |= 7989 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7990 filter_replace_buf.data[2] = 0xFF; 7991 filter_replace_buf.data[3] = 0xFF; 7992 filter_replace_buf.data[4] = 7993 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 7994 filter_replace_buf.data[4] |= 7995 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7996 filter_replace_buf.data[7] = 0xF0; 7997 filter_replace_buf.data[8] 7998 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0; 7999 filter_replace_buf.data[8] |= 8000 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8001 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK | 8002 I40E_TR_GENEVE_KEY_MASK | 8003 I40E_TR_GENERIC_UDP_TUNNEL_MASK; 8004 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK | 8005 I40E_TR_GRE_KEY_WITH_XSUM_MASK | 8006 I40E_TR_GRE_NO_KEY_MASK) >> 8; 8007 8008 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8009 &filter_replace_buf); 8010 if (!status && (filter_replace.old_filter_type != 8011 filter_replace.new_filter_type)) 8012 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 8013 " original: 0x%x, new: 0x%x", 8014 dev->device->name, 8015 filter_replace.old_filter_type, 8016 filter_replace.new_filter_type); 8017 8018 return status; 8019 } 8020 8021 static enum 8022 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) 8023 { 8024 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 8025 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 8026 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8027 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 8028 enum i40e_status_code status = I40E_SUCCESS; 8029 8030 if (pf->support_multi_driver) { 8031 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 8032 return I40E_NOT_SUPPORTED; 8033 } 8034 8035 /* For MPLSoUDP */ 8036 memset(&filter_replace, 0, 8037 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8038 memset(&filter_replace_buf, 0, 8039 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8040 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | 8041 I40E_AQC_MIRROR_CLOUD_FILTER; 8042 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP; 8043 filter_replace.new_filter_type = 8044 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8045 /* Prepare the buffer, 2 entries */ 8046 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8047 filter_replace_buf.data[0] |= 8048 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8049 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11; 8050 filter_replace_buf.data[4] |= 8051 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8052 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8053 &filter_replace_buf); 8054 if (status < 0) 8055 return status; 8056 if (filter_replace.old_filter_type != 8057 filter_replace.new_filter_type) 8058 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8059 " original: 0x%x, new: 0x%x", 8060 dev->device->name, 8061 filter_replace.old_filter_type, 8062 filter_replace.new_filter_type); 8063 8064 /* For MPLSoGRE */ 8065 memset(&filter_replace, 0, 8066 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8067 memset(&filter_replace_buf, 0, 8068 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8069 8070 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | 8071 I40E_AQC_MIRROR_CLOUD_FILTER; 8072 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC; 8073 filter_replace.new_filter_type = 8074 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8075 /* Prepare the buffer, 2 entries */ 8076 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8077 filter_replace_buf.data[0] |= 8078 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8079 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11; 8080 filter_replace_buf.data[4] |= 8081 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8082 8083 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8084 &filter_replace_buf); 8085 if (!status && (filter_replace.old_filter_type != 8086 filter_replace.new_filter_type)) 8087 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8088 " original: 0x%x, new: 0x%x", 8089 dev->device->name, 8090 filter_replace.old_filter_type, 8091 filter_replace.new_filter_type); 8092 8093 return status; 8094 } 8095 8096 static enum i40e_status_code 8097 i40e_replace_gtp_l1_filter(struct i40e_pf *pf) 8098 { 8099 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 8100 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 8101 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8102 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 8103 enum i40e_status_code status = I40E_SUCCESS; 8104 8105 if (pf->support_multi_driver) { 8106 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported."); 8107 return I40E_NOT_SUPPORTED; 8108 } 8109 8110 /* For GTP-C */ 8111 memset(&filter_replace, 0, 8112 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8113 memset(&filter_replace_buf, 0, 8114 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8115 /* create L1 filter */ 8116 filter_replace.old_filter_type = 8117 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; 8118 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12; 8119 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 | 8120 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8121 /* Prepare the buffer, 2 entries */ 8122 filter_replace_buf.data[0] = 8123 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 8124 filter_replace_buf.data[0] |= 8125 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8126 filter_replace_buf.data[2] = 0xFF; 8127 filter_replace_buf.data[3] = 0xFF; 8128 filter_replace_buf.data[4] = 8129 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 8130 filter_replace_buf.data[4] |= 8131 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8132 filter_replace_buf.data[6] = 0xFF; 8133 filter_replace_buf.data[7] = 0xFF; 8134 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8135 &filter_replace_buf); 8136 if (status < 0) 8137 return status; 8138 if (filter_replace.old_filter_type != 8139 filter_replace.new_filter_type) 8140 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 8141 " original: 0x%x, new: 0x%x", 8142 dev->device->name, 8143 filter_replace.old_filter_type, 8144 filter_replace.new_filter_type); 8145 8146 /* for GTP-U */ 8147 memset(&filter_replace, 0, 8148 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8149 memset(&filter_replace_buf, 0, 8150 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8151 /* create L1 filter */ 8152 filter_replace.old_filter_type = 8153 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY; 8154 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13; 8155 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 | 8156 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8157 /* Prepare the buffer, 2 entries */ 8158 filter_replace_buf.data[0] = 8159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 8160 filter_replace_buf.data[0] |= 8161 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8162 filter_replace_buf.data[2] = 0xFF; 8163 filter_replace_buf.data[3] = 0xFF; 8164 filter_replace_buf.data[4] = 8165 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 8166 filter_replace_buf.data[4] |= 8167 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8168 filter_replace_buf.data[6] = 0xFF; 8169 filter_replace_buf.data[7] = 0xFF; 8170 8171 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8172 &filter_replace_buf); 8173 if (!status && (filter_replace.old_filter_type != 8174 filter_replace.new_filter_type)) 8175 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 8176 " original: 0x%x, new: 0x%x", 8177 dev->device->name, 8178 filter_replace.old_filter_type, 8179 filter_replace.new_filter_type); 8180 8181 return status; 8182 } 8183 8184 static enum 8185 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf) 8186 { 8187 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 8188 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 8189 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8190 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 8191 enum i40e_status_code status = I40E_SUCCESS; 8192 8193 if (pf->support_multi_driver) { 8194 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 8195 return I40E_NOT_SUPPORTED; 8196 } 8197 8198 /* for GTP-C */ 8199 memset(&filter_replace, 0, 8200 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8201 memset(&filter_replace_buf, 0, 8202 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8203 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 8204 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN; 8205 filter_replace.new_filter_type = 8206 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8207 /* Prepare the buffer, 2 entries */ 8208 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12; 8209 filter_replace_buf.data[0] |= 8210 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8211 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8212 filter_replace_buf.data[4] |= 8213 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8214 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8215 &filter_replace_buf); 8216 if (status < 0) 8217 return status; 8218 if (filter_replace.old_filter_type != 8219 filter_replace.new_filter_type) 8220 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8221 " original: 0x%x, new: 0x%x", 8222 dev->device->name, 8223 filter_replace.old_filter_type, 8224 filter_replace.new_filter_type); 8225 8226 /* for GTP-U */ 8227 memset(&filter_replace, 0, 8228 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8229 memset(&filter_replace_buf, 0, 8230 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8231 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 8232 filter_replace.old_filter_type = 8233 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID; 8234 filter_replace.new_filter_type = 8235 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8236 /* Prepare the buffer, 2 entries */ 8237 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13; 8238 filter_replace_buf.data[0] |= 8239 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8240 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8241 filter_replace_buf.data[4] |= 8242 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8243 8244 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8245 &filter_replace_buf); 8246 if (!status && (filter_replace.old_filter_type != 8247 filter_replace.new_filter_type)) 8248 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8249 " original: 0x%x, new: 0x%x", 8250 dev->device->name, 8251 filter_replace.old_filter_type, 8252 filter_replace.new_filter_type); 8253 8254 return status; 8255 } 8256 8257 int 8258 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 8259 struct i40e_tunnel_filter_conf *tunnel_filter, 8260 uint8_t add) 8261 { 8262 uint16_t ip_type; 8263 uint32_t ipv4_addr, ipv4_addr_le; 8264 uint8_t i, tun_type = 0; 8265 /* internal variable to convert ipv6 byte order */ 8266 uint32_t convert_ipv6[4]; 8267 int val, ret = 0; 8268 struct i40e_pf_vf *vf = NULL; 8269 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8270 struct i40e_vsi *vsi; 8271 struct i40e_aqc_cloud_filters_element_bb *cld_filter; 8272 struct i40e_aqc_cloud_filters_element_bb *pfilter; 8273 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 8274 struct i40e_tunnel_filter *tunnel, *node; 8275 struct i40e_tunnel_filter check_filter; /* Check if filter exists */ 8276 uint32_t teid_le; 8277 bool big_buffer = 0; 8278 8279 cld_filter = rte_zmalloc("tunnel_filter", 8280 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), 8281 0); 8282 8283 if (cld_filter == NULL) { 8284 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 8285 return -ENOMEM; 8286 } 8287 pfilter = cld_filter; 8288 8289 rte_ether_addr_copy(&tunnel_filter->outer_mac, 8290 (struct rte_ether_addr *)&pfilter->element.outer_mac); 8291 rte_ether_addr_copy(&tunnel_filter->inner_mac, 8292 (struct rte_ether_addr *)&pfilter->element.inner_mac); 8293 8294 pfilter->element.inner_vlan = 8295 rte_cpu_to_le_16(tunnel_filter->inner_vlan); 8296 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) { 8297 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4; 8298 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr); 8299 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr); 8300 rte_memcpy(&pfilter->element.ipaddr.v4.data, 8301 &ipv4_addr_le, 8302 sizeof(pfilter->element.ipaddr.v4.data)); 8303 } else { 8304 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6; 8305 for (i = 0; i < 4; i++) { 8306 convert_ipv6[i] = 8307 rte_cpu_to_le_32(rte_be_to_cpu_32( 8308 tunnel_filter->ip_addr.ipv6_addr[i])); 8309 } 8310 rte_memcpy(&pfilter->element.ipaddr.v6.data, 8311 &convert_ipv6, 8312 sizeof(pfilter->element.ipaddr.v6.data)); 8313 } 8314 8315 /* check tunneled type */ 8316 switch (tunnel_filter->tunnel_type) { 8317 case I40E_TUNNEL_TYPE_VXLAN: 8318 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN; 8319 break; 8320 case I40E_TUNNEL_TYPE_NVGRE: 8321 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC; 8322 break; 8323 case I40E_TUNNEL_TYPE_IP_IN_GRE: 8324 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; 8325 break; 8326 case I40E_TUNNEL_TYPE_MPLSoUDP: 8327 if (!pf->mpls_replace_flag) { 8328 i40e_replace_mpls_l1_filter(pf); 8329 i40e_replace_mpls_cloud_filter(pf); 8330 pf->mpls_replace_flag = 1; 8331 } 8332 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8333 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = 8334 teid_le >> 4; 8335 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = 8336 (teid_le & 0xF) << 12; 8337 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = 8338 0x40; 8339 big_buffer = 1; 8340 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP; 8341 break; 8342 case I40E_TUNNEL_TYPE_MPLSoGRE: 8343 if (!pf->mpls_replace_flag) { 8344 i40e_replace_mpls_l1_filter(pf); 8345 i40e_replace_mpls_cloud_filter(pf); 8346 pf->mpls_replace_flag = 1; 8347 } 8348 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8349 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = 8350 teid_le >> 4; 8351 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = 8352 (teid_le & 0xF) << 12; 8353 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = 8354 0x0; 8355 big_buffer = 1; 8356 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE; 8357 break; 8358 case I40E_TUNNEL_TYPE_GTPC: 8359 if (!pf->gtp_replace_flag) { 8360 i40e_replace_gtp_l1_filter(pf); 8361 i40e_replace_gtp_cloud_filter(pf); 8362 pf->gtp_replace_flag = 1; 8363 } 8364 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8365 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] = 8366 (teid_le >> 16) & 0xFFFF; 8367 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] = 8368 teid_le & 0xFFFF; 8369 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] = 8370 0x0; 8371 big_buffer = 1; 8372 break; 8373 case I40E_TUNNEL_TYPE_GTPU: 8374 if (!pf->gtp_replace_flag) { 8375 i40e_replace_gtp_l1_filter(pf); 8376 i40e_replace_gtp_cloud_filter(pf); 8377 pf->gtp_replace_flag = 1; 8378 } 8379 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8380 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] = 8381 (teid_le >> 16) & 0xFFFF; 8382 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] = 8383 teid_le & 0xFFFF; 8384 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] = 8385 0x0; 8386 big_buffer = 1; 8387 break; 8388 case I40E_TUNNEL_TYPE_QINQ: 8389 if (!pf->qinq_replace_flag) { 8390 ret = i40e_cloud_filter_qinq_create(pf); 8391 if (ret < 0) 8392 PMD_DRV_LOG(DEBUG, 8393 "QinQ tunnel filter already created."); 8394 pf->qinq_replace_flag = 1; 8395 } 8396 /* Add in the General fields the values of 8397 * the Outer and Inner VLAN 8398 * Big Buffer should be set, see changes in 8399 * i40e_aq_add_cloud_filters 8400 */ 8401 pfilter->general_fields[0] = tunnel_filter->inner_vlan; 8402 pfilter->general_fields[1] = tunnel_filter->outer_vlan; 8403 big_buffer = 1; 8404 break; 8405 default: 8406 /* Other tunnel types is not supported. */ 8407 PMD_DRV_LOG(ERR, "tunnel type is not supported."); 8408 rte_free(cld_filter); 8409 return -EINVAL; 8410 } 8411 8412 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP) 8413 pfilter->element.flags = 8414 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8415 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE) 8416 pfilter->element.flags = 8417 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8418 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC) 8419 pfilter->element.flags = 8420 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8421 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU) 8422 pfilter->element.flags = 8423 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8424 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ) 8425 pfilter->element.flags |= 8426 I40E_AQC_ADD_CLOUD_FILTER_0X10; 8427 else { 8428 val = i40e_dev_get_filter_type(tunnel_filter->filter_type, 8429 &pfilter->element.flags); 8430 if (val < 0) { 8431 rte_free(cld_filter); 8432 return -EINVAL; 8433 } 8434 } 8435 8436 pfilter->element.flags |= rte_cpu_to_le_16( 8437 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | 8438 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)); 8439 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8440 pfilter->element.queue_number = 8441 rte_cpu_to_le_16(tunnel_filter->queue_id); 8442 8443 if (!tunnel_filter->is_to_vf) 8444 vsi = pf->main_vsi; 8445 else { 8446 if (tunnel_filter->vf_id >= pf->vf_num) { 8447 PMD_DRV_LOG(ERR, "Invalid argument."); 8448 rte_free(cld_filter); 8449 return -EINVAL; 8450 } 8451 vf = &pf->vfs[tunnel_filter->vf_id]; 8452 vsi = vf->vsi; 8453 } 8454 8455 /* Check if there is the filter in SW list */ 8456 memset(&check_filter, 0, sizeof(check_filter)); 8457 i40e_tunnel_filter_convert(cld_filter, &check_filter); 8458 check_filter.is_to_vf = tunnel_filter->is_to_vf; 8459 check_filter.vf_id = tunnel_filter->vf_id; 8460 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input); 8461 if (add && node) { 8462 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!"); 8463 rte_free(cld_filter); 8464 return -EINVAL; 8465 } 8466 8467 if (!add && !node) { 8468 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!"); 8469 rte_free(cld_filter); 8470 return -EINVAL; 8471 } 8472 8473 if (add) { 8474 if (big_buffer) 8475 ret = i40e_aq_add_cloud_filters_bb(hw, 8476 vsi->seid, cld_filter, 1); 8477 else 8478 ret = i40e_aq_add_cloud_filters(hw, 8479 vsi->seid, &cld_filter->element, 1); 8480 if (ret < 0) { 8481 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter."); 8482 rte_free(cld_filter); 8483 return -ENOTSUP; 8484 } 8485 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0); 8486 if (tunnel == NULL) { 8487 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 8488 rte_free(cld_filter); 8489 return -ENOMEM; 8490 } 8491 8492 rte_memcpy(tunnel, &check_filter, sizeof(check_filter)); 8493 ret = i40e_sw_tunnel_filter_insert(pf, tunnel); 8494 if (ret < 0) 8495 rte_free(tunnel); 8496 } else { 8497 if (big_buffer) 8498 ret = i40e_aq_rem_cloud_filters_bb( 8499 hw, vsi->seid, cld_filter, 1); 8500 else 8501 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 8502 &cld_filter->element, 1); 8503 if (ret < 0) { 8504 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter."); 8505 rte_free(cld_filter); 8506 return -ENOTSUP; 8507 } 8508 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 8509 } 8510 8511 rte_free(cld_filter); 8512 return ret; 8513 } 8514 8515 static int 8516 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port) 8517 { 8518 uint8_t i; 8519 8520 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { 8521 if (pf->vxlan_ports[i] == port) 8522 return i; 8523 } 8524 8525 return -1; 8526 } 8527 8528 static int 8529 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type) 8530 { 8531 int idx, ret; 8532 uint8_t filter_idx = 0; 8533 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8534 8535 idx = i40e_get_vxlan_port_idx(pf, port); 8536 8537 /* Check if port already exists */ 8538 if (idx >= 0) { 8539 PMD_DRV_LOG(ERR, "Port %d already offloaded", port); 8540 return -EINVAL; 8541 } 8542 8543 /* Now check if there is space to add the new port */ 8544 idx = i40e_get_vxlan_port_idx(pf, 0); 8545 if (idx < 0) { 8546 PMD_DRV_LOG(ERR, 8547 "Maximum number of UDP ports reached, not adding port %d", 8548 port); 8549 return -ENOSPC; 8550 } 8551 8552 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type, 8553 &filter_idx, NULL); 8554 if (ret < 0) { 8555 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port); 8556 return -1; 8557 } 8558 8559 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d", 8560 port, filter_idx); 8561 8562 /* New port: add it and mark its index in the bitmap */ 8563 pf->vxlan_ports[idx] = port; 8564 pf->vxlan_bitmap |= (1 << idx); 8565 8566 if (!(pf->flags & I40E_FLAG_VXLAN)) 8567 pf->flags |= I40E_FLAG_VXLAN; 8568 8569 return 0; 8570 } 8571 8572 static int 8573 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port) 8574 { 8575 int idx; 8576 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8577 8578 if (!(pf->flags & I40E_FLAG_VXLAN)) { 8579 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured."); 8580 return -EINVAL; 8581 } 8582 8583 idx = i40e_get_vxlan_port_idx(pf, port); 8584 8585 if (idx < 0) { 8586 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port); 8587 return -EINVAL; 8588 } 8589 8590 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) { 8591 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port); 8592 return -1; 8593 } 8594 8595 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d", 8596 port, idx); 8597 8598 pf->vxlan_ports[idx] = 0; 8599 pf->vxlan_bitmap &= ~(1 << idx); 8600 8601 if (!pf->vxlan_bitmap) 8602 pf->flags &= ~I40E_FLAG_VXLAN; 8603 8604 return 0; 8605 } 8606 8607 /* Add UDP tunneling port */ 8608 static int 8609 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8610 struct rte_eth_udp_tunnel *udp_tunnel) 8611 { 8612 int ret = 0; 8613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8614 8615 if (udp_tunnel == NULL) 8616 return -EINVAL; 8617 8618 switch (udp_tunnel->prot_type) { 8619 case RTE_TUNNEL_TYPE_VXLAN: 8620 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port, 8621 I40E_AQC_TUNNEL_TYPE_VXLAN); 8622 break; 8623 case RTE_TUNNEL_TYPE_VXLAN_GPE: 8624 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port, 8625 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE); 8626 break; 8627 case RTE_TUNNEL_TYPE_GENEVE: 8628 case RTE_TUNNEL_TYPE_TEREDO: 8629 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8630 ret = -1; 8631 break; 8632 8633 default: 8634 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8635 ret = -1; 8636 break; 8637 } 8638 8639 return ret; 8640 } 8641 8642 /* Remove UDP tunneling port */ 8643 static int 8644 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8645 struct rte_eth_udp_tunnel *udp_tunnel) 8646 { 8647 int ret = 0; 8648 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8649 8650 if (udp_tunnel == NULL) 8651 return -EINVAL; 8652 8653 switch (udp_tunnel->prot_type) { 8654 case RTE_TUNNEL_TYPE_VXLAN: 8655 case RTE_TUNNEL_TYPE_VXLAN_GPE: 8656 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port); 8657 break; 8658 case RTE_TUNNEL_TYPE_GENEVE: 8659 case RTE_TUNNEL_TYPE_TEREDO: 8660 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8661 ret = -1; 8662 break; 8663 default: 8664 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8665 ret = -1; 8666 break; 8667 } 8668 8669 return ret; 8670 } 8671 8672 /* Calculate the maximum number of contiguous PF queues that are configured */ 8673 static int 8674 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf) 8675 { 8676 struct rte_eth_dev_data *data = pf->dev_data; 8677 int i, num; 8678 struct i40e_rx_queue *rxq; 8679 8680 num = 0; 8681 for (i = 0; i < pf->lan_nb_qps; i++) { 8682 rxq = data->rx_queues[i]; 8683 if (rxq && rxq->q_set) 8684 num++; 8685 else 8686 break; 8687 } 8688 8689 return num; 8690 } 8691 8692 /* Configure RSS */ 8693 static int 8694 i40e_pf_config_rss(struct i40e_pf *pf) 8695 { 8696 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8697 struct rte_eth_rss_conf rss_conf; 8698 uint32_t i, lut = 0; 8699 uint16_t j, num; 8700 8701 /* 8702 * If both VMDQ and RSS enabled, not all of PF queues are configured. 8703 * It's necessary to calculate the actual PF queues that are configured. 8704 */ 8705 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 8706 num = i40e_pf_calc_configured_queues_num(pf); 8707 else 8708 num = pf->dev_data->nb_rx_queues; 8709 8710 num = RTE_MIN(num, I40E_MAX_Q_PER_TC); 8711 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured", 8712 num); 8713 8714 if (num == 0) { 8715 PMD_INIT_LOG(ERR, 8716 "No PF queues are configured to enable RSS for port %u", 8717 pf->dev_data->port_id); 8718 return -ENOTSUP; 8719 } 8720 8721 if (pf->adapter->rss_reta_updated == 0) { 8722 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 8723 if (j == num) 8724 j = 0; 8725 lut = (lut << 8) | (j & ((0x1 << 8726 hw->func_caps.rss_table_entry_width) - 1)); 8727 if ((i & 3) == 3) 8728 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), 8729 rte_bswap32(lut)); 8730 } 8731 } 8732 8733 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf; 8734 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) { 8735 i40e_pf_disable_rss(pf); 8736 return 0; 8737 } 8738 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < 8739 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 8740 /* Random default keys */ 8741 static uint32_t rss_key_default[] = {0x6b793944, 8742 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8, 8743 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605, 8744 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581}; 8745 8746 rss_conf.rss_key = (uint8_t *)rss_key_default; 8747 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 8748 sizeof(uint32_t); 8749 } 8750 8751 return i40e_hw_rss_hash_set(pf, &rss_conf); 8752 } 8753 8754 static int 8755 i40e_tunnel_filter_param_check(struct i40e_pf *pf, 8756 struct rte_eth_tunnel_filter_conf *filter) 8757 { 8758 if (pf == NULL || filter == NULL) { 8759 PMD_DRV_LOG(ERR, "Invalid parameter"); 8760 return -EINVAL; 8761 } 8762 8763 if (filter->queue_id >= pf->dev_data->nb_rx_queues) { 8764 PMD_DRV_LOG(ERR, "Invalid queue ID"); 8765 return -EINVAL; 8766 } 8767 8768 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) { 8769 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID"); 8770 return -EINVAL; 8771 } 8772 8773 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) && 8774 (rte_is_zero_ether_addr(&filter->outer_mac))) { 8775 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address"); 8776 return -EINVAL; 8777 } 8778 8779 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) && 8780 (rte_is_zero_ether_addr(&filter->inner_mac))) { 8781 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address"); 8782 return -EINVAL; 8783 } 8784 8785 return 0; 8786 } 8787 8788 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000 8789 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) 8790 static int 8791 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) 8792 { 8793 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 8794 uint32_t val, reg; 8795 int ret = -EINVAL; 8796 8797 if (pf->support_multi_driver) { 8798 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported"); 8799 return -ENOTSUP; 8800 } 8801 8802 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)); 8803 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val); 8804 8805 if (len == 3) { 8806 reg = val | I40E_GL_PRS_FVBM_MSK_ENA; 8807 } else if (len == 4) { 8808 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA; 8809 } else { 8810 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len); 8811 return ret; 8812 } 8813 8814 if (reg != val) { 8815 ret = i40e_aq_debug_write_global_register(hw, 8816 I40E_GL_PRS_FVBM(2), 8817 reg, NULL); 8818 if (ret != 0) 8819 return ret; 8820 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed " 8821 "with value 0x%08x", 8822 I40E_GL_PRS_FVBM(2), reg); 8823 } else { 8824 ret = 0; 8825 } 8826 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x", 8827 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2))); 8828 8829 return ret; 8830 } 8831 8832 static int 8833 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg) 8834 { 8835 int ret = -EINVAL; 8836 8837 if (!hw || !cfg) 8838 return -EINVAL; 8839 8840 switch (cfg->cfg_type) { 8841 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN: 8842 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len); 8843 break; 8844 default: 8845 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type); 8846 break; 8847 } 8848 8849 return ret; 8850 } 8851 8852 static int 8853 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev, 8854 enum rte_filter_op filter_op, 8855 void *arg) 8856 { 8857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8858 int ret = I40E_ERR_PARAM; 8859 8860 switch (filter_op) { 8861 case RTE_ETH_FILTER_SET: 8862 ret = i40e_dev_global_config_set(hw, 8863 (struct rte_eth_global_cfg *)arg); 8864 break; 8865 default: 8866 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 8867 break; 8868 } 8869 8870 return ret; 8871 } 8872 8873 static int 8874 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, 8875 enum rte_filter_op filter_op, 8876 void *arg) 8877 { 8878 struct rte_eth_tunnel_filter_conf *filter; 8879 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8880 int ret = I40E_SUCCESS; 8881 8882 filter = (struct rte_eth_tunnel_filter_conf *)(arg); 8883 8884 if (i40e_tunnel_filter_param_check(pf, filter) < 0) 8885 return I40E_ERR_PARAM; 8886 8887 switch (filter_op) { 8888 case RTE_ETH_FILTER_NOP: 8889 if (!(pf->flags & I40E_FLAG_VXLAN)) 8890 ret = I40E_NOT_SUPPORTED; 8891 break; 8892 case RTE_ETH_FILTER_ADD: 8893 ret = i40e_dev_tunnel_filter_set(pf, filter, 1); 8894 break; 8895 case RTE_ETH_FILTER_DELETE: 8896 ret = i40e_dev_tunnel_filter_set(pf, filter, 0); 8897 break; 8898 default: 8899 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 8900 ret = I40E_ERR_PARAM; 8901 break; 8902 } 8903 8904 return ret; 8905 } 8906 8907 static int 8908 i40e_pf_config_mq_rx(struct i40e_pf *pf) 8909 { 8910 int ret = 0; 8911 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode; 8912 8913 /* RSS setup */ 8914 if (mq_mode & ETH_MQ_RX_RSS_FLAG) 8915 ret = i40e_pf_config_rss(pf); 8916 else 8917 i40e_pf_disable_rss(pf); 8918 8919 return ret; 8920 } 8921 8922 /* Get the symmetric hash enable configurations per port */ 8923 static void 8924 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable) 8925 { 8926 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); 8927 8928 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0; 8929 } 8930 8931 /* Set the symmetric hash enable configurations per port */ 8932 static void 8933 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable) 8934 { 8935 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); 8936 8937 if (enable > 0) { 8938 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) { 8939 PMD_DRV_LOG(INFO, 8940 "Symmetric hash has already been enabled"); 8941 return; 8942 } 8943 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK; 8944 } else { 8945 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) { 8946 PMD_DRV_LOG(INFO, 8947 "Symmetric hash has already been disabled"); 8948 return; 8949 } 8950 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK; 8951 } 8952 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg); 8953 I40E_WRITE_FLUSH(hw); 8954 } 8955 8956 /* 8957 * Get global configurations of hash function type and symmetric hash enable 8958 * per flow type (pctype). Note that global configuration means it affects all 8959 * the ports on the same NIC. 8960 */ 8961 static int 8962 i40e_get_hash_filter_global_config(struct i40e_hw *hw, 8963 struct rte_eth_hash_global_conf *g_cfg) 8964 { 8965 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back; 8966 uint32_t reg; 8967 uint16_t i, j; 8968 8969 memset(g_cfg, 0, sizeof(*g_cfg)); 8970 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 8971 if (reg & I40E_GLQF_CTL_HTOEP_MASK) 8972 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ; 8973 else 8974 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR; 8975 PMD_DRV_LOG(DEBUG, "Hash function is %s", 8976 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); 8977 8978 /* 8979 * As i40e supports less than 64 flow types, only first 64 bits need to 8980 * be checked. 8981 */ 8982 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { 8983 g_cfg->valid_bit_mask[i] = 0ULL; 8984 g_cfg->sym_hash_enable_mask[i] = 0ULL; 8985 } 8986 8987 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask; 8988 8989 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) { 8990 if (!adapter->pctypes_tbl[i]) 8991 continue; 8992 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 8993 j < I40E_FILTER_PCTYPE_MAX; j++) { 8994 if (adapter->pctypes_tbl[i] & (1ULL << j)) { 8995 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j)); 8996 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) { 8997 g_cfg->sym_hash_enable_mask[0] |= 8998 (1ULL << i); 8999 } 9000 } 9001 } 9002 } 9003 9004 return 0; 9005 } 9006 9007 static int 9008 i40e_hash_global_config_check(const struct i40e_adapter *adapter, 9009 const struct rte_eth_hash_global_conf *g_cfg) 9010 { 9011 uint32_t i; 9012 uint64_t mask0, i40e_mask = adapter->flow_types_mask; 9013 9014 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ && 9015 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR && 9016 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) { 9017 PMD_DRV_LOG(ERR, "Unsupported hash function type %d", 9018 g_cfg->hash_func); 9019 return -EINVAL; 9020 } 9021 9022 /* 9023 * As i40e supports less than 64 flow types, only first 64 bits need to 9024 * be checked. 9025 */ 9026 mask0 = g_cfg->valid_bit_mask[0]; 9027 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { 9028 if (i == 0) { 9029 /* Check if any unsupported flow type configured */ 9030 if ((mask0 | i40e_mask) ^ i40e_mask) 9031 goto mask_err; 9032 } else { 9033 if (g_cfg->valid_bit_mask[i]) 9034 goto mask_err; 9035 } 9036 } 9037 9038 return 0; 9039 9040 mask_err: 9041 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured"); 9042 9043 return -EINVAL; 9044 } 9045 9046 /* 9047 * Set global configurations of hash function type and symmetric hash enable 9048 * per flow type (pctype). Note any modifying global configuration will affect 9049 * all the ports on the same NIC. 9050 */ 9051 static int 9052 i40e_set_hash_filter_global_config(struct i40e_hw *hw, 9053 struct rte_eth_hash_global_conf *g_cfg) 9054 { 9055 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back; 9056 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 9057 int ret; 9058 uint16_t i, j; 9059 uint32_t reg; 9060 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask; 9061 9062 if (pf->support_multi_driver) { 9063 PMD_DRV_LOG(ERR, "Hash global configuration is not supported."); 9064 return -ENOTSUP; 9065 } 9066 9067 /* Check the input parameters */ 9068 ret = i40e_hash_global_config_check(adapter, g_cfg); 9069 if (ret < 0) 9070 return ret; 9071 9072 /* 9073 * As i40e supports less than 64 flow types, only first 64 bits need to 9074 * be configured. 9075 */ 9076 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) { 9077 if (mask0 & (1UL << i)) { 9078 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ? 9079 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; 9080 9081 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 9082 j < I40E_FILTER_PCTYPE_MAX; j++) { 9083 if (adapter->pctypes_tbl[i] & (1ULL << j)) 9084 i40e_write_global_rx_ctl(hw, 9085 I40E_GLQF_HSYM(j), 9086 reg); 9087 } 9088 } 9089 } 9090 9091 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 9092 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) { 9093 /* Toeplitz */ 9094 if (reg & I40E_GLQF_CTL_HTOEP_MASK) { 9095 PMD_DRV_LOG(DEBUG, 9096 "Hash function already set to Toeplitz"); 9097 goto out; 9098 } 9099 reg |= I40E_GLQF_CTL_HTOEP_MASK; 9100 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { 9101 /* Simple XOR */ 9102 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) { 9103 PMD_DRV_LOG(DEBUG, 9104 "Hash function already set to Simple XOR"); 9105 goto out; 9106 } 9107 reg &= ~I40E_GLQF_CTL_HTOEP_MASK; 9108 } else 9109 /* Use the default, and keep it as it is */ 9110 goto out; 9111 9112 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg); 9113 9114 out: 9115 I40E_WRITE_FLUSH(hw); 9116 9117 return 0; 9118 } 9119 9120 /** 9121 * Valid input sets for hash and flow director filters per PCTYPE 9122 */ 9123 static uint64_t 9124 i40e_get_valid_input_set(enum i40e_filter_pctype pctype, 9125 enum rte_filter_type filter) 9126 { 9127 uint64_t valid; 9128 9129 static const uint64_t valid_hash_inset_table[] = { 9130 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9131 I40E_INSET_DMAC | I40E_INSET_SMAC | 9132 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9133 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC | 9134 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS | 9135 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9136 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9137 I40E_INSET_FLEX_PAYLOAD, 9138 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9139 I40E_INSET_DMAC | I40E_INSET_SMAC | 9140 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9141 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9142 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9143 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9144 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9145 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9146 I40E_INSET_FLEX_PAYLOAD, 9147 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9148 I40E_INSET_DMAC | I40E_INSET_SMAC | 9149 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9150 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9151 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9152 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9153 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9154 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9155 I40E_INSET_FLEX_PAYLOAD, 9156 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9157 I40E_INSET_DMAC | I40E_INSET_SMAC | 9158 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9159 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9160 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9161 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9162 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9163 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9164 I40E_INSET_FLEX_PAYLOAD, 9165 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9166 I40E_INSET_DMAC | I40E_INSET_SMAC | 9167 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9168 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9169 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9170 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9171 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9172 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9173 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD, 9174 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9175 I40E_INSET_DMAC | I40E_INSET_SMAC | 9176 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9177 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9178 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9179 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9180 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9181 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9182 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD, 9183 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9184 I40E_INSET_DMAC | I40E_INSET_SMAC | 9185 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9186 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9187 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9188 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9189 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9190 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9191 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD, 9192 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9193 I40E_INSET_DMAC | I40E_INSET_SMAC | 9194 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9195 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9196 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9197 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9198 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9199 I40E_INSET_FLEX_PAYLOAD, 9200 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9201 I40E_INSET_DMAC | I40E_INSET_SMAC | 9202 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9203 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9204 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9205 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC | 9206 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC | 9207 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD, 9208 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9209 I40E_INSET_DMAC | I40E_INSET_SMAC | 9210 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9211 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9212 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9213 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9214 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9215 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD, 9216 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9217 I40E_INSET_DMAC | I40E_INSET_SMAC | 9218 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9219 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9220 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9221 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9222 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9223 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9224 I40E_INSET_FLEX_PAYLOAD, 9225 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9226 I40E_INSET_DMAC | I40E_INSET_SMAC | 9227 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9228 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9229 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9230 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9231 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9232 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9233 I40E_INSET_FLEX_PAYLOAD, 9234 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9235 I40E_INSET_DMAC | I40E_INSET_SMAC | 9236 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9237 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9238 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9239 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9240 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9241 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9242 I40E_INSET_FLEX_PAYLOAD, 9243 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9244 I40E_INSET_DMAC | I40E_INSET_SMAC | 9245 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9246 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9247 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9248 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9249 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9250 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9251 I40E_INSET_FLEX_PAYLOAD, 9252 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9253 I40E_INSET_DMAC | I40E_INSET_SMAC | 9254 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9255 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9256 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9257 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9258 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9259 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT | 9260 I40E_INSET_FLEX_PAYLOAD, 9261 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9262 I40E_INSET_DMAC | I40E_INSET_SMAC | 9263 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9264 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9265 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9266 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9267 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID | 9268 I40E_INSET_FLEX_PAYLOAD, 9269 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9270 I40E_INSET_DMAC | I40E_INSET_SMAC | 9271 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9272 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE | 9273 I40E_INSET_FLEX_PAYLOAD, 9274 }; 9275 9276 /** 9277 * Flow director supports only fields defined in 9278 * union rte_eth_fdir_flow. 9279 */ 9280 static const uint64_t valid_fdir_inset_table[] = { 9281 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9282 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9283 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9284 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO | 9285 I40E_INSET_IPV4_TTL, 9286 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9287 I40E_INSET_DMAC | I40E_INSET_SMAC | 9288 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9289 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9290 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9291 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9292 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9293 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9294 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9295 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9296 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9297 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9298 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9299 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9300 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9301 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9302 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9303 I40E_INSET_DMAC | I40E_INSET_SMAC | 9304 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9305 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9306 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9307 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9308 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9309 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9310 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9311 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9312 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9313 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9314 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9315 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9316 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9317 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9318 I40E_INSET_SCTP_VT, 9319 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9320 I40E_INSET_DMAC | I40E_INSET_SMAC | 9321 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9322 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9323 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO | 9324 I40E_INSET_IPV4_TTL, 9325 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9326 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9327 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9328 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR | 9329 I40E_INSET_IPV6_HOP_LIMIT, 9330 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9331 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9332 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9333 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9334 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9335 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9336 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9337 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9338 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9339 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9340 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9341 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9342 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9343 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9344 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9345 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9346 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9347 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9348 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9349 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9350 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9351 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9352 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9353 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9354 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9355 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9356 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9357 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9358 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9359 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9360 I40E_INSET_SCTP_VT, 9361 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9362 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9363 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9364 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR | 9365 I40E_INSET_IPV6_HOP_LIMIT, 9366 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9367 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9368 I40E_INSET_LAST_ETHER_TYPE, 9369 }; 9370 9371 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) 9372 return 0; 9373 if (filter == RTE_ETH_FILTER_HASH) 9374 valid = valid_hash_inset_table[pctype]; 9375 else 9376 valid = valid_fdir_inset_table[pctype]; 9377 9378 return valid; 9379 } 9380 9381 /** 9382 * Validate if the input set is allowed for a specific PCTYPE 9383 */ 9384 int 9385 i40e_validate_input_set(enum i40e_filter_pctype pctype, 9386 enum rte_filter_type filter, uint64_t inset) 9387 { 9388 uint64_t valid; 9389 9390 valid = i40e_get_valid_input_set(pctype, filter); 9391 if (inset & (~valid)) 9392 return -EINVAL; 9393 9394 return 0; 9395 } 9396 9397 /* default input set fields combination per pctype */ 9398 uint64_t 9399 i40e_get_default_input_set(uint16_t pctype) 9400 { 9401 static const uint64_t default_inset_table[] = { 9402 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9403 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, 9404 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9405 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9406 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9407 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9408 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9409 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9410 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9411 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9412 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9413 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9414 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9415 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9416 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9417 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9418 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9419 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9420 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9421 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9422 I40E_INSET_SCTP_VT, 9423 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9424 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, 9425 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9426 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, 9427 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9428 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9429 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9430 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9431 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9432 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9433 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9434 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9435 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9436 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9437 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9438 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9439 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9440 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9441 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9442 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9443 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9444 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9445 I40E_INSET_SCTP_VT, 9446 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9447 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, 9448 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9449 I40E_INSET_LAST_ETHER_TYPE, 9450 }; 9451 9452 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) 9453 return 0; 9454 9455 return default_inset_table[pctype]; 9456 } 9457 9458 /** 9459 * Parse the input set from index to logical bit masks 9460 */ 9461 static int 9462 i40e_parse_input_set(uint64_t *inset, 9463 enum i40e_filter_pctype pctype, 9464 enum rte_eth_input_set_field *field, 9465 uint16_t size) 9466 { 9467 uint16_t i, j; 9468 int ret = -EINVAL; 9469 9470 static const struct { 9471 enum rte_eth_input_set_field field; 9472 uint64_t inset; 9473 } inset_convert_table[] = { 9474 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE}, 9475 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC}, 9476 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC}, 9477 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER}, 9478 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER}, 9479 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE}, 9480 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC}, 9481 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST}, 9482 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS}, 9483 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO}, 9484 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL}, 9485 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC}, 9486 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST}, 9487 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC}, 9488 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER, 9489 I40E_INSET_IPV6_NEXT_HDR}, 9490 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS, 9491 I40E_INSET_IPV6_HOP_LIMIT}, 9492 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT}, 9493 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT}, 9494 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT}, 9495 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT}, 9496 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT}, 9497 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT}, 9498 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG, 9499 I40E_INSET_SCTP_VT}, 9500 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC, 9501 I40E_INSET_TUNNEL_DMAC}, 9502 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN, 9503 I40E_INSET_VLAN_TUNNEL}, 9504 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY, 9505 I40E_INSET_TUNNEL_ID}, 9506 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID}, 9507 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD, 9508 I40E_INSET_FLEX_PAYLOAD_W1}, 9509 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD, 9510 I40E_INSET_FLEX_PAYLOAD_W2}, 9511 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD, 9512 I40E_INSET_FLEX_PAYLOAD_W3}, 9513 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD, 9514 I40E_INSET_FLEX_PAYLOAD_W4}, 9515 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD, 9516 I40E_INSET_FLEX_PAYLOAD_W5}, 9517 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD, 9518 I40E_INSET_FLEX_PAYLOAD_W6}, 9519 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD, 9520 I40E_INSET_FLEX_PAYLOAD_W7}, 9521 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD, 9522 I40E_INSET_FLEX_PAYLOAD_W8}, 9523 }; 9524 9525 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX) 9526 return ret; 9527 9528 /* Only one item allowed for default or all */ 9529 if (size == 1) { 9530 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) { 9531 *inset = i40e_get_default_input_set(pctype); 9532 return 0; 9533 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) { 9534 *inset = I40E_INSET_NONE; 9535 return 0; 9536 } 9537 } 9538 9539 for (i = 0, *inset = 0; i < size; i++) { 9540 for (j = 0; j < RTE_DIM(inset_convert_table); j++) { 9541 if (field[i] == inset_convert_table[j].field) { 9542 *inset |= inset_convert_table[j].inset; 9543 break; 9544 } 9545 } 9546 9547 /* It contains unsupported input set, return immediately */ 9548 if (j == RTE_DIM(inset_convert_table)) 9549 return ret; 9550 } 9551 9552 return 0; 9553 } 9554 9555 /** 9556 * Translate the input set from bit masks to register aware bit masks 9557 * and vice versa 9558 */ 9559 uint64_t 9560 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input) 9561 { 9562 uint64_t val = 0; 9563 uint16_t i; 9564 9565 struct inset_map { 9566 uint64_t inset; 9567 uint64_t inset_reg; 9568 }; 9569 9570 static const struct inset_map inset_map_common[] = { 9571 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC}, 9572 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC}, 9573 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN}, 9574 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN}, 9575 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE}, 9576 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS}, 9577 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6}, 9578 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6}, 9579 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC}, 9580 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR}, 9581 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT}, 9582 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT}, 9583 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT}, 9584 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG}, 9585 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID}, 9586 {I40E_INSET_TUNNEL_DMAC, 9587 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC}, 9588 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4}, 9589 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6}, 9590 {I40E_INSET_TUNNEL_SRC_PORT, 9591 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT}, 9592 {I40E_INSET_TUNNEL_DST_PORT, 9593 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT}, 9594 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN}, 9595 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1}, 9596 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2}, 9597 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3}, 9598 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4}, 9599 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5}, 9600 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6}, 9601 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7}, 9602 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8}, 9603 }; 9604 9605 /* some different registers map in x722*/ 9606 static const struct inset_map inset_map_diff_x722[] = { 9607 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4}, 9608 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4}, 9609 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO}, 9610 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL}, 9611 }; 9612 9613 static const struct inset_map inset_map_diff_not_x722[] = { 9614 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4}, 9615 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4}, 9616 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO}, 9617 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL}, 9618 }; 9619 9620 if (input == 0) 9621 return val; 9622 9623 /* Translate input set to register aware inset */ 9624 if (type == I40E_MAC_X722) { 9625 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) { 9626 if (input & inset_map_diff_x722[i].inset) 9627 val |= inset_map_diff_x722[i].inset_reg; 9628 } 9629 } else { 9630 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) { 9631 if (input & inset_map_diff_not_x722[i].inset) 9632 val |= inset_map_diff_not_x722[i].inset_reg; 9633 } 9634 } 9635 9636 for (i = 0; i < RTE_DIM(inset_map_common); i++) { 9637 if (input & inset_map_common[i].inset) 9638 val |= inset_map_common[i].inset_reg; 9639 } 9640 9641 return val; 9642 } 9643 9644 int 9645 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem) 9646 { 9647 uint8_t i, idx = 0; 9648 uint64_t inset_need_mask = inset; 9649 9650 static const struct { 9651 uint64_t inset; 9652 uint32_t mask; 9653 } inset_mask_map[] = { 9654 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK}, 9655 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0}, 9656 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK}, 9657 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK}, 9658 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK}, 9659 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0}, 9660 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK}, 9661 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK}, 9662 }; 9663 9664 if (!inset || !mask || !nb_elem) 9665 return 0; 9666 9667 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { 9668 /* Clear the inset bit, if no MASK is required, 9669 * for example proto + ttl 9670 */ 9671 if ((inset & inset_mask_map[i].inset) == 9672 inset_mask_map[i].inset && inset_mask_map[i].mask == 0) 9673 inset_need_mask &= ~inset_mask_map[i].inset; 9674 if (!inset_need_mask) 9675 return 0; 9676 } 9677 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { 9678 if ((inset_need_mask & inset_mask_map[i].inset) == 9679 inset_mask_map[i].inset) { 9680 if (idx >= nb_elem) { 9681 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks"); 9682 return -EINVAL; 9683 } 9684 mask[idx] = inset_mask_map[i].mask; 9685 idx++; 9686 } 9687 } 9688 9689 return idx; 9690 } 9691 9692 void 9693 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) 9694 { 9695 uint32_t reg = i40e_read_rx_ctl(hw, addr); 9696 9697 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg); 9698 if (reg != val) 9699 i40e_write_rx_ctl(hw, addr, val); 9700 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr, 9701 (uint32_t)i40e_read_rx_ctl(hw, addr)); 9702 } 9703 9704 void 9705 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) 9706 { 9707 uint32_t reg = i40e_read_rx_ctl(hw, addr); 9708 struct rte_eth_dev *dev; 9709 9710 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 9711 if (reg != val) { 9712 i40e_write_rx_ctl(hw, addr, val); 9713 PMD_DRV_LOG(WARNING, 9714 "i40e device %s changed global register [0x%08x]." 9715 " original: 0x%08x, new: 0x%08x", 9716 dev->device->name, addr, reg, 9717 (uint32_t)i40e_read_rx_ctl(hw, addr)); 9718 } 9719 } 9720 9721 static void 9722 i40e_filter_input_set_init(struct i40e_pf *pf) 9723 { 9724 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9725 enum i40e_filter_pctype pctype; 9726 uint64_t input_set, inset_reg; 9727 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9728 int num, i; 9729 uint16_t flow_type; 9730 9731 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 9732 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) { 9733 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype); 9734 9735 if (flow_type == RTE_ETH_FLOW_UNKNOWN) 9736 continue; 9737 9738 input_set = i40e_get_default_input_set(pctype); 9739 9740 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9741 I40E_INSET_MASK_NUM_REG); 9742 if (num < 0) 9743 return; 9744 if (pf->support_multi_driver && num > 0) { 9745 PMD_DRV_LOG(ERR, "Input set setting is not supported."); 9746 return; 9747 } 9748 inset_reg = i40e_translate_input_set_reg(hw->mac.type, 9749 input_set); 9750 9751 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 9752 (uint32_t)(inset_reg & UINT32_MAX)); 9753 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 9754 (uint32_t)((inset_reg >> 9755 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9756 if (!pf->support_multi_driver) { 9757 i40e_check_write_global_reg(hw, 9758 I40E_GLQF_HASH_INSET(0, pctype), 9759 (uint32_t)(inset_reg & UINT32_MAX)); 9760 i40e_check_write_global_reg(hw, 9761 I40E_GLQF_HASH_INSET(1, pctype), 9762 (uint32_t)((inset_reg >> 9763 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9764 9765 for (i = 0; i < num; i++) { 9766 i40e_check_write_global_reg(hw, 9767 I40E_GLQF_FD_MSK(i, pctype), 9768 mask_reg[i]); 9769 i40e_check_write_global_reg(hw, 9770 I40E_GLQF_HASH_MSK(i, pctype), 9771 mask_reg[i]); 9772 } 9773 /*clear unused mask registers of the pctype */ 9774 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) { 9775 i40e_check_write_global_reg(hw, 9776 I40E_GLQF_FD_MSK(i, pctype), 9777 0); 9778 i40e_check_write_global_reg(hw, 9779 I40E_GLQF_HASH_MSK(i, pctype), 9780 0); 9781 } 9782 } else { 9783 PMD_DRV_LOG(ERR, "Input set setting is not supported."); 9784 } 9785 I40E_WRITE_FLUSH(hw); 9786 9787 /* store the default input set */ 9788 if (!pf->support_multi_driver) 9789 pf->hash_input_set[pctype] = input_set; 9790 pf->fdir.input_set[pctype] = input_set; 9791 } 9792 } 9793 9794 int 9795 i40e_hash_filter_inset_select(struct i40e_hw *hw, 9796 struct rte_eth_input_set_conf *conf) 9797 { 9798 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 9799 enum i40e_filter_pctype pctype; 9800 uint64_t input_set, inset_reg = 0; 9801 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9802 int ret, i, num; 9803 9804 if (!conf) { 9805 PMD_DRV_LOG(ERR, "Invalid pointer"); 9806 return -EFAULT; 9807 } 9808 if (conf->op != RTE_ETH_INPUT_SET_SELECT && 9809 conf->op != RTE_ETH_INPUT_SET_ADD) { 9810 PMD_DRV_LOG(ERR, "Unsupported input set operation"); 9811 return -EINVAL; 9812 } 9813 9814 if (pf->support_multi_driver) { 9815 PMD_DRV_LOG(ERR, "Hash input set setting is not supported."); 9816 return -ENOTSUP; 9817 } 9818 9819 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); 9820 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 9821 PMD_DRV_LOG(ERR, "invalid flow_type input."); 9822 return -EINVAL; 9823 } 9824 9825 if (hw->mac.type == I40E_MAC_X722) { 9826 /* get translated pctype value in fd pctype register */ 9827 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw, 9828 I40E_GLQF_FD_PCTYPES((int)pctype)); 9829 } 9830 9831 ret = i40e_parse_input_set(&input_set, pctype, conf->field, 9832 conf->inset_size); 9833 if (ret) { 9834 PMD_DRV_LOG(ERR, "Failed to parse input set"); 9835 return -EINVAL; 9836 } 9837 9838 if (conf->op == RTE_ETH_INPUT_SET_ADD) { 9839 /* get inset value in register */ 9840 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype)); 9841 inset_reg <<= I40E_32_BIT_WIDTH; 9842 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype)); 9843 input_set |= pf->hash_input_set[pctype]; 9844 } 9845 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9846 I40E_INSET_MASK_NUM_REG); 9847 if (num < 0) 9848 return -EINVAL; 9849 9850 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 9851 9852 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype), 9853 (uint32_t)(inset_reg & UINT32_MAX)); 9854 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), 9855 (uint32_t)((inset_reg >> 9856 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9857 9858 for (i = 0; i < num; i++) 9859 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 9860 mask_reg[i]); 9861 /*clear unused mask registers of the pctype */ 9862 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 9863 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 9864 0); 9865 I40E_WRITE_FLUSH(hw); 9866 9867 pf->hash_input_set[pctype] = input_set; 9868 return 0; 9869 } 9870 9871 int 9872 i40e_fdir_filter_inset_select(struct i40e_pf *pf, 9873 struct rte_eth_input_set_conf *conf) 9874 { 9875 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9876 enum i40e_filter_pctype pctype; 9877 uint64_t input_set, inset_reg = 0; 9878 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9879 int ret, i, num; 9880 9881 if (!hw || !conf) { 9882 PMD_DRV_LOG(ERR, "Invalid pointer"); 9883 return -EFAULT; 9884 } 9885 if (conf->op != RTE_ETH_INPUT_SET_SELECT && 9886 conf->op != RTE_ETH_INPUT_SET_ADD) { 9887 PMD_DRV_LOG(ERR, "Unsupported input set operation"); 9888 return -EINVAL; 9889 } 9890 9891 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); 9892 9893 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 9894 PMD_DRV_LOG(ERR, "invalid flow_type input."); 9895 return -EINVAL; 9896 } 9897 9898 ret = i40e_parse_input_set(&input_set, pctype, conf->field, 9899 conf->inset_size); 9900 if (ret) { 9901 PMD_DRV_LOG(ERR, "Failed to parse input set"); 9902 return -EINVAL; 9903 } 9904 9905 /* get inset value in register */ 9906 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1)); 9907 inset_reg <<= I40E_32_BIT_WIDTH; 9908 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0)); 9909 9910 /* Can not change the inset reg for flex payload for fdir, 9911 * it is done by writing I40E_PRTQF_FD_FLXINSET 9912 * in i40e_set_flex_mask_on_pctype. 9913 */ 9914 if (conf->op == RTE_ETH_INPUT_SET_SELECT) 9915 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS; 9916 else 9917 input_set |= pf->fdir.input_set[pctype]; 9918 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9919 I40E_INSET_MASK_NUM_REG); 9920 if (num < 0) 9921 return -EINVAL; 9922 if (pf->support_multi_driver && num > 0) { 9923 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); 9924 return -ENOTSUP; 9925 } 9926 9927 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 9928 9929 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 9930 (uint32_t)(inset_reg & UINT32_MAX)); 9931 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 9932 (uint32_t)((inset_reg >> 9933 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9934 9935 if (!pf->support_multi_driver) { 9936 for (i = 0; i < num; i++) 9937 i40e_check_write_global_reg(hw, 9938 I40E_GLQF_FD_MSK(i, pctype), 9939 mask_reg[i]); 9940 /*clear unused mask registers of the pctype */ 9941 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 9942 i40e_check_write_global_reg(hw, 9943 I40E_GLQF_FD_MSK(i, pctype), 9944 0); 9945 } else { 9946 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); 9947 } 9948 I40E_WRITE_FLUSH(hw); 9949 9950 pf->fdir.input_set[pctype] = input_set; 9951 return 0; 9952 } 9953 9954 static int 9955 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) 9956 { 9957 int ret = 0; 9958 9959 if (!hw || !info) { 9960 PMD_DRV_LOG(ERR, "Invalid pointer"); 9961 return -EFAULT; 9962 } 9963 9964 switch (info->info_type) { 9965 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT: 9966 i40e_get_symmetric_hash_enable_per_port(hw, 9967 &(info->info.enable)); 9968 break; 9969 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG: 9970 ret = i40e_get_hash_filter_global_config(hw, 9971 &(info->info.global_conf)); 9972 break; 9973 default: 9974 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", 9975 info->info_type); 9976 ret = -EINVAL; 9977 break; 9978 } 9979 9980 return ret; 9981 } 9982 9983 static int 9984 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) 9985 { 9986 int ret = 0; 9987 9988 if (!hw || !info) { 9989 PMD_DRV_LOG(ERR, "Invalid pointer"); 9990 return -EFAULT; 9991 } 9992 9993 switch (info->info_type) { 9994 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT: 9995 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable); 9996 break; 9997 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG: 9998 ret = i40e_set_hash_filter_global_config(hw, 9999 &(info->info.global_conf)); 10000 break; 10001 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT: 10002 ret = i40e_hash_filter_inset_select(hw, 10003 &(info->info.input_set_conf)); 10004 break; 10005 10006 default: 10007 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", 10008 info->info_type); 10009 ret = -EINVAL; 10010 break; 10011 } 10012 10013 return ret; 10014 } 10015 10016 /* Operations for hash function */ 10017 static int 10018 i40e_hash_filter_ctrl(struct rte_eth_dev *dev, 10019 enum rte_filter_op filter_op, 10020 void *arg) 10021 { 10022 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10023 int ret = 0; 10024 10025 switch (filter_op) { 10026 case RTE_ETH_FILTER_NOP: 10027 break; 10028 case RTE_ETH_FILTER_GET: 10029 ret = i40e_hash_filter_get(hw, 10030 (struct rte_eth_hash_filter_info *)arg); 10031 break; 10032 case RTE_ETH_FILTER_SET: 10033 ret = i40e_hash_filter_set(hw, 10034 (struct rte_eth_hash_filter_info *)arg); 10035 break; 10036 default: 10037 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported", 10038 filter_op); 10039 ret = -ENOTSUP; 10040 break; 10041 } 10042 10043 return ret; 10044 } 10045 10046 /* Convert ethertype filter structure */ 10047 static int 10048 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input, 10049 struct i40e_ethertype_filter *filter) 10050 { 10051 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, 10052 RTE_ETHER_ADDR_LEN); 10053 filter->input.ether_type = input->ether_type; 10054 filter->flags = input->flags; 10055 filter->queue = input->queue; 10056 10057 return 0; 10058 } 10059 10060 /* Check if there exists the ehtertype filter */ 10061 struct i40e_ethertype_filter * 10062 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 10063 const struct i40e_ethertype_filter_input *input) 10064 { 10065 int ret; 10066 10067 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input); 10068 if (ret < 0) 10069 return NULL; 10070 10071 return ethertype_rule->hash_map[ret]; 10072 } 10073 10074 /* Add ethertype filter in SW list */ 10075 static int 10076 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf, 10077 struct i40e_ethertype_filter *filter) 10078 { 10079 struct i40e_ethertype_rule *rule = &pf->ethertype; 10080 int ret; 10081 10082 ret = rte_hash_add_key(rule->hash_table, &filter->input); 10083 if (ret < 0) { 10084 PMD_DRV_LOG(ERR, 10085 "Failed to insert ethertype filter" 10086 " to hash table %d!", 10087 ret); 10088 return ret; 10089 } 10090 rule->hash_map[ret] = filter; 10091 10092 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules); 10093 10094 return 0; 10095 } 10096 10097 /* Delete ethertype filter in SW list */ 10098 int 10099 i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 10100 struct i40e_ethertype_filter_input *input) 10101 { 10102 struct i40e_ethertype_rule *rule = &pf->ethertype; 10103 struct i40e_ethertype_filter *filter; 10104 int ret; 10105 10106 ret = rte_hash_del_key(rule->hash_table, input); 10107 if (ret < 0) { 10108 PMD_DRV_LOG(ERR, 10109 "Failed to delete ethertype filter" 10110 " to hash table %d!", 10111 ret); 10112 return ret; 10113 } 10114 filter = rule->hash_map[ret]; 10115 rule->hash_map[ret] = NULL; 10116 10117 TAILQ_REMOVE(&rule->ethertype_list, filter, rules); 10118 rte_free(filter); 10119 10120 return 0; 10121 } 10122 10123 /* 10124 * Configure ethertype filter, which can director packet by filtering 10125 * with mac address and ether_type or only ether_type 10126 */ 10127 int 10128 i40e_ethertype_filter_set(struct i40e_pf *pf, 10129 struct rte_eth_ethertype_filter *filter, 10130 bool add) 10131 { 10132 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 10133 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 10134 struct i40e_ethertype_filter *ethertype_filter, *node; 10135 struct i40e_ethertype_filter check_filter; 10136 struct i40e_control_filter_stats stats; 10137 uint16_t flags = 0; 10138 int ret; 10139 10140 if (filter->queue >= pf->dev_data->nb_rx_queues) { 10141 PMD_DRV_LOG(ERR, "Invalid queue ID"); 10142 return -EINVAL; 10143 } 10144 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 10145 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 10146 PMD_DRV_LOG(ERR, 10147 "unsupported ether_type(0x%04x) in control packet filter.", 10148 filter->ether_type); 10149 return -EINVAL; 10150 } 10151 if (filter->ether_type == RTE_ETHER_TYPE_VLAN) 10152 PMD_DRV_LOG(WARNING, 10153 "filter vlan ether_type in first tag is not supported."); 10154 10155 /* Check if there is the filter in SW list */ 10156 memset(&check_filter, 0, sizeof(check_filter)); 10157 i40e_ethertype_filter_convert(filter, &check_filter); 10158 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, 10159 &check_filter.input); 10160 if (add && node) { 10161 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!"); 10162 return -EINVAL; 10163 } 10164 10165 if (!add && !node) { 10166 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!"); 10167 return -EINVAL; 10168 } 10169 10170 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC)) 10171 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 10172 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) 10173 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 10174 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 10175 10176 memset(&stats, 0, sizeof(stats)); 10177 ret = i40e_aq_add_rem_control_packet_filter(hw, 10178 filter->mac_addr.addr_bytes, 10179 filter->ether_type, flags, 10180 pf->main_vsi->seid, 10181 filter->queue, add, &stats, NULL); 10182 10183 PMD_DRV_LOG(INFO, 10184 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u", 10185 ret, stats.mac_etype_used, stats.etype_used, 10186 stats.mac_etype_free, stats.etype_free); 10187 if (ret < 0) 10188 return -ENOSYS; 10189 10190 /* Add or delete a filter in SW list */ 10191 if (add) { 10192 ethertype_filter = rte_zmalloc("ethertype_filter", 10193 sizeof(*ethertype_filter), 0); 10194 if (ethertype_filter == NULL) { 10195 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 10196 return -ENOMEM; 10197 } 10198 10199 rte_memcpy(ethertype_filter, &check_filter, 10200 sizeof(check_filter)); 10201 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter); 10202 if (ret < 0) 10203 rte_free(ethertype_filter); 10204 } else { 10205 ret = i40e_sw_ethertype_filter_del(pf, &node->input); 10206 } 10207 10208 return ret; 10209 } 10210 10211 /* 10212 * Handle operations for ethertype filter. 10213 */ 10214 static int 10215 i40e_ethertype_filter_handle(struct rte_eth_dev *dev, 10216 enum rte_filter_op filter_op, 10217 void *arg) 10218 { 10219 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10220 int ret = 0; 10221 10222 if (filter_op == RTE_ETH_FILTER_NOP) 10223 return ret; 10224 10225 if (arg == NULL) { 10226 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 10227 filter_op); 10228 return -EINVAL; 10229 } 10230 10231 switch (filter_op) { 10232 case RTE_ETH_FILTER_ADD: 10233 ret = i40e_ethertype_filter_set(pf, 10234 (struct rte_eth_ethertype_filter *)arg, 10235 TRUE); 10236 break; 10237 case RTE_ETH_FILTER_DELETE: 10238 ret = i40e_ethertype_filter_set(pf, 10239 (struct rte_eth_ethertype_filter *)arg, 10240 FALSE); 10241 break; 10242 default: 10243 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 10244 ret = -ENOSYS; 10245 break; 10246 } 10247 return ret; 10248 } 10249 10250 static int 10251 i40e_dev_filter_ctrl(struct rte_eth_dev *dev, 10252 enum rte_filter_type filter_type, 10253 enum rte_filter_op filter_op, 10254 void *arg) 10255 { 10256 int ret = 0; 10257 10258 if (dev == NULL) 10259 return -EINVAL; 10260 10261 switch (filter_type) { 10262 case RTE_ETH_FILTER_NONE: 10263 /* For global configuration */ 10264 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg); 10265 break; 10266 case RTE_ETH_FILTER_HASH: 10267 ret = i40e_hash_filter_ctrl(dev, filter_op, arg); 10268 break; 10269 case RTE_ETH_FILTER_MACVLAN: 10270 ret = i40e_mac_filter_handle(dev, filter_op, arg); 10271 break; 10272 case RTE_ETH_FILTER_ETHERTYPE: 10273 ret = i40e_ethertype_filter_handle(dev, filter_op, arg); 10274 break; 10275 case RTE_ETH_FILTER_TUNNEL: 10276 ret = i40e_tunnel_filter_handle(dev, filter_op, arg); 10277 break; 10278 case RTE_ETH_FILTER_FDIR: 10279 ret = i40e_fdir_ctrl_func(dev, filter_op, arg); 10280 break; 10281 case RTE_ETH_FILTER_GENERIC: 10282 if (filter_op != RTE_ETH_FILTER_GET) 10283 return -EINVAL; 10284 *(const void **)arg = &i40e_flow_ops; 10285 break; 10286 default: 10287 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 10288 filter_type); 10289 ret = -EINVAL; 10290 break; 10291 } 10292 10293 return ret; 10294 } 10295 10296 /* 10297 * Check and enable Extended Tag. 10298 * Enabling Extended Tag is important for 40G performance. 10299 */ 10300 static void 10301 i40e_enable_extended_tag(struct rte_eth_dev *dev) 10302 { 10303 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 10304 uint32_t buf = 0; 10305 int ret; 10306 10307 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf), 10308 PCI_DEV_CAP_REG); 10309 if (ret < 0) { 10310 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", 10311 PCI_DEV_CAP_REG); 10312 return; 10313 } 10314 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { 10315 PMD_DRV_LOG(ERR, "Does not support Extended Tag"); 10316 return; 10317 } 10318 10319 buf = 0; 10320 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf), 10321 PCI_DEV_CTRL_REG); 10322 if (ret < 0) { 10323 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", 10324 PCI_DEV_CTRL_REG); 10325 return; 10326 } 10327 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { 10328 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); 10329 return; 10330 } 10331 buf |= PCI_DEV_CTRL_EXT_TAG_MASK; 10332 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf), 10333 PCI_DEV_CTRL_REG); 10334 if (ret < 0) { 10335 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", 10336 PCI_DEV_CTRL_REG); 10337 return; 10338 } 10339 } 10340 10341 /* 10342 * As some registers wouldn't be reset unless a global hardware reset, 10343 * hardware initialization is needed to put those registers into an 10344 * expected initial state. 10345 */ 10346 static void 10347 i40e_hw_init(struct rte_eth_dev *dev) 10348 { 10349 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10350 10351 i40e_enable_extended_tag(dev); 10352 10353 /* clear the PF Queue Filter control register */ 10354 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0); 10355 10356 /* Disable symmetric hash per port */ 10357 i40e_set_symmetric_hash_enable_per_port(hw, 0); 10358 } 10359 10360 /* 10361 * For X722 it is possible to have multiple pctypes mapped to the same flowtype 10362 * however this function will return only one highest pctype index, 10363 * which is not quite correct. This is known problem of i40e driver 10364 * and needs to be fixed later. 10365 */ 10366 enum i40e_filter_pctype 10367 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type) 10368 { 10369 int i; 10370 uint64_t pctype_mask; 10371 10372 if (flow_type < I40E_FLOW_TYPE_MAX) { 10373 pctype_mask = adapter->pctypes_tbl[flow_type]; 10374 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) { 10375 if (pctype_mask & (1ULL << i)) 10376 return (enum i40e_filter_pctype)i; 10377 } 10378 } 10379 return I40E_FILTER_PCTYPE_INVALID; 10380 } 10381 10382 uint16_t 10383 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 10384 enum i40e_filter_pctype pctype) 10385 { 10386 uint16_t flowtype; 10387 uint64_t pctype_mask = 1ULL << pctype; 10388 10389 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX; 10390 flowtype++) { 10391 if (adapter->pctypes_tbl[flowtype] & pctype_mask) 10392 return flowtype; 10393 } 10394 10395 return RTE_ETH_FLOW_UNKNOWN; 10396 } 10397 10398 /* 10399 * On X710, performance number is far from the expectation on recent firmware 10400 * versions; on XL710, performance number is also far from the expectation on 10401 * recent firmware versions, if promiscuous mode is disabled, or promiscuous 10402 * mode is enabled and port MAC address is equal to the packet destination MAC 10403 * address. The fix for this issue may not be integrated in the following 10404 * firmware version. So the workaround in software driver is needed. It needs 10405 * to modify the initial values of 3 internal only registers for both X710 and 10406 * XL710. Note that the values for X710 or XL710 could be different, and the 10407 * workaround can be removed when it is fixed in firmware in the future. 10408 */ 10409 10410 /* For both X710 and XL710 */ 10411 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200 10412 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200 10413 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00 10414 10415 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200 10416 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08 10417 10418 /* For X722 */ 10419 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200 10420 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200 10421 10422 /* For X710 */ 10423 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303 10424 /* For XL710 */ 10425 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606 10426 #define I40E_GL_SWR_PM_UP_THR 0x269FBC 10427 10428 /* 10429 * GL_SWR_PM_UP_THR: 10430 * The value is not impacted from the link speed, its value is set according 10431 * to the total number of ports for a better pipe-monitor configuration. 10432 */ 10433 static bool 10434 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value) 10435 { 10436 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \ 10437 .device_id = (dev), \ 10438 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE 10439 10440 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \ 10441 .device_id = (dev), \ 10442 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE 10443 10444 static const struct { 10445 uint16_t device_id; 10446 uint32_t val; 10447 } swr_pm_table[] = { 10448 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) }, 10449 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) }, 10450 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) }, 10451 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) }, 10452 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) }, 10453 10454 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) }, 10455 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) }, 10456 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) }, 10457 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) }, 10458 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) }, 10459 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) }, 10460 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) }, 10461 }; 10462 uint32_t i; 10463 10464 if (value == NULL) { 10465 PMD_DRV_LOG(ERR, "value is NULL"); 10466 return false; 10467 } 10468 10469 for (i = 0; i < RTE_DIM(swr_pm_table); i++) { 10470 if (hw->device_id == swr_pm_table[i].device_id) { 10471 *value = swr_pm_table[i].val; 10472 10473 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR " 10474 "value - 0x%08x", 10475 hw->device_id, *value); 10476 return true; 10477 } 10478 } 10479 10480 return false; 10481 } 10482 10483 static int 10484 i40e_dev_sync_phy_type(struct i40e_hw *hw) 10485 { 10486 enum i40e_status_code status; 10487 struct i40e_aq_get_phy_abilities_resp phy_ab; 10488 int ret = -ENOTSUP; 10489 int retries = 0; 10490 10491 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, 10492 NULL); 10493 10494 while (status) { 10495 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d", 10496 status); 10497 retries++; 10498 rte_delay_us(100000); 10499 if (retries < 5) 10500 status = i40e_aq_get_phy_capabilities(hw, false, 10501 true, &phy_ab, NULL); 10502 else 10503 return ret; 10504 } 10505 return 0; 10506 } 10507 10508 static void 10509 i40e_configure_registers(struct i40e_hw *hw) 10510 { 10511 static struct { 10512 uint32_t addr; 10513 uint64_t val; 10514 } reg_table[] = { 10515 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0}, 10516 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0}, 10517 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */ 10518 }; 10519 uint64_t reg; 10520 uint32_t i; 10521 int ret; 10522 10523 for (i = 0; i < RTE_DIM(reg_table); i++) { 10524 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) { 10525 if (hw->mac.type == I40E_MAC_X722) /* For X722 */ 10526 reg_table[i].val = 10527 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE; 10528 else /* For X710/XL710/XXV710 */ 10529 if (hw->aq.fw_maj_ver < 6) 10530 reg_table[i].val = 10531 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1; 10532 else 10533 reg_table[i].val = 10534 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2; 10535 } 10536 10537 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) { 10538 if (hw->mac.type == I40E_MAC_X722) /* For X722 */ 10539 reg_table[i].val = 10540 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE; 10541 else /* For X710/XL710/XXV710 */ 10542 reg_table[i].val = 10543 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE; 10544 } 10545 10546 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) { 10547 uint32_t cfg_val; 10548 10549 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) { 10550 PMD_DRV_LOG(DEBUG, "Device 0x%x skips " 10551 "GL_SWR_PM_UP_THR value fixup", 10552 hw->device_id); 10553 continue; 10554 } 10555 10556 reg_table[i].val = cfg_val; 10557 } 10558 10559 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr, 10560 ®, NULL); 10561 if (ret < 0) { 10562 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32, 10563 reg_table[i].addr); 10564 break; 10565 } 10566 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64, 10567 reg_table[i].addr, reg); 10568 if (reg == reg_table[i].val) 10569 continue; 10570 10571 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr, 10572 reg_table[i].val, NULL); 10573 if (ret < 0) { 10574 PMD_DRV_LOG(ERR, 10575 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32, 10576 reg_table[i].val, reg_table[i].addr); 10577 break; 10578 } 10579 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of " 10580 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr); 10581 } 10582 } 10583 10584 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4)) 10585 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030 10586 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4)) 10587 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab 10588 static int 10589 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi) 10590 { 10591 uint32_t reg; 10592 int ret; 10593 10594 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) { 10595 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum"); 10596 return -EINVAL; 10597 } 10598 10599 /* Configure for double VLAN RX stripping */ 10600 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id)); 10601 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) { 10602 reg |= I40E_VSI_TSR_QINQ_CONFIG; 10603 ret = i40e_aq_debug_write_register(hw, 10604 I40E_VSI_TSR(vsi->vsi_id), 10605 reg, NULL); 10606 if (ret < 0) { 10607 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]", 10608 vsi->vsi_id); 10609 return I40E_ERR_CONFIG; 10610 } 10611 } 10612 10613 /* Configure for double VLAN TX insertion */ 10614 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id)); 10615 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) { 10616 reg = I40E_VSI_L2TAGSTXVALID_QINQ; 10617 ret = i40e_aq_debug_write_register(hw, 10618 I40E_VSI_L2TAGSTXVALID( 10619 vsi->vsi_id), reg, NULL); 10620 if (ret < 0) { 10621 PMD_DRV_LOG(ERR, 10622 "Failed to update VSI_L2TAGSTXVALID[%d]", 10623 vsi->vsi_id); 10624 return I40E_ERR_CONFIG; 10625 } 10626 } 10627 10628 return 0; 10629 } 10630 10631 /** 10632 * i40e_aq_add_mirror_rule 10633 * @hw: pointer to the hardware structure 10634 * @seid: VEB seid to add mirror rule to 10635 * @dst_id: destination vsi seid 10636 * @entries: Buffer which contains the entities to be mirrored 10637 * @count: number of entities contained in the buffer 10638 * @rule_id:the rule_id of the rule to be added 10639 * 10640 * Add a mirror rule for a given veb. 10641 * 10642 **/ 10643 static enum i40e_status_code 10644 i40e_aq_add_mirror_rule(struct i40e_hw *hw, 10645 uint16_t seid, uint16_t dst_id, 10646 uint16_t rule_type, uint16_t *entries, 10647 uint16_t count, uint16_t *rule_id) 10648 { 10649 struct i40e_aq_desc desc; 10650 struct i40e_aqc_add_delete_mirror_rule cmd; 10651 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 10652 (struct i40e_aqc_add_delete_mirror_rule_completion *) 10653 &desc.params.raw; 10654 uint16_t buff_len; 10655 enum i40e_status_code status; 10656 10657 i40e_fill_default_direct_cmd_desc(&desc, 10658 i40e_aqc_opc_add_mirror_rule); 10659 memset(&cmd, 0, sizeof(cmd)); 10660 10661 buff_len = sizeof(uint16_t) * count; 10662 desc.datalen = rte_cpu_to_le_16(buff_len); 10663 if (buff_len > 0) 10664 desc.flags |= rte_cpu_to_le_16( 10665 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 10666 cmd.rule_type = rte_cpu_to_le_16(rule_type << 10667 I40E_AQC_MIRROR_RULE_TYPE_SHIFT); 10668 cmd.num_entries = rte_cpu_to_le_16(count); 10669 cmd.seid = rte_cpu_to_le_16(seid); 10670 cmd.destination = rte_cpu_to_le_16(dst_id); 10671 10672 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd)); 10673 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL); 10674 PMD_DRV_LOG(INFO, 10675 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,", 10676 hw->aq.asq_last_status, resp->rule_id, 10677 resp->mirror_rules_used, resp->mirror_rules_free); 10678 *rule_id = rte_le_to_cpu_16(resp->rule_id); 10679 10680 return status; 10681 } 10682 10683 /** 10684 * i40e_aq_del_mirror_rule 10685 * @hw: pointer to the hardware structure 10686 * @seid: VEB seid to add mirror rule to 10687 * @entries: Buffer which contains the entities to be mirrored 10688 * @count: number of entities contained in the buffer 10689 * @rule_id:the rule_id of the rule to be delete 10690 * 10691 * Delete a mirror rule for a given veb. 10692 * 10693 **/ 10694 static enum i40e_status_code 10695 i40e_aq_del_mirror_rule(struct i40e_hw *hw, 10696 uint16_t seid, uint16_t rule_type, uint16_t *entries, 10697 uint16_t count, uint16_t rule_id) 10698 { 10699 struct i40e_aq_desc desc; 10700 struct i40e_aqc_add_delete_mirror_rule cmd; 10701 uint16_t buff_len = 0; 10702 enum i40e_status_code status; 10703 void *buff = NULL; 10704 10705 i40e_fill_default_direct_cmd_desc(&desc, 10706 i40e_aqc_opc_delete_mirror_rule); 10707 memset(&cmd, 0, sizeof(cmd)); 10708 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 10709 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF | 10710 I40E_AQ_FLAG_RD)); 10711 cmd.num_entries = count; 10712 buff_len = sizeof(uint16_t) * count; 10713 desc.datalen = rte_cpu_to_le_16(buff_len); 10714 buff = (void *)entries; 10715 } else 10716 /* rule id is filled in destination field for deleting mirror rule */ 10717 cmd.destination = rte_cpu_to_le_16(rule_id); 10718 10719 cmd.rule_type = rte_cpu_to_le_16(rule_type << 10720 I40E_AQC_MIRROR_RULE_TYPE_SHIFT); 10721 cmd.seid = rte_cpu_to_le_16(seid); 10722 10723 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd)); 10724 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL); 10725 10726 return status; 10727 } 10728 10729 /** 10730 * i40e_mirror_rule_set 10731 * @dev: pointer to the hardware structure 10732 * @mirror_conf: mirror rule info 10733 * @sw_id: mirror rule's sw_id 10734 * @on: enable/disable 10735 * 10736 * set a mirror rule. 10737 * 10738 **/ 10739 static int 10740 i40e_mirror_rule_set(struct rte_eth_dev *dev, 10741 struct rte_eth_mirror_conf *mirror_conf, 10742 uint8_t sw_id, uint8_t on) 10743 { 10744 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10746 struct i40e_mirror_rule *it, *mirr_rule = NULL; 10747 struct i40e_mirror_rule *parent = NULL; 10748 uint16_t seid, dst_seid, rule_id; 10749 uint16_t i, j = 0; 10750 int ret; 10751 10752 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id); 10753 10754 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) { 10755 PMD_DRV_LOG(ERR, 10756 "mirror rule can not be configured without veb or vfs."); 10757 return -ENOSYS; 10758 } 10759 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) { 10760 PMD_DRV_LOG(ERR, "mirror table is full."); 10761 return -ENOSPC; 10762 } 10763 if (mirror_conf->dst_pool > pf->vf_num) { 10764 PMD_DRV_LOG(ERR, "invalid destination pool %u.", 10765 mirror_conf->dst_pool); 10766 return -EINVAL; 10767 } 10768 10769 seid = pf->main_vsi->veb->seid; 10770 10771 TAILQ_FOREACH(it, &pf->mirror_list, rules) { 10772 if (sw_id <= it->index) { 10773 mirr_rule = it; 10774 break; 10775 } 10776 parent = it; 10777 } 10778 if (mirr_rule && sw_id == mirr_rule->index) { 10779 if (on) { 10780 PMD_DRV_LOG(ERR, "mirror rule exists."); 10781 return -EEXIST; 10782 } else { 10783 ret = i40e_aq_del_mirror_rule(hw, seid, 10784 mirr_rule->rule_type, 10785 mirr_rule->entries, 10786 mirr_rule->num_entries, mirr_rule->id); 10787 if (ret < 0) { 10788 PMD_DRV_LOG(ERR, 10789 "failed to remove mirror rule: ret = %d, aq_err = %d.", 10790 ret, hw->aq.asq_last_status); 10791 return -ENOSYS; 10792 } 10793 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules); 10794 rte_free(mirr_rule); 10795 pf->nb_mirror_rule--; 10796 return 0; 10797 } 10798 } else if (!on) { 10799 PMD_DRV_LOG(ERR, "mirror rule doesn't exist."); 10800 return -ENOENT; 10801 } 10802 10803 mirr_rule = rte_zmalloc("i40e_mirror_rule", 10804 sizeof(struct i40e_mirror_rule) , 0); 10805 if (!mirr_rule) { 10806 PMD_DRV_LOG(ERR, "failed to allocate memory"); 10807 return I40E_ERR_NO_MEMORY; 10808 } 10809 switch (mirror_conf->rule_type) { 10810 case ETH_MIRROR_VLAN: 10811 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) { 10812 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 10813 mirr_rule->entries[j] = 10814 mirror_conf->vlan.vlan_id[i]; 10815 j++; 10816 } 10817 } 10818 if (j == 0) { 10819 PMD_DRV_LOG(ERR, "vlan is not specified."); 10820 rte_free(mirr_rule); 10821 return -EINVAL; 10822 } 10823 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN; 10824 break; 10825 case ETH_MIRROR_VIRTUAL_POOL_UP: 10826 case ETH_MIRROR_VIRTUAL_POOL_DOWN: 10827 /* check if the specified pool bit is out of range */ 10828 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) { 10829 PMD_DRV_LOG(ERR, "pool mask is out of range."); 10830 rte_free(mirr_rule); 10831 return -EINVAL; 10832 } 10833 for (i = 0, j = 0; i < pf->vf_num; i++) { 10834 if (mirror_conf->pool_mask & (1ULL << i)) { 10835 mirr_rule->entries[j] = pf->vfs[i].vsi->seid; 10836 j++; 10837 } 10838 } 10839 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) { 10840 /* add pf vsi to entries */ 10841 mirr_rule->entries[j] = pf->main_vsi_seid; 10842 j++; 10843 } 10844 if (j == 0) { 10845 PMD_DRV_LOG(ERR, "pool is not specified."); 10846 rte_free(mirr_rule); 10847 return -EINVAL; 10848 } 10849 /* egress and ingress in aq commands means from switch but not port */ 10850 mirr_rule->rule_type = 10851 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ? 10852 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS : 10853 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS; 10854 break; 10855 case ETH_MIRROR_UPLINK_PORT: 10856 /* egress and ingress in aq commands means from switch but not port*/ 10857 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS; 10858 break; 10859 case ETH_MIRROR_DOWNLINK_PORT: 10860 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS; 10861 break; 10862 default: 10863 PMD_DRV_LOG(ERR, "unsupported mirror type %d.", 10864 mirror_conf->rule_type); 10865 rte_free(mirr_rule); 10866 return -EINVAL; 10867 } 10868 10869 /* If the dst_pool is equal to vf_num, consider it as PF */ 10870 if (mirror_conf->dst_pool == pf->vf_num) 10871 dst_seid = pf->main_vsi_seid; 10872 else 10873 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid; 10874 10875 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid, 10876 mirr_rule->rule_type, mirr_rule->entries, 10877 j, &rule_id); 10878 if (ret < 0) { 10879 PMD_DRV_LOG(ERR, 10880 "failed to add mirror rule: ret = %d, aq_err = %d.", 10881 ret, hw->aq.asq_last_status); 10882 rte_free(mirr_rule); 10883 return -ENOSYS; 10884 } 10885 10886 mirr_rule->index = sw_id; 10887 mirr_rule->num_entries = j; 10888 mirr_rule->id = rule_id; 10889 mirr_rule->dst_vsi_seid = dst_seid; 10890 10891 if (parent) 10892 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules); 10893 else 10894 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules); 10895 10896 pf->nb_mirror_rule++; 10897 return 0; 10898 } 10899 10900 /** 10901 * i40e_mirror_rule_reset 10902 * @dev: pointer to the device 10903 * @sw_id: mirror rule's sw_id 10904 * 10905 * reset a mirror rule. 10906 * 10907 **/ 10908 static int 10909 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id) 10910 { 10911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10913 struct i40e_mirror_rule *it, *mirr_rule = NULL; 10914 uint16_t seid; 10915 int ret; 10916 10917 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id); 10918 10919 seid = pf->main_vsi->veb->seid; 10920 10921 TAILQ_FOREACH(it, &pf->mirror_list, rules) { 10922 if (sw_id == it->index) { 10923 mirr_rule = it; 10924 break; 10925 } 10926 } 10927 if (mirr_rule) { 10928 ret = i40e_aq_del_mirror_rule(hw, seid, 10929 mirr_rule->rule_type, 10930 mirr_rule->entries, 10931 mirr_rule->num_entries, mirr_rule->id); 10932 if (ret < 0) { 10933 PMD_DRV_LOG(ERR, 10934 "failed to remove mirror rule: status = %d, aq_err = %d.", 10935 ret, hw->aq.asq_last_status); 10936 return -ENOSYS; 10937 } 10938 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules); 10939 rte_free(mirr_rule); 10940 pf->nb_mirror_rule--; 10941 } else { 10942 PMD_DRV_LOG(ERR, "mirror rule doesn't exist."); 10943 return -ENOENT; 10944 } 10945 return 0; 10946 } 10947 10948 static uint64_t 10949 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev) 10950 { 10951 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10952 uint64_t systim_cycles; 10953 10954 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L); 10955 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H) 10956 << 32; 10957 10958 return systim_cycles; 10959 } 10960 10961 static uint64_t 10962 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index) 10963 { 10964 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10965 uint64_t rx_tstamp; 10966 10967 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index)); 10968 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index)) 10969 << 32; 10970 10971 return rx_tstamp; 10972 } 10973 10974 static uint64_t 10975 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 10976 { 10977 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10978 uint64_t tx_tstamp; 10979 10980 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L); 10981 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H) 10982 << 32; 10983 10984 return tx_tstamp; 10985 } 10986 10987 static void 10988 i40e_start_timecounters(struct rte_eth_dev *dev) 10989 { 10990 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10991 struct i40e_adapter *adapter = dev->data->dev_private; 10992 struct rte_eth_link link; 10993 uint32_t tsync_inc_l; 10994 uint32_t tsync_inc_h; 10995 10996 /* Get current link speed. */ 10997 i40e_dev_link_update(dev, 1); 10998 rte_eth_linkstatus_get(dev, &link); 10999 11000 switch (link.link_speed) { 11001 case ETH_SPEED_NUM_40G: 11002 case ETH_SPEED_NUM_25G: 11003 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF; 11004 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32; 11005 break; 11006 case ETH_SPEED_NUM_10G: 11007 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF; 11008 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32; 11009 break; 11010 case ETH_SPEED_NUM_1G: 11011 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF; 11012 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32; 11013 break; 11014 default: 11015 tsync_inc_l = 0x0; 11016 tsync_inc_h = 0x0; 11017 } 11018 11019 /* Set the timesync increment value. */ 11020 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l); 11021 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h); 11022 11023 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 11024 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 11025 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 11026 11027 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 11028 adapter->systime_tc.cc_shift = 0; 11029 adapter->systime_tc.nsec_mask = 0; 11030 11031 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 11032 adapter->rx_tstamp_tc.cc_shift = 0; 11033 adapter->rx_tstamp_tc.nsec_mask = 0; 11034 11035 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 11036 adapter->tx_tstamp_tc.cc_shift = 0; 11037 adapter->tx_tstamp_tc.nsec_mask = 0; 11038 } 11039 11040 static int 11041 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 11042 { 11043 struct i40e_adapter *adapter = dev->data->dev_private; 11044 11045 adapter->systime_tc.nsec += delta; 11046 adapter->rx_tstamp_tc.nsec += delta; 11047 adapter->tx_tstamp_tc.nsec += delta; 11048 11049 return 0; 11050 } 11051 11052 static int 11053 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 11054 { 11055 uint64_t ns; 11056 struct i40e_adapter *adapter = dev->data->dev_private; 11057 11058 ns = rte_timespec_to_ns(ts); 11059 11060 /* Set the timecounters to a new value. */ 11061 adapter->systime_tc.nsec = ns; 11062 adapter->rx_tstamp_tc.nsec = ns; 11063 adapter->tx_tstamp_tc.nsec = ns; 11064 11065 return 0; 11066 } 11067 11068 static int 11069 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 11070 { 11071 uint64_t ns, systime_cycles; 11072 struct i40e_adapter *adapter = dev->data->dev_private; 11073 11074 systime_cycles = i40e_read_systime_cyclecounter(dev); 11075 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 11076 *ts = rte_ns_to_timespec(ns); 11077 11078 return 0; 11079 } 11080 11081 static int 11082 i40e_timesync_enable(struct rte_eth_dev *dev) 11083 { 11084 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11085 uint32_t tsync_ctl_l; 11086 uint32_t tsync_ctl_h; 11087 11088 /* Stop the timesync system time. */ 11089 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); 11090 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); 11091 /* Reset the timesync system time value. */ 11092 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0); 11093 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0); 11094 11095 i40e_start_timecounters(dev); 11096 11097 /* Clear timesync registers. */ 11098 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); 11099 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H); 11100 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0)); 11101 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1)); 11102 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2)); 11103 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3)); 11104 11105 /* Enable timestamping of PTP packets. */ 11106 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); 11107 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA; 11108 11109 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); 11110 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA; 11111 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE; 11112 11113 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); 11114 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); 11115 11116 return 0; 11117 } 11118 11119 static int 11120 i40e_timesync_disable(struct rte_eth_dev *dev) 11121 { 11122 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11123 uint32_t tsync_ctl_l; 11124 uint32_t tsync_ctl_h; 11125 11126 /* Disable timestamping of transmitted PTP packets. */ 11127 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); 11128 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA; 11129 11130 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); 11131 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA; 11132 11133 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); 11134 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); 11135 11136 /* Reset the timesync increment value. */ 11137 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); 11138 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); 11139 11140 return 0; 11141 } 11142 11143 static int 11144 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 11145 struct timespec *timestamp, uint32_t flags) 11146 { 11147 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11148 struct i40e_adapter *adapter = dev->data->dev_private; 11149 uint32_t sync_status; 11150 uint32_t index = flags & 0x03; 11151 uint64_t rx_tstamp_cycles; 11152 uint64_t ns; 11153 11154 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1); 11155 if ((sync_status & (1 << index)) == 0) 11156 return -EINVAL; 11157 11158 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index); 11159 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 11160 *timestamp = rte_ns_to_timespec(ns); 11161 11162 return 0; 11163 } 11164 11165 static int 11166 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 11167 struct timespec *timestamp) 11168 { 11169 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11170 struct i40e_adapter *adapter = dev->data->dev_private; 11171 uint32_t sync_status; 11172 uint64_t tx_tstamp_cycles; 11173 uint64_t ns; 11174 11175 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); 11176 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0) 11177 return -EINVAL; 11178 11179 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev); 11180 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 11181 *timestamp = rte_ns_to_timespec(ns); 11182 11183 return 0; 11184 } 11185 11186 /* 11187 * i40e_parse_dcb_configure - parse dcb configure from user 11188 * @dev: the device being configured 11189 * @dcb_cfg: pointer of the result of parse 11190 * @*tc_map: bit map of enabled traffic classes 11191 * 11192 * Returns 0 on success, negative value on failure 11193 */ 11194 static int 11195 i40e_parse_dcb_configure(struct rte_eth_dev *dev, 11196 struct i40e_dcbx_config *dcb_cfg, 11197 uint8_t *tc_map) 11198 { 11199 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 11200 uint8_t i, tc_bw, bw_lf; 11201 11202 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config)); 11203 11204 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 11205 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) { 11206 PMD_INIT_LOG(ERR, "number of tc exceeds max."); 11207 return -EINVAL; 11208 } 11209 11210 /* assume each tc has the same bw */ 11211 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs; 11212 for (i = 0; i < dcb_rx_conf->nb_tcs; i++) 11213 dcb_cfg->etscfg.tcbwtable[i] = tc_bw; 11214 /* to ensure the sum of tcbw is equal to 100 */ 11215 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs; 11216 for (i = 0; i < bw_lf; i++) 11217 dcb_cfg->etscfg.tcbwtable[i]++; 11218 11219 /* assume each tc has the same Transmission Selection Algorithm */ 11220 for (i = 0; i < dcb_rx_conf->nb_tcs; i++) 11221 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS; 11222 11223 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11224 dcb_cfg->etscfg.prioritytable[i] = 11225 dcb_rx_conf->dcb_tc[i]; 11226 11227 /* FW needs one App to configure HW */ 11228 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM; 11229 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE; 11230 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO; 11231 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE; 11232 11233 if (dcb_rx_conf->nb_tcs == 0) 11234 *tc_map = 1; /* tc0 only */ 11235 else 11236 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t); 11237 11238 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) { 11239 dcb_cfg->pfc.willing = 0; 11240 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; 11241 dcb_cfg->pfc.pfcenable = *tc_map; 11242 } 11243 return 0; 11244 } 11245 11246 11247 static enum i40e_status_code 11248 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi, 11249 struct i40e_aqc_vsi_properties_data *info, 11250 uint8_t enabled_tcmap) 11251 { 11252 enum i40e_status_code ret; 11253 int i, total_tc = 0; 11254 uint16_t qpnum_per_tc, bsf, qp_idx; 11255 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi); 11256 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 11257 uint16_t used_queues; 11258 11259 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 11260 if (ret != I40E_SUCCESS) 11261 return ret; 11262 11263 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11264 if (enabled_tcmap & (1 << i)) 11265 total_tc++; 11266 } 11267 if (total_tc == 0) 11268 total_tc = 1; 11269 vsi->enabled_tc = enabled_tcmap; 11270 11271 /* different VSI has different queues assigned */ 11272 if (vsi->type == I40E_VSI_MAIN) 11273 used_queues = dev_data->nb_rx_queues - 11274 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 11275 else if (vsi->type == I40E_VSI_VMDQ2) 11276 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 11277 else { 11278 PMD_INIT_LOG(ERR, "unsupported VSI type."); 11279 return I40E_ERR_NO_AVAILABLE_VSI; 11280 } 11281 11282 qpnum_per_tc = used_queues / total_tc; 11283 /* Number of queues per enabled TC */ 11284 if (qpnum_per_tc == 0) { 11285 PMD_INIT_LOG(ERR, " number of queues is less that tcs."); 11286 return I40E_ERR_INVALID_QP_ID; 11287 } 11288 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc), 11289 I40E_MAX_Q_PER_TC); 11290 bsf = rte_bsf32(qpnum_per_tc); 11291 11292 /** 11293 * Configure TC and queue mapping parameters, for enabled TC, 11294 * allocate qpnum_per_tc queues to this traffic. For disabled TC, 11295 * default queue will serve it. 11296 */ 11297 qp_idx = 0; 11298 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11299 if (vsi->enabled_tc & (1 << i)) { 11300 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx << 11301 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 11302 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 11303 qp_idx += qpnum_per_tc; 11304 } else 11305 info->tc_mapping[i] = 0; 11306 } 11307 11308 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */ 11309 if (vsi->type == I40E_VSI_SRIOV) { 11310 info->mapping_flags |= 11311 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 11312 for (i = 0; i < vsi->nb_qps; i++) 11313 info->queue_mapping[i] = 11314 rte_cpu_to_le_16(vsi->base_queue + i); 11315 } else { 11316 info->mapping_flags |= 11317 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG); 11318 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 11319 } 11320 info->valid_sections |= 11321 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 11322 11323 return I40E_SUCCESS; 11324 } 11325 11326 /* 11327 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map 11328 * @veb: VEB to be configured 11329 * @tc_map: enabled TC bitmap 11330 * 11331 * Returns 0 on success, negative value on failure 11332 */ 11333 static enum i40e_status_code 11334 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map) 11335 { 11336 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw; 11337 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query; 11338 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query; 11339 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi); 11340 enum i40e_status_code ret = I40E_SUCCESS; 11341 int i; 11342 uint32_t bw_max; 11343 11344 /* Check if enabled_tc is same as existing or new TCs */ 11345 if (veb->enabled_tc == tc_map) 11346 return ret; 11347 11348 /* configure tc bandwidth */ 11349 memset(&veb_bw, 0, sizeof(veb_bw)); 11350 veb_bw.tc_valid_bits = tc_map; 11351 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 11352 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11353 if (tc_map & BIT_ULL(i)) 11354 veb_bw.tc_bw_share_credits[i] = 1; 11355 } 11356 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid, 11357 &veb_bw, NULL); 11358 if (ret) { 11359 PMD_INIT_LOG(ERR, 11360 "AQ command Config switch_comp BW allocation per TC failed = %d", 11361 hw->aq.asq_last_status); 11362 return ret; 11363 } 11364 11365 memset(&ets_query, 0, sizeof(ets_query)); 11366 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, 11367 &ets_query, NULL); 11368 if (ret != I40E_SUCCESS) { 11369 PMD_DRV_LOG(ERR, 11370 "Failed to get switch_comp ETS configuration %u", 11371 hw->aq.asq_last_status); 11372 return ret; 11373 } 11374 memset(&bw_query, 0, sizeof(bw_query)); 11375 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, 11376 &bw_query, NULL); 11377 if (ret != I40E_SUCCESS) { 11378 PMD_DRV_LOG(ERR, 11379 "Failed to get switch_comp bandwidth configuration %u", 11380 hw->aq.asq_last_status); 11381 return ret; 11382 } 11383 11384 /* store and print out BW info */ 11385 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit); 11386 veb->bw_info.bw_max = ets_query.tc_bw_max; 11387 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit); 11388 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max); 11389 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) | 11390 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) << 11391 I40E_16_BIT_WIDTH); 11392 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11393 veb->bw_info.bw_ets_share_credits[i] = 11394 bw_query.tc_bw_share_credits[i]; 11395 veb->bw_info.bw_ets_credits[i] = 11396 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]); 11397 /* 4 bits per TC, 4th bit is reserved */ 11398 veb->bw_info.bw_ets_max[i] = 11399 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) & 11400 RTE_LEN2MASK(3, uint8_t)); 11401 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i, 11402 veb->bw_info.bw_ets_share_credits[i]); 11403 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i, 11404 veb->bw_info.bw_ets_credits[i]); 11405 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i, 11406 veb->bw_info.bw_ets_max[i]); 11407 } 11408 11409 veb->enabled_tc = tc_map; 11410 11411 return ret; 11412 } 11413 11414 11415 /* 11416 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map 11417 * @vsi: VSI to be configured 11418 * @tc_map: enabled TC bitmap 11419 * 11420 * Returns 0 on success, negative value on failure 11421 */ 11422 static enum i40e_status_code 11423 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map) 11424 { 11425 struct i40e_aqc_configure_vsi_tc_bw_data bw_data; 11426 struct i40e_vsi_context ctxt; 11427 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 11428 enum i40e_status_code ret = I40E_SUCCESS; 11429 int i; 11430 11431 /* Check if enabled_tc is same as existing or new TCs */ 11432 if (vsi->enabled_tc == tc_map) 11433 return ret; 11434 11435 /* configure tc bandwidth */ 11436 memset(&bw_data, 0, sizeof(bw_data)); 11437 bw_data.tc_valid_bits = tc_map; 11438 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 11439 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11440 if (tc_map & BIT_ULL(i)) 11441 bw_data.tc_bw_credits[i] = 1; 11442 } 11443 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL); 11444 if (ret) { 11445 PMD_INIT_LOG(ERR, 11446 "AQ command Config VSI BW allocation per TC failed = %d", 11447 hw->aq.asq_last_status); 11448 goto out; 11449 } 11450 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 11451 vsi->info.qs_handle[i] = bw_data.qs_handles[i]; 11452 11453 /* Update Queue Pairs Mapping for currently enabled UPs */ 11454 ctxt.seid = vsi->seid; 11455 ctxt.pf_num = hw->pf_id; 11456 ctxt.vf_num = 0; 11457 ctxt.uplink_seid = vsi->uplink_seid; 11458 ctxt.info = vsi->info; 11459 i40e_get_cap(hw); 11460 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map); 11461 if (ret) 11462 goto out; 11463 11464 /* Update the VSI after updating the VSI queue-mapping information */ 11465 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 11466 if (ret) { 11467 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d", 11468 hw->aq.asq_last_status); 11469 goto out; 11470 } 11471 /* update the local VSI info with updated queue map */ 11472 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping, 11473 sizeof(vsi->info.tc_mapping)); 11474 rte_memcpy(&vsi->info.queue_mapping, 11475 &ctxt.info.queue_mapping, 11476 sizeof(vsi->info.queue_mapping)); 11477 vsi->info.mapping_flags = ctxt.info.mapping_flags; 11478 vsi->info.valid_sections = 0; 11479 11480 /* query and update current VSI BW information */ 11481 ret = i40e_vsi_get_bw_config(vsi); 11482 if (ret) { 11483 PMD_INIT_LOG(ERR, 11484 "Failed updating vsi bw info, err %s aq_err %s", 11485 i40e_stat_str(hw, ret), 11486 i40e_aq_str(hw, hw->aq.asq_last_status)); 11487 goto out; 11488 } 11489 11490 vsi->enabled_tc = tc_map; 11491 11492 out: 11493 return ret; 11494 } 11495 11496 /* 11497 * i40e_dcb_hw_configure - program the dcb setting to hw 11498 * @pf: pf the configuration is taken on 11499 * @new_cfg: new configuration 11500 * @tc_map: enabled TC bitmap 11501 * 11502 * Returns 0 on success, negative value on failure 11503 */ 11504 static enum i40e_status_code 11505 i40e_dcb_hw_configure(struct i40e_pf *pf, 11506 struct i40e_dcbx_config *new_cfg, 11507 uint8_t tc_map) 11508 { 11509 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 11510 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config; 11511 struct i40e_vsi *main_vsi = pf->main_vsi; 11512 struct i40e_vsi_list *vsi_list; 11513 enum i40e_status_code ret; 11514 int i; 11515 uint32_t val; 11516 11517 /* Use the FW API if FW > v4.4*/ 11518 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) || 11519 (hw->aq.fw_maj_ver >= 5))) { 11520 PMD_INIT_LOG(ERR, 11521 "FW < v4.4, can not use FW LLDP API to configure DCB"); 11522 return I40E_ERR_FIRMWARE_API_VERSION; 11523 } 11524 11525 /* Check if need reconfiguration */ 11526 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) { 11527 PMD_INIT_LOG(ERR, "No Change in DCB Config required."); 11528 return I40E_SUCCESS; 11529 } 11530 11531 /* Copy the new config to the current config */ 11532 *old_cfg = *new_cfg; 11533 old_cfg->etsrec = old_cfg->etscfg; 11534 ret = i40e_set_dcb_config(hw); 11535 if (ret) { 11536 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s", 11537 i40e_stat_str(hw, ret), 11538 i40e_aq_str(hw, hw->aq.asq_last_status)); 11539 return ret; 11540 } 11541 /* set receive Arbiter to RR mode and ETS scheme by default */ 11542 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) { 11543 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i)); 11544 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK | 11545 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK | 11546 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT); 11547 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] << 11548 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) & 11549 I40E_PRTDCB_RETSTCC_BWSHARE_MASK; 11550 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) & 11551 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK; 11552 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) & 11553 I40E_PRTDCB_RETSTCC_ETSTC_MASK; 11554 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val); 11555 } 11556 /* get local mib to check whether it is configured correctly */ 11557 /* IEEE mode */ 11558 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE; 11559 /* Get Local DCB Config */ 11560 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0, 11561 &hw->local_dcbx_config); 11562 11563 /* if Veb is created, need to update TC of it at first */ 11564 if (main_vsi->veb) { 11565 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map); 11566 if (ret) 11567 PMD_INIT_LOG(WARNING, 11568 "Failed configuring TC for VEB seid=%d", 11569 main_vsi->veb->seid); 11570 } 11571 /* Update each VSI */ 11572 i40e_vsi_config_tc(main_vsi, tc_map); 11573 if (main_vsi->veb) { 11574 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) { 11575 /* Beside main VSI and VMDQ VSIs, only enable default 11576 * TC for other VSIs 11577 */ 11578 if (vsi_list->vsi->type == I40E_VSI_VMDQ2) 11579 ret = i40e_vsi_config_tc(vsi_list->vsi, 11580 tc_map); 11581 else 11582 ret = i40e_vsi_config_tc(vsi_list->vsi, 11583 I40E_DEFAULT_TCMAP); 11584 if (ret) 11585 PMD_INIT_LOG(WARNING, 11586 "Failed configuring TC for VSI seid=%d", 11587 vsi_list->vsi->seid); 11588 /* continue */ 11589 } 11590 } 11591 return I40E_SUCCESS; 11592 } 11593 11594 /* 11595 * i40e_dcb_init_configure - initial dcb config 11596 * @dev: device being configured 11597 * @sw_dcb: indicate whether dcb is sw configured or hw offload 11598 * 11599 * Returns 0 on success, negative value on failure 11600 */ 11601 int 11602 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb) 11603 { 11604 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11605 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11606 int i, ret = 0; 11607 11608 if ((pf->flags & I40E_FLAG_DCB) == 0) { 11609 PMD_INIT_LOG(ERR, "HW doesn't support DCB"); 11610 return -ENOTSUP; 11611 } 11612 11613 /* DCB initialization: 11614 * Update DCB configuration from the Firmware and configure 11615 * LLDP MIB change event. 11616 */ 11617 if (sw_dcb == TRUE) { 11618 /* Stopping lldp is necessary for DPDK, but it will cause 11619 * DCB init failed. For i40e_init_dcb(), the prerequisite 11620 * for successful initialization of DCB is that LLDP is 11621 * enabled. So it is needed to start lldp before DCB init 11622 * and stop it after initialization. 11623 */ 11624 ret = i40e_aq_start_lldp(hw, true, NULL); 11625 if (ret != I40E_SUCCESS) 11626 PMD_INIT_LOG(DEBUG, "Failed to start lldp"); 11627 11628 ret = i40e_init_dcb(hw, true); 11629 /* If lldp agent is stopped, the return value from 11630 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM 11631 * adminq status. Otherwise, it should return success. 11632 */ 11633 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS && 11634 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) { 11635 memset(&hw->local_dcbx_config, 0, 11636 sizeof(struct i40e_dcbx_config)); 11637 /* set dcb default configuration */ 11638 hw->local_dcbx_config.etscfg.willing = 0; 11639 hw->local_dcbx_config.etscfg.maxtcs = 0; 11640 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100; 11641 hw->local_dcbx_config.etscfg.tsatable[0] = 11642 I40E_IEEE_TSA_ETS; 11643 /* all UPs mapping to TC0 */ 11644 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11645 hw->local_dcbx_config.etscfg.prioritytable[i] = 0; 11646 hw->local_dcbx_config.etsrec = 11647 hw->local_dcbx_config.etscfg; 11648 hw->local_dcbx_config.pfc.willing = 0; 11649 hw->local_dcbx_config.pfc.pfccap = 11650 I40E_MAX_TRAFFIC_CLASS; 11651 /* FW needs one App to configure HW */ 11652 hw->local_dcbx_config.numapps = 1; 11653 hw->local_dcbx_config.app[0].selector = 11654 I40E_APP_SEL_ETHTYPE; 11655 hw->local_dcbx_config.app[0].priority = 3; 11656 hw->local_dcbx_config.app[0].protocolid = 11657 I40E_APP_PROTOID_FCOE; 11658 ret = i40e_set_dcb_config(hw); 11659 if (ret) { 11660 PMD_INIT_LOG(ERR, 11661 "default dcb config fails. err = %d, aq_err = %d.", 11662 ret, hw->aq.asq_last_status); 11663 return -ENOSYS; 11664 } 11665 } else { 11666 PMD_INIT_LOG(ERR, 11667 "DCB initialization in FW fails, err = %d, aq_err = %d.", 11668 ret, hw->aq.asq_last_status); 11669 return -ENOTSUP; 11670 } 11671 11672 if (i40e_need_stop_lldp(dev)) { 11673 ret = i40e_aq_stop_lldp(hw, true, true, NULL); 11674 if (ret != I40E_SUCCESS) 11675 PMD_INIT_LOG(DEBUG, "Failed to stop lldp"); 11676 } 11677 } else { 11678 ret = i40e_aq_start_lldp(hw, true, NULL); 11679 if (ret != I40E_SUCCESS) 11680 PMD_INIT_LOG(DEBUG, "Failed to start lldp"); 11681 11682 ret = i40e_init_dcb(hw, true); 11683 if (!ret) { 11684 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) { 11685 PMD_INIT_LOG(ERR, 11686 "HW doesn't support DCBX offload."); 11687 return -ENOTSUP; 11688 } 11689 } else { 11690 PMD_INIT_LOG(ERR, 11691 "DCBX configuration failed, err = %d, aq_err = %d.", 11692 ret, hw->aq.asq_last_status); 11693 return -ENOTSUP; 11694 } 11695 } 11696 return 0; 11697 } 11698 11699 /* 11700 * i40e_dcb_setup - setup dcb related config 11701 * @dev: device being configured 11702 * 11703 * Returns 0 on success, negative value on failure 11704 */ 11705 static int 11706 i40e_dcb_setup(struct rte_eth_dev *dev) 11707 { 11708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11709 struct i40e_dcbx_config dcb_cfg; 11710 uint8_t tc_map = 0; 11711 int ret = 0; 11712 11713 if ((pf->flags & I40E_FLAG_DCB) == 0) { 11714 PMD_INIT_LOG(ERR, "HW doesn't support DCB"); 11715 return -ENOTSUP; 11716 } 11717 11718 if (pf->vf_num != 0) 11719 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis."); 11720 11721 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map); 11722 if (ret) { 11723 PMD_INIT_LOG(ERR, "invalid dcb config"); 11724 return -EINVAL; 11725 } 11726 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map); 11727 if (ret) { 11728 PMD_INIT_LOG(ERR, "dcb sw configure fails"); 11729 return -ENOSYS; 11730 } 11731 11732 return 0; 11733 } 11734 11735 static int 11736 i40e_dev_get_dcb_info(struct rte_eth_dev *dev, 11737 struct rte_eth_dcb_info *dcb_info) 11738 { 11739 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11740 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11741 struct i40e_vsi *vsi = pf->main_vsi; 11742 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config; 11743 uint16_t bsf, tc_mapping; 11744 int i, j = 0; 11745 11746 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 11747 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1); 11748 else 11749 dcb_info->nb_tcs = 1; 11750 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11751 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i]; 11752 for (i = 0; i < dcb_info->nb_tcs; i++) 11753 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i]; 11754 11755 /* get queue mapping if vmdq is disabled */ 11756 if (!pf->nb_cfg_vmdq_vsi) { 11757 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11758 if (!(vsi->enabled_tc & (1 << i))) 11759 continue; 11760 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]); 11761 dcb_info->tc_queue.tc_rxq[j][i].base = 11762 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >> 11763 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT; 11764 dcb_info->tc_queue.tc_txq[j][i].base = 11765 dcb_info->tc_queue.tc_rxq[j][i].base; 11766 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >> 11767 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT; 11768 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf; 11769 dcb_info->tc_queue.tc_txq[j][i].nb_queue = 11770 dcb_info->tc_queue.tc_rxq[j][i].nb_queue; 11771 } 11772 return 0; 11773 } 11774 11775 /* get queue mapping if vmdq is enabled */ 11776 do { 11777 vsi = pf->vmdq[j].vsi; 11778 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11779 if (!(vsi->enabled_tc & (1 << i))) 11780 continue; 11781 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]); 11782 dcb_info->tc_queue.tc_rxq[j][i].base = 11783 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >> 11784 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT; 11785 dcb_info->tc_queue.tc_txq[j][i].base = 11786 dcb_info->tc_queue.tc_rxq[j][i].base; 11787 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >> 11788 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT; 11789 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf; 11790 dcb_info->tc_queue.tc_txq[j][i].nb_queue = 11791 dcb_info->tc_queue.tc_rxq[j][i].nb_queue; 11792 } 11793 j++; 11794 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL)); 11795 return 0; 11796 } 11797 11798 static int 11799 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 11800 { 11801 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 11802 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 11803 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11804 uint16_t msix_intr; 11805 11806 msix_intr = intr_handle->intr_vec[queue_id]; 11807 if (msix_intr == I40E_MISC_VEC_ID) 11808 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 11809 I40E_PFINT_DYN_CTL0_INTENA_MASK | 11810 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 11811 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 11812 else 11813 I40E_WRITE_REG(hw, 11814 I40E_PFINT_DYN_CTLN(msix_intr - 11815 I40E_RX_VEC_START), 11816 I40E_PFINT_DYN_CTLN_INTENA_MASK | 11817 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 11818 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 11819 11820 I40E_WRITE_FLUSH(hw); 11821 rte_intr_ack(&pci_dev->intr_handle); 11822 11823 return 0; 11824 } 11825 11826 static int 11827 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 11828 { 11829 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 11830 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 11831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11832 uint16_t msix_intr; 11833 11834 msix_intr = intr_handle->intr_vec[queue_id]; 11835 if (msix_intr == I40E_MISC_VEC_ID) 11836 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 11837 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 11838 else 11839 I40E_WRITE_REG(hw, 11840 I40E_PFINT_DYN_CTLN(msix_intr - 11841 I40E_RX_VEC_START), 11842 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 11843 I40E_WRITE_FLUSH(hw); 11844 11845 return 0; 11846 } 11847 11848 /** 11849 * This function is used to check if the register is valid. 11850 * Below is the valid registers list for X722 only: 11851 * 0x2b800--0x2bb00 11852 * 0x38700--0x38a00 11853 * 0x3d800--0x3db00 11854 * 0x208e00--0x209000 11855 * 0x20be00--0x20c000 11856 * 0x263c00--0x264000 11857 * 0x265c00--0x266000 11858 */ 11859 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset) 11860 { 11861 if ((type != I40E_MAC_X722) && 11862 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) || 11863 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) || 11864 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) || 11865 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) || 11866 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) || 11867 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) || 11868 (reg_offset >= 0x265c00 && reg_offset <= 0x266000))) 11869 return 0; 11870 else 11871 return 1; 11872 } 11873 11874 static int i40e_get_regs(struct rte_eth_dev *dev, 11875 struct rte_dev_reg_info *regs) 11876 { 11877 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11878 uint32_t *ptr_data = regs->data; 11879 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset; 11880 const struct i40e_reg_info *reg_info; 11881 11882 if (ptr_data == NULL) { 11883 regs->length = I40E_GLGEN_STAT_CLEAR + 4; 11884 regs->width = sizeof(uint32_t); 11885 return 0; 11886 } 11887 11888 /* The first few registers have to be read using AQ operations */ 11889 reg_idx = 0; 11890 while (i40e_regs_adminq[reg_idx].name) { 11891 reg_info = &i40e_regs_adminq[reg_idx++]; 11892 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++) 11893 for (arr_idx2 = 0; 11894 arr_idx2 <= reg_info->count2; 11895 arr_idx2++) { 11896 reg_offset = arr_idx * reg_info->stride1 + 11897 arr_idx2 * reg_info->stride2; 11898 reg_offset += reg_info->base_addr; 11899 ptr_data[reg_offset >> 2] = 11900 i40e_read_rx_ctl(hw, reg_offset); 11901 } 11902 } 11903 11904 /* The remaining registers can be read using primitives */ 11905 reg_idx = 0; 11906 while (i40e_regs_others[reg_idx].name) { 11907 reg_info = &i40e_regs_others[reg_idx++]; 11908 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++) 11909 for (arr_idx2 = 0; 11910 arr_idx2 <= reg_info->count2; 11911 arr_idx2++) { 11912 reg_offset = arr_idx * reg_info->stride1 + 11913 arr_idx2 * reg_info->stride2; 11914 reg_offset += reg_info->base_addr; 11915 if (!i40e_valid_regs(hw->mac.type, reg_offset)) 11916 ptr_data[reg_offset >> 2] = 0; 11917 else 11918 ptr_data[reg_offset >> 2] = 11919 I40E_READ_REG(hw, reg_offset); 11920 } 11921 } 11922 11923 return 0; 11924 } 11925 11926 static int i40e_get_eeprom_length(struct rte_eth_dev *dev) 11927 { 11928 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11929 11930 /* Convert word count to byte count */ 11931 return hw->nvm.sr_size << 1; 11932 } 11933 11934 static int i40e_get_eeprom(struct rte_eth_dev *dev, 11935 struct rte_dev_eeprom_info *eeprom) 11936 { 11937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11938 uint16_t *data = eeprom->data; 11939 uint16_t offset, length, cnt_words; 11940 int ret_code; 11941 11942 offset = eeprom->offset >> 1; 11943 length = eeprom->length >> 1; 11944 cnt_words = length; 11945 11946 if (offset > hw->nvm.sr_size || 11947 offset + length > hw->nvm.sr_size) { 11948 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 11949 return -EINVAL; 11950 } 11951 11952 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 11953 11954 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data); 11955 if (ret_code != I40E_SUCCESS || cnt_words != length) { 11956 PMD_DRV_LOG(ERR, "EEPROM read failed."); 11957 return -EIO; 11958 } 11959 11960 return 0; 11961 } 11962 11963 static int i40e_get_module_info(struct rte_eth_dev *dev, 11964 struct rte_eth_dev_module_info *modinfo) 11965 { 11966 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11967 uint32_t sff8472_comp = 0; 11968 uint32_t sff8472_swap = 0; 11969 uint32_t sff8636_rev = 0; 11970 i40e_status status; 11971 uint32_t type = 0; 11972 11973 /* Check if firmware supports reading module EEPROM. */ 11974 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) { 11975 PMD_DRV_LOG(ERR, 11976 "Module EEPROM memory read not supported. " 11977 "Please update the NVM image.\n"); 11978 return -EINVAL; 11979 } 11980 11981 status = i40e_update_link_info(hw); 11982 if (status) 11983 return -EIO; 11984 11985 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) { 11986 PMD_DRV_LOG(ERR, 11987 "Cannot read module EEPROM memory. " 11988 "No module connected.\n"); 11989 return -EINVAL; 11990 } 11991 11992 type = hw->phy.link_info.module_type[0]; 11993 11994 switch (type) { 11995 case I40E_MODULE_TYPE_SFP: 11996 status = i40e_aq_get_phy_register(hw, 11997 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11998 I40E_I2C_EEPROM_DEV_ADDR, 1, 11999 I40E_MODULE_SFF_8472_COMP, 12000 &sff8472_comp, NULL); 12001 if (status) 12002 return -EIO; 12003 12004 status = i40e_aq_get_phy_register(hw, 12005 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 12006 I40E_I2C_EEPROM_DEV_ADDR, 1, 12007 I40E_MODULE_SFF_8472_SWAP, 12008 &sff8472_swap, NULL); 12009 if (status) 12010 return -EIO; 12011 12012 /* Check if the module requires address swap to access 12013 * the other EEPROM memory page. 12014 */ 12015 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) { 12016 PMD_DRV_LOG(WARNING, 12017 "Module address swap to access " 12018 "page 0xA2 is not supported.\n"); 12019 modinfo->type = RTE_ETH_MODULE_SFF_8079; 12020 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 12021 } else if (sff8472_comp == 0x00) { 12022 /* Module is not SFF-8472 compliant */ 12023 modinfo->type = RTE_ETH_MODULE_SFF_8079; 12024 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 12025 } else { 12026 modinfo->type = RTE_ETH_MODULE_SFF_8472; 12027 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 12028 } 12029 break; 12030 case I40E_MODULE_TYPE_QSFP_PLUS: 12031 /* Read from memory page 0. */ 12032 status = i40e_aq_get_phy_register(hw, 12033 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 12034 0, 1, 12035 I40E_MODULE_REVISION_ADDR, 12036 &sff8636_rev, NULL); 12037 if (status) 12038 return -EIO; 12039 /* Determine revision compliance byte */ 12040 if (sff8636_rev > 0x02) { 12041 /* Module is SFF-8636 compliant */ 12042 modinfo->type = RTE_ETH_MODULE_SFF_8636; 12043 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 12044 } else { 12045 modinfo->type = RTE_ETH_MODULE_SFF_8436; 12046 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 12047 } 12048 break; 12049 case I40E_MODULE_TYPE_QSFP28: 12050 modinfo->type = RTE_ETH_MODULE_SFF_8636; 12051 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 12052 break; 12053 default: 12054 PMD_DRV_LOG(ERR, "Module type unrecognized\n"); 12055 return -EINVAL; 12056 } 12057 return 0; 12058 } 12059 12060 static int i40e_get_module_eeprom(struct rte_eth_dev *dev, 12061 struct rte_dev_eeprom_info *info) 12062 { 12063 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 12064 bool is_sfp = false; 12065 i40e_status status; 12066 uint8_t *data; 12067 uint32_t value = 0; 12068 uint32_t i; 12069 12070 if (!info || !info->length || !info->data) 12071 return -EINVAL; 12072 12073 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP) 12074 is_sfp = true; 12075 12076 data = info->data; 12077 for (i = 0; i < info->length; i++) { 12078 u32 offset = i + info->offset; 12079 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0; 12080 12081 /* Check if we need to access the other memory page */ 12082 if (is_sfp) { 12083 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) { 12084 offset -= RTE_ETH_MODULE_SFF_8079_LEN; 12085 addr = I40E_I2C_EEPROM_DEV_ADDR2; 12086 } 12087 } else { 12088 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) { 12089 /* Compute memory page number and offset. */ 12090 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2; 12091 addr++; 12092 } 12093 } 12094 status = i40e_aq_get_phy_register(hw, 12095 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 12096 addr, offset, 1, &value, NULL); 12097 if (status) 12098 return -EIO; 12099 data[i] = (uint8_t)value; 12100 } 12101 return 0; 12102 } 12103 12104 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, 12105 struct rte_ether_addr *mac_addr) 12106 { 12107 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 12108 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12109 struct i40e_vsi *vsi = pf->main_vsi; 12110 struct i40e_mac_filter_info mac_filter; 12111 struct i40e_mac_filter *f; 12112 int ret; 12113 12114 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 12115 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 12116 return -EINVAL; 12117 } 12118 12119 TAILQ_FOREACH(f, &vsi->mac_list, next) { 12120 if (rte_is_same_ether_addr(&pf->dev_addr, 12121 &f->mac_info.mac_addr)) 12122 break; 12123 } 12124 12125 if (f == NULL) { 12126 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 12127 return -EIO; 12128 } 12129 12130 mac_filter = f->mac_info; 12131 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr); 12132 if (ret != I40E_SUCCESS) { 12133 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 12134 return -EIO; 12135 } 12136 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN); 12137 ret = i40e_vsi_add_mac(vsi, &mac_filter); 12138 if (ret != I40E_SUCCESS) { 12139 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 12140 return -EIO; 12141 } 12142 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN); 12143 12144 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL, 12145 mac_addr->addr_bytes, NULL); 12146 if (ret != I40E_SUCCESS) { 12147 PMD_DRV_LOG(ERR, "Failed to change mac"); 12148 return -EIO; 12149 } 12150 12151 return 0; 12152 } 12153 12154 static int 12155 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 12156 { 12157 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12158 struct rte_eth_dev_data *dev_data = pf->dev_data; 12159 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD; 12160 int ret = 0; 12161 12162 /* check if mtu is within the allowed range */ 12163 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX) 12164 return -EINVAL; 12165 12166 /* mtu setting is forbidden if port is start */ 12167 if (dev_data->dev_started) { 12168 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 12169 dev_data->port_id); 12170 return -EBUSY; 12171 } 12172 12173 if (frame_size > RTE_ETHER_MAX_LEN) 12174 dev_data->dev_conf.rxmode.offloads |= 12175 DEV_RX_OFFLOAD_JUMBO_FRAME; 12176 else 12177 dev_data->dev_conf.rxmode.offloads &= 12178 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 12179 12180 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 12181 12182 return ret; 12183 } 12184 12185 /* Restore ethertype filter */ 12186 static void 12187 i40e_ethertype_filter_restore(struct i40e_pf *pf) 12188 { 12189 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12190 struct i40e_ethertype_filter_list 12191 *ethertype_list = &pf->ethertype.ethertype_list; 12192 struct i40e_ethertype_filter *f; 12193 struct i40e_control_filter_stats stats; 12194 uint16_t flags; 12195 12196 TAILQ_FOREACH(f, ethertype_list, rules) { 12197 flags = 0; 12198 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC)) 12199 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 12200 if (f->flags & RTE_ETHTYPE_FLAGS_DROP) 12201 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 12202 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 12203 12204 memset(&stats, 0, sizeof(stats)); 12205 i40e_aq_add_rem_control_packet_filter(hw, 12206 f->input.mac_addr.addr_bytes, 12207 f->input.ether_type, 12208 flags, pf->main_vsi->seid, 12209 f->queue, 1, &stats, NULL); 12210 } 12211 PMD_DRV_LOG(INFO, "Ethertype filter:" 12212 " mac_etype_used = %u, etype_used = %u," 12213 " mac_etype_free = %u, etype_free = %u", 12214 stats.mac_etype_used, stats.etype_used, 12215 stats.mac_etype_free, stats.etype_free); 12216 } 12217 12218 /* Restore tunnel filter */ 12219 static void 12220 i40e_tunnel_filter_restore(struct i40e_pf *pf) 12221 { 12222 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12223 struct i40e_vsi *vsi; 12224 struct i40e_pf_vf *vf; 12225 struct i40e_tunnel_filter_list 12226 *tunnel_list = &pf->tunnel.tunnel_list; 12227 struct i40e_tunnel_filter *f; 12228 struct i40e_aqc_cloud_filters_element_bb cld_filter; 12229 bool big_buffer = 0; 12230 12231 TAILQ_FOREACH(f, tunnel_list, rules) { 12232 if (!f->is_to_vf) 12233 vsi = pf->main_vsi; 12234 else { 12235 vf = &pf->vfs[f->vf_id]; 12236 vsi = vf->vsi; 12237 } 12238 memset(&cld_filter, 0, sizeof(cld_filter)); 12239 rte_ether_addr_copy((struct rte_ether_addr *) 12240 &f->input.outer_mac, 12241 (struct rte_ether_addr *)&cld_filter.element.outer_mac); 12242 rte_ether_addr_copy((struct rte_ether_addr *) 12243 &f->input.inner_mac, 12244 (struct rte_ether_addr *)&cld_filter.element.inner_mac); 12245 cld_filter.element.inner_vlan = f->input.inner_vlan; 12246 cld_filter.element.flags = f->input.flags; 12247 cld_filter.element.tenant_id = f->input.tenant_id; 12248 cld_filter.element.queue_number = f->queue; 12249 rte_memcpy(cld_filter.general_fields, 12250 f->input.general_fields, 12251 sizeof(f->input.general_fields)); 12252 12253 if (((f->input.flags & 12254 I40E_AQC_ADD_CLOUD_FILTER_0X11) == 12255 I40E_AQC_ADD_CLOUD_FILTER_0X11) || 12256 ((f->input.flags & 12257 I40E_AQC_ADD_CLOUD_FILTER_0X12) == 12258 I40E_AQC_ADD_CLOUD_FILTER_0X12) || 12259 ((f->input.flags & 12260 I40E_AQC_ADD_CLOUD_FILTER_0X10) == 12261 I40E_AQC_ADD_CLOUD_FILTER_0X10)) 12262 big_buffer = 1; 12263 12264 if (big_buffer) 12265 i40e_aq_add_cloud_filters_bb(hw, 12266 vsi->seid, &cld_filter, 1); 12267 else 12268 i40e_aq_add_cloud_filters(hw, vsi->seid, 12269 &cld_filter.element, 1); 12270 } 12271 } 12272 12273 /* Restore RSS filter */ 12274 static inline void 12275 i40e_rss_filter_restore(struct i40e_pf *pf) 12276 { 12277 struct i40e_rss_conf_list *list = &pf->rss_config_list; 12278 struct i40e_rss_filter *filter; 12279 12280 TAILQ_FOREACH(filter, list, next) { 12281 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE); 12282 } 12283 } 12284 12285 static void 12286 i40e_filter_restore(struct i40e_pf *pf) 12287 { 12288 i40e_ethertype_filter_restore(pf); 12289 i40e_tunnel_filter_restore(pf); 12290 i40e_fdir_filter_restore(pf); 12291 i40e_rss_filter_restore(pf); 12292 } 12293 12294 bool 12295 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 12296 { 12297 if (strcmp(dev->device->driver->name, drv->driver.name)) 12298 return false; 12299 12300 return true; 12301 } 12302 12303 bool 12304 is_i40e_supported(struct rte_eth_dev *dev) 12305 { 12306 return is_device_supported(dev, &rte_i40e_pmd); 12307 } 12308 12309 struct i40e_customized_pctype* 12310 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index) 12311 { 12312 int i; 12313 12314 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) { 12315 if (pf->customized_pctype[i].index == index) 12316 return &pf->customized_pctype[i]; 12317 } 12318 return NULL; 12319 } 12320 12321 static int 12322 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg, 12323 uint32_t pkg_size, uint32_t proto_num, 12324 struct rte_pmd_i40e_proto_info *proto, 12325 enum rte_pmd_i40e_package_op op) 12326 { 12327 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12328 uint32_t pctype_num; 12329 struct rte_pmd_i40e_ptype_info *pctype; 12330 uint32_t buff_size; 12331 struct i40e_customized_pctype *new_pctype = NULL; 12332 uint8_t proto_id; 12333 uint8_t pctype_value; 12334 char name[64]; 12335 uint32_t i, j, n; 12336 int ret; 12337 12338 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12339 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12340 PMD_DRV_LOG(ERR, "Unsupported operation."); 12341 return -1; 12342 } 12343 12344 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12345 (uint8_t *)&pctype_num, sizeof(pctype_num), 12346 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM); 12347 if (ret) { 12348 PMD_DRV_LOG(ERR, "Failed to get pctype number"); 12349 return -1; 12350 } 12351 if (!pctype_num) { 12352 PMD_DRV_LOG(INFO, "No new pctype added"); 12353 return -1; 12354 } 12355 12356 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info); 12357 pctype = rte_zmalloc("new_pctype", buff_size, 0); 12358 if (!pctype) { 12359 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12360 return -1; 12361 } 12362 /* get information about new pctype list */ 12363 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12364 (uint8_t *)pctype, buff_size, 12365 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST); 12366 if (ret) { 12367 PMD_DRV_LOG(ERR, "Failed to get pctype list"); 12368 rte_free(pctype); 12369 return -1; 12370 } 12371 12372 /* Update customized pctype. */ 12373 for (i = 0; i < pctype_num; i++) { 12374 pctype_value = pctype[i].ptype_id; 12375 memset(name, 0, sizeof(name)); 12376 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) { 12377 proto_id = pctype[i].protocols[j]; 12378 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED) 12379 continue; 12380 for (n = 0; n < proto_num; n++) { 12381 if (proto[n].proto_id != proto_id) 12382 continue; 12383 strlcat(name, proto[n].name, sizeof(name)); 12384 strlcat(name, "_", sizeof(name)); 12385 break; 12386 } 12387 } 12388 name[strlen(name) - 1] = '\0'; 12389 PMD_DRV_LOG(INFO, "name = %s\n", name); 12390 if (!strcmp(name, "GTPC")) 12391 new_pctype = 12392 i40e_find_customized_pctype(pf, 12393 I40E_CUSTOMIZED_GTPC); 12394 else if (!strcmp(name, "GTPU_IPV4")) 12395 new_pctype = 12396 i40e_find_customized_pctype(pf, 12397 I40E_CUSTOMIZED_GTPU_IPV4); 12398 else if (!strcmp(name, "GTPU_IPV6")) 12399 new_pctype = 12400 i40e_find_customized_pctype(pf, 12401 I40E_CUSTOMIZED_GTPU_IPV6); 12402 else if (!strcmp(name, "GTPU")) 12403 new_pctype = 12404 i40e_find_customized_pctype(pf, 12405 I40E_CUSTOMIZED_GTPU); 12406 else if (!strcmp(name, "IPV4_L2TPV3")) 12407 new_pctype = 12408 i40e_find_customized_pctype(pf, 12409 I40E_CUSTOMIZED_IPV4_L2TPV3); 12410 else if (!strcmp(name, "IPV6_L2TPV3")) 12411 new_pctype = 12412 i40e_find_customized_pctype(pf, 12413 I40E_CUSTOMIZED_IPV6_L2TPV3); 12414 else if (!strcmp(name, "IPV4_ESP")) 12415 new_pctype = 12416 i40e_find_customized_pctype(pf, 12417 I40E_CUSTOMIZED_ESP_IPV4); 12418 else if (!strcmp(name, "IPV6_ESP")) 12419 new_pctype = 12420 i40e_find_customized_pctype(pf, 12421 I40E_CUSTOMIZED_ESP_IPV6); 12422 else if (!strcmp(name, "IPV4_UDP_ESP")) 12423 new_pctype = 12424 i40e_find_customized_pctype(pf, 12425 I40E_CUSTOMIZED_ESP_IPV4_UDP); 12426 else if (!strcmp(name, "IPV6_UDP_ESP")) 12427 new_pctype = 12428 i40e_find_customized_pctype(pf, 12429 I40E_CUSTOMIZED_ESP_IPV6_UDP); 12430 else if (!strcmp(name, "IPV4_AH")) 12431 new_pctype = 12432 i40e_find_customized_pctype(pf, 12433 I40E_CUSTOMIZED_AH_IPV4); 12434 else if (!strcmp(name, "IPV6_AH")) 12435 new_pctype = 12436 i40e_find_customized_pctype(pf, 12437 I40E_CUSTOMIZED_AH_IPV6); 12438 if (new_pctype) { 12439 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) { 12440 new_pctype->pctype = pctype_value; 12441 new_pctype->valid = true; 12442 } else { 12443 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID; 12444 new_pctype->valid = false; 12445 } 12446 } 12447 } 12448 12449 rte_free(pctype); 12450 return 0; 12451 } 12452 12453 static int 12454 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg, 12455 uint32_t pkg_size, uint32_t proto_num, 12456 struct rte_pmd_i40e_proto_info *proto, 12457 enum rte_pmd_i40e_package_op op) 12458 { 12459 struct rte_pmd_i40e_ptype_mapping *ptype_mapping; 12460 uint16_t port_id = dev->data->port_id; 12461 uint32_t ptype_num; 12462 struct rte_pmd_i40e_ptype_info *ptype; 12463 uint32_t buff_size; 12464 uint8_t proto_id; 12465 char name[RTE_PMD_I40E_DDP_NAME_SIZE]; 12466 uint32_t i, j, n; 12467 bool in_tunnel; 12468 int ret; 12469 12470 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12471 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12472 PMD_DRV_LOG(ERR, "Unsupported operation."); 12473 return -1; 12474 } 12475 12476 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) { 12477 rte_pmd_i40e_ptype_mapping_reset(port_id); 12478 return 0; 12479 } 12480 12481 /* get information about new ptype num */ 12482 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12483 (uint8_t *)&ptype_num, sizeof(ptype_num), 12484 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM); 12485 if (ret) { 12486 PMD_DRV_LOG(ERR, "Failed to get ptype number"); 12487 return ret; 12488 } 12489 if (!ptype_num) { 12490 PMD_DRV_LOG(INFO, "No new ptype added"); 12491 return -1; 12492 } 12493 12494 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info); 12495 ptype = rte_zmalloc("new_ptype", buff_size, 0); 12496 if (!ptype) { 12497 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12498 return -1; 12499 } 12500 12501 /* get information about new ptype list */ 12502 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12503 (uint8_t *)ptype, buff_size, 12504 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST); 12505 if (ret) { 12506 PMD_DRV_LOG(ERR, "Failed to get ptype list"); 12507 rte_free(ptype); 12508 return ret; 12509 } 12510 12511 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping); 12512 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0); 12513 if (!ptype_mapping) { 12514 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12515 rte_free(ptype); 12516 return -1; 12517 } 12518 12519 /* Update ptype mapping table. */ 12520 for (i = 0; i < ptype_num; i++) { 12521 ptype_mapping[i].hw_ptype = ptype[i].ptype_id; 12522 ptype_mapping[i].sw_ptype = 0; 12523 in_tunnel = false; 12524 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) { 12525 proto_id = ptype[i].protocols[j]; 12526 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED) 12527 continue; 12528 for (n = 0; n < proto_num; n++) { 12529 if (proto[n].proto_id != proto_id) 12530 continue; 12531 memset(name, 0, sizeof(name)); 12532 strcpy(name, proto[n].name); 12533 PMD_DRV_LOG(INFO, "name = %s\n", name); 12534 if (!strncasecmp(name, "PPPOE", 5)) 12535 ptype_mapping[i].sw_ptype |= 12536 RTE_PTYPE_L2_ETHER_PPPOE; 12537 else if (!strncasecmp(name, "IPV4FRAG", 8) && 12538 !in_tunnel) { 12539 ptype_mapping[i].sw_ptype |= 12540 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12541 ptype_mapping[i].sw_ptype |= 12542 RTE_PTYPE_L4_FRAG; 12543 } else if (!strncasecmp(name, "IPV4FRAG", 8) && 12544 in_tunnel) { 12545 ptype_mapping[i].sw_ptype |= 12546 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 12547 ptype_mapping[i].sw_ptype |= 12548 RTE_PTYPE_INNER_L4_FRAG; 12549 } else if (!strncasecmp(name, "OIPV4", 5)) { 12550 ptype_mapping[i].sw_ptype |= 12551 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12552 in_tunnel = true; 12553 } else if (!strncasecmp(name, "IPV4", 4) && 12554 !in_tunnel) 12555 ptype_mapping[i].sw_ptype |= 12556 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12557 else if (!strncasecmp(name, "IPV4", 4) && 12558 in_tunnel) 12559 ptype_mapping[i].sw_ptype |= 12560 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 12561 else if (!strncasecmp(name, "IPV6FRAG", 8) && 12562 !in_tunnel) { 12563 ptype_mapping[i].sw_ptype |= 12564 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12565 ptype_mapping[i].sw_ptype |= 12566 RTE_PTYPE_L4_FRAG; 12567 } else if (!strncasecmp(name, "IPV6FRAG", 8) && 12568 in_tunnel) { 12569 ptype_mapping[i].sw_ptype |= 12570 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 12571 ptype_mapping[i].sw_ptype |= 12572 RTE_PTYPE_INNER_L4_FRAG; 12573 } else if (!strncasecmp(name, "OIPV6", 5)) { 12574 ptype_mapping[i].sw_ptype |= 12575 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12576 in_tunnel = true; 12577 } else if (!strncasecmp(name, "IPV6", 4) && 12578 !in_tunnel) 12579 ptype_mapping[i].sw_ptype |= 12580 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12581 else if (!strncasecmp(name, "IPV6", 4) && 12582 in_tunnel) 12583 ptype_mapping[i].sw_ptype |= 12584 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 12585 else if (!strncasecmp(name, "UDP", 3) && 12586 !in_tunnel) 12587 ptype_mapping[i].sw_ptype |= 12588 RTE_PTYPE_L4_UDP; 12589 else if (!strncasecmp(name, "UDP", 3) && 12590 in_tunnel) 12591 ptype_mapping[i].sw_ptype |= 12592 RTE_PTYPE_INNER_L4_UDP; 12593 else if (!strncasecmp(name, "TCP", 3) && 12594 !in_tunnel) 12595 ptype_mapping[i].sw_ptype |= 12596 RTE_PTYPE_L4_TCP; 12597 else if (!strncasecmp(name, "TCP", 3) && 12598 in_tunnel) 12599 ptype_mapping[i].sw_ptype |= 12600 RTE_PTYPE_INNER_L4_TCP; 12601 else if (!strncasecmp(name, "SCTP", 4) && 12602 !in_tunnel) 12603 ptype_mapping[i].sw_ptype |= 12604 RTE_PTYPE_L4_SCTP; 12605 else if (!strncasecmp(name, "SCTP", 4) && 12606 in_tunnel) 12607 ptype_mapping[i].sw_ptype |= 12608 RTE_PTYPE_INNER_L4_SCTP; 12609 else if ((!strncasecmp(name, "ICMP", 4) || 12610 !strncasecmp(name, "ICMPV6", 6)) && 12611 !in_tunnel) 12612 ptype_mapping[i].sw_ptype |= 12613 RTE_PTYPE_L4_ICMP; 12614 else if ((!strncasecmp(name, "ICMP", 4) || 12615 !strncasecmp(name, "ICMPV6", 6)) && 12616 in_tunnel) 12617 ptype_mapping[i].sw_ptype |= 12618 RTE_PTYPE_INNER_L4_ICMP; 12619 else if (!strncasecmp(name, "GTPC", 4)) { 12620 ptype_mapping[i].sw_ptype |= 12621 RTE_PTYPE_TUNNEL_GTPC; 12622 in_tunnel = true; 12623 } else if (!strncasecmp(name, "GTPU", 4)) { 12624 ptype_mapping[i].sw_ptype |= 12625 RTE_PTYPE_TUNNEL_GTPU; 12626 in_tunnel = true; 12627 } else if (!strncasecmp(name, "ESP", 3)) { 12628 ptype_mapping[i].sw_ptype |= 12629 RTE_PTYPE_TUNNEL_ESP; 12630 in_tunnel = true; 12631 } else if (!strncasecmp(name, "GRENAT", 6)) { 12632 ptype_mapping[i].sw_ptype |= 12633 RTE_PTYPE_TUNNEL_GRENAT; 12634 in_tunnel = true; 12635 } else if (!strncasecmp(name, "L2TPV2CTL", 9) || 12636 !strncasecmp(name, "L2TPV2", 6) || 12637 !strncasecmp(name, "L2TPV3", 6)) { 12638 ptype_mapping[i].sw_ptype |= 12639 RTE_PTYPE_TUNNEL_L2TP; 12640 in_tunnel = true; 12641 } 12642 12643 break; 12644 } 12645 } 12646 } 12647 12648 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping, 12649 ptype_num, 0); 12650 if (ret) 12651 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table."); 12652 12653 rte_free(ptype_mapping); 12654 rte_free(ptype); 12655 return ret; 12656 } 12657 12658 void 12659 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 12660 uint32_t pkg_size, enum rte_pmd_i40e_package_op op) 12661 { 12662 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12663 uint32_t proto_num; 12664 struct rte_pmd_i40e_proto_info *proto; 12665 uint32_t buff_size; 12666 uint32_t i; 12667 int ret; 12668 12669 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12670 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12671 PMD_DRV_LOG(ERR, "Unsupported operation."); 12672 return; 12673 } 12674 12675 /* get information about protocol number */ 12676 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12677 (uint8_t *)&proto_num, sizeof(proto_num), 12678 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM); 12679 if (ret) { 12680 PMD_DRV_LOG(ERR, "Failed to get protocol number"); 12681 return; 12682 } 12683 if (!proto_num) { 12684 PMD_DRV_LOG(INFO, "No new protocol added"); 12685 return; 12686 } 12687 12688 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info); 12689 proto = rte_zmalloc("new_proto", buff_size, 0); 12690 if (!proto) { 12691 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12692 return; 12693 } 12694 12695 /* get information about protocol list */ 12696 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12697 (uint8_t *)proto, buff_size, 12698 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST); 12699 if (ret) { 12700 PMD_DRV_LOG(ERR, "Failed to get protocol list"); 12701 rte_free(proto); 12702 return; 12703 } 12704 12705 /* Check if GTP is supported. */ 12706 for (i = 0; i < proto_num; i++) { 12707 if (!strncmp(proto[i].name, "GTP", 3)) { 12708 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) 12709 pf->gtp_support = true; 12710 else 12711 pf->gtp_support = false; 12712 break; 12713 } 12714 } 12715 12716 /* Check if ESP is supported. */ 12717 for (i = 0; i < proto_num; i++) { 12718 if (!strncmp(proto[i].name, "ESP", 3)) { 12719 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) 12720 pf->esp_support = true; 12721 else 12722 pf->esp_support = false; 12723 break; 12724 } 12725 } 12726 12727 /* Update customized pctype info */ 12728 ret = i40e_update_customized_pctype(dev, pkg, pkg_size, 12729 proto_num, proto, op); 12730 if (ret) 12731 PMD_DRV_LOG(INFO, "No pctype is updated."); 12732 12733 /* Update customized ptype info */ 12734 ret = i40e_update_customized_ptype(dev, pkg, pkg_size, 12735 proto_num, proto, op); 12736 if (ret) 12737 PMD_DRV_LOG(INFO, "No ptype is updated."); 12738 12739 rte_free(proto); 12740 } 12741 12742 /* Create a QinQ cloud filter 12743 * 12744 * The Fortville NIC has limited resources for tunnel filters, 12745 * so we can only reuse existing filters. 12746 * 12747 * In step 1 we define which Field Vector fields can be used for 12748 * filter types. 12749 * As we do not have the inner tag defined as a field, 12750 * we have to define it first, by reusing one of L1 entries. 12751 * 12752 * In step 2 we are replacing one of existing filter types with 12753 * a new one for QinQ. 12754 * As we reusing L1 and replacing L2, some of the default filter 12755 * types will disappear,which depends on L1 and L2 entries we reuse. 12756 * 12757 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b) 12758 * 12759 * 1. Create L1 filter of outer vlan (12b) which will be in use 12760 * later when we define the cloud filter. 12761 * a. Valid_flags.replace_cloud = 0 12762 * b. Old_filter = 10 (Stag_Inner_Vlan) 12763 * c. New_filter = 0x10 12764 * d. TR bit = 0xff (optional, not used here) 12765 * e. Buffer – 2 entries: 12766 * i. Byte 0 = 8 (outer vlan FV index). 12767 * Byte 1 = 0 (rsv) 12768 * Byte 2-3 = 0x0fff 12769 * ii. Byte 0 = 37 (inner vlan FV index). 12770 * Byte 1 =0 (rsv) 12771 * Byte 2-3 = 0x0fff 12772 * 12773 * Step 2: 12774 * 2. Create cloud filter using two L1 filters entries: stag and 12775 * new filter(outer vlan+ inner vlan) 12776 * a. Valid_flags.replace_cloud = 1 12777 * b. Old_filter = 1 (instead of outer IP) 12778 * c. New_filter = 0x10 12779 * d. Buffer – 2 entries: 12780 * i. Byte 0 = 0x80 | 7 (valid | Stag). 12781 * Byte 1-3 = 0 (rsv) 12782 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1) 12783 * Byte 9-11 = 0 (rsv) 12784 */ 12785 static int 12786 i40e_cloud_filter_qinq_create(struct i40e_pf *pf) 12787 { 12788 int ret = -ENOTSUP; 12789 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 12790 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 12791 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12792 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 12793 12794 if (pf->support_multi_driver) { 12795 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 12796 return ret; 12797 } 12798 12799 /* Init */ 12800 memset(&filter_replace, 0, 12801 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 12802 memset(&filter_replace_buf, 0, 12803 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 12804 12805 /* create L1 filter */ 12806 filter_replace.old_filter_type = 12807 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN; 12808 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12809 filter_replace.tr_bit = 0; 12810 12811 /* Prepare the buffer, 2 entries */ 12812 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN; 12813 filter_replace_buf.data[0] |= 12814 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12815 /* Field Vector 12b mask */ 12816 filter_replace_buf.data[2] = 0xff; 12817 filter_replace_buf.data[3] = 0x0f; 12818 filter_replace_buf.data[4] = 12819 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN; 12820 filter_replace_buf.data[4] |= 12821 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12822 /* Field Vector 12b mask */ 12823 filter_replace_buf.data[6] = 0xff; 12824 filter_replace_buf.data[7] = 0x0f; 12825 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, 12826 &filter_replace_buf); 12827 if (ret != I40E_SUCCESS) 12828 return ret; 12829 12830 if (filter_replace.old_filter_type != 12831 filter_replace.new_filter_type) 12832 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 12833 " original: 0x%x, new: 0x%x", 12834 dev->device->name, 12835 filter_replace.old_filter_type, 12836 filter_replace.new_filter_type); 12837 12838 /* Apply the second L2 cloud filter */ 12839 memset(&filter_replace, 0, 12840 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 12841 memset(&filter_replace_buf, 0, 12842 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 12843 12844 /* create L2 filter, input for L2 filter will be L1 filter */ 12845 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 12846 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP; 12847 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12848 12849 /* Prepare the buffer, 2 entries */ 12850 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 12851 filter_replace_buf.data[0] |= 12852 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12853 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12854 filter_replace_buf.data[4] |= 12855 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12856 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, 12857 &filter_replace_buf); 12858 if (!ret && (filter_replace.old_filter_type != 12859 filter_replace.new_filter_type)) 12860 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 12861 " original: 0x%x, new: 0x%x", 12862 dev->device->name, 12863 filter_replace.old_filter_type, 12864 filter_replace.new_filter_type); 12865 12866 return ret; 12867 } 12868 12869 int 12870 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, 12871 const struct rte_flow_action_rss *in) 12872 { 12873 if (in->key_len > RTE_DIM(out->key) || 12874 in->queue_num > RTE_DIM(out->queue)) 12875 return -EINVAL; 12876 if (!in->key && in->key_len) 12877 return -EINVAL; 12878 out->conf = (struct rte_flow_action_rss){ 12879 .func = in->func, 12880 .level = in->level, 12881 .types = in->types, 12882 .key_len = in->key_len, 12883 .queue_num = in->queue_num, 12884 .queue = memcpy(out->queue, in->queue, 12885 sizeof(*in->queue) * in->queue_num), 12886 }; 12887 if (in->key) 12888 out->conf.key = memcpy(out->key, in->key, in->key_len); 12889 return 0; 12890 } 12891 12892 /* Write HENA register to enable hash */ 12893 static int 12894 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf) 12895 { 12896 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12897 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key; 12898 uint64_t hena; 12899 int ret; 12900 12901 ret = i40e_set_rss_key(pf->main_vsi, key, 12902 rss_conf->conf.key_len); 12903 if (ret) 12904 return ret; 12905 12906 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types); 12907 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); 12908 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); 12909 I40E_WRITE_FLUSH(hw); 12910 12911 return 0; 12912 } 12913 12914 /* Configure hash input set */ 12915 static int 12916 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types) 12917 { 12918 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12919 struct rte_eth_input_set_conf conf; 12920 uint64_t mask0; 12921 int ret = 0; 12922 uint32_t j; 12923 int i; 12924 static const struct { 12925 uint64_t type; 12926 enum rte_eth_input_set_field field; 12927 } inset_match_table[] = { 12928 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY, 12929 RTE_ETH_INPUT_SET_L3_SRC_IP4}, 12930 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY, 12931 RTE_ETH_INPUT_SET_L3_DST_IP4}, 12932 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY, 12933 RTE_ETH_INPUT_SET_UNKNOWN}, 12934 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY, 12935 RTE_ETH_INPUT_SET_UNKNOWN}, 12936 12937 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY, 12938 RTE_ETH_INPUT_SET_L3_SRC_IP4}, 12939 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY, 12940 RTE_ETH_INPUT_SET_L3_DST_IP4}, 12941 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY, 12942 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT}, 12943 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY, 12944 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT}, 12945 12946 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY, 12947 RTE_ETH_INPUT_SET_L3_SRC_IP4}, 12948 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY, 12949 RTE_ETH_INPUT_SET_L3_DST_IP4}, 12950 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY, 12951 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT}, 12952 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY, 12953 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT}, 12954 12955 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY, 12956 RTE_ETH_INPUT_SET_L3_SRC_IP4}, 12957 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY, 12958 RTE_ETH_INPUT_SET_L3_DST_IP4}, 12959 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY, 12960 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT}, 12961 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY, 12962 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT}, 12963 12964 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY, 12965 RTE_ETH_INPUT_SET_L3_SRC_IP4}, 12966 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY, 12967 RTE_ETH_INPUT_SET_L3_DST_IP4}, 12968 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY, 12969 RTE_ETH_INPUT_SET_UNKNOWN}, 12970 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY, 12971 RTE_ETH_INPUT_SET_UNKNOWN}, 12972 12973 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY, 12974 RTE_ETH_INPUT_SET_L3_SRC_IP6}, 12975 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY, 12976 RTE_ETH_INPUT_SET_L3_DST_IP6}, 12977 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY, 12978 RTE_ETH_INPUT_SET_UNKNOWN}, 12979 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY, 12980 RTE_ETH_INPUT_SET_UNKNOWN}, 12981 12982 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY, 12983 RTE_ETH_INPUT_SET_L3_SRC_IP6}, 12984 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY, 12985 RTE_ETH_INPUT_SET_L3_DST_IP6}, 12986 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY, 12987 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT}, 12988 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY, 12989 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT}, 12990 12991 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY, 12992 RTE_ETH_INPUT_SET_L3_SRC_IP6}, 12993 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY, 12994 RTE_ETH_INPUT_SET_L3_DST_IP6}, 12995 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY, 12996 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT}, 12997 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY, 12998 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT}, 12999 13000 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY, 13001 RTE_ETH_INPUT_SET_L3_SRC_IP6}, 13002 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY, 13003 RTE_ETH_INPUT_SET_L3_DST_IP6}, 13004 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY, 13005 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT}, 13006 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY, 13007 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT}, 13008 13009 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY, 13010 RTE_ETH_INPUT_SET_L3_SRC_IP6}, 13011 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY, 13012 RTE_ETH_INPUT_SET_L3_DST_IP6}, 13013 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY, 13014 RTE_ETH_INPUT_SET_UNKNOWN}, 13015 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY, 13016 RTE_ETH_INPUT_SET_UNKNOWN}, 13017 }; 13018 13019 mask0 = types & pf->adapter->flow_types_mask; 13020 conf.op = RTE_ETH_INPUT_SET_SELECT; 13021 conf.inset_size = 0; 13022 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) { 13023 if (mask0 & (1ULL << i)) { 13024 conf.flow_type = i; 13025 break; 13026 } 13027 } 13028 13029 for (j = 0; j < RTE_DIM(inset_match_table); j++) { 13030 if ((types & inset_match_table[j].type) == 13031 inset_match_table[j].type) { 13032 if (inset_match_table[j].field == 13033 RTE_ETH_INPUT_SET_UNKNOWN) 13034 return -EINVAL; 13035 13036 conf.field[conf.inset_size] = 13037 inset_match_table[j].field; 13038 conf.inset_size++; 13039 } 13040 } 13041 13042 if (conf.inset_size) { 13043 ret = i40e_hash_filter_inset_select(hw, &conf); 13044 if (ret) 13045 return ret; 13046 } 13047 13048 return ret; 13049 } 13050 13051 /* Look up the conflicted rule then mark it as invalid */ 13052 static void 13053 i40e_rss_mark_invalid_rule(struct i40e_pf *pf, 13054 struct i40e_rte_flow_rss_conf *conf) 13055 { 13056 struct i40e_rss_filter *rss_item; 13057 uint64_t rss_inset; 13058 13059 /* Clear input set bits before comparing the pctype */ 13060 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | 13061 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY); 13062 13063 /* Look up the conflicted rule then mark it as invalid */ 13064 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) { 13065 if (!rss_item->rss_filter_info.valid) 13066 continue; 13067 13068 if (conf->conf.queue_num && 13069 rss_item->rss_filter_info.conf.queue_num) 13070 rss_item->rss_filter_info.valid = false; 13071 13072 if (conf->conf.types && 13073 (rss_item->rss_filter_info.conf.types & 13074 rss_inset) == 13075 (conf->conf.types & rss_inset)) 13076 rss_item->rss_filter_info.valid = false; 13077 13078 if (conf->conf.func == 13079 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR && 13080 rss_item->rss_filter_info.conf.func == 13081 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) 13082 rss_item->rss_filter_info.valid = false; 13083 } 13084 } 13085 13086 /* Configure RSS hash function */ 13087 static int 13088 i40e_rss_config_hash_function(struct i40e_pf *pf, 13089 struct i40e_rte_flow_rss_conf *conf) 13090 { 13091 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 13092 uint32_t reg, i; 13093 uint64_t mask0; 13094 uint16_t j; 13095 13096 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { 13097 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 13098 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) { 13099 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR"); 13100 I40E_WRITE_FLUSH(hw); 13101 i40e_rss_mark_invalid_rule(pf, conf); 13102 13103 return 0; 13104 } 13105 reg &= ~I40E_GLQF_CTL_HTOEP_MASK; 13106 13107 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg); 13108 I40E_WRITE_FLUSH(hw); 13109 i40e_rss_mark_invalid_rule(pf, conf); 13110 } else if (conf->conf.func == 13111 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) { 13112 mask0 = conf->conf.types & pf->adapter->flow_types_mask; 13113 13114 i40e_set_symmetric_hash_enable_per_port(hw, 1); 13115 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) { 13116 if (mask0 & (1UL << i)) 13117 break; 13118 } 13119 13120 if (i == UINT64_BIT) 13121 return -EINVAL; 13122 13123 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 13124 j < I40E_FILTER_PCTYPE_MAX; j++) { 13125 if (pf->adapter->pctypes_tbl[i] & (1ULL << j)) 13126 i40e_write_global_rx_ctl(hw, 13127 I40E_GLQF_HSYM(j), 13128 I40E_GLQF_HSYM_SYMH_ENA_MASK); 13129 } 13130 } 13131 13132 return 0; 13133 } 13134 13135 /* Enable RSS according to the configuration */ 13136 static int 13137 i40e_rss_enable_hash(struct i40e_pf *pf, 13138 struct i40e_rte_flow_rss_conf *conf) 13139 { 13140 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 13141 struct i40e_rte_flow_rss_conf rss_conf; 13142 13143 if (!(conf->conf.types & pf->adapter->flow_types_mask)) 13144 return -ENOTSUP; 13145 13146 memset(&rss_conf, 0, sizeof(rss_conf)); 13147 rte_memcpy(&rss_conf, conf, sizeof(rss_conf)); 13148 13149 /* Configure hash input set */ 13150 if (i40e_rss_conf_hash_inset(pf, conf->conf.types)) 13151 return -EINVAL; 13152 13153 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len < 13154 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 13155 /* Random default keys */ 13156 static uint32_t rss_key_default[] = {0x6b793944, 13157 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8, 13158 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605, 13159 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581}; 13160 13161 rss_conf.conf.key = (uint8_t *)rss_key_default; 13162 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 13163 sizeof(uint32_t); 13164 PMD_DRV_LOG(INFO, 13165 "No valid RSS key config for i40e, using default\n"); 13166 } 13167 13168 rss_conf.conf.types |= rss_info->conf.types; 13169 i40e_rss_hash_set(pf, &rss_conf); 13170 13171 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) 13172 i40e_rss_config_hash_function(pf, conf); 13173 13174 i40e_rss_mark_invalid_rule(pf, conf); 13175 13176 return 0; 13177 } 13178 13179 /* Configure RSS queue region */ 13180 static int 13181 i40e_rss_config_queue_region(struct i40e_pf *pf, 13182 struct i40e_rte_flow_rss_conf *conf) 13183 { 13184 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 13185 uint32_t lut = 0; 13186 uint16_t j, num; 13187 uint32_t i; 13188 13189 /* If both VMDQ and RSS enabled, not all of PF queues are configured. 13190 * It's necessary to calculate the actual PF queues that are configured. 13191 */ 13192 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 13193 num = i40e_pf_calc_configured_queues_num(pf); 13194 else 13195 num = pf->dev_data->nb_rx_queues; 13196 13197 num = RTE_MIN(num, conf->conf.queue_num); 13198 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured", 13199 num); 13200 13201 if (num == 0) { 13202 PMD_DRV_LOG(ERR, 13203 "No PF queues are configured to enable RSS for port %u", 13204 pf->dev_data->port_id); 13205 return -ENOTSUP; 13206 } 13207 13208 /* Fill in redirection table */ 13209 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 13210 if (j == num) 13211 j = 0; 13212 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 << 13213 hw->func_caps.rss_table_entry_width) - 1)); 13214 if ((i & 3) == 3) 13215 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut); 13216 } 13217 13218 i40e_rss_mark_invalid_rule(pf, conf); 13219 13220 return 0; 13221 } 13222 13223 /* Configure RSS hash function to default */ 13224 static int 13225 i40e_rss_clear_hash_function(struct i40e_pf *pf, 13226 struct i40e_rte_flow_rss_conf *conf) 13227 { 13228 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 13229 uint32_t i, reg; 13230 uint64_t mask0; 13231 uint16_t j; 13232 13233 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { 13234 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 13235 if (reg & I40E_GLQF_CTL_HTOEP_MASK) { 13236 PMD_DRV_LOG(DEBUG, 13237 "Hash function already set to Toeplitz"); 13238 I40E_WRITE_FLUSH(hw); 13239 13240 return 0; 13241 } 13242 reg |= I40E_GLQF_CTL_HTOEP_MASK; 13243 13244 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg); 13245 I40E_WRITE_FLUSH(hw); 13246 } else if (conf->conf.func == 13247 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) { 13248 mask0 = conf->conf.types & pf->adapter->flow_types_mask; 13249 13250 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) { 13251 if (mask0 & (1UL << i)) 13252 break; 13253 } 13254 13255 if (i == UINT64_BIT) 13256 return -EINVAL; 13257 13258 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 13259 j < I40E_FILTER_PCTYPE_MAX; j++) { 13260 if (pf->adapter->pctypes_tbl[i] & (1ULL << j)) 13261 i40e_write_global_rx_ctl(hw, 13262 I40E_GLQF_HSYM(j), 13263 0); 13264 } 13265 } 13266 13267 return 0; 13268 } 13269 13270 /* Disable RSS hash and configure default input set */ 13271 static int 13272 i40e_rss_disable_hash(struct i40e_pf *pf, 13273 struct i40e_rte_flow_rss_conf *conf) 13274 { 13275 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 13276 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 13277 struct i40e_rte_flow_rss_conf rss_conf; 13278 uint32_t i; 13279 13280 memset(&rss_conf, 0, sizeof(rss_conf)); 13281 rte_memcpy(&rss_conf, conf, sizeof(rss_conf)); 13282 13283 /* Disable RSS hash */ 13284 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types); 13285 i40e_rss_hash_set(pf, &rss_conf); 13286 13287 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) { 13288 if (!(pf->adapter->flow_types_mask & (1ULL << i)) || 13289 !(conf->conf.types & (1ULL << i))) 13290 continue; 13291 13292 /* Configure default input set */ 13293 struct rte_eth_input_set_conf input_conf = { 13294 .op = RTE_ETH_INPUT_SET_SELECT, 13295 .flow_type = i, 13296 .inset_size = 1, 13297 }; 13298 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT; 13299 i40e_hash_filter_inset_select(hw, &input_conf); 13300 } 13301 13302 rss_info->conf.types = rss_conf.conf.types; 13303 13304 i40e_rss_clear_hash_function(pf, conf); 13305 13306 return 0; 13307 } 13308 13309 /* Configure RSS queue region to default */ 13310 static int 13311 i40e_rss_clear_queue_region(struct i40e_pf *pf) 13312 { 13313 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 13314 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 13315 uint16_t queue[I40E_MAX_Q_PER_TC]; 13316 uint32_t num_rxq, i; 13317 uint32_t lut = 0; 13318 uint16_t j, num; 13319 13320 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC); 13321 13322 for (j = 0; j < num_rxq; j++) 13323 queue[j] = j; 13324 13325 /* If both VMDQ and RSS enabled, not all of PF queues are configured. 13326 * It's necessary to calculate the actual PF queues that are configured. 13327 */ 13328 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 13329 num = i40e_pf_calc_configured_queues_num(pf); 13330 else 13331 num = pf->dev_data->nb_rx_queues; 13332 13333 num = RTE_MIN(num, num_rxq); 13334 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured", 13335 num); 13336 13337 if (num == 0) { 13338 PMD_DRV_LOG(ERR, 13339 "No PF queues are configured to enable RSS for port %u", 13340 pf->dev_data->port_id); 13341 return -ENOTSUP; 13342 } 13343 13344 /* Fill in redirection table */ 13345 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 13346 if (j == num) 13347 j = 0; 13348 lut = (lut << 8) | (queue[j] & ((0x1 << 13349 hw->func_caps.rss_table_entry_width) - 1)); 13350 if ((i & 3) == 3) 13351 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut); 13352 } 13353 13354 rss_info->conf.queue_num = 0; 13355 memset(&rss_info->conf.queue, 0, sizeof(uint16_t)); 13356 13357 return 0; 13358 } 13359 13360 int 13361 i40e_config_rss_filter(struct i40e_pf *pf, 13362 struct i40e_rte_flow_rss_conf *conf, bool add) 13363 { 13364 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 13365 struct rte_flow_action_rss update_conf = rss_info->conf; 13366 int ret = 0; 13367 13368 if (add) { 13369 if (conf->conf.queue_num) { 13370 /* Configure RSS queue region */ 13371 ret = i40e_rss_config_queue_region(pf, conf); 13372 if (ret) 13373 return ret; 13374 13375 update_conf.queue_num = conf->conf.queue_num; 13376 update_conf.queue = conf->conf.queue; 13377 } else if (conf->conf.func == 13378 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { 13379 /* Configure hash function */ 13380 ret = i40e_rss_config_hash_function(pf, conf); 13381 if (ret) 13382 return ret; 13383 13384 update_conf.func = conf->conf.func; 13385 } else { 13386 /* Configure hash enable and input set */ 13387 ret = i40e_rss_enable_hash(pf, conf); 13388 if (ret) 13389 return ret; 13390 13391 update_conf.types |= conf->conf.types; 13392 update_conf.key = conf->conf.key; 13393 update_conf.key_len = conf->conf.key_len; 13394 } 13395 13396 /* Update RSS info in pf */ 13397 if (i40e_rss_conf_init(rss_info, &update_conf)) 13398 return -EINVAL; 13399 } else { 13400 if (!conf->valid) 13401 return 0; 13402 13403 if (conf->conf.queue_num) 13404 i40e_rss_clear_queue_region(pf); 13405 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) 13406 i40e_rss_clear_hash_function(pf, conf); 13407 else 13408 i40e_rss_disable_hash(pf, conf); 13409 } 13410 13411 return 0; 13412 } 13413 13414 RTE_INIT(i40e_init_log) 13415 { 13416 i40e_logtype_init = rte_log_register("pmd.net.i40e.init"); 13417 if (i40e_logtype_init >= 0) 13418 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE); 13419 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver"); 13420 if (i40e_logtype_driver >= 0) 13421 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE); 13422 13423 #ifdef RTE_LIBRTE_I40E_DEBUG_RX 13424 i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx"); 13425 if (i40e_logtype_rx >= 0) 13426 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG); 13427 #endif 13428 13429 #ifdef RTE_LIBRTE_I40E_DEBUG_TX 13430 i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx"); 13431 if (i40e_logtype_tx >= 0) 13432 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG); 13433 #endif 13434 13435 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE 13436 i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free"); 13437 if (i40e_logtype_tx_free >= 0) 13438 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG); 13439 #endif 13440 } 13441 13442 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, 13443 ETH_I40E_FLOATING_VEB_ARG "=1" 13444 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>" 13445 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16" 13446 ETH_I40E_SUPPORT_MULTI_DRIVER "=1" 13447 ETH_I40E_USE_LATEST_VEC "=0|1"); 13448