1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <unistd.h> 10 #include <stdarg.h> 11 #include <inttypes.h> 12 #include <assert.h> 13 14 #include <rte_common.h> 15 #include <rte_eal.h> 16 #include <rte_string_fns.h> 17 #include <rte_pci.h> 18 #include <rte_bus_pci.h> 19 #include <rte_ether.h> 20 #include <rte_ethdev_driver.h> 21 #include <rte_ethdev_pci.h> 22 #include <rte_memzone.h> 23 #include <rte_malloc.h> 24 #include <rte_memcpy.h> 25 #include <rte_alarm.h> 26 #include <rte_dev.h> 27 #include <rte_tailq.h> 28 #include <rte_hash_crc.h> 29 30 #include "i40e_logs.h" 31 #include "base/i40e_prototype.h" 32 #include "base/i40e_adminq_cmd.h" 33 #include "base/i40e_type.h" 34 #include "base/i40e_register.h" 35 #include "base/i40e_dcb.h" 36 #include "i40e_ethdev.h" 37 #include "i40e_rxtx.h" 38 #include "i40e_pf.h" 39 #include "i40e_regs.h" 40 #include "rte_pmd_i40e.h" 41 42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" 43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" 44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" 45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" 46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" 47 48 #define I40E_CLEAR_PXE_WAIT_MS 200 49 50 /* Maximun number of capability elements */ 51 #define I40E_MAX_CAP_ELE_NUM 128 52 53 /* Wait count and interval */ 54 #define I40E_CHK_Q_ENA_COUNT 1000 55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000 56 57 /* Maximun number of VSI */ 58 #define I40E_MAX_NUM_VSIS (384UL) 59 60 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */ 61 62 /* Flow control default timer */ 63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU 64 65 /* Flow control enable fwd bit */ 66 #define I40E_PRTMAC_FWD_CTRL 0x00000001 67 68 /* Receive Packet Buffer size */ 69 #define I40E_RXPBSIZE (968 * 1024) 70 71 /* Kilobytes shift */ 72 #define I40E_KILOSHIFT 10 73 74 /* Flow control default high water */ 75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT) 76 77 /* Flow control default low water */ 78 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT) 79 80 /* Receive Average Packet Size in Byte*/ 81 #define I40E_PACKET_AVERAGE_SIZE 128 82 83 /* Mask of PF interrupt causes */ 84 #define I40E_PFINT_ICR0_ENA_MASK ( \ 85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \ 86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \ 87 I40E_PFINT_ICR0_ENA_GRST_MASK | \ 88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \ 89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \ 90 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \ 91 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \ 92 I40E_PFINT_ICR0_ENA_VFLR_MASK | \ 93 I40E_PFINT_ICR0_ENA_ADMINQ_MASK) 94 95 #define I40E_FLOW_TYPES ( \ 96 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \ 97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ 98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ 99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ 100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ 101 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \ 102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ 103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ 104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ 105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \ 106 (1UL << RTE_ETH_FLOW_L2_PAYLOAD)) 107 108 /* Additional timesync values. */ 109 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 110 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 111 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 112 #define I40E_PRTTSYN_TSYNENA 0x80000000 113 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000 114 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL 115 116 /** 117 * Below are values for writing un-exposed registers suggested 118 * by silicon experts 119 */ 120 /* Destination MAC address */ 121 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL 122 /* Source MAC address */ 123 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL 124 /* Outer (S-Tag) VLAN tag in the outer L2 header */ 125 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL 126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */ 127 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL 128 /* Single VLAN tag in the inner L2 header */ 129 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL 130 /* Source IPv4 address */ 131 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL 132 /* Destination IPv4 address */ 133 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL 134 /* Source IPv4 address for X722 */ 135 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL 136 /* Destination IPv4 address for X722 */ 137 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL 138 /* IPv4 Protocol for X722 */ 139 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL 140 /* IPv4 Time to Live for X722 */ 141 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL 142 /* IPv4 Type of Service (TOS) */ 143 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL 144 /* IPv4 Protocol */ 145 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL 146 /* IPv4 Time to Live */ 147 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL 148 /* Source IPv6 address */ 149 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL 150 /* Destination IPv6 address */ 151 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL 152 /* IPv6 Traffic Class (TC) */ 153 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL 154 /* IPv6 Next Header */ 155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL 156 /* IPv6 Hop Limit */ 157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL 158 /* Source L4 port */ 159 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL 160 /* Destination L4 port */ 161 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL 162 /* SCTP verification tag */ 163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL 164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/ 165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL 166 /* Source port of tunneling UDP */ 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL 168 /* Destination port of tunneling UDP */ 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL 170 /* UDP Tunneling ID, NVGRE/GRE key */ 171 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL 172 /* Last ether type */ 173 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL 174 /* Tunneling outer destination IPv4 address */ 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL 176 /* Tunneling outer destination IPv6 address */ 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL 178 /* 1st word of flex payload */ 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL 180 /* 2nd word of flex payload */ 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL 182 /* 3rd word of flex payload */ 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL 184 /* 4th word of flex payload */ 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL 186 /* 5th word of flex payload */ 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL 188 /* 6th word of flex payload */ 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL 190 /* 7th word of flex payload */ 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL 192 /* 8th word of flex payload */ 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL 194 /* all 8 words flex payload */ 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL 196 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL 197 198 #define I40E_TRANSLATE_INSET 0 199 #define I40E_TRANSLATE_REG 1 200 201 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL 202 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL 203 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL 204 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL 205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL 206 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL 207 208 /* PCI offset for querying capability */ 209 #define PCI_DEV_CAP_REG 0xA4 210 /* PCI offset for enabling/disabling Extended Tag */ 211 #define PCI_DEV_CTRL_REG 0xA8 212 /* Bit mask of Extended Tag capability */ 213 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20 214 /* Bit shift of Extended Tag enable/disable */ 215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 216 /* Bit mask of Extended Tag enable/disable */ 217 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) 218 219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); 221 static int i40e_dev_configure(struct rte_eth_dev *dev); 222 static int i40e_dev_start(struct rte_eth_dev *dev); 223 static void i40e_dev_stop(struct rte_eth_dev *dev); 224 static void i40e_dev_close(struct rte_eth_dev *dev); 225 static int i40e_dev_reset(struct rte_eth_dev *dev); 226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev); 227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev); 228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev); 229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev); 230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev); 231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev); 232 static int i40e_dev_stats_get(struct rte_eth_dev *dev, 233 struct rte_eth_stats *stats); 234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev, 235 struct rte_eth_xstat *xstats, unsigned n); 236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev, 237 struct rte_eth_xstat_name *xstats_names, 238 unsigned limit); 239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev); 240 static int i40e_fw_version_get(struct rte_eth_dev *dev, 241 char *fw_version, size_t fw_size); 242 static void i40e_dev_info_get(struct rte_eth_dev *dev, 243 struct rte_eth_dev_info *dev_info); 244 static int i40e_vlan_filter_set(struct rte_eth_dev *dev, 245 uint16_t vlan_id, 246 int on); 247 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev, 248 enum rte_vlan_type vlan_type, 249 uint16_t tpid); 250 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask); 251 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev, 252 uint16_t queue, 253 int on); 254 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on); 255 static int i40e_dev_led_on(struct rte_eth_dev *dev); 256 static int i40e_dev_led_off(struct rte_eth_dev *dev); 257 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev, 258 struct rte_eth_fc_conf *fc_conf); 259 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev, 260 struct rte_eth_fc_conf *fc_conf); 261 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev, 262 struct rte_eth_pfc_conf *pfc_conf); 263 static int i40e_macaddr_add(struct rte_eth_dev *dev, 264 struct rte_ether_addr *mac_addr, 265 uint32_t index, 266 uint32_t pool); 267 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 268 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev, 269 struct rte_eth_rss_reta_entry64 *reta_conf, 270 uint16_t reta_size); 271 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev, 272 struct rte_eth_rss_reta_entry64 *reta_conf, 273 uint16_t reta_size); 274 275 static int i40e_get_cap(struct i40e_hw *hw); 276 static int i40e_pf_parameter_init(struct rte_eth_dev *dev); 277 static int i40e_pf_setup(struct i40e_pf *pf); 278 static int i40e_dev_rxtx_init(struct i40e_pf *pf); 279 static int i40e_vmdq_setup(struct rte_eth_dev *dev); 280 static int i40e_dcb_setup(struct rte_eth_dev *dev); 281 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg, 282 bool offset_loaded, uint64_t *offset, uint64_t *stat); 283 static void i40e_stat_update_48(struct i40e_hw *hw, 284 uint32_t hireg, 285 uint32_t loreg, 286 bool offset_loaded, 287 uint64_t *offset, 288 uint64_t *stat); 289 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue); 290 static void i40e_dev_interrupt_handler(void *param); 291 static void i40e_dev_alarm_handler(void *param); 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool, 293 uint32_t base, uint32_t num); 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool); 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool, 296 uint32_t base); 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool, 298 uint16_t num); 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev); 300 static int i40e_veb_release(struct i40e_veb *veb); 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, 302 struct i40e_vsi *vsi); 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf); 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on); 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi, 306 struct i40e_macvlan_filter *mv_f, 307 int num, 308 uint16_t vlan); 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi); 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev, 311 struct rte_eth_rss_conf *rss_conf); 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 313 struct rte_eth_rss_conf *rss_conf); 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 315 struct rte_eth_udp_tunnel *udp_tunnel); 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 317 struct rte_eth_udp_tunnel *udp_tunnel); 318 static void i40e_filter_input_set_init(struct i40e_pf *pf); 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev, 320 enum rte_filter_op filter_op, 321 void *arg); 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, 323 enum rte_filter_type filter_type, 324 enum rte_filter_op filter_op, 325 void *arg); 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, 327 struct rte_eth_dcb_info *dcb_info); 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw); 329 static void i40e_configure_registers(struct i40e_hw *hw); 330 static void i40e_hw_init(struct rte_eth_dev *dev); 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw, 333 uint16_t seid, 334 uint16_t rule_type, 335 uint16_t *entries, 336 uint16_t count, 337 uint16_t rule_id); 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev, 339 struct rte_eth_mirror_conf *mirror_conf, 340 uint8_t sw_id, uint8_t on); 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id); 342 343 static int i40e_timesync_enable(struct rte_eth_dev *dev); 344 static int i40e_timesync_disable(struct rte_eth_dev *dev); 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 346 struct timespec *timestamp, 347 uint32_t flags); 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 349 struct timespec *timestamp); 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw); 351 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 353 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev, 355 struct timespec *timestamp); 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev, 357 const struct timespec *timestamp); 358 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 360 uint16_t queue_id); 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 362 uint16_t queue_id); 363 364 static int i40e_get_regs(struct rte_eth_dev *dev, 365 struct rte_dev_reg_info *regs); 366 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev); 368 369 static int i40e_get_eeprom(struct rte_eth_dev *dev, 370 struct rte_dev_eeprom_info *eeprom); 371 372 static int i40e_get_module_info(struct rte_eth_dev *dev, 373 struct rte_eth_dev_module_info *modinfo); 374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev, 375 struct rte_dev_eeprom_info *info); 376 377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, 378 struct rte_ether_addr *mac_addr); 379 380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 381 382 static int i40e_ethertype_filter_convert( 383 const struct rte_eth_ethertype_filter *input, 384 struct i40e_ethertype_filter *filter); 385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf, 386 struct i40e_ethertype_filter *filter); 387 388 static int i40e_tunnel_filter_convert( 389 struct i40e_aqc_cloud_filters_element_bb *cld_filter, 390 struct i40e_tunnel_filter *tunnel_filter); 391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, 392 struct i40e_tunnel_filter *tunnel_filter); 393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf); 394 395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf); 396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf); 397 static void i40e_filter_restore(struct i40e_pf *pf); 398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev); 399 400 int i40e_logtype_init; 401 int i40e_logtype_driver; 402 403 static const char *const valid_keys[] = { 404 ETH_I40E_FLOATING_VEB_ARG, 405 ETH_I40E_FLOATING_VEB_LIST_ARG, 406 ETH_I40E_SUPPORT_MULTI_DRIVER, 407 ETH_I40E_QUEUE_NUM_PER_VF_ARG, 408 ETH_I40E_USE_LATEST_VEC, 409 NULL}; 410 411 static const struct rte_pci_id pci_id_i40e_map[] = { 412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) }, 413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) }, 414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) }, 415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) }, 416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) }, 417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) }, 418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) }, 419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) }, 420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) }, 421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) }, 422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) }, 423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) }, 424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) }, 425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) }, 426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) }, 427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) }, 428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) }, 429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) }, 430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) }, 431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) }, 432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) }, 433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) }, 434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) }, 435 { .vendor_id = 0, /* sentinel */ }, 436 }; 437 438 static const struct eth_dev_ops i40e_eth_dev_ops = { 439 .dev_configure = i40e_dev_configure, 440 .dev_start = i40e_dev_start, 441 .dev_stop = i40e_dev_stop, 442 .dev_close = i40e_dev_close, 443 .dev_reset = i40e_dev_reset, 444 .promiscuous_enable = i40e_dev_promiscuous_enable, 445 .promiscuous_disable = i40e_dev_promiscuous_disable, 446 .allmulticast_enable = i40e_dev_allmulticast_enable, 447 .allmulticast_disable = i40e_dev_allmulticast_disable, 448 .dev_set_link_up = i40e_dev_set_link_up, 449 .dev_set_link_down = i40e_dev_set_link_down, 450 .link_update = i40e_dev_link_update, 451 .stats_get = i40e_dev_stats_get, 452 .xstats_get = i40e_dev_xstats_get, 453 .xstats_get_names = i40e_dev_xstats_get_names, 454 .stats_reset = i40e_dev_stats_reset, 455 .xstats_reset = i40e_dev_stats_reset, 456 .fw_version_get = i40e_fw_version_get, 457 .dev_infos_get = i40e_dev_info_get, 458 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get, 459 .vlan_filter_set = i40e_vlan_filter_set, 460 .vlan_tpid_set = i40e_vlan_tpid_set, 461 .vlan_offload_set = i40e_vlan_offload_set, 462 .vlan_strip_queue_set = i40e_vlan_strip_queue_set, 463 .vlan_pvid_set = i40e_vlan_pvid_set, 464 .rx_queue_start = i40e_dev_rx_queue_start, 465 .rx_queue_stop = i40e_dev_rx_queue_stop, 466 .tx_queue_start = i40e_dev_tx_queue_start, 467 .tx_queue_stop = i40e_dev_tx_queue_stop, 468 .rx_queue_setup = i40e_dev_rx_queue_setup, 469 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable, 470 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable, 471 .rx_queue_release = i40e_dev_rx_queue_release, 472 .rx_queue_count = i40e_dev_rx_queue_count, 473 .rx_descriptor_done = i40e_dev_rx_descriptor_done, 474 .rx_descriptor_status = i40e_dev_rx_descriptor_status, 475 .tx_descriptor_status = i40e_dev_tx_descriptor_status, 476 .tx_queue_setup = i40e_dev_tx_queue_setup, 477 .tx_queue_release = i40e_dev_tx_queue_release, 478 .dev_led_on = i40e_dev_led_on, 479 .dev_led_off = i40e_dev_led_off, 480 .flow_ctrl_get = i40e_flow_ctrl_get, 481 .flow_ctrl_set = i40e_flow_ctrl_set, 482 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set, 483 .mac_addr_add = i40e_macaddr_add, 484 .mac_addr_remove = i40e_macaddr_remove, 485 .reta_update = i40e_dev_rss_reta_update, 486 .reta_query = i40e_dev_rss_reta_query, 487 .rss_hash_update = i40e_dev_rss_hash_update, 488 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get, 489 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add, 490 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del, 491 .filter_ctrl = i40e_dev_filter_ctrl, 492 .rxq_info_get = i40e_rxq_info_get, 493 .txq_info_get = i40e_txq_info_get, 494 .mirror_rule_set = i40e_mirror_rule_set, 495 .mirror_rule_reset = i40e_mirror_rule_reset, 496 .timesync_enable = i40e_timesync_enable, 497 .timesync_disable = i40e_timesync_disable, 498 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp, 499 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp, 500 .get_dcb_info = i40e_dev_get_dcb_info, 501 .timesync_adjust_time = i40e_timesync_adjust_time, 502 .timesync_read_time = i40e_timesync_read_time, 503 .timesync_write_time = i40e_timesync_write_time, 504 .get_reg = i40e_get_regs, 505 .get_eeprom_length = i40e_get_eeprom_length, 506 .get_eeprom = i40e_get_eeprom, 507 .get_module_info = i40e_get_module_info, 508 .get_module_eeprom = i40e_get_module_eeprom, 509 .mac_addr_set = i40e_set_default_mac_addr, 510 .mtu_set = i40e_dev_mtu_set, 511 .tm_ops_get = i40e_tm_ops_get, 512 }; 513 514 /* store statistics names and its offset in stats structure */ 515 struct rte_i40e_xstats_name_off { 516 char name[RTE_ETH_XSTATS_NAME_SIZE]; 517 unsigned offset; 518 }; 519 520 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = { 521 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)}, 522 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)}, 523 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)}, 524 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)}, 525 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats, 526 rx_unknown_protocol)}, 527 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)}, 528 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)}, 529 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)}, 530 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)}, 531 }; 532 533 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \ 534 sizeof(rte_i40e_stats_strings[0])) 535 536 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = { 537 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats, 538 tx_dropped_link_down)}, 539 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)}, 540 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats, 541 illegal_bytes)}, 542 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)}, 543 {"mac_local_errors", offsetof(struct i40e_hw_port_stats, 544 mac_local_faults)}, 545 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats, 546 mac_remote_faults)}, 547 {"rx_length_errors", offsetof(struct i40e_hw_port_stats, 548 rx_length_errors)}, 549 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)}, 550 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)}, 551 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)}, 552 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)}, 553 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)}, 554 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats, 555 rx_size_127)}, 556 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats, 557 rx_size_255)}, 558 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats, 559 rx_size_511)}, 560 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats, 561 rx_size_1023)}, 562 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats, 563 rx_size_1522)}, 564 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats, 565 rx_size_big)}, 566 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats, 567 rx_undersize)}, 568 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats, 569 rx_oversize)}, 570 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats, 571 mac_short_packet_dropped)}, 572 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats, 573 rx_fragments)}, 574 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)}, 575 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)}, 576 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats, 577 tx_size_127)}, 578 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats, 579 tx_size_255)}, 580 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats, 581 tx_size_511)}, 582 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats, 583 tx_size_1023)}, 584 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats, 585 tx_size_1522)}, 586 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats, 587 tx_size_big)}, 588 {"rx_flow_director_atr_match_packets", 589 offsetof(struct i40e_hw_port_stats, fd_atr_match)}, 590 {"rx_flow_director_sb_match_packets", 591 offsetof(struct i40e_hw_port_stats, fd_sb_match)}, 592 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats, 593 tx_lpi_status)}, 594 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats, 595 rx_lpi_status)}, 596 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats, 597 tx_lpi_count)}, 598 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats, 599 rx_lpi_count)}, 600 }; 601 602 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \ 603 sizeof(rte_i40e_hw_port_strings[0])) 604 605 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = { 606 {"xon_packets", offsetof(struct i40e_hw_port_stats, 607 priority_xon_rx)}, 608 {"xoff_packets", offsetof(struct i40e_hw_port_stats, 609 priority_xoff_rx)}, 610 }; 611 612 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \ 613 sizeof(rte_i40e_rxq_prio_strings[0])) 614 615 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = { 616 {"xon_packets", offsetof(struct i40e_hw_port_stats, 617 priority_xon_tx)}, 618 {"xoff_packets", offsetof(struct i40e_hw_port_stats, 619 priority_xoff_tx)}, 620 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats, 621 priority_xon_2_xoff)}, 622 }; 623 624 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \ 625 sizeof(rte_i40e_txq_prio_strings[0])) 626 627 static int 628 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 629 struct rte_pci_device *pci_dev) 630 { 631 char name[RTE_ETH_NAME_MAX_LEN]; 632 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 633 int i, retval; 634 635 if (pci_dev->device.devargs) { 636 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 637 ð_da); 638 if (retval) 639 return retval; 640 } 641 642 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 643 sizeof(struct i40e_adapter), 644 eth_dev_pci_specific_init, pci_dev, 645 eth_i40e_dev_init, NULL); 646 647 if (retval || eth_da.nb_representor_ports < 1) 648 return retval; 649 650 /* probe VF representor ports */ 651 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated( 652 pci_dev->device.name); 653 654 if (pf_ethdev == NULL) 655 return -ENODEV; 656 657 for (i = 0; i < eth_da.nb_representor_ports; i++) { 658 struct i40e_vf_representor representor = { 659 .vf_id = eth_da.representor_ports[i], 660 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF( 661 pf_ethdev->data->dev_private)->switch_domain_id, 662 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER( 663 pf_ethdev->data->dev_private) 664 }; 665 666 /* representor port net_bdf_port */ 667 snprintf(name, sizeof(name), "net_%s_representor_%d", 668 pci_dev->device.name, eth_da.representor_ports[i]); 669 670 retval = rte_eth_dev_create(&pci_dev->device, name, 671 sizeof(struct i40e_vf_representor), NULL, NULL, 672 i40e_vf_representor_init, &representor); 673 674 if (retval) 675 PMD_DRV_LOG(ERR, "failed to create i40e vf " 676 "representor %s.", name); 677 } 678 679 return 0; 680 } 681 682 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev) 683 { 684 struct rte_eth_dev *ethdev; 685 686 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 687 if (!ethdev) 688 return -ENODEV; 689 690 691 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 692 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit); 693 else 694 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit); 695 } 696 697 static struct rte_pci_driver rte_i40e_pmd = { 698 .id_table = pci_id_i40e_map, 699 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 700 .probe = eth_i40e_pci_probe, 701 .remove = eth_i40e_pci_remove, 702 }; 703 704 static inline void 705 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr, 706 uint32_t reg_val) 707 { 708 uint32_t ori_reg_val; 709 struct rte_eth_dev *dev; 710 711 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr); 712 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 713 i40e_write_rx_ctl(hw, reg_addr, reg_val); 714 if (ori_reg_val != reg_val) 715 PMD_DRV_LOG(WARNING, 716 "i40e device %s changed global register [0x%08x]." 717 " original: 0x%08x, new: 0x%08x", 718 dev->device->name, reg_addr, ori_reg_val, reg_val); 719 } 720 721 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd); 722 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map); 723 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci"); 724 725 #ifndef I40E_GLQF_ORT 726 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) 727 #endif 728 #ifndef I40E_GLQF_PIT 729 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) 730 #endif 731 #ifndef I40E_GLQF_L3_MAP 732 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4)) 733 #endif 734 735 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) 736 { 737 /* 738 * Initialize registers for parsing packet type of QinQ 739 * This should be removed from code once proper 740 * configuration API is added to avoid configuration conflicts 741 * between ports of the same device. 742 */ 743 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029); 744 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420); 745 } 746 747 static inline void i40e_config_automask(struct i40e_pf *pf) 748 { 749 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 750 uint32_t val; 751 752 /* INTENA flag is not auto-cleared for interrupt */ 753 val = I40E_READ_REG(hw, I40E_GLINT_CTL); 754 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK | 755 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK; 756 757 /* If support multi-driver, PF will use INT0. */ 758 if (!pf->support_multi_driver) 759 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK; 760 761 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val); 762 } 763 764 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808 765 766 /* 767 * Add a ethertype filter to drop all flow control frames transmitted 768 * from VSIs. 769 */ 770 static void 771 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf) 772 { 773 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 774 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 775 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 776 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 777 int ret; 778 779 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL, 780 I40E_FLOW_CONTROL_ETHERTYPE, flags, 781 pf->main_vsi_seid, 0, 782 TRUE, NULL, NULL); 783 if (ret) 784 PMD_INIT_LOG(ERR, 785 "Failed to add filter to drop flow control frames from VSIs."); 786 } 787 788 static int 789 floating_veb_list_handler(__rte_unused const char *key, 790 const char *floating_veb_value, 791 void *opaque) 792 { 793 int idx = 0; 794 unsigned int count = 0; 795 char *end = NULL; 796 int min, max; 797 bool *vf_floating_veb = opaque; 798 799 while (isblank(*floating_veb_value)) 800 floating_veb_value++; 801 802 /* Reset floating VEB configuration for VFs */ 803 for (idx = 0; idx < I40E_MAX_VF; idx++) 804 vf_floating_veb[idx] = false; 805 806 min = I40E_MAX_VF; 807 do { 808 while (isblank(*floating_veb_value)) 809 floating_veb_value++; 810 if (*floating_veb_value == '\0') 811 return -1; 812 errno = 0; 813 idx = strtoul(floating_veb_value, &end, 10); 814 if (errno || end == NULL) 815 return -1; 816 while (isblank(*end)) 817 end++; 818 if (*end == '-') { 819 min = idx; 820 } else if ((*end == ';') || (*end == '\0')) { 821 max = idx; 822 if (min == I40E_MAX_VF) 823 min = idx; 824 if (max >= I40E_MAX_VF) 825 max = I40E_MAX_VF - 1; 826 for (idx = min; idx <= max; idx++) { 827 vf_floating_veb[idx] = true; 828 count++; 829 } 830 min = I40E_MAX_VF; 831 } else { 832 return -1; 833 } 834 floating_veb_value = end + 1; 835 } while (*end != '\0'); 836 837 if (count == 0) 838 return -1; 839 840 return 0; 841 } 842 843 static void 844 config_vf_floating_veb(struct rte_devargs *devargs, 845 uint16_t floating_veb, 846 bool *vf_floating_veb) 847 { 848 struct rte_kvargs *kvlist; 849 int i; 850 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG; 851 852 if (!floating_veb) 853 return; 854 /* All the VFs attach to the floating VEB by default 855 * when the floating VEB is enabled. 856 */ 857 for (i = 0; i < I40E_MAX_VF; i++) 858 vf_floating_veb[i] = true; 859 860 if (devargs == NULL) 861 return; 862 863 kvlist = rte_kvargs_parse(devargs->args, valid_keys); 864 if (kvlist == NULL) 865 return; 866 867 if (!rte_kvargs_count(kvlist, floating_veb_list)) { 868 rte_kvargs_free(kvlist); 869 return; 870 } 871 /* When the floating_veb_list parameter exists, all the VFs 872 * will attach to the legacy VEB firstly, then configure VFs 873 * to the floating VEB according to the floating_veb_list. 874 */ 875 if (rte_kvargs_process(kvlist, floating_veb_list, 876 floating_veb_list_handler, 877 vf_floating_veb) < 0) { 878 rte_kvargs_free(kvlist); 879 return; 880 } 881 rte_kvargs_free(kvlist); 882 } 883 884 static int 885 i40e_check_floating_handler(__rte_unused const char *key, 886 const char *value, 887 __rte_unused void *opaque) 888 { 889 if (strcmp(value, "1")) 890 return -1; 891 892 return 0; 893 } 894 895 static int 896 is_floating_veb_supported(struct rte_devargs *devargs) 897 { 898 struct rte_kvargs *kvlist; 899 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG; 900 901 if (devargs == NULL) 902 return 0; 903 904 kvlist = rte_kvargs_parse(devargs->args, valid_keys); 905 if (kvlist == NULL) 906 return 0; 907 908 if (!rte_kvargs_count(kvlist, floating_veb_key)) { 909 rte_kvargs_free(kvlist); 910 return 0; 911 } 912 /* Floating VEB is enabled when there's key-value: 913 * enable_floating_veb=1 914 */ 915 if (rte_kvargs_process(kvlist, floating_veb_key, 916 i40e_check_floating_handler, NULL) < 0) { 917 rte_kvargs_free(kvlist); 918 return 0; 919 } 920 rte_kvargs_free(kvlist); 921 922 return 1; 923 } 924 925 static void 926 config_floating_veb(struct rte_eth_dev *dev) 927 { 928 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 931 932 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list)); 933 934 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) { 935 pf->floating_veb = 936 is_floating_veb_supported(pci_dev->device.devargs); 937 config_vf_floating_veb(pci_dev->device.devargs, 938 pf->floating_veb, 939 pf->floating_veb_list); 940 } else { 941 pf->floating_veb = false; 942 } 943 } 944 945 #define I40E_L2_TAGS_S_TAG_SHIFT 1 946 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT) 947 948 static int 949 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev) 950 { 951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 952 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 953 char ethertype_hash_name[RTE_HASH_NAMESIZE]; 954 int ret; 955 956 struct rte_hash_parameters ethertype_hash_params = { 957 .name = ethertype_hash_name, 958 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM, 959 .key_len = sizeof(struct i40e_ethertype_filter_input), 960 .hash_func = rte_hash_crc, 961 .hash_func_init_val = 0, 962 .socket_id = rte_socket_id(), 963 }; 964 965 /* Initialize ethertype filter rule list and hash */ 966 TAILQ_INIT(ðertype_rule->ethertype_list); 967 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE, 968 "ethertype_%s", dev->device->name); 969 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params); 970 if (!ethertype_rule->hash_table) { 971 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!"); 972 return -EINVAL; 973 } 974 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map", 975 sizeof(struct i40e_ethertype_filter *) * 976 I40E_MAX_ETHERTYPE_FILTER_NUM, 977 0); 978 if (!ethertype_rule->hash_map) { 979 PMD_INIT_LOG(ERR, 980 "Failed to allocate memory for ethertype hash map!"); 981 ret = -ENOMEM; 982 goto err_ethertype_hash_map_alloc; 983 } 984 985 return 0; 986 987 err_ethertype_hash_map_alloc: 988 rte_hash_free(ethertype_rule->hash_table); 989 990 return ret; 991 } 992 993 static int 994 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev) 995 { 996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 997 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 998 char tunnel_hash_name[RTE_HASH_NAMESIZE]; 999 int ret; 1000 1001 struct rte_hash_parameters tunnel_hash_params = { 1002 .name = tunnel_hash_name, 1003 .entries = I40E_MAX_TUNNEL_FILTER_NUM, 1004 .key_len = sizeof(struct i40e_tunnel_filter_input), 1005 .hash_func = rte_hash_crc, 1006 .hash_func_init_val = 0, 1007 .socket_id = rte_socket_id(), 1008 }; 1009 1010 /* Initialize tunnel filter rule list and hash */ 1011 TAILQ_INIT(&tunnel_rule->tunnel_list); 1012 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE, 1013 "tunnel_%s", dev->device->name); 1014 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params); 1015 if (!tunnel_rule->hash_table) { 1016 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!"); 1017 return -EINVAL; 1018 } 1019 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map", 1020 sizeof(struct i40e_tunnel_filter *) * 1021 I40E_MAX_TUNNEL_FILTER_NUM, 1022 0); 1023 if (!tunnel_rule->hash_map) { 1024 PMD_INIT_LOG(ERR, 1025 "Failed to allocate memory for tunnel hash map!"); 1026 ret = -ENOMEM; 1027 goto err_tunnel_hash_map_alloc; 1028 } 1029 1030 return 0; 1031 1032 err_tunnel_hash_map_alloc: 1033 rte_hash_free(tunnel_rule->hash_table); 1034 1035 return ret; 1036 } 1037 1038 static int 1039 i40e_init_fdir_filter_list(struct rte_eth_dev *dev) 1040 { 1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1042 struct i40e_fdir_info *fdir_info = &pf->fdir; 1043 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1044 int ret; 1045 1046 struct rte_hash_parameters fdir_hash_params = { 1047 .name = fdir_hash_name, 1048 .entries = I40E_MAX_FDIR_FILTER_NUM, 1049 .key_len = sizeof(struct i40e_fdir_input), 1050 .hash_func = rte_hash_crc, 1051 .hash_func_init_val = 0, 1052 .socket_id = rte_socket_id(), 1053 }; 1054 1055 /* Initialize flow director filter rule list and hash */ 1056 TAILQ_INIT(&fdir_info->fdir_list); 1057 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1058 "fdir_%s", dev->device->name); 1059 fdir_info->hash_table = rte_hash_create(&fdir_hash_params); 1060 if (!fdir_info->hash_table) { 1061 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1062 return -EINVAL; 1063 } 1064 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map", 1065 sizeof(struct i40e_fdir_filter *) * 1066 I40E_MAX_FDIR_FILTER_NUM, 1067 0); 1068 if (!fdir_info->hash_map) { 1069 PMD_INIT_LOG(ERR, 1070 "Failed to allocate memory for fdir hash map!"); 1071 ret = -ENOMEM; 1072 goto err_fdir_hash_map_alloc; 1073 } 1074 return 0; 1075 1076 err_fdir_hash_map_alloc: 1077 rte_hash_free(fdir_info->hash_table); 1078 1079 return ret; 1080 } 1081 1082 static void 1083 i40e_init_customized_info(struct i40e_pf *pf) 1084 { 1085 int i; 1086 1087 /* Initialize customized pctype */ 1088 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) { 1089 pf->customized_pctype[i].index = i; 1090 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID; 1091 pf->customized_pctype[i].valid = false; 1092 } 1093 1094 pf->gtp_support = false; 1095 } 1096 1097 void 1098 i40e_init_queue_region_conf(struct rte_eth_dev *dev) 1099 { 1100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1101 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1102 struct i40e_queue_regions *info = &pf->queue_region; 1103 uint16_t i; 1104 1105 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++) 1106 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0); 1107 1108 memset(info, 0, sizeof(struct i40e_queue_regions)); 1109 } 1110 1111 static int 1112 i40e_parse_multi_drv_handler(__rte_unused const char *key, 1113 const char *value, 1114 void *opaque) 1115 { 1116 struct i40e_pf *pf; 1117 unsigned long support_multi_driver; 1118 char *end; 1119 1120 pf = (struct i40e_pf *)opaque; 1121 1122 errno = 0; 1123 support_multi_driver = strtoul(value, &end, 10); 1124 if (errno != 0 || end == value || *end != 0) { 1125 PMD_DRV_LOG(WARNING, "Wrong global configuration"); 1126 return -(EINVAL); 1127 } 1128 1129 if (support_multi_driver == 1 || support_multi_driver == 0) 1130 pf->support_multi_driver = (bool)support_multi_driver; 1131 else 1132 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,", 1133 "enable global configuration by default." 1134 ETH_I40E_SUPPORT_MULTI_DRIVER); 1135 return 0; 1136 } 1137 1138 static int 1139 i40e_support_multi_driver(struct rte_eth_dev *dev) 1140 { 1141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1142 struct rte_kvargs *kvlist; 1143 int kvargs_count; 1144 1145 /* Enable global configuration by default */ 1146 pf->support_multi_driver = false; 1147 1148 if (!dev->device->devargs) 1149 return 0; 1150 1151 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1152 if (!kvlist) 1153 return -EINVAL; 1154 1155 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER); 1156 if (!kvargs_count) { 1157 rte_kvargs_free(kvlist); 1158 return 0; 1159 } 1160 1161 if (kvargs_count > 1) 1162 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 1163 "the first invalid or last valid one is used !", 1164 ETH_I40E_SUPPORT_MULTI_DRIVER); 1165 1166 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER, 1167 i40e_parse_multi_drv_handler, pf) < 0) { 1168 rte_kvargs_free(kvlist); 1169 return -EINVAL; 1170 } 1171 1172 rte_kvargs_free(kvlist); 1173 return 0; 1174 } 1175 1176 static int 1177 i40e_aq_debug_write_global_register(struct i40e_hw *hw, 1178 uint32_t reg_addr, uint64_t reg_val, 1179 struct i40e_asq_cmd_details *cmd_details) 1180 { 1181 uint64_t ori_reg_val; 1182 struct rte_eth_dev *dev; 1183 int ret; 1184 1185 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL); 1186 if (ret != I40E_SUCCESS) { 1187 PMD_DRV_LOG(ERR, 1188 "Fail to debug read from 0x%08x", 1189 reg_addr); 1190 return -EIO; 1191 } 1192 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 1193 1194 if (ori_reg_val != reg_val) 1195 PMD_DRV_LOG(WARNING, 1196 "i40e device %s changed global register [0x%08x]." 1197 " original: 0x%"PRIx64", after: 0x%"PRIx64, 1198 dev->device->name, reg_addr, ori_reg_val, reg_val); 1199 1200 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details); 1201 } 1202 1203 static int 1204 i40e_parse_latest_vec_handler(__rte_unused const char *key, 1205 const char *value, 1206 void *opaque) 1207 { 1208 struct i40e_adapter *ad = opaque; 1209 int use_latest_vec; 1210 1211 use_latest_vec = atoi(value); 1212 1213 if (use_latest_vec != 0 && use_latest_vec != 1) 1214 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!"); 1215 1216 ad->use_latest_vec = (uint8_t)use_latest_vec; 1217 1218 return 0; 1219 } 1220 1221 static int 1222 i40e_use_latest_vec(struct rte_eth_dev *dev) 1223 { 1224 struct i40e_adapter *ad = 1225 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1226 struct rte_kvargs *kvlist; 1227 int kvargs_count; 1228 1229 ad->use_latest_vec = false; 1230 1231 if (!dev->device->devargs) 1232 return 0; 1233 1234 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1235 if (!kvlist) 1236 return -EINVAL; 1237 1238 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC); 1239 if (!kvargs_count) { 1240 rte_kvargs_free(kvlist); 1241 return 0; 1242 } 1243 1244 if (kvargs_count > 1) 1245 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 1246 "the first invalid or last valid one is used !", 1247 ETH_I40E_USE_LATEST_VEC); 1248 1249 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC, 1250 i40e_parse_latest_vec_handler, ad) < 0) { 1251 rte_kvargs_free(kvlist); 1252 return -EINVAL; 1253 } 1254 1255 rte_kvargs_free(kvlist); 1256 return 0; 1257 } 1258 1259 #define I40E_ALARM_INTERVAL 50000 /* us */ 1260 1261 static int 1262 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) 1263 { 1264 struct rte_pci_device *pci_dev; 1265 struct rte_intr_handle *intr_handle; 1266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1268 struct i40e_vsi *vsi; 1269 int ret; 1270 uint32_t len, val; 1271 uint8_t aq_fail = 0; 1272 1273 PMD_INIT_FUNC_TRACE(); 1274 1275 dev->dev_ops = &i40e_eth_dev_ops; 1276 dev->rx_pkt_burst = i40e_recv_pkts; 1277 dev->tx_pkt_burst = i40e_xmit_pkts; 1278 dev->tx_pkt_prepare = i40e_prep_pkts; 1279 1280 /* for secondary processes, we don't initialise any further as primary 1281 * has already done this work. Only check we don't need a different 1282 * RX function */ 1283 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 1284 i40e_set_rx_function(dev); 1285 i40e_set_tx_function(dev); 1286 return 0; 1287 } 1288 i40e_set_default_ptype_table(dev); 1289 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1290 intr_handle = &pci_dev->intr_handle; 1291 1292 rte_eth_copy_pci_info(dev, pci_dev); 1293 1294 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1295 pf->adapter->eth_dev = dev; 1296 pf->dev_data = dev->data; 1297 1298 hw->back = I40E_PF_TO_ADAPTER(pf); 1299 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr); 1300 if (!hw->hw_addr) { 1301 PMD_INIT_LOG(ERR, 1302 "Hardware is not available, as address is NULL"); 1303 return -ENODEV; 1304 } 1305 1306 hw->vendor_id = pci_dev->id.vendor_id; 1307 hw->device_id = pci_dev->id.device_id; 1308 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1309 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1310 hw->bus.device = pci_dev->addr.devid; 1311 hw->bus.func = pci_dev->addr.function; 1312 hw->adapter_stopped = 0; 1313 hw->adapter_closed = 0; 1314 1315 /* 1316 * Switch Tag value should not be identical to either the First Tag 1317 * or Second Tag values. So set something other than common Ethertype 1318 * for internal switching. 1319 */ 1320 hw->switch_tag = 0xffff; 1321 1322 val = I40E_READ_REG(hw, I40E_GL_FWSTS); 1323 if (val & I40E_GL_FWSTS_FWS1B_MASK) { 1324 PMD_INIT_LOG(ERR, "\nERROR: " 1325 "Firmware recovery mode detected. Limiting functionality.\n" 1326 "Refer to the Intel(R) Ethernet Adapters and Devices " 1327 "User Guide for details on firmware recovery mode."); 1328 return -EIO; 1329 } 1330 1331 /* Check if need to support multi-driver */ 1332 i40e_support_multi_driver(dev); 1333 /* Check if users want the latest supported vec path */ 1334 i40e_use_latest_vec(dev); 1335 1336 /* Make sure all is clean before doing PF reset */ 1337 i40e_clear_hw(hw); 1338 1339 /* Reset here to make sure all is clean for each PF */ 1340 ret = i40e_pf_reset(hw); 1341 if (ret) { 1342 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret); 1343 return ret; 1344 } 1345 1346 /* Initialize the shared code (base driver) */ 1347 ret = i40e_init_shared_code(hw); 1348 if (ret) { 1349 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret); 1350 return ret; 1351 } 1352 1353 /* Initialize the parameters for adminq */ 1354 i40e_init_adminq_parameter(hw); 1355 ret = i40e_init_adminq(hw); 1356 if (ret != I40E_SUCCESS) { 1357 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret); 1358 return -EIO; 1359 } 1360 /* Firmware of SFP x722 does not support adminq option */ 1361 if (hw->device_id == I40E_DEV_ID_SFP_X722) 1362 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE; 1363 1364 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x", 1365 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 1366 hw->aq.api_maj_ver, hw->aq.api_min_ver, 1367 ((hw->nvm.version >> 12) & 0xf), 1368 ((hw->nvm.version >> 4) & 0xff), 1369 (hw->nvm.version & 0xf), hw->nvm.eetrack); 1370 1371 /* Initialize the hardware */ 1372 i40e_hw_init(dev); 1373 1374 i40e_config_automask(pf); 1375 1376 i40e_set_default_pctype_table(dev); 1377 1378 /* 1379 * To work around the NVM issue, initialize registers 1380 * for packet type of QinQ by software. 1381 * It should be removed once issues are fixed in NVM. 1382 */ 1383 if (!pf->support_multi_driver) 1384 i40e_GLQF_reg_init(hw); 1385 1386 /* Initialize the input set for filters (hash and fd) to default value */ 1387 i40e_filter_input_set_init(pf); 1388 1389 /* initialise the L3_MAP register */ 1390 if (!pf->support_multi_driver) { 1391 ret = i40e_aq_debug_write_global_register(hw, 1392 I40E_GLQF_L3_MAP(40), 1393 0x00000028, NULL); 1394 if (ret) 1395 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", 1396 ret); 1397 PMD_INIT_LOG(DEBUG, 1398 "Global register 0x%08x is changed with 0x28", 1399 I40E_GLQF_L3_MAP(40)); 1400 } 1401 1402 /* Need the special FW version to support floating VEB */ 1403 config_floating_veb(dev); 1404 /* Clear PXE mode */ 1405 i40e_clear_pxe_mode(hw); 1406 i40e_dev_sync_phy_type(hw); 1407 1408 /* 1409 * On X710, performance number is far from the expectation on recent 1410 * firmware versions. The fix for this issue may not be integrated in 1411 * the following firmware version. So the workaround in software driver 1412 * is needed. It needs to modify the initial values of 3 internal only 1413 * registers. Note that the workaround can be removed when it is fixed 1414 * in firmware in the future. 1415 */ 1416 i40e_configure_registers(hw); 1417 1418 /* Get hw capabilities */ 1419 ret = i40e_get_cap(hw); 1420 if (ret != I40E_SUCCESS) { 1421 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret); 1422 goto err_get_capabilities; 1423 } 1424 1425 /* Initialize parameters for PF */ 1426 ret = i40e_pf_parameter_init(dev); 1427 if (ret != 0) { 1428 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret); 1429 goto err_parameter_init; 1430 } 1431 1432 /* Initialize the queue management */ 1433 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp); 1434 if (ret < 0) { 1435 PMD_INIT_LOG(ERR, "Failed to init queue pool"); 1436 goto err_qp_pool_init; 1437 } 1438 ret = i40e_res_pool_init(&pf->msix_pool, 1, 1439 hw->func_caps.num_msix_vectors - 1); 1440 if (ret < 0) { 1441 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 1442 goto err_msix_pool_init; 1443 } 1444 1445 /* Initialize lan hmc */ 1446 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 1447 hw->func_caps.num_rx_qp, 0, 0); 1448 if (ret != I40E_SUCCESS) { 1449 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret); 1450 goto err_init_lan_hmc; 1451 } 1452 1453 /* Configure lan hmc */ 1454 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 1455 if (ret != I40E_SUCCESS) { 1456 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret); 1457 goto err_configure_lan_hmc; 1458 } 1459 1460 /* Get and check the mac address */ 1461 i40e_get_mac_addr(hw, hw->mac.addr); 1462 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) { 1463 PMD_INIT_LOG(ERR, "mac address is not valid"); 1464 ret = -EIO; 1465 goto err_get_mac_addr; 1466 } 1467 /* Copy the permanent MAC address */ 1468 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, 1469 (struct rte_ether_addr *)hw->mac.perm_addr); 1470 1471 /* Disable flow control */ 1472 hw->fc.requested_mode = I40E_FC_NONE; 1473 i40e_set_fc(hw, &aq_fail, TRUE); 1474 1475 /* Set the global registers with default ether type value */ 1476 if (!pf->support_multi_driver) { 1477 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 1478 RTE_ETHER_TYPE_VLAN); 1479 if (ret != I40E_SUCCESS) { 1480 PMD_INIT_LOG(ERR, 1481 "Failed to set the default outer " 1482 "VLAN ether type"); 1483 goto err_setup_pf_switch; 1484 } 1485 } 1486 1487 /* PF setup, which includes VSI setup */ 1488 ret = i40e_pf_setup(pf); 1489 if (ret) { 1490 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret); 1491 goto err_setup_pf_switch; 1492 } 1493 1494 vsi = pf->main_vsi; 1495 1496 /* Disable double vlan by default */ 1497 i40e_vsi_config_double_vlan(vsi, FALSE); 1498 1499 /* Disable S-TAG identification when floating_veb is disabled */ 1500 if (!pf->floating_veb) { 1501 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN); 1502 if (ret & I40E_L2_TAGS_S_TAG_MASK) { 1503 ret &= ~I40E_L2_TAGS_S_TAG_MASK; 1504 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret); 1505 } 1506 } 1507 1508 if (!vsi->max_macaddrs) 1509 len = RTE_ETHER_ADDR_LEN; 1510 else 1511 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs; 1512 1513 /* Should be after VSI initialized */ 1514 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0); 1515 if (!dev->data->mac_addrs) { 1516 PMD_INIT_LOG(ERR, 1517 "Failed to allocated memory for storing mac address"); 1518 goto err_mac_alloc; 1519 } 1520 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1521 &dev->data->mac_addrs[0]); 1522 1523 /* Init dcb to sw mode by default */ 1524 ret = i40e_dcb_init_configure(dev, TRUE); 1525 if (ret != I40E_SUCCESS) { 1526 PMD_INIT_LOG(INFO, "Failed to init dcb."); 1527 pf->flags &= ~I40E_FLAG_DCB; 1528 } 1529 /* Update HW struct after DCB configuration */ 1530 i40e_get_cap(hw); 1531 1532 /* initialize pf host driver to setup SRIOV resource if applicable */ 1533 i40e_pf_host_init(dev); 1534 1535 /* register callback func to eal lib */ 1536 rte_intr_callback_register(intr_handle, 1537 i40e_dev_interrupt_handler, dev); 1538 1539 /* configure and enable device interrupt */ 1540 i40e_pf_config_irq0(hw, TRUE); 1541 i40e_pf_enable_irq0(hw); 1542 1543 /* enable uio intr after callback register */ 1544 rte_intr_enable(intr_handle); 1545 1546 /* By default disable flexible payload in global configuration */ 1547 if (!pf->support_multi_driver) 1548 i40e_flex_payload_reg_set_default(hw); 1549 1550 /* 1551 * Add an ethertype filter to drop all flow control frames transmitted 1552 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC 1553 * frames to wire. 1554 */ 1555 i40e_add_tx_flow_control_drop_filter(pf); 1556 1557 /* Set the max frame size to 0x2600 by default, 1558 * in case other drivers changed the default value. 1559 */ 1560 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL); 1561 1562 /* initialize mirror rule list */ 1563 TAILQ_INIT(&pf->mirror_list); 1564 1565 /* initialize Traffic Manager configuration */ 1566 i40e_tm_conf_init(dev); 1567 1568 /* Initialize customized information */ 1569 i40e_init_customized_info(pf); 1570 1571 ret = i40e_init_ethtype_filter_list(dev); 1572 if (ret < 0) 1573 goto err_init_ethtype_filter_list; 1574 ret = i40e_init_tunnel_filter_list(dev); 1575 if (ret < 0) 1576 goto err_init_tunnel_filter_list; 1577 ret = i40e_init_fdir_filter_list(dev); 1578 if (ret < 0) 1579 goto err_init_fdir_filter_list; 1580 1581 /* initialize queue region configuration */ 1582 i40e_init_queue_region_conf(dev); 1583 1584 /* initialize rss configuration from rte_flow */ 1585 memset(&pf->rss_info, 0, 1586 sizeof(struct i40e_rte_flow_rss_conf)); 1587 1588 /* reset all stats of the device, including pf and main vsi */ 1589 i40e_dev_stats_reset(dev); 1590 1591 return 0; 1592 1593 err_init_fdir_filter_list: 1594 rte_free(pf->tunnel.hash_table); 1595 rte_free(pf->tunnel.hash_map); 1596 err_init_tunnel_filter_list: 1597 rte_free(pf->ethertype.hash_table); 1598 rte_free(pf->ethertype.hash_map); 1599 err_init_ethtype_filter_list: 1600 rte_free(dev->data->mac_addrs); 1601 dev->data->mac_addrs = NULL; 1602 err_mac_alloc: 1603 i40e_vsi_release(pf->main_vsi); 1604 err_setup_pf_switch: 1605 err_get_mac_addr: 1606 err_configure_lan_hmc: 1607 (void)i40e_shutdown_lan_hmc(hw); 1608 err_init_lan_hmc: 1609 i40e_res_pool_destroy(&pf->msix_pool); 1610 err_msix_pool_init: 1611 i40e_res_pool_destroy(&pf->qp_pool); 1612 err_qp_pool_init: 1613 err_parameter_init: 1614 err_get_capabilities: 1615 (void)i40e_shutdown_adminq(hw); 1616 1617 return ret; 1618 } 1619 1620 static void 1621 i40e_rm_ethtype_filter_list(struct i40e_pf *pf) 1622 { 1623 struct i40e_ethertype_filter *p_ethertype; 1624 struct i40e_ethertype_rule *ethertype_rule; 1625 1626 ethertype_rule = &pf->ethertype; 1627 /* Remove all ethertype filter rules and hash */ 1628 if (ethertype_rule->hash_map) 1629 rte_free(ethertype_rule->hash_map); 1630 if (ethertype_rule->hash_table) 1631 rte_hash_free(ethertype_rule->hash_table); 1632 1633 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) { 1634 TAILQ_REMOVE(ðertype_rule->ethertype_list, 1635 p_ethertype, rules); 1636 rte_free(p_ethertype); 1637 } 1638 } 1639 1640 static void 1641 i40e_rm_tunnel_filter_list(struct i40e_pf *pf) 1642 { 1643 struct i40e_tunnel_filter *p_tunnel; 1644 struct i40e_tunnel_rule *tunnel_rule; 1645 1646 tunnel_rule = &pf->tunnel; 1647 /* Remove all tunnel director rules and hash */ 1648 if (tunnel_rule->hash_map) 1649 rte_free(tunnel_rule->hash_map); 1650 if (tunnel_rule->hash_table) 1651 rte_hash_free(tunnel_rule->hash_table); 1652 1653 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) { 1654 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules); 1655 rte_free(p_tunnel); 1656 } 1657 } 1658 1659 static void 1660 i40e_rm_fdir_filter_list(struct i40e_pf *pf) 1661 { 1662 struct i40e_fdir_filter *p_fdir; 1663 struct i40e_fdir_info *fdir_info; 1664 1665 fdir_info = &pf->fdir; 1666 /* Remove all flow director rules and hash */ 1667 if (fdir_info->hash_map) 1668 rte_free(fdir_info->hash_map); 1669 if (fdir_info->hash_table) 1670 rte_hash_free(fdir_info->hash_table); 1671 1672 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) { 1673 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules); 1674 rte_free(p_fdir); 1675 } 1676 } 1677 1678 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw) 1679 { 1680 /* 1681 * Disable by default flexible payload 1682 * for corresponding L2/L3/L4 layers. 1683 */ 1684 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000); 1685 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000); 1686 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000); 1687 } 1688 1689 static int 1690 eth_i40e_dev_uninit(struct rte_eth_dev *dev) 1691 { 1692 struct i40e_pf *pf; 1693 struct rte_pci_device *pci_dev; 1694 struct rte_intr_handle *intr_handle; 1695 struct i40e_hw *hw; 1696 struct i40e_filter_control_settings settings; 1697 struct rte_flow *p_flow; 1698 int ret; 1699 uint8_t aq_fail = 0; 1700 int retries = 0; 1701 1702 PMD_INIT_FUNC_TRACE(); 1703 1704 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1705 return 0; 1706 1707 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1708 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1709 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1710 intr_handle = &pci_dev->intr_handle; 1711 1712 ret = rte_eth_switch_domain_free(pf->switch_domain_id); 1713 if (ret) 1714 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret); 1715 1716 if (hw->adapter_closed == 0) 1717 i40e_dev_close(dev); 1718 1719 dev->dev_ops = NULL; 1720 dev->rx_pkt_burst = NULL; 1721 dev->tx_pkt_burst = NULL; 1722 1723 /* Clear PXE mode */ 1724 i40e_clear_pxe_mode(hw); 1725 1726 /* Unconfigure filter control */ 1727 memset(&settings, 0, sizeof(settings)); 1728 ret = i40e_set_filter_control(hw, &settings); 1729 if (ret) 1730 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d", 1731 ret); 1732 1733 /* Disable flow control */ 1734 hw->fc.requested_mode = I40E_FC_NONE; 1735 i40e_set_fc(hw, &aq_fail, TRUE); 1736 1737 /* uninitialize pf host driver */ 1738 i40e_pf_host_uninit(dev); 1739 1740 /* disable uio intr before callback unregister */ 1741 rte_intr_disable(intr_handle); 1742 1743 /* unregister callback func to eal lib */ 1744 do { 1745 ret = rte_intr_callback_unregister(intr_handle, 1746 i40e_dev_interrupt_handler, dev); 1747 if (ret >= 0) { 1748 break; 1749 } else if (ret != -EAGAIN) { 1750 PMD_INIT_LOG(ERR, 1751 "intr callback unregister failed: %d", 1752 ret); 1753 return ret; 1754 } 1755 i40e_msec_delay(500); 1756 } while (retries++ < 5); 1757 1758 i40e_rm_ethtype_filter_list(pf); 1759 i40e_rm_tunnel_filter_list(pf); 1760 i40e_rm_fdir_filter_list(pf); 1761 1762 /* Remove all flows */ 1763 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) { 1764 TAILQ_REMOVE(&pf->flow_list, p_flow, node); 1765 rte_free(p_flow); 1766 } 1767 1768 /* Remove all Traffic Manager configuration */ 1769 i40e_tm_conf_uninit(dev); 1770 1771 return 0; 1772 } 1773 1774 static int 1775 i40e_dev_configure(struct rte_eth_dev *dev) 1776 { 1777 struct i40e_adapter *ad = 1778 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1779 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1781 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1782 int i, ret; 1783 1784 ret = i40e_dev_sync_phy_type(hw); 1785 if (ret) 1786 return ret; 1787 1788 /* Initialize to TRUE. If any of Rx queues doesn't meet the 1789 * bulk allocation or vector Rx preconditions we will reset it. 1790 */ 1791 ad->rx_bulk_alloc_allowed = true; 1792 ad->rx_vec_allowed = true; 1793 ad->tx_simple_allowed = true; 1794 ad->tx_vec_allowed = true; 1795 1796 /* Only legacy filter API needs the following fdir config. So when the 1797 * legacy filter API is deprecated, the following codes should also be 1798 * removed. 1799 */ 1800 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) { 1801 ret = i40e_fdir_setup(pf); 1802 if (ret != I40E_SUCCESS) { 1803 PMD_DRV_LOG(ERR, "Failed to setup flow director."); 1804 return -ENOTSUP; 1805 } 1806 ret = i40e_fdir_configure(dev); 1807 if (ret < 0) { 1808 PMD_DRV_LOG(ERR, "failed to configure fdir."); 1809 goto err; 1810 } 1811 } else 1812 i40e_fdir_teardown(pf); 1813 1814 ret = i40e_dev_init_vlan(dev); 1815 if (ret < 0) 1816 goto err; 1817 1818 /* VMDQ setup. 1819 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and 1820 * RSS setting have different requirements. 1821 * General PMD driver call sequence are NIC init, configure, 1822 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it 1823 * will try to lookup the VSI that specific queue belongs to if VMDQ 1824 * applicable. So, VMDQ setting has to be done before 1825 * rx/tx_queue_setup(). This function is good to place vmdq_setup. 1826 * For RSS setting, it will try to calculate actual configured RX queue 1827 * number, which will be available after rx_queue_setup(). dev_start() 1828 * function is good to place RSS setup. 1829 */ 1830 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) { 1831 ret = i40e_vmdq_setup(dev); 1832 if (ret) 1833 goto err; 1834 } 1835 1836 if (mq_mode & ETH_MQ_RX_DCB_FLAG) { 1837 ret = i40e_dcb_setup(dev); 1838 if (ret) { 1839 PMD_DRV_LOG(ERR, "failed to configure DCB."); 1840 goto err_dcb; 1841 } 1842 } 1843 1844 TAILQ_INIT(&pf->flow_list); 1845 1846 return 0; 1847 1848 err_dcb: 1849 /* need to release vmdq resource if exists */ 1850 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 1851 i40e_vsi_release(pf->vmdq[i].vsi); 1852 pf->vmdq[i].vsi = NULL; 1853 } 1854 rte_free(pf->vmdq); 1855 pf->vmdq = NULL; 1856 err: 1857 /* Need to release fdir resource if exists. 1858 * Only legacy filter API needs the following fdir config. So when the 1859 * legacy filter API is deprecated, the following code should also be 1860 * removed. 1861 */ 1862 i40e_fdir_teardown(pf); 1863 return ret; 1864 } 1865 1866 void 1867 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi) 1868 { 1869 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1870 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1871 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1872 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1873 uint16_t msix_vect = vsi->msix_intr; 1874 uint16_t i; 1875 1876 for (i = 0; i < vsi->nb_qps; i++) { 1877 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); 1878 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); 1879 rte_wmb(); 1880 } 1881 1882 if (vsi->type != I40E_VSI_SRIOV) { 1883 if (!rte_intr_allow_others(intr_handle)) { 1884 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 1885 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); 1886 I40E_WRITE_REG(hw, 1887 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), 1888 0); 1889 } else { 1890 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 1891 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); 1892 I40E_WRITE_REG(hw, 1893 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, 1894 msix_vect - 1), 0); 1895 } 1896 } else { 1897 uint32_t reg; 1898 reg = (hw->func_caps.num_msix_vectors_vf - 1) * 1899 vsi->user_param + (msix_vect - 1); 1900 1901 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 1902 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK); 1903 } 1904 I40E_WRITE_FLUSH(hw); 1905 } 1906 1907 static void 1908 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect, 1909 int base_queue, int nb_queue, 1910 uint16_t itr_idx) 1911 { 1912 int i; 1913 uint32_t val; 1914 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1915 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 1916 1917 /* Bind all RX queues to allocated MSIX interrupt */ 1918 for (i = 0; i < nb_queue; i++) { 1919 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 1920 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT | 1921 ((base_queue + i + 1) << 1922 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 1923 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 1924 I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1925 1926 if (i == nb_queue - 1) 1927 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK; 1928 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val); 1929 } 1930 1931 /* Write first RX queue to Link list register as the head element */ 1932 if (vsi->type != I40E_VSI_SRIOV) { 1933 uint16_t interval = 1934 i40e_calc_itr_interval(1, pf->support_multi_driver); 1935 1936 if (msix_vect == I40E_MISC_VEC_ID) { 1937 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 1938 (base_queue << 1939 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 1940 (0x0 << 1941 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 1942 I40E_WRITE_REG(hw, 1943 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), 1944 interval); 1945 } else { 1946 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 1947 (base_queue << 1948 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 1949 (0x0 << 1950 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 1951 I40E_WRITE_REG(hw, 1952 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, 1953 msix_vect - 1), 1954 interval); 1955 } 1956 } else { 1957 uint32_t reg; 1958 1959 if (msix_vect == I40E_MISC_VEC_ID) { 1960 I40E_WRITE_REG(hw, 1961 I40E_VPINT_LNKLST0(vsi->user_param), 1962 (base_queue << 1963 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 1964 (0x0 << 1965 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 1966 } else { 1967 /* num_msix_vectors_vf needs to minus irq0 */ 1968 reg = (hw->func_caps.num_msix_vectors_vf - 1) * 1969 vsi->user_param + (msix_vect - 1); 1970 1971 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 1972 (base_queue << 1973 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 1974 (0x0 << 1975 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 1976 } 1977 } 1978 1979 I40E_WRITE_FLUSH(hw); 1980 } 1981 1982 void 1983 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx) 1984 { 1985 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1989 uint16_t msix_vect = vsi->msix_intr; 1990 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 1991 uint16_t queue_idx = 0; 1992 int record = 0; 1993 int i; 1994 1995 for (i = 0; i < vsi->nb_qps; i++) { 1996 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); 1997 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); 1998 } 1999 2000 /* VF bind interrupt */ 2001 if (vsi->type == I40E_VSI_SRIOV) { 2002 __vsi_queues_bind_intr(vsi, msix_vect, 2003 vsi->base_queue, vsi->nb_qps, 2004 itr_idx); 2005 return; 2006 } 2007 2008 /* PF & VMDq bind interrupt */ 2009 if (rte_intr_dp_is_en(intr_handle)) { 2010 if (vsi->type == I40E_VSI_MAIN) { 2011 queue_idx = 0; 2012 record = 1; 2013 } else if (vsi->type == I40E_VSI_VMDQ2) { 2014 struct i40e_vsi *main_vsi = 2015 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter); 2016 queue_idx = vsi->base_queue - main_vsi->nb_qps; 2017 record = 1; 2018 } 2019 } 2020 2021 for (i = 0; i < vsi->nb_used_qps; i++) { 2022 if (nb_msix <= 1) { 2023 if (!rte_intr_allow_others(intr_handle)) 2024 /* allow to share MISC_VEC_ID */ 2025 msix_vect = I40E_MISC_VEC_ID; 2026 2027 /* no enough msix_vect, map all to one */ 2028 __vsi_queues_bind_intr(vsi, msix_vect, 2029 vsi->base_queue + i, 2030 vsi->nb_used_qps - i, 2031 itr_idx); 2032 for (; !!record && i < vsi->nb_used_qps; i++) 2033 intr_handle->intr_vec[queue_idx + i] = 2034 msix_vect; 2035 break; 2036 } 2037 /* 1:1 queue/msix_vect mapping */ 2038 __vsi_queues_bind_intr(vsi, msix_vect, 2039 vsi->base_queue + i, 1, 2040 itr_idx); 2041 if (!!record) 2042 intr_handle->intr_vec[queue_idx + i] = msix_vect; 2043 2044 msix_vect++; 2045 nb_msix--; 2046 } 2047 } 2048 2049 static void 2050 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi) 2051 { 2052 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2055 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2056 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 2057 uint16_t msix_intr, i; 2058 2059 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) 2060 for (i = 0; i < vsi->nb_msix; i++) { 2061 msix_intr = vsi->msix_intr + i; 2062 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), 2063 I40E_PFINT_DYN_CTLN_INTENA_MASK | 2064 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 2065 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 2066 } 2067 else 2068 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 2069 I40E_PFINT_DYN_CTL0_INTENA_MASK | 2070 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 2071 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 2072 2073 I40E_WRITE_FLUSH(hw); 2074 } 2075 2076 static void 2077 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi) 2078 { 2079 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2083 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 2084 uint16_t msix_intr, i; 2085 2086 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) 2087 for (i = 0; i < vsi->nb_msix; i++) { 2088 msix_intr = vsi->msix_intr + i; 2089 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), 2090 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 2091 } 2092 else 2093 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 2094 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 2095 2096 I40E_WRITE_FLUSH(hw); 2097 } 2098 2099 static inline uint8_t 2100 i40e_parse_link_speeds(uint16_t link_speeds) 2101 { 2102 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN; 2103 2104 if (link_speeds & ETH_LINK_SPEED_40G) 2105 link_speed |= I40E_LINK_SPEED_40GB; 2106 if (link_speeds & ETH_LINK_SPEED_25G) 2107 link_speed |= I40E_LINK_SPEED_25GB; 2108 if (link_speeds & ETH_LINK_SPEED_20G) 2109 link_speed |= I40E_LINK_SPEED_20GB; 2110 if (link_speeds & ETH_LINK_SPEED_10G) 2111 link_speed |= I40E_LINK_SPEED_10GB; 2112 if (link_speeds & ETH_LINK_SPEED_1G) 2113 link_speed |= I40E_LINK_SPEED_1GB; 2114 if (link_speeds & ETH_LINK_SPEED_100M) 2115 link_speed |= I40E_LINK_SPEED_100MB; 2116 2117 return link_speed; 2118 } 2119 2120 static int 2121 i40e_phy_conf_link(struct i40e_hw *hw, 2122 uint8_t abilities, 2123 uint8_t force_speed, 2124 bool is_up) 2125 { 2126 enum i40e_status_code status; 2127 struct i40e_aq_get_phy_abilities_resp phy_ab; 2128 struct i40e_aq_set_phy_config phy_conf; 2129 enum i40e_aq_phy_type cnt; 2130 uint8_t avail_speed; 2131 uint32_t phy_type_mask = 0; 2132 2133 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX | 2134 I40E_AQ_PHY_FLAG_PAUSE_RX | 2135 I40E_AQ_PHY_FLAG_PAUSE_RX | 2136 I40E_AQ_PHY_FLAG_LOW_POWER; 2137 int ret = -ENOTSUP; 2138 2139 /* To get phy capabilities of available speeds. */ 2140 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, 2141 NULL); 2142 if (status) { 2143 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n", 2144 status); 2145 return ret; 2146 } 2147 avail_speed = phy_ab.link_speed; 2148 2149 /* To get the current phy config. */ 2150 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab, 2151 NULL); 2152 if (status) { 2153 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n", 2154 status); 2155 return ret; 2156 } 2157 2158 /* If link needs to go up and it is in autoneg mode the speed is OK, 2159 * no need to set up again. 2160 */ 2161 if (is_up && phy_ab.phy_type != 0 && 2162 abilities & I40E_AQ_PHY_AN_ENABLED && 2163 phy_ab.link_speed != 0) 2164 return I40E_SUCCESS; 2165 2166 memset(&phy_conf, 0, sizeof(phy_conf)); 2167 2168 /* bits 0-2 use the values from get_phy_abilities_resp */ 2169 abilities &= ~mask; 2170 abilities |= phy_ab.abilities & mask; 2171 2172 phy_conf.abilities = abilities; 2173 2174 /* If link needs to go up, but the force speed is not supported, 2175 * Warn users and config the default available speeds. 2176 */ 2177 if (is_up && !(force_speed & avail_speed)) { 2178 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n"); 2179 phy_conf.link_speed = avail_speed; 2180 } else { 2181 phy_conf.link_speed = is_up ? force_speed : avail_speed; 2182 } 2183 2184 /* PHY type mask needs to include each type except PHY type extension */ 2185 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++) 2186 phy_type_mask |= 1 << cnt; 2187 2188 /* use get_phy_abilities_resp value for the rest */ 2189 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0; 2190 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR | 2191 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR | 2192 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0; 2193 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info; 2194 phy_conf.eee_capability = phy_ab.eee_capability; 2195 phy_conf.eeer = phy_ab.eeer_val; 2196 phy_conf.low_power_ctrl = phy_ab.d3_lpan; 2197 2198 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x", 2199 phy_ab.abilities, phy_ab.link_speed); 2200 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x", 2201 phy_conf.abilities, phy_conf.link_speed); 2202 2203 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL); 2204 if (status) 2205 return ret; 2206 2207 return I40E_SUCCESS; 2208 } 2209 2210 static int 2211 i40e_apply_link_speed(struct rte_eth_dev *dev) 2212 { 2213 uint8_t speed; 2214 uint8_t abilities = 0; 2215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2216 struct rte_eth_conf *conf = &dev->data->dev_conf; 2217 2218 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) { 2219 conf->link_speeds = ETH_LINK_SPEED_40G | 2220 ETH_LINK_SPEED_25G | 2221 ETH_LINK_SPEED_20G | 2222 ETH_LINK_SPEED_10G | 2223 ETH_LINK_SPEED_1G | 2224 ETH_LINK_SPEED_100M; 2225 } 2226 speed = i40e_parse_link_speeds(conf->link_speeds); 2227 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK | 2228 I40E_AQ_PHY_AN_ENABLED | 2229 I40E_AQ_PHY_LINK_ENABLED; 2230 2231 return i40e_phy_conf_link(hw, abilities, speed, true); 2232 } 2233 2234 static int 2235 i40e_dev_start(struct rte_eth_dev *dev) 2236 { 2237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2239 struct i40e_vsi *main_vsi = pf->main_vsi; 2240 int ret, i; 2241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2242 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2243 uint32_t intr_vector = 0; 2244 struct i40e_vsi *vsi; 2245 2246 hw->adapter_stopped = 0; 2247 2248 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2249 PMD_INIT_LOG(ERR, 2250 "Invalid link_speeds for port %u, autonegotiation disabled", 2251 dev->data->port_id); 2252 return -EINVAL; 2253 } 2254 2255 rte_intr_disable(intr_handle); 2256 2257 if ((rte_intr_cap_multiple(intr_handle) || 2258 !RTE_ETH_DEV_SRIOV(dev).active) && 2259 dev->data->dev_conf.intr_conf.rxq != 0) { 2260 intr_vector = dev->data->nb_rx_queues; 2261 ret = rte_intr_efd_enable(intr_handle, intr_vector); 2262 if (ret) 2263 return ret; 2264 } 2265 2266 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2267 intr_handle->intr_vec = 2268 rte_zmalloc("intr_vec", 2269 dev->data->nb_rx_queues * sizeof(int), 2270 0); 2271 if (!intr_handle->intr_vec) { 2272 PMD_INIT_LOG(ERR, 2273 "Failed to allocate %d rx_queues intr_vec", 2274 dev->data->nb_rx_queues); 2275 return -ENOMEM; 2276 } 2277 } 2278 2279 /* Initialize VSI */ 2280 ret = i40e_dev_rxtx_init(pf); 2281 if (ret != I40E_SUCCESS) { 2282 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues"); 2283 goto err_up; 2284 } 2285 2286 /* Map queues with MSIX interrupt */ 2287 main_vsi->nb_used_qps = dev->data->nb_rx_queues - 2288 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 2289 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT); 2290 i40e_vsi_enable_queues_intr(main_vsi); 2291 2292 /* Map VMDQ VSI queues with MSIX interrupt */ 2293 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2294 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 2295 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi, 2296 I40E_ITR_INDEX_DEFAULT); 2297 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi); 2298 } 2299 2300 /* enable FDIR MSIX interrupt */ 2301 if (pf->fdir.fdir_vsi) { 2302 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi, 2303 I40E_ITR_INDEX_NONE); 2304 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi); 2305 } 2306 2307 /* Enable all queues which have been configured */ 2308 ret = i40e_dev_switch_queues(pf, TRUE); 2309 if (ret != I40E_SUCCESS) { 2310 PMD_DRV_LOG(ERR, "Failed to enable VSI"); 2311 goto err_up; 2312 } 2313 2314 /* Enable receiving broadcast packets */ 2315 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL); 2316 if (ret != I40E_SUCCESS) 2317 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2318 2319 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2320 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid, 2321 true, NULL); 2322 if (ret != I40E_SUCCESS) 2323 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2324 } 2325 2326 /* Enable the VLAN promiscuous mode. */ 2327 if (pf->vfs) { 2328 for (i = 0; i < pf->vf_num; i++) { 2329 vsi = pf->vfs[i].vsi; 2330 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, 2331 true, NULL); 2332 } 2333 } 2334 2335 /* Enable mac loopback mode */ 2336 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE || 2337 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) { 2338 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL); 2339 if (ret != I40E_SUCCESS) { 2340 PMD_DRV_LOG(ERR, "fail to set loopback link"); 2341 goto err_up; 2342 } 2343 } 2344 2345 /* Apply link configure */ 2346 ret = i40e_apply_link_speed(dev); 2347 if (I40E_SUCCESS != ret) { 2348 PMD_DRV_LOG(ERR, "Fail to apply link setting"); 2349 goto err_up; 2350 } 2351 2352 if (!rte_intr_allow_others(intr_handle)) { 2353 rte_intr_callback_unregister(intr_handle, 2354 i40e_dev_interrupt_handler, 2355 (void *)dev); 2356 /* configure and enable device interrupt */ 2357 i40e_pf_config_irq0(hw, FALSE); 2358 i40e_pf_enable_irq0(hw); 2359 2360 if (dev->data->dev_conf.intr_conf.lsc != 0) 2361 PMD_INIT_LOG(INFO, 2362 "lsc won't enable because of no intr multiplex"); 2363 } else { 2364 ret = i40e_aq_set_phy_int_mask(hw, 2365 ~(I40E_AQ_EVENT_LINK_UPDOWN | 2366 I40E_AQ_EVENT_MODULE_QUAL_FAIL | 2367 I40E_AQ_EVENT_MEDIA_NA), NULL); 2368 if (ret != I40E_SUCCESS) 2369 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 2370 2371 /* Call get_link_info aq commond to enable/disable LSE */ 2372 i40e_dev_link_update(dev, 0); 2373 } 2374 2375 if (dev->data->dev_conf.intr_conf.rxq == 0) { 2376 rte_eal_alarm_set(I40E_ALARM_INTERVAL, 2377 i40e_dev_alarm_handler, dev); 2378 } else { 2379 /* enable uio intr after callback register */ 2380 rte_intr_enable(intr_handle); 2381 } 2382 2383 i40e_filter_restore(pf); 2384 2385 if (pf->tm_conf.root && !pf->tm_conf.committed) 2386 PMD_DRV_LOG(WARNING, 2387 "please call hierarchy_commit() " 2388 "before starting the port"); 2389 2390 return I40E_SUCCESS; 2391 2392 err_up: 2393 i40e_dev_switch_queues(pf, FALSE); 2394 i40e_dev_clear_queues(dev); 2395 2396 return ret; 2397 } 2398 2399 static void 2400 i40e_dev_stop(struct rte_eth_dev *dev) 2401 { 2402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2404 struct i40e_vsi *main_vsi = pf->main_vsi; 2405 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2406 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2407 int i; 2408 2409 if (hw->adapter_stopped == 1) 2410 return; 2411 2412 if (dev->data->dev_conf.intr_conf.rxq == 0) { 2413 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev); 2414 rte_intr_enable(intr_handle); 2415 } 2416 2417 /* Disable all queues */ 2418 i40e_dev_switch_queues(pf, FALSE); 2419 2420 /* un-map queues with interrupt registers */ 2421 i40e_vsi_disable_queues_intr(main_vsi); 2422 i40e_vsi_queues_unbind_intr(main_vsi); 2423 2424 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2425 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi); 2426 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi); 2427 } 2428 2429 if (pf->fdir.fdir_vsi) { 2430 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi); 2431 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi); 2432 } 2433 /* Clear all queues and release memory */ 2434 i40e_dev_clear_queues(dev); 2435 2436 /* Set link down */ 2437 i40e_dev_set_link_down(dev); 2438 2439 if (!rte_intr_allow_others(intr_handle)) 2440 /* resume to the default handler */ 2441 rte_intr_callback_register(intr_handle, 2442 i40e_dev_interrupt_handler, 2443 (void *)dev); 2444 2445 /* Clean datapath event and queue/vec mapping */ 2446 rte_intr_efd_disable(intr_handle); 2447 if (intr_handle->intr_vec) { 2448 rte_free(intr_handle->intr_vec); 2449 intr_handle->intr_vec = NULL; 2450 } 2451 2452 /* reset hierarchy commit */ 2453 pf->tm_conf.committed = false; 2454 2455 hw->adapter_stopped = 1; 2456 2457 pf->adapter->rss_reta_updated = 0; 2458 } 2459 2460 static void 2461 i40e_dev_close(struct rte_eth_dev *dev) 2462 { 2463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2465 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2466 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2467 struct i40e_mirror_rule *p_mirror; 2468 uint32_t reg; 2469 int i; 2470 int ret; 2471 2472 PMD_INIT_FUNC_TRACE(); 2473 2474 i40e_dev_stop(dev); 2475 2476 /* Remove all mirror rules */ 2477 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) { 2478 ret = i40e_aq_del_mirror_rule(hw, 2479 pf->main_vsi->veb->seid, 2480 p_mirror->rule_type, 2481 p_mirror->entries, 2482 p_mirror->num_entries, 2483 p_mirror->id); 2484 if (ret < 0) 2485 PMD_DRV_LOG(ERR, "failed to remove mirror rule: " 2486 "status = %d, aq_err = %d.", ret, 2487 hw->aq.asq_last_status); 2488 2489 /* remove mirror software resource anyway */ 2490 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules); 2491 rte_free(p_mirror); 2492 pf->nb_mirror_rule--; 2493 } 2494 2495 i40e_dev_free_queues(dev); 2496 2497 /* Disable interrupt */ 2498 i40e_pf_disable_irq0(hw); 2499 rte_intr_disable(intr_handle); 2500 2501 /* 2502 * Only legacy filter API needs the following fdir config. So when the 2503 * legacy filter API is deprecated, the following code should also be 2504 * removed. 2505 */ 2506 i40e_fdir_teardown(pf); 2507 2508 /* shutdown and destroy the HMC */ 2509 i40e_shutdown_lan_hmc(hw); 2510 2511 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2512 i40e_vsi_release(pf->vmdq[i].vsi); 2513 pf->vmdq[i].vsi = NULL; 2514 } 2515 rte_free(pf->vmdq); 2516 pf->vmdq = NULL; 2517 2518 /* release all the existing VSIs and VEBs */ 2519 i40e_vsi_release(pf->main_vsi); 2520 2521 /* shutdown the adminq */ 2522 i40e_aq_queue_shutdown(hw, true); 2523 i40e_shutdown_adminq(hw); 2524 2525 i40e_res_pool_destroy(&pf->qp_pool); 2526 i40e_res_pool_destroy(&pf->msix_pool); 2527 2528 /* Disable flexible payload in global configuration */ 2529 if (!pf->support_multi_driver) 2530 i40e_flex_payload_reg_set_default(hw); 2531 2532 /* force a PF reset to clean anything leftover */ 2533 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL); 2534 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL, 2535 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 2536 I40E_WRITE_FLUSH(hw); 2537 2538 hw->adapter_closed = 1; 2539 } 2540 2541 /* 2542 * Reset PF device only to re-initialize resources in PMD layer 2543 */ 2544 static int 2545 i40e_dev_reset(struct rte_eth_dev *dev) 2546 { 2547 int ret; 2548 2549 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2550 * its VF to make them align with it. The detailed notification 2551 * mechanism is PMD specific. As to i40e PF, it is rather complex. 2552 * To avoid unexpected behavior in VF, currently reset of PF with 2553 * SR-IOV activation is not supported. It might be supported later. 2554 */ 2555 if (dev->data->sriov.active) 2556 return -ENOTSUP; 2557 2558 ret = eth_i40e_dev_uninit(dev); 2559 if (ret) 2560 return ret; 2561 2562 ret = eth_i40e_dev_init(dev, NULL); 2563 2564 return ret; 2565 } 2566 2567 static void 2568 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev) 2569 { 2570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2572 struct i40e_vsi *vsi = pf->main_vsi; 2573 int status; 2574 2575 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2576 true, NULL, true); 2577 if (status != I40E_SUCCESS) 2578 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous"); 2579 2580 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, 2581 TRUE, NULL); 2582 if (status != I40E_SUCCESS) 2583 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous"); 2584 2585 } 2586 2587 static void 2588 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev) 2589 { 2590 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2592 struct i40e_vsi *vsi = pf->main_vsi; 2593 int status; 2594 2595 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2596 false, NULL, true); 2597 if (status != I40E_SUCCESS) 2598 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous"); 2599 2600 /* must remain in all_multicast mode */ 2601 if (dev->data->all_multicast == 1) 2602 return; 2603 2604 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, 2605 false, NULL); 2606 if (status != I40E_SUCCESS) 2607 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous"); 2608 } 2609 2610 static void 2611 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev) 2612 { 2613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2615 struct i40e_vsi *vsi = pf->main_vsi; 2616 int ret; 2617 2618 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL); 2619 if (ret != I40E_SUCCESS) 2620 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous"); 2621 } 2622 2623 static void 2624 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev) 2625 { 2626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2627 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2628 struct i40e_vsi *vsi = pf->main_vsi; 2629 int ret; 2630 2631 if (dev->data->promiscuous == 1) 2632 return; /* must remain in all_multicast mode */ 2633 2634 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, 2635 vsi->seid, FALSE, NULL); 2636 if (ret != I40E_SUCCESS) 2637 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous"); 2638 } 2639 2640 /* 2641 * Set device link up. 2642 */ 2643 static int 2644 i40e_dev_set_link_up(struct rte_eth_dev *dev) 2645 { 2646 /* re-apply link speed setting */ 2647 return i40e_apply_link_speed(dev); 2648 } 2649 2650 /* 2651 * Set device link down. 2652 */ 2653 static int 2654 i40e_dev_set_link_down(struct rte_eth_dev *dev) 2655 { 2656 uint8_t speed = I40E_LINK_SPEED_UNKNOWN; 2657 uint8_t abilities = 0; 2658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2659 2660 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 2661 return i40e_phy_conf_link(hw, abilities, speed, false); 2662 } 2663 2664 static __rte_always_inline void 2665 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link) 2666 { 2667 /* Link status registers and values*/ 2668 #define I40E_PRTMAC_LINKSTA 0x001E2420 2669 #define I40E_REG_LINK_UP 0x40000080 2670 #define I40E_PRTMAC_MACC 0x001E24E0 2671 #define I40E_REG_MACC_25GB 0x00020000 2672 #define I40E_REG_SPEED_MASK 0x38000000 2673 #define I40E_REG_SPEED_0 0x00000000 2674 #define I40E_REG_SPEED_1 0x08000000 2675 #define I40E_REG_SPEED_2 0x10000000 2676 #define I40E_REG_SPEED_3 0x18000000 2677 #define I40E_REG_SPEED_4 0x20000000 2678 uint32_t link_speed; 2679 uint32_t reg_val; 2680 2681 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA); 2682 link_speed = reg_val & I40E_REG_SPEED_MASK; 2683 reg_val &= I40E_REG_LINK_UP; 2684 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0; 2685 2686 if (unlikely(link->link_status == 0)) 2687 return; 2688 2689 /* Parse the link status */ 2690 switch (link_speed) { 2691 case I40E_REG_SPEED_0: 2692 link->link_speed = ETH_SPEED_NUM_100M; 2693 break; 2694 case I40E_REG_SPEED_1: 2695 link->link_speed = ETH_SPEED_NUM_1G; 2696 break; 2697 case I40E_REG_SPEED_2: 2698 if (hw->mac.type == I40E_MAC_X722) 2699 link->link_speed = ETH_SPEED_NUM_2_5G; 2700 else 2701 link->link_speed = ETH_SPEED_NUM_10G; 2702 break; 2703 case I40E_REG_SPEED_3: 2704 if (hw->mac.type == I40E_MAC_X722) { 2705 link->link_speed = ETH_SPEED_NUM_5G; 2706 } else { 2707 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC); 2708 2709 if (reg_val & I40E_REG_MACC_25GB) 2710 link->link_speed = ETH_SPEED_NUM_25G; 2711 else 2712 link->link_speed = ETH_SPEED_NUM_40G; 2713 } 2714 break; 2715 case I40E_REG_SPEED_4: 2716 if (hw->mac.type == I40E_MAC_X722) 2717 link->link_speed = ETH_SPEED_NUM_10G; 2718 else 2719 link->link_speed = ETH_SPEED_NUM_20G; 2720 break; 2721 default: 2722 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed); 2723 break; 2724 } 2725 } 2726 2727 static __rte_always_inline void 2728 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link, 2729 bool enable_lse, int wait_to_complete) 2730 { 2731 #define CHECK_INTERVAL 100 /* 100ms */ 2732 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 2733 uint32_t rep_cnt = MAX_REPEAT_TIME; 2734 struct i40e_link_status link_status; 2735 int status; 2736 2737 memset(&link_status, 0, sizeof(link_status)); 2738 2739 do { 2740 memset(&link_status, 0, sizeof(link_status)); 2741 2742 /* Get link status information from hardware */ 2743 status = i40e_aq_get_link_info(hw, enable_lse, 2744 &link_status, NULL); 2745 if (unlikely(status != I40E_SUCCESS)) { 2746 link->link_speed = ETH_SPEED_NUM_100M; 2747 link->link_duplex = ETH_LINK_FULL_DUPLEX; 2748 PMD_DRV_LOG(ERR, "Failed to get link info"); 2749 return; 2750 } 2751 2752 link->link_status = link_status.link_info & I40E_AQ_LINK_UP; 2753 if (!wait_to_complete || link->link_status) 2754 break; 2755 2756 rte_delay_ms(CHECK_INTERVAL); 2757 } while (--rep_cnt); 2758 2759 /* Parse the link status */ 2760 switch (link_status.link_speed) { 2761 case I40E_LINK_SPEED_100MB: 2762 link->link_speed = ETH_SPEED_NUM_100M; 2763 break; 2764 case I40E_LINK_SPEED_1GB: 2765 link->link_speed = ETH_SPEED_NUM_1G; 2766 break; 2767 case I40E_LINK_SPEED_10GB: 2768 link->link_speed = ETH_SPEED_NUM_10G; 2769 break; 2770 case I40E_LINK_SPEED_20GB: 2771 link->link_speed = ETH_SPEED_NUM_20G; 2772 break; 2773 case I40E_LINK_SPEED_25GB: 2774 link->link_speed = ETH_SPEED_NUM_25G; 2775 break; 2776 case I40E_LINK_SPEED_40GB: 2777 link->link_speed = ETH_SPEED_NUM_40G; 2778 break; 2779 default: 2780 link->link_speed = ETH_SPEED_NUM_100M; 2781 break; 2782 } 2783 } 2784 2785 int 2786 i40e_dev_link_update(struct rte_eth_dev *dev, 2787 int wait_to_complete) 2788 { 2789 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2790 struct rte_eth_link link; 2791 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2792 int ret; 2793 2794 memset(&link, 0, sizeof(link)); 2795 2796 /* i40e uses full duplex only */ 2797 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2798 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2799 ETH_LINK_SPEED_FIXED); 2800 2801 if (!wait_to_complete && !enable_lse) 2802 update_link_reg(hw, &link); 2803 else 2804 update_link_aq(hw, &link, enable_lse, wait_to_complete); 2805 2806 ret = rte_eth_linkstatus_set(dev, &link); 2807 i40e_notify_all_vfs_link_status(dev); 2808 2809 return ret; 2810 } 2811 2812 /* Get all the statistics of a VSI */ 2813 void 2814 i40e_update_vsi_stats(struct i40e_vsi *vsi) 2815 { 2816 struct i40e_eth_stats *oes = &vsi->eth_stats_offset; 2817 struct i40e_eth_stats *nes = &vsi->eth_stats; 2818 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2819 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx); 2820 2821 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx), 2822 vsi->offset_loaded, &oes->rx_bytes, 2823 &nes->rx_bytes); 2824 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx), 2825 vsi->offset_loaded, &oes->rx_unicast, 2826 &nes->rx_unicast); 2827 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx), 2828 vsi->offset_loaded, &oes->rx_multicast, 2829 &nes->rx_multicast); 2830 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx), 2831 vsi->offset_loaded, &oes->rx_broadcast, 2832 &nes->rx_broadcast); 2833 /* exclude CRC bytes */ 2834 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 2835 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 2836 2837 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded, 2838 &oes->rx_discards, &nes->rx_discards); 2839 /* GLV_REPC not supported */ 2840 /* GLV_RMPC not supported */ 2841 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded, 2842 &oes->rx_unknown_protocol, 2843 &nes->rx_unknown_protocol); 2844 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx), 2845 vsi->offset_loaded, &oes->tx_bytes, 2846 &nes->tx_bytes); 2847 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx), 2848 vsi->offset_loaded, &oes->tx_unicast, 2849 &nes->tx_unicast); 2850 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx), 2851 vsi->offset_loaded, &oes->tx_multicast, 2852 &nes->tx_multicast); 2853 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx), 2854 vsi->offset_loaded, &oes->tx_broadcast, 2855 &nes->tx_broadcast); 2856 /* GLV_TDPC not supported */ 2857 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded, 2858 &oes->tx_errors, &nes->tx_errors); 2859 vsi->offset_loaded = true; 2860 2861 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************", 2862 vsi->vsi_id); 2863 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 2864 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 2865 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 2866 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 2867 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 2868 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 2869 nes->rx_unknown_protocol); 2870 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 2871 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 2872 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 2873 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 2874 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 2875 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 2876 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************", 2877 vsi->vsi_id); 2878 } 2879 2880 static void 2881 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) 2882 { 2883 unsigned int i; 2884 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */ 2885 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */ 2886 2887 /* Get rx/tx bytes of internal transfer packets */ 2888 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port), 2889 I40E_GLV_GORCL(hw->port), 2890 pf->offset_loaded, 2891 &pf->internal_stats_offset.rx_bytes, 2892 &pf->internal_stats.rx_bytes); 2893 2894 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port), 2895 I40E_GLV_GOTCL(hw->port), 2896 pf->offset_loaded, 2897 &pf->internal_stats_offset.tx_bytes, 2898 &pf->internal_stats.tx_bytes); 2899 /* Get total internal rx packet count */ 2900 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port), 2901 I40E_GLV_UPRCL(hw->port), 2902 pf->offset_loaded, 2903 &pf->internal_stats_offset.rx_unicast, 2904 &pf->internal_stats.rx_unicast); 2905 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port), 2906 I40E_GLV_MPRCL(hw->port), 2907 pf->offset_loaded, 2908 &pf->internal_stats_offset.rx_multicast, 2909 &pf->internal_stats.rx_multicast); 2910 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port), 2911 I40E_GLV_BPRCL(hw->port), 2912 pf->offset_loaded, 2913 &pf->internal_stats_offset.rx_broadcast, 2914 &pf->internal_stats.rx_broadcast); 2915 /* Get total internal tx packet count */ 2916 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port), 2917 I40E_GLV_UPTCL(hw->port), 2918 pf->offset_loaded, 2919 &pf->internal_stats_offset.tx_unicast, 2920 &pf->internal_stats.tx_unicast); 2921 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port), 2922 I40E_GLV_MPTCL(hw->port), 2923 pf->offset_loaded, 2924 &pf->internal_stats_offset.tx_multicast, 2925 &pf->internal_stats.tx_multicast); 2926 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port), 2927 I40E_GLV_BPTCL(hw->port), 2928 pf->offset_loaded, 2929 &pf->internal_stats_offset.tx_broadcast, 2930 &pf->internal_stats.tx_broadcast); 2931 2932 /* exclude CRC size */ 2933 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast + 2934 pf->internal_stats.rx_multicast + 2935 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN; 2936 2937 /* Get statistics of struct i40e_eth_stats */ 2938 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port), 2939 I40E_GLPRT_GORCL(hw->port), 2940 pf->offset_loaded, &os->eth.rx_bytes, 2941 &ns->eth.rx_bytes); 2942 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port), 2943 I40E_GLPRT_UPRCL(hw->port), 2944 pf->offset_loaded, &os->eth.rx_unicast, 2945 &ns->eth.rx_unicast); 2946 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port), 2947 I40E_GLPRT_MPRCL(hw->port), 2948 pf->offset_loaded, &os->eth.rx_multicast, 2949 &ns->eth.rx_multicast); 2950 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port), 2951 I40E_GLPRT_BPRCL(hw->port), 2952 pf->offset_loaded, &os->eth.rx_broadcast, 2953 &ns->eth.rx_broadcast); 2954 /* Workaround: CRC size should not be included in byte statistics, 2955 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 2956 * packet. 2957 */ 2958 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 2959 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 2960 2961 /* exclude internal rx bytes 2962 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before 2963 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative 2964 * value. 2965 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L]. 2966 */ 2967 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes) 2968 ns->eth.rx_bytes = 0; 2969 else 2970 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes; 2971 2972 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast) 2973 ns->eth.rx_unicast = 0; 2974 else 2975 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast; 2976 2977 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast) 2978 ns->eth.rx_multicast = 0; 2979 else 2980 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast; 2981 2982 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast) 2983 ns->eth.rx_broadcast = 0; 2984 else 2985 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast; 2986 2987 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port), 2988 pf->offset_loaded, &os->eth.rx_discards, 2989 &ns->eth.rx_discards); 2990 /* GLPRT_REPC not supported */ 2991 /* GLPRT_RMPC not supported */ 2992 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port), 2993 pf->offset_loaded, 2994 &os->eth.rx_unknown_protocol, 2995 &ns->eth.rx_unknown_protocol); 2996 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port), 2997 I40E_GLPRT_GOTCL(hw->port), 2998 pf->offset_loaded, &os->eth.tx_bytes, 2999 &ns->eth.tx_bytes); 3000 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port), 3001 I40E_GLPRT_UPTCL(hw->port), 3002 pf->offset_loaded, &os->eth.tx_unicast, 3003 &ns->eth.tx_unicast); 3004 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port), 3005 I40E_GLPRT_MPTCL(hw->port), 3006 pf->offset_loaded, &os->eth.tx_multicast, 3007 &ns->eth.tx_multicast); 3008 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port), 3009 I40E_GLPRT_BPTCL(hw->port), 3010 pf->offset_loaded, &os->eth.tx_broadcast, 3011 &ns->eth.tx_broadcast); 3012 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 3013 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 3014 3015 /* exclude internal tx bytes 3016 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before 3017 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative 3018 * value. 3019 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L]. 3020 */ 3021 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes) 3022 ns->eth.tx_bytes = 0; 3023 else 3024 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes; 3025 3026 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast) 3027 ns->eth.tx_unicast = 0; 3028 else 3029 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast; 3030 3031 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast) 3032 ns->eth.tx_multicast = 0; 3033 else 3034 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast; 3035 3036 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast) 3037 ns->eth.tx_broadcast = 0; 3038 else 3039 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast; 3040 3041 /* GLPRT_TEPC not supported */ 3042 3043 /* additional port specific stats */ 3044 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port), 3045 pf->offset_loaded, &os->tx_dropped_link_down, 3046 &ns->tx_dropped_link_down); 3047 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port), 3048 pf->offset_loaded, &os->crc_errors, 3049 &ns->crc_errors); 3050 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port), 3051 pf->offset_loaded, &os->illegal_bytes, 3052 &ns->illegal_bytes); 3053 /* GLPRT_ERRBC not supported */ 3054 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port), 3055 pf->offset_loaded, &os->mac_local_faults, 3056 &ns->mac_local_faults); 3057 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port), 3058 pf->offset_loaded, &os->mac_remote_faults, 3059 &ns->mac_remote_faults); 3060 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port), 3061 pf->offset_loaded, &os->rx_length_errors, 3062 &ns->rx_length_errors); 3063 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port), 3064 pf->offset_loaded, &os->link_xon_rx, 3065 &ns->link_xon_rx); 3066 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 3067 pf->offset_loaded, &os->link_xoff_rx, 3068 &ns->link_xoff_rx); 3069 for (i = 0; i < 8; i++) { 3070 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i), 3071 pf->offset_loaded, 3072 &os->priority_xon_rx[i], 3073 &ns->priority_xon_rx[i]); 3074 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), 3075 pf->offset_loaded, 3076 &os->priority_xoff_rx[i], 3077 &ns->priority_xoff_rx[i]); 3078 } 3079 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port), 3080 pf->offset_loaded, &os->link_xon_tx, 3081 &ns->link_xon_tx); 3082 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 3083 pf->offset_loaded, &os->link_xoff_tx, 3084 &ns->link_xoff_tx); 3085 for (i = 0; i < 8; i++) { 3086 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i), 3087 pf->offset_loaded, 3088 &os->priority_xon_tx[i], 3089 &ns->priority_xon_tx[i]); 3090 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), 3091 pf->offset_loaded, 3092 &os->priority_xoff_tx[i], 3093 &ns->priority_xoff_tx[i]); 3094 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i), 3095 pf->offset_loaded, 3096 &os->priority_xon_2_xoff[i], 3097 &ns->priority_xon_2_xoff[i]); 3098 } 3099 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port), 3100 I40E_GLPRT_PRC64L(hw->port), 3101 pf->offset_loaded, &os->rx_size_64, 3102 &ns->rx_size_64); 3103 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port), 3104 I40E_GLPRT_PRC127L(hw->port), 3105 pf->offset_loaded, &os->rx_size_127, 3106 &ns->rx_size_127); 3107 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port), 3108 I40E_GLPRT_PRC255L(hw->port), 3109 pf->offset_loaded, &os->rx_size_255, 3110 &ns->rx_size_255); 3111 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port), 3112 I40E_GLPRT_PRC511L(hw->port), 3113 pf->offset_loaded, &os->rx_size_511, 3114 &ns->rx_size_511); 3115 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port), 3116 I40E_GLPRT_PRC1023L(hw->port), 3117 pf->offset_loaded, &os->rx_size_1023, 3118 &ns->rx_size_1023); 3119 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port), 3120 I40E_GLPRT_PRC1522L(hw->port), 3121 pf->offset_loaded, &os->rx_size_1522, 3122 &ns->rx_size_1522); 3123 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port), 3124 I40E_GLPRT_PRC9522L(hw->port), 3125 pf->offset_loaded, &os->rx_size_big, 3126 &ns->rx_size_big); 3127 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port), 3128 pf->offset_loaded, &os->rx_undersize, 3129 &ns->rx_undersize); 3130 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port), 3131 pf->offset_loaded, &os->rx_fragments, 3132 &ns->rx_fragments); 3133 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port), 3134 pf->offset_loaded, &os->rx_oversize, 3135 &ns->rx_oversize); 3136 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port), 3137 pf->offset_loaded, &os->rx_jabber, 3138 &ns->rx_jabber); 3139 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port), 3140 I40E_GLPRT_PTC64L(hw->port), 3141 pf->offset_loaded, &os->tx_size_64, 3142 &ns->tx_size_64); 3143 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port), 3144 I40E_GLPRT_PTC127L(hw->port), 3145 pf->offset_loaded, &os->tx_size_127, 3146 &ns->tx_size_127); 3147 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port), 3148 I40E_GLPRT_PTC255L(hw->port), 3149 pf->offset_loaded, &os->tx_size_255, 3150 &ns->tx_size_255); 3151 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port), 3152 I40E_GLPRT_PTC511L(hw->port), 3153 pf->offset_loaded, &os->tx_size_511, 3154 &ns->tx_size_511); 3155 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port), 3156 I40E_GLPRT_PTC1023L(hw->port), 3157 pf->offset_loaded, &os->tx_size_1023, 3158 &ns->tx_size_1023); 3159 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port), 3160 I40E_GLPRT_PTC1522L(hw->port), 3161 pf->offset_loaded, &os->tx_size_1522, 3162 &ns->tx_size_1522); 3163 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port), 3164 I40E_GLPRT_PTC9522L(hw->port), 3165 pf->offset_loaded, &os->tx_size_big, 3166 &ns->tx_size_big); 3167 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index), 3168 pf->offset_loaded, 3169 &os->fd_sb_match, &ns->fd_sb_match); 3170 /* GLPRT_MSPDC not supported */ 3171 /* GLPRT_XEC not supported */ 3172 3173 pf->offset_loaded = true; 3174 3175 if (pf->main_vsi) 3176 i40e_update_vsi_stats(pf->main_vsi); 3177 } 3178 3179 /* Get all statistics of a port */ 3180 static int 3181 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3182 { 3183 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3184 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3185 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */ 3186 struct i40e_vsi *vsi; 3187 unsigned i; 3188 3189 /* call read registers - updates values, now write them to struct */ 3190 i40e_read_stats_registers(pf, hw); 3191 3192 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 3193 pf->main_vsi->eth_stats.rx_multicast + 3194 pf->main_vsi->eth_stats.rx_broadcast - 3195 pf->main_vsi->eth_stats.rx_discards; 3196 stats->opackets = ns->eth.tx_unicast + 3197 ns->eth.tx_multicast + 3198 ns->eth.tx_broadcast; 3199 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 3200 stats->obytes = ns->eth.tx_bytes; 3201 stats->oerrors = ns->eth.tx_errors + 3202 pf->main_vsi->eth_stats.tx_errors; 3203 3204 /* Rx Errors */ 3205 stats->imissed = ns->eth.rx_discards + 3206 pf->main_vsi->eth_stats.rx_discards; 3207 stats->ierrors = ns->crc_errors + 3208 ns->rx_length_errors + ns->rx_undersize + 3209 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 3210 3211 if (pf->vfs) { 3212 for (i = 0; i < pf->vf_num; i++) { 3213 vsi = pf->vfs[i].vsi; 3214 i40e_update_vsi_stats(vsi); 3215 3216 stats->ipackets += (vsi->eth_stats.rx_unicast + 3217 vsi->eth_stats.rx_multicast + 3218 vsi->eth_stats.rx_broadcast - 3219 vsi->eth_stats.rx_discards); 3220 stats->ibytes += vsi->eth_stats.rx_bytes; 3221 stats->oerrors += vsi->eth_stats.tx_errors; 3222 stats->imissed += vsi->eth_stats.rx_discards; 3223 } 3224 } 3225 3226 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************"); 3227 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 3228 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 3229 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast); 3230 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast); 3231 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards); 3232 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3233 ns->eth.rx_unknown_protocol); 3234 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 3235 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 3236 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast); 3237 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast); 3238 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards); 3239 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 3240 3241 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 3242 ns->tx_dropped_link_down); 3243 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 3244 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 3245 ns->illegal_bytes); 3246 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 3247 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 3248 ns->mac_local_faults); 3249 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 3250 ns->mac_remote_faults); 3251 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"", 3252 ns->rx_length_errors); 3253 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 3254 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 3255 for (i = 0; i < 8; i++) { 3256 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"", 3257 i, ns->priority_xon_rx[i]); 3258 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"", 3259 i, ns->priority_xoff_rx[i]); 3260 } 3261 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 3262 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 3263 for (i = 0; i < 8; i++) { 3264 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"", 3265 i, ns->priority_xon_tx[i]); 3266 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"", 3267 i, ns->priority_xoff_tx[i]); 3268 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"", 3269 i, ns->priority_xon_2_xoff[i]); 3270 } 3271 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 3272 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 3273 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 3274 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 3275 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 3276 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 3277 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 3278 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 3279 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 3280 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 3281 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 3282 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 3283 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 3284 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 3285 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 3286 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 3287 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 3288 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 3289 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"", 3290 ns->mac_short_packet_dropped); 3291 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"", 3292 ns->checksum_error); 3293 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match); 3294 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************"); 3295 return 0; 3296 } 3297 3298 /* Reset the statistics */ 3299 static void 3300 i40e_dev_stats_reset(struct rte_eth_dev *dev) 3301 { 3302 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3303 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3304 3305 /* Mark PF and VSI stats to update the offset, aka "reset" */ 3306 pf->offset_loaded = false; 3307 if (pf->main_vsi) 3308 pf->main_vsi->offset_loaded = false; 3309 3310 /* read the stats, reading current register values into offset */ 3311 i40e_read_stats_registers(pf, hw); 3312 } 3313 3314 static uint32_t 3315 i40e_xstats_calc_num(void) 3316 { 3317 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + 3318 (I40E_NB_RXQ_PRIO_XSTATS * 8) + 3319 (I40E_NB_TXQ_PRIO_XSTATS * 8); 3320 } 3321 3322 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3323 struct rte_eth_xstat_name *xstats_names, 3324 __rte_unused unsigned limit) 3325 { 3326 unsigned count = 0; 3327 unsigned i, prio; 3328 3329 if (xstats_names == NULL) 3330 return i40e_xstats_calc_num(); 3331 3332 /* Note: limit checked in rte_eth_xstats_names() */ 3333 3334 /* Get stats from i40e_eth_stats struct */ 3335 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) { 3336 strlcpy(xstats_names[count].name, 3337 rte_i40e_stats_strings[i].name, 3338 sizeof(xstats_names[count].name)); 3339 count++; 3340 } 3341 3342 /* Get individiual stats from i40e_hw_port struct */ 3343 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) { 3344 strlcpy(xstats_names[count].name, 3345 rte_i40e_hw_port_strings[i].name, 3346 sizeof(xstats_names[count].name)); 3347 count++; 3348 } 3349 3350 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) { 3351 for (prio = 0; prio < 8; prio++) { 3352 snprintf(xstats_names[count].name, 3353 sizeof(xstats_names[count].name), 3354 "rx_priority%u_%s", prio, 3355 rte_i40e_rxq_prio_strings[i].name); 3356 count++; 3357 } 3358 } 3359 3360 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) { 3361 for (prio = 0; prio < 8; prio++) { 3362 snprintf(xstats_names[count].name, 3363 sizeof(xstats_names[count].name), 3364 "tx_priority%u_%s", prio, 3365 rte_i40e_txq_prio_strings[i].name); 3366 count++; 3367 } 3368 } 3369 return count; 3370 } 3371 3372 static int 3373 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3374 unsigned n) 3375 { 3376 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3377 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3378 unsigned i, count, prio; 3379 struct i40e_hw_port_stats *hw_stats = &pf->stats; 3380 3381 count = i40e_xstats_calc_num(); 3382 if (n < count) 3383 return count; 3384 3385 i40e_read_stats_registers(pf, hw); 3386 3387 if (xstats == NULL) 3388 return 0; 3389 3390 count = 0; 3391 3392 /* Get stats from i40e_eth_stats struct */ 3393 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) { 3394 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) + 3395 rte_i40e_stats_strings[i].offset); 3396 xstats[count].id = count; 3397 count++; 3398 } 3399 3400 /* Get individiual stats from i40e_hw_port struct */ 3401 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) { 3402 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3403 rte_i40e_hw_port_strings[i].offset); 3404 xstats[count].id = count; 3405 count++; 3406 } 3407 3408 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) { 3409 for (prio = 0; prio < 8; prio++) { 3410 xstats[count].value = 3411 *(uint64_t *)(((char *)hw_stats) + 3412 rte_i40e_rxq_prio_strings[i].offset + 3413 (sizeof(uint64_t) * prio)); 3414 xstats[count].id = count; 3415 count++; 3416 } 3417 } 3418 3419 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) { 3420 for (prio = 0; prio < 8; prio++) { 3421 xstats[count].value = 3422 *(uint64_t *)(((char *)hw_stats) + 3423 rte_i40e_txq_prio_strings[i].offset + 3424 (sizeof(uint64_t) * prio)); 3425 xstats[count].id = count; 3426 count++; 3427 } 3428 } 3429 3430 return count; 3431 } 3432 3433 static int 3434 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3435 { 3436 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3437 u32 full_ver; 3438 u8 ver, patch; 3439 u16 build; 3440 int ret; 3441 3442 full_ver = hw->nvm.oem_ver; 3443 ver = (u8)(full_ver >> 24); 3444 build = (u16)((full_ver >> 8) & 0xffff); 3445 patch = (u8)(full_ver & 0xff); 3446 3447 ret = snprintf(fw_version, fw_size, 3448 "%d.%d%d 0x%08x %d.%d.%d", 3449 ((hw->nvm.version >> 12) & 0xf), 3450 ((hw->nvm.version >> 4) & 0xff), 3451 (hw->nvm.version & 0xf), hw->nvm.eetrack, 3452 ver, build, patch); 3453 3454 ret += 1; /* add the size of '\0' */ 3455 if (fw_size < (u32)ret) 3456 return ret; 3457 else 3458 return 0; 3459 } 3460 3461 /* 3462 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later, 3463 * the Rx data path does not hang if the FW LLDP is stopped. 3464 * return true if lldp need to stop 3465 * return false if we cannot disable the LLDP to avoid Rx data path blocking. 3466 */ 3467 static bool 3468 i40e_need_stop_lldp(struct rte_eth_dev *dev) 3469 { 3470 double nvm_ver; 3471 char ver_str[64] = {0}; 3472 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3473 3474 i40e_fw_version_get(dev, ver_str, 64); 3475 nvm_ver = atof(ver_str); 3476 if ((hw->mac.type == I40E_MAC_X722 || 3477 hw->mac.type == I40E_MAC_X722_VF) && 3478 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000))) 3479 return true; 3480 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000)) 3481 return true; 3482 3483 return false; 3484 } 3485 3486 static void 3487 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3488 { 3489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3490 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3491 struct i40e_vsi *vsi = pf->main_vsi; 3492 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3493 3494 dev_info->max_rx_queues = vsi->nb_qps; 3495 dev_info->max_tx_queues = vsi->nb_qps; 3496 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN; 3497 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX; 3498 dev_info->max_mac_addrs = vsi->max_macaddrs; 3499 dev_info->max_vfs = pci_dev->max_vfs; 3500 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD; 3501 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3502 dev_info->rx_queue_offload_capa = 0; 3503 dev_info->rx_offload_capa = 3504 DEV_RX_OFFLOAD_VLAN_STRIP | 3505 DEV_RX_OFFLOAD_QINQ_STRIP | 3506 DEV_RX_OFFLOAD_IPV4_CKSUM | 3507 DEV_RX_OFFLOAD_UDP_CKSUM | 3508 DEV_RX_OFFLOAD_TCP_CKSUM | 3509 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3510 DEV_RX_OFFLOAD_KEEP_CRC | 3511 DEV_RX_OFFLOAD_SCATTER | 3512 DEV_RX_OFFLOAD_VLAN_EXTEND | 3513 DEV_RX_OFFLOAD_VLAN_FILTER | 3514 DEV_RX_OFFLOAD_JUMBO_FRAME; 3515 3516 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3517 dev_info->tx_offload_capa = 3518 DEV_TX_OFFLOAD_VLAN_INSERT | 3519 DEV_TX_OFFLOAD_QINQ_INSERT | 3520 DEV_TX_OFFLOAD_IPV4_CKSUM | 3521 DEV_TX_OFFLOAD_UDP_CKSUM | 3522 DEV_TX_OFFLOAD_TCP_CKSUM | 3523 DEV_TX_OFFLOAD_SCTP_CKSUM | 3524 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3525 DEV_TX_OFFLOAD_TCP_TSO | 3526 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 3527 DEV_TX_OFFLOAD_GRE_TNL_TSO | 3528 DEV_TX_OFFLOAD_IPIP_TNL_TSO | 3529 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 3530 DEV_TX_OFFLOAD_MULTI_SEGS | 3531 dev_info->tx_queue_offload_capa; 3532 dev_info->dev_capa = 3533 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 3534 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 3535 3536 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 3537 sizeof(uint32_t); 3538 dev_info->reta_size = pf->hash_lut_size; 3539 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask; 3540 3541 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3542 .rx_thresh = { 3543 .pthresh = I40E_DEFAULT_RX_PTHRESH, 3544 .hthresh = I40E_DEFAULT_RX_HTHRESH, 3545 .wthresh = I40E_DEFAULT_RX_WTHRESH, 3546 }, 3547 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH, 3548 .rx_drop_en = 0, 3549 .offloads = 0, 3550 }; 3551 3552 dev_info->default_txconf = (struct rte_eth_txconf) { 3553 .tx_thresh = { 3554 .pthresh = I40E_DEFAULT_TX_PTHRESH, 3555 .hthresh = I40E_DEFAULT_TX_HTHRESH, 3556 .wthresh = I40E_DEFAULT_TX_WTHRESH, 3557 }, 3558 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH, 3559 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH, 3560 .offloads = 0, 3561 }; 3562 3563 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3564 .nb_max = I40E_MAX_RING_DESC, 3565 .nb_min = I40E_MIN_RING_DESC, 3566 .nb_align = I40E_ALIGN_RING_DESC, 3567 }; 3568 3569 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3570 .nb_max = I40E_MAX_RING_DESC, 3571 .nb_min = I40E_MIN_RING_DESC, 3572 .nb_align = I40E_ALIGN_RING_DESC, 3573 .nb_seg_max = I40E_TX_MAX_SEG, 3574 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG, 3575 }; 3576 3577 if (pf->flags & I40E_FLAG_VMDQ) { 3578 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi; 3579 dev_info->vmdq_queue_base = dev_info->max_rx_queues; 3580 dev_info->vmdq_queue_num = pf->vmdq_nb_qps * 3581 pf->max_nb_vmdq_vsi; 3582 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE; 3583 dev_info->max_rx_queues += dev_info->vmdq_queue_num; 3584 dev_info->max_tx_queues += dev_info->vmdq_queue_num; 3585 } 3586 3587 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { 3588 /* For XL710 */ 3589 dev_info->speed_capa = ETH_LINK_SPEED_40G; 3590 dev_info->default_rxportconf.nb_queues = 2; 3591 dev_info->default_txportconf.nb_queues = 2; 3592 if (dev->data->nb_rx_queues == 1) 3593 dev_info->default_rxportconf.ring_size = 2048; 3594 else 3595 dev_info->default_rxportconf.ring_size = 1024; 3596 if (dev->data->nb_tx_queues == 1) 3597 dev_info->default_txportconf.ring_size = 1024; 3598 else 3599 dev_info->default_txportconf.ring_size = 512; 3600 3601 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) { 3602 /* For XXV710 */ 3603 dev_info->speed_capa = ETH_LINK_SPEED_25G; 3604 dev_info->default_rxportconf.nb_queues = 1; 3605 dev_info->default_txportconf.nb_queues = 1; 3606 dev_info->default_rxportconf.ring_size = 256; 3607 dev_info->default_txportconf.ring_size = 256; 3608 } else { 3609 /* For X710 */ 3610 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3611 dev_info->default_rxportconf.nb_queues = 1; 3612 dev_info->default_txportconf.nb_queues = 1; 3613 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) { 3614 dev_info->default_rxportconf.ring_size = 512; 3615 dev_info->default_txportconf.ring_size = 256; 3616 } else { 3617 dev_info->default_rxportconf.ring_size = 256; 3618 dev_info->default_txportconf.ring_size = 256; 3619 } 3620 } 3621 dev_info->default_rxportconf.burst_size = 32; 3622 dev_info->default_txportconf.burst_size = 32; 3623 } 3624 3625 static int 3626 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3627 { 3628 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3629 struct i40e_vsi *vsi = pf->main_vsi; 3630 PMD_INIT_FUNC_TRACE(); 3631 3632 if (on) 3633 return i40e_vsi_add_vlan(vsi, vlan_id); 3634 else 3635 return i40e_vsi_delete_vlan(vsi, vlan_id); 3636 } 3637 3638 static int 3639 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev, 3640 enum rte_vlan_type vlan_type, 3641 uint16_t tpid, int qinq) 3642 { 3643 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3644 uint64_t reg_r = 0; 3645 uint64_t reg_w = 0; 3646 uint16_t reg_id = 3; 3647 int ret; 3648 3649 if (qinq) { 3650 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3651 reg_id = 2; 3652 } 3653 3654 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), 3655 ®_r, NULL); 3656 if (ret != I40E_SUCCESS) { 3657 PMD_DRV_LOG(ERR, 3658 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]", 3659 reg_id); 3660 return -EIO; 3661 } 3662 PMD_DRV_LOG(DEBUG, 3663 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64, 3664 reg_id, reg_r); 3665 3666 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK)); 3667 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT); 3668 if (reg_r == reg_w) { 3669 PMD_DRV_LOG(DEBUG, "No need to write"); 3670 return 0; 3671 } 3672 3673 ret = i40e_aq_debug_write_global_register(hw, 3674 I40E_GL_SWT_L2TAGCTRL(reg_id), 3675 reg_w, NULL); 3676 if (ret != I40E_SUCCESS) { 3677 PMD_DRV_LOG(ERR, 3678 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]", 3679 reg_id); 3680 return -EIO; 3681 } 3682 PMD_DRV_LOG(DEBUG, 3683 "Global register 0x%08x is changed with value 0x%08x", 3684 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w); 3685 3686 return 0; 3687 } 3688 3689 static int 3690 i40e_vlan_tpid_set(struct rte_eth_dev *dev, 3691 enum rte_vlan_type vlan_type, 3692 uint16_t tpid) 3693 { 3694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3695 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3696 int qinq = dev->data->dev_conf.rxmode.offloads & 3697 DEV_RX_OFFLOAD_VLAN_EXTEND; 3698 int ret = 0; 3699 3700 if ((vlan_type != ETH_VLAN_TYPE_INNER && 3701 vlan_type != ETH_VLAN_TYPE_OUTER) || 3702 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) { 3703 PMD_DRV_LOG(ERR, 3704 "Unsupported vlan type."); 3705 return -EINVAL; 3706 } 3707 3708 if (pf->support_multi_driver) { 3709 PMD_DRV_LOG(ERR, "Setting TPID is not supported."); 3710 return -ENOTSUP; 3711 } 3712 3713 /* 802.1ad frames ability is added in NVM API 1.7*/ 3714 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 3715 if (qinq) { 3716 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3717 hw->first_tag = rte_cpu_to_le_16(tpid); 3718 else if (vlan_type == ETH_VLAN_TYPE_INNER) 3719 hw->second_tag = rte_cpu_to_le_16(tpid); 3720 } else { 3721 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3722 hw->second_tag = rte_cpu_to_le_16(tpid); 3723 } 3724 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL); 3725 if (ret != I40E_SUCCESS) { 3726 PMD_DRV_LOG(ERR, 3727 "Set switch config failed aq_err: %d", 3728 hw->aq.asq_last_status); 3729 ret = -EIO; 3730 } 3731 } else 3732 /* If NVM API < 1.7, keep the register setting */ 3733 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type, 3734 tpid, qinq); 3735 3736 return ret; 3737 } 3738 3739 static int 3740 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) 3741 { 3742 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3743 struct i40e_vsi *vsi = pf->main_vsi; 3744 struct rte_eth_rxmode *rxmode; 3745 3746 rxmode = &dev->data->dev_conf.rxmode; 3747 if (mask & ETH_VLAN_FILTER_MASK) { 3748 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 3749 i40e_vsi_config_vlan_filter(vsi, TRUE); 3750 else 3751 i40e_vsi_config_vlan_filter(vsi, FALSE); 3752 } 3753 3754 if (mask & ETH_VLAN_STRIP_MASK) { 3755 /* Enable or disable VLAN stripping */ 3756 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 3757 i40e_vsi_config_vlan_stripping(vsi, TRUE); 3758 else 3759 i40e_vsi_config_vlan_stripping(vsi, FALSE); 3760 } 3761 3762 if (mask & ETH_VLAN_EXTEND_MASK) { 3763 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) { 3764 i40e_vsi_config_double_vlan(vsi, TRUE); 3765 /* Set global registers with default ethertype. */ 3766 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 3767 RTE_ETHER_TYPE_VLAN); 3768 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, 3769 RTE_ETHER_TYPE_VLAN); 3770 } 3771 else 3772 i40e_vsi_config_double_vlan(vsi, FALSE); 3773 } 3774 3775 return 0; 3776 } 3777 3778 static void 3779 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev, 3780 __rte_unused uint16_t queue, 3781 __rte_unused int on) 3782 { 3783 PMD_INIT_FUNC_TRACE(); 3784 } 3785 3786 static int 3787 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 3788 { 3789 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3790 struct i40e_vsi *vsi = pf->main_vsi; 3791 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi); 3792 struct i40e_vsi_vlan_pvid_info info; 3793 3794 memset(&info, 0, sizeof(info)); 3795 info.on = on; 3796 if (info.on) 3797 info.config.pvid = pvid; 3798 else { 3799 info.config.reject.tagged = 3800 data->dev_conf.txmode.hw_vlan_reject_tagged; 3801 info.config.reject.untagged = 3802 data->dev_conf.txmode.hw_vlan_reject_untagged; 3803 } 3804 3805 return i40e_vsi_vlan_pvid_set(vsi, &info); 3806 } 3807 3808 static int 3809 i40e_dev_led_on(struct rte_eth_dev *dev) 3810 { 3811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3812 uint32_t mode = i40e_led_get(hw); 3813 3814 if (mode == 0) 3815 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */ 3816 3817 return 0; 3818 } 3819 3820 static int 3821 i40e_dev_led_off(struct rte_eth_dev *dev) 3822 { 3823 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3824 uint32_t mode = i40e_led_get(hw); 3825 3826 if (mode != 0) 3827 i40e_led_set(hw, 0, false); 3828 3829 return 0; 3830 } 3831 3832 static int 3833 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3834 { 3835 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3836 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3837 3838 fc_conf->pause_time = pf->fc_conf.pause_time; 3839 3840 /* read out from register, in case they are modified by other port */ 3841 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = 3842 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT; 3843 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = 3844 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT; 3845 3846 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]; 3847 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]; 3848 3849 /* Return current mode according to actual setting*/ 3850 switch (hw->fc.current_mode) { 3851 case I40E_FC_FULL: 3852 fc_conf->mode = RTE_FC_FULL; 3853 break; 3854 case I40E_FC_TX_PAUSE: 3855 fc_conf->mode = RTE_FC_TX_PAUSE; 3856 break; 3857 case I40E_FC_RX_PAUSE: 3858 fc_conf->mode = RTE_FC_RX_PAUSE; 3859 break; 3860 case I40E_FC_NONE: 3861 default: 3862 fc_conf->mode = RTE_FC_NONE; 3863 }; 3864 3865 return 0; 3866 } 3867 3868 static int 3869 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3870 { 3871 uint32_t mflcn_reg, fctrl_reg, reg; 3872 uint32_t max_high_water; 3873 uint8_t i, aq_failure; 3874 int err; 3875 struct i40e_hw *hw; 3876 struct i40e_pf *pf; 3877 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = { 3878 [RTE_FC_NONE] = I40E_FC_NONE, 3879 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE, 3880 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE, 3881 [RTE_FC_FULL] = I40E_FC_FULL 3882 }; 3883 3884 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */ 3885 3886 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT; 3887 if ((fc_conf->high_water > max_high_water) || 3888 (fc_conf->high_water < fc_conf->low_water)) { 3889 PMD_INIT_LOG(ERR, 3890 "Invalid high/low water setup value in KB, High_water must be <= %d.", 3891 max_high_water); 3892 return -EINVAL; 3893 } 3894 3895 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3896 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3897 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode]; 3898 3899 pf->fc_conf.pause_time = fc_conf->pause_time; 3900 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water; 3901 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water; 3902 3903 PMD_INIT_FUNC_TRACE(); 3904 3905 /* All the link flow control related enable/disable register 3906 * configuration is handle by the F/W 3907 */ 3908 err = i40e_set_fc(hw, &aq_failure, true); 3909 if (err < 0) 3910 return -ENOSYS; 3911 3912 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { 3913 /* Configure flow control refresh threshold, 3914 * the value for stat_tx_pause_refresh_timer[8] 3915 * is used for global pause operation. 3916 */ 3917 3918 I40E_WRITE_REG(hw, 3919 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8), 3920 pf->fc_conf.pause_time); 3921 3922 /* configure the timer value included in transmitted pause 3923 * frame, 3924 * the value for stat_tx_pause_quanta[8] is used for global 3925 * pause operation 3926 */ 3927 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8), 3928 pf->fc_conf.pause_time); 3929 3930 fctrl_reg = I40E_READ_REG(hw, 3931 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL); 3932 3933 if (fc_conf->mac_ctrl_frame_fwd != 0) 3934 fctrl_reg |= I40E_PRTMAC_FWD_CTRL; 3935 else 3936 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL; 3937 3938 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL, 3939 fctrl_reg); 3940 } else { 3941 /* Configure pause time (2 TCs per register) */ 3942 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001; 3943 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++) 3944 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg); 3945 3946 /* Configure flow control refresh threshold value */ 3947 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV, 3948 pf->fc_conf.pause_time / 2); 3949 3950 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); 3951 3952 /* set or clear MFLCN.PMCF & MFLCN.DPF bits 3953 *depending on configuration 3954 */ 3955 if (fc_conf->mac_ctrl_frame_fwd != 0) { 3956 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK; 3957 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK; 3958 } else { 3959 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK; 3960 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK; 3961 } 3962 3963 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg); 3964 } 3965 3966 if (!pf->support_multi_driver) { 3967 /* config water marker both based on the packets and bytes */ 3968 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW, 3969 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] 3970 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE); 3971 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW, 3972 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] 3973 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE); 3974 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW, 3975 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] 3976 << I40E_KILOSHIFT); 3977 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW, 3978 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] 3979 << I40E_KILOSHIFT); 3980 } else { 3981 PMD_DRV_LOG(ERR, 3982 "Water marker configuration is not supported."); 3983 } 3984 3985 I40E_WRITE_FLUSH(hw); 3986 3987 return 0; 3988 } 3989 3990 static int 3991 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev, 3992 __rte_unused struct rte_eth_pfc_conf *pfc_conf) 3993 { 3994 PMD_INIT_FUNC_TRACE(); 3995 3996 return -ENOSYS; 3997 } 3998 3999 /* Add a MAC address, and update filters */ 4000 static int 4001 i40e_macaddr_add(struct rte_eth_dev *dev, 4002 struct rte_ether_addr *mac_addr, 4003 __rte_unused uint32_t index, 4004 uint32_t pool) 4005 { 4006 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4007 struct i40e_mac_filter_info mac_filter; 4008 struct i40e_vsi *vsi; 4009 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 4010 int ret; 4011 4012 /* If VMDQ not enabled or configured, return */ 4013 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) || 4014 !pf->nb_cfg_vmdq_vsi)) { 4015 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u", 4016 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled", 4017 pool); 4018 return -ENOTSUP; 4019 } 4020 4021 if (pool > pf->nb_cfg_vmdq_vsi) { 4022 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u", 4023 pool, pf->nb_cfg_vmdq_vsi); 4024 return -EINVAL; 4025 } 4026 4027 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN); 4028 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 4029 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 4030 else 4031 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH; 4032 4033 if (pool == 0) 4034 vsi = pf->main_vsi; 4035 else 4036 vsi = pf->vmdq[pool - 1].vsi; 4037 4038 ret = i40e_vsi_add_mac(vsi, &mac_filter); 4039 if (ret != I40E_SUCCESS) { 4040 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter"); 4041 return -ENODEV; 4042 } 4043 return 0; 4044 } 4045 4046 /* Remove a MAC address, and update filters */ 4047 static void 4048 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 4049 { 4050 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4051 struct i40e_vsi *vsi; 4052 struct rte_eth_dev_data *data = dev->data; 4053 struct rte_ether_addr *macaddr; 4054 int ret; 4055 uint32_t i; 4056 uint64_t pool_sel; 4057 4058 macaddr = &(data->mac_addrs[index]); 4059 4060 pool_sel = dev->data->mac_pool_sel[index]; 4061 4062 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) { 4063 if (pool_sel & (1ULL << i)) { 4064 if (i == 0) 4065 vsi = pf->main_vsi; 4066 else { 4067 /* No VMDQ pool enabled or configured */ 4068 if (!(pf->flags & I40E_FLAG_VMDQ) || 4069 (i > pf->nb_cfg_vmdq_vsi)) { 4070 PMD_DRV_LOG(ERR, 4071 "No VMDQ pool enabled/configured"); 4072 return; 4073 } 4074 vsi = pf->vmdq[i - 1].vsi; 4075 } 4076 ret = i40e_vsi_delete_mac(vsi, macaddr); 4077 4078 if (ret) { 4079 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter"); 4080 return; 4081 } 4082 } 4083 } 4084 } 4085 4086 /* Set perfect match or hash match of MAC and VLAN for a VF */ 4087 static int 4088 i40e_vf_mac_filter_set(struct i40e_pf *pf, 4089 struct rte_eth_mac_filter *filter, 4090 bool add) 4091 { 4092 struct i40e_hw *hw; 4093 struct i40e_mac_filter_info mac_filter; 4094 struct rte_ether_addr old_mac; 4095 struct rte_ether_addr *new_mac; 4096 struct i40e_pf_vf *vf = NULL; 4097 uint16_t vf_id; 4098 int ret; 4099 4100 if (pf == NULL) { 4101 PMD_DRV_LOG(ERR, "Invalid PF argument."); 4102 return -EINVAL; 4103 } 4104 hw = I40E_PF_TO_HW(pf); 4105 4106 if (filter == NULL) { 4107 PMD_DRV_LOG(ERR, "Invalid mac filter argument."); 4108 return -EINVAL; 4109 } 4110 4111 new_mac = &filter->mac_addr; 4112 4113 if (rte_is_zero_ether_addr(new_mac)) { 4114 PMD_DRV_LOG(ERR, "Invalid ethernet address."); 4115 return -EINVAL; 4116 } 4117 4118 vf_id = filter->dst_id; 4119 4120 if (vf_id > pf->vf_num - 1 || !pf->vfs) { 4121 PMD_DRV_LOG(ERR, "Invalid argument."); 4122 return -EINVAL; 4123 } 4124 vf = &pf->vfs[vf_id]; 4125 4126 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) { 4127 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address."); 4128 return -EINVAL; 4129 } 4130 4131 if (add) { 4132 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN); 4133 rte_memcpy(hw->mac.addr, new_mac->addr_bytes, 4134 RTE_ETHER_ADDR_LEN); 4135 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr, 4136 RTE_ETHER_ADDR_LEN); 4137 4138 mac_filter.filter_type = filter->filter_type; 4139 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter); 4140 if (ret != I40E_SUCCESS) { 4141 PMD_DRV_LOG(ERR, "Failed to add MAC filter."); 4142 return -1; 4143 } 4144 rte_ether_addr_copy(new_mac, &pf->dev_addr); 4145 } else { 4146 rte_memcpy(hw->mac.addr, hw->mac.perm_addr, 4147 RTE_ETHER_ADDR_LEN); 4148 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr); 4149 if (ret != I40E_SUCCESS) { 4150 PMD_DRV_LOG(ERR, "Failed to delete MAC filter."); 4151 return -1; 4152 } 4153 4154 /* Clear device address as it has been removed */ 4155 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac)) 4156 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr)); 4157 } 4158 4159 return 0; 4160 } 4161 4162 /* MAC filter handle */ 4163 static int 4164 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op, 4165 void *arg) 4166 { 4167 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4168 struct rte_eth_mac_filter *filter; 4169 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4170 int ret = I40E_NOT_SUPPORTED; 4171 4172 filter = (struct rte_eth_mac_filter *)(arg); 4173 4174 switch (filter_op) { 4175 case RTE_ETH_FILTER_NOP: 4176 ret = I40E_SUCCESS; 4177 break; 4178 case RTE_ETH_FILTER_ADD: 4179 i40e_pf_disable_irq0(hw); 4180 if (filter->is_vf) 4181 ret = i40e_vf_mac_filter_set(pf, filter, 1); 4182 i40e_pf_enable_irq0(hw); 4183 break; 4184 case RTE_ETH_FILTER_DELETE: 4185 i40e_pf_disable_irq0(hw); 4186 if (filter->is_vf) 4187 ret = i40e_vf_mac_filter_set(pf, filter, 0); 4188 i40e_pf_enable_irq0(hw); 4189 break; 4190 default: 4191 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 4192 ret = I40E_ERR_PARAM; 4193 break; 4194 } 4195 4196 return ret; 4197 } 4198 4199 static int 4200 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4201 { 4202 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 4203 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 4204 uint32_t reg; 4205 int ret; 4206 4207 if (!lut) 4208 return -EINVAL; 4209 4210 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 4211 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, 4212 vsi->type != I40E_VSI_SRIOV, 4213 lut, lut_size); 4214 if (ret) { 4215 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 4216 return ret; 4217 } 4218 } else { 4219 uint32_t *lut_dw = (uint32_t *)lut; 4220 uint16_t i, lut_size_dw = lut_size / 4; 4221 4222 if (vsi->type == I40E_VSI_SRIOV) { 4223 for (i = 0; i <= lut_size_dw; i++) { 4224 reg = I40E_VFQF_HLUT1(i, vsi->user_param); 4225 lut_dw[i] = i40e_read_rx_ctl(hw, reg); 4226 } 4227 } else { 4228 for (i = 0; i < lut_size_dw; i++) 4229 lut_dw[i] = I40E_READ_REG(hw, 4230 I40E_PFQF_HLUT(i)); 4231 } 4232 } 4233 4234 return 0; 4235 } 4236 4237 int 4238 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4239 { 4240 struct i40e_pf *pf; 4241 struct i40e_hw *hw; 4242 int ret; 4243 4244 if (!vsi || !lut) 4245 return -EINVAL; 4246 4247 pf = I40E_VSI_TO_PF(vsi); 4248 hw = I40E_VSI_TO_HW(vsi); 4249 4250 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 4251 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, 4252 vsi->type != I40E_VSI_SRIOV, 4253 lut, lut_size); 4254 if (ret) { 4255 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 4256 return ret; 4257 } 4258 } else { 4259 uint32_t *lut_dw = (uint32_t *)lut; 4260 uint16_t i, lut_size_dw = lut_size / 4; 4261 4262 if (vsi->type == I40E_VSI_SRIOV) { 4263 for (i = 0; i < lut_size_dw; i++) 4264 I40E_WRITE_REG( 4265 hw, 4266 I40E_VFQF_HLUT1(i, vsi->user_param), 4267 lut_dw[i]); 4268 } else { 4269 for (i = 0; i < lut_size_dw; i++) 4270 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), 4271 lut_dw[i]); 4272 } 4273 I40E_WRITE_FLUSH(hw); 4274 } 4275 4276 return 0; 4277 } 4278 4279 static int 4280 i40e_dev_rss_reta_update(struct rte_eth_dev *dev, 4281 struct rte_eth_rss_reta_entry64 *reta_conf, 4282 uint16_t reta_size) 4283 { 4284 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4285 uint16_t i, lut_size = pf->hash_lut_size; 4286 uint16_t idx, shift; 4287 uint8_t *lut; 4288 int ret; 4289 4290 if (reta_size != lut_size || 4291 reta_size > ETH_RSS_RETA_SIZE_512) { 4292 PMD_DRV_LOG(ERR, 4293 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)", 4294 reta_size, lut_size); 4295 return -EINVAL; 4296 } 4297 4298 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 4299 if (!lut) { 4300 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4301 return -ENOMEM; 4302 } 4303 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size); 4304 if (ret) 4305 goto out; 4306 for (i = 0; i < reta_size; i++) { 4307 idx = i / RTE_RETA_GROUP_SIZE; 4308 shift = i % RTE_RETA_GROUP_SIZE; 4309 if (reta_conf[idx].mask & (1ULL << shift)) 4310 lut[i] = reta_conf[idx].reta[shift]; 4311 } 4312 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size); 4313 4314 pf->adapter->rss_reta_updated = 1; 4315 4316 out: 4317 rte_free(lut); 4318 4319 return ret; 4320 } 4321 4322 static int 4323 i40e_dev_rss_reta_query(struct rte_eth_dev *dev, 4324 struct rte_eth_rss_reta_entry64 *reta_conf, 4325 uint16_t reta_size) 4326 { 4327 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4328 uint16_t i, lut_size = pf->hash_lut_size; 4329 uint16_t idx, shift; 4330 uint8_t *lut; 4331 int ret; 4332 4333 if (reta_size != lut_size || 4334 reta_size > ETH_RSS_RETA_SIZE_512) { 4335 PMD_DRV_LOG(ERR, 4336 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)", 4337 reta_size, lut_size); 4338 return -EINVAL; 4339 } 4340 4341 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 4342 if (!lut) { 4343 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4344 return -ENOMEM; 4345 } 4346 4347 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size); 4348 if (ret) 4349 goto out; 4350 for (i = 0; i < reta_size; i++) { 4351 idx = i / RTE_RETA_GROUP_SIZE; 4352 shift = i % RTE_RETA_GROUP_SIZE; 4353 if (reta_conf[idx].mask & (1ULL << shift)) 4354 reta_conf[idx].reta[shift] = lut[i]; 4355 } 4356 4357 out: 4358 rte_free(lut); 4359 4360 return ret; 4361 } 4362 4363 /** 4364 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver) 4365 * @hw: pointer to the HW structure 4366 * @mem: pointer to mem struct to fill out 4367 * @size: size of memory requested 4368 * @alignment: what to align the allocation to 4369 **/ 4370 enum i40e_status_code 4371 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4372 struct i40e_dma_mem *mem, 4373 u64 size, 4374 u32 alignment) 4375 { 4376 const struct rte_memzone *mz = NULL; 4377 char z_name[RTE_MEMZONE_NAMESIZE]; 4378 4379 if (!mem) 4380 return I40E_ERR_PARAM; 4381 4382 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand()); 4383 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 4384 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M); 4385 if (!mz) 4386 return I40E_ERR_NO_MEMORY; 4387 4388 mem->size = size; 4389 mem->va = mz->addr; 4390 mem->pa = mz->iova; 4391 mem->zone = (const void *)mz; 4392 PMD_DRV_LOG(DEBUG, 4393 "memzone %s allocated with physical address: %"PRIu64, 4394 mz->name, mem->pa); 4395 4396 return I40E_SUCCESS; 4397 } 4398 4399 /** 4400 * i40e_free_dma_mem_d - specific memory free for shared code (base driver) 4401 * @hw: pointer to the HW structure 4402 * @mem: ptr to mem struct to free 4403 **/ 4404 enum i40e_status_code 4405 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4406 struct i40e_dma_mem *mem) 4407 { 4408 if (!mem) 4409 return I40E_ERR_PARAM; 4410 4411 PMD_DRV_LOG(DEBUG, 4412 "memzone %s to be freed with physical address: %"PRIu64, 4413 ((const struct rte_memzone *)mem->zone)->name, mem->pa); 4414 rte_memzone_free((const struct rte_memzone *)mem->zone); 4415 mem->zone = NULL; 4416 mem->va = NULL; 4417 mem->pa = (u64)0; 4418 4419 return I40E_SUCCESS; 4420 } 4421 4422 /** 4423 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver) 4424 * @hw: pointer to the HW structure 4425 * @mem: pointer to mem struct to fill out 4426 * @size: size of memory requested 4427 **/ 4428 enum i40e_status_code 4429 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4430 struct i40e_virt_mem *mem, 4431 u32 size) 4432 { 4433 if (!mem) 4434 return I40E_ERR_PARAM; 4435 4436 mem->size = size; 4437 mem->va = rte_zmalloc("i40e", size, 0); 4438 4439 if (mem->va) 4440 return I40E_SUCCESS; 4441 else 4442 return I40E_ERR_NO_MEMORY; 4443 } 4444 4445 /** 4446 * i40e_free_virt_mem_d - specific memory free for shared code (base driver) 4447 * @hw: pointer to the HW structure 4448 * @mem: pointer to mem struct to free 4449 **/ 4450 enum i40e_status_code 4451 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4452 struct i40e_virt_mem *mem) 4453 { 4454 if (!mem) 4455 return I40E_ERR_PARAM; 4456 4457 rte_free(mem->va); 4458 mem->va = NULL; 4459 4460 return I40E_SUCCESS; 4461 } 4462 4463 void 4464 i40e_init_spinlock_d(struct i40e_spinlock *sp) 4465 { 4466 rte_spinlock_init(&sp->spinlock); 4467 } 4468 4469 void 4470 i40e_acquire_spinlock_d(struct i40e_spinlock *sp) 4471 { 4472 rte_spinlock_lock(&sp->spinlock); 4473 } 4474 4475 void 4476 i40e_release_spinlock_d(struct i40e_spinlock *sp) 4477 { 4478 rte_spinlock_unlock(&sp->spinlock); 4479 } 4480 4481 void 4482 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp) 4483 { 4484 return; 4485 } 4486 4487 /** 4488 * Get the hardware capabilities, which will be parsed 4489 * and saved into struct i40e_hw. 4490 */ 4491 static int 4492 i40e_get_cap(struct i40e_hw *hw) 4493 { 4494 struct i40e_aqc_list_capabilities_element_resp *buf; 4495 uint16_t len, size = 0; 4496 int ret; 4497 4498 /* Calculate a huge enough buff for saving response data temporarily */ 4499 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) * 4500 I40E_MAX_CAP_ELE_NUM; 4501 buf = rte_zmalloc("i40e", len, 0); 4502 if (!buf) { 4503 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 4504 return I40E_ERR_NO_MEMORY; 4505 } 4506 4507 /* Get, parse the capabilities and save it to hw */ 4508 ret = i40e_aq_discover_capabilities(hw, buf, len, &size, 4509 i40e_aqc_opc_list_func_capabilities, NULL); 4510 if (ret != I40E_SUCCESS) 4511 PMD_DRV_LOG(ERR, "Failed to discover capabilities"); 4512 4513 /* Free the temporary buffer after being used */ 4514 rte_free(buf); 4515 4516 return ret; 4517 } 4518 4519 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 4520 4521 static int i40e_pf_parse_vf_queue_number_handler(const char *key, 4522 const char *value, 4523 void *opaque) 4524 { 4525 struct i40e_pf *pf; 4526 unsigned long num; 4527 char *end; 4528 4529 pf = (struct i40e_pf *)opaque; 4530 RTE_SET_USED(key); 4531 4532 errno = 0; 4533 num = strtoul(value, &end, 0); 4534 if (errno != 0 || end == value || *end != 0) { 4535 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is " 4536 "kept the value = %hu", value, pf->vf_nb_qp_max); 4537 return -(EINVAL); 4538 } 4539 4540 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num)) 4541 pf->vf_nb_qp_max = (uint16_t)num; 4542 else 4543 /* here return 0 to make next valid same argument work */ 4544 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be " 4545 "power of 2 and equal or less than 16 !, Now it is " 4546 "kept the value = %hu", num, pf->vf_nb_qp_max); 4547 4548 return 0; 4549 } 4550 4551 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev) 4552 { 4553 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4554 struct rte_kvargs *kvlist; 4555 int kvargs_count; 4556 4557 /* set default queue number per VF as 4 */ 4558 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF; 4559 4560 if (dev->device->devargs == NULL) 4561 return 0; 4562 4563 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 4564 if (kvlist == NULL) 4565 return -(EINVAL); 4566 4567 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG); 4568 if (!kvargs_count) { 4569 rte_kvargs_free(kvlist); 4570 return 0; 4571 } 4572 4573 if (kvargs_count > 1) 4574 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 4575 "the first invalid or last valid one is used !", 4576 ETH_I40E_QUEUE_NUM_PER_VF_ARG); 4577 4578 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG, 4579 i40e_pf_parse_vf_queue_number_handler, pf); 4580 4581 rte_kvargs_free(kvlist); 4582 4583 return 0; 4584 } 4585 4586 static int 4587 i40e_pf_parameter_init(struct rte_eth_dev *dev) 4588 { 4589 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4590 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4591 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4592 uint16_t qp_count = 0, vsi_count = 0; 4593 4594 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) { 4595 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV"); 4596 return -EINVAL; 4597 } 4598 4599 i40e_pf_config_vf_rxq_number(dev); 4600 4601 /* Add the parameter init for LFC */ 4602 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME; 4603 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER; 4604 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER; 4605 4606 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED; 4607 pf->max_num_vsi = hw->func_caps.num_vsis; 4608 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF; 4609 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 4610 4611 /* FDir queue/VSI allocation */ 4612 pf->fdir_qp_offset = 0; 4613 if (hw->func_caps.fd) { 4614 pf->flags |= I40E_FLAG_FDIR; 4615 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR; 4616 } else { 4617 pf->fdir_nb_qps = 0; 4618 } 4619 qp_count += pf->fdir_nb_qps; 4620 vsi_count += 1; 4621 4622 /* LAN queue/VSI allocation */ 4623 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps; 4624 if (!hw->func_caps.rss) { 4625 pf->lan_nb_qps = 1; 4626 } else { 4627 pf->flags |= I40E_FLAG_RSS; 4628 if (hw->mac.type == I40E_MAC_X722) 4629 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE; 4630 pf->lan_nb_qps = pf->lan_nb_qp_max; 4631 } 4632 qp_count += pf->lan_nb_qps; 4633 vsi_count += 1; 4634 4635 /* VF queue/VSI allocation */ 4636 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps; 4637 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) { 4638 pf->flags |= I40E_FLAG_SRIOV; 4639 pf->vf_nb_qps = pf->vf_nb_qp_max; 4640 pf->vf_num = pci_dev->max_vfs; 4641 PMD_DRV_LOG(DEBUG, 4642 "%u VF VSIs, %u queues per VF VSI, in total %u queues", 4643 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num); 4644 } else { 4645 pf->vf_nb_qps = 0; 4646 pf->vf_num = 0; 4647 } 4648 qp_count += pf->vf_nb_qps * pf->vf_num; 4649 vsi_count += pf->vf_num; 4650 4651 /* VMDq queue/VSI allocation */ 4652 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num; 4653 pf->vmdq_nb_qps = 0; 4654 pf->max_nb_vmdq_vsi = 0; 4655 if (hw->func_caps.vmdq) { 4656 if (qp_count < hw->func_caps.num_tx_qp && 4657 vsi_count < hw->func_caps.num_vsis) { 4658 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp - 4659 qp_count) / pf->vmdq_nb_qp_max; 4660 4661 /* Limit the maximum number of VMDq vsi to the maximum 4662 * ethdev can support 4663 */ 4664 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi, 4665 hw->func_caps.num_vsis - vsi_count); 4666 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi, 4667 ETH_64_POOLS); 4668 if (pf->max_nb_vmdq_vsi) { 4669 pf->flags |= I40E_FLAG_VMDQ; 4670 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max; 4671 PMD_DRV_LOG(DEBUG, 4672 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues", 4673 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps, 4674 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi); 4675 } else { 4676 PMD_DRV_LOG(INFO, 4677 "No enough queues left for VMDq"); 4678 } 4679 } else { 4680 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq"); 4681 } 4682 } 4683 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi; 4684 vsi_count += pf->max_nb_vmdq_vsi; 4685 4686 if (hw->func_caps.dcb) 4687 pf->flags |= I40E_FLAG_DCB; 4688 4689 if (qp_count > hw->func_caps.num_tx_qp) { 4690 PMD_DRV_LOG(ERR, 4691 "Failed to allocate %u queues, which exceeds the hardware maximum %u", 4692 qp_count, hw->func_caps.num_tx_qp); 4693 return -EINVAL; 4694 } 4695 if (vsi_count > hw->func_caps.num_vsis) { 4696 PMD_DRV_LOG(ERR, 4697 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u", 4698 vsi_count, hw->func_caps.num_vsis); 4699 return -EINVAL; 4700 } 4701 4702 return 0; 4703 } 4704 4705 static int 4706 i40e_pf_get_switch_config(struct i40e_pf *pf) 4707 { 4708 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4709 struct i40e_aqc_get_switch_config_resp *switch_config; 4710 struct i40e_aqc_switch_config_element_resp *element; 4711 uint16_t start_seid = 0, num_reported; 4712 int ret; 4713 4714 switch_config = (struct i40e_aqc_get_switch_config_resp *)\ 4715 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0); 4716 if (!switch_config) { 4717 PMD_DRV_LOG(ERR, "Failed to allocated memory"); 4718 return -ENOMEM; 4719 } 4720 4721 /* Get the switch configurations */ 4722 ret = i40e_aq_get_switch_config(hw, switch_config, 4723 I40E_AQ_LARGE_BUF, &start_seid, NULL); 4724 if (ret != I40E_SUCCESS) { 4725 PMD_DRV_LOG(ERR, "Failed to get switch configurations"); 4726 goto fail; 4727 } 4728 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported); 4729 if (num_reported != 1) { /* The number should be 1 */ 4730 PMD_DRV_LOG(ERR, "Wrong number of switch config reported"); 4731 goto fail; 4732 } 4733 4734 /* Parse the switch configuration elements */ 4735 element = &(switch_config->element[0]); 4736 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) { 4737 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid); 4738 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid); 4739 } else 4740 PMD_DRV_LOG(INFO, "Unknown element type"); 4741 4742 fail: 4743 rte_free(switch_config); 4744 4745 return ret; 4746 } 4747 4748 static int 4749 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base, 4750 uint32_t num) 4751 { 4752 struct pool_entry *entry; 4753 4754 if (pool == NULL || num == 0) 4755 return -EINVAL; 4756 4757 entry = rte_zmalloc("i40e", sizeof(*entry), 0); 4758 if (entry == NULL) { 4759 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool"); 4760 return -ENOMEM; 4761 } 4762 4763 /* queue heap initialize */ 4764 pool->num_free = num; 4765 pool->num_alloc = 0; 4766 pool->base = base; 4767 LIST_INIT(&pool->alloc_list); 4768 LIST_INIT(&pool->free_list); 4769 4770 /* Initialize element */ 4771 entry->base = 0; 4772 entry->len = num; 4773 4774 LIST_INSERT_HEAD(&pool->free_list, entry, next); 4775 return 0; 4776 } 4777 4778 static void 4779 i40e_res_pool_destroy(struct i40e_res_pool_info *pool) 4780 { 4781 struct pool_entry *entry, *next_entry; 4782 4783 if (pool == NULL) 4784 return; 4785 4786 for (entry = LIST_FIRST(&pool->alloc_list); 4787 entry && (next_entry = LIST_NEXT(entry, next), 1); 4788 entry = next_entry) { 4789 LIST_REMOVE(entry, next); 4790 rte_free(entry); 4791 } 4792 4793 for (entry = LIST_FIRST(&pool->free_list); 4794 entry && (next_entry = LIST_NEXT(entry, next), 1); 4795 entry = next_entry) { 4796 LIST_REMOVE(entry, next); 4797 rte_free(entry); 4798 } 4799 4800 pool->num_free = 0; 4801 pool->num_alloc = 0; 4802 pool->base = 0; 4803 LIST_INIT(&pool->alloc_list); 4804 LIST_INIT(&pool->free_list); 4805 } 4806 4807 static int 4808 i40e_res_pool_free(struct i40e_res_pool_info *pool, 4809 uint32_t base) 4810 { 4811 struct pool_entry *entry, *next, *prev, *valid_entry = NULL; 4812 uint32_t pool_offset; 4813 int insert; 4814 4815 if (pool == NULL) { 4816 PMD_DRV_LOG(ERR, "Invalid parameter"); 4817 return -EINVAL; 4818 } 4819 4820 pool_offset = base - pool->base; 4821 /* Lookup in alloc list */ 4822 LIST_FOREACH(entry, &pool->alloc_list, next) { 4823 if (entry->base == pool_offset) { 4824 valid_entry = entry; 4825 LIST_REMOVE(entry, next); 4826 break; 4827 } 4828 } 4829 4830 /* Not find, return */ 4831 if (valid_entry == NULL) { 4832 PMD_DRV_LOG(ERR, "Failed to find entry"); 4833 return -EINVAL; 4834 } 4835 4836 /** 4837 * Found it, move it to free list and try to merge. 4838 * In order to make merge easier, always sort it by qbase. 4839 * Find adjacent prev and last entries. 4840 */ 4841 prev = next = NULL; 4842 LIST_FOREACH(entry, &pool->free_list, next) { 4843 if (entry->base > valid_entry->base) { 4844 next = entry; 4845 break; 4846 } 4847 prev = entry; 4848 } 4849 4850 insert = 0; 4851 /* Try to merge with next one*/ 4852 if (next != NULL) { 4853 /* Merge with next one */ 4854 if (valid_entry->base + valid_entry->len == next->base) { 4855 next->base = valid_entry->base; 4856 next->len += valid_entry->len; 4857 rte_free(valid_entry); 4858 valid_entry = next; 4859 insert = 1; 4860 } 4861 } 4862 4863 if (prev != NULL) { 4864 /* Merge with previous one */ 4865 if (prev->base + prev->len == valid_entry->base) { 4866 prev->len += valid_entry->len; 4867 /* If it merge with next one, remove next node */ 4868 if (insert == 1) { 4869 LIST_REMOVE(valid_entry, next); 4870 rte_free(valid_entry); 4871 } else { 4872 rte_free(valid_entry); 4873 insert = 1; 4874 } 4875 } 4876 } 4877 4878 /* Not find any entry to merge, insert */ 4879 if (insert == 0) { 4880 if (prev != NULL) 4881 LIST_INSERT_AFTER(prev, valid_entry, next); 4882 else if (next != NULL) 4883 LIST_INSERT_BEFORE(next, valid_entry, next); 4884 else /* It's empty list, insert to head */ 4885 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next); 4886 } 4887 4888 pool->num_free += valid_entry->len; 4889 pool->num_alloc -= valid_entry->len; 4890 4891 return 0; 4892 } 4893 4894 static int 4895 i40e_res_pool_alloc(struct i40e_res_pool_info *pool, 4896 uint16_t num) 4897 { 4898 struct pool_entry *entry, *valid_entry; 4899 4900 if (pool == NULL || num == 0) { 4901 PMD_DRV_LOG(ERR, "Invalid parameter"); 4902 return -EINVAL; 4903 } 4904 4905 if (pool->num_free < num) { 4906 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u", 4907 num, pool->num_free); 4908 return -ENOMEM; 4909 } 4910 4911 valid_entry = NULL; 4912 /* Lookup in free list and find most fit one */ 4913 LIST_FOREACH(entry, &pool->free_list, next) { 4914 if (entry->len >= num) { 4915 /* Find best one */ 4916 if (entry->len == num) { 4917 valid_entry = entry; 4918 break; 4919 } 4920 if (valid_entry == NULL || valid_entry->len > entry->len) 4921 valid_entry = entry; 4922 } 4923 } 4924 4925 /* Not find one to satisfy the request, return */ 4926 if (valid_entry == NULL) { 4927 PMD_DRV_LOG(ERR, "No valid entry found"); 4928 return -ENOMEM; 4929 } 4930 /** 4931 * The entry have equal queue number as requested, 4932 * remove it from alloc_list. 4933 */ 4934 if (valid_entry->len == num) { 4935 LIST_REMOVE(valid_entry, next); 4936 } else { 4937 /** 4938 * The entry have more numbers than requested, 4939 * create a new entry for alloc_list and minus its 4940 * queue base and number in free_list. 4941 */ 4942 entry = rte_zmalloc("res_pool", sizeof(*entry), 0); 4943 if (entry == NULL) { 4944 PMD_DRV_LOG(ERR, 4945 "Failed to allocate memory for resource pool"); 4946 return -ENOMEM; 4947 } 4948 entry->base = valid_entry->base; 4949 entry->len = num; 4950 valid_entry->base += num; 4951 valid_entry->len -= num; 4952 valid_entry = entry; 4953 } 4954 4955 /* Insert it into alloc list, not sorted */ 4956 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 4957 4958 pool->num_free -= valid_entry->len; 4959 pool->num_alloc += valid_entry->len; 4960 4961 return valid_entry->base + pool->base; 4962 } 4963 4964 /** 4965 * bitmap_is_subset - Check whether src2 is subset of src1 4966 **/ 4967 static inline int 4968 bitmap_is_subset(uint8_t src1, uint8_t src2) 4969 { 4970 return !((src1 ^ src2) & src2); 4971 } 4972 4973 static enum i40e_status_code 4974 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap) 4975 { 4976 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 4977 4978 /* If DCB is not supported, only default TC is supported */ 4979 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) { 4980 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported"); 4981 return I40E_NOT_SUPPORTED; 4982 } 4983 4984 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) { 4985 PMD_DRV_LOG(ERR, 4986 "Enabled TC map 0x%x not applicable to HW support 0x%x", 4987 hw->func_caps.enabled_tcmap, enabled_tcmap); 4988 return I40E_NOT_SUPPORTED; 4989 } 4990 return I40E_SUCCESS; 4991 } 4992 4993 int 4994 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 4995 struct i40e_vsi_vlan_pvid_info *info) 4996 { 4997 struct i40e_hw *hw; 4998 struct i40e_vsi_context ctxt; 4999 uint8_t vlan_flags = 0; 5000 int ret; 5001 5002 if (vsi == NULL || info == NULL) { 5003 PMD_DRV_LOG(ERR, "invalid parameters"); 5004 return I40E_ERR_PARAM; 5005 } 5006 5007 if (info->on) { 5008 vsi->info.pvid = info->config.pvid; 5009 /** 5010 * If insert pvid is enabled, only tagged pkts are 5011 * allowed to be sent out. 5012 */ 5013 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID | 5014 I40E_AQ_VSI_PVLAN_MODE_TAGGED; 5015 } else { 5016 vsi->info.pvid = 0; 5017 if (info->config.reject.tagged == 0) 5018 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED; 5019 5020 if (info->config.reject.untagged == 0) 5021 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED; 5022 } 5023 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID | 5024 I40E_AQ_VSI_PVLAN_MODE_MASK); 5025 vsi->info.port_vlan_flags |= vlan_flags; 5026 vsi->info.valid_sections = 5027 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5028 memset(&ctxt, 0, sizeof(ctxt)); 5029 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 5030 ctxt.seid = vsi->seid; 5031 5032 hw = I40E_VSI_TO_HW(vsi); 5033 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5034 if (ret != I40E_SUCCESS) 5035 PMD_DRV_LOG(ERR, "Failed to update VSI params"); 5036 5037 return ret; 5038 } 5039 5040 static int 5041 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap) 5042 { 5043 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5044 int i, ret; 5045 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data; 5046 5047 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 5048 if (ret != I40E_SUCCESS) 5049 return ret; 5050 5051 if (!vsi->seid) { 5052 PMD_DRV_LOG(ERR, "seid not valid"); 5053 return -EINVAL; 5054 } 5055 5056 memset(&tc_bw_data, 0, sizeof(tc_bw_data)); 5057 tc_bw_data.tc_valid_bits = enabled_tcmap; 5058 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 5059 tc_bw_data.tc_bw_credits[i] = 5060 (enabled_tcmap & (1 << i)) ? 1 : 0; 5061 5062 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL); 5063 if (ret != I40E_SUCCESS) { 5064 PMD_DRV_LOG(ERR, "Failed to configure TC BW"); 5065 return ret; 5066 } 5067 5068 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles, 5069 sizeof(vsi->info.qs_handle)); 5070 return I40E_SUCCESS; 5071 } 5072 5073 static enum i40e_status_code 5074 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi, 5075 struct i40e_aqc_vsi_properties_data *info, 5076 uint8_t enabled_tcmap) 5077 { 5078 enum i40e_status_code ret; 5079 int i, total_tc = 0; 5080 uint16_t qpnum_per_tc, bsf, qp_idx; 5081 5082 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 5083 if (ret != I40E_SUCCESS) 5084 return ret; 5085 5086 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 5087 if (enabled_tcmap & (1 << i)) 5088 total_tc++; 5089 if (total_tc == 0) 5090 total_tc = 1; 5091 vsi->enabled_tc = enabled_tcmap; 5092 5093 /* Number of queues per enabled TC */ 5094 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc); 5095 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC); 5096 bsf = rte_bsf32(qpnum_per_tc); 5097 5098 /* Adjust the queue number to actual queues that can be applied */ 5099 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1)) 5100 vsi->nb_qps = qpnum_per_tc * total_tc; 5101 5102 /** 5103 * Configure TC and queue mapping parameters, for enabled TC, 5104 * allocate qpnum_per_tc queues to this traffic. For disabled TC, 5105 * default queue will serve it. 5106 */ 5107 qp_idx = 0; 5108 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 5109 if (vsi->enabled_tc & (1 << i)) { 5110 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx << 5111 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 5112 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 5113 qp_idx += qpnum_per_tc; 5114 } else 5115 info->tc_mapping[i] = 0; 5116 } 5117 5118 /* Associate queue number with VSI */ 5119 if (vsi->type == I40E_VSI_SRIOV) { 5120 info->mapping_flags |= 5121 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 5122 for (i = 0; i < vsi->nb_qps; i++) 5123 info->queue_mapping[i] = 5124 rte_cpu_to_le_16(vsi->base_queue + i); 5125 } else { 5126 info->mapping_flags |= 5127 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG); 5128 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 5129 } 5130 info->valid_sections |= 5131 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 5132 5133 return I40E_SUCCESS; 5134 } 5135 5136 static int 5137 i40e_veb_release(struct i40e_veb *veb) 5138 { 5139 struct i40e_vsi *vsi; 5140 struct i40e_hw *hw; 5141 5142 if (veb == NULL) 5143 return -EINVAL; 5144 5145 if (!TAILQ_EMPTY(&veb->head)) { 5146 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove"); 5147 return -EACCES; 5148 } 5149 /* associate_vsi field is NULL for floating VEB */ 5150 if (veb->associate_vsi != NULL) { 5151 vsi = veb->associate_vsi; 5152 hw = I40E_VSI_TO_HW(vsi); 5153 5154 vsi->uplink_seid = veb->uplink_seid; 5155 vsi->veb = NULL; 5156 } else { 5157 veb->associate_pf->main_vsi->floating_veb = NULL; 5158 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi); 5159 } 5160 5161 i40e_aq_delete_element(hw, veb->seid, NULL); 5162 rte_free(veb); 5163 return I40E_SUCCESS; 5164 } 5165 5166 /* Setup a veb */ 5167 static struct i40e_veb * 5168 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi) 5169 { 5170 struct i40e_veb *veb; 5171 int ret; 5172 struct i40e_hw *hw; 5173 5174 if (pf == NULL) { 5175 PMD_DRV_LOG(ERR, 5176 "veb setup failed, associated PF shouldn't null"); 5177 return NULL; 5178 } 5179 hw = I40E_PF_TO_HW(pf); 5180 5181 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0); 5182 if (!veb) { 5183 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb"); 5184 goto fail; 5185 } 5186 5187 veb->associate_vsi = vsi; 5188 veb->associate_pf = pf; 5189 TAILQ_INIT(&veb->head); 5190 veb->uplink_seid = vsi ? vsi->uplink_seid : 0; 5191 5192 /* create floating veb if vsi is NULL */ 5193 if (vsi != NULL) { 5194 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid, 5195 I40E_DEFAULT_TCMAP, false, 5196 &veb->seid, false, NULL); 5197 } else { 5198 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP, 5199 true, &veb->seid, false, NULL); 5200 } 5201 5202 if (ret != I40E_SUCCESS) { 5203 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d", 5204 hw->aq.asq_last_status); 5205 goto fail; 5206 } 5207 veb->enabled_tc = I40E_DEFAULT_TCMAP; 5208 5209 /* get statistics index */ 5210 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL, 5211 &veb->stats_idx, NULL, NULL, NULL); 5212 if (ret != I40E_SUCCESS) { 5213 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d", 5214 hw->aq.asq_last_status); 5215 goto fail; 5216 } 5217 /* Get VEB bandwidth, to be implemented */ 5218 /* Now associated vsi binding to the VEB, set uplink to this VEB */ 5219 if (vsi) 5220 vsi->uplink_seid = veb->seid; 5221 5222 return veb; 5223 fail: 5224 rte_free(veb); 5225 return NULL; 5226 } 5227 5228 int 5229 i40e_vsi_release(struct i40e_vsi *vsi) 5230 { 5231 struct i40e_pf *pf; 5232 struct i40e_hw *hw; 5233 struct i40e_vsi_list *vsi_list; 5234 void *temp; 5235 int ret; 5236 struct i40e_mac_filter *f; 5237 uint16_t user_param; 5238 5239 if (!vsi) 5240 return I40E_SUCCESS; 5241 5242 if (!vsi->adapter) 5243 return -EFAULT; 5244 5245 user_param = vsi->user_param; 5246 5247 pf = I40E_VSI_TO_PF(vsi); 5248 hw = I40E_VSI_TO_HW(vsi); 5249 5250 /* VSI has child to attach, release child first */ 5251 if (vsi->veb) { 5252 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) { 5253 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS) 5254 return -1; 5255 } 5256 i40e_veb_release(vsi->veb); 5257 } 5258 5259 if (vsi->floating_veb) { 5260 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) { 5261 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS) 5262 return -1; 5263 } 5264 } 5265 5266 /* Remove all macvlan filters of the VSI */ 5267 i40e_vsi_remove_all_macvlan_filter(vsi); 5268 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) 5269 rte_free(f); 5270 5271 if (vsi->type != I40E_VSI_MAIN && 5272 ((vsi->type != I40E_VSI_SRIOV) || 5273 !pf->floating_veb_list[user_param])) { 5274 /* Remove vsi from parent's sibling list */ 5275 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) { 5276 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL"); 5277 return I40E_ERR_PARAM; 5278 } 5279 TAILQ_REMOVE(&vsi->parent_vsi->veb->head, 5280 &vsi->sib_vsi_list, list); 5281 5282 /* Remove all switch element of the VSI */ 5283 ret = i40e_aq_delete_element(hw, vsi->seid, NULL); 5284 if (ret != I40E_SUCCESS) 5285 PMD_DRV_LOG(ERR, "Failed to delete element"); 5286 } 5287 5288 if ((vsi->type == I40E_VSI_SRIOV) && 5289 pf->floating_veb_list[user_param]) { 5290 /* Remove vsi from parent's sibling list */ 5291 if (vsi->parent_vsi == NULL || 5292 vsi->parent_vsi->floating_veb == NULL) { 5293 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL"); 5294 return I40E_ERR_PARAM; 5295 } 5296 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head, 5297 &vsi->sib_vsi_list, list); 5298 5299 /* Remove all switch element of the VSI */ 5300 ret = i40e_aq_delete_element(hw, vsi->seid, NULL); 5301 if (ret != I40E_SUCCESS) 5302 PMD_DRV_LOG(ERR, "Failed to delete element"); 5303 } 5304 5305 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue); 5306 5307 if (vsi->type != I40E_VSI_SRIOV) 5308 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr); 5309 rte_free(vsi); 5310 5311 return I40E_SUCCESS; 5312 } 5313 5314 static int 5315 i40e_update_default_filter_setting(struct i40e_vsi *vsi) 5316 { 5317 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5318 struct i40e_aqc_remove_macvlan_element_data def_filter; 5319 struct i40e_mac_filter_info filter; 5320 int ret; 5321 5322 if (vsi->type != I40E_VSI_MAIN) 5323 return I40E_ERR_CONFIG; 5324 memset(&def_filter, 0, sizeof(def_filter)); 5325 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr, 5326 ETH_ADDR_LEN); 5327 def_filter.vlan_tag = 0; 5328 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 5329 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 5330 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL); 5331 if (ret != I40E_SUCCESS) { 5332 struct i40e_mac_filter *f; 5333 struct rte_ether_addr *mac; 5334 5335 PMD_DRV_LOG(DEBUG, 5336 "Cannot remove the default macvlan filter"); 5337 /* It needs to add the permanent mac into mac list */ 5338 f = rte_zmalloc("macv_filter", sizeof(*f), 0); 5339 if (f == NULL) { 5340 PMD_DRV_LOG(ERR, "failed to allocate memory"); 5341 return I40E_ERR_NO_MEMORY; 5342 } 5343 mac = &f->mac_info.mac_addr; 5344 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr, 5345 ETH_ADDR_LEN); 5346 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5347 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 5348 vsi->mac_num++; 5349 5350 return ret; 5351 } 5352 rte_memcpy(&filter.mac_addr, 5353 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN); 5354 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5355 return i40e_vsi_add_mac(vsi, &filter); 5356 } 5357 5358 /* 5359 * i40e_vsi_get_bw_config - Query VSI BW Information 5360 * @vsi: the VSI to be queried 5361 * 5362 * Returns 0 on success, negative value on failure 5363 */ 5364 static enum i40e_status_code 5365 i40e_vsi_get_bw_config(struct i40e_vsi *vsi) 5366 { 5367 struct i40e_aqc_query_vsi_bw_config_resp bw_config; 5368 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config; 5369 struct i40e_hw *hw = &vsi->adapter->hw; 5370 i40e_status ret; 5371 int i; 5372 uint32_t bw_max; 5373 5374 memset(&bw_config, 0, sizeof(bw_config)); 5375 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); 5376 if (ret != I40E_SUCCESS) { 5377 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u", 5378 hw->aq.asq_last_status); 5379 return ret; 5380 } 5381 5382 memset(&ets_sla_config, 0, sizeof(ets_sla_config)); 5383 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, 5384 &ets_sla_config, NULL); 5385 if (ret != I40E_SUCCESS) { 5386 PMD_DRV_LOG(ERR, 5387 "VSI failed to get TC bandwdith configuration %u", 5388 hw->aq.asq_last_status); 5389 return ret; 5390 } 5391 5392 /* store and print out BW info */ 5393 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit); 5394 vsi->bw_info.bw_max = bw_config.max_bw; 5395 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit); 5396 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max); 5397 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) | 5398 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) << 5399 I40E_16_BIT_WIDTH); 5400 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 5401 vsi->bw_info.bw_ets_share_credits[i] = 5402 ets_sla_config.share_credits[i]; 5403 vsi->bw_info.bw_ets_credits[i] = 5404 rte_le_to_cpu_16(ets_sla_config.credits[i]); 5405 /* 4 bits per TC, 4th bit is reserved */ 5406 vsi->bw_info.bw_ets_max[i] = 5407 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) & 5408 RTE_LEN2MASK(3, uint8_t)); 5409 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i, 5410 vsi->bw_info.bw_ets_share_credits[i]); 5411 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i, 5412 vsi->bw_info.bw_ets_credits[i]); 5413 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i, 5414 vsi->bw_info.bw_ets_max[i]); 5415 } 5416 5417 return I40E_SUCCESS; 5418 } 5419 5420 /* i40e_enable_pf_lb 5421 * @pf: pointer to the pf structure 5422 * 5423 * allow loopback on pf 5424 */ 5425 static inline void 5426 i40e_enable_pf_lb(struct i40e_pf *pf) 5427 { 5428 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 5429 struct i40e_vsi_context ctxt; 5430 int ret; 5431 5432 /* Use the FW API if FW >= v5.0 */ 5433 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) { 5434 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback"); 5435 return; 5436 } 5437 5438 memset(&ctxt, 0, sizeof(ctxt)); 5439 ctxt.seid = pf->main_vsi_seid; 5440 ctxt.pf_num = hw->pf_id; 5441 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 5442 if (ret) { 5443 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d", 5444 ret, hw->aq.asq_last_status); 5445 return; 5446 } 5447 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 5448 ctxt.info.valid_sections = 5449 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5450 ctxt.info.switch_id |= 5451 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5452 5453 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5454 if (ret) 5455 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d", 5456 hw->aq.asq_last_status); 5457 } 5458 5459 /* Setup a VSI */ 5460 struct i40e_vsi * 5461 i40e_vsi_setup(struct i40e_pf *pf, 5462 enum i40e_vsi_type type, 5463 struct i40e_vsi *uplink_vsi, 5464 uint16_t user_param) 5465 { 5466 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 5467 struct i40e_vsi *vsi; 5468 struct i40e_mac_filter_info filter; 5469 int ret; 5470 struct i40e_vsi_context ctxt; 5471 struct rte_ether_addr broadcast = 5472 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; 5473 5474 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV && 5475 uplink_vsi == NULL) { 5476 PMD_DRV_LOG(ERR, 5477 "VSI setup failed, VSI link shouldn't be NULL"); 5478 return NULL; 5479 } 5480 5481 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) { 5482 PMD_DRV_LOG(ERR, 5483 "VSI setup failed, MAIN VSI uplink VSI should be NULL"); 5484 return NULL; 5485 } 5486 5487 /* two situations 5488 * 1.type is not MAIN and uplink vsi is not NULL 5489 * If uplink vsi didn't setup VEB, create one first under veb field 5490 * 2.type is SRIOV and the uplink is NULL 5491 * If floating VEB is NULL, create one veb under floating veb field 5492 */ 5493 5494 if (type != I40E_VSI_MAIN && uplink_vsi != NULL && 5495 uplink_vsi->veb == NULL) { 5496 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi); 5497 5498 if (uplink_vsi->veb == NULL) { 5499 PMD_DRV_LOG(ERR, "VEB setup failed"); 5500 return NULL; 5501 } 5502 /* set ALLOWLOOPBACk on pf, when veb is created */ 5503 i40e_enable_pf_lb(pf); 5504 } 5505 5506 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL && 5507 pf->main_vsi->floating_veb == NULL) { 5508 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi); 5509 5510 if (pf->main_vsi->floating_veb == NULL) { 5511 PMD_DRV_LOG(ERR, "VEB setup failed"); 5512 return NULL; 5513 } 5514 } 5515 5516 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0); 5517 if (!vsi) { 5518 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi"); 5519 return NULL; 5520 } 5521 TAILQ_INIT(&vsi->mac_list); 5522 vsi->type = type; 5523 vsi->adapter = I40E_PF_TO_ADAPTER(pf); 5524 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX; 5525 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi; 5526 vsi->user_param = user_param; 5527 vsi->vlan_anti_spoof_on = 0; 5528 vsi->vlan_filter_on = 0; 5529 /* Allocate queues */ 5530 switch (vsi->type) { 5531 case I40E_VSI_MAIN : 5532 vsi->nb_qps = pf->lan_nb_qps; 5533 break; 5534 case I40E_VSI_SRIOV : 5535 vsi->nb_qps = pf->vf_nb_qps; 5536 break; 5537 case I40E_VSI_VMDQ2: 5538 vsi->nb_qps = pf->vmdq_nb_qps; 5539 break; 5540 case I40E_VSI_FDIR: 5541 vsi->nb_qps = pf->fdir_nb_qps; 5542 break; 5543 default: 5544 goto fail_mem; 5545 } 5546 /* 5547 * The filter status descriptor is reported in rx queue 0, 5548 * while the tx queue for fdir filter programming has no 5549 * such constraints, can be non-zero queues. 5550 * To simplify it, choose FDIR vsi use queue 0 pair. 5551 * To make sure it will use queue 0 pair, queue allocation 5552 * need be done before this function is called 5553 */ 5554 if (type != I40E_VSI_FDIR) { 5555 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps); 5556 if (ret < 0) { 5557 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d", 5558 vsi->seid, ret); 5559 goto fail_mem; 5560 } 5561 vsi->base_queue = ret; 5562 } else 5563 vsi->base_queue = I40E_FDIR_QUEUE_ID; 5564 5565 /* VF has MSIX interrupt in VF range, don't allocate here */ 5566 if (type == I40E_VSI_MAIN) { 5567 if (pf->support_multi_driver) { 5568 /* If support multi-driver, need to use INT0 instead of 5569 * allocating from msix pool. The Msix pool is init from 5570 * INT1, so it's OK just set msix_intr to 0 and nb_msix 5571 * to 1 without calling i40e_res_pool_alloc. 5572 */ 5573 vsi->msix_intr = 0; 5574 vsi->nb_msix = 1; 5575 } else { 5576 ret = i40e_res_pool_alloc(&pf->msix_pool, 5577 RTE_MIN(vsi->nb_qps, 5578 RTE_MAX_RXTX_INTR_VEC_ID)); 5579 if (ret < 0) { 5580 PMD_DRV_LOG(ERR, 5581 "VSI MAIN %d get heap failed %d", 5582 vsi->seid, ret); 5583 goto fail_queue_alloc; 5584 } 5585 vsi->msix_intr = ret; 5586 vsi->nb_msix = RTE_MIN(vsi->nb_qps, 5587 RTE_MAX_RXTX_INTR_VEC_ID); 5588 } 5589 } else if (type != I40E_VSI_SRIOV) { 5590 ret = i40e_res_pool_alloc(&pf->msix_pool, 1); 5591 if (ret < 0) { 5592 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret); 5593 goto fail_queue_alloc; 5594 } 5595 vsi->msix_intr = ret; 5596 vsi->nb_msix = 1; 5597 } else { 5598 vsi->msix_intr = 0; 5599 vsi->nb_msix = 0; 5600 } 5601 5602 /* Add VSI */ 5603 if (type == I40E_VSI_MAIN) { 5604 /* For main VSI, no need to add since it's default one */ 5605 vsi->uplink_seid = pf->mac_seid; 5606 vsi->seid = pf->main_vsi_seid; 5607 /* Bind queues with specific MSIX interrupt */ 5608 /** 5609 * Needs 2 interrupt at least, one for misc cause which will 5610 * enabled from OS side, Another for queues binding the 5611 * interrupt from device side only. 5612 */ 5613 5614 /* Get default VSI parameters from hardware */ 5615 memset(&ctxt, 0, sizeof(ctxt)); 5616 ctxt.seid = vsi->seid; 5617 ctxt.pf_num = hw->pf_id; 5618 ctxt.uplink_seid = vsi->uplink_seid; 5619 ctxt.vf_num = 0; 5620 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 5621 if (ret != I40E_SUCCESS) { 5622 PMD_DRV_LOG(ERR, "Failed to get VSI params"); 5623 goto fail_msix_alloc; 5624 } 5625 rte_memcpy(&vsi->info, &ctxt.info, 5626 sizeof(struct i40e_aqc_vsi_properties_data)); 5627 vsi->vsi_id = ctxt.vsi_number; 5628 vsi->info.valid_sections = 0; 5629 5630 /* Configure tc, enabled TC0 only */ 5631 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) != 5632 I40E_SUCCESS) { 5633 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth"); 5634 goto fail_msix_alloc; 5635 } 5636 5637 /* TC, queue mapping */ 5638 memset(&ctxt, 0, sizeof(ctxt)); 5639 vsi->info.valid_sections |= 5640 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5641 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 5642 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 5643 rte_memcpy(&ctxt.info, &vsi->info, 5644 sizeof(struct i40e_aqc_vsi_properties_data)); 5645 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5646 I40E_DEFAULT_TCMAP); 5647 if (ret != I40E_SUCCESS) { 5648 PMD_DRV_LOG(ERR, 5649 "Failed to configure TC queue mapping"); 5650 goto fail_msix_alloc; 5651 } 5652 ctxt.seid = vsi->seid; 5653 ctxt.pf_num = hw->pf_id; 5654 ctxt.uplink_seid = vsi->uplink_seid; 5655 ctxt.vf_num = 0; 5656 5657 /* Update VSI parameters */ 5658 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5659 if (ret != I40E_SUCCESS) { 5660 PMD_DRV_LOG(ERR, "Failed to update VSI params"); 5661 goto fail_msix_alloc; 5662 } 5663 5664 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping, 5665 sizeof(vsi->info.tc_mapping)); 5666 rte_memcpy(&vsi->info.queue_mapping, 5667 &ctxt.info.queue_mapping, 5668 sizeof(vsi->info.queue_mapping)); 5669 vsi->info.mapping_flags = ctxt.info.mapping_flags; 5670 vsi->info.valid_sections = 0; 5671 5672 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr, 5673 ETH_ADDR_LEN); 5674 5675 /** 5676 * Updating default filter settings are necessary to prevent 5677 * reception of tagged packets. 5678 * Some old firmware configurations load a default macvlan 5679 * filter which accepts both tagged and untagged packets. 5680 * The updating is to use a normal filter instead if needed. 5681 * For NVM 4.2.2 or after, the updating is not needed anymore. 5682 * The firmware with correct configurations load the default 5683 * macvlan filter which is expected and cannot be removed. 5684 */ 5685 i40e_update_default_filter_setting(vsi); 5686 i40e_config_qinq(hw, vsi); 5687 } else if (type == I40E_VSI_SRIOV) { 5688 memset(&ctxt, 0, sizeof(ctxt)); 5689 /** 5690 * For other VSI, the uplink_seid equals to uplink VSI's 5691 * uplink_seid since they share same VEB 5692 */ 5693 if (uplink_vsi == NULL) 5694 vsi->uplink_seid = pf->main_vsi->floating_veb->seid; 5695 else 5696 vsi->uplink_seid = uplink_vsi->uplink_seid; 5697 ctxt.pf_num = hw->pf_id; 5698 ctxt.vf_num = hw->func_caps.vf_base_id + user_param; 5699 ctxt.uplink_seid = vsi->uplink_seid; 5700 ctxt.connection_type = 0x1; 5701 ctxt.flags = I40E_AQ_VSI_TYPE_VF; 5702 5703 /* Use the VEB configuration if FW >= v5.0 */ 5704 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) { 5705 /* Configure switch ID */ 5706 ctxt.info.valid_sections |= 5707 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5708 ctxt.info.switch_id = 5709 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5710 } 5711 5712 /* Configure port/vlan */ 5713 ctxt.info.valid_sections |= 5714 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5715 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 5716 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5717 hw->func_caps.enabled_tcmap); 5718 if (ret != I40E_SUCCESS) { 5719 PMD_DRV_LOG(ERR, 5720 "Failed to configure TC queue mapping"); 5721 goto fail_msix_alloc; 5722 } 5723 5724 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap; 5725 ctxt.info.valid_sections |= 5726 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5727 /** 5728 * Since VSI is not created yet, only configure parameter, 5729 * will add vsi below. 5730 */ 5731 5732 i40e_config_qinq(hw, vsi); 5733 } else if (type == I40E_VSI_VMDQ2) { 5734 memset(&ctxt, 0, sizeof(ctxt)); 5735 /* 5736 * For other VSI, the uplink_seid equals to uplink VSI's 5737 * uplink_seid since they share same VEB 5738 */ 5739 vsi->uplink_seid = uplink_vsi->uplink_seid; 5740 ctxt.pf_num = hw->pf_id; 5741 ctxt.vf_num = 0; 5742 ctxt.uplink_seid = vsi->uplink_seid; 5743 ctxt.connection_type = 0x1; 5744 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; 5745 5746 ctxt.info.valid_sections |= 5747 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5748 /* user_param carries flag to enable loop back */ 5749 if (user_param) { 5750 ctxt.info.switch_id = 5751 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB); 5752 ctxt.info.switch_id |= 5753 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5754 } 5755 5756 /* Configure port/vlan */ 5757 ctxt.info.valid_sections |= 5758 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5759 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 5760 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5761 I40E_DEFAULT_TCMAP); 5762 if (ret != I40E_SUCCESS) { 5763 PMD_DRV_LOG(ERR, 5764 "Failed to configure TC queue mapping"); 5765 goto fail_msix_alloc; 5766 } 5767 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP; 5768 ctxt.info.valid_sections |= 5769 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5770 } else if (type == I40E_VSI_FDIR) { 5771 memset(&ctxt, 0, sizeof(ctxt)); 5772 vsi->uplink_seid = uplink_vsi->uplink_seid; 5773 ctxt.pf_num = hw->pf_id; 5774 ctxt.vf_num = 0; 5775 ctxt.uplink_seid = vsi->uplink_seid; 5776 ctxt.connection_type = 0x1; /* regular data port */ 5777 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 5778 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5779 I40E_DEFAULT_TCMAP); 5780 if (ret != I40E_SUCCESS) { 5781 PMD_DRV_LOG(ERR, 5782 "Failed to configure TC queue mapping."); 5783 goto fail_msix_alloc; 5784 } 5785 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP; 5786 ctxt.info.valid_sections |= 5787 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5788 } else { 5789 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet"); 5790 goto fail_msix_alloc; 5791 } 5792 5793 if (vsi->type != I40E_VSI_MAIN) { 5794 ret = i40e_aq_add_vsi(hw, &ctxt, NULL); 5795 if (ret != I40E_SUCCESS) { 5796 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d", 5797 hw->aq.asq_last_status); 5798 goto fail_msix_alloc; 5799 } 5800 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 5801 vsi->info.valid_sections = 0; 5802 vsi->seid = ctxt.seid; 5803 vsi->vsi_id = ctxt.vsi_number; 5804 vsi->sib_vsi_list.vsi = vsi; 5805 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) { 5806 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head, 5807 &vsi->sib_vsi_list, list); 5808 } else { 5809 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head, 5810 &vsi->sib_vsi_list, list); 5811 } 5812 } 5813 5814 /* MAC/VLAN configuration */ 5815 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN); 5816 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5817 5818 ret = i40e_vsi_add_mac(vsi, &filter); 5819 if (ret != I40E_SUCCESS) { 5820 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter"); 5821 goto fail_msix_alloc; 5822 } 5823 5824 /* Get VSI BW information */ 5825 i40e_vsi_get_bw_config(vsi); 5826 return vsi; 5827 fail_msix_alloc: 5828 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr); 5829 fail_queue_alloc: 5830 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue); 5831 fail_mem: 5832 rte_free(vsi); 5833 return NULL; 5834 } 5835 5836 /* Configure vlan filter on or off */ 5837 int 5838 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on) 5839 { 5840 int i, num; 5841 struct i40e_mac_filter *f; 5842 void *temp; 5843 struct i40e_mac_filter_info *mac_filter; 5844 enum rte_mac_filter_type desired_filter; 5845 int ret = I40E_SUCCESS; 5846 5847 if (on) { 5848 /* Filter to match MAC and VLAN */ 5849 desired_filter = RTE_MACVLAN_PERFECT_MATCH; 5850 } else { 5851 /* Filter to match only MAC */ 5852 desired_filter = RTE_MAC_PERFECT_MATCH; 5853 } 5854 5855 num = vsi->mac_num; 5856 5857 mac_filter = rte_zmalloc("mac_filter_info_data", 5858 num * sizeof(*mac_filter), 0); 5859 if (mac_filter == NULL) { 5860 PMD_DRV_LOG(ERR, "failed to allocate memory"); 5861 return I40E_ERR_NO_MEMORY; 5862 } 5863 5864 i = 0; 5865 5866 /* Remove all existing mac */ 5867 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) { 5868 mac_filter[i] = f->mac_info; 5869 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr); 5870 if (ret) { 5871 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter", 5872 on ? "enable" : "disable"); 5873 goto DONE; 5874 } 5875 i++; 5876 } 5877 5878 /* Override with new filter */ 5879 for (i = 0; i < num; i++) { 5880 mac_filter[i].filter_type = desired_filter; 5881 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]); 5882 if (ret) { 5883 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter", 5884 on ? "enable" : "disable"); 5885 goto DONE; 5886 } 5887 } 5888 5889 DONE: 5890 rte_free(mac_filter); 5891 return ret; 5892 } 5893 5894 /* Configure vlan stripping on or off */ 5895 int 5896 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on) 5897 { 5898 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5899 struct i40e_vsi_context ctxt; 5900 uint8_t vlan_flags; 5901 int ret = I40E_SUCCESS; 5902 5903 /* Check if it has been already on or off */ 5904 if (vsi->info.valid_sections & 5905 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) { 5906 if (on) { 5907 if ((vsi->info.port_vlan_flags & 5908 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0) 5909 return 0; /* already on */ 5910 } else { 5911 if ((vsi->info.port_vlan_flags & 5912 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 5913 I40E_AQ_VSI_PVLAN_EMOD_MASK) 5914 return 0; /* already off */ 5915 } 5916 } 5917 5918 if (on) 5919 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 5920 else 5921 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 5922 vsi->info.valid_sections = 5923 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5924 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK); 5925 vsi->info.port_vlan_flags |= vlan_flags; 5926 ctxt.seid = vsi->seid; 5927 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 5928 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5929 if (ret) 5930 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 5931 on ? "enable" : "disable"); 5932 5933 return ret; 5934 } 5935 5936 static int 5937 i40e_dev_init_vlan(struct rte_eth_dev *dev) 5938 { 5939 struct rte_eth_dev_data *data = dev->data; 5940 int ret; 5941 int mask = 0; 5942 5943 /* Apply vlan offload setting */ 5944 mask = ETH_VLAN_STRIP_MASK | 5945 ETH_VLAN_FILTER_MASK | 5946 ETH_VLAN_EXTEND_MASK; 5947 ret = i40e_vlan_offload_set(dev, mask); 5948 if (ret) { 5949 PMD_DRV_LOG(INFO, "Failed to update vlan offload"); 5950 return ret; 5951 } 5952 5953 /* Apply pvid setting */ 5954 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid, 5955 data->dev_conf.txmode.hw_vlan_insert_pvid); 5956 if (ret) 5957 PMD_DRV_LOG(INFO, "Failed to update VSI params"); 5958 5959 return ret; 5960 } 5961 5962 static int 5963 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on) 5964 { 5965 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5966 5967 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL); 5968 } 5969 5970 static int 5971 i40e_update_flow_control(struct i40e_hw *hw) 5972 { 5973 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX) 5974 struct i40e_link_status link_status; 5975 uint32_t rxfc = 0, txfc = 0, reg; 5976 uint8_t an_info; 5977 int ret; 5978 5979 memset(&link_status, 0, sizeof(link_status)); 5980 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL); 5981 if (ret != I40E_SUCCESS) { 5982 PMD_DRV_LOG(ERR, "Failed to get link status information"); 5983 goto write_reg; /* Disable flow control */ 5984 } 5985 5986 an_info = hw->phy.link_info.an_info; 5987 if (!(an_info & I40E_AQ_AN_COMPLETED)) { 5988 PMD_DRV_LOG(INFO, "Link auto negotiation not completed"); 5989 ret = I40E_ERR_NOT_READY; 5990 goto write_reg; /* Disable flow control */ 5991 } 5992 /** 5993 * If link auto negotiation is enabled, flow control needs to 5994 * be configured according to it 5995 */ 5996 switch (an_info & I40E_LINK_PAUSE_RXTX) { 5997 case I40E_LINK_PAUSE_RXTX: 5998 rxfc = 1; 5999 txfc = 1; 6000 hw->fc.current_mode = I40E_FC_FULL; 6001 break; 6002 case I40E_AQ_LINK_PAUSE_RX: 6003 rxfc = 1; 6004 hw->fc.current_mode = I40E_FC_RX_PAUSE; 6005 break; 6006 case I40E_AQ_LINK_PAUSE_TX: 6007 txfc = 1; 6008 hw->fc.current_mode = I40E_FC_TX_PAUSE; 6009 break; 6010 default: 6011 hw->fc.current_mode = I40E_FC_NONE; 6012 break; 6013 } 6014 6015 write_reg: 6016 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG, 6017 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT); 6018 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); 6019 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK; 6020 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT; 6021 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg); 6022 6023 return ret; 6024 } 6025 6026 /* PF setup */ 6027 static int 6028 i40e_pf_setup(struct i40e_pf *pf) 6029 { 6030 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 6031 struct i40e_filter_control_settings settings; 6032 struct i40e_vsi *vsi; 6033 int ret; 6034 6035 /* Clear all stats counters */ 6036 pf->offset_loaded = FALSE; 6037 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats)); 6038 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats)); 6039 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats)); 6040 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats)); 6041 6042 ret = i40e_pf_get_switch_config(pf); 6043 if (ret != I40E_SUCCESS) { 6044 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret); 6045 return ret; 6046 } 6047 6048 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id); 6049 if (ret) 6050 PMD_INIT_LOG(WARNING, 6051 "failed to allocate switch domain for device %d", ret); 6052 6053 if (pf->flags & I40E_FLAG_FDIR) { 6054 /* make queue allocated first, let FDIR use queue pair 0*/ 6055 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR); 6056 if (ret != I40E_FDIR_QUEUE_ID) { 6057 PMD_DRV_LOG(ERR, 6058 "queue allocation fails for FDIR: ret =%d", 6059 ret); 6060 pf->flags &= ~I40E_FLAG_FDIR; 6061 } 6062 } 6063 /* main VSI setup */ 6064 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0); 6065 if (!vsi) { 6066 PMD_DRV_LOG(ERR, "Setup of main vsi failed"); 6067 return I40E_ERR_NOT_READY; 6068 } 6069 pf->main_vsi = vsi; 6070 6071 /* Configure filter control */ 6072 memset(&settings, 0, sizeof(settings)); 6073 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128) 6074 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128; 6075 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512) 6076 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512; 6077 else { 6078 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported", 6079 hw->func_caps.rss_table_size); 6080 return I40E_ERR_PARAM; 6081 } 6082 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u", 6083 hw->func_caps.rss_table_size); 6084 pf->hash_lut_size = hw->func_caps.rss_table_size; 6085 6086 /* Enable ethtype and macvlan filters */ 6087 settings.enable_ethtype = TRUE; 6088 settings.enable_macvlan = TRUE; 6089 ret = i40e_set_filter_control(hw, &settings); 6090 if (ret) 6091 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d", 6092 ret); 6093 6094 /* Update flow control according to the auto negotiation */ 6095 i40e_update_flow_control(hw); 6096 6097 return I40E_SUCCESS; 6098 } 6099 6100 int 6101 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) 6102 { 6103 uint32_t reg; 6104 uint16_t j; 6105 6106 /** 6107 * Set or clear TX Queue Disable flags, 6108 * which is required by hardware. 6109 */ 6110 i40e_pre_tx_queue_cfg(hw, q_idx, on); 6111 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US); 6112 6113 /* Wait until the request is finished */ 6114 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6115 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6116 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx)); 6117 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^ 6118 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) 6119 & 0x1))) { 6120 break; 6121 } 6122 } 6123 if (on) { 6124 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 6125 return I40E_SUCCESS; /* already on, skip next steps */ 6126 6127 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0); 6128 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 6129 } else { 6130 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6131 return I40E_SUCCESS; /* already off, skip next steps */ 6132 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 6133 } 6134 /* Write the register */ 6135 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg); 6136 /* Check the result */ 6137 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6138 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6139 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx)); 6140 if (on) { 6141 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) && 6142 (reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6143 break; 6144 } else { 6145 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) && 6146 !(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6147 break; 6148 } 6149 } 6150 /* Check if it is timeout */ 6151 if (j >= I40E_CHK_Q_ENA_COUNT) { 6152 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]", 6153 (on ? "enable" : "disable"), q_idx); 6154 return I40E_ERR_TIMEOUT; 6155 } 6156 6157 return I40E_SUCCESS; 6158 } 6159 6160 /* Swith on or off the tx queues */ 6161 static int 6162 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on) 6163 { 6164 struct rte_eth_dev_data *dev_data = pf->dev_data; 6165 struct i40e_tx_queue *txq; 6166 struct rte_eth_dev *dev = pf->adapter->eth_dev; 6167 uint16_t i; 6168 int ret; 6169 6170 for (i = 0; i < dev_data->nb_tx_queues; i++) { 6171 txq = dev_data->tx_queues[i]; 6172 /* Don't operate the queue if not configured or 6173 * if starting only per queue */ 6174 if (!txq || !txq->q_set || (on && txq->tx_deferred_start)) 6175 continue; 6176 if (on) 6177 ret = i40e_dev_tx_queue_start(dev, i); 6178 else 6179 ret = i40e_dev_tx_queue_stop(dev, i); 6180 if ( ret != I40E_SUCCESS) 6181 return ret; 6182 } 6183 6184 return I40E_SUCCESS; 6185 } 6186 6187 int 6188 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) 6189 { 6190 uint32_t reg; 6191 uint16_t j; 6192 6193 /* Wait until the request is finished */ 6194 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6195 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6196 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); 6197 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^ 6198 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1)) 6199 break; 6200 } 6201 6202 if (on) { 6203 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 6204 return I40E_SUCCESS; /* Already on, skip next steps */ 6205 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 6206 } else { 6207 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6208 return I40E_SUCCESS; /* Already off, skip next steps */ 6209 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 6210 } 6211 6212 /* Write the register */ 6213 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg); 6214 /* Check the result */ 6215 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6216 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6217 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); 6218 if (on) { 6219 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) && 6220 (reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6221 break; 6222 } else { 6223 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) && 6224 !(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6225 break; 6226 } 6227 } 6228 6229 /* Check if it is timeout */ 6230 if (j >= I40E_CHK_Q_ENA_COUNT) { 6231 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]", 6232 (on ? "enable" : "disable"), q_idx); 6233 return I40E_ERR_TIMEOUT; 6234 } 6235 6236 return I40E_SUCCESS; 6237 } 6238 /* Switch on or off the rx queues */ 6239 static int 6240 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on) 6241 { 6242 struct rte_eth_dev_data *dev_data = pf->dev_data; 6243 struct i40e_rx_queue *rxq; 6244 struct rte_eth_dev *dev = pf->adapter->eth_dev; 6245 uint16_t i; 6246 int ret; 6247 6248 for (i = 0; i < dev_data->nb_rx_queues; i++) { 6249 rxq = dev_data->rx_queues[i]; 6250 /* Don't operate the queue if not configured or 6251 * if starting only per queue */ 6252 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start)) 6253 continue; 6254 if (on) 6255 ret = i40e_dev_rx_queue_start(dev, i); 6256 else 6257 ret = i40e_dev_rx_queue_stop(dev, i); 6258 if (ret != I40E_SUCCESS) 6259 return ret; 6260 } 6261 6262 return I40E_SUCCESS; 6263 } 6264 6265 /* Switch on or off all the rx/tx queues */ 6266 int 6267 i40e_dev_switch_queues(struct i40e_pf *pf, bool on) 6268 { 6269 int ret; 6270 6271 if (on) { 6272 /* enable rx queues before enabling tx queues */ 6273 ret = i40e_dev_switch_rx_queues(pf, on); 6274 if (ret) { 6275 PMD_DRV_LOG(ERR, "Failed to switch rx queues"); 6276 return ret; 6277 } 6278 ret = i40e_dev_switch_tx_queues(pf, on); 6279 } else { 6280 /* Stop tx queues before stopping rx queues */ 6281 ret = i40e_dev_switch_tx_queues(pf, on); 6282 if (ret) { 6283 PMD_DRV_LOG(ERR, "Failed to switch tx queues"); 6284 return ret; 6285 } 6286 ret = i40e_dev_switch_rx_queues(pf, on); 6287 } 6288 6289 return ret; 6290 } 6291 6292 /* Initialize VSI for TX */ 6293 static int 6294 i40e_dev_tx_init(struct i40e_pf *pf) 6295 { 6296 struct rte_eth_dev_data *data = pf->dev_data; 6297 uint16_t i; 6298 uint32_t ret = I40E_SUCCESS; 6299 struct i40e_tx_queue *txq; 6300 6301 for (i = 0; i < data->nb_tx_queues; i++) { 6302 txq = data->tx_queues[i]; 6303 if (!txq || !txq->q_set) 6304 continue; 6305 ret = i40e_tx_queue_init(txq); 6306 if (ret != I40E_SUCCESS) 6307 break; 6308 } 6309 if (ret == I40E_SUCCESS) 6310 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf) 6311 ->eth_dev); 6312 6313 return ret; 6314 } 6315 6316 /* Initialize VSI for RX */ 6317 static int 6318 i40e_dev_rx_init(struct i40e_pf *pf) 6319 { 6320 struct rte_eth_dev_data *data = pf->dev_data; 6321 int ret = I40E_SUCCESS; 6322 uint16_t i; 6323 struct i40e_rx_queue *rxq; 6324 6325 i40e_pf_config_mq_rx(pf); 6326 for (i = 0; i < data->nb_rx_queues; i++) { 6327 rxq = data->rx_queues[i]; 6328 if (!rxq || !rxq->q_set) 6329 continue; 6330 6331 ret = i40e_rx_queue_init(rxq); 6332 if (ret != I40E_SUCCESS) { 6333 PMD_DRV_LOG(ERR, 6334 "Failed to do RX queue initialization"); 6335 break; 6336 } 6337 } 6338 if (ret == I40E_SUCCESS) 6339 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf) 6340 ->eth_dev); 6341 6342 return ret; 6343 } 6344 6345 static int 6346 i40e_dev_rxtx_init(struct i40e_pf *pf) 6347 { 6348 int err; 6349 6350 err = i40e_dev_tx_init(pf); 6351 if (err) { 6352 PMD_DRV_LOG(ERR, "Failed to do TX initialization"); 6353 return err; 6354 } 6355 err = i40e_dev_rx_init(pf); 6356 if (err) { 6357 PMD_DRV_LOG(ERR, "Failed to do RX initialization"); 6358 return err; 6359 } 6360 6361 return err; 6362 } 6363 6364 static int 6365 i40e_vmdq_setup(struct rte_eth_dev *dev) 6366 { 6367 struct rte_eth_conf *conf = &dev->data->dev_conf; 6368 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6369 int i, err, conf_vsis, j, loop; 6370 struct i40e_vsi *vsi; 6371 struct i40e_vmdq_info *vmdq_info; 6372 struct rte_eth_vmdq_rx_conf *vmdq_conf; 6373 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 6374 6375 /* 6376 * Disable interrupt to avoid message from VF. Furthermore, it will 6377 * avoid race condition in VSI creation/destroy. 6378 */ 6379 i40e_pf_disable_irq0(hw); 6380 6381 if ((pf->flags & I40E_FLAG_VMDQ) == 0) { 6382 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ"); 6383 return -ENOTSUP; 6384 } 6385 6386 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools; 6387 if (conf_vsis > pf->max_nb_vmdq_vsi) { 6388 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u", 6389 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools, 6390 pf->max_nb_vmdq_vsi); 6391 return -ENOTSUP; 6392 } 6393 6394 if (pf->vmdq != NULL) { 6395 PMD_INIT_LOG(INFO, "VMDQ already configured"); 6396 return 0; 6397 } 6398 6399 pf->vmdq = rte_zmalloc("vmdq_info_struct", 6400 sizeof(*vmdq_info) * conf_vsis, 0); 6401 6402 if (pf->vmdq == NULL) { 6403 PMD_INIT_LOG(ERR, "Failed to allocate memory"); 6404 return -ENOMEM; 6405 } 6406 6407 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf; 6408 6409 /* Create VMDQ VSI */ 6410 for (i = 0; i < conf_vsis; i++) { 6411 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi, 6412 vmdq_conf->enable_loop_back); 6413 if (vsi == NULL) { 6414 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI"); 6415 err = -1; 6416 goto err_vsi_setup; 6417 } 6418 vmdq_info = &pf->vmdq[i]; 6419 vmdq_info->pf = pf; 6420 vmdq_info->vsi = vsi; 6421 } 6422 pf->nb_cfg_vmdq_vsi = conf_vsis; 6423 6424 /* Configure Vlan */ 6425 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT; 6426 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) { 6427 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) { 6428 if (vmdq_conf->pool_map[i].pools & (1UL << j)) { 6429 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u", 6430 vmdq_conf->pool_map[i].vlan_id, j); 6431 6432 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi, 6433 vmdq_conf->pool_map[i].vlan_id); 6434 if (err) { 6435 PMD_INIT_LOG(ERR, "Failed to add vlan"); 6436 err = -1; 6437 goto err_vsi_setup; 6438 } 6439 } 6440 } 6441 } 6442 6443 i40e_pf_enable_irq0(hw); 6444 6445 return 0; 6446 6447 err_vsi_setup: 6448 for (i = 0; i < conf_vsis; i++) 6449 if (pf->vmdq[i].vsi == NULL) 6450 break; 6451 else 6452 i40e_vsi_release(pf->vmdq[i].vsi); 6453 6454 rte_free(pf->vmdq); 6455 pf->vmdq = NULL; 6456 i40e_pf_enable_irq0(hw); 6457 return err; 6458 } 6459 6460 static void 6461 i40e_stat_update_32(struct i40e_hw *hw, 6462 uint32_t reg, 6463 bool offset_loaded, 6464 uint64_t *offset, 6465 uint64_t *stat) 6466 { 6467 uint64_t new_data; 6468 6469 new_data = (uint64_t)I40E_READ_REG(hw, reg); 6470 if (!offset_loaded) 6471 *offset = new_data; 6472 6473 if (new_data >= *offset) 6474 *stat = (uint64_t)(new_data - *offset); 6475 else 6476 *stat = (uint64_t)((new_data + 6477 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset); 6478 } 6479 6480 static void 6481 i40e_stat_update_48(struct i40e_hw *hw, 6482 uint32_t hireg, 6483 uint32_t loreg, 6484 bool offset_loaded, 6485 uint64_t *offset, 6486 uint64_t *stat) 6487 { 6488 uint64_t new_data; 6489 6490 new_data = (uint64_t)I40E_READ_REG(hw, loreg); 6491 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & 6492 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; 6493 6494 if (!offset_loaded) 6495 *offset = new_data; 6496 6497 if (new_data >= *offset) 6498 *stat = new_data - *offset; 6499 else 6500 *stat = (uint64_t)((new_data + 6501 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset); 6502 6503 *stat &= I40E_48_BIT_MASK; 6504 } 6505 6506 /* Disable IRQ0 */ 6507 void 6508 i40e_pf_disable_irq0(struct i40e_hw *hw) 6509 { 6510 /* Disable all interrupt types */ 6511 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 6512 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 6513 I40E_WRITE_FLUSH(hw); 6514 } 6515 6516 /* Enable IRQ0 */ 6517 void 6518 i40e_pf_enable_irq0(struct i40e_hw *hw) 6519 { 6520 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 6521 I40E_PFINT_DYN_CTL0_INTENA_MASK | 6522 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 6523 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 6524 I40E_WRITE_FLUSH(hw); 6525 } 6526 6527 static void 6528 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue) 6529 { 6530 /* read pending request and disable first */ 6531 i40e_pf_disable_irq0(hw); 6532 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK); 6533 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0, 6534 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK); 6535 6536 if (no_queue) 6537 /* Link no queues with irq0 */ 6538 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 6539 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); 6540 } 6541 6542 static void 6543 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev) 6544 { 6545 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6546 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6547 int i; 6548 uint16_t abs_vf_id; 6549 uint32_t index, offset, val; 6550 6551 if (!pf->vfs) 6552 return; 6553 /** 6554 * Try to find which VF trigger a reset, use absolute VF id to access 6555 * since the reg is global register. 6556 */ 6557 for (i = 0; i < pf->vf_num; i++) { 6558 abs_vf_id = hw->func_caps.vf_base_id + i; 6559 index = abs_vf_id / I40E_UINT32_BIT_SIZE; 6560 offset = abs_vf_id % I40E_UINT32_BIT_SIZE; 6561 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index)); 6562 /* VFR event occurred */ 6563 if (val & (0x1 << offset)) { 6564 int ret; 6565 6566 /* Clear the event first */ 6567 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index), 6568 (0x1 << offset)); 6569 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id); 6570 /** 6571 * Only notify a VF reset event occurred, 6572 * don't trigger another SW reset 6573 */ 6574 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0); 6575 if (ret != I40E_SUCCESS) 6576 PMD_DRV_LOG(ERR, "Failed to do VF reset"); 6577 } 6578 } 6579 } 6580 6581 static void 6582 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev) 6583 { 6584 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6585 int i; 6586 6587 for (i = 0; i < pf->vf_num; i++) 6588 i40e_notify_vf_link_status(dev, &pf->vfs[i]); 6589 } 6590 6591 static void 6592 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev) 6593 { 6594 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6595 struct i40e_arq_event_info info; 6596 uint16_t pending, opcode; 6597 int ret; 6598 6599 info.buf_len = I40E_AQ_BUF_SZ; 6600 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0); 6601 if (!info.msg_buf) { 6602 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 6603 return; 6604 } 6605 6606 pending = 1; 6607 while (pending) { 6608 ret = i40e_clean_arq_element(hw, &info, &pending); 6609 6610 if (ret != I40E_SUCCESS) { 6611 PMD_DRV_LOG(INFO, 6612 "Failed to read msg from AdminQ, aq_err: %u", 6613 hw->aq.asq_last_status); 6614 break; 6615 } 6616 opcode = rte_le_to_cpu_16(info.desc.opcode); 6617 6618 switch (opcode) { 6619 case i40e_aqc_opc_send_msg_to_pf: 6620 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/ 6621 i40e_pf_host_handle_vf_msg(dev, 6622 rte_le_to_cpu_16(info.desc.retval), 6623 rte_le_to_cpu_32(info.desc.cookie_high), 6624 rte_le_to_cpu_32(info.desc.cookie_low), 6625 info.msg_buf, 6626 info.msg_len); 6627 break; 6628 case i40e_aqc_opc_get_link_status: 6629 ret = i40e_dev_link_update(dev, 0); 6630 if (!ret) 6631 _rte_eth_dev_callback_process(dev, 6632 RTE_ETH_EVENT_INTR_LSC, NULL); 6633 break; 6634 default: 6635 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 6636 opcode); 6637 break; 6638 } 6639 } 6640 rte_free(info.msg_buf); 6641 } 6642 6643 /** 6644 * Interrupt handler triggered by NIC for handling 6645 * specific interrupt. 6646 * 6647 * @param handle 6648 * Pointer to interrupt handle. 6649 * @param param 6650 * The address of parameter (struct rte_eth_dev *) regsitered before. 6651 * 6652 * @return 6653 * void 6654 */ 6655 static void 6656 i40e_dev_interrupt_handler(void *param) 6657 { 6658 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 6659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6660 uint32_t icr0; 6661 6662 /* Disable interrupt */ 6663 i40e_pf_disable_irq0(hw); 6664 6665 /* read out interrupt causes */ 6666 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); 6667 6668 /* No interrupt event indicated */ 6669 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) { 6670 PMD_DRV_LOG(INFO, "No interrupt event"); 6671 goto done; 6672 } 6673 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) 6674 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); 6675 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) 6676 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); 6677 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) 6678 PMD_DRV_LOG(INFO, "ICR0: global reset requested"); 6679 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) 6680 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); 6681 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) 6682 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); 6683 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) 6684 PMD_DRV_LOG(ERR, "ICR0: HMC error"); 6685 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) 6686 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); 6687 6688 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 6689 PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); 6690 i40e_dev_handle_vfr_event(dev); 6691 } 6692 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 6693 PMD_DRV_LOG(INFO, "ICR0: adminq event"); 6694 i40e_dev_handle_aq_msg(dev); 6695 } 6696 6697 done: 6698 /* Enable interrupt */ 6699 i40e_pf_enable_irq0(hw); 6700 } 6701 6702 static void 6703 i40e_dev_alarm_handler(void *param) 6704 { 6705 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 6706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6707 uint32_t icr0; 6708 6709 /* Disable interrupt */ 6710 i40e_pf_disable_irq0(hw); 6711 6712 /* read out interrupt causes */ 6713 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); 6714 6715 /* No interrupt event indicated */ 6716 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) 6717 goto done; 6718 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) 6719 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); 6720 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) 6721 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); 6722 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) 6723 PMD_DRV_LOG(INFO, "ICR0: global reset requested"); 6724 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) 6725 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); 6726 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) 6727 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); 6728 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) 6729 PMD_DRV_LOG(ERR, "ICR0: HMC error"); 6730 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) 6731 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); 6732 6733 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 6734 PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); 6735 i40e_dev_handle_vfr_event(dev); 6736 } 6737 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 6738 PMD_DRV_LOG(INFO, "ICR0: adminq event"); 6739 i40e_dev_handle_aq_msg(dev); 6740 } 6741 6742 done: 6743 /* Enable interrupt */ 6744 i40e_pf_enable_irq0(hw); 6745 rte_eal_alarm_set(I40E_ALARM_INTERVAL, 6746 i40e_dev_alarm_handler, dev); 6747 } 6748 6749 int 6750 i40e_add_macvlan_filters(struct i40e_vsi *vsi, 6751 struct i40e_macvlan_filter *filter, 6752 int total) 6753 { 6754 int ele_num, ele_buff_size; 6755 int num, actual_num, i; 6756 uint16_t flags; 6757 int ret = I40E_SUCCESS; 6758 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6759 struct i40e_aqc_add_macvlan_element_data *req_list; 6760 6761 if (filter == NULL || total == 0) 6762 return I40E_ERR_PARAM; 6763 ele_num = hw->aq.asq_buf_size / sizeof(*req_list); 6764 ele_buff_size = hw->aq.asq_buf_size; 6765 6766 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0); 6767 if (req_list == NULL) { 6768 PMD_DRV_LOG(ERR, "Fail to allocate memory"); 6769 return I40E_ERR_NO_MEMORY; 6770 } 6771 6772 num = 0; 6773 do { 6774 actual_num = (num + ele_num > total) ? (total - num) : ele_num; 6775 memset(req_list, 0, ele_buff_size); 6776 6777 for (i = 0; i < actual_num; i++) { 6778 rte_memcpy(req_list[i].mac_addr, 6779 &filter[num + i].macaddr, ETH_ADDR_LEN); 6780 req_list[i].vlan_tag = 6781 rte_cpu_to_le_16(filter[num + i].vlan_id); 6782 6783 switch (filter[num + i].filter_type) { 6784 case RTE_MAC_PERFECT_MATCH: 6785 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH | 6786 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 6787 break; 6788 case RTE_MACVLAN_PERFECT_MATCH: 6789 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 6790 break; 6791 case RTE_MAC_HASH_MATCH: 6792 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH | 6793 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 6794 break; 6795 case RTE_MACVLAN_HASH_MATCH: 6796 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH; 6797 break; 6798 default: 6799 PMD_DRV_LOG(ERR, "Invalid MAC match type"); 6800 ret = I40E_ERR_PARAM; 6801 goto DONE; 6802 } 6803 6804 req_list[i].queue_number = 0; 6805 6806 req_list[i].flags = rte_cpu_to_le_16(flags); 6807 } 6808 6809 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list, 6810 actual_num, NULL); 6811 if (ret != I40E_SUCCESS) { 6812 PMD_DRV_LOG(ERR, "Failed to add macvlan filter"); 6813 goto DONE; 6814 } 6815 num += actual_num; 6816 } while (num < total); 6817 6818 DONE: 6819 rte_free(req_list); 6820 return ret; 6821 } 6822 6823 int 6824 i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 6825 struct i40e_macvlan_filter *filter, 6826 int total) 6827 { 6828 int ele_num, ele_buff_size; 6829 int num, actual_num, i; 6830 uint16_t flags; 6831 int ret = I40E_SUCCESS; 6832 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6833 struct i40e_aqc_remove_macvlan_element_data *req_list; 6834 6835 if (filter == NULL || total == 0) 6836 return I40E_ERR_PARAM; 6837 6838 ele_num = hw->aq.asq_buf_size / sizeof(*req_list); 6839 ele_buff_size = hw->aq.asq_buf_size; 6840 6841 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0); 6842 if (req_list == NULL) { 6843 PMD_DRV_LOG(ERR, "Fail to allocate memory"); 6844 return I40E_ERR_NO_MEMORY; 6845 } 6846 6847 num = 0; 6848 do { 6849 actual_num = (num + ele_num > total) ? (total - num) : ele_num; 6850 memset(req_list, 0, ele_buff_size); 6851 6852 for (i = 0; i < actual_num; i++) { 6853 rte_memcpy(req_list[i].mac_addr, 6854 &filter[num + i].macaddr, ETH_ADDR_LEN); 6855 req_list[i].vlan_tag = 6856 rte_cpu_to_le_16(filter[num + i].vlan_id); 6857 6858 switch (filter[num + i].filter_type) { 6859 case RTE_MAC_PERFECT_MATCH: 6860 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 6861 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 6862 break; 6863 case RTE_MACVLAN_PERFECT_MATCH: 6864 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 6865 break; 6866 case RTE_MAC_HASH_MATCH: 6867 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH | 6868 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 6869 break; 6870 case RTE_MACVLAN_HASH_MATCH: 6871 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH; 6872 break; 6873 default: 6874 PMD_DRV_LOG(ERR, "Invalid MAC filter type"); 6875 ret = I40E_ERR_PARAM; 6876 goto DONE; 6877 } 6878 req_list[i].flags = rte_cpu_to_le_16(flags); 6879 } 6880 6881 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list, 6882 actual_num, NULL); 6883 if (ret != I40E_SUCCESS) { 6884 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter"); 6885 goto DONE; 6886 } 6887 num += actual_num; 6888 } while (num < total); 6889 6890 DONE: 6891 rte_free(req_list); 6892 return ret; 6893 } 6894 6895 /* Find out specific MAC filter */ 6896 static struct i40e_mac_filter * 6897 i40e_find_mac_filter(struct i40e_vsi *vsi, 6898 struct rte_ether_addr *macaddr) 6899 { 6900 struct i40e_mac_filter *f; 6901 6902 TAILQ_FOREACH(f, &vsi->mac_list, next) { 6903 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 6904 return f; 6905 } 6906 6907 return NULL; 6908 } 6909 6910 static bool 6911 i40e_find_vlan_filter(struct i40e_vsi *vsi, 6912 uint16_t vlan_id) 6913 { 6914 uint32_t vid_idx, vid_bit; 6915 6916 if (vlan_id > ETH_VLAN_ID_MAX) 6917 return 0; 6918 6919 vid_idx = I40E_VFTA_IDX(vlan_id); 6920 vid_bit = I40E_VFTA_BIT(vlan_id); 6921 6922 if (vsi->vfta[vid_idx] & vid_bit) 6923 return 1; 6924 else 6925 return 0; 6926 } 6927 6928 static void 6929 i40e_store_vlan_filter(struct i40e_vsi *vsi, 6930 uint16_t vlan_id, bool on) 6931 { 6932 uint32_t vid_idx, vid_bit; 6933 6934 vid_idx = I40E_VFTA_IDX(vlan_id); 6935 vid_bit = I40E_VFTA_BIT(vlan_id); 6936 6937 if (on) 6938 vsi->vfta[vid_idx] |= vid_bit; 6939 else 6940 vsi->vfta[vid_idx] &= ~vid_bit; 6941 } 6942 6943 void 6944 i40e_set_vlan_filter(struct i40e_vsi *vsi, 6945 uint16_t vlan_id, bool on) 6946 { 6947 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6948 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0}; 6949 int ret; 6950 6951 if (vlan_id > ETH_VLAN_ID_MAX) 6952 return; 6953 6954 i40e_store_vlan_filter(vsi, vlan_id, on); 6955 6956 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id) 6957 return; 6958 6959 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id); 6960 6961 if (on) { 6962 ret = i40e_aq_add_vlan(hw, vsi->seid, 6963 &vlan_data, 1, NULL); 6964 if (ret != I40E_SUCCESS) 6965 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 6966 } else { 6967 ret = i40e_aq_remove_vlan(hw, vsi->seid, 6968 &vlan_data, 1, NULL); 6969 if (ret != I40E_SUCCESS) 6970 PMD_DRV_LOG(ERR, 6971 "Failed to remove vlan filter"); 6972 } 6973 } 6974 6975 /** 6976 * Find all vlan options for specific mac addr, 6977 * return with actual vlan found. 6978 */ 6979 int 6980 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 6981 struct i40e_macvlan_filter *mv_f, 6982 int num, struct rte_ether_addr *addr) 6983 { 6984 int i; 6985 uint32_t j, k; 6986 6987 /** 6988 * Not to use i40e_find_vlan_filter to decrease the loop time, 6989 * although the code looks complex. 6990 */ 6991 if (num < vsi->vlan_num) 6992 return I40E_ERR_PARAM; 6993 6994 i = 0; 6995 for (j = 0; j < I40E_VFTA_SIZE; j++) { 6996 if (vsi->vfta[j]) { 6997 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) { 6998 if (vsi->vfta[j] & (1 << k)) { 6999 if (i > num - 1) { 7000 PMD_DRV_LOG(ERR, 7001 "vlan number doesn't match"); 7002 return I40E_ERR_PARAM; 7003 } 7004 rte_memcpy(&mv_f[i].macaddr, 7005 addr, ETH_ADDR_LEN); 7006 mv_f[i].vlan_id = 7007 j * I40E_UINT32_BIT_SIZE + k; 7008 i++; 7009 } 7010 } 7011 } 7012 } 7013 return I40E_SUCCESS; 7014 } 7015 7016 static inline int 7017 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi, 7018 struct i40e_macvlan_filter *mv_f, 7019 int num, 7020 uint16_t vlan) 7021 { 7022 int i = 0; 7023 struct i40e_mac_filter *f; 7024 7025 if (num < vsi->mac_num) 7026 return I40E_ERR_PARAM; 7027 7028 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7029 if (i > num - 1) { 7030 PMD_DRV_LOG(ERR, "buffer number not match"); 7031 return I40E_ERR_PARAM; 7032 } 7033 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr, 7034 ETH_ADDR_LEN); 7035 mv_f[i].vlan_id = vlan; 7036 mv_f[i].filter_type = f->mac_info.filter_type; 7037 i++; 7038 } 7039 7040 return I40E_SUCCESS; 7041 } 7042 7043 static int 7044 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi) 7045 { 7046 int i, j, num; 7047 struct i40e_mac_filter *f; 7048 struct i40e_macvlan_filter *mv_f; 7049 int ret = I40E_SUCCESS; 7050 7051 if (vsi == NULL || vsi->mac_num == 0) 7052 return I40E_ERR_PARAM; 7053 7054 /* Case that no vlan is set */ 7055 if (vsi->vlan_num == 0) 7056 num = vsi->mac_num; 7057 else 7058 num = vsi->mac_num * vsi->vlan_num; 7059 7060 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0); 7061 if (mv_f == NULL) { 7062 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7063 return I40E_ERR_NO_MEMORY; 7064 } 7065 7066 i = 0; 7067 if (vsi->vlan_num == 0) { 7068 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7069 rte_memcpy(&mv_f[i].macaddr, 7070 &f->mac_info.mac_addr, ETH_ADDR_LEN); 7071 mv_f[i].filter_type = f->mac_info.filter_type; 7072 mv_f[i].vlan_id = 0; 7073 i++; 7074 } 7075 } else { 7076 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7077 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i], 7078 vsi->vlan_num, &f->mac_info.mac_addr); 7079 if (ret != I40E_SUCCESS) 7080 goto DONE; 7081 for (j = i; j < i + vsi->vlan_num; j++) 7082 mv_f[j].filter_type = f->mac_info.filter_type; 7083 i += vsi->vlan_num; 7084 } 7085 } 7086 7087 ret = i40e_remove_macvlan_filters(vsi, mv_f, num); 7088 DONE: 7089 rte_free(mv_f); 7090 7091 return ret; 7092 } 7093 7094 int 7095 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan) 7096 { 7097 struct i40e_macvlan_filter *mv_f; 7098 int mac_num; 7099 int ret = I40E_SUCCESS; 7100 7101 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID) 7102 return I40E_ERR_PARAM; 7103 7104 /* If it's already set, just return */ 7105 if (i40e_find_vlan_filter(vsi,vlan)) 7106 return I40E_SUCCESS; 7107 7108 mac_num = vsi->mac_num; 7109 7110 if (mac_num == 0) { 7111 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr"); 7112 return I40E_ERR_PARAM; 7113 } 7114 7115 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0); 7116 7117 if (mv_f == NULL) { 7118 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7119 return I40E_ERR_NO_MEMORY; 7120 } 7121 7122 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan); 7123 7124 if (ret != I40E_SUCCESS) 7125 goto DONE; 7126 7127 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num); 7128 7129 if (ret != I40E_SUCCESS) 7130 goto DONE; 7131 7132 i40e_set_vlan_filter(vsi, vlan, 1); 7133 7134 vsi->vlan_num++; 7135 ret = I40E_SUCCESS; 7136 DONE: 7137 rte_free(mv_f); 7138 return ret; 7139 } 7140 7141 int 7142 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan) 7143 { 7144 struct i40e_macvlan_filter *mv_f; 7145 int mac_num; 7146 int ret = I40E_SUCCESS; 7147 7148 /** 7149 * Vlan 0 is the generic filter for untagged packets 7150 * and can't be removed. 7151 */ 7152 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID) 7153 return I40E_ERR_PARAM; 7154 7155 /* If can't find it, just return */ 7156 if (!i40e_find_vlan_filter(vsi, vlan)) 7157 return I40E_ERR_PARAM; 7158 7159 mac_num = vsi->mac_num; 7160 7161 if (mac_num == 0) { 7162 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr"); 7163 return I40E_ERR_PARAM; 7164 } 7165 7166 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0); 7167 7168 if (mv_f == NULL) { 7169 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7170 return I40E_ERR_NO_MEMORY; 7171 } 7172 7173 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan); 7174 7175 if (ret != I40E_SUCCESS) 7176 goto DONE; 7177 7178 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num); 7179 7180 if (ret != I40E_SUCCESS) 7181 goto DONE; 7182 7183 /* This is last vlan to remove, replace all mac filter with vlan 0 */ 7184 if (vsi->vlan_num == 1) { 7185 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0); 7186 if (ret != I40E_SUCCESS) 7187 goto DONE; 7188 7189 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num); 7190 if (ret != I40E_SUCCESS) 7191 goto DONE; 7192 } 7193 7194 i40e_set_vlan_filter(vsi, vlan, 0); 7195 7196 vsi->vlan_num--; 7197 ret = I40E_SUCCESS; 7198 DONE: 7199 rte_free(mv_f); 7200 return ret; 7201 } 7202 7203 int 7204 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter) 7205 { 7206 struct i40e_mac_filter *f; 7207 struct i40e_macvlan_filter *mv_f; 7208 int i, vlan_num = 0; 7209 int ret = I40E_SUCCESS; 7210 7211 /* If it's add and we've config it, return */ 7212 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr); 7213 if (f != NULL) 7214 return I40E_SUCCESS; 7215 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) || 7216 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) { 7217 7218 /** 7219 * If vlan_num is 0, that's the first time to add mac, 7220 * set mask for vlan_id 0. 7221 */ 7222 if (vsi->vlan_num == 0) { 7223 i40e_set_vlan_filter(vsi, 0, 1); 7224 vsi->vlan_num = 1; 7225 } 7226 vlan_num = vsi->vlan_num; 7227 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) || 7228 (mac_filter->filter_type == RTE_MAC_HASH_MATCH)) 7229 vlan_num = 1; 7230 7231 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0); 7232 if (mv_f == NULL) { 7233 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7234 return I40E_ERR_NO_MEMORY; 7235 } 7236 7237 for (i = 0; i < vlan_num; i++) { 7238 mv_f[i].filter_type = mac_filter->filter_type; 7239 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr, 7240 ETH_ADDR_LEN); 7241 } 7242 7243 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH || 7244 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) { 7245 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, 7246 &mac_filter->mac_addr); 7247 if (ret != I40E_SUCCESS) 7248 goto DONE; 7249 } 7250 7251 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num); 7252 if (ret != I40E_SUCCESS) 7253 goto DONE; 7254 7255 /* Add the mac addr into mac list */ 7256 f = rte_zmalloc("macv_filter", sizeof(*f), 0); 7257 if (f == NULL) { 7258 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7259 ret = I40E_ERR_NO_MEMORY; 7260 goto DONE; 7261 } 7262 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr, 7263 ETH_ADDR_LEN); 7264 f->mac_info.filter_type = mac_filter->filter_type; 7265 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 7266 vsi->mac_num++; 7267 7268 ret = I40E_SUCCESS; 7269 DONE: 7270 rte_free(mv_f); 7271 7272 return ret; 7273 } 7274 7275 int 7276 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr) 7277 { 7278 struct i40e_mac_filter *f; 7279 struct i40e_macvlan_filter *mv_f; 7280 int i, vlan_num; 7281 enum rte_mac_filter_type filter_type; 7282 int ret = I40E_SUCCESS; 7283 7284 /* Can't find it, return an error */ 7285 f = i40e_find_mac_filter(vsi, addr); 7286 if (f == NULL) 7287 return I40E_ERR_PARAM; 7288 7289 vlan_num = vsi->vlan_num; 7290 filter_type = f->mac_info.filter_type; 7291 if (filter_type == RTE_MACVLAN_PERFECT_MATCH || 7292 filter_type == RTE_MACVLAN_HASH_MATCH) { 7293 if (vlan_num == 0) { 7294 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0"); 7295 return I40E_ERR_PARAM; 7296 } 7297 } else if (filter_type == RTE_MAC_PERFECT_MATCH || 7298 filter_type == RTE_MAC_HASH_MATCH) 7299 vlan_num = 1; 7300 7301 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0); 7302 if (mv_f == NULL) { 7303 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7304 return I40E_ERR_NO_MEMORY; 7305 } 7306 7307 for (i = 0; i < vlan_num; i++) { 7308 mv_f[i].filter_type = filter_type; 7309 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr, 7310 ETH_ADDR_LEN); 7311 } 7312 if (filter_type == RTE_MACVLAN_PERFECT_MATCH || 7313 filter_type == RTE_MACVLAN_HASH_MATCH) { 7314 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr); 7315 if (ret != I40E_SUCCESS) 7316 goto DONE; 7317 } 7318 7319 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num); 7320 if (ret != I40E_SUCCESS) 7321 goto DONE; 7322 7323 /* Remove the mac addr into mac list */ 7324 TAILQ_REMOVE(&vsi->mac_list, f, next); 7325 rte_free(f); 7326 vsi->mac_num--; 7327 7328 ret = I40E_SUCCESS; 7329 DONE: 7330 rte_free(mv_f); 7331 return ret; 7332 } 7333 7334 /* Configure hash enable flags for RSS */ 7335 uint64_t 7336 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags) 7337 { 7338 uint64_t hena = 0; 7339 int i; 7340 7341 if (!flags) 7342 return hena; 7343 7344 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) { 7345 if (flags & (1ULL << i)) 7346 hena |= adapter->pctypes_tbl[i]; 7347 } 7348 7349 return hena; 7350 } 7351 7352 /* Parse the hash enable flags */ 7353 uint64_t 7354 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags) 7355 { 7356 uint64_t rss_hf = 0; 7357 7358 if (!flags) 7359 return rss_hf; 7360 int i; 7361 7362 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) { 7363 if (flags & adapter->pctypes_tbl[i]) 7364 rss_hf |= (1ULL << i); 7365 } 7366 return rss_hf; 7367 } 7368 7369 /* Disable RSS */ 7370 static void 7371 i40e_pf_disable_rss(struct i40e_pf *pf) 7372 { 7373 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7374 7375 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); 7376 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); 7377 I40E_WRITE_FLUSH(hw); 7378 } 7379 7380 int 7381 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len) 7382 { 7383 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 7384 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7385 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ? 7386 I40E_VFQF_HKEY_MAX_INDEX : 7387 I40E_PFQF_HKEY_MAX_INDEX; 7388 int ret = 0; 7389 7390 if (!key || key_len == 0) { 7391 PMD_DRV_LOG(DEBUG, "No key to be configured"); 7392 return 0; 7393 } else if (key_len != (key_idx + 1) * 7394 sizeof(uint32_t)) { 7395 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 7396 return -EINVAL; 7397 } 7398 7399 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 7400 struct i40e_aqc_get_set_rss_key_data *key_dw = 7401 (struct i40e_aqc_get_set_rss_key_data *)key; 7402 7403 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw); 7404 if (ret) 7405 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ"); 7406 } else { 7407 uint32_t *hash_key = (uint32_t *)key; 7408 uint16_t i; 7409 7410 if (vsi->type == I40E_VSI_SRIOV) { 7411 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) 7412 I40E_WRITE_REG( 7413 hw, 7414 I40E_VFQF_HKEY1(i, vsi->user_param), 7415 hash_key[i]); 7416 7417 } else { 7418 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) 7419 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), 7420 hash_key[i]); 7421 } 7422 I40E_WRITE_FLUSH(hw); 7423 } 7424 7425 return ret; 7426 } 7427 7428 static int 7429 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len) 7430 { 7431 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 7432 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7433 uint32_t reg; 7434 int ret; 7435 7436 if (!key || !key_len) 7437 return 0; 7438 7439 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 7440 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id, 7441 (struct i40e_aqc_get_set_rss_key_data *)key); 7442 if (ret) { 7443 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ"); 7444 return ret; 7445 } 7446 } else { 7447 uint32_t *key_dw = (uint32_t *)key; 7448 uint16_t i; 7449 7450 if (vsi->type == I40E_VSI_SRIOV) { 7451 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) { 7452 reg = I40E_VFQF_HKEY1(i, vsi->user_param); 7453 key_dw[i] = i40e_read_rx_ctl(hw, reg); 7454 } 7455 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * 7456 sizeof(uint32_t); 7457 } else { 7458 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) { 7459 reg = I40E_PFQF_HKEY(i); 7460 key_dw[i] = i40e_read_rx_ctl(hw, reg); 7461 } 7462 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 7463 sizeof(uint32_t); 7464 } 7465 } 7466 return 0; 7467 } 7468 7469 static int 7470 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf) 7471 { 7472 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7473 uint64_t hena; 7474 int ret; 7475 7476 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key, 7477 rss_conf->rss_key_len); 7478 if (ret) 7479 return ret; 7480 7481 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf); 7482 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); 7483 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); 7484 I40E_WRITE_FLUSH(hw); 7485 7486 return 0; 7487 } 7488 7489 static int 7490 i40e_dev_rss_hash_update(struct rte_eth_dev *dev, 7491 struct rte_eth_rss_conf *rss_conf) 7492 { 7493 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7494 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7495 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask; 7496 uint64_t hena; 7497 7498 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); 7499 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; 7500 7501 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */ 7502 if (rss_hf != 0) /* Enable RSS */ 7503 return -EINVAL; 7504 return 0; /* Nothing to do */ 7505 } 7506 /* RSS enabled */ 7507 if (rss_hf == 0) /* Disable RSS */ 7508 return -EINVAL; 7509 7510 return i40e_hw_rss_hash_set(pf, rss_conf); 7511 } 7512 7513 static int 7514 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 7515 struct rte_eth_rss_conf *rss_conf) 7516 { 7517 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7518 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7519 uint64_t hena; 7520 int ret; 7521 7522 if (!rss_conf) 7523 return -EINVAL; 7524 7525 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key, 7526 &rss_conf->rss_key_len); 7527 if (ret) 7528 return ret; 7529 7530 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); 7531 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; 7532 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena); 7533 7534 return 0; 7535 } 7536 7537 static int 7538 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag) 7539 { 7540 switch (filter_type) { 7541 case RTE_TUNNEL_FILTER_IMAC_IVLAN: 7542 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN; 7543 break; 7544 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID: 7545 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID; 7546 break; 7547 case RTE_TUNNEL_FILTER_IMAC_TENID: 7548 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID; 7549 break; 7550 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC: 7551 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC; 7552 break; 7553 case ETH_TUNNEL_FILTER_IMAC: 7554 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC; 7555 break; 7556 case ETH_TUNNEL_FILTER_OIP: 7557 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP; 7558 break; 7559 case ETH_TUNNEL_FILTER_IIP: 7560 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP; 7561 break; 7562 default: 7563 PMD_DRV_LOG(ERR, "invalid tunnel filter type"); 7564 return -EINVAL; 7565 } 7566 7567 return 0; 7568 } 7569 7570 /* Convert tunnel filter structure */ 7571 static int 7572 i40e_tunnel_filter_convert( 7573 struct i40e_aqc_cloud_filters_element_bb *cld_filter, 7574 struct i40e_tunnel_filter *tunnel_filter) 7575 { 7576 rte_ether_addr_copy((struct rte_ether_addr *) 7577 &cld_filter->element.outer_mac, 7578 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac); 7579 rte_ether_addr_copy((struct rte_ether_addr *) 7580 &cld_filter->element.inner_mac, 7581 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac); 7582 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan; 7583 if ((rte_le_to_cpu_16(cld_filter->element.flags) & 7584 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) == 7585 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) 7586 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6; 7587 else 7588 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4; 7589 tunnel_filter->input.flags = cld_filter->element.flags; 7590 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id; 7591 tunnel_filter->queue = cld_filter->element.queue_number; 7592 rte_memcpy(tunnel_filter->input.general_fields, 7593 cld_filter->general_fields, 7594 sizeof(cld_filter->general_fields)); 7595 7596 return 0; 7597 } 7598 7599 /* Check if there exists the tunnel filter */ 7600 struct i40e_tunnel_filter * 7601 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 7602 const struct i40e_tunnel_filter_input *input) 7603 { 7604 int ret; 7605 7606 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input); 7607 if (ret < 0) 7608 return NULL; 7609 7610 return tunnel_rule->hash_map[ret]; 7611 } 7612 7613 /* Add a tunnel filter into the SW list */ 7614 static int 7615 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, 7616 struct i40e_tunnel_filter *tunnel_filter) 7617 { 7618 struct i40e_tunnel_rule *rule = &pf->tunnel; 7619 int ret; 7620 7621 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input); 7622 if (ret < 0) { 7623 PMD_DRV_LOG(ERR, 7624 "Failed to insert tunnel filter to hash table %d!", 7625 ret); 7626 return ret; 7627 } 7628 rule->hash_map[ret] = tunnel_filter; 7629 7630 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules); 7631 7632 return 0; 7633 } 7634 7635 /* Delete a tunnel filter from the SW list */ 7636 int 7637 i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 7638 struct i40e_tunnel_filter_input *input) 7639 { 7640 struct i40e_tunnel_rule *rule = &pf->tunnel; 7641 struct i40e_tunnel_filter *tunnel_filter; 7642 int ret; 7643 7644 ret = rte_hash_del_key(rule->hash_table, input); 7645 if (ret < 0) { 7646 PMD_DRV_LOG(ERR, 7647 "Failed to delete tunnel filter to hash table %d!", 7648 ret); 7649 return ret; 7650 } 7651 tunnel_filter = rule->hash_map[ret]; 7652 rule->hash_map[ret] = NULL; 7653 7654 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules); 7655 rte_free(tunnel_filter); 7656 7657 return 0; 7658 } 7659 7660 int 7661 i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 7662 struct rte_eth_tunnel_filter_conf *tunnel_filter, 7663 uint8_t add) 7664 { 7665 uint16_t ip_type; 7666 uint32_t ipv4_addr, ipv4_addr_le; 7667 uint8_t i, tun_type = 0; 7668 /* internal varialbe to convert ipv6 byte order */ 7669 uint32_t convert_ipv6[4]; 7670 int val, ret = 0; 7671 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7672 struct i40e_vsi *vsi = pf->main_vsi; 7673 struct i40e_aqc_cloud_filters_element_bb *cld_filter; 7674 struct i40e_aqc_cloud_filters_element_bb *pfilter; 7675 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 7676 struct i40e_tunnel_filter *tunnel, *node; 7677 struct i40e_tunnel_filter check_filter; /* Check if filter exists */ 7678 7679 cld_filter = rte_zmalloc("tunnel_filter", 7680 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), 7681 0); 7682 7683 if (NULL == cld_filter) { 7684 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 7685 return -ENOMEM; 7686 } 7687 pfilter = cld_filter; 7688 7689 rte_ether_addr_copy(&tunnel_filter->outer_mac, 7690 (struct rte_ether_addr *)&pfilter->element.outer_mac); 7691 rte_ether_addr_copy(&tunnel_filter->inner_mac, 7692 (struct rte_ether_addr *)&pfilter->element.inner_mac); 7693 7694 pfilter->element.inner_vlan = 7695 rte_cpu_to_le_16(tunnel_filter->inner_vlan); 7696 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) { 7697 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4; 7698 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr); 7699 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr); 7700 rte_memcpy(&pfilter->element.ipaddr.v4.data, 7701 &ipv4_addr_le, 7702 sizeof(pfilter->element.ipaddr.v4.data)); 7703 } else { 7704 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6; 7705 for (i = 0; i < 4; i++) { 7706 convert_ipv6[i] = 7707 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i])); 7708 } 7709 rte_memcpy(&pfilter->element.ipaddr.v6.data, 7710 &convert_ipv6, 7711 sizeof(pfilter->element.ipaddr.v6.data)); 7712 } 7713 7714 /* check tunneled type */ 7715 switch (tunnel_filter->tunnel_type) { 7716 case RTE_TUNNEL_TYPE_VXLAN: 7717 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN; 7718 break; 7719 case RTE_TUNNEL_TYPE_NVGRE: 7720 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC; 7721 break; 7722 case RTE_TUNNEL_TYPE_IP_IN_GRE: 7723 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; 7724 break; 7725 case RTE_TUNNEL_TYPE_VXLAN_GPE: 7726 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE; 7727 break; 7728 default: 7729 /* Other tunnel types is not supported. */ 7730 PMD_DRV_LOG(ERR, "tunnel type is not supported."); 7731 rte_free(cld_filter); 7732 return -EINVAL; 7733 } 7734 7735 val = i40e_dev_get_filter_type(tunnel_filter->filter_type, 7736 &pfilter->element.flags); 7737 if (val < 0) { 7738 rte_free(cld_filter); 7739 return -EINVAL; 7740 } 7741 7742 pfilter->element.flags |= rte_cpu_to_le_16( 7743 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | 7744 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)); 7745 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id); 7746 pfilter->element.queue_number = 7747 rte_cpu_to_le_16(tunnel_filter->queue_id); 7748 7749 /* Check if there is the filter in SW list */ 7750 memset(&check_filter, 0, sizeof(check_filter)); 7751 i40e_tunnel_filter_convert(cld_filter, &check_filter); 7752 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input); 7753 if (add && node) { 7754 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!"); 7755 rte_free(cld_filter); 7756 return -EINVAL; 7757 } 7758 7759 if (!add && !node) { 7760 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!"); 7761 rte_free(cld_filter); 7762 return -EINVAL; 7763 } 7764 7765 if (add) { 7766 ret = i40e_aq_add_cloud_filters(hw, 7767 vsi->seid, &cld_filter->element, 1); 7768 if (ret < 0) { 7769 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter."); 7770 rte_free(cld_filter); 7771 return -ENOTSUP; 7772 } 7773 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0); 7774 if (tunnel == NULL) { 7775 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 7776 rte_free(cld_filter); 7777 return -ENOMEM; 7778 } 7779 7780 rte_memcpy(tunnel, &check_filter, sizeof(check_filter)); 7781 ret = i40e_sw_tunnel_filter_insert(pf, tunnel); 7782 if (ret < 0) 7783 rte_free(tunnel); 7784 } else { 7785 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 7786 &cld_filter->element, 1); 7787 if (ret < 0) { 7788 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter."); 7789 rte_free(cld_filter); 7790 return -ENOTSUP; 7791 } 7792 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 7793 } 7794 7795 rte_free(cld_filter); 7796 return ret; 7797 } 7798 7799 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48 7800 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4 7801 #define I40E_TR_GENEVE_KEY_MASK 0x8 7802 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40 7803 #define I40E_TR_GRE_KEY_MASK 0x400 7804 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800 7805 #define I40E_TR_GRE_NO_KEY_MASK 0x8000 7806 7807 static enum 7808 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf) 7809 { 7810 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7811 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7812 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7813 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7814 enum i40e_status_code status = I40E_SUCCESS; 7815 7816 if (pf->support_multi_driver) { 7817 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported."); 7818 return I40E_NOT_SUPPORTED; 7819 } 7820 7821 memset(&filter_replace, 0, 7822 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7823 memset(&filter_replace_buf, 0, 7824 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7825 7826 /* create L1 filter */ 7827 filter_replace.old_filter_type = 7828 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; 7829 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11; 7830 filter_replace.tr_bit = 0; 7831 7832 /* Prepare the buffer, 3 entries */ 7833 filter_replace_buf.data[0] = 7834 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 7835 filter_replace_buf.data[0] |= 7836 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7837 filter_replace_buf.data[2] = 0xFF; 7838 filter_replace_buf.data[3] = 0xFF; 7839 filter_replace_buf.data[4] = 7840 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 7841 filter_replace_buf.data[4] |= 7842 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7843 filter_replace_buf.data[7] = 0xF0; 7844 filter_replace_buf.data[8] 7845 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0; 7846 filter_replace_buf.data[8] |= 7847 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7848 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK | 7849 I40E_TR_GENEVE_KEY_MASK | 7850 I40E_TR_GENERIC_UDP_TUNNEL_MASK; 7851 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK | 7852 I40E_TR_GRE_KEY_WITH_XSUM_MASK | 7853 I40E_TR_GRE_NO_KEY_MASK) >> 8; 7854 7855 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7856 &filter_replace_buf); 7857 if (!status && (filter_replace.old_filter_type != 7858 filter_replace.new_filter_type)) 7859 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 7860 " original: 0x%x, new: 0x%x", 7861 dev->device->name, 7862 filter_replace.old_filter_type, 7863 filter_replace.new_filter_type); 7864 7865 return status; 7866 } 7867 7868 static enum 7869 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) 7870 { 7871 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7872 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7873 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7874 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7875 enum i40e_status_code status = I40E_SUCCESS; 7876 7877 if (pf->support_multi_driver) { 7878 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 7879 return I40E_NOT_SUPPORTED; 7880 } 7881 7882 /* For MPLSoUDP */ 7883 memset(&filter_replace, 0, 7884 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7885 memset(&filter_replace_buf, 0, 7886 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7887 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | 7888 I40E_AQC_MIRROR_CLOUD_FILTER; 7889 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP; 7890 filter_replace.new_filter_type = 7891 I40E_AQC_ADD_CLOUD_FILTER_0X11; 7892 /* Prepare the buffer, 2 entries */ 7893 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 7894 filter_replace_buf.data[0] |= 7895 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7896 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11; 7897 filter_replace_buf.data[4] |= 7898 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7899 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7900 &filter_replace_buf); 7901 if (status < 0) 7902 return status; 7903 if (filter_replace.old_filter_type != 7904 filter_replace.new_filter_type) 7905 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 7906 " original: 0x%x, new: 0x%x", 7907 dev->device->name, 7908 filter_replace.old_filter_type, 7909 filter_replace.new_filter_type); 7910 7911 /* For MPLSoGRE */ 7912 memset(&filter_replace, 0, 7913 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7914 memset(&filter_replace_buf, 0, 7915 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7916 7917 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | 7918 I40E_AQC_MIRROR_CLOUD_FILTER; 7919 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC; 7920 filter_replace.new_filter_type = 7921 I40E_AQC_ADD_CLOUD_FILTER_0X12; 7922 /* Prepare the buffer, 2 entries */ 7923 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 7924 filter_replace_buf.data[0] |= 7925 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7926 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11; 7927 filter_replace_buf.data[4] |= 7928 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7929 7930 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7931 &filter_replace_buf); 7932 if (!status && (filter_replace.old_filter_type != 7933 filter_replace.new_filter_type)) 7934 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 7935 " original: 0x%x, new: 0x%x", 7936 dev->device->name, 7937 filter_replace.old_filter_type, 7938 filter_replace.new_filter_type); 7939 7940 return status; 7941 } 7942 7943 static enum i40e_status_code 7944 i40e_replace_gtp_l1_filter(struct i40e_pf *pf) 7945 { 7946 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7947 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7948 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7949 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7950 enum i40e_status_code status = I40E_SUCCESS; 7951 7952 if (pf->support_multi_driver) { 7953 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported."); 7954 return I40E_NOT_SUPPORTED; 7955 } 7956 7957 /* For GTP-C */ 7958 memset(&filter_replace, 0, 7959 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7960 memset(&filter_replace_buf, 0, 7961 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7962 /* create L1 filter */ 7963 filter_replace.old_filter_type = 7964 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; 7965 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12; 7966 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 | 7967 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7968 /* Prepare the buffer, 2 entries */ 7969 filter_replace_buf.data[0] = 7970 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 7971 filter_replace_buf.data[0] |= 7972 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7973 filter_replace_buf.data[2] = 0xFF; 7974 filter_replace_buf.data[3] = 0xFF; 7975 filter_replace_buf.data[4] = 7976 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 7977 filter_replace_buf.data[4] |= 7978 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7979 filter_replace_buf.data[6] = 0xFF; 7980 filter_replace_buf.data[7] = 0xFF; 7981 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7982 &filter_replace_buf); 7983 if (status < 0) 7984 return status; 7985 if (filter_replace.old_filter_type != 7986 filter_replace.new_filter_type) 7987 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 7988 " original: 0x%x, new: 0x%x", 7989 dev->device->name, 7990 filter_replace.old_filter_type, 7991 filter_replace.new_filter_type); 7992 7993 /* for GTP-U */ 7994 memset(&filter_replace, 0, 7995 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7996 memset(&filter_replace_buf, 0, 7997 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7998 /* create L1 filter */ 7999 filter_replace.old_filter_type = 8000 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY; 8001 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13; 8002 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 | 8003 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8004 /* Prepare the buffer, 2 entries */ 8005 filter_replace_buf.data[0] = 8006 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 8007 filter_replace_buf.data[0] |= 8008 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8009 filter_replace_buf.data[2] = 0xFF; 8010 filter_replace_buf.data[3] = 0xFF; 8011 filter_replace_buf.data[4] = 8012 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 8013 filter_replace_buf.data[4] |= 8014 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8015 filter_replace_buf.data[6] = 0xFF; 8016 filter_replace_buf.data[7] = 0xFF; 8017 8018 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8019 &filter_replace_buf); 8020 if (!status && (filter_replace.old_filter_type != 8021 filter_replace.new_filter_type)) 8022 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 8023 " original: 0x%x, new: 0x%x", 8024 dev->device->name, 8025 filter_replace.old_filter_type, 8026 filter_replace.new_filter_type); 8027 8028 return status; 8029 } 8030 8031 static enum 8032 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf) 8033 { 8034 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 8035 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 8036 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8037 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 8038 enum i40e_status_code status = I40E_SUCCESS; 8039 8040 if (pf->support_multi_driver) { 8041 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 8042 return I40E_NOT_SUPPORTED; 8043 } 8044 8045 /* for GTP-C */ 8046 memset(&filter_replace, 0, 8047 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8048 memset(&filter_replace_buf, 0, 8049 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8050 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 8051 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN; 8052 filter_replace.new_filter_type = 8053 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8054 /* Prepare the buffer, 2 entries */ 8055 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12; 8056 filter_replace_buf.data[0] |= 8057 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8058 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8059 filter_replace_buf.data[4] |= 8060 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8061 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8062 &filter_replace_buf); 8063 if (status < 0) 8064 return status; 8065 if (filter_replace.old_filter_type != 8066 filter_replace.new_filter_type) 8067 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8068 " original: 0x%x, new: 0x%x", 8069 dev->device->name, 8070 filter_replace.old_filter_type, 8071 filter_replace.new_filter_type); 8072 8073 /* for GTP-U */ 8074 memset(&filter_replace, 0, 8075 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8076 memset(&filter_replace_buf, 0, 8077 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8078 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 8079 filter_replace.old_filter_type = 8080 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID; 8081 filter_replace.new_filter_type = 8082 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8083 /* Prepare the buffer, 2 entries */ 8084 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13; 8085 filter_replace_buf.data[0] |= 8086 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8087 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8088 filter_replace_buf.data[4] |= 8089 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8090 8091 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8092 &filter_replace_buf); 8093 if (!status && (filter_replace.old_filter_type != 8094 filter_replace.new_filter_type)) 8095 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8096 " original: 0x%x, new: 0x%x", 8097 dev->device->name, 8098 filter_replace.old_filter_type, 8099 filter_replace.new_filter_type); 8100 8101 return status; 8102 } 8103 8104 int 8105 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 8106 struct i40e_tunnel_filter_conf *tunnel_filter, 8107 uint8_t add) 8108 { 8109 uint16_t ip_type; 8110 uint32_t ipv4_addr, ipv4_addr_le; 8111 uint8_t i, tun_type = 0; 8112 /* internal variable to convert ipv6 byte order */ 8113 uint32_t convert_ipv6[4]; 8114 int val, ret = 0; 8115 struct i40e_pf_vf *vf = NULL; 8116 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8117 struct i40e_vsi *vsi; 8118 struct i40e_aqc_cloud_filters_element_bb *cld_filter; 8119 struct i40e_aqc_cloud_filters_element_bb *pfilter; 8120 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 8121 struct i40e_tunnel_filter *tunnel, *node; 8122 struct i40e_tunnel_filter check_filter; /* Check if filter exists */ 8123 uint32_t teid_le; 8124 bool big_buffer = 0; 8125 8126 cld_filter = rte_zmalloc("tunnel_filter", 8127 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), 8128 0); 8129 8130 if (cld_filter == NULL) { 8131 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 8132 return -ENOMEM; 8133 } 8134 pfilter = cld_filter; 8135 8136 rte_ether_addr_copy(&tunnel_filter->outer_mac, 8137 (struct rte_ether_addr *)&pfilter->element.outer_mac); 8138 rte_ether_addr_copy(&tunnel_filter->inner_mac, 8139 (struct rte_ether_addr *)&pfilter->element.inner_mac); 8140 8141 pfilter->element.inner_vlan = 8142 rte_cpu_to_le_16(tunnel_filter->inner_vlan); 8143 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) { 8144 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4; 8145 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr); 8146 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr); 8147 rte_memcpy(&pfilter->element.ipaddr.v4.data, 8148 &ipv4_addr_le, 8149 sizeof(pfilter->element.ipaddr.v4.data)); 8150 } else { 8151 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6; 8152 for (i = 0; i < 4; i++) { 8153 convert_ipv6[i] = 8154 rte_cpu_to_le_32(rte_be_to_cpu_32( 8155 tunnel_filter->ip_addr.ipv6_addr[i])); 8156 } 8157 rte_memcpy(&pfilter->element.ipaddr.v6.data, 8158 &convert_ipv6, 8159 sizeof(pfilter->element.ipaddr.v6.data)); 8160 } 8161 8162 /* check tunneled type */ 8163 switch (tunnel_filter->tunnel_type) { 8164 case I40E_TUNNEL_TYPE_VXLAN: 8165 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN; 8166 break; 8167 case I40E_TUNNEL_TYPE_NVGRE: 8168 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC; 8169 break; 8170 case I40E_TUNNEL_TYPE_IP_IN_GRE: 8171 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; 8172 break; 8173 case I40E_TUNNEL_TYPE_MPLSoUDP: 8174 if (!pf->mpls_replace_flag) { 8175 i40e_replace_mpls_l1_filter(pf); 8176 i40e_replace_mpls_cloud_filter(pf); 8177 pf->mpls_replace_flag = 1; 8178 } 8179 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8180 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = 8181 teid_le >> 4; 8182 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = 8183 (teid_le & 0xF) << 12; 8184 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = 8185 0x40; 8186 big_buffer = 1; 8187 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP; 8188 break; 8189 case I40E_TUNNEL_TYPE_MPLSoGRE: 8190 if (!pf->mpls_replace_flag) { 8191 i40e_replace_mpls_l1_filter(pf); 8192 i40e_replace_mpls_cloud_filter(pf); 8193 pf->mpls_replace_flag = 1; 8194 } 8195 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8196 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = 8197 teid_le >> 4; 8198 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = 8199 (teid_le & 0xF) << 12; 8200 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = 8201 0x0; 8202 big_buffer = 1; 8203 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE; 8204 break; 8205 case I40E_TUNNEL_TYPE_GTPC: 8206 if (!pf->gtp_replace_flag) { 8207 i40e_replace_gtp_l1_filter(pf); 8208 i40e_replace_gtp_cloud_filter(pf); 8209 pf->gtp_replace_flag = 1; 8210 } 8211 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8212 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] = 8213 (teid_le >> 16) & 0xFFFF; 8214 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] = 8215 teid_le & 0xFFFF; 8216 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] = 8217 0x0; 8218 big_buffer = 1; 8219 break; 8220 case I40E_TUNNEL_TYPE_GTPU: 8221 if (!pf->gtp_replace_flag) { 8222 i40e_replace_gtp_l1_filter(pf); 8223 i40e_replace_gtp_cloud_filter(pf); 8224 pf->gtp_replace_flag = 1; 8225 } 8226 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8227 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] = 8228 (teid_le >> 16) & 0xFFFF; 8229 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] = 8230 teid_le & 0xFFFF; 8231 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] = 8232 0x0; 8233 big_buffer = 1; 8234 break; 8235 case I40E_TUNNEL_TYPE_QINQ: 8236 if (!pf->qinq_replace_flag) { 8237 ret = i40e_cloud_filter_qinq_create(pf); 8238 if (ret < 0) 8239 PMD_DRV_LOG(DEBUG, 8240 "QinQ tunnel filter already created."); 8241 pf->qinq_replace_flag = 1; 8242 } 8243 /* Add in the General fields the values of 8244 * the Outer and Inner VLAN 8245 * Big Buffer should be set, see changes in 8246 * i40e_aq_add_cloud_filters 8247 */ 8248 pfilter->general_fields[0] = tunnel_filter->inner_vlan; 8249 pfilter->general_fields[1] = tunnel_filter->outer_vlan; 8250 big_buffer = 1; 8251 break; 8252 default: 8253 /* Other tunnel types is not supported. */ 8254 PMD_DRV_LOG(ERR, "tunnel type is not supported."); 8255 rte_free(cld_filter); 8256 return -EINVAL; 8257 } 8258 8259 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP) 8260 pfilter->element.flags = 8261 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8262 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE) 8263 pfilter->element.flags = 8264 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8265 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC) 8266 pfilter->element.flags = 8267 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8268 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU) 8269 pfilter->element.flags = 8270 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8271 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ) 8272 pfilter->element.flags |= 8273 I40E_AQC_ADD_CLOUD_FILTER_0X10; 8274 else { 8275 val = i40e_dev_get_filter_type(tunnel_filter->filter_type, 8276 &pfilter->element.flags); 8277 if (val < 0) { 8278 rte_free(cld_filter); 8279 return -EINVAL; 8280 } 8281 } 8282 8283 pfilter->element.flags |= rte_cpu_to_le_16( 8284 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | 8285 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)); 8286 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8287 pfilter->element.queue_number = 8288 rte_cpu_to_le_16(tunnel_filter->queue_id); 8289 8290 if (!tunnel_filter->is_to_vf) 8291 vsi = pf->main_vsi; 8292 else { 8293 if (tunnel_filter->vf_id >= pf->vf_num) { 8294 PMD_DRV_LOG(ERR, "Invalid argument."); 8295 rte_free(cld_filter); 8296 return -EINVAL; 8297 } 8298 vf = &pf->vfs[tunnel_filter->vf_id]; 8299 vsi = vf->vsi; 8300 } 8301 8302 /* Check if there is the filter in SW list */ 8303 memset(&check_filter, 0, sizeof(check_filter)); 8304 i40e_tunnel_filter_convert(cld_filter, &check_filter); 8305 check_filter.is_to_vf = tunnel_filter->is_to_vf; 8306 check_filter.vf_id = tunnel_filter->vf_id; 8307 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input); 8308 if (add && node) { 8309 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!"); 8310 rte_free(cld_filter); 8311 return -EINVAL; 8312 } 8313 8314 if (!add && !node) { 8315 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!"); 8316 rte_free(cld_filter); 8317 return -EINVAL; 8318 } 8319 8320 if (add) { 8321 if (big_buffer) 8322 ret = i40e_aq_add_cloud_filters_bb(hw, 8323 vsi->seid, cld_filter, 1); 8324 else 8325 ret = i40e_aq_add_cloud_filters(hw, 8326 vsi->seid, &cld_filter->element, 1); 8327 if (ret < 0) { 8328 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter."); 8329 rte_free(cld_filter); 8330 return -ENOTSUP; 8331 } 8332 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0); 8333 if (tunnel == NULL) { 8334 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 8335 rte_free(cld_filter); 8336 return -ENOMEM; 8337 } 8338 8339 rte_memcpy(tunnel, &check_filter, sizeof(check_filter)); 8340 ret = i40e_sw_tunnel_filter_insert(pf, tunnel); 8341 if (ret < 0) 8342 rte_free(tunnel); 8343 } else { 8344 if (big_buffer) 8345 ret = i40e_aq_rem_cloud_filters_bb( 8346 hw, vsi->seid, cld_filter, 1); 8347 else 8348 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 8349 &cld_filter->element, 1); 8350 if (ret < 0) { 8351 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter."); 8352 rte_free(cld_filter); 8353 return -ENOTSUP; 8354 } 8355 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 8356 } 8357 8358 rte_free(cld_filter); 8359 return ret; 8360 } 8361 8362 static int 8363 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port) 8364 { 8365 uint8_t i; 8366 8367 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { 8368 if (pf->vxlan_ports[i] == port) 8369 return i; 8370 } 8371 8372 return -1; 8373 } 8374 8375 static int 8376 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type) 8377 { 8378 int idx, ret; 8379 uint8_t filter_idx; 8380 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8381 8382 idx = i40e_get_vxlan_port_idx(pf, port); 8383 8384 /* Check if port already exists */ 8385 if (idx >= 0) { 8386 PMD_DRV_LOG(ERR, "Port %d already offloaded", port); 8387 return -EINVAL; 8388 } 8389 8390 /* Now check if there is space to add the new port */ 8391 idx = i40e_get_vxlan_port_idx(pf, 0); 8392 if (idx < 0) { 8393 PMD_DRV_LOG(ERR, 8394 "Maximum number of UDP ports reached, not adding port %d", 8395 port); 8396 return -ENOSPC; 8397 } 8398 8399 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type, 8400 &filter_idx, NULL); 8401 if (ret < 0) { 8402 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port); 8403 return -1; 8404 } 8405 8406 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d", 8407 port, filter_idx); 8408 8409 /* New port: add it and mark its index in the bitmap */ 8410 pf->vxlan_ports[idx] = port; 8411 pf->vxlan_bitmap |= (1 << idx); 8412 8413 if (!(pf->flags & I40E_FLAG_VXLAN)) 8414 pf->flags |= I40E_FLAG_VXLAN; 8415 8416 return 0; 8417 } 8418 8419 static int 8420 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port) 8421 { 8422 int idx; 8423 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8424 8425 if (!(pf->flags & I40E_FLAG_VXLAN)) { 8426 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured."); 8427 return -EINVAL; 8428 } 8429 8430 idx = i40e_get_vxlan_port_idx(pf, port); 8431 8432 if (idx < 0) { 8433 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port); 8434 return -EINVAL; 8435 } 8436 8437 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) { 8438 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port); 8439 return -1; 8440 } 8441 8442 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d", 8443 port, idx); 8444 8445 pf->vxlan_ports[idx] = 0; 8446 pf->vxlan_bitmap &= ~(1 << idx); 8447 8448 if (!pf->vxlan_bitmap) 8449 pf->flags &= ~I40E_FLAG_VXLAN; 8450 8451 return 0; 8452 } 8453 8454 /* Add UDP tunneling port */ 8455 static int 8456 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8457 struct rte_eth_udp_tunnel *udp_tunnel) 8458 { 8459 int ret = 0; 8460 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8461 8462 if (udp_tunnel == NULL) 8463 return -EINVAL; 8464 8465 switch (udp_tunnel->prot_type) { 8466 case RTE_TUNNEL_TYPE_VXLAN: 8467 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port, 8468 I40E_AQC_TUNNEL_TYPE_VXLAN); 8469 break; 8470 case RTE_TUNNEL_TYPE_VXLAN_GPE: 8471 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port, 8472 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE); 8473 break; 8474 case RTE_TUNNEL_TYPE_GENEVE: 8475 case RTE_TUNNEL_TYPE_TEREDO: 8476 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8477 ret = -1; 8478 break; 8479 8480 default: 8481 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8482 ret = -1; 8483 break; 8484 } 8485 8486 return ret; 8487 } 8488 8489 /* Remove UDP tunneling port */ 8490 static int 8491 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8492 struct rte_eth_udp_tunnel *udp_tunnel) 8493 { 8494 int ret = 0; 8495 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8496 8497 if (udp_tunnel == NULL) 8498 return -EINVAL; 8499 8500 switch (udp_tunnel->prot_type) { 8501 case RTE_TUNNEL_TYPE_VXLAN: 8502 case RTE_TUNNEL_TYPE_VXLAN_GPE: 8503 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port); 8504 break; 8505 case RTE_TUNNEL_TYPE_GENEVE: 8506 case RTE_TUNNEL_TYPE_TEREDO: 8507 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8508 ret = -1; 8509 break; 8510 default: 8511 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8512 ret = -1; 8513 break; 8514 } 8515 8516 return ret; 8517 } 8518 8519 /* Calculate the maximum number of contiguous PF queues that are configured */ 8520 static int 8521 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf) 8522 { 8523 struct rte_eth_dev_data *data = pf->dev_data; 8524 int i, num; 8525 struct i40e_rx_queue *rxq; 8526 8527 num = 0; 8528 for (i = 0; i < pf->lan_nb_qps; i++) { 8529 rxq = data->rx_queues[i]; 8530 if (rxq && rxq->q_set) 8531 num++; 8532 else 8533 break; 8534 } 8535 8536 return num; 8537 } 8538 8539 /* Configure RSS */ 8540 static int 8541 i40e_pf_config_rss(struct i40e_pf *pf) 8542 { 8543 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8544 struct rte_eth_rss_conf rss_conf; 8545 uint32_t i, lut = 0; 8546 uint16_t j, num; 8547 8548 /* 8549 * If both VMDQ and RSS enabled, not all of PF queues are configured. 8550 * It's necessary to calculate the actual PF queues that are configured. 8551 */ 8552 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 8553 num = i40e_pf_calc_configured_queues_num(pf); 8554 else 8555 num = pf->dev_data->nb_rx_queues; 8556 8557 num = RTE_MIN(num, I40E_MAX_Q_PER_TC); 8558 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured", 8559 num); 8560 8561 if (num == 0) { 8562 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS"); 8563 return -ENOTSUP; 8564 } 8565 8566 if (pf->adapter->rss_reta_updated == 0) { 8567 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 8568 if (j == num) 8569 j = 0; 8570 lut = (lut << 8) | (j & ((0x1 << 8571 hw->func_caps.rss_table_entry_width) - 1)); 8572 if ((i & 3) == 3) 8573 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), 8574 rte_bswap32(lut)); 8575 } 8576 } 8577 8578 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf; 8579 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) { 8580 i40e_pf_disable_rss(pf); 8581 return 0; 8582 } 8583 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < 8584 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 8585 /* Random default keys */ 8586 static uint32_t rss_key_default[] = {0x6b793944, 8587 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8, 8588 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605, 8589 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581}; 8590 8591 rss_conf.rss_key = (uint8_t *)rss_key_default; 8592 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 8593 sizeof(uint32_t); 8594 } 8595 8596 return i40e_hw_rss_hash_set(pf, &rss_conf); 8597 } 8598 8599 static int 8600 i40e_tunnel_filter_param_check(struct i40e_pf *pf, 8601 struct rte_eth_tunnel_filter_conf *filter) 8602 { 8603 if (pf == NULL || filter == NULL) { 8604 PMD_DRV_LOG(ERR, "Invalid parameter"); 8605 return -EINVAL; 8606 } 8607 8608 if (filter->queue_id >= pf->dev_data->nb_rx_queues) { 8609 PMD_DRV_LOG(ERR, "Invalid queue ID"); 8610 return -EINVAL; 8611 } 8612 8613 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) { 8614 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID"); 8615 return -EINVAL; 8616 } 8617 8618 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) && 8619 (rte_is_zero_ether_addr(&filter->outer_mac))) { 8620 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address"); 8621 return -EINVAL; 8622 } 8623 8624 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) && 8625 (rte_is_zero_ether_addr(&filter->inner_mac))) { 8626 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address"); 8627 return -EINVAL; 8628 } 8629 8630 return 0; 8631 } 8632 8633 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000 8634 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) 8635 static int 8636 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) 8637 { 8638 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 8639 uint32_t val, reg; 8640 int ret = -EINVAL; 8641 8642 if (pf->support_multi_driver) { 8643 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported"); 8644 return -ENOTSUP; 8645 } 8646 8647 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)); 8648 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val); 8649 8650 if (len == 3) { 8651 reg = val | I40E_GL_PRS_FVBM_MSK_ENA; 8652 } else if (len == 4) { 8653 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA; 8654 } else { 8655 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len); 8656 return ret; 8657 } 8658 8659 if (reg != val) { 8660 ret = i40e_aq_debug_write_global_register(hw, 8661 I40E_GL_PRS_FVBM(2), 8662 reg, NULL); 8663 if (ret != 0) 8664 return ret; 8665 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed " 8666 "with value 0x%08x", 8667 I40E_GL_PRS_FVBM(2), reg); 8668 } else { 8669 ret = 0; 8670 } 8671 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x", 8672 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2))); 8673 8674 return ret; 8675 } 8676 8677 static int 8678 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg) 8679 { 8680 int ret = -EINVAL; 8681 8682 if (!hw || !cfg) 8683 return -EINVAL; 8684 8685 switch (cfg->cfg_type) { 8686 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN: 8687 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len); 8688 break; 8689 default: 8690 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type); 8691 break; 8692 } 8693 8694 return ret; 8695 } 8696 8697 static int 8698 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev, 8699 enum rte_filter_op filter_op, 8700 void *arg) 8701 { 8702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8703 int ret = I40E_ERR_PARAM; 8704 8705 switch (filter_op) { 8706 case RTE_ETH_FILTER_SET: 8707 ret = i40e_dev_global_config_set(hw, 8708 (struct rte_eth_global_cfg *)arg); 8709 break; 8710 default: 8711 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 8712 break; 8713 } 8714 8715 return ret; 8716 } 8717 8718 static int 8719 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, 8720 enum rte_filter_op filter_op, 8721 void *arg) 8722 { 8723 struct rte_eth_tunnel_filter_conf *filter; 8724 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8725 int ret = I40E_SUCCESS; 8726 8727 filter = (struct rte_eth_tunnel_filter_conf *)(arg); 8728 8729 if (i40e_tunnel_filter_param_check(pf, filter) < 0) 8730 return I40E_ERR_PARAM; 8731 8732 switch (filter_op) { 8733 case RTE_ETH_FILTER_NOP: 8734 if (!(pf->flags & I40E_FLAG_VXLAN)) 8735 ret = I40E_NOT_SUPPORTED; 8736 break; 8737 case RTE_ETH_FILTER_ADD: 8738 ret = i40e_dev_tunnel_filter_set(pf, filter, 1); 8739 break; 8740 case RTE_ETH_FILTER_DELETE: 8741 ret = i40e_dev_tunnel_filter_set(pf, filter, 0); 8742 break; 8743 default: 8744 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 8745 ret = I40E_ERR_PARAM; 8746 break; 8747 } 8748 8749 return ret; 8750 } 8751 8752 static int 8753 i40e_pf_config_mq_rx(struct i40e_pf *pf) 8754 { 8755 int ret = 0; 8756 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode; 8757 8758 /* RSS setup */ 8759 if (mq_mode & ETH_MQ_RX_RSS_FLAG) 8760 ret = i40e_pf_config_rss(pf); 8761 else 8762 i40e_pf_disable_rss(pf); 8763 8764 return ret; 8765 } 8766 8767 /* Get the symmetric hash enable configurations per port */ 8768 static void 8769 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable) 8770 { 8771 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); 8772 8773 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0; 8774 } 8775 8776 /* Set the symmetric hash enable configurations per port */ 8777 static void 8778 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable) 8779 { 8780 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); 8781 8782 if (enable > 0) { 8783 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) { 8784 PMD_DRV_LOG(INFO, 8785 "Symmetric hash has already been enabled"); 8786 return; 8787 } 8788 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK; 8789 } else { 8790 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) { 8791 PMD_DRV_LOG(INFO, 8792 "Symmetric hash has already been disabled"); 8793 return; 8794 } 8795 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK; 8796 } 8797 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg); 8798 I40E_WRITE_FLUSH(hw); 8799 } 8800 8801 /* 8802 * Get global configurations of hash function type and symmetric hash enable 8803 * per flow type (pctype). Note that global configuration means it affects all 8804 * the ports on the same NIC. 8805 */ 8806 static int 8807 i40e_get_hash_filter_global_config(struct i40e_hw *hw, 8808 struct rte_eth_hash_global_conf *g_cfg) 8809 { 8810 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back; 8811 uint32_t reg; 8812 uint16_t i, j; 8813 8814 memset(g_cfg, 0, sizeof(*g_cfg)); 8815 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 8816 if (reg & I40E_GLQF_CTL_HTOEP_MASK) 8817 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ; 8818 else 8819 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR; 8820 PMD_DRV_LOG(DEBUG, "Hash function is %s", 8821 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); 8822 8823 /* 8824 * As i40e supports less than 64 flow types, only first 64 bits need to 8825 * be checked. 8826 */ 8827 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { 8828 g_cfg->valid_bit_mask[i] = 0ULL; 8829 g_cfg->sym_hash_enable_mask[i] = 0ULL; 8830 } 8831 8832 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask; 8833 8834 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) { 8835 if (!adapter->pctypes_tbl[i]) 8836 continue; 8837 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 8838 j < I40E_FILTER_PCTYPE_MAX; j++) { 8839 if (adapter->pctypes_tbl[i] & (1ULL << j)) { 8840 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j)); 8841 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) { 8842 g_cfg->sym_hash_enable_mask[0] |= 8843 (1ULL << i); 8844 } 8845 } 8846 } 8847 } 8848 8849 return 0; 8850 } 8851 8852 static int 8853 i40e_hash_global_config_check(const struct i40e_adapter *adapter, 8854 const struct rte_eth_hash_global_conf *g_cfg) 8855 { 8856 uint32_t i; 8857 uint64_t mask0, i40e_mask = adapter->flow_types_mask; 8858 8859 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ && 8860 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR && 8861 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) { 8862 PMD_DRV_LOG(ERR, "Unsupported hash function type %d", 8863 g_cfg->hash_func); 8864 return -EINVAL; 8865 } 8866 8867 /* 8868 * As i40e supports less than 64 flow types, only first 64 bits need to 8869 * be checked. 8870 */ 8871 mask0 = g_cfg->valid_bit_mask[0]; 8872 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { 8873 if (i == 0) { 8874 /* Check if any unsupported flow type configured */ 8875 if ((mask0 | i40e_mask) ^ i40e_mask) 8876 goto mask_err; 8877 } else { 8878 if (g_cfg->valid_bit_mask[i]) 8879 goto mask_err; 8880 } 8881 } 8882 8883 return 0; 8884 8885 mask_err: 8886 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured"); 8887 8888 return -EINVAL; 8889 } 8890 8891 /* 8892 * Set global configurations of hash function type and symmetric hash enable 8893 * per flow type (pctype). Note any modifying global configuration will affect 8894 * all the ports on the same NIC. 8895 */ 8896 static int 8897 i40e_set_hash_filter_global_config(struct i40e_hw *hw, 8898 struct rte_eth_hash_global_conf *g_cfg) 8899 { 8900 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back; 8901 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 8902 int ret; 8903 uint16_t i, j; 8904 uint32_t reg; 8905 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask; 8906 8907 if (pf->support_multi_driver) { 8908 PMD_DRV_LOG(ERR, "Hash global configuration is not supported."); 8909 return -ENOTSUP; 8910 } 8911 8912 /* Check the input parameters */ 8913 ret = i40e_hash_global_config_check(adapter, g_cfg); 8914 if (ret < 0) 8915 return ret; 8916 8917 /* 8918 * As i40e supports less than 64 flow types, only first 64 bits need to 8919 * be configured. 8920 */ 8921 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) { 8922 if (mask0 & (1UL << i)) { 8923 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ? 8924 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; 8925 8926 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 8927 j < I40E_FILTER_PCTYPE_MAX; j++) { 8928 if (adapter->pctypes_tbl[i] & (1ULL << j)) 8929 i40e_write_global_rx_ctl(hw, 8930 I40E_GLQF_HSYM(j), 8931 reg); 8932 } 8933 } 8934 } 8935 8936 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 8937 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) { 8938 /* Toeplitz */ 8939 if (reg & I40E_GLQF_CTL_HTOEP_MASK) { 8940 PMD_DRV_LOG(DEBUG, 8941 "Hash function already set to Toeplitz"); 8942 goto out; 8943 } 8944 reg |= I40E_GLQF_CTL_HTOEP_MASK; 8945 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { 8946 /* Simple XOR */ 8947 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) { 8948 PMD_DRV_LOG(DEBUG, 8949 "Hash function already set to Simple XOR"); 8950 goto out; 8951 } 8952 reg &= ~I40E_GLQF_CTL_HTOEP_MASK; 8953 } else 8954 /* Use the default, and keep it as it is */ 8955 goto out; 8956 8957 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg); 8958 8959 out: 8960 I40E_WRITE_FLUSH(hw); 8961 8962 return 0; 8963 } 8964 8965 /** 8966 * Valid input sets for hash and flow director filters per PCTYPE 8967 */ 8968 static uint64_t 8969 i40e_get_valid_input_set(enum i40e_filter_pctype pctype, 8970 enum rte_filter_type filter) 8971 { 8972 uint64_t valid; 8973 8974 static const uint64_t valid_hash_inset_table[] = { 8975 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 8976 I40E_INSET_DMAC | I40E_INSET_SMAC | 8977 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8978 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC | 8979 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS | 8980 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8981 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8982 I40E_INSET_FLEX_PAYLOAD, 8983 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 8984 I40E_INSET_DMAC | I40E_INSET_SMAC | 8985 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8986 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 8987 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8988 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8989 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 8990 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 8991 I40E_INSET_FLEX_PAYLOAD, 8992 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 8993 I40E_INSET_DMAC | I40E_INSET_SMAC | 8994 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8995 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 8996 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8997 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8998 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 8999 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9000 I40E_INSET_FLEX_PAYLOAD, 9001 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9002 I40E_INSET_DMAC | I40E_INSET_SMAC | 9003 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9004 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9005 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9006 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9007 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9008 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9009 I40E_INSET_FLEX_PAYLOAD, 9010 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9011 I40E_INSET_DMAC | I40E_INSET_SMAC | 9012 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9013 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9014 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9015 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9016 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9017 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9018 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD, 9019 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9020 I40E_INSET_DMAC | I40E_INSET_SMAC | 9021 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9022 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9023 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9024 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9025 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9026 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9027 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD, 9028 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9029 I40E_INSET_DMAC | I40E_INSET_SMAC | 9030 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9031 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9032 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9033 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9034 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9035 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9036 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD, 9037 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9038 I40E_INSET_DMAC | I40E_INSET_SMAC | 9039 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9040 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9041 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9042 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9043 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9044 I40E_INSET_FLEX_PAYLOAD, 9045 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9046 I40E_INSET_DMAC | I40E_INSET_SMAC | 9047 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9048 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9049 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9050 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC | 9051 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC | 9052 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD, 9053 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9054 I40E_INSET_DMAC | I40E_INSET_SMAC | 9055 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9056 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9057 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9058 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9059 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9060 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD, 9061 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9062 I40E_INSET_DMAC | I40E_INSET_SMAC | 9063 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9064 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9065 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9066 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9067 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9068 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9069 I40E_INSET_FLEX_PAYLOAD, 9070 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9071 I40E_INSET_DMAC | I40E_INSET_SMAC | 9072 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9073 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9074 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9075 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9076 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9077 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9078 I40E_INSET_FLEX_PAYLOAD, 9079 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9080 I40E_INSET_DMAC | I40E_INSET_SMAC | 9081 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9082 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9083 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9084 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9085 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9086 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9087 I40E_INSET_FLEX_PAYLOAD, 9088 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9089 I40E_INSET_DMAC | I40E_INSET_SMAC | 9090 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9091 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9092 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9093 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9094 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9095 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9096 I40E_INSET_FLEX_PAYLOAD, 9097 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9098 I40E_INSET_DMAC | I40E_INSET_SMAC | 9099 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9100 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9101 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9102 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9103 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9104 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT | 9105 I40E_INSET_FLEX_PAYLOAD, 9106 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9107 I40E_INSET_DMAC | I40E_INSET_SMAC | 9108 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9109 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9110 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9111 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9112 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID | 9113 I40E_INSET_FLEX_PAYLOAD, 9114 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9115 I40E_INSET_DMAC | I40E_INSET_SMAC | 9116 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9117 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE | 9118 I40E_INSET_FLEX_PAYLOAD, 9119 }; 9120 9121 /** 9122 * Flow director supports only fields defined in 9123 * union rte_eth_fdir_flow. 9124 */ 9125 static const uint64_t valid_fdir_inset_table[] = { 9126 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9127 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9128 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9129 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO | 9130 I40E_INSET_IPV4_TTL, 9131 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9132 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9133 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9134 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9135 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9136 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9138 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9139 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9140 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9141 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9142 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9143 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9144 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9145 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9146 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9147 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9148 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9149 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9150 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9151 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9152 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9153 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9154 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9155 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9156 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9157 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9158 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9159 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9160 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9161 I40E_INSET_SCTP_VT, 9162 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9163 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9164 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9165 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO | 9166 I40E_INSET_IPV4_TTL, 9167 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9168 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9169 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9170 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR | 9171 I40E_INSET_IPV6_HOP_LIMIT, 9172 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9173 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9174 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9175 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9176 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9177 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9178 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9179 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9180 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9181 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9182 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9183 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9184 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9185 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9186 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9187 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9188 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9189 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9190 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9191 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9192 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9193 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9194 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9195 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9196 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9197 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9198 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9199 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9200 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9201 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9202 I40E_INSET_SCTP_VT, 9203 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9204 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9205 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9206 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR | 9207 I40E_INSET_IPV6_HOP_LIMIT, 9208 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9209 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9210 I40E_INSET_LAST_ETHER_TYPE, 9211 }; 9212 9213 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) 9214 return 0; 9215 if (filter == RTE_ETH_FILTER_HASH) 9216 valid = valid_hash_inset_table[pctype]; 9217 else 9218 valid = valid_fdir_inset_table[pctype]; 9219 9220 return valid; 9221 } 9222 9223 /** 9224 * Validate if the input set is allowed for a specific PCTYPE 9225 */ 9226 int 9227 i40e_validate_input_set(enum i40e_filter_pctype pctype, 9228 enum rte_filter_type filter, uint64_t inset) 9229 { 9230 uint64_t valid; 9231 9232 valid = i40e_get_valid_input_set(pctype, filter); 9233 if (inset & (~valid)) 9234 return -EINVAL; 9235 9236 return 0; 9237 } 9238 9239 /* default input set fields combination per pctype */ 9240 uint64_t 9241 i40e_get_default_input_set(uint16_t pctype) 9242 { 9243 static const uint64_t default_inset_table[] = { 9244 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9245 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, 9246 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9247 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9248 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9249 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9250 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9251 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9252 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9253 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9254 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9255 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9256 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9257 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9258 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9259 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9260 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9261 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9262 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9263 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9264 I40E_INSET_SCTP_VT, 9265 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9266 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, 9267 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9268 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, 9269 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9270 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9271 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9272 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9273 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9274 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9275 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9276 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9277 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9278 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9279 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9280 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9281 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9282 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9283 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9284 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9285 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9286 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9287 I40E_INSET_SCTP_VT, 9288 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9289 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, 9290 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9291 I40E_INSET_LAST_ETHER_TYPE, 9292 }; 9293 9294 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) 9295 return 0; 9296 9297 return default_inset_table[pctype]; 9298 } 9299 9300 /** 9301 * Parse the input set from index to logical bit masks 9302 */ 9303 static int 9304 i40e_parse_input_set(uint64_t *inset, 9305 enum i40e_filter_pctype pctype, 9306 enum rte_eth_input_set_field *field, 9307 uint16_t size) 9308 { 9309 uint16_t i, j; 9310 int ret = -EINVAL; 9311 9312 static const struct { 9313 enum rte_eth_input_set_field field; 9314 uint64_t inset; 9315 } inset_convert_table[] = { 9316 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE}, 9317 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC}, 9318 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC}, 9319 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER}, 9320 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER}, 9321 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE}, 9322 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC}, 9323 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST}, 9324 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS}, 9325 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO}, 9326 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL}, 9327 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC}, 9328 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST}, 9329 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC}, 9330 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER, 9331 I40E_INSET_IPV6_NEXT_HDR}, 9332 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS, 9333 I40E_INSET_IPV6_HOP_LIMIT}, 9334 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT}, 9335 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT}, 9336 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT}, 9337 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT}, 9338 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT}, 9339 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT}, 9340 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG, 9341 I40E_INSET_SCTP_VT}, 9342 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC, 9343 I40E_INSET_TUNNEL_DMAC}, 9344 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN, 9345 I40E_INSET_VLAN_TUNNEL}, 9346 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY, 9347 I40E_INSET_TUNNEL_ID}, 9348 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID}, 9349 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD, 9350 I40E_INSET_FLEX_PAYLOAD_W1}, 9351 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD, 9352 I40E_INSET_FLEX_PAYLOAD_W2}, 9353 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD, 9354 I40E_INSET_FLEX_PAYLOAD_W3}, 9355 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD, 9356 I40E_INSET_FLEX_PAYLOAD_W4}, 9357 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD, 9358 I40E_INSET_FLEX_PAYLOAD_W5}, 9359 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD, 9360 I40E_INSET_FLEX_PAYLOAD_W6}, 9361 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD, 9362 I40E_INSET_FLEX_PAYLOAD_W7}, 9363 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD, 9364 I40E_INSET_FLEX_PAYLOAD_W8}, 9365 }; 9366 9367 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX) 9368 return ret; 9369 9370 /* Only one item allowed for default or all */ 9371 if (size == 1) { 9372 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) { 9373 *inset = i40e_get_default_input_set(pctype); 9374 return 0; 9375 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) { 9376 *inset = I40E_INSET_NONE; 9377 return 0; 9378 } 9379 } 9380 9381 for (i = 0, *inset = 0; i < size; i++) { 9382 for (j = 0; j < RTE_DIM(inset_convert_table); j++) { 9383 if (field[i] == inset_convert_table[j].field) { 9384 *inset |= inset_convert_table[j].inset; 9385 break; 9386 } 9387 } 9388 9389 /* It contains unsupported input set, return immediately */ 9390 if (j == RTE_DIM(inset_convert_table)) 9391 return ret; 9392 } 9393 9394 return 0; 9395 } 9396 9397 /** 9398 * Translate the input set from bit masks to register aware bit masks 9399 * and vice versa 9400 */ 9401 uint64_t 9402 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input) 9403 { 9404 uint64_t val = 0; 9405 uint16_t i; 9406 9407 struct inset_map { 9408 uint64_t inset; 9409 uint64_t inset_reg; 9410 }; 9411 9412 static const struct inset_map inset_map_common[] = { 9413 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC}, 9414 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC}, 9415 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN}, 9416 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN}, 9417 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE}, 9418 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS}, 9419 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6}, 9420 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6}, 9421 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC}, 9422 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR}, 9423 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT}, 9424 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT}, 9425 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT}, 9426 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG}, 9427 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID}, 9428 {I40E_INSET_TUNNEL_DMAC, 9429 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC}, 9430 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4}, 9431 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6}, 9432 {I40E_INSET_TUNNEL_SRC_PORT, 9433 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT}, 9434 {I40E_INSET_TUNNEL_DST_PORT, 9435 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT}, 9436 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN}, 9437 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1}, 9438 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2}, 9439 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3}, 9440 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4}, 9441 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5}, 9442 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6}, 9443 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7}, 9444 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8}, 9445 }; 9446 9447 /* some different registers map in x722*/ 9448 static const struct inset_map inset_map_diff_x722[] = { 9449 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4}, 9450 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4}, 9451 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO}, 9452 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL}, 9453 }; 9454 9455 static const struct inset_map inset_map_diff_not_x722[] = { 9456 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4}, 9457 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4}, 9458 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO}, 9459 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL}, 9460 }; 9461 9462 if (input == 0) 9463 return val; 9464 9465 /* Translate input set to register aware inset */ 9466 if (type == I40E_MAC_X722) { 9467 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) { 9468 if (input & inset_map_diff_x722[i].inset) 9469 val |= inset_map_diff_x722[i].inset_reg; 9470 } 9471 } else { 9472 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) { 9473 if (input & inset_map_diff_not_x722[i].inset) 9474 val |= inset_map_diff_not_x722[i].inset_reg; 9475 } 9476 } 9477 9478 for (i = 0; i < RTE_DIM(inset_map_common); i++) { 9479 if (input & inset_map_common[i].inset) 9480 val |= inset_map_common[i].inset_reg; 9481 } 9482 9483 return val; 9484 } 9485 9486 int 9487 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem) 9488 { 9489 uint8_t i, idx = 0; 9490 uint64_t inset_need_mask = inset; 9491 9492 static const struct { 9493 uint64_t inset; 9494 uint32_t mask; 9495 } inset_mask_map[] = { 9496 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK}, 9497 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0}, 9498 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK}, 9499 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK}, 9500 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK}, 9501 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0}, 9502 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK}, 9503 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK}, 9504 }; 9505 9506 if (!inset || !mask || !nb_elem) 9507 return 0; 9508 9509 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { 9510 /* Clear the inset bit, if no MASK is required, 9511 * for example proto + ttl 9512 */ 9513 if ((inset & inset_mask_map[i].inset) == 9514 inset_mask_map[i].inset && inset_mask_map[i].mask == 0) 9515 inset_need_mask &= ~inset_mask_map[i].inset; 9516 if (!inset_need_mask) 9517 return 0; 9518 } 9519 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { 9520 if ((inset_need_mask & inset_mask_map[i].inset) == 9521 inset_mask_map[i].inset) { 9522 if (idx >= nb_elem) { 9523 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks"); 9524 return -EINVAL; 9525 } 9526 mask[idx] = inset_mask_map[i].mask; 9527 idx++; 9528 } 9529 } 9530 9531 return idx; 9532 } 9533 9534 void 9535 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) 9536 { 9537 uint32_t reg = i40e_read_rx_ctl(hw, addr); 9538 9539 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg); 9540 if (reg != val) 9541 i40e_write_rx_ctl(hw, addr, val); 9542 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr, 9543 (uint32_t)i40e_read_rx_ctl(hw, addr)); 9544 } 9545 9546 void 9547 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) 9548 { 9549 uint32_t reg = i40e_read_rx_ctl(hw, addr); 9550 struct rte_eth_dev *dev; 9551 9552 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 9553 if (reg != val) { 9554 i40e_write_rx_ctl(hw, addr, val); 9555 PMD_DRV_LOG(WARNING, 9556 "i40e device %s changed global register [0x%08x]." 9557 " original: 0x%08x, new: 0x%08x", 9558 dev->device->name, addr, reg, 9559 (uint32_t)i40e_read_rx_ctl(hw, addr)); 9560 } 9561 } 9562 9563 static void 9564 i40e_filter_input_set_init(struct i40e_pf *pf) 9565 { 9566 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9567 enum i40e_filter_pctype pctype; 9568 uint64_t input_set, inset_reg; 9569 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9570 int num, i; 9571 uint16_t flow_type; 9572 9573 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 9574 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) { 9575 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype); 9576 9577 if (flow_type == RTE_ETH_FLOW_UNKNOWN) 9578 continue; 9579 9580 input_set = i40e_get_default_input_set(pctype); 9581 9582 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9583 I40E_INSET_MASK_NUM_REG); 9584 if (num < 0) 9585 return; 9586 if (pf->support_multi_driver && num > 0) { 9587 PMD_DRV_LOG(ERR, "Input set setting is not supported."); 9588 return; 9589 } 9590 inset_reg = i40e_translate_input_set_reg(hw->mac.type, 9591 input_set); 9592 9593 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 9594 (uint32_t)(inset_reg & UINT32_MAX)); 9595 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 9596 (uint32_t)((inset_reg >> 9597 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9598 if (!pf->support_multi_driver) { 9599 i40e_check_write_global_reg(hw, 9600 I40E_GLQF_HASH_INSET(0, pctype), 9601 (uint32_t)(inset_reg & UINT32_MAX)); 9602 i40e_check_write_global_reg(hw, 9603 I40E_GLQF_HASH_INSET(1, pctype), 9604 (uint32_t)((inset_reg >> 9605 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9606 9607 for (i = 0; i < num; i++) { 9608 i40e_check_write_global_reg(hw, 9609 I40E_GLQF_FD_MSK(i, pctype), 9610 mask_reg[i]); 9611 i40e_check_write_global_reg(hw, 9612 I40E_GLQF_HASH_MSK(i, pctype), 9613 mask_reg[i]); 9614 } 9615 /*clear unused mask registers of the pctype */ 9616 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) { 9617 i40e_check_write_global_reg(hw, 9618 I40E_GLQF_FD_MSK(i, pctype), 9619 0); 9620 i40e_check_write_global_reg(hw, 9621 I40E_GLQF_HASH_MSK(i, pctype), 9622 0); 9623 } 9624 } else { 9625 PMD_DRV_LOG(ERR, "Input set setting is not supported."); 9626 } 9627 I40E_WRITE_FLUSH(hw); 9628 9629 /* store the default input set */ 9630 if (!pf->support_multi_driver) 9631 pf->hash_input_set[pctype] = input_set; 9632 pf->fdir.input_set[pctype] = input_set; 9633 } 9634 } 9635 9636 int 9637 i40e_hash_filter_inset_select(struct i40e_hw *hw, 9638 struct rte_eth_input_set_conf *conf) 9639 { 9640 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 9641 enum i40e_filter_pctype pctype; 9642 uint64_t input_set, inset_reg = 0; 9643 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9644 int ret, i, num; 9645 9646 if (!conf) { 9647 PMD_DRV_LOG(ERR, "Invalid pointer"); 9648 return -EFAULT; 9649 } 9650 if (conf->op != RTE_ETH_INPUT_SET_SELECT && 9651 conf->op != RTE_ETH_INPUT_SET_ADD) { 9652 PMD_DRV_LOG(ERR, "Unsupported input set operation"); 9653 return -EINVAL; 9654 } 9655 9656 if (pf->support_multi_driver) { 9657 PMD_DRV_LOG(ERR, "Hash input set setting is not supported."); 9658 return -ENOTSUP; 9659 } 9660 9661 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); 9662 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 9663 PMD_DRV_LOG(ERR, "invalid flow_type input."); 9664 return -EINVAL; 9665 } 9666 9667 if (hw->mac.type == I40E_MAC_X722) { 9668 /* get translated pctype value in fd pctype register */ 9669 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw, 9670 I40E_GLQF_FD_PCTYPES((int)pctype)); 9671 } 9672 9673 ret = i40e_parse_input_set(&input_set, pctype, conf->field, 9674 conf->inset_size); 9675 if (ret) { 9676 PMD_DRV_LOG(ERR, "Failed to parse input set"); 9677 return -EINVAL; 9678 } 9679 9680 if (conf->op == RTE_ETH_INPUT_SET_ADD) { 9681 /* get inset value in register */ 9682 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype)); 9683 inset_reg <<= I40E_32_BIT_WIDTH; 9684 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype)); 9685 input_set |= pf->hash_input_set[pctype]; 9686 } 9687 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9688 I40E_INSET_MASK_NUM_REG); 9689 if (num < 0) 9690 return -EINVAL; 9691 9692 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 9693 9694 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype), 9695 (uint32_t)(inset_reg & UINT32_MAX)); 9696 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), 9697 (uint32_t)((inset_reg >> 9698 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9699 9700 for (i = 0; i < num; i++) 9701 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 9702 mask_reg[i]); 9703 /*clear unused mask registers of the pctype */ 9704 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 9705 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 9706 0); 9707 I40E_WRITE_FLUSH(hw); 9708 9709 pf->hash_input_set[pctype] = input_set; 9710 return 0; 9711 } 9712 9713 int 9714 i40e_fdir_filter_inset_select(struct i40e_pf *pf, 9715 struct rte_eth_input_set_conf *conf) 9716 { 9717 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9718 enum i40e_filter_pctype pctype; 9719 uint64_t input_set, inset_reg = 0; 9720 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9721 int ret, i, num; 9722 9723 if (!hw || !conf) { 9724 PMD_DRV_LOG(ERR, "Invalid pointer"); 9725 return -EFAULT; 9726 } 9727 if (conf->op != RTE_ETH_INPUT_SET_SELECT && 9728 conf->op != RTE_ETH_INPUT_SET_ADD) { 9729 PMD_DRV_LOG(ERR, "Unsupported input set operation"); 9730 return -EINVAL; 9731 } 9732 9733 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); 9734 9735 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 9736 PMD_DRV_LOG(ERR, "invalid flow_type input."); 9737 return -EINVAL; 9738 } 9739 9740 ret = i40e_parse_input_set(&input_set, pctype, conf->field, 9741 conf->inset_size); 9742 if (ret) { 9743 PMD_DRV_LOG(ERR, "Failed to parse input set"); 9744 return -EINVAL; 9745 } 9746 9747 /* get inset value in register */ 9748 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1)); 9749 inset_reg <<= I40E_32_BIT_WIDTH; 9750 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0)); 9751 9752 /* Can not change the inset reg for flex payload for fdir, 9753 * it is done by writing I40E_PRTQF_FD_FLXINSET 9754 * in i40e_set_flex_mask_on_pctype. 9755 */ 9756 if (conf->op == RTE_ETH_INPUT_SET_SELECT) 9757 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS; 9758 else 9759 input_set |= pf->fdir.input_set[pctype]; 9760 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9761 I40E_INSET_MASK_NUM_REG); 9762 if (num < 0) 9763 return -EINVAL; 9764 if (pf->support_multi_driver && num > 0) { 9765 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); 9766 return -ENOTSUP; 9767 } 9768 9769 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 9770 9771 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 9772 (uint32_t)(inset_reg & UINT32_MAX)); 9773 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 9774 (uint32_t)((inset_reg >> 9775 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9776 9777 if (!pf->support_multi_driver) { 9778 for (i = 0; i < num; i++) 9779 i40e_check_write_global_reg(hw, 9780 I40E_GLQF_FD_MSK(i, pctype), 9781 mask_reg[i]); 9782 /*clear unused mask registers of the pctype */ 9783 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 9784 i40e_check_write_global_reg(hw, 9785 I40E_GLQF_FD_MSK(i, pctype), 9786 0); 9787 } else { 9788 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); 9789 } 9790 I40E_WRITE_FLUSH(hw); 9791 9792 pf->fdir.input_set[pctype] = input_set; 9793 return 0; 9794 } 9795 9796 static int 9797 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) 9798 { 9799 int ret = 0; 9800 9801 if (!hw || !info) { 9802 PMD_DRV_LOG(ERR, "Invalid pointer"); 9803 return -EFAULT; 9804 } 9805 9806 switch (info->info_type) { 9807 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT: 9808 i40e_get_symmetric_hash_enable_per_port(hw, 9809 &(info->info.enable)); 9810 break; 9811 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG: 9812 ret = i40e_get_hash_filter_global_config(hw, 9813 &(info->info.global_conf)); 9814 break; 9815 default: 9816 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", 9817 info->info_type); 9818 ret = -EINVAL; 9819 break; 9820 } 9821 9822 return ret; 9823 } 9824 9825 static int 9826 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) 9827 { 9828 int ret = 0; 9829 9830 if (!hw || !info) { 9831 PMD_DRV_LOG(ERR, "Invalid pointer"); 9832 return -EFAULT; 9833 } 9834 9835 switch (info->info_type) { 9836 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT: 9837 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable); 9838 break; 9839 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG: 9840 ret = i40e_set_hash_filter_global_config(hw, 9841 &(info->info.global_conf)); 9842 break; 9843 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT: 9844 ret = i40e_hash_filter_inset_select(hw, 9845 &(info->info.input_set_conf)); 9846 break; 9847 9848 default: 9849 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", 9850 info->info_type); 9851 ret = -EINVAL; 9852 break; 9853 } 9854 9855 return ret; 9856 } 9857 9858 /* Operations for hash function */ 9859 static int 9860 i40e_hash_filter_ctrl(struct rte_eth_dev *dev, 9861 enum rte_filter_op filter_op, 9862 void *arg) 9863 { 9864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 9865 int ret = 0; 9866 9867 switch (filter_op) { 9868 case RTE_ETH_FILTER_NOP: 9869 break; 9870 case RTE_ETH_FILTER_GET: 9871 ret = i40e_hash_filter_get(hw, 9872 (struct rte_eth_hash_filter_info *)arg); 9873 break; 9874 case RTE_ETH_FILTER_SET: 9875 ret = i40e_hash_filter_set(hw, 9876 (struct rte_eth_hash_filter_info *)arg); 9877 break; 9878 default: 9879 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported", 9880 filter_op); 9881 ret = -ENOTSUP; 9882 break; 9883 } 9884 9885 return ret; 9886 } 9887 9888 /* Convert ethertype filter structure */ 9889 static int 9890 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input, 9891 struct i40e_ethertype_filter *filter) 9892 { 9893 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, 9894 RTE_ETHER_ADDR_LEN); 9895 filter->input.ether_type = input->ether_type; 9896 filter->flags = input->flags; 9897 filter->queue = input->queue; 9898 9899 return 0; 9900 } 9901 9902 /* Check if there exists the ehtertype filter */ 9903 struct i40e_ethertype_filter * 9904 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 9905 const struct i40e_ethertype_filter_input *input) 9906 { 9907 int ret; 9908 9909 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input); 9910 if (ret < 0) 9911 return NULL; 9912 9913 return ethertype_rule->hash_map[ret]; 9914 } 9915 9916 /* Add ethertype filter in SW list */ 9917 static int 9918 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf, 9919 struct i40e_ethertype_filter *filter) 9920 { 9921 struct i40e_ethertype_rule *rule = &pf->ethertype; 9922 int ret; 9923 9924 ret = rte_hash_add_key(rule->hash_table, &filter->input); 9925 if (ret < 0) { 9926 PMD_DRV_LOG(ERR, 9927 "Failed to insert ethertype filter" 9928 " to hash table %d!", 9929 ret); 9930 return ret; 9931 } 9932 rule->hash_map[ret] = filter; 9933 9934 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules); 9935 9936 return 0; 9937 } 9938 9939 /* Delete ethertype filter in SW list */ 9940 int 9941 i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 9942 struct i40e_ethertype_filter_input *input) 9943 { 9944 struct i40e_ethertype_rule *rule = &pf->ethertype; 9945 struct i40e_ethertype_filter *filter; 9946 int ret; 9947 9948 ret = rte_hash_del_key(rule->hash_table, input); 9949 if (ret < 0) { 9950 PMD_DRV_LOG(ERR, 9951 "Failed to delete ethertype filter" 9952 " to hash table %d!", 9953 ret); 9954 return ret; 9955 } 9956 filter = rule->hash_map[ret]; 9957 rule->hash_map[ret] = NULL; 9958 9959 TAILQ_REMOVE(&rule->ethertype_list, filter, rules); 9960 rte_free(filter); 9961 9962 return 0; 9963 } 9964 9965 /* 9966 * Configure ethertype filter, which can director packet by filtering 9967 * with mac address and ether_type or only ether_type 9968 */ 9969 int 9970 i40e_ethertype_filter_set(struct i40e_pf *pf, 9971 struct rte_eth_ethertype_filter *filter, 9972 bool add) 9973 { 9974 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9975 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 9976 struct i40e_ethertype_filter *ethertype_filter, *node; 9977 struct i40e_ethertype_filter check_filter; 9978 struct i40e_control_filter_stats stats; 9979 uint16_t flags = 0; 9980 int ret; 9981 9982 if (filter->queue >= pf->dev_data->nb_rx_queues) { 9983 PMD_DRV_LOG(ERR, "Invalid queue ID"); 9984 return -EINVAL; 9985 } 9986 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 9987 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 9988 PMD_DRV_LOG(ERR, 9989 "unsupported ether_type(0x%04x) in control packet filter.", 9990 filter->ether_type); 9991 return -EINVAL; 9992 } 9993 if (filter->ether_type == RTE_ETHER_TYPE_VLAN) 9994 PMD_DRV_LOG(WARNING, 9995 "filter vlan ether_type in first tag is not supported."); 9996 9997 /* Check if there is the filter in SW list */ 9998 memset(&check_filter, 0, sizeof(check_filter)); 9999 i40e_ethertype_filter_convert(filter, &check_filter); 10000 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, 10001 &check_filter.input); 10002 if (add && node) { 10003 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!"); 10004 return -EINVAL; 10005 } 10006 10007 if (!add && !node) { 10008 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!"); 10009 return -EINVAL; 10010 } 10011 10012 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC)) 10013 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 10014 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) 10015 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 10016 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 10017 10018 memset(&stats, 0, sizeof(stats)); 10019 ret = i40e_aq_add_rem_control_packet_filter(hw, 10020 filter->mac_addr.addr_bytes, 10021 filter->ether_type, flags, 10022 pf->main_vsi->seid, 10023 filter->queue, add, &stats, NULL); 10024 10025 PMD_DRV_LOG(INFO, 10026 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u", 10027 ret, stats.mac_etype_used, stats.etype_used, 10028 stats.mac_etype_free, stats.etype_free); 10029 if (ret < 0) 10030 return -ENOSYS; 10031 10032 /* Add or delete a filter in SW list */ 10033 if (add) { 10034 ethertype_filter = rte_zmalloc("ethertype_filter", 10035 sizeof(*ethertype_filter), 0); 10036 if (ethertype_filter == NULL) { 10037 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 10038 return -ENOMEM; 10039 } 10040 10041 rte_memcpy(ethertype_filter, &check_filter, 10042 sizeof(check_filter)); 10043 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter); 10044 if (ret < 0) 10045 rte_free(ethertype_filter); 10046 } else { 10047 ret = i40e_sw_ethertype_filter_del(pf, &node->input); 10048 } 10049 10050 return ret; 10051 } 10052 10053 /* 10054 * Handle operations for ethertype filter. 10055 */ 10056 static int 10057 i40e_ethertype_filter_handle(struct rte_eth_dev *dev, 10058 enum rte_filter_op filter_op, 10059 void *arg) 10060 { 10061 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10062 int ret = 0; 10063 10064 if (filter_op == RTE_ETH_FILTER_NOP) 10065 return ret; 10066 10067 if (arg == NULL) { 10068 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 10069 filter_op); 10070 return -EINVAL; 10071 } 10072 10073 switch (filter_op) { 10074 case RTE_ETH_FILTER_ADD: 10075 ret = i40e_ethertype_filter_set(pf, 10076 (struct rte_eth_ethertype_filter *)arg, 10077 TRUE); 10078 break; 10079 case RTE_ETH_FILTER_DELETE: 10080 ret = i40e_ethertype_filter_set(pf, 10081 (struct rte_eth_ethertype_filter *)arg, 10082 FALSE); 10083 break; 10084 default: 10085 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 10086 ret = -ENOSYS; 10087 break; 10088 } 10089 return ret; 10090 } 10091 10092 static int 10093 i40e_dev_filter_ctrl(struct rte_eth_dev *dev, 10094 enum rte_filter_type filter_type, 10095 enum rte_filter_op filter_op, 10096 void *arg) 10097 { 10098 int ret = 0; 10099 10100 if (dev == NULL) 10101 return -EINVAL; 10102 10103 switch (filter_type) { 10104 case RTE_ETH_FILTER_NONE: 10105 /* For global configuration */ 10106 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg); 10107 break; 10108 case RTE_ETH_FILTER_HASH: 10109 ret = i40e_hash_filter_ctrl(dev, filter_op, arg); 10110 break; 10111 case RTE_ETH_FILTER_MACVLAN: 10112 ret = i40e_mac_filter_handle(dev, filter_op, arg); 10113 break; 10114 case RTE_ETH_FILTER_ETHERTYPE: 10115 ret = i40e_ethertype_filter_handle(dev, filter_op, arg); 10116 break; 10117 case RTE_ETH_FILTER_TUNNEL: 10118 ret = i40e_tunnel_filter_handle(dev, filter_op, arg); 10119 break; 10120 case RTE_ETH_FILTER_FDIR: 10121 ret = i40e_fdir_ctrl_func(dev, filter_op, arg); 10122 break; 10123 case RTE_ETH_FILTER_GENERIC: 10124 if (filter_op != RTE_ETH_FILTER_GET) 10125 return -EINVAL; 10126 *(const void **)arg = &i40e_flow_ops; 10127 break; 10128 default: 10129 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 10130 filter_type); 10131 ret = -EINVAL; 10132 break; 10133 } 10134 10135 return ret; 10136 } 10137 10138 /* 10139 * Check and enable Extended Tag. 10140 * Enabling Extended Tag is important for 40G performance. 10141 */ 10142 static void 10143 i40e_enable_extended_tag(struct rte_eth_dev *dev) 10144 { 10145 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 10146 uint32_t buf = 0; 10147 int ret; 10148 10149 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf), 10150 PCI_DEV_CAP_REG); 10151 if (ret < 0) { 10152 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", 10153 PCI_DEV_CAP_REG); 10154 return; 10155 } 10156 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { 10157 PMD_DRV_LOG(ERR, "Does not support Extended Tag"); 10158 return; 10159 } 10160 10161 buf = 0; 10162 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf), 10163 PCI_DEV_CTRL_REG); 10164 if (ret < 0) { 10165 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", 10166 PCI_DEV_CTRL_REG); 10167 return; 10168 } 10169 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { 10170 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); 10171 return; 10172 } 10173 buf |= PCI_DEV_CTRL_EXT_TAG_MASK; 10174 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf), 10175 PCI_DEV_CTRL_REG); 10176 if (ret < 0) { 10177 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", 10178 PCI_DEV_CTRL_REG); 10179 return; 10180 } 10181 } 10182 10183 /* 10184 * As some registers wouldn't be reset unless a global hardware reset, 10185 * hardware initialization is needed to put those registers into an 10186 * expected initial state. 10187 */ 10188 static void 10189 i40e_hw_init(struct rte_eth_dev *dev) 10190 { 10191 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10192 10193 i40e_enable_extended_tag(dev); 10194 10195 /* clear the PF Queue Filter control register */ 10196 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0); 10197 10198 /* Disable symmetric hash per port */ 10199 i40e_set_symmetric_hash_enable_per_port(hw, 0); 10200 } 10201 10202 /* 10203 * For X722 it is possible to have multiple pctypes mapped to the same flowtype 10204 * however this function will return only one highest pctype index, 10205 * which is not quite correct. This is known problem of i40e driver 10206 * and needs to be fixed later. 10207 */ 10208 enum i40e_filter_pctype 10209 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type) 10210 { 10211 int i; 10212 uint64_t pctype_mask; 10213 10214 if (flow_type < I40E_FLOW_TYPE_MAX) { 10215 pctype_mask = adapter->pctypes_tbl[flow_type]; 10216 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) { 10217 if (pctype_mask & (1ULL << i)) 10218 return (enum i40e_filter_pctype)i; 10219 } 10220 } 10221 return I40E_FILTER_PCTYPE_INVALID; 10222 } 10223 10224 uint16_t 10225 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 10226 enum i40e_filter_pctype pctype) 10227 { 10228 uint16_t flowtype; 10229 uint64_t pctype_mask = 1ULL << pctype; 10230 10231 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX; 10232 flowtype++) { 10233 if (adapter->pctypes_tbl[flowtype] & pctype_mask) 10234 return flowtype; 10235 } 10236 10237 return RTE_ETH_FLOW_UNKNOWN; 10238 } 10239 10240 /* 10241 * On X710, performance number is far from the expectation on recent firmware 10242 * versions; on XL710, performance number is also far from the expectation on 10243 * recent firmware versions, if promiscuous mode is disabled, or promiscuous 10244 * mode is enabled and port MAC address is equal to the packet destination MAC 10245 * address. The fix for this issue may not be integrated in the following 10246 * firmware version. So the workaround in software driver is needed. It needs 10247 * to modify the initial values of 3 internal only registers for both X710 and 10248 * XL710. Note that the values for X710 or XL710 could be different, and the 10249 * workaround can be removed when it is fixed in firmware in the future. 10250 */ 10251 10252 /* For both X710 and XL710 */ 10253 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200 10254 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200 10255 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00 10256 10257 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200 10258 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08 10259 10260 /* For X722 */ 10261 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200 10262 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200 10263 10264 /* For X710 */ 10265 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303 10266 /* For XL710 */ 10267 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606 10268 #define I40E_GL_SWR_PM_UP_THR 0x269FBC 10269 10270 /* 10271 * GL_SWR_PM_UP_THR: 10272 * The value is not impacted from the link speed, its value is set according 10273 * to the total number of ports for a better pipe-monitor configuration. 10274 */ 10275 static bool 10276 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value) 10277 { 10278 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \ 10279 .device_id = (dev), \ 10280 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE 10281 10282 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \ 10283 .device_id = (dev), \ 10284 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE 10285 10286 static const struct { 10287 uint16_t device_id; 10288 uint32_t val; 10289 } swr_pm_table[] = { 10290 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) }, 10291 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) }, 10292 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) }, 10293 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) }, 10294 10295 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) }, 10296 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) }, 10297 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) }, 10298 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) }, 10299 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) }, 10300 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) }, 10301 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) }, 10302 }; 10303 uint32_t i; 10304 10305 if (value == NULL) { 10306 PMD_DRV_LOG(ERR, "value is NULL"); 10307 return false; 10308 } 10309 10310 for (i = 0; i < RTE_DIM(swr_pm_table); i++) { 10311 if (hw->device_id == swr_pm_table[i].device_id) { 10312 *value = swr_pm_table[i].val; 10313 10314 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR " 10315 "value - 0x%08x", 10316 hw->device_id, *value); 10317 return true; 10318 } 10319 } 10320 10321 return false; 10322 } 10323 10324 static int 10325 i40e_dev_sync_phy_type(struct i40e_hw *hw) 10326 { 10327 enum i40e_status_code status; 10328 struct i40e_aq_get_phy_abilities_resp phy_ab; 10329 int ret = -ENOTSUP; 10330 int retries = 0; 10331 10332 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, 10333 NULL); 10334 10335 while (status) { 10336 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d", 10337 status); 10338 retries++; 10339 rte_delay_us(100000); 10340 if (retries < 5) 10341 status = i40e_aq_get_phy_capabilities(hw, false, 10342 true, &phy_ab, NULL); 10343 else 10344 return ret; 10345 } 10346 return 0; 10347 } 10348 10349 static void 10350 i40e_configure_registers(struct i40e_hw *hw) 10351 { 10352 static struct { 10353 uint32_t addr; 10354 uint64_t val; 10355 } reg_table[] = { 10356 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0}, 10357 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0}, 10358 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */ 10359 }; 10360 uint64_t reg; 10361 uint32_t i; 10362 int ret; 10363 10364 for (i = 0; i < RTE_DIM(reg_table); i++) { 10365 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) { 10366 if (hw->mac.type == I40E_MAC_X722) /* For X722 */ 10367 reg_table[i].val = 10368 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE; 10369 else /* For X710/XL710/XXV710 */ 10370 if (hw->aq.fw_maj_ver < 6) 10371 reg_table[i].val = 10372 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1; 10373 else 10374 reg_table[i].val = 10375 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2; 10376 } 10377 10378 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) { 10379 if (hw->mac.type == I40E_MAC_X722) /* For X722 */ 10380 reg_table[i].val = 10381 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE; 10382 else /* For X710/XL710/XXV710 */ 10383 reg_table[i].val = 10384 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE; 10385 } 10386 10387 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) { 10388 uint32_t cfg_val; 10389 10390 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) { 10391 PMD_DRV_LOG(DEBUG, "Device 0x%x skips " 10392 "GL_SWR_PM_UP_THR value fixup", 10393 hw->device_id); 10394 continue; 10395 } 10396 10397 reg_table[i].val = cfg_val; 10398 } 10399 10400 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr, 10401 ®, NULL); 10402 if (ret < 0) { 10403 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32, 10404 reg_table[i].addr); 10405 break; 10406 } 10407 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64, 10408 reg_table[i].addr, reg); 10409 if (reg == reg_table[i].val) 10410 continue; 10411 10412 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr, 10413 reg_table[i].val, NULL); 10414 if (ret < 0) { 10415 PMD_DRV_LOG(ERR, 10416 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32, 10417 reg_table[i].val, reg_table[i].addr); 10418 break; 10419 } 10420 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of " 10421 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr); 10422 } 10423 } 10424 10425 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4)) 10426 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030 10427 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4)) 10428 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab 10429 static int 10430 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi) 10431 { 10432 uint32_t reg; 10433 int ret; 10434 10435 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) { 10436 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum"); 10437 return -EINVAL; 10438 } 10439 10440 /* Configure for double VLAN RX stripping */ 10441 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id)); 10442 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) { 10443 reg |= I40E_VSI_TSR_QINQ_CONFIG; 10444 ret = i40e_aq_debug_write_register(hw, 10445 I40E_VSI_TSR(vsi->vsi_id), 10446 reg, NULL); 10447 if (ret < 0) { 10448 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]", 10449 vsi->vsi_id); 10450 return I40E_ERR_CONFIG; 10451 } 10452 } 10453 10454 /* Configure for double VLAN TX insertion */ 10455 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id)); 10456 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) { 10457 reg = I40E_VSI_L2TAGSTXVALID_QINQ; 10458 ret = i40e_aq_debug_write_register(hw, 10459 I40E_VSI_L2TAGSTXVALID( 10460 vsi->vsi_id), reg, NULL); 10461 if (ret < 0) { 10462 PMD_DRV_LOG(ERR, 10463 "Failed to update VSI_L2TAGSTXVALID[%d]", 10464 vsi->vsi_id); 10465 return I40E_ERR_CONFIG; 10466 } 10467 } 10468 10469 return 0; 10470 } 10471 10472 /** 10473 * i40e_aq_add_mirror_rule 10474 * @hw: pointer to the hardware structure 10475 * @seid: VEB seid to add mirror rule to 10476 * @dst_id: destination vsi seid 10477 * @entries: Buffer which contains the entities to be mirrored 10478 * @count: number of entities contained in the buffer 10479 * @rule_id:the rule_id of the rule to be added 10480 * 10481 * Add a mirror rule for a given veb. 10482 * 10483 **/ 10484 static enum i40e_status_code 10485 i40e_aq_add_mirror_rule(struct i40e_hw *hw, 10486 uint16_t seid, uint16_t dst_id, 10487 uint16_t rule_type, uint16_t *entries, 10488 uint16_t count, uint16_t *rule_id) 10489 { 10490 struct i40e_aq_desc desc; 10491 struct i40e_aqc_add_delete_mirror_rule cmd; 10492 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 10493 (struct i40e_aqc_add_delete_mirror_rule_completion *) 10494 &desc.params.raw; 10495 uint16_t buff_len; 10496 enum i40e_status_code status; 10497 10498 i40e_fill_default_direct_cmd_desc(&desc, 10499 i40e_aqc_opc_add_mirror_rule); 10500 memset(&cmd, 0, sizeof(cmd)); 10501 10502 buff_len = sizeof(uint16_t) * count; 10503 desc.datalen = rte_cpu_to_le_16(buff_len); 10504 if (buff_len > 0) 10505 desc.flags |= rte_cpu_to_le_16( 10506 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 10507 cmd.rule_type = rte_cpu_to_le_16(rule_type << 10508 I40E_AQC_MIRROR_RULE_TYPE_SHIFT); 10509 cmd.num_entries = rte_cpu_to_le_16(count); 10510 cmd.seid = rte_cpu_to_le_16(seid); 10511 cmd.destination = rte_cpu_to_le_16(dst_id); 10512 10513 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd)); 10514 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL); 10515 PMD_DRV_LOG(INFO, 10516 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,", 10517 hw->aq.asq_last_status, resp->rule_id, 10518 resp->mirror_rules_used, resp->mirror_rules_free); 10519 *rule_id = rte_le_to_cpu_16(resp->rule_id); 10520 10521 return status; 10522 } 10523 10524 /** 10525 * i40e_aq_del_mirror_rule 10526 * @hw: pointer to the hardware structure 10527 * @seid: VEB seid to add mirror rule to 10528 * @entries: Buffer which contains the entities to be mirrored 10529 * @count: number of entities contained in the buffer 10530 * @rule_id:the rule_id of the rule to be delete 10531 * 10532 * Delete a mirror rule for a given veb. 10533 * 10534 **/ 10535 static enum i40e_status_code 10536 i40e_aq_del_mirror_rule(struct i40e_hw *hw, 10537 uint16_t seid, uint16_t rule_type, uint16_t *entries, 10538 uint16_t count, uint16_t rule_id) 10539 { 10540 struct i40e_aq_desc desc; 10541 struct i40e_aqc_add_delete_mirror_rule cmd; 10542 uint16_t buff_len = 0; 10543 enum i40e_status_code status; 10544 void *buff = NULL; 10545 10546 i40e_fill_default_direct_cmd_desc(&desc, 10547 i40e_aqc_opc_delete_mirror_rule); 10548 memset(&cmd, 0, sizeof(cmd)); 10549 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 10550 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF | 10551 I40E_AQ_FLAG_RD)); 10552 cmd.num_entries = count; 10553 buff_len = sizeof(uint16_t) * count; 10554 desc.datalen = rte_cpu_to_le_16(buff_len); 10555 buff = (void *)entries; 10556 } else 10557 /* rule id is filled in destination field for deleting mirror rule */ 10558 cmd.destination = rte_cpu_to_le_16(rule_id); 10559 10560 cmd.rule_type = rte_cpu_to_le_16(rule_type << 10561 I40E_AQC_MIRROR_RULE_TYPE_SHIFT); 10562 cmd.seid = rte_cpu_to_le_16(seid); 10563 10564 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd)); 10565 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL); 10566 10567 return status; 10568 } 10569 10570 /** 10571 * i40e_mirror_rule_set 10572 * @dev: pointer to the hardware structure 10573 * @mirror_conf: mirror rule info 10574 * @sw_id: mirror rule's sw_id 10575 * @on: enable/disable 10576 * 10577 * set a mirror rule. 10578 * 10579 **/ 10580 static int 10581 i40e_mirror_rule_set(struct rte_eth_dev *dev, 10582 struct rte_eth_mirror_conf *mirror_conf, 10583 uint8_t sw_id, uint8_t on) 10584 { 10585 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10586 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10587 struct i40e_mirror_rule *it, *mirr_rule = NULL; 10588 struct i40e_mirror_rule *parent = NULL; 10589 uint16_t seid, dst_seid, rule_id; 10590 uint16_t i, j = 0; 10591 int ret; 10592 10593 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id); 10594 10595 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) { 10596 PMD_DRV_LOG(ERR, 10597 "mirror rule can not be configured without veb or vfs."); 10598 return -ENOSYS; 10599 } 10600 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) { 10601 PMD_DRV_LOG(ERR, "mirror table is full."); 10602 return -ENOSPC; 10603 } 10604 if (mirror_conf->dst_pool > pf->vf_num) { 10605 PMD_DRV_LOG(ERR, "invalid destination pool %u.", 10606 mirror_conf->dst_pool); 10607 return -EINVAL; 10608 } 10609 10610 seid = pf->main_vsi->veb->seid; 10611 10612 TAILQ_FOREACH(it, &pf->mirror_list, rules) { 10613 if (sw_id <= it->index) { 10614 mirr_rule = it; 10615 break; 10616 } 10617 parent = it; 10618 } 10619 if (mirr_rule && sw_id == mirr_rule->index) { 10620 if (on) { 10621 PMD_DRV_LOG(ERR, "mirror rule exists."); 10622 return -EEXIST; 10623 } else { 10624 ret = i40e_aq_del_mirror_rule(hw, seid, 10625 mirr_rule->rule_type, 10626 mirr_rule->entries, 10627 mirr_rule->num_entries, mirr_rule->id); 10628 if (ret < 0) { 10629 PMD_DRV_LOG(ERR, 10630 "failed to remove mirror rule: ret = %d, aq_err = %d.", 10631 ret, hw->aq.asq_last_status); 10632 return -ENOSYS; 10633 } 10634 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules); 10635 rte_free(mirr_rule); 10636 pf->nb_mirror_rule--; 10637 return 0; 10638 } 10639 } else if (!on) { 10640 PMD_DRV_LOG(ERR, "mirror rule doesn't exist."); 10641 return -ENOENT; 10642 } 10643 10644 mirr_rule = rte_zmalloc("i40e_mirror_rule", 10645 sizeof(struct i40e_mirror_rule) , 0); 10646 if (!mirr_rule) { 10647 PMD_DRV_LOG(ERR, "failed to allocate memory"); 10648 return I40E_ERR_NO_MEMORY; 10649 } 10650 switch (mirror_conf->rule_type) { 10651 case ETH_MIRROR_VLAN: 10652 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) { 10653 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 10654 mirr_rule->entries[j] = 10655 mirror_conf->vlan.vlan_id[i]; 10656 j++; 10657 } 10658 } 10659 if (j == 0) { 10660 PMD_DRV_LOG(ERR, "vlan is not specified."); 10661 rte_free(mirr_rule); 10662 return -EINVAL; 10663 } 10664 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN; 10665 break; 10666 case ETH_MIRROR_VIRTUAL_POOL_UP: 10667 case ETH_MIRROR_VIRTUAL_POOL_DOWN: 10668 /* check if the specified pool bit is out of range */ 10669 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) { 10670 PMD_DRV_LOG(ERR, "pool mask is out of range."); 10671 rte_free(mirr_rule); 10672 return -EINVAL; 10673 } 10674 for (i = 0, j = 0; i < pf->vf_num; i++) { 10675 if (mirror_conf->pool_mask & (1ULL << i)) { 10676 mirr_rule->entries[j] = pf->vfs[i].vsi->seid; 10677 j++; 10678 } 10679 } 10680 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) { 10681 /* add pf vsi to entries */ 10682 mirr_rule->entries[j] = pf->main_vsi_seid; 10683 j++; 10684 } 10685 if (j == 0) { 10686 PMD_DRV_LOG(ERR, "pool is not specified."); 10687 rte_free(mirr_rule); 10688 return -EINVAL; 10689 } 10690 /* egress and ingress in aq commands means from switch but not port */ 10691 mirr_rule->rule_type = 10692 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ? 10693 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS : 10694 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS; 10695 break; 10696 case ETH_MIRROR_UPLINK_PORT: 10697 /* egress and ingress in aq commands means from switch but not port*/ 10698 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS; 10699 break; 10700 case ETH_MIRROR_DOWNLINK_PORT: 10701 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS; 10702 break; 10703 default: 10704 PMD_DRV_LOG(ERR, "unsupported mirror type %d.", 10705 mirror_conf->rule_type); 10706 rte_free(mirr_rule); 10707 return -EINVAL; 10708 } 10709 10710 /* If the dst_pool is equal to vf_num, consider it as PF */ 10711 if (mirror_conf->dst_pool == pf->vf_num) 10712 dst_seid = pf->main_vsi_seid; 10713 else 10714 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid; 10715 10716 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid, 10717 mirr_rule->rule_type, mirr_rule->entries, 10718 j, &rule_id); 10719 if (ret < 0) { 10720 PMD_DRV_LOG(ERR, 10721 "failed to add mirror rule: ret = %d, aq_err = %d.", 10722 ret, hw->aq.asq_last_status); 10723 rte_free(mirr_rule); 10724 return -ENOSYS; 10725 } 10726 10727 mirr_rule->index = sw_id; 10728 mirr_rule->num_entries = j; 10729 mirr_rule->id = rule_id; 10730 mirr_rule->dst_vsi_seid = dst_seid; 10731 10732 if (parent) 10733 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules); 10734 else 10735 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules); 10736 10737 pf->nb_mirror_rule++; 10738 return 0; 10739 } 10740 10741 /** 10742 * i40e_mirror_rule_reset 10743 * @dev: pointer to the device 10744 * @sw_id: mirror rule's sw_id 10745 * 10746 * reset a mirror rule. 10747 * 10748 **/ 10749 static int 10750 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id) 10751 { 10752 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10754 struct i40e_mirror_rule *it, *mirr_rule = NULL; 10755 uint16_t seid; 10756 int ret; 10757 10758 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id); 10759 10760 seid = pf->main_vsi->veb->seid; 10761 10762 TAILQ_FOREACH(it, &pf->mirror_list, rules) { 10763 if (sw_id == it->index) { 10764 mirr_rule = it; 10765 break; 10766 } 10767 } 10768 if (mirr_rule) { 10769 ret = i40e_aq_del_mirror_rule(hw, seid, 10770 mirr_rule->rule_type, 10771 mirr_rule->entries, 10772 mirr_rule->num_entries, mirr_rule->id); 10773 if (ret < 0) { 10774 PMD_DRV_LOG(ERR, 10775 "failed to remove mirror rule: status = %d, aq_err = %d.", 10776 ret, hw->aq.asq_last_status); 10777 return -ENOSYS; 10778 } 10779 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules); 10780 rte_free(mirr_rule); 10781 pf->nb_mirror_rule--; 10782 } else { 10783 PMD_DRV_LOG(ERR, "mirror rule doesn't exist."); 10784 return -ENOENT; 10785 } 10786 return 0; 10787 } 10788 10789 static uint64_t 10790 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev) 10791 { 10792 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10793 uint64_t systim_cycles; 10794 10795 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L); 10796 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H) 10797 << 32; 10798 10799 return systim_cycles; 10800 } 10801 10802 static uint64_t 10803 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index) 10804 { 10805 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10806 uint64_t rx_tstamp; 10807 10808 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index)); 10809 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index)) 10810 << 32; 10811 10812 return rx_tstamp; 10813 } 10814 10815 static uint64_t 10816 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 10817 { 10818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10819 uint64_t tx_tstamp; 10820 10821 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L); 10822 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H) 10823 << 32; 10824 10825 return tx_tstamp; 10826 } 10827 10828 static void 10829 i40e_start_timecounters(struct rte_eth_dev *dev) 10830 { 10831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10832 struct i40e_adapter *adapter = dev->data->dev_private; 10833 struct rte_eth_link link; 10834 uint32_t tsync_inc_l; 10835 uint32_t tsync_inc_h; 10836 10837 /* Get current link speed. */ 10838 i40e_dev_link_update(dev, 1); 10839 rte_eth_linkstatus_get(dev, &link); 10840 10841 switch (link.link_speed) { 10842 case ETH_SPEED_NUM_40G: 10843 case ETH_SPEED_NUM_25G: 10844 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF; 10845 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32; 10846 break; 10847 case ETH_SPEED_NUM_10G: 10848 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF; 10849 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32; 10850 break; 10851 case ETH_SPEED_NUM_1G: 10852 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF; 10853 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32; 10854 break; 10855 default: 10856 tsync_inc_l = 0x0; 10857 tsync_inc_h = 0x0; 10858 } 10859 10860 /* Set the timesync increment value. */ 10861 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l); 10862 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h); 10863 10864 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 10865 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 10866 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 10867 10868 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10869 adapter->systime_tc.cc_shift = 0; 10870 adapter->systime_tc.nsec_mask = 0; 10871 10872 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10873 adapter->rx_tstamp_tc.cc_shift = 0; 10874 adapter->rx_tstamp_tc.nsec_mask = 0; 10875 10876 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10877 adapter->tx_tstamp_tc.cc_shift = 0; 10878 adapter->tx_tstamp_tc.nsec_mask = 0; 10879 } 10880 10881 static int 10882 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 10883 { 10884 struct i40e_adapter *adapter = dev->data->dev_private; 10885 10886 adapter->systime_tc.nsec += delta; 10887 adapter->rx_tstamp_tc.nsec += delta; 10888 adapter->tx_tstamp_tc.nsec += delta; 10889 10890 return 0; 10891 } 10892 10893 static int 10894 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 10895 { 10896 uint64_t ns; 10897 struct i40e_adapter *adapter = dev->data->dev_private; 10898 10899 ns = rte_timespec_to_ns(ts); 10900 10901 /* Set the timecounters to a new value. */ 10902 adapter->systime_tc.nsec = ns; 10903 adapter->rx_tstamp_tc.nsec = ns; 10904 adapter->tx_tstamp_tc.nsec = ns; 10905 10906 return 0; 10907 } 10908 10909 static int 10910 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 10911 { 10912 uint64_t ns, systime_cycles; 10913 struct i40e_adapter *adapter = dev->data->dev_private; 10914 10915 systime_cycles = i40e_read_systime_cyclecounter(dev); 10916 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 10917 *ts = rte_ns_to_timespec(ns); 10918 10919 return 0; 10920 } 10921 10922 static int 10923 i40e_timesync_enable(struct rte_eth_dev *dev) 10924 { 10925 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10926 uint32_t tsync_ctl_l; 10927 uint32_t tsync_ctl_h; 10928 10929 /* Stop the timesync system time. */ 10930 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); 10931 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); 10932 /* Reset the timesync system time value. */ 10933 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0); 10934 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0); 10935 10936 i40e_start_timecounters(dev); 10937 10938 /* Clear timesync registers. */ 10939 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); 10940 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H); 10941 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0)); 10942 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1)); 10943 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2)); 10944 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3)); 10945 10946 /* Enable timestamping of PTP packets. */ 10947 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); 10948 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA; 10949 10950 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); 10951 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA; 10952 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE; 10953 10954 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); 10955 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); 10956 10957 return 0; 10958 } 10959 10960 static int 10961 i40e_timesync_disable(struct rte_eth_dev *dev) 10962 { 10963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10964 uint32_t tsync_ctl_l; 10965 uint32_t tsync_ctl_h; 10966 10967 /* Disable timestamping of transmitted PTP packets. */ 10968 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); 10969 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA; 10970 10971 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); 10972 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA; 10973 10974 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); 10975 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); 10976 10977 /* Reset the timesync increment value. */ 10978 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); 10979 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); 10980 10981 return 0; 10982 } 10983 10984 static int 10985 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 10986 struct timespec *timestamp, uint32_t flags) 10987 { 10988 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10989 struct i40e_adapter *adapter = dev->data->dev_private; 10990 uint32_t sync_status; 10991 uint32_t index = flags & 0x03; 10992 uint64_t rx_tstamp_cycles; 10993 uint64_t ns; 10994 10995 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1); 10996 if ((sync_status & (1 << index)) == 0) 10997 return -EINVAL; 10998 10999 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index); 11000 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 11001 *timestamp = rte_ns_to_timespec(ns); 11002 11003 return 0; 11004 } 11005 11006 static int 11007 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 11008 struct timespec *timestamp) 11009 { 11010 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11011 struct i40e_adapter *adapter = dev->data->dev_private; 11012 uint32_t sync_status; 11013 uint64_t tx_tstamp_cycles; 11014 uint64_t ns; 11015 11016 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); 11017 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0) 11018 return -EINVAL; 11019 11020 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev); 11021 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 11022 *timestamp = rte_ns_to_timespec(ns); 11023 11024 return 0; 11025 } 11026 11027 /* 11028 * i40e_parse_dcb_configure - parse dcb configure from user 11029 * @dev: the device being configured 11030 * @dcb_cfg: pointer of the result of parse 11031 * @*tc_map: bit map of enabled traffic classes 11032 * 11033 * Returns 0 on success, negative value on failure 11034 */ 11035 static int 11036 i40e_parse_dcb_configure(struct rte_eth_dev *dev, 11037 struct i40e_dcbx_config *dcb_cfg, 11038 uint8_t *tc_map) 11039 { 11040 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 11041 uint8_t i, tc_bw, bw_lf; 11042 11043 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config)); 11044 11045 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 11046 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) { 11047 PMD_INIT_LOG(ERR, "number of tc exceeds max."); 11048 return -EINVAL; 11049 } 11050 11051 /* assume each tc has the same bw */ 11052 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs; 11053 for (i = 0; i < dcb_rx_conf->nb_tcs; i++) 11054 dcb_cfg->etscfg.tcbwtable[i] = tc_bw; 11055 /* to ensure the sum of tcbw is equal to 100 */ 11056 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs; 11057 for (i = 0; i < bw_lf; i++) 11058 dcb_cfg->etscfg.tcbwtable[i]++; 11059 11060 /* assume each tc has the same Transmission Selection Algorithm */ 11061 for (i = 0; i < dcb_rx_conf->nb_tcs; i++) 11062 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS; 11063 11064 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11065 dcb_cfg->etscfg.prioritytable[i] = 11066 dcb_rx_conf->dcb_tc[i]; 11067 11068 /* FW needs one App to configure HW */ 11069 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM; 11070 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE; 11071 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO; 11072 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE; 11073 11074 if (dcb_rx_conf->nb_tcs == 0) 11075 *tc_map = 1; /* tc0 only */ 11076 else 11077 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t); 11078 11079 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) { 11080 dcb_cfg->pfc.willing = 0; 11081 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; 11082 dcb_cfg->pfc.pfcenable = *tc_map; 11083 } 11084 return 0; 11085 } 11086 11087 11088 static enum i40e_status_code 11089 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi, 11090 struct i40e_aqc_vsi_properties_data *info, 11091 uint8_t enabled_tcmap) 11092 { 11093 enum i40e_status_code ret; 11094 int i, total_tc = 0; 11095 uint16_t qpnum_per_tc, bsf, qp_idx; 11096 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi); 11097 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 11098 uint16_t used_queues; 11099 11100 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 11101 if (ret != I40E_SUCCESS) 11102 return ret; 11103 11104 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11105 if (enabled_tcmap & (1 << i)) 11106 total_tc++; 11107 } 11108 if (total_tc == 0) 11109 total_tc = 1; 11110 vsi->enabled_tc = enabled_tcmap; 11111 11112 /* different VSI has different queues assigned */ 11113 if (vsi->type == I40E_VSI_MAIN) 11114 used_queues = dev_data->nb_rx_queues - 11115 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 11116 else if (vsi->type == I40E_VSI_VMDQ2) 11117 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 11118 else { 11119 PMD_INIT_LOG(ERR, "unsupported VSI type."); 11120 return I40E_ERR_NO_AVAILABLE_VSI; 11121 } 11122 11123 qpnum_per_tc = used_queues / total_tc; 11124 /* Number of queues per enabled TC */ 11125 if (qpnum_per_tc == 0) { 11126 PMD_INIT_LOG(ERR, " number of queues is less that tcs."); 11127 return I40E_ERR_INVALID_QP_ID; 11128 } 11129 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc), 11130 I40E_MAX_Q_PER_TC); 11131 bsf = rte_bsf32(qpnum_per_tc); 11132 11133 /** 11134 * Configure TC and queue mapping parameters, for enabled TC, 11135 * allocate qpnum_per_tc queues to this traffic. For disabled TC, 11136 * default queue will serve it. 11137 */ 11138 qp_idx = 0; 11139 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11140 if (vsi->enabled_tc & (1 << i)) { 11141 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx << 11142 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 11143 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 11144 qp_idx += qpnum_per_tc; 11145 } else 11146 info->tc_mapping[i] = 0; 11147 } 11148 11149 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */ 11150 if (vsi->type == I40E_VSI_SRIOV) { 11151 info->mapping_flags |= 11152 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 11153 for (i = 0; i < vsi->nb_qps; i++) 11154 info->queue_mapping[i] = 11155 rte_cpu_to_le_16(vsi->base_queue + i); 11156 } else { 11157 info->mapping_flags |= 11158 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG); 11159 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 11160 } 11161 info->valid_sections |= 11162 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 11163 11164 return I40E_SUCCESS; 11165 } 11166 11167 /* 11168 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map 11169 * @veb: VEB to be configured 11170 * @tc_map: enabled TC bitmap 11171 * 11172 * Returns 0 on success, negative value on failure 11173 */ 11174 static enum i40e_status_code 11175 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map) 11176 { 11177 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw; 11178 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query; 11179 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query; 11180 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi); 11181 enum i40e_status_code ret = I40E_SUCCESS; 11182 int i; 11183 uint32_t bw_max; 11184 11185 /* Check if enabled_tc is same as existing or new TCs */ 11186 if (veb->enabled_tc == tc_map) 11187 return ret; 11188 11189 /* configure tc bandwidth */ 11190 memset(&veb_bw, 0, sizeof(veb_bw)); 11191 veb_bw.tc_valid_bits = tc_map; 11192 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 11193 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11194 if (tc_map & BIT_ULL(i)) 11195 veb_bw.tc_bw_share_credits[i] = 1; 11196 } 11197 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid, 11198 &veb_bw, NULL); 11199 if (ret) { 11200 PMD_INIT_LOG(ERR, 11201 "AQ command Config switch_comp BW allocation per TC failed = %d", 11202 hw->aq.asq_last_status); 11203 return ret; 11204 } 11205 11206 memset(&ets_query, 0, sizeof(ets_query)); 11207 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, 11208 &ets_query, NULL); 11209 if (ret != I40E_SUCCESS) { 11210 PMD_DRV_LOG(ERR, 11211 "Failed to get switch_comp ETS configuration %u", 11212 hw->aq.asq_last_status); 11213 return ret; 11214 } 11215 memset(&bw_query, 0, sizeof(bw_query)); 11216 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, 11217 &bw_query, NULL); 11218 if (ret != I40E_SUCCESS) { 11219 PMD_DRV_LOG(ERR, 11220 "Failed to get switch_comp bandwidth configuration %u", 11221 hw->aq.asq_last_status); 11222 return ret; 11223 } 11224 11225 /* store and print out BW info */ 11226 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit); 11227 veb->bw_info.bw_max = ets_query.tc_bw_max; 11228 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit); 11229 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max); 11230 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) | 11231 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) << 11232 I40E_16_BIT_WIDTH); 11233 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11234 veb->bw_info.bw_ets_share_credits[i] = 11235 bw_query.tc_bw_share_credits[i]; 11236 veb->bw_info.bw_ets_credits[i] = 11237 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]); 11238 /* 4 bits per TC, 4th bit is reserved */ 11239 veb->bw_info.bw_ets_max[i] = 11240 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) & 11241 RTE_LEN2MASK(3, uint8_t)); 11242 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i, 11243 veb->bw_info.bw_ets_share_credits[i]); 11244 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i, 11245 veb->bw_info.bw_ets_credits[i]); 11246 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i, 11247 veb->bw_info.bw_ets_max[i]); 11248 } 11249 11250 veb->enabled_tc = tc_map; 11251 11252 return ret; 11253 } 11254 11255 11256 /* 11257 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map 11258 * @vsi: VSI to be configured 11259 * @tc_map: enabled TC bitmap 11260 * 11261 * Returns 0 on success, negative value on failure 11262 */ 11263 static enum i40e_status_code 11264 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map) 11265 { 11266 struct i40e_aqc_configure_vsi_tc_bw_data bw_data; 11267 struct i40e_vsi_context ctxt; 11268 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 11269 enum i40e_status_code ret = I40E_SUCCESS; 11270 int i; 11271 11272 /* Check if enabled_tc is same as existing or new TCs */ 11273 if (vsi->enabled_tc == tc_map) 11274 return ret; 11275 11276 /* configure tc bandwidth */ 11277 memset(&bw_data, 0, sizeof(bw_data)); 11278 bw_data.tc_valid_bits = tc_map; 11279 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 11280 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11281 if (tc_map & BIT_ULL(i)) 11282 bw_data.tc_bw_credits[i] = 1; 11283 } 11284 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL); 11285 if (ret) { 11286 PMD_INIT_LOG(ERR, 11287 "AQ command Config VSI BW allocation per TC failed = %d", 11288 hw->aq.asq_last_status); 11289 goto out; 11290 } 11291 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 11292 vsi->info.qs_handle[i] = bw_data.qs_handles[i]; 11293 11294 /* Update Queue Pairs Mapping for currently enabled UPs */ 11295 ctxt.seid = vsi->seid; 11296 ctxt.pf_num = hw->pf_id; 11297 ctxt.vf_num = 0; 11298 ctxt.uplink_seid = vsi->uplink_seid; 11299 ctxt.info = vsi->info; 11300 i40e_get_cap(hw); 11301 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map); 11302 if (ret) 11303 goto out; 11304 11305 /* Update the VSI after updating the VSI queue-mapping information */ 11306 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 11307 if (ret) { 11308 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d", 11309 hw->aq.asq_last_status); 11310 goto out; 11311 } 11312 /* update the local VSI info with updated queue map */ 11313 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping, 11314 sizeof(vsi->info.tc_mapping)); 11315 rte_memcpy(&vsi->info.queue_mapping, 11316 &ctxt.info.queue_mapping, 11317 sizeof(vsi->info.queue_mapping)); 11318 vsi->info.mapping_flags = ctxt.info.mapping_flags; 11319 vsi->info.valid_sections = 0; 11320 11321 /* query and update current VSI BW information */ 11322 ret = i40e_vsi_get_bw_config(vsi); 11323 if (ret) { 11324 PMD_INIT_LOG(ERR, 11325 "Failed updating vsi bw info, err %s aq_err %s", 11326 i40e_stat_str(hw, ret), 11327 i40e_aq_str(hw, hw->aq.asq_last_status)); 11328 goto out; 11329 } 11330 11331 vsi->enabled_tc = tc_map; 11332 11333 out: 11334 return ret; 11335 } 11336 11337 /* 11338 * i40e_dcb_hw_configure - program the dcb setting to hw 11339 * @pf: pf the configuration is taken on 11340 * @new_cfg: new configuration 11341 * @tc_map: enabled TC bitmap 11342 * 11343 * Returns 0 on success, negative value on failure 11344 */ 11345 static enum i40e_status_code 11346 i40e_dcb_hw_configure(struct i40e_pf *pf, 11347 struct i40e_dcbx_config *new_cfg, 11348 uint8_t tc_map) 11349 { 11350 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 11351 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config; 11352 struct i40e_vsi *main_vsi = pf->main_vsi; 11353 struct i40e_vsi_list *vsi_list; 11354 enum i40e_status_code ret; 11355 int i; 11356 uint32_t val; 11357 11358 /* Use the FW API if FW > v4.4*/ 11359 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) || 11360 (hw->aq.fw_maj_ver >= 5))) { 11361 PMD_INIT_LOG(ERR, 11362 "FW < v4.4, can not use FW LLDP API to configure DCB"); 11363 return I40E_ERR_FIRMWARE_API_VERSION; 11364 } 11365 11366 /* Check if need reconfiguration */ 11367 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) { 11368 PMD_INIT_LOG(ERR, "No Change in DCB Config required."); 11369 return I40E_SUCCESS; 11370 } 11371 11372 /* Copy the new config to the current config */ 11373 *old_cfg = *new_cfg; 11374 old_cfg->etsrec = old_cfg->etscfg; 11375 ret = i40e_set_dcb_config(hw); 11376 if (ret) { 11377 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s", 11378 i40e_stat_str(hw, ret), 11379 i40e_aq_str(hw, hw->aq.asq_last_status)); 11380 return ret; 11381 } 11382 /* set receive Arbiter to RR mode and ETS scheme by default */ 11383 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) { 11384 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i)); 11385 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK | 11386 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK | 11387 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT); 11388 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] << 11389 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) & 11390 I40E_PRTDCB_RETSTCC_BWSHARE_MASK; 11391 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) & 11392 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK; 11393 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) & 11394 I40E_PRTDCB_RETSTCC_ETSTC_MASK; 11395 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val); 11396 } 11397 /* get local mib to check whether it is configured correctly */ 11398 /* IEEE mode */ 11399 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE; 11400 /* Get Local DCB Config */ 11401 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0, 11402 &hw->local_dcbx_config); 11403 11404 /* if Veb is created, need to update TC of it at first */ 11405 if (main_vsi->veb) { 11406 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map); 11407 if (ret) 11408 PMD_INIT_LOG(WARNING, 11409 "Failed configuring TC for VEB seid=%d", 11410 main_vsi->veb->seid); 11411 } 11412 /* Update each VSI */ 11413 i40e_vsi_config_tc(main_vsi, tc_map); 11414 if (main_vsi->veb) { 11415 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) { 11416 /* Beside main VSI and VMDQ VSIs, only enable default 11417 * TC for other VSIs 11418 */ 11419 if (vsi_list->vsi->type == I40E_VSI_VMDQ2) 11420 ret = i40e_vsi_config_tc(vsi_list->vsi, 11421 tc_map); 11422 else 11423 ret = i40e_vsi_config_tc(vsi_list->vsi, 11424 I40E_DEFAULT_TCMAP); 11425 if (ret) 11426 PMD_INIT_LOG(WARNING, 11427 "Failed configuring TC for VSI seid=%d", 11428 vsi_list->vsi->seid); 11429 /* continue */ 11430 } 11431 } 11432 return I40E_SUCCESS; 11433 } 11434 11435 /* 11436 * i40e_dcb_init_configure - initial dcb config 11437 * @dev: device being configured 11438 * @sw_dcb: indicate whether dcb is sw configured or hw offload 11439 * 11440 * Returns 0 on success, negative value on failure 11441 */ 11442 int 11443 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb) 11444 { 11445 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11446 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11447 int i, ret = 0; 11448 11449 if ((pf->flags & I40E_FLAG_DCB) == 0) { 11450 PMD_INIT_LOG(ERR, "HW doesn't support DCB"); 11451 return -ENOTSUP; 11452 } 11453 11454 /* DCB initialization: 11455 * Update DCB configuration from the Firmware and configure 11456 * LLDP MIB change event. 11457 */ 11458 if (sw_dcb == TRUE) { 11459 if (i40e_need_stop_lldp(dev)) { 11460 ret = i40e_aq_stop_lldp(hw, TRUE, NULL); 11461 if (ret != I40E_SUCCESS) 11462 PMD_INIT_LOG(DEBUG, "Failed to stop lldp"); 11463 } 11464 11465 ret = i40e_init_dcb(hw); 11466 /* If lldp agent is stopped, the return value from 11467 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM 11468 * adminq status. Otherwise, it should return success. 11469 */ 11470 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS && 11471 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) { 11472 memset(&hw->local_dcbx_config, 0, 11473 sizeof(struct i40e_dcbx_config)); 11474 /* set dcb default configuration */ 11475 hw->local_dcbx_config.etscfg.willing = 0; 11476 hw->local_dcbx_config.etscfg.maxtcs = 0; 11477 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100; 11478 hw->local_dcbx_config.etscfg.tsatable[0] = 11479 I40E_IEEE_TSA_ETS; 11480 /* all UPs mapping to TC0 */ 11481 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11482 hw->local_dcbx_config.etscfg.prioritytable[i] = 0; 11483 hw->local_dcbx_config.etsrec = 11484 hw->local_dcbx_config.etscfg; 11485 hw->local_dcbx_config.pfc.willing = 0; 11486 hw->local_dcbx_config.pfc.pfccap = 11487 I40E_MAX_TRAFFIC_CLASS; 11488 /* FW needs one App to configure HW */ 11489 hw->local_dcbx_config.numapps = 1; 11490 hw->local_dcbx_config.app[0].selector = 11491 I40E_APP_SEL_ETHTYPE; 11492 hw->local_dcbx_config.app[0].priority = 3; 11493 hw->local_dcbx_config.app[0].protocolid = 11494 I40E_APP_PROTOID_FCOE; 11495 ret = i40e_set_dcb_config(hw); 11496 if (ret) { 11497 PMD_INIT_LOG(ERR, 11498 "default dcb config fails. err = %d, aq_err = %d.", 11499 ret, hw->aq.asq_last_status); 11500 return -ENOSYS; 11501 } 11502 } else { 11503 PMD_INIT_LOG(ERR, 11504 "DCB initialization in FW fails, err = %d, aq_err = %d.", 11505 ret, hw->aq.asq_last_status); 11506 return -ENOTSUP; 11507 } 11508 } else { 11509 ret = i40e_aq_start_lldp(hw, NULL); 11510 if (ret != I40E_SUCCESS) 11511 PMD_INIT_LOG(DEBUG, "Failed to start lldp"); 11512 11513 ret = i40e_init_dcb(hw); 11514 if (!ret) { 11515 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) { 11516 PMD_INIT_LOG(ERR, 11517 "HW doesn't support DCBX offload."); 11518 return -ENOTSUP; 11519 } 11520 } else { 11521 PMD_INIT_LOG(ERR, 11522 "DCBX configuration failed, err = %d, aq_err = %d.", 11523 ret, hw->aq.asq_last_status); 11524 return -ENOTSUP; 11525 } 11526 } 11527 return 0; 11528 } 11529 11530 /* 11531 * i40e_dcb_setup - setup dcb related config 11532 * @dev: device being configured 11533 * 11534 * Returns 0 on success, negative value on failure 11535 */ 11536 static int 11537 i40e_dcb_setup(struct rte_eth_dev *dev) 11538 { 11539 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11540 struct i40e_dcbx_config dcb_cfg; 11541 uint8_t tc_map = 0; 11542 int ret = 0; 11543 11544 if ((pf->flags & I40E_FLAG_DCB) == 0) { 11545 PMD_INIT_LOG(ERR, "HW doesn't support DCB"); 11546 return -ENOTSUP; 11547 } 11548 11549 if (pf->vf_num != 0) 11550 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis."); 11551 11552 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map); 11553 if (ret) { 11554 PMD_INIT_LOG(ERR, "invalid dcb config"); 11555 return -EINVAL; 11556 } 11557 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map); 11558 if (ret) { 11559 PMD_INIT_LOG(ERR, "dcb sw configure fails"); 11560 return -ENOSYS; 11561 } 11562 11563 return 0; 11564 } 11565 11566 static int 11567 i40e_dev_get_dcb_info(struct rte_eth_dev *dev, 11568 struct rte_eth_dcb_info *dcb_info) 11569 { 11570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11572 struct i40e_vsi *vsi = pf->main_vsi; 11573 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config; 11574 uint16_t bsf, tc_mapping; 11575 int i, j = 0; 11576 11577 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 11578 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1); 11579 else 11580 dcb_info->nb_tcs = 1; 11581 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11582 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i]; 11583 for (i = 0; i < dcb_info->nb_tcs; i++) 11584 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i]; 11585 11586 /* get queue mapping if vmdq is disabled */ 11587 if (!pf->nb_cfg_vmdq_vsi) { 11588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11589 if (!(vsi->enabled_tc & (1 << i))) 11590 continue; 11591 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]); 11592 dcb_info->tc_queue.tc_rxq[j][i].base = 11593 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >> 11594 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT; 11595 dcb_info->tc_queue.tc_txq[j][i].base = 11596 dcb_info->tc_queue.tc_rxq[j][i].base; 11597 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >> 11598 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT; 11599 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf; 11600 dcb_info->tc_queue.tc_txq[j][i].nb_queue = 11601 dcb_info->tc_queue.tc_rxq[j][i].nb_queue; 11602 } 11603 return 0; 11604 } 11605 11606 /* get queue mapping if vmdq is enabled */ 11607 do { 11608 vsi = pf->vmdq[j].vsi; 11609 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11610 if (!(vsi->enabled_tc & (1 << i))) 11611 continue; 11612 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]); 11613 dcb_info->tc_queue.tc_rxq[j][i].base = 11614 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >> 11615 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT; 11616 dcb_info->tc_queue.tc_txq[j][i].base = 11617 dcb_info->tc_queue.tc_rxq[j][i].base; 11618 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >> 11619 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT; 11620 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf; 11621 dcb_info->tc_queue.tc_txq[j][i].nb_queue = 11622 dcb_info->tc_queue.tc_rxq[j][i].nb_queue; 11623 } 11624 j++; 11625 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL)); 11626 return 0; 11627 } 11628 11629 static int 11630 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 11631 { 11632 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 11633 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 11634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11635 uint16_t msix_intr; 11636 11637 msix_intr = intr_handle->intr_vec[queue_id]; 11638 if (msix_intr == I40E_MISC_VEC_ID) 11639 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 11640 I40E_PFINT_DYN_CTL0_INTENA_MASK | 11641 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 11642 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 11643 else 11644 I40E_WRITE_REG(hw, 11645 I40E_PFINT_DYN_CTLN(msix_intr - 11646 I40E_RX_VEC_START), 11647 I40E_PFINT_DYN_CTLN_INTENA_MASK | 11648 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 11649 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 11650 11651 I40E_WRITE_FLUSH(hw); 11652 rte_intr_ack(&pci_dev->intr_handle); 11653 11654 return 0; 11655 } 11656 11657 static int 11658 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 11659 { 11660 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 11661 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 11662 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11663 uint16_t msix_intr; 11664 11665 msix_intr = intr_handle->intr_vec[queue_id]; 11666 if (msix_intr == I40E_MISC_VEC_ID) 11667 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 11668 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 11669 else 11670 I40E_WRITE_REG(hw, 11671 I40E_PFINT_DYN_CTLN(msix_intr - 11672 I40E_RX_VEC_START), 11673 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 11674 I40E_WRITE_FLUSH(hw); 11675 11676 return 0; 11677 } 11678 11679 /** 11680 * This function is used to check if the register is valid. 11681 * Below is the valid registers list for X722 only: 11682 * 0x2b800--0x2bb00 11683 * 0x38700--0x38a00 11684 * 0x3d800--0x3db00 11685 * 0x208e00--0x209000 11686 * 0x20be00--0x20c000 11687 * 0x263c00--0x264000 11688 * 0x265c00--0x266000 11689 */ 11690 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset) 11691 { 11692 if ((type != I40E_MAC_X722) && 11693 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) || 11694 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) || 11695 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) || 11696 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) || 11697 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) || 11698 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) || 11699 (reg_offset >= 0x265c00 && reg_offset <= 0x266000))) 11700 return 0; 11701 else 11702 return 1; 11703 } 11704 11705 static int i40e_get_regs(struct rte_eth_dev *dev, 11706 struct rte_dev_reg_info *regs) 11707 { 11708 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11709 uint32_t *ptr_data = regs->data; 11710 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset; 11711 const struct i40e_reg_info *reg_info; 11712 11713 if (ptr_data == NULL) { 11714 regs->length = I40E_GLGEN_STAT_CLEAR + 4; 11715 regs->width = sizeof(uint32_t); 11716 return 0; 11717 } 11718 11719 /* The first few registers have to be read using AQ operations */ 11720 reg_idx = 0; 11721 while (i40e_regs_adminq[reg_idx].name) { 11722 reg_info = &i40e_regs_adminq[reg_idx++]; 11723 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++) 11724 for (arr_idx2 = 0; 11725 arr_idx2 <= reg_info->count2; 11726 arr_idx2++) { 11727 reg_offset = arr_idx * reg_info->stride1 + 11728 arr_idx2 * reg_info->stride2; 11729 reg_offset += reg_info->base_addr; 11730 ptr_data[reg_offset >> 2] = 11731 i40e_read_rx_ctl(hw, reg_offset); 11732 } 11733 } 11734 11735 /* The remaining registers can be read using primitives */ 11736 reg_idx = 0; 11737 while (i40e_regs_others[reg_idx].name) { 11738 reg_info = &i40e_regs_others[reg_idx++]; 11739 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++) 11740 for (arr_idx2 = 0; 11741 arr_idx2 <= reg_info->count2; 11742 arr_idx2++) { 11743 reg_offset = arr_idx * reg_info->stride1 + 11744 arr_idx2 * reg_info->stride2; 11745 reg_offset += reg_info->base_addr; 11746 if (!i40e_valid_regs(hw->mac.type, reg_offset)) 11747 ptr_data[reg_offset >> 2] = 0; 11748 else 11749 ptr_data[reg_offset >> 2] = 11750 I40E_READ_REG(hw, reg_offset); 11751 } 11752 } 11753 11754 return 0; 11755 } 11756 11757 static int i40e_get_eeprom_length(struct rte_eth_dev *dev) 11758 { 11759 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11760 11761 /* Convert word count to byte count */ 11762 return hw->nvm.sr_size << 1; 11763 } 11764 11765 static int i40e_get_eeprom(struct rte_eth_dev *dev, 11766 struct rte_dev_eeprom_info *eeprom) 11767 { 11768 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11769 uint16_t *data = eeprom->data; 11770 uint16_t offset, length, cnt_words; 11771 int ret_code; 11772 11773 offset = eeprom->offset >> 1; 11774 length = eeprom->length >> 1; 11775 cnt_words = length; 11776 11777 if (offset > hw->nvm.sr_size || 11778 offset + length > hw->nvm.sr_size) { 11779 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 11780 return -EINVAL; 11781 } 11782 11783 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 11784 11785 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data); 11786 if (ret_code != I40E_SUCCESS || cnt_words != length) { 11787 PMD_DRV_LOG(ERR, "EEPROM read failed."); 11788 return -EIO; 11789 } 11790 11791 return 0; 11792 } 11793 11794 static int i40e_get_module_info(struct rte_eth_dev *dev, 11795 struct rte_eth_dev_module_info *modinfo) 11796 { 11797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11798 uint32_t sff8472_comp = 0; 11799 uint32_t sff8472_swap = 0; 11800 uint32_t sff8636_rev = 0; 11801 i40e_status status; 11802 uint32_t type = 0; 11803 11804 /* Check if firmware supports reading module EEPROM. */ 11805 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) { 11806 PMD_DRV_LOG(ERR, 11807 "Module EEPROM memory read not supported. " 11808 "Please update the NVM image.\n"); 11809 return -EINVAL; 11810 } 11811 11812 status = i40e_update_link_info(hw); 11813 if (status) 11814 return -EIO; 11815 11816 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) { 11817 PMD_DRV_LOG(ERR, 11818 "Cannot read module EEPROM memory. " 11819 "No module connected.\n"); 11820 return -EINVAL; 11821 } 11822 11823 type = hw->phy.link_info.module_type[0]; 11824 11825 switch (type) { 11826 case I40E_MODULE_TYPE_SFP: 11827 status = i40e_aq_get_phy_register(hw, 11828 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11829 I40E_I2C_EEPROM_DEV_ADDR, 1, 11830 I40E_MODULE_SFF_8472_COMP, 11831 &sff8472_comp, NULL); 11832 if (status) 11833 return -EIO; 11834 11835 status = i40e_aq_get_phy_register(hw, 11836 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11837 I40E_I2C_EEPROM_DEV_ADDR, 1, 11838 I40E_MODULE_SFF_8472_SWAP, 11839 &sff8472_swap, NULL); 11840 if (status) 11841 return -EIO; 11842 11843 /* Check if the module requires address swap to access 11844 * the other EEPROM memory page. 11845 */ 11846 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) { 11847 PMD_DRV_LOG(WARNING, 11848 "Module address swap to access " 11849 "page 0xA2 is not supported.\n"); 11850 modinfo->type = RTE_ETH_MODULE_SFF_8079; 11851 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 11852 } else if (sff8472_comp == 0x00) { 11853 /* Module is not SFF-8472 compliant */ 11854 modinfo->type = RTE_ETH_MODULE_SFF_8079; 11855 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 11856 } else { 11857 modinfo->type = RTE_ETH_MODULE_SFF_8472; 11858 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 11859 } 11860 break; 11861 case I40E_MODULE_TYPE_QSFP_PLUS: 11862 /* Read from memory page 0. */ 11863 status = i40e_aq_get_phy_register(hw, 11864 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11865 0, 1, 11866 I40E_MODULE_REVISION_ADDR, 11867 &sff8636_rev, NULL); 11868 if (status) 11869 return -EIO; 11870 /* Determine revision compliance byte */ 11871 if (sff8636_rev > 0x02) { 11872 /* Module is SFF-8636 compliant */ 11873 modinfo->type = RTE_ETH_MODULE_SFF_8636; 11874 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11875 } else { 11876 modinfo->type = RTE_ETH_MODULE_SFF_8436; 11877 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11878 } 11879 break; 11880 case I40E_MODULE_TYPE_QSFP28: 11881 modinfo->type = RTE_ETH_MODULE_SFF_8636; 11882 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11883 break; 11884 default: 11885 PMD_DRV_LOG(ERR, "Module type unrecognized\n"); 11886 return -EINVAL; 11887 } 11888 return 0; 11889 } 11890 11891 static int i40e_get_module_eeprom(struct rte_eth_dev *dev, 11892 struct rte_dev_eeprom_info *info) 11893 { 11894 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11895 bool is_sfp = false; 11896 i40e_status status; 11897 uint8_t *data; 11898 uint32_t value = 0; 11899 uint32_t i; 11900 11901 if (!info || !info->length || !info->data) 11902 return -EINVAL; 11903 11904 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP) 11905 is_sfp = true; 11906 11907 data = info->data; 11908 for (i = 0; i < info->length; i++) { 11909 u32 offset = i + info->offset; 11910 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0; 11911 11912 /* Check if we need to access the other memory page */ 11913 if (is_sfp) { 11914 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) { 11915 offset -= RTE_ETH_MODULE_SFF_8079_LEN; 11916 addr = I40E_I2C_EEPROM_DEV_ADDR2; 11917 } 11918 } else { 11919 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) { 11920 /* Compute memory page number and offset. */ 11921 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2; 11922 addr++; 11923 } 11924 } 11925 status = i40e_aq_get_phy_register(hw, 11926 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11927 addr, offset, 1, &value, NULL); 11928 if (status) 11929 return -EIO; 11930 data[i] = (uint8_t)value; 11931 } 11932 return 0; 11933 } 11934 11935 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, 11936 struct rte_ether_addr *mac_addr) 11937 { 11938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11940 struct i40e_vsi *vsi = pf->main_vsi; 11941 struct i40e_mac_filter_info mac_filter; 11942 struct i40e_mac_filter *f; 11943 int ret; 11944 11945 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 11946 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 11947 return -EINVAL; 11948 } 11949 11950 TAILQ_FOREACH(f, &vsi->mac_list, next) { 11951 if (rte_is_same_ether_addr(&pf->dev_addr, 11952 &f->mac_info.mac_addr)) 11953 break; 11954 } 11955 11956 if (f == NULL) { 11957 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 11958 return -EIO; 11959 } 11960 11961 mac_filter = f->mac_info; 11962 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr); 11963 if (ret != I40E_SUCCESS) { 11964 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 11965 return -EIO; 11966 } 11967 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN); 11968 ret = i40e_vsi_add_mac(vsi, &mac_filter); 11969 if (ret != I40E_SUCCESS) { 11970 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 11971 return -EIO; 11972 } 11973 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN); 11974 11975 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL, 11976 mac_addr->addr_bytes, NULL); 11977 if (ret != I40E_SUCCESS) { 11978 PMD_DRV_LOG(ERR, "Failed to change mac"); 11979 return -EIO; 11980 } 11981 11982 return 0; 11983 } 11984 11985 static int 11986 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 11987 { 11988 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11989 struct rte_eth_dev_data *dev_data = pf->dev_data; 11990 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD; 11991 int ret = 0; 11992 11993 /* check if mtu is within the allowed range */ 11994 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX) 11995 return -EINVAL; 11996 11997 /* mtu setting is forbidden if port is start */ 11998 if (dev_data->dev_started) { 11999 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 12000 dev_data->port_id); 12001 return -EBUSY; 12002 } 12003 12004 if (frame_size > RTE_ETHER_MAX_LEN) 12005 dev_data->dev_conf.rxmode.offloads |= 12006 DEV_RX_OFFLOAD_JUMBO_FRAME; 12007 else 12008 dev_data->dev_conf.rxmode.offloads &= 12009 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 12010 12011 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 12012 12013 return ret; 12014 } 12015 12016 /* Restore ethertype filter */ 12017 static void 12018 i40e_ethertype_filter_restore(struct i40e_pf *pf) 12019 { 12020 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12021 struct i40e_ethertype_filter_list 12022 *ethertype_list = &pf->ethertype.ethertype_list; 12023 struct i40e_ethertype_filter *f; 12024 struct i40e_control_filter_stats stats; 12025 uint16_t flags; 12026 12027 TAILQ_FOREACH(f, ethertype_list, rules) { 12028 flags = 0; 12029 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC)) 12030 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 12031 if (f->flags & RTE_ETHTYPE_FLAGS_DROP) 12032 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 12033 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 12034 12035 memset(&stats, 0, sizeof(stats)); 12036 i40e_aq_add_rem_control_packet_filter(hw, 12037 f->input.mac_addr.addr_bytes, 12038 f->input.ether_type, 12039 flags, pf->main_vsi->seid, 12040 f->queue, 1, &stats, NULL); 12041 } 12042 PMD_DRV_LOG(INFO, "Ethertype filter:" 12043 " mac_etype_used = %u, etype_used = %u," 12044 " mac_etype_free = %u, etype_free = %u", 12045 stats.mac_etype_used, stats.etype_used, 12046 stats.mac_etype_free, stats.etype_free); 12047 } 12048 12049 /* Restore tunnel filter */ 12050 static void 12051 i40e_tunnel_filter_restore(struct i40e_pf *pf) 12052 { 12053 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12054 struct i40e_vsi *vsi; 12055 struct i40e_pf_vf *vf; 12056 struct i40e_tunnel_filter_list 12057 *tunnel_list = &pf->tunnel.tunnel_list; 12058 struct i40e_tunnel_filter *f; 12059 struct i40e_aqc_cloud_filters_element_bb cld_filter; 12060 bool big_buffer = 0; 12061 12062 TAILQ_FOREACH(f, tunnel_list, rules) { 12063 if (!f->is_to_vf) 12064 vsi = pf->main_vsi; 12065 else { 12066 vf = &pf->vfs[f->vf_id]; 12067 vsi = vf->vsi; 12068 } 12069 memset(&cld_filter, 0, sizeof(cld_filter)); 12070 rte_ether_addr_copy((struct rte_ether_addr *) 12071 &f->input.outer_mac, 12072 (struct rte_ether_addr *)&cld_filter.element.outer_mac); 12073 rte_ether_addr_copy((struct rte_ether_addr *) 12074 &f->input.inner_mac, 12075 (struct rte_ether_addr *)&cld_filter.element.inner_mac); 12076 cld_filter.element.inner_vlan = f->input.inner_vlan; 12077 cld_filter.element.flags = f->input.flags; 12078 cld_filter.element.tenant_id = f->input.tenant_id; 12079 cld_filter.element.queue_number = f->queue; 12080 rte_memcpy(cld_filter.general_fields, 12081 f->input.general_fields, 12082 sizeof(f->input.general_fields)); 12083 12084 if (((f->input.flags & 12085 I40E_AQC_ADD_CLOUD_FILTER_0X11) == 12086 I40E_AQC_ADD_CLOUD_FILTER_0X11) || 12087 ((f->input.flags & 12088 I40E_AQC_ADD_CLOUD_FILTER_0X12) == 12089 I40E_AQC_ADD_CLOUD_FILTER_0X12) || 12090 ((f->input.flags & 12091 I40E_AQC_ADD_CLOUD_FILTER_0X10) == 12092 I40E_AQC_ADD_CLOUD_FILTER_0X10)) 12093 big_buffer = 1; 12094 12095 if (big_buffer) 12096 i40e_aq_add_cloud_filters_bb(hw, 12097 vsi->seid, &cld_filter, 1); 12098 else 12099 i40e_aq_add_cloud_filters(hw, vsi->seid, 12100 &cld_filter.element, 1); 12101 } 12102 } 12103 12104 /* Restore rss filter */ 12105 static inline void 12106 i40e_rss_filter_restore(struct i40e_pf *pf) 12107 { 12108 struct i40e_rte_flow_rss_conf *conf = 12109 &pf->rss_info; 12110 if (conf->conf.queue_num) 12111 i40e_config_rss_filter(pf, conf, TRUE); 12112 } 12113 12114 static void 12115 i40e_filter_restore(struct i40e_pf *pf) 12116 { 12117 i40e_ethertype_filter_restore(pf); 12118 i40e_tunnel_filter_restore(pf); 12119 i40e_fdir_filter_restore(pf); 12120 i40e_rss_filter_restore(pf); 12121 } 12122 12123 bool 12124 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 12125 { 12126 if (strcmp(dev->device->driver->name, drv->driver.name)) 12127 return false; 12128 12129 return true; 12130 } 12131 12132 bool 12133 is_i40e_supported(struct rte_eth_dev *dev) 12134 { 12135 return is_device_supported(dev, &rte_i40e_pmd); 12136 } 12137 12138 struct i40e_customized_pctype* 12139 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index) 12140 { 12141 int i; 12142 12143 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) { 12144 if (pf->customized_pctype[i].index == index) 12145 return &pf->customized_pctype[i]; 12146 } 12147 return NULL; 12148 } 12149 12150 static int 12151 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg, 12152 uint32_t pkg_size, uint32_t proto_num, 12153 struct rte_pmd_i40e_proto_info *proto, 12154 enum rte_pmd_i40e_package_op op) 12155 { 12156 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12157 uint32_t pctype_num; 12158 struct rte_pmd_i40e_ptype_info *pctype; 12159 uint32_t buff_size; 12160 struct i40e_customized_pctype *new_pctype = NULL; 12161 uint8_t proto_id; 12162 uint8_t pctype_value; 12163 char name[64]; 12164 uint32_t i, j, n; 12165 int ret; 12166 12167 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12168 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12169 PMD_DRV_LOG(ERR, "Unsupported operation."); 12170 return -1; 12171 } 12172 12173 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12174 (uint8_t *)&pctype_num, sizeof(pctype_num), 12175 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM); 12176 if (ret) { 12177 PMD_DRV_LOG(ERR, "Failed to get pctype number"); 12178 return -1; 12179 } 12180 if (!pctype_num) { 12181 PMD_DRV_LOG(INFO, "No new pctype added"); 12182 return -1; 12183 } 12184 12185 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info); 12186 pctype = rte_zmalloc("new_pctype", buff_size, 0); 12187 if (!pctype) { 12188 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12189 return -1; 12190 } 12191 /* get information about new pctype list */ 12192 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12193 (uint8_t *)pctype, buff_size, 12194 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST); 12195 if (ret) { 12196 PMD_DRV_LOG(ERR, "Failed to get pctype list"); 12197 rte_free(pctype); 12198 return -1; 12199 } 12200 12201 /* Update customized pctype. */ 12202 for (i = 0; i < pctype_num; i++) { 12203 pctype_value = pctype[i].ptype_id; 12204 memset(name, 0, sizeof(name)); 12205 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) { 12206 proto_id = pctype[i].protocols[j]; 12207 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED) 12208 continue; 12209 for (n = 0; n < proto_num; n++) { 12210 if (proto[n].proto_id != proto_id) 12211 continue; 12212 strlcat(name, proto[n].name, sizeof(name)); 12213 strlcat(name, "_", sizeof(name)); 12214 break; 12215 } 12216 } 12217 name[strlen(name) - 1] = '\0'; 12218 if (!strcmp(name, "GTPC")) 12219 new_pctype = 12220 i40e_find_customized_pctype(pf, 12221 I40E_CUSTOMIZED_GTPC); 12222 else if (!strcmp(name, "GTPU_IPV4")) 12223 new_pctype = 12224 i40e_find_customized_pctype(pf, 12225 I40E_CUSTOMIZED_GTPU_IPV4); 12226 else if (!strcmp(name, "GTPU_IPV6")) 12227 new_pctype = 12228 i40e_find_customized_pctype(pf, 12229 I40E_CUSTOMIZED_GTPU_IPV6); 12230 else if (!strcmp(name, "GTPU")) 12231 new_pctype = 12232 i40e_find_customized_pctype(pf, 12233 I40E_CUSTOMIZED_GTPU); 12234 if (new_pctype) { 12235 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) { 12236 new_pctype->pctype = pctype_value; 12237 new_pctype->valid = true; 12238 } else { 12239 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID; 12240 new_pctype->valid = false; 12241 } 12242 } 12243 } 12244 12245 rte_free(pctype); 12246 return 0; 12247 } 12248 12249 static int 12250 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg, 12251 uint32_t pkg_size, uint32_t proto_num, 12252 struct rte_pmd_i40e_proto_info *proto, 12253 enum rte_pmd_i40e_package_op op) 12254 { 12255 struct rte_pmd_i40e_ptype_mapping *ptype_mapping; 12256 uint16_t port_id = dev->data->port_id; 12257 uint32_t ptype_num; 12258 struct rte_pmd_i40e_ptype_info *ptype; 12259 uint32_t buff_size; 12260 uint8_t proto_id; 12261 char name[RTE_PMD_I40E_DDP_NAME_SIZE]; 12262 uint32_t i, j, n; 12263 bool in_tunnel; 12264 int ret; 12265 12266 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12267 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12268 PMD_DRV_LOG(ERR, "Unsupported operation."); 12269 return -1; 12270 } 12271 12272 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) { 12273 rte_pmd_i40e_ptype_mapping_reset(port_id); 12274 return 0; 12275 } 12276 12277 /* get information about new ptype num */ 12278 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12279 (uint8_t *)&ptype_num, sizeof(ptype_num), 12280 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM); 12281 if (ret) { 12282 PMD_DRV_LOG(ERR, "Failed to get ptype number"); 12283 return ret; 12284 } 12285 if (!ptype_num) { 12286 PMD_DRV_LOG(INFO, "No new ptype added"); 12287 return -1; 12288 } 12289 12290 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info); 12291 ptype = rte_zmalloc("new_ptype", buff_size, 0); 12292 if (!ptype) { 12293 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12294 return -1; 12295 } 12296 12297 /* get information about new ptype list */ 12298 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12299 (uint8_t *)ptype, buff_size, 12300 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST); 12301 if (ret) { 12302 PMD_DRV_LOG(ERR, "Failed to get ptype list"); 12303 rte_free(ptype); 12304 return ret; 12305 } 12306 12307 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping); 12308 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0); 12309 if (!ptype_mapping) { 12310 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12311 rte_free(ptype); 12312 return -1; 12313 } 12314 12315 /* Update ptype mapping table. */ 12316 for (i = 0; i < ptype_num; i++) { 12317 ptype_mapping[i].hw_ptype = ptype[i].ptype_id; 12318 ptype_mapping[i].sw_ptype = 0; 12319 in_tunnel = false; 12320 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) { 12321 proto_id = ptype[i].protocols[j]; 12322 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED) 12323 continue; 12324 for (n = 0; n < proto_num; n++) { 12325 if (proto[n].proto_id != proto_id) 12326 continue; 12327 memset(name, 0, sizeof(name)); 12328 strcpy(name, proto[n].name); 12329 if (!strncasecmp(name, "PPPOE", 5)) 12330 ptype_mapping[i].sw_ptype |= 12331 RTE_PTYPE_L2_ETHER_PPPOE; 12332 else if (!strncasecmp(name, "IPV4FRAG", 8) && 12333 !in_tunnel) { 12334 ptype_mapping[i].sw_ptype |= 12335 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12336 ptype_mapping[i].sw_ptype |= 12337 RTE_PTYPE_L4_FRAG; 12338 } else if (!strncasecmp(name, "IPV4FRAG", 8) && 12339 in_tunnel) { 12340 ptype_mapping[i].sw_ptype |= 12341 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 12342 ptype_mapping[i].sw_ptype |= 12343 RTE_PTYPE_INNER_L4_FRAG; 12344 } else if (!strncasecmp(name, "OIPV4", 5)) { 12345 ptype_mapping[i].sw_ptype |= 12346 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12347 in_tunnel = true; 12348 } else if (!strncasecmp(name, "IPV4", 4) && 12349 !in_tunnel) 12350 ptype_mapping[i].sw_ptype |= 12351 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12352 else if (!strncasecmp(name, "IPV4", 4) && 12353 in_tunnel) 12354 ptype_mapping[i].sw_ptype |= 12355 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 12356 else if (!strncasecmp(name, "IPV6FRAG", 8) && 12357 !in_tunnel) { 12358 ptype_mapping[i].sw_ptype |= 12359 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12360 ptype_mapping[i].sw_ptype |= 12361 RTE_PTYPE_L4_FRAG; 12362 } else if (!strncasecmp(name, "IPV6FRAG", 8) && 12363 in_tunnel) { 12364 ptype_mapping[i].sw_ptype |= 12365 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 12366 ptype_mapping[i].sw_ptype |= 12367 RTE_PTYPE_INNER_L4_FRAG; 12368 } else if (!strncasecmp(name, "OIPV6", 5)) { 12369 ptype_mapping[i].sw_ptype |= 12370 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12371 in_tunnel = true; 12372 } else if (!strncasecmp(name, "IPV6", 4) && 12373 !in_tunnel) 12374 ptype_mapping[i].sw_ptype |= 12375 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12376 else if (!strncasecmp(name, "IPV6", 4) && 12377 in_tunnel) 12378 ptype_mapping[i].sw_ptype |= 12379 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 12380 else if (!strncasecmp(name, "UDP", 3) && 12381 !in_tunnel) 12382 ptype_mapping[i].sw_ptype |= 12383 RTE_PTYPE_L4_UDP; 12384 else if (!strncasecmp(name, "UDP", 3) && 12385 in_tunnel) 12386 ptype_mapping[i].sw_ptype |= 12387 RTE_PTYPE_INNER_L4_UDP; 12388 else if (!strncasecmp(name, "TCP", 3) && 12389 !in_tunnel) 12390 ptype_mapping[i].sw_ptype |= 12391 RTE_PTYPE_L4_TCP; 12392 else if (!strncasecmp(name, "TCP", 3) && 12393 in_tunnel) 12394 ptype_mapping[i].sw_ptype |= 12395 RTE_PTYPE_INNER_L4_TCP; 12396 else if (!strncasecmp(name, "SCTP", 4) && 12397 !in_tunnel) 12398 ptype_mapping[i].sw_ptype |= 12399 RTE_PTYPE_L4_SCTP; 12400 else if (!strncasecmp(name, "SCTP", 4) && 12401 in_tunnel) 12402 ptype_mapping[i].sw_ptype |= 12403 RTE_PTYPE_INNER_L4_SCTP; 12404 else if ((!strncasecmp(name, "ICMP", 4) || 12405 !strncasecmp(name, "ICMPV6", 6)) && 12406 !in_tunnel) 12407 ptype_mapping[i].sw_ptype |= 12408 RTE_PTYPE_L4_ICMP; 12409 else if ((!strncasecmp(name, "ICMP", 4) || 12410 !strncasecmp(name, "ICMPV6", 6)) && 12411 in_tunnel) 12412 ptype_mapping[i].sw_ptype |= 12413 RTE_PTYPE_INNER_L4_ICMP; 12414 else if (!strncasecmp(name, "GTPC", 4)) { 12415 ptype_mapping[i].sw_ptype |= 12416 RTE_PTYPE_TUNNEL_GTPC; 12417 in_tunnel = true; 12418 } else if (!strncasecmp(name, "GTPU", 4)) { 12419 ptype_mapping[i].sw_ptype |= 12420 RTE_PTYPE_TUNNEL_GTPU; 12421 in_tunnel = true; 12422 } else if (!strncasecmp(name, "GRENAT", 6)) { 12423 ptype_mapping[i].sw_ptype |= 12424 RTE_PTYPE_TUNNEL_GRENAT; 12425 in_tunnel = true; 12426 } else if (!strncasecmp(name, "L2TPV2CTL", 9) || 12427 !strncasecmp(name, "L2TPV2", 6)) { 12428 ptype_mapping[i].sw_ptype |= 12429 RTE_PTYPE_TUNNEL_L2TP; 12430 in_tunnel = true; 12431 } 12432 12433 break; 12434 } 12435 } 12436 } 12437 12438 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping, 12439 ptype_num, 0); 12440 if (ret) 12441 PMD_DRV_LOG(ERR, "Failed to update mapping table."); 12442 12443 rte_free(ptype_mapping); 12444 rte_free(ptype); 12445 return ret; 12446 } 12447 12448 void 12449 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 12450 uint32_t pkg_size, enum rte_pmd_i40e_package_op op) 12451 { 12452 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12453 uint32_t proto_num; 12454 struct rte_pmd_i40e_proto_info *proto; 12455 uint32_t buff_size; 12456 uint32_t i; 12457 int ret; 12458 12459 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12460 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12461 PMD_DRV_LOG(ERR, "Unsupported operation."); 12462 return; 12463 } 12464 12465 /* get information about protocol number */ 12466 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12467 (uint8_t *)&proto_num, sizeof(proto_num), 12468 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM); 12469 if (ret) { 12470 PMD_DRV_LOG(ERR, "Failed to get protocol number"); 12471 return; 12472 } 12473 if (!proto_num) { 12474 PMD_DRV_LOG(INFO, "No new protocol added"); 12475 return; 12476 } 12477 12478 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info); 12479 proto = rte_zmalloc("new_proto", buff_size, 0); 12480 if (!proto) { 12481 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12482 return; 12483 } 12484 12485 /* get information about protocol list */ 12486 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12487 (uint8_t *)proto, buff_size, 12488 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST); 12489 if (ret) { 12490 PMD_DRV_LOG(ERR, "Failed to get protocol list"); 12491 rte_free(proto); 12492 return; 12493 } 12494 12495 /* Check if GTP is supported. */ 12496 for (i = 0; i < proto_num; i++) { 12497 if (!strncmp(proto[i].name, "GTP", 3)) { 12498 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) 12499 pf->gtp_support = true; 12500 else 12501 pf->gtp_support = false; 12502 break; 12503 } 12504 } 12505 12506 /* Update customized pctype info */ 12507 ret = i40e_update_customized_pctype(dev, pkg, pkg_size, 12508 proto_num, proto, op); 12509 if (ret) 12510 PMD_DRV_LOG(INFO, "No pctype is updated."); 12511 12512 /* Update customized ptype info */ 12513 ret = i40e_update_customized_ptype(dev, pkg, pkg_size, 12514 proto_num, proto, op); 12515 if (ret) 12516 PMD_DRV_LOG(INFO, "No ptype is updated."); 12517 12518 rte_free(proto); 12519 } 12520 12521 /* Create a QinQ cloud filter 12522 * 12523 * The Fortville NIC has limited resources for tunnel filters, 12524 * so we can only reuse existing filters. 12525 * 12526 * In step 1 we define which Field Vector fields can be used for 12527 * filter types. 12528 * As we do not have the inner tag defined as a field, 12529 * we have to define it first, by reusing one of L1 entries. 12530 * 12531 * In step 2 we are replacing one of existing filter types with 12532 * a new one for QinQ. 12533 * As we reusing L1 and replacing L2, some of the default filter 12534 * types will disappear,which depends on L1 and L2 entries we reuse. 12535 * 12536 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b) 12537 * 12538 * 1. Create L1 filter of outer vlan (12b) which will be in use 12539 * later when we define the cloud filter. 12540 * a. Valid_flags.replace_cloud = 0 12541 * b. Old_filter = 10 (Stag_Inner_Vlan) 12542 * c. New_filter = 0x10 12543 * d. TR bit = 0xff (optional, not used here) 12544 * e. Buffer – 2 entries: 12545 * i. Byte 0 = 8 (outer vlan FV index). 12546 * Byte 1 = 0 (rsv) 12547 * Byte 2-3 = 0x0fff 12548 * ii. Byte 0 = 37 (inner vlan FV index). 12549 * Byte 1 =0 (rsv) 12550 * Byte 2-3 = 0x0fff 12551 * 12552 * Step 2: 12553 * 2. Create cloud filter using two L1 filters entries: stag and 12554 * new filter(outer vlan+ inner vlan) 12555 * a. Valid_flags.replace_cloud = 1 12556 * b. Old_filter = 1 (instead of outer IP) 12557 * c. New_filter = 0x10 12558 * d. Buffer – 2 entries: 12559 * i. Byte 0 = 0x80 | 7 (valid | Stag). 12560 * Byte 1-3 = 0 (rsv) 12561 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1) 12562 * Byte 9-11 = 0 (rsv) 12563 */ 12564 static int 12565 i40e_cloud_filter_qinq_create(struct i40e_pf *pf) 12566 { 12567 int ret = -ENOTSUP; 12568 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 12569 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 12570 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12571 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 12572 12573 if (pf->support_multi_driver) { 12574 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 12575 return ret; 12576 } 12577 12578 /* Init */ 12579 memset(&filter_replace, 0, 12580 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 12581 memset(&filter_replace_buf, 0, 12582 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 12583 12584 /* create L1 filter */ 12585 filter_replace.old_filter_type = 12586 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN; 12587 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12588 filter_replace.tr_bit = 0; 12589 12590 /* Prepare the buffer, 2 entries */ 12591 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN; 12592 filter_replace_buf.data[0] |= 12593 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12594 /* Field Vector 12b mask */ 12595 filter_replace_buf.data[2] = 0xff; 12596 filter_replace_buf.data[3] = 0x0f; 12597 filter_replace_buf.data[4] = 12598 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN; 12599 filter_replace_buf.data[4] |= 12600 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12601 /* Field Vector 12b mask */ 12602 filter_replace_buf.data[6] = 0xff; 12603 filter_replace_buf.data[7] = 0x0f; 12604 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, 12605 &filter_replace_buf); 12606 if (ret != I40E_SUCCESS) 12607 return ret; 12608 12609 if (filter_replace.old_filter_type != 12610 filter_replace.new_filter_type) 12611 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 12612 " original: 0x%x, new: 0x%x", 12613 dev->device->name, 12614 filter_replace.old_filter_type, 12615 filter_replace.new_filter_type); 12616 12617 /* Apply the second L2 cloud filter */ 12618 memset(&filter_replace, 0, 12619 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 12620 memset(&filter_replace_buf, 0, 12621 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 12622 12623 /* create L2 filter, input for L2 filter will be L1 filter */ 12624 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 12625 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP; 12626 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12627 12628 /* Prepare the buffer, 2 entries */ 12629 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 12630 filter_replace_buf.data[0] |= 12631 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12632 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12633 filter_replace_buf.data[4] |= 12634 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12635 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, 12636 &filter_replace_buf); 12637 if (!ret && (filter_replace.old_filter_type != 12638 filter_replace.new_filter_type)) 12639 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 12640 " original: 0x%x, new: 0x%x", 12641 dev->device->name, 12642 filter_replace.old_filter_type, 12643 filter_replace.new_filter_type); 12644 12645 return ret; 12646 } 12647 12648 int 12649 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, 12650 const struct rte_flow_action_rss *in) 12651 { 12652 if (in->key_len > RTE_DIM(out->key) || 12653 in->queue_num > RTE_DIM(out->queue)) 12654 return -EINVAL; 12655 if (!in->key && in->key_len) 12656 return -EINVAL; 12657 out->conf = (struct rte_flow_action_rss){ 12658 .func = in->func, 12659 .level = in->level, 12660 .types = in->types, 12661 .key_len = in->key_len, 12662 .queue_num = in->queue_num, 12663 .queue = memcpy(out->queue, in->queue, 12664 sizeof(*in->queue) * in->queue_num), 12665 }; 12666 if (in->key) 12667 out->conf.key = memcpy(out->key, in->key, in->key_len); 12668 return 0; 12669 } 12670 12671 int 12672 i40e_action_rss_same(const struct rte_flow_action_rss *comp, 12673 const struct rte_flow_action_rss *with) 12674 { 12675 return (comp->func == with->func && 12676 comp->level == with->level && 12677 comp->types == with->types && 12678 comp->key_len == with->key_len && 12679 comp->queue_num == with->queue_num && 12680 !memcmp(comp->key, with->key, with->key_len) && 12681 !memcmp(comp->queue, with->queue, 12682 sizeof(*with->queue) * with->queue_num)); 12683 } 12684 12685 int 12686 i40e_config_rss_filter(struct i40e_pf *pf, 12687 struct i40e_rte_flow_rss_conf *conf, bool add) 12688 { 12689 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12690 uint32_t i, lut = 0; 12691 uint16_t j, num; 12692 struct rte_eth_rss_conf rss_conf = { 12693 .rss_key = conf->conf.key_len ? 12694 (void *)(uintptr_t)conf->conf.key : NULL, 12695 .rss_key_len = conf->conf.key_len, 12696 .rss_hf = conf->conf.types, 12697 }; 12698 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 12699 12700 if (!add) { 12701 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) { 12702 i40e_pf_disable_rss(pf); 12703 memset(rss_info, 0, 12704 sizeof(struct i40e_rte_flow_rss_conf)); 12705 return 0; 12706 } 12707 return -EINVAL; 12708 } 12709 12710 /* If both VMDQ and RSS enabled, not all of PF queues are configured. 12711 * It's necessary to calculate the actual PF queues that are configured. 12712 */ 12713 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 12714 num = i40e_pf_calc_configured_queues_num(pf); 12715 else 12716 num = pf->dev_data->nb_rx_queues; 12717 12718 num = RTE_MIN(num, conf->conf.queue_num); 12719 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured", 12720 num); 12721 12722 if (num == 0) { 12723 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS"); 12724 return -ENOTSUP; 12725 } 12726 12727 /* Fill in redirection table */ 12728 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 12729 if (j == num) 12730 j = 0; 12731 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 << 12732 hw->func_caps.rss_table_entry_width) - 1)); 12733 if ((i & 3) == 3) 12734 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut); 12735 } 12736 12737 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) { 12738 i40e_pf_disable_rss(pf); 12739 return 0; 12740 } 12741 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < 12742 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 12743 /* Random default keys */ 12744 static uint32_t rss_key_default[] = {0x6b793944, 12745 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8, 12746 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605, 12747 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581}; 12748 12749 rss_conf.rss_key = (uint8_t *)rss_key_default; 12750 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 12751 sizeof(uint32_t); 12752 PMD_DRV_LOG(INFO, 12753 "No valid RSS key config for i40e, using default\n"); 12754 } 12755 12756 i40e_hw_rss_hash_set(pf, &rss_conf); 12757 12758 if (i40e_rss_conf_init(rss_info, &conf->conf)) 12759 return -EINVAL; 12760 12761 return 0; 12762 } 12763 12764 RTE_INIT(i40e_init_log) 12765 { 12766 i40e_logtype_init = rte_log_register("pmd.net.i40e.init"); 12767 if (i40e_logtype_init >= 0) 12768 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE); 12769 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver"); 12770 if (i40e_logtype_driver >= 0) 12771 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE); 12772 } 12773 12774 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, 12775 ETH_I40E_FLOATING_VEB_ARG "=1" 12776 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>" 12777 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16" 12778 ETH_I40E_SUPPORT_MULTI_DRIVER "=1" 12779 ETH_I40E_USE_LATEST_VEC "=0|1"); 12780