1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <unistd.h> 10 #include <stdarg.h> 11 #include <inttypes.h> 12 #include <assert.h> 13 14 #include <rte_common.h> 15 #include <rte_eal.h> 16 #include <rte_string_fns.h> 17 #include <rte_pci.h> 18 #include <rte_bus_pci.h> 19 #include <rte_ether.h> 20 #include <rte_ethdev_driver.h> 21 #include <rte_ethdev_pci.h> 22 #include <rte_memzone.h> 23 #include <rte_malloc.h> 24 #include <rte_memcpy.h> 25 #include <rte_alarm.h> 26 #include <rte_dev.h> 27 #include <rte_eth_ctrl.h> 28 #include <rte_tailq.h> 29 #include <rte_hash_crc.h> 30 31 #include "i40e_logs.h" 32 #include "base/i40e_prototype.h" 33 #include "base/i40e_adminq_cmd.h" 34 #include "base/i40e_type.h" 35 #include "base/i40e_register.h" 36 #include "base/i40e_dcb.h" 37 #include "i40e_ethdev.h" 38 #include "i40e_rxtx.h" 39 #include "i40e_pf.h" 40 #include "i40e_regs.h" 41 #include "rte_pmd_i40e.h" 42 43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" 44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" 45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" 46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" 47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" 48 49 #define I40E_CLEAR_PXE_WAIT_MS 200 50 51 /* Maximun number of capability elements */ 52 #define I40E_MAX_CAP_ELE_NUM 128 53 54 /* Wait count and interval */ 55 #define I40E_CHK_Q_ENA_COUNT 1000 56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000 57 58 /* Maximun number of VSI */ 59 #define I40E_MAX_NUM_VSIS (384UL) 60 61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */ 62 63 /* Flow control default timer */ 64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU 65 66 /* Flow control enable fwd bit */ 67 #define I40E_PRTMAC_FWD_CTRL 0x00000001 68 69 /* Receive Packet Buffer size */ 70 #define I40E_RXPBSIZE (968 * 1024) 71 72 /* Kilobytes shift */ 73 #define I40E_KILOSHIFT 10 74 75 /* Flow control default high water */ 76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT) 77 78 /* Flow control default low water */ 79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT) 80 81 /* Receive Average Packet Size in Byte*/ 82 #define I40E_PACKET_AVERAGE_SIZE 128 83 84 /* Mask of PF interrupt causes */ 85 #define I40E_PFINT_ICR0_ENA_MASK ( \ 86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \ 87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \ 88 I40E_PFINT_ICR0_ENA_GRST_MASK | \ 89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \ 90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \ 91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \ 92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \ 93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \ 94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK) 95 96 #define I40E_FLOW_TYPES ( \ 97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \ 98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ 99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ 100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ 101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ 102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \ 103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ 104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ 105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ 106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \ 107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD)) 108 109 /* Additional timesync values. */ 110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 113 #define I40E_PRTTSYN_TSYNENA 0x80000000 114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000 115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL 116 117 /** 118 * Below are values for writing un-exposed registers suggested 119 * by silicon experts 120 */ 121 /* Destination MAC address */ 122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL 123 /* Source MAC address */ 124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */ 126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */ 128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL 129 /* Single VLAN tag in the inner L2 header */ 130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL 131 /* Source IPv4 address */ 132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL 133 /* Destination IPv4 address */ 134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL 135 /* Source IPv4 address for X722 */ 136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL 137 /* Destination IPv4 address for X722 */ 138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL 139 /* IPv4 Protocol for X722 */ 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL 141 /* IPv4 Time to Live for X722 */ 142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL 143 /* IPv4 Type of Service (TOS) */ 144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL 145 /* IPv4 Protocol */ 146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL 147 /* IPv4 Time to Live */ 148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL 149 /* Source IPv6 address */ 150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL 151 /* Destination IPv6 address */ 152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL 153 /* IPv6 Traffic Class (TC) */ 154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL 155 /* IPv6 Next Header */ 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL 157 /* IPv6 Hop Limit */ 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL 159 /* Source L4 port */ 160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL 161 /* Destination L4 port */ 162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL 163 /* SCTP verification tag */ 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/ 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL 167 /* Source port of tunneling UDP */ 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL 169 /* Destination port of tunneling UDP */ 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL 171 /* UDP Tunneling ID, NVGRE/GRE key */ 172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL 173 /* Last ether type */ 174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL 175 /* Tunneling outer destination IPv4 address */ 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL 177 /* Tunneling outer destination IPv6 address */ 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL 179 /* 1st word of flex payload */ 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL 181 /* 2nd word of flex payload */ 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL 183 /* 3rd word of flex payload */ 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL 185 /* 4th word of flex payload */ 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL 187 /* 5th word of flex payload */ 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL 189 /* 6th word of flex payload */ 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL 191 /* 7th word of flex payload */ 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL 193 /* 8th word of flex payload */ 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL 195 /* all 8 words flex payload */ 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL 197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL 198 199 #define I40E_TRANSLATE_INSET 0 200 #define I40E_TRANSLATE_REG 1 201 202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL 203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL 204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL 205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL 208 209 /* PCI offset for querying capability */ 210 #define PCI_DEV_CAP_REG 0xA4 211 /* PCI offset for enabling/disabling Extended Tag */ 212 #define PCI_DEV_CTRL_REG 0xA8 213 /* Bit mask of Extended Tag capability */ 214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20 215 /* Bit shift of Extended Tag enable/disable */ 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 217 /* Bit mask of Extended Tag enable/disable */ 218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) 219 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); 222 static int i40e_dev_configure(struct rte_eth_dev *dev); 223 static int i40e_dev_start(struct rte_eth_dev *dev); 224 static void i40e_dev_stop(struct rte_eth_dev *dev); 225 static void i40e_dev_close(struct rte_eth_dev *dev); 226 static int i40e_dev_reset(struct rte_eth_dev *dev); 227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev); 228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev); 229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev); 230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev); 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev); 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev); 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev, 234 struct rte_eth_stats *stats); 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev, 236 struct rte_eth_xstat *xstats, unsigned n); 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev, 238 struct rte_eth_xstat_name *xstats_names, 239 unsigned limit); 240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev); 241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev, 242 uint16_t queue_id, 243 uint8_t stat_idx, 244 uint8_t is_rx); 245 static int i40e_fw_version_get(struct rte_eth_dev *dev, 246 char *fw_version, size_t fw_size); 247 static void i40e_dev_info_get(struct rte_eth_dev *dev, 248 struct rte_eth_dev_info *dev_info); 249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev, 250 uint16_t vlan_id, 251 int on); 252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev, 253 enum rte_vlan_type vlan_type, 254 uint16_t tpid); 255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask); 256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev, 257 uint16_t queue, 258 int on); 259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on); 260 static int i40e_dev_led_on(struct rte_eth_dev *dev); 261 static int i40e_dev_led_off(struct rte_eth_dev *dev); 262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev, 263 struct rte_eth_fc_conf *fc_conf); 264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev, 265 struct rte_eth_fc_conf *fc_conf); 266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev, 267 struct rte_eth_pfc_conf *pfc_conf); 268 static int i40e_macaddr_add(struct rte_eth_dev *dev, 269 struct ether_addr *mac_addr, 270 uint32_t index, 271 uint32_t pool); 272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev, 274 struct rte_eth_rss_reta_entry64 *reta_conf, 275 uint16_t reta_size); 276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev, 277 struct rte_eth_rss_reta_entry64 *reta_conf, 278 uint16_t reta_size); 279 280 static int i40e_get_cap(struct i40e_hw *hw); 281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev); 282 static int i40e_pf_setup(struct i40e_pf *pf); 283 static int i40e_dev_rxtx_init(struct i40e_pf *pf); 284 static int i40e_vmdq_setup(struct rte_eth_dev *dev); 285 static int i40e_dcb_setup(struct rte_eth_dev *dev); 286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg, 287 bool offset_loaded, uint64_t *offset, uint64_t *stat); 288 static void i40e_stat_update_48(struct i40e_hw *hw, 289 uint32_t hireg, 290 uint32_t loreg, 291 bool offset_loaded, 292 uint64_t *offset, 293 uint64_t *stat); 294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue); 295 static void i40e_dev_interrupt_handler(void *param); 296 static void i40e_dev_alarm_handler(void *param); 297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool, 298 uint32_t base, uint32_t num); 299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool); 300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool, 301 uint32_t base); 302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool, 303 uint16_t num); 304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev); 305 static int i40e_veb_release(struct i40e_veb *veb); 306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, 307 struct i40e_vsi *vsi); 308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf); 309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on); 310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi, 311 struct i40e_macvlan_filter *mv_f, 312 int num, 313 uint16_t vlan); 314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi); 315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev, 316 struct rte_eth_rss_conf *rss_conf); 317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 318 struct rte_eth_rss_conf *rss_conf); 319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 320 struct rte_eth_udp_tunnel *udp_tunnel); 321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 322 struct rte_eth_udp_tunnel *udp_tunnel); 323 static void i40e_filter_input_set_init(struct i40e_pf *pf); 324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev, 325 enum rte_filter_op filter_op, 326 void *arg); 327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, 328 enum rte_filter_type filter_type, 329 enum rte_filter_op filter_op, 330 void *arg); 331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, 332 struct rte_eth_dcb_info *dcb_info); 333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw); 334 static void i40e_configure_registers(struct i40e_hw *hw); 335 static void i40e_hw_init(struct rte_eth_dev *dev); 336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); 337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw, 338 uint16_t seid, 339 uint16_t rule_type, 340 uint16_t *entries, 341 uint16_t count, 342 uint16_t rule_id); 343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev, 344 struct rte_eth_mirror_conf *mirror_conf, 345 uint8_t sw_id, uint8_t on); 346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id); 347 348 static int i40e_timesync_enable(struct rte_eth_dev *dev); 349 static int i40e_timesync_disable(struct rte_eth_dev *dev); 350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 351 struct timespec *timestamp, 352 uint32_t flags); 353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 354 struct timespec *timestamp); 355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw); 356 357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 358 359 static int i40e_timesync_read_time(struct rte_eth_dev *dev, 360 struct timespec *timestamp); 361 static int i40e_timesync_write_time(struct rte_eth_dev *dev, 362 const struct timespec *timestamp); 363 364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 365 uint16_t queue_id); 366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 367 uint16_t queue_id); 368 369 static int i40e_get_regs(struct rte_eth_dev *dev, 370 struct rte_dev_reg_info *regs); 371 372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev); 373 374 static int i40e_get_eeprom(struct rte_eth_dev *dev, 375 struct rte_dev_eeprom_info *eeprom); 376 377 static int i40e_get_module_info(struct rte_eth_dev *dev, 378 struct rte_eth_dev_module_info *modinfo); 379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev, 380 struct rte_dev_eeprom_info *info); 381 382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, 383 struct ether_addr *mac_addr); 384 385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 386 387 static int i40e_ethertype_filter_convert( 388 const struct rte_eth_ethertype_filter *input, 389 struct i40e_ethertype_filter *filter); 390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf, 391 struct i40e_ethertype_filter *filter); 392 393 static int i40e_tunnel_filter_convert( 394 struct i40e_aqc_cloud_filters_element_bb *cld_filter, 395 struct i40e_tunnel_filter *tunnel_filter); 396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, 397 struct i40e_tunnel_filter *tunnel_filter); 398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf); 399 400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf); 401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf); 402 static void i40e_filter_restore(struct i40e_pf *pf); 403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev); 404 405 int i40e_logtype_init; 406 int i40e_logtype_driver; 407 408 static const char *const valid_keys[] = { 409 ETH_I40E_FLOATING_VEB_ARG, 410 ETH_I40E_FLOATING_VEB_LIST_ARG, 411 ETH_I40E_SUPPORT_MULTI_DRIVER, 412 ETH_I40E_QUEUE_NUM_PER_VF_ARG, 413 ETH_I40E_USE_LATEST_VEC, 414 NULL}; 415 416 static const struct rte_pci_id pci_id_i40e_map[] = { 417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) }, 418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) }, 419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) }, 420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) }, 421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) }, 422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) }, 423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) }, 424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) }, 425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) }, 426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) }, 427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) }, 428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) }, 429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) }, 430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) }, 431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) }, 432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) }, 433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) }, 434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) }, 435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) }, 436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) }, 437 { .vendor_id = 0, /* sentinel */ }, 438 }; 439 440 static const struct eth_dev_ops i40e_eth_dev_ops = { 441 .dev_configure = i40e_dev_configure, 442 .dev_start = i40e_dev_start, 443 .dev_stop = i40e_dev_stop, 444 .dev_close = i40e_dev_close, 445 .dev_reset = i40e_dev_reset, 446 .promiscuous_enable = i40e_dev_promiscuous_enable, 447 .promiscuous_disable = i40e_dev_promiscuous_disable, 448 .allmulticast_enable = i40e_dev_allmulticast_enable, 449 .allmulticast_disable = i40e_dev_allmulticast_disable, 450 .dev_set_link_up = i40e_dev_set_link_up, 451 .dev_set_link_down = i40e_dev_set_link_down, 452 .link_update = i40e_dev_link_update, 453 .stats_get = i40e_dev_stats_get, 454 .xstats_get = i40e_dev_xstats_get, 455 .xstats_get_names = i40e_dev_xstats_get_names, 456 .stats_reset = i40e_dev_stats_reset, 457 .xstats_reset = i40e_dev_stats_reset, 458 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set, 459 .fw_version_get = i40e_fw_version_get, 460 .dev_infos_get = i40e_dev_info_get, 461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get, 462 .vlan_filter_set = i40e_vlan_filter_set, 463 .vlan_tpid_set = i40e_vlan_tpid_set, 464 .vlan_offload_set = i40e_vlan_offload_set, 465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set, 466 .vlan_pvid_set = i40e_vlan_pvid_set, 467 .rx_queue_start = i40e_dev_rx_queue_start, 468 .rx_queue_stop = i40e_dev_rx_queue_stop, 469 .tx_queue_start = i40e_dev_tx_queue_start, 470 .tx_queue_stop = i40e_dev_tx_queue_stop, 471 .rx_queue_setup = i40e_dev_rx_queue_setup, 472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable, 473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable, 474 .rx_queue_release = i40e_dev_rx_queue_release, 475 .rx_queue_count = i40e_dev_rx_queue_count, 476 .rx_descriptor_done = i40e_dev_rx_descriptor_done, 477 .rx_descriptor_status = i40e_dev_rx_descriptor_status, 478 .tx_descriptor_status = i40e_dev_tx_descriptor_status, 479 .tx_queue_setup = i40e_dev_tx_queue_setup, 480 .tx_queue_release = i40e_dev_tx_queue_release, 481 .dev_led_on = i40e_dev_led_on, 482 .dev_led_off = i40e_dev_led_off, 483 .flow_ctrl_get = i40e_flow_ctrl_get, 484 .flow_ctrl_set = i40e_flow_ctrl_set, 485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set, 486 .mac_addr_add = i40e_macaddr_add, 487 .mac_addr_remove = i40e_macaddr_remove, 488 .reta_update = i40e_dev_rss_reta_update, 489 .reta_query = i40e_dev_rss_reta_query, 490 .rss_hash_update = i40e_dev_rss_hash_update, 491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get, 492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add, 493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del, 494 .filter_ctrl = i40e_dev_filter_ctrl, 495 .rxq_info_get = i40e_rxq_info_get, 496 .txq_info_get = i40e_txq_info_get, 497 .mirror_rule_set = i40e_mirror_rule_set, 498 .mirror_rule_reset = i40e_mirror_rule_reset, 499 .timesync_enable = i40e_timesync_enable, 500 .timesync_disable = i40e_timesync_disable, 501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp, 502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp, 503 .get_dcb_info = i40e_dev_get_dcb_info, 504 .timesync_adjust_time = i40e_timesync_adjust_time, 505 .timesync_read_time = i40e_timesync_read_time, 506 .timesync_write_time = i40e_timesync_write_time, 507 .get_reg = i40e_get_regs, 508 .get_eeprom_length = i40e_get_eeprom_length, 509 .get_eeprom = i40e_get_eeprom, 510 .get_module_info = i40e_get_module_info, 511 .get_module_eeprom = i40e_get_module_eeprom, 512 .mac_addr_set = i40e_set_default_mac_addr, 513 .mtu_set = i40e_dev_mtu_set, 514 .tm_ops_get = i40e_tm_ops_get, 515 }; 516 517 /* store statistics names and its offset in stats structure */ 518 struct rte_i40e_xstats_name_off { 519 char name[RTE_ETH_XSTATS_NAME_SIZE]; 520 unsigned offset; 521 }; 522 523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = { 524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)}, 525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)}, 526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)}, 527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)}, 528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats, 529 rx_unknown_protocol)}, 530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)}, 531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)}, 532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)}, 533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)}, 534 }; 535 536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \ 537 sizeof(rte_i40e_stats_strings[0])) 538 539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = { 540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats, 541 tx_dropped_link_down)}, 542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)}, 543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats, 544 illegal_bytes)}, 545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)}, 546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats, 547 mac_local_faults)}, 548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats, 549 mac_remote_faults)}, 550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats, 551 rx_length_errors)}, 552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)}, 553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)}, 554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)}, 555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)}, 556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)}, 557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats, 558 rx_size_127)}, 559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats, 560 rx_size_255)}, 561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats, 562 rx_size_511)}, 563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats, 564 rx_size_1023)}, 565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats, 566 rx_size_1522)}, 567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats, 568 rx_size_big)}, 569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats, 570 rx_undersize)}, 571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats, 572 rx_oversize)}, 573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats, 574 mac_short_packet_dropped)}, 575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats, 576 rx_fragments)}, 577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)}, 578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)}, 579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats, 580 tx_size_127)}, 581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats, 582 tx_size_255)}, 583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats, 584 tx_size_511)}, 585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats, 586 tx_size_1023)}, 587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats, 588 tx_size_1522)}, 589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats, 590 tx_size_big)}, 591 {"rx_flow_director_atr_match_packets", 592 offsetof(struct i40e_hw_port_stats, fd_atr_match)}, 593 {"rx_flow_director_sb_match_packets", 594 offsetof(struct i40e_hw_port_stats, fd_sb_match)}, 595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats, 596 tx_lpi_status)}, 597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats, 598 rx_lpi_status)}, 599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats, 600 tx_lpi_count)}, 601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats, 602 rx_lpi_count)}, 603 }; 604 605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \ 606 sizeof(rte_i40e_hw_port_strings[0])) 607 608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = { 609 {"xon_packets", offsetof(struct i40e_hw_port_stats, 610 priority_xon_rx)}, 611 {"xoff_packets", offsetof(struct i40e_hw_port_stats, 612 priority_xoff_rx)}, 613 }; 614 615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \ 616 sizeof(rte_i40e_rxq_prio_strings[0])) 617 618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = { 619 {"xon_packets", offsetof(struct i40e_hw_port_stats, 620 priority_xon_tx)}, 621 {"xoff_packets", offsetof(struct i40e_hw_port_stats, 622 priority_xoff_tx)}, 623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats, 624 priority_xon_2_xoff)}, 625 }; 626 627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \ 628 sizeof(rte_i40e_txq_prio_strings[0])) 629 630 static int 631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 632 struct rte_pci_device *pci_dev) 633 { 634 char name[RTE_ETH_NAME_MAX_LEN]; 635 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 636 int i, retval; 637 638 if (pci_dev->device.devargs) { 639 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 640 ð_da); 641 if (retval) 642 return retval; 643 } 644 645 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 646 sizeof(struct i40e_adapter), 647 eth_dev_pci_specific_init, pci_dev, 648 eth_i40e_dev_init, NULL); 649 650 if (retval || eth_da.nb_representor_ports < 1) 651 return retval; 652 653 /* probe VF representor ports */ 654 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated( 655 pci_dev->device.name); 656 657 if (pf_ethdev == NULL) 658 return -ENODEV; 659 660 for (i = 0; i < eth_da.nb_representor_ports; i++) { 661 struct i40e_vf_representor representor = { 662 .vf_id = eth_da.representor_ports[i], 663 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF( 664 pf_ethdev->data->dev_private)->switch_domain_id, 665 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER( 666 pf_ethdev->data->dev_private) 667 }; 668 669 /* representor port net_bdf_port */ 670 snprintf(name, sizeof(name), "net_%s_representor_%d", 671 pci_dev->device.name, eth_da.representor_ports[i]); 672 673 retval = rte_eth_dev_create(&pci_dev->device, name, 674 sizeof(struct i40e_vf_representor), NULL, NULL, 675 i40e_vf_representor_init, &representor); 676 677 if (retval) 678 PMD_DRV_LOG(ERR, "failed to create i40e vf " 679 "representor %s.", name); 680 } 681 682 return 0; 683 } 684 685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev) 686 { 687 struct rte_eth_dev *ethdev; 688 689 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 690 if (!ethdev) 691 return -ENODEV; 692 693 694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 695 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit); 696 else 697 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit); 698 } 699 700 static struct rte_pci_driver rte_i40e_pmd = { 701 .id_table = pci_id_i40e_map, 702 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 703 RTE_PCI_DRV_IOVA_AS_VA, 704 .probe = eth_i40e_pci_probe, 705 .remove = eth_i40e_pci_remove, 706 }; 707 708 static inline void 709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr, 710 uint32_t reg_val) 711 { 712 uint32_t ori_reg_val; 713 struct rte_eth_dev *dev; 714 715 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr); 716 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 717 i40e_write_rx_ctl(hw, reg_addr, reg_val); 718 if (ori_reg_val != reg_val) 719 PMD_DRV_LOG(WARNING, 720 "i40e device %s changed global register [0x%08x]." 721 " original: 0x%08x, new: 0x%08x", 722 dev->device->name, reg_addr, ori_reg_val, reg_val); 723 } 724 725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd); 726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map); 727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci"); 728 729 #ifndef I40E_GLQF_ORT 730 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) 731 #endif 732 #ifndef I40E_GLQF_PIT 733 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) 734 #endif 735 #ifndef I40E_GLQF_L3_MAP 736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4)) 737 #endif 738 739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) 740 { 741 /* 742 * Initialize registers for parsing packet type of QinQ 743 * This should be removed from code once proper 744 * configuration API is added to avoid configuration conflicts 745 * between ports of the same device. 746 */ 747 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029); 748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420); 749 } 750 751 static inline void i40e_config_automask(struct i40e_pf *pf) 752 { 753 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 754 uint32_t val; 755 756 /* INTENA flag is not auto-cleared for interrupt */ 757 val = I40E_READ_REG(hw, I40E_GLINT_CTL); 758 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK | 759 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK; 760 761 /* If support multi-driver, PF will use INT0. */ 762 if (!pf->support_multi_driver) 763 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK; 764 765 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val); 766 } 767 768 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808 769 770 /* 771 * Add a ethertype filter to drop all flow control frames transmitted 772 * from VSIs. 773 */ 774 static void 775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf) 776 { 777 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 778 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 779 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 781 int ret; 782 783 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL, 784 I40E_FLOW_CONTROL_ETHERTYPE, flags, 785 pf->main_vsi_seid, 0, 786 TRUE, NULL, NULL); 787 if (ret) 788 PMD_INIT_LOG(ERR, 789 "Failed to add filter to drop flow control frames from VSIs."); 790 } 791 792 static int 793 floating_veb_list_handler(__rte_unused const char *key, 794 const char *floating_veb_value, 795 void *opaque) 796 { 797 int idx = 0; 798 unsigned int count = 0; 799 char *end = NULL; 800 int min, max; 801 bool *vf_floating_veb = opaque; 802 803 while (isblank(*floating_veb_value)) 804 floating_veb_value++; 805 806 /* Reset floating VEB configuration for VFs */ 807 for (idx = 0; idx < I40E_MAX_VF; idx++) 808 vf_floating_veb[idx] = false; 809 810 min = I40E_MAX_VF; 811 do { 812 while (isblank(*floating_veb_value)) 813 floating_veb_value++; 814 if (*floating_veb_value == '\0') 815 return -1; 816 errno = 0; 817 idx = strtoul(floating_veb_value, &end, 10); 818 if (errno || end == NULL) 819 return -1; 820 while (isblank(*end)) 821 end++; 822 if (*end == '-') { 823 min = idx; 824 } else if ((*end == ';') || (*end == '\0')) { 825 max = idx; 826 if (min == I40E_MAX_VF) 827 min = idx; 828 if (max >= I40E_MAX_VF) 829 max = I40E_MAX_VF - 1; 830 for (idx = min; idx <= max; idx++) { 831 vf_floating_veb[idx] = true; 832 count++; 833 } 834 min = I40E_MAX_VF; 835 } else { 836 return -1; 837 } 838 floating_veb_value = end + 1; 839 } while (*end != '\0'); 840 841 if (count == 0) 842 return -1; 843 844 return 0; 845 } 846 847 static void 848 config_vf_floating_veb(struct rte_devargs *devargs, 849 uint16_t floating_veb, 850 bool *vf_floating_veb) 851 { 852 struct rte_kvargs *kvlist; 853 int i; 854 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG; 855 856 if (!floating_veb) 857 return; 858 /* All the VFs attach to the floating VEB by default 859 * when the floating VEB is enabled. 860 */ 861 for (i = 0; i < I40E_MAX_VF; i++) 862 vf_floating_veb[i] = true; 863 864 if (devargs == NULL) 865 return; 866 867 kvlist = rte_kvargs_parse(devargs->args, valid_keys); 868 if (kvlist == NULL) 869 return; 870 871 if (!rte_kvargs_count(kvlist, floating_veb_list)) { 872 rte_kvargs_free(kvlist); 873 return; 874 } 875 /* When the floating_veb_list parameter exists, all the VFs 876 * will attach to the legacy VEB firstly, then configure VFs 877 * to the floating VEB according to the floating_veb_list. 878 */ 879 if (rte_kvargs_process(kvlist, floating_veb_list, 880 floating_veb_list_handler, 881 vf_floating_veb) < 0) { 882 rte_kvargs_free(kvlist); 883 return; 884 } 885 rte_kvargs_free(kvlist); 886 } 887 888 static int 889 i40e_check_floating_handler(__rte_unused const char *key, 890 const char *value, 891 __rte_unused void *opaque) 892 { 893 if (strcmp(value, "1")) 894 return -1; 895 896 return 0; 897 } 898 899 static int 900 is_floating_veb_supported(struct rte_devargs *devargs) 901 { 902 struct rte_kvargs *kvlist; 903 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG; 904 905 if (devargs == NULL) 906 return 0; 907 908 kvlist = rte_kvargs_parse(devargs->args, valid_keys); 909 if (kvlist == NULL) 910 return 0; 911 912 if (!rte_kvargs_count(kvlist, floating_veb_key)) { 913 rte_kvargs_free(kvlist); 914 return 0; 915 } 916 /* Floating VEB is enabled when there's key-value: 917 * enable_floating_veb=1 918 */ 919 if (rte_kvargs_process(kvlist, floating_veb_key, 920 i40e_check_floating_handler, NULL) < 0) { 921 rte_kvargs_free(kvlist); 922 return 0; 923 } 924 rte_kvargs_free(kvlist); 925 926 return 1; 927 } 928 929 static void 930 config_floating_veb(struct rte_eth_dev *dev) 931 { 932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 935 936 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list)); 937 938 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) { 939 pf->floating_veb = 940 is_floating_veb_supported(pci_dev->device.devargs); 941 config_vf_floating_veb(pci_dev->device.devargs, 942 pf->floating_veb, 943 pf->floating_veb_list); 944 } else { 945 pf->floating_veb = false; 946 } 947 } 948 949 #define I40E_L2_TAGS_S_TAG_SHIFT 1 950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT) 951 952 static int 953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev) 954 { 955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 956 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 957 char ethertype_hash_name[RTE_HASH_NAMESIZE]; 958 int ret; 959 960 struct rte_hash_parameters ethertype_hash_params = { 961 .name = ethertype_hash_name, 962 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM, 963 .key_len = sizeof(struct i40e_ethertype_filter_input), 964 .hash_func = rte_hash_crc, 965 .hash_func_init_val = 0, 966 .socket_id = rte_socket_id(), 967 }; 968 969 /* Initialize ethertype filter rule list and hash */ 970 TAILQ_INIT(ðertype_rule->ethertype_list); 971 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE, 972 "ethertype_%s", dev->device->name); 973 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params); 974 if (!ethertype_rule->hash_table) { 975 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!"); 976 return -EINVAL; 977 } 978 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map", 979 sizeof(struct i40e_ethertype_filter *) * 980 I40E_MAX_ETHERTYPE_FILTER_NUM, 981 0); 982 if (!ethertype_rule->hash_map) { 983 PMD_INIT_LOG(ERR, 984 "Failed to allocate memory for ethertype hash map!"); 985 ret = -ENOMEM; 986 goto err_ethertype_hash_map_alloc; 987 } 988 989 return 0; 990 991 err_ethertype_hash_map_alloc: 992 rte_hash_free(ethertype_rule->hash_table); 993 994 return ret; 995 } 996 997 static int 998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev) 999 { 1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1001 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 1002 char tunnel_hash_name[RTE_HASH_NAMESIZE]; 1003 int ret; 1004 1005 struct rte_hash_parameters tunnel_hash_params = { 1006 .name = tunnel_hash_name, 1007 .entries = I40E_MAX_TUNNEL_FILTER_NUM, 1008 .key_len = sizeof(struct i40e_tunnel_filter_input), 1009 .hash_func = rte_hash_crc, 1010 .hash_func_init_val = 0, 1011 .socket_id = rte_socket_id(), 1012 }; 1013 1014 /* Initialize tunnel filter rule list and hash */ 1015 TAILQ_INIT(&tunnel_rule->tunnel_list); 1016 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE, 1017 "tunnel_%s", dev->device->name); 1018 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params); 1019 if (!tunnel_rule->hash_table) { 1020 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!"); 1021 return -EINVAL; 1022 } 1023 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map", 1024 sizeof(struct i40e_tunnel_filter *) * 1025 I40E_MAX_TUNNEL_FILTER_NUM, 1026 0); 1027 if (!tunnel_rule->hash_map) { 1028 PMD_INIT_LOG(ERR, 1029 "Failed to allocate memory for tunnel hash map!"); 1030 ret = -ENOMEM; 1031 goto err_tunnel_hash_map_alloc; 1032 } 1033 1034 return 0; 1035 1036 err_tunnel_hash_map_alloc: 1037 rte_hash_free(tunnel_rule->hash_table); 1038 1039 return ret; 1040 } 1041 1042 static int 1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev) 1044 { 1045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1046 struct i40e_fdir_info *fdir_info = &pf->fdir; 1047 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1048 int ret; 1049 1050 struct rte_hash_parameters fdir_hash_params = { 1051 .name = fdir_hash_name, 1052 .entries = I40E_MAX_FDIR_FILTER_NUM, 1053 .key_len = sizeof(struct i40e_fdir_input), 1054 .hash_func = rte_hash_crc, 1055 .hash_func_init_val = 0, 1056 .socket_id = rte_socket_id(), 1057 }; 1058 1059 /* Initialize flow director filter rule list and hash */ 1060 TAILQ_INIT(&fdir_info->fdir_list); 1061 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1062 "fdir_%s", dev->device->name); 1063 fdir_info->hash_table = rte_hash_create(&fdir_hash_params); 1064 if (!fdir_info->hash_table) { 1065 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1066 return -EINVAL; 1067 } 1068 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map", 1069 sizeof(struct i40e_fdir_filter *) * 1070 I40E_MAX_FDIR_FILTER_NUM, 1071 0); 1072 if (!fdir_info->hash_map) { 1073 PMD_INIT_LOG(ERR, 1074 "Failed to allocate memory for fdir hash map!"); 1075 ret = -ENOMEM; 1076 goto err_fdir_hash_map_alloc; 1077 } 1078 return 0; 1079 1080 err_fdir_hash_map_alloc: 1081 rte_hash_free(fdir_info->hash_table); 1082 1083 return ret; 1084 } 1085 1086 static void 1087 i40e_init_customized_info(struct i40e_pf *pf) 1088 { 1089 int i; 1090 1091 /* Initialize customized pctype */ 1092 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) { 1093 pf->customized_pctype[i].index = i; 1094 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID; 1095 pf->customized_pctype[i].valid = false; 1096 } 1097 1098 pf->gtp_support = false; 1099 } 1100 1101 void 1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev) 1103 { 1104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1106 struct i40e_queue_regions *info = &pf->queue_region; 1107 uint16_t i; 1108 1109 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++) 1110 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0); 1111 1112 memset(info, 0, sizeof(struct i40e_queue_regions)); 1113 } 1114 1115 static int 1116 i40e_parse_multi_drv_handler(__rte_unused const char *key, 1117 const char *value, 1118 void *opaque) 1119 { 1120 struct i40e_pf *pf; 1121 unsigned long support_multi_driver; 1122 char *end; 1123 1124 pf = (struct i40e_pf *)opaque; 1125 1126 errno = 0; 1127 support_multi_driver = strtoul(value, &end, 10); 1128 if (errno != 0 || end == value || *end != 0) { 1129 PMD_DRV_LOG(WARNING, "Wrong global configuration"); 1130 return -(EINVAL); 1131 } 1132 1133 if (support_multi_driver == 1 || support_multi_driver == 0) 1134 pf->support_multi_driver = (bool)support_multi_driver; 1135 else 1136 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,", 1137 "enable global configuration by default." 1138 ETH_I40E_SUPPORT_MULTI_DRIVER); 1139 return 0; 1140 } 1141 1142 static int 1143 i40e_support_multi_driver(struct rte_eth_dev *dev) 1144 { 1145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1146 struct rte_kvargs *kvlist; 1147 int kvargs_count; 1148 1149 /* Enable global configuration by default */ 1150 pf->support_multi_driver = false; 1151 1152 if (!dev->device->devargs) 1153 return 0; 1154 1155 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1156 if (!kvlist) 1157 return -EINVAL; 1158 1159 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER); 1160 if (!kvargs_count) { 1161 rte_kvargs_free(kvlist); 1162 return 0; 1163 } 1164 1165 if (kvargs_count > 1) 1166 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 1167 "the first invalid or last valid one is used !", 1168 ETH_I40E_SUPPORT_MULTI_DRIVER); 1169 1170 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER, 1171 i40e_parse_multi_drv_handler, pf) < 0) { 1172 rte_kvargs_free(kvlist); 1173 return -EINVAL; 1174 } 1175 1176 rte_kvargs_free(kvlist); 1177 return 0; 1178 } 1179 1180 static int 1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw, 1182 uint32_t reg_addr, uint64_t reg_val, 1183 struct i40e_asq_cmd_details *cmd_details) 1184 { 1185 uint64_t ori_reg_val; 1186 struct rte_eth_dev *dev; 1187 int ret; 1188 1189 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL); 1190 if (ret != I40E_SUCCESS) { 1191 PMD_DRV_LOG(ERR, 1192 "Fail to debug read from 0x%08x", 1193 reg_addr); 1194 return -EIO; 1195 } 1196 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 1197 1198 if (ori_reg_val != reg_val) 1199 PMD_DRV_LOG(WARNING, 1200 "i40e device %s changed global register [0x%08x]." 1201 " original: 0x%"PRIx64", after: 0x%"PRIx64, 1202 dev->device->name, reg_addr, ori_reg_val, reg_val); 1203 1204 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details); 1205 } 1206 1207 static int 1208 i40e_parse_latest_vec_handler(__rte_unused const char *key, 1209 const char *value, 1210 void *opaque) 1211 { 1212 struct i40e_adapter *ad; 1213 int use_latest_vec; 1214 1215 ad = (struct i40e_adapter *)opaque; 1216 1217 use_latest_vec = atoi(value); 1218 1219 if (use_latest_vec != 0 && use_latest_vec != 1) 1220 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!"); 1221 1222 ad->use_latest_vec = (uint8_t)use_latest_vec; 1223 1224 return 0; 1225 } 1226 1227 static int 1228 i40e_use_latest_vec(struct rte_eth_dev *dev) 1229 { 1230 struct i40e_adapter *ad = 1231 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1232 struct rte_kvargs *kvlist; 1233 int kvargs_count; 1234 1235 ad->use_latest_vec = false; 1236 1237 if (!dev->device->devargs) 1238 return 0; 1239 1240 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1241 if (!kvlist) 1242 return -EINVAL; 1243 1244 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC); 1245 if (!kvargs_count) { 1246 rte_kvargs_free(kvlist); 1247 return 0; 1248 } 1249 1250 if (kvargs_count > 1) 1251 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 1252 "the first invalid or last valid one is used !", 1253 ETH_I40E_USE_LATEST_VEC); 1254 1255 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC, 1256 i40e_parse_latest_vec_handler, ad) < 0) { 1257 rte_kvargs_free(kvlist); 1258 return -EINVAL; 1259 } 1260 1261 rte_kvargs_free(kvlist); 1262 return 0; 1263 } 1264 1265 #define I40E_ALARM_INTERVAL 50000 /* us */ 1266 1267 static int 1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) 1269 { 1270 struct rte_pci_device *pci_dev; 1271 struct rte_intr_handle *intr_handle; 1272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1274 struct i40e_vsi *vsi; 1275 int ret; 1276 uint32_t len, val; 1277 uint8_t aq_fail = 0; 1278 1279 PMD_INIT_FUNC_TRACE(); 1280 1281 dev->dev_ops = &i40e_eth_dev_ops; 1282 dev->rx_pkt_burst = i40e_recv_pkts; 1283 dev->tx_pkt_burst = i40e_xmit_pkts; 1284 dev->tx_pkt_prepare = i40e_prep_pkts; 1285 1286 /* for secondary processes, we don't initialise any further as primary 1287 * has already done this work. Only check we don't need a different 1288 * RX function */ 1289 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 1290 i40e_set_rx_function(dev); 1291 i40e_set_tx_function(dev); 1292 return 0; 1293 } 1294 i40e_set_default_ptype_table(dev); 1295 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1296 intr_handle = &pci_dev->intr_handle; 1297 1298 rte_eth_copy_pci_info(dev, pci_dev); 1299 1300 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1301 pf->adapter->eth_dev = dev; 1302 pf->dev_data = dev->data; 1303 1304 hw->back = I40E_PF_TO_ADAPTER(pf); 1305 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr); 1306 if (!hw->hw_addr) { 1307 PMD_INIT_LOG(ERR, 1308 "Hardware is not available, as address is NULL"); 1309 return -ENODEV; 1310 } 1311 1312 hw->vendor_id = pci_dev->id.vendor_id; 1313 hw->device_id = pci_dev->id.device_id; 1314 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1315 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1316 hw->bus.device = pci_dev->addr.devid; 1317 hw->bus.func = pci_dev->addr.function; 1318 hw->adapter_stopped = 0; 1319 hw->adapter_closed = 0; 1320 1321 /* 1322 * Switch Tag value should not be identical to either the First Tag 1323 * or Second Tag values. So set something other than common Ethertype 1324 * for internal switching. 1325 */ 1326 hw->switch_tag = 0xffff; 1327 1328 val = I40E_READ_REG(hw, I40E_GL_FWSTS); 1329 if (val & I40E_GL_FWSTS_FWS1B_MASK) { 1330 PMD_INIT_LOG(ERR, "\nERROR: " 1331 "Firmware recovery mode detected. Limiting functionality.\n" 1332 "Refer to the Intel(R) Ethernet Adapters and Devices " 1333 "User Guide for details on firmware recovery mode."); 1334 return -EIO; 1335 } 1336 1337 /* Check if need to support multi-driver */ 1338 i40e_support_multi_driver(dev); 1339 /* Check if users want the latest supported vec path */ 1340 i40e_use_latest_vec(dev); 1341 1342 /* Make sure all is clean before doing PF reset */ 1343 i40e_clear_hw(hw); 1344 1345 /* Reset here to make sure all is clean for each PF */ 1346 ret = i40e_pf_reset(hw); 1347 if (ret) { 1348 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret); 1349 return ret; 1350 } 1351 1352 /* Initialize the shared code (base driver) */ 1353 ret = i40e_init_shared_code(hw); 1354 if (ret) { 1355 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret); 1356 return ret; 1357 } 1358 1359 /* Initialize the parameters for adminq */ 1360 i40e_init_adminq_parameter(hw); 1361 ret = i40e_init_adminq(hw); 1362 if (ret != I40E_SUCCESS) { 1363 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret); 1364 return -EIO; 1365 } 1366 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x", 1367 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 1368 hw->aq.api_maj_ver, hw->aq.api_min_ver, 1369 ((hw->nvm.version >> 12) & 0xf), 1370 ((hw->nvm.version >> 4) & 0xff), 1371 (hw->nvm.version & 0xf), hw->nvm.eetrack); 1372 1373 /* Initialize the hardware */ 1374 i40e_hw_init(dev); 1375 1376 i40e_config_automask(pf); 1377 1378 i40e_set_default_pctype_table(dev); 1379 1380 /* 1381 * To work around the NVM issue, initialize registers 1382 * for packet type of QinQ by software. 1383 * It should be removed once issues are fixed in NVM. 1384 */ 1385 if (!pf->support_multi_driver) 1386 i40e_GLQF_reg_init(hw); 1387 1388 /* Initialize the input set for filters (hash and fd) to default value */ 1389 i40e_filter_input_set_init(pf); 1390 1391 /* initialise the L3_MAP register */ 1392 if (!pf->support_multi_driver) { 1393 ret = i40e_aq_debug_write_global_register(hw, 1394 I40E_GLQF_L3_MAP(40), 1395 0x00000028, NULL); 1396 if (ret) 1397 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", 1398 ret); 1399 PMD_INIT_LOG(DEBUG, 1400 "Global register 0x%08x is changed with 0x28", 1401 I40E_GLQF_L3_MAP(40)); 1402 } 1403 1404 /* Need the special FW version to support floating VEB */ 1405 config_floating_veb(dev); 1406 /* Clear PXE mode */ 1407 i40e_clear_pxe_mode(hw); 1408 i40e_dev_sync_phy_type(hw); 1409 1410 /* 1411 * On X710, performance number is far from the expectation on recent 1412 * firmware versions. The fix for this issue may not be integrated in 1413 * the following firmware version. So the workaround in software driver 1414 * is needed. It needs to modify the initial values of 3 internal only 1415 * registers. Note that the workaround can be removed when it is fixed 1416 * in firmware in the future. 1417 */ 1418 i40e_configure_registers(hw); 1419 1420 /* Get hw capabilities */ 1421 ret = i40e_get_cap(hw); 1422 if (ret != I40E_SUCCESS) { 1423 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret); 1424 goto err_get_capabilities; 1425 } 1426 1427 /* Initialize parameters for PF */ 1428 ret = i40e_pf_parameter_init(dev); 1429 if (ret != 0) { 1430 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret); 1431 goto err_parameter_init; 1432 } 1433 1434 /* Initialize the queue management */ 1435 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp); 1436 if (ret < 0) { 1437 PMD_INIT_LOG(ERR, "Failed to init queue pool"); 1438 goto err_qp_pool_init; 1439 } 1440 ret = i40e_res_pool_init(&pf->msix_pool, 1, 1441 hw->func_caps.num_msix_vectors - 1); 1442 if (ret < 0) { 1443 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 1444 goto err_msix_pool_init; 1445 } 1446 1447 /* Initialize lan hmc */ 1448 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 1449 hw->func_caps.num_rx_qp, 0, 0); 1450 if (ret != I40E_SUCCESS) { 1451 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret); 1452 goto err_init_lan_hmc; 1453 } 1454 1455 /* Configure lan hmc */ 1456 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 1457 if (ret != I40E_SUCCESS) { 1458 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret); 1459 goto err_configure_lan_hmc; 1460 } 1461 1462 /* Get and check the mac address */ 1463 i40e_get_mac_addr(hw, hw->mac.addr); 1464 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) { 1465 PMD_INIT_LOG(ERR, "mac address is not valid"); 1466 ret = -EIO; 1467 goto err_get_mac_addr; 1468 } 1469 /* Copy the permanent MAC address */ 1470 ether_addr_copy((struct ether_addr *) hw->mac.addr, 1471 (struct ether_addr *) hw->mac.perm_addr); 1472 1473 /* Disable flow control */ 1474 hw->fc.requested_mode = I40E_FC_NONE; 1475 i40e_set_fc(hw, &aq_fail, TRUE); 1476 1477 /* Set the global registers with default ether type value */ 1478 if (!pf->support_multi_driver) { 1479 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 1480 ETHER_TYPE_VLAN); 1481 if (ret != I40E_SUCCESS) { 1482 PMD_INIT_LOG(ERR, 1483 "Failed to set the default outer " 1484 "VLAN ether type"); 1485 goto err_setup_pf_switch; 1486 } 1487 } 1488 1489 /* PF setup, which includes VSI setup */ 1490 ret = i40e_pf_setup(pf); 1491 if (ret) { 1492 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret); 1493 goto err_setup_pf_switch; 1494 } 1495 1496 /* reset all stats of the device, including pf and main vsi */ 1497 i40e_dev_stats_reset(dev); 1498 1499 vsi = pf->main_vsi; 1500 1501 /* Disable double vlan by default */ 1502 i40e_vsi_config_double_vlan(vsi, FALSE); 1503 1504 /* Disable S-TAG identification when floating_veb is disabled */ 1505 if (!pf->floating_veb) { 1506 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN); 1507 if (ret & I40E_L2_TAGS_S_TAG_MASK) { 1508 ret &= ~I40E_L2_TAGS_S_TAG_MASK; 1509 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret); 1510 } 1511 } 1512 1513 if (!vsi->max_macaddrs) 1514 len = ETHER_ADDR_LEN; 1515 else 1516 len = ETHER_ADDR_LEN * vsi->max_macaddrs; 1517 1518 /* Should be after VSI initialized */ 1519 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0); 1520 if (!dev->data->mac_addrs) { 1521 PMD_INIT_LOG(ERR, 1522 "Failed to allocated memory for storing mac address"); 1523 goto err_mac_alloc; 1524 } 1525 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr, 1526 &dev->data->mac_addrs[0]); 1527 1528 /* Init dcb to sw mode by default */ 1529 ret = i40e_dcb_init_configure(dev, TRUE); 1530 if (ret != I40E_SUCCESS) { 1531 PMD_INIT_LOG(INFO, "Failed to init dcb."); 1532 pf->flags &= ~I40E_FLAG_DCB; 1533 } 1534 /* Update HW struct after DCB configuration */ 1535 i40e_get_cap(hw); 1536 1537 /* initialize pf host driver to setup SRIOV resource if applicable */ 1538 i40e_pf_host_init(dev); 1539 1540 /* register callback func to eal lib */ 1541 rte_intr_callback_register(intr_handle, 1542 i40e_dev_interrupt_handler, dev); 1543 1544 /* configure and enable device interrupt */ 1545 i40e_pf_config_irq0(hw, TRUE); 1546 i40e_pf_enable_irq0(hw); 1547 1548 /* enable uio intr after callback register */ 1549 rte_intr_enable(intr_handle); 1550 1551 /* By default disable flexible payload in global configuration */ 1552 if (!pf->support_multi_driver) 1553 i40e_flex_payload_reg_set_default(hw); 1554 1555 /* 1556 * Add an ethertype filter to drop all flow control frames transmitted 1557 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC 1558 * frames to wire. 1559 */ 1560 i40e_add_tx_flow_control_drop_filter(pf); 1561 1562 /* Set the max frame size to 0x2600 by default, 1563 * in case other drivers changed the default value. 1564 */ 1565 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL); 1566 1567 /* initialize mirror rule list */ 1568 TAILQ_INIT(&pf->mirror_list); 1569 1570 /* initialize Traffic Manager configuration */ 1571 i40e_tm_conf_init(dev); 1572 1573 /* Initialize customized information */ 1574 i40e_init_customized_info(pf); 1575 1576 ret = i40e_init_ethtype_filter_list(dev); 1577 if (ret < 0) 1578 goto err_init_ethtype_filter_list; 1579 ret = i40e_init_tunnel_filter_list(dev); 1580 if (ret < 0) 1581 goto err_init_tunnel_filter_list; 1582 ret = i40e_init_fdir_filter_list(dev); 1583 if (ret < 0) 1584 goto err_init_fdir_filter_list; 1585 1586 /* initialize queue region configuration */ 1587 i40e_init_queue_region_conf(dev); 1588 1589 /* initialize rss configuration from rte_flow */ 1590 memset(&pf->rss_info, 0, 1591 sizeof(struct i40e_rte_flow_rss_conf)); 1592 1593 return 0; 1594 1595 err_init_fdir_filter_list: 1596 rte_free(pf->tunnel.hash_table); 1597 rte_free(pf->tunnel.hash_map); 1598 err_init_tunnel_filter_list: 1599 rte_free(pf->ethertype.hash_table); 1600 rte_free(pf->ethertype.hash_map); 1601 err_init_ethtype_filter_list: 1602 rte_free(dev->data->mac_addrs); 1603 err_mac_alloc: 1604 i40e_vsi_release(pf->main_vsi); 1605 err_setup_pf_switch: 1606 err_get_mac_addr: 1607 err_configure_lan_hmc: 1608 (void)i40e_shutdown_lan_hmc(hw); 1609 err_init_lan_hmc: 1610 i40e_res_pool_destroy(&pf->msix_pool); 1611 err_msix_pool_init: 1612 i40e_res_pool_destroy(&pf->qp_pool); 1613 err_qp_pool_init: 1614 err_parameter_init: 1615 err_get_capabilities: 1616 (void)i40e_shutdown_adminq(hw); 1617 1618 return ret; 1619 } 1620 1621 static void 1622 i40e_rm_ethtype_filter_list(struct i40e_pf *pf) 1623 { 1624 struct i40e_ethertype_filter *p_ethertype; 1625 struct i40e_ethertype_rule *ethertype_rule; 1626 1627 ethertype_rule = &pf->ethertype; 1628 /* Remove all ethertype filter rules and hash */ 1629 if (ethertype_rule->hash_map) 1630 rte_free(ethertype_rule->hash_map); 1631 if (ethertype_rule->hash_table) 1632 rte_hash_free(ethertype_rule->hash_table); 1633 1634 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) { 1635 TAILQ_REMOVE(ðertype_rule->ethertype_list, 1636 p_ethertype, rules); 1637 rte_free(p_ethertype); 1638 } 1639 } 1640 1641 static void 1642 i40e_rm_tunnel_filter_list(struct i40e_pf *pf) 1643 { 1644 struct i40e_tunnel_filter *p_tunnel; 1645 struct i40e_tunnel_rule *tunnel_rule; 1646 1647 tunnel_rule = &pf->tunnel; 1648 /* Remove all tunnel director rules and hash */ 1649 if (tunnel_rule->hash_map) 1650 rte_free(tunnel_rule->hash_map); 1651 if (tunnel_rule->hash_table) 1652 rte_hash_free(tunnel_rule->hash_table); 1653 1654 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) { 1655 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules); 1656 rte_free(p_tunnel); 1657 } 1658 } 1659 1660 static void 1661 i40e_rm_fdir_filter_list(struct i40e_pf *pf) 1662 { 1663 struct i40e_fdir_filter *p_fdir; 1664 struct i40e_fdir_info *fdir_info; 1665 1666 fdir_info = &pf->fdir; 1667 /* Remove all flow director rules and hash */ 1668 if (fdir_info->hash_map) 1669 rte_free(fdir_info->hash_map); 1670 if (fdir_info->hash_table) 1671 rte_hash_free(fdir_info->hash_table); 1672 1673 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) { 1674 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules); 1675 rte_free(p_fdir); 1676 } 1677 } 1678 1679 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw) 1680 { 1681 /* 1682 * Disable by default flexible payload 1683 * for corresponding L2/L3/L4 layers. 1684 */ 1685 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000); 1686 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000); 1687 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000); 1688 } 1689 1690 static int 1691 eth_i40e_dev_uninit(struct rte_eth_dev *dev) 1692 { 1693 struct i40e_pf *pf; 1694 struct rte_pci_device *pci_dev; 1695 struct rte_intr_handle *intr_handle; 1696 struct i40e_hw *hw; 1697 struct i40e_filter_control_settings settings; 1698 struct rte_flow *p_flow; 1699 int ret; 1700 uint8_t aq_fail = 0; 1701 int retries = 0; 1702 1703 PMD_INIT_FUNC_TRACE(); 1704 1705 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1706 return 0; 1707 1708 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1709 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1710 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1711 intr_handle = &pci_dev->intr_handle; 1712 1713 ret = rte_eth_switch_domain_free(pf->switch_domain_id); 1714 if (ret) 1715 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret); 1716 1717 if (hw->adapter_closed == 0) 1718 i40e_dev_close(dev); 1719 1720 dev->dev_ops = NULL; 1721 dev->rx_pkt_burst = NULL; 1722 dev->tx_pkt_burst = NULL; 1723 1724 /* Clear PXE mode */ 1725 i40e_clear_pxe_mode(hw); 1726 1727 /* Unconfigure filter control */ 1728 memset(&settings, 0, sizeof(settings)); 1729 ret = i40e_set_filter_control(hw, &settings); 1730 if (ret) 1731 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d", 1732 ret); 1733 1734 /* Disable flow control */ 1735 hw->fc.requested_mode = I40E_FC_NONE; 1736 i40e_set_fc(hw, &aq_fail, TRUE); 1737 1738 /* uninitialize pf host driver */ 1739 i40e_pf_host_uninit(dev); 1740 1741 /* disable uio intr before callback unregister */ 1742 rte_intr_disable(intr_handle); 1743 1744 /* unregister callback func to eal lib */ 1745 do { 1746 ret = rte_intr_callback_unregister(intr_handle, 1747 i40e_dev_interrupt_handler, dev); 1748 if (ret >= 0) { 1749 break; 1750 } else if (ret != -EAGAIN) { 1751 PMD_INIT_LOG(ERR, 1752 "intr callback unregister failed: %d", 1753 ret); 1754 return ret; 1755 } 1756 i40e_msec_delay(500); 1757 } while (retries++ < 5); 1758 1759 i40e_rm_ethtype_filter_list(pf); 1760 i40e_rm_tunnel_filter_list(pf); 1761 i40e_rm_fdir_filter_list(pf); 1762 1763 /* Remove all flows */ 1764 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) { 1765 TAILQ_REMOVE(&pf->flow_list, p_flow, node); 1766 rte_free(p_flow); 1767 } 1768 1769 /* Remove all Traffic Manager configuration */ 1770 i40e_tm_conf_uninit(dev); 1771 1772 return 0; 1773 } 1774 1775 static int 1776 i40e_dev_configure(struct rte_eth_dev *dev) 1777 { 1778 struct i40e_adapter *ad = 1779 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1782 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1783 int i, ret; 1784 1785 ret = i40e_dev_sync_phy_type(hw); 1786 if (ret) 1787 return ret; 1788 1789 /* Initialize to TRUE. If any of Rx queues doesn't meet the 1790 * bulk allocation or vector Rx preconditions we will reset it. 1791 */ 1792 ad->rx_bulk_alloc_allowed = true; 1793 ad->rx_vec_allowed = true; 1794 ad->tx_simple_allowed = true; 1795 ad->tx_vec_allowed = true; 1796 1797 /* Only legacy filter API needs the following fdir config. So when the 1798 * legacy filter API is deprecated, the following codes should also be 1799 * removed. 1800 */ 1801 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) { 1802 ret = i40e_fdir_setup(pf); 1803 if (ret != I40E_SUCCESS) { 1804 PMD_DRV_LOG(ERR, "Failed to setup flow director."); 1805 return -ENOTSUP; 1806 } 1807 ret = i40e_fdir_configure(dev); 1808 if (ret < 0) { 1809 PMD_DRV_LOG(ERR, "failed to configure fdir."); 1810 goto err; 1811 } 1812 } else 1813 i40e_fdir_teardown(pf); 1814 1815 ret = i40e_dev_init_vlan(dev); 1816 if (ret < 0) 1817 goto err; 1818 1819 /* VMDQ setup. 1820 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and 1821 * RSS setting have different requirements. 1822 * General PMD driver call sequence are NIC init, configure, 1823 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it 1824 * will try to lookup the VSI that specific queue belongs to if VMDQ 1825 * applicable. So, VMDQ setting has to be done before 1826 * rx/tx_queue_setup(). This function is good to place vmdq_setup. 1827 * For RSS setting, it will try to calculate actual configured RX queue 1828 * number, which will be available after rx_queue_setup(). dev_start() 1829 * function is good to place RSS setup. 1830 */ 1831 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) { 1832 ret = i40e_vmdq_setup(dev); 1833 if (ret) 1834 goto err; 1835 } 1836 1837 if (mq_mode & ETH_MQ_RX_DCB_FLAG) { 1838 ret = i40e_dcb_setup(dev); 1839 if (ret) { 1840 PMD_DRV_LOG(ERR, "failed to configure DCB."); 1841 goto err_dcb; 1842 } 1843 } 1844 1845 TAILQ_INIT(&pf->flow_list); 1846 1847 return 0; 1848 1849 err_dcb: 1850 /* need to release vmdq resource if exists */ 1851 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 1852 i40e_vsi_release(pf->vmdq[i].vsi); 1853 pf->vmdq[i].vsi = NULL; 1854 } 1855 rte_free(pf->vmdq); 1856 pf->vmdq = NULL; 1857 err: 1858 /* Need to release fdir resource if exists. 1859 * Only legacy filter API needs the following fdir config. So when the 1860 * legacy filter API is deprecated, the following code should also be 1861 * removed. 1862 */ 1863 i40e_fdir_teardown(pf); 1864 return ret; 1865 } 1866 1867 void 1868 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi) 1869 { 1870 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1871 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1872 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1873 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1874 uint16_t msix_vect = vsi->msix_intr; 1875 uint16_t i; 1876 1877 for (i = 0; i < vsi->nb_qps; i++) { 1878 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); 1879 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); 1880 rte_wmb(); 1881 } 1882 1883 if (vsi->type != I40E_VSI_SRIOV) { 1884 if (!rte_intr_allow_others(intr_handle)) { 1885 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 1886 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); 1887 I40E_WRITE_REG(hw, 1888 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), 1889 0); 1890 } else { 1891 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 1892 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); 1893 I40E_WRITE_REG(hw, 1894 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, 1895 msix_vect - 1), 0); 1896 } 1897 } else { 1898 uint32_t reg; 1899 reg = (hw->func_caps.num_msix_vectors_vf - 1) * 1900 vsi->user_param + (msix_vect - 1); 1901 1902 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 1903 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK); 1904 } 1905 I40E_WRITE_FLUSH(hw); 1906 } 1907 1908 static void 1909 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect, 1910 int base_queue, int nb_queue, 1911 uint16_t itr_idx) 1912 { 1913 int i; 1914 uint32_t val; 1915 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1916 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 1917 1918 /* Bind all RX queues to allocated MSIX interrupt */ 1919 for (i = 0; i < nb_queue; i++) { 1920 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 1921 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT | 1922 ((base_queue + i + 1) << 1923 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 1924 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 1925 I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1926 1927 if (i == nb_queue - 1) 1928 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK; 1929 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val); 1930 } 1931 1932 /* Write first RX queue to Link list register as the head element */ 1933 if (vsi->type != I40E_VSI_SRIOV) { 1934 uint16_t interval = 1935 i40e_calc_itr_interval(1, pf->support_multi_driver); 1936 1937 if (msix_vect == I40E_MISC_VEC_ID) { 1938 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 1939 (base_queue << 1940 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 1941 (0x0 << 1942 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 1943 I40E_WRITE_REG(hw, 1944 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), 1945 interval); 1946 } else { 1947 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 1948 (base_queue << 1949 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 1950 (0x0 << 1951 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 1952 I40E_WRITE_REG(hw, 1953 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, 1954 msix_vect - 1), 1955 interval); 1956 } 1957 } else { 1958 uint32_t reg; 1959 1960 if (msix_vect == I40E_MISC_VEC_ID) { 1961 I40E_WRITE_REG(hw, 1962 I40E_VPINT_LNKLST0(vsi->user_param), 1963 (base_queue << 1964 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 1965 (0x0 << 1966 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 1967 } else { 1968 /* num_msix_vectors_vf needs to minus irq0 */ 1969 reg = (hw->func_caps.num_msix_vectors_vf - 1) * 1970 vsi->user_param + (msix_vect - 1); 1971 1972 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 1973 (base_queue << 1974 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 1975 (0x0 << 1976 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 1977 } 1978 } 1979 1980 I40E_WRITE_FLUSH(hw); 1981 } 1982 1983 void 1984 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx) 1985 { 1986 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1987 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1988 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1989 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1990 uint16_t msix_vect = vsi->msix_intr; 1991 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 1992 uint16_t queue_idx = 0; 1993 int record = 0; 1994 int i; 1995 1996 for (i = 0; i < vsi->nb_qps; i++) { 1997 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); 1998 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); 1999 } 2000 2001 /* VF bind interrupt */ 2002 if (vsi->type == I40E_VSI_SRIOV) { 2003 __vsi_queues_bind_intr(vsi, msix_vect, 2004 vsi->base_queue, vsi->nb_qps, 2005 itr_idx); 2006 return; 2007 } 2008 2009 /* PF & VMDq bind interrupt */ 2010 if (rte_intr_dp_is_en(intr_handle)) { 2011 if (vsi->type == I40E_VSI_MAIN) { 2012 queue_idx = 0; 2013 record = 1; 2014 } else if (vsi->type == I40E_VSI_VMDQ2) { 2015 struct i40e_vsi *main_vsi = 2016 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter); 2017 queue_idx = vsi->base_queue - main_vsi->nb_qps; 2018 record = 1; 2019 } 2020 } 2021 2022 for (i = 0; i < vsi->nb_used_qps; i++) { 2023 if (nb_msix <= 1) { 2024 if (!rte_intr_allow_others(intr_handle)) 2025 /* allow to share MISC_VEC_ID */ 2026 msix_vect = I40E_MISC_VEC_ID; 2027 2028 /* no enough msix_vect, map all to one */ 2029 __vsi_queues_bind_intr(vsi, msix_vect, 2030 vsi->base_queue + i, 2031 vsi->nb_used_qps - i, 2032 itr_idx); 2033 for (; !!record && i < vsi->nb_used_qps; i++) 2034 intr_handle->intr_vec[queue_idx + i] = 2035 msix_vect; 2036 break; 2037 } 2038 /* 1:1 queue/msix_vect mapping */ 2039 __vsi_queues_bind_intr(vsi, msix_vect, 2040 vsi->base_queue + i, 1, 2041 itr_idx); 2042 if (!!record) 2043 intr_handle->intr_vec[queue_idx + i] = msix_vect; 2044 2045 msix_vect++; 2046 nb_msix--; 2047 } 2048 } 2049 2050 static void 2051 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi) 2052 { 2053 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2054 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2055 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2056 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2057 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 2058 uint16_t msix_intr, i; 2059 2060 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) 2061 for (i = 0; i < vsi->nb_msix; i++) { 2062 msix_intr = vsi->msix_intr + i; 2063 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), 2064 I40E_PFINT_DYN_CTLN_INTENA_MASK | 2065 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 2066 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 2067 } 2068 else 2069 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 2070 I40E_PFINT_DYN_CTL0_INTENA_MASK | 2071 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 2072 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 2073 2074 I40E_WRITE_FLUSH(hw); 2075 } 2076 2077 static void 2078 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi) 2079 { 2080 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2081 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2082 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2083 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2084 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 2085 uint16_t msix_intr, i; 2086 2087 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) 2088 for (i = 0; i < vsi->nb_msix; i++) { 2089 msix_intr = vsi->msix_intr + i; 2090 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), 2091 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 2092 } 2093 else 2094 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 2095 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 2096 2097 I40E_WRITE_FLUSH(hw); 2098 } 2099 2100 static inline uint8_t 2101 i40e_parse_link_speeds(uint16_t link_speeds) 2102 { 2103 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN; 2104 2105 if (link_speeds & ETH_LINK_SPEED_40G) 2106 link_speed |= I40E_LINK_SPEED_40GB; 2107 if (link_speeds & ETH_LINK_SPEED_25G) 2108 link_speed |= I40E_LINK_SPEED_25GB; 2109 if (link_speeds & ETH_LINK_SPEED_20G) 2110 link_speed |= I40E_LINK_SPEED_20GB; 2111 if (link_speeds & ETH_LINK_SPEED_10G) 2112 link_speed |= I40E_LINK_SPEED_10GB; 2113 if (link_speeds & ETH_LINK_SPEED_1G) 2114 link_speed |= I40E_LINK_SPEED_1GB; 2115 if (link_speeds & ETH_LINK_SPEED_100M) 2116 link_speed |= I40E_LINK_SPEED_100MB; 2117 2118 return link_speed; 2119 } 2120 2121 static int 2122 i40e_phy_conf_link(struct i40e_hw *hw, 2123 uint8_t abilities, 2124 uint8_t force_speed, 2125 bool is_up) 2126 { 2127 enum i40e_status_code status; 2128 struct i40e_aq_get_phy_abilities_resp phy_ab; 2129 struct i40e_aq_set_phy_config phy_conf; 2130 enum i40e_aq_phy_type cnt; 2131 uint8_t avail_speed; 2132 uint32_t phy_type_mask = 0; 2133 2134 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX | 2135 I40E_AQ_PHY_FLAG_PAUSE_RX | 2136 I40E_AQ_PHY_FLAG_PAUSE_RX | 2137 I40E_AQ_PHY_FLAG_LOW_POWER; 2138 int ret = -ENOTSUP; 2139 2140 /* To get phy capabilities of available speeds. */ 2141 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, 2142 NULL); 2143 if (status) { 2144 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n", 2145 status); 2146 return ret; 2147 } 2148 avail_speed = phy_ab.link_speed; 2149 2150 /* To get the current phy config. */ 2151 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab, 2152 NULL); 2153 if (status) { 2154 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n", 2155 status); 2156 return ret; 2157 } 2158 2159 /* If link needs to go up and it is in autoneg mode the speed is OK, 2160 * no need to set up again. 2161 */ 2162 if (is_up && phy_ab.phy_type != 0 && 2163 abilities & I40E_AQ_PHY_AN_ENABLED && 2164 phy_ab.link_speed != 0) 2165 return I40E_SUCCESS; 2166 2167 memset(&phy_conf, 0, sizeof(phy_conf)); 2168 2169 /* bits 0-2 use the values from get_phy_abilities_resp */ 2170 abilities &= ~mask; 2171 abilities |= phy_ab.abilities & mask; 2172 2173 phy_conf.abilities = abilities; 2174 2175 /* If link needs to go up, but the force speed is not supported, 2176 * Warn users and config the default available speeds. 2177 */ 2178 if (is_up && !(force_speed & avail_speed)) { 2179 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n"); 2180 phy_conf.link_speed = avail_speed; 2181 } else { 2182 phy_conf.link_speed = is_up ? force_speed : avail_speed; 2183 } 2184 2185 /* PHY type mask needs to include each type except PHY type extension */ 2186 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++) 2187 phy_type_mask |= 1 << cnt; 2188 2189 /* use get_phy_abilities_resp value for the rest */ 2190 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0; 2191 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR | 2192 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR | 2193 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0; 2194 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info; 2195 phy_conf.eee_capability = phy_ab.eee_capability; 2196 phy_conf.eeer = phy_ab.eeer_val; 2197 phy_conf.low_power_ctrl = phy_ab.d3_lpan; 2198 2199 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x", 2200 phy_ab.abilities, phy_ab.link_speed); 2201 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x", 2202 phy_conf.abilities, phy_conf.link_speed); 2203 2204 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL); 2205 if (status) 2206 return ret; 2207 2208 return I40E_SUCCESS; 2209 } 2210 2211 static int 2212 i40e_apply_link_speed(struct rte_eth_dev *dev) 2213 { 2214 uint8_t speed; 2215 uint8_t abilities = 0; 2216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2217 struct rte_eth_conf *conf = &dev->data->dev_conf; 2218 2219 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) { 2220 conf->link_speeds = ETH_LINK_SPEED_40G | 2221 ETH_LINK_SPEED_25G | 2222 ETH_LINK_SPEED_20G | 2223 ETH_LINK_SPEED_10G | 2224 ETH_LINK_SPEED_1G | 2225 ETH_LINK_SPEED_100M; 2226 } 2227 speed = i40e_parse_link_speeds(conf->link_speeds); 2228 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK | 2229 I40E_AQ_PHY_AN_ENABLED | 2230 I40E_AQ_PHY_LINK_ENABLED; 2231 2232 return i40e_phy_conf_link(hw, abilities, speed, true); 2233 } 2234 2235 static int 2236 i40e_dev_start(struct rte_eth_dev *dev) 2237 { 2238 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2239 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2240 struct i40e_vsi *main_vsi = pf->main_vsi; 2241 int ret, i; 2242 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2243 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2244 uint32_t intr_vector = 0; 2245 struct i40e_vsi *vsi; 2246 2247 hw->adapter_stopped = 0; 2248 2249 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2250 PMD_INIT_LOG(ERR, 2251 "Invalid link_speeds for port %u, autonegotiation disabled", 2252 dev->data->port_id); 2253 return -EINVAL; 2254 } 2255 2256 rte_intr_disable(intr_handle); 2257 2258 if ((rte_intr_cap_multiple(intr_handle) || 2259 !RTE_ETH_DEV_SRIOV(dev).active) && 2260 dev->data->dev_conf.intr_conf.rxq != 0) { 2261 intr_vector = dev->data->nb_rx_queues; 2262 ret = rte_intr_efd_enable(intr_handle, intr_vector); 2263 if (ret) 2264 return ret; 2265 } 2266 2267 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2268 intr_handle->intr_vec = 2269 rte_zmalloc("intr_vec", 2270 dev->data->nb_rx_queues * sizeof(int), 2271 0); 2272 if (!intr_handle->intr_vec) { 2273 PMD_INIT_LOG(ERR, 2274 "Failed to allocate %d rx_queues intr_vec", 2275 dev->data->nb_rx_queues); 2276 return -ENOMEM; 2277 } 2278 } 2279 2280 /* Initialize VSI */ 2281 ret = i40e_dev_rxtx_init(pf); 2282 if (ret != I40E_SUCCESS) { 2283 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues"); 2284 goto err_up; 2285 } 2286 2287 /* Map queues with MSIX interrupt */ 2288 main_vsi->nb_used_qps = dev->data->nb_rx_queues - 2289 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 2290 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT); 2291 i40e_vsi_enable_queues_intr(main_vsi); 2292 2293 /* Map VMDQ VSI queues with MSIX interrupt */ 2294 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2295 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 2296 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi, 2297 I40E_ITR_INDEX_DEFAULT); 2298 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi); 2299 } 2300 2301 /* enable FDIR MSIX interrupt */ 2302 if (pf->fdir.fdir_vsi) { 2303 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi, 2304 I40E_ITR_INDEX_NONE); 2305 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi); 2306 } 2307 2308 /* Enable all queues which have been configured */ 2309 ret = i40e_dev_switch_queues(pf, TRUE); 2310 if (ret != I40E_SUCCESS) { 2311 PMD_DRV_LOG(ERR, "Failed to enable VSI"); 2312 goto err_up; 2313 } 2314 2315 /* Enable receiving broadcast packets */ 2316 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL); 2317 if (ret != I40E_SUCCESS) 2318 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2319 2320 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2321 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid, 2322 true, NULL); 2323 if (ret != I40E_SUCCESS) 2324 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2325 } 2326 2327 /* Enable the VLAN promiscuous mode. */ 2328 if (pf->vfs) { 2329 for (i = 0; i < pf->vf_num; i++) { 2330 vsi = pf->vfs[i].vsi; 2331 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, 2332 true, NULL); 2333 } 2334 } 2335 2336 /* Enable mac loopback mode */ 2337 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE || 2338 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) { 2339 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL); 2340 if (ret != I40E_SUCCESS) { 2341 PMD_DRV_LOG(ERR, "fail to set loopback link"); 2342 goto err_up; 2343 } 2344 } 2345 2346 /* Apply link configure */ 2347 ret = i40e_apply_link_speed(dev); 2348 if (I40E_SUCCESS != ret) { 2349 PMD_DRV_LOG(ERR, "Fail to apply link setting"); 2350 goto err_up; 2351 } 2352 2353 if (!rte_intr_allow_others(intr_handle)) { 2354 rte_intr_callback_unregister(intr_handle, 2355 i40e_dev_interrupt_handler, 2356 (void *)dev); 2357 /* configure and enable device interrupt */ 2358 i40e_pf_config_irq0(hw, FALSE); 2359 i40e_pf_enable_irq0(hw); 2360 2361 if (dev->data->dev_conf.intr_conf.lsc != 0) 2362 PMD_INIT_LOG(INFO, 2363 "lsc won't enable because of no intr multiplex"); 2364 } else { 2365 ret = i40e_aq_set_phy_int_mask(hw, 2366 ~(I40E_AQ_EVENT_LINK_UPDOWN | 2367 I40E_AQ_EVENT_MODULE_QUAL_FAIL | 2368 I40E_AQ_EVENT_MEDIA_NA), NULL); 2369 if (ret != I40E_SUCCESS) 2370 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 2371 2372 /* Call get_link_info aq commond to enable/disable LSE */ 2373 i40e_dev_link_update(dev, 0); 2374 } 2375 2376 if (dev->data->dev_conf.intr_conf.rxq == 0) { 2377 rte_eal_alarm_set(I40E_ALARM_INTERVAL, 2378 i40e_dev_alarm_handler, dev); 2379 } else { 2380 /* enable uio intr after callback register */ 2381 rte_intr_enable(intr_handle); 2382 } 2383 2384 i40e_filter_restore(pf); 2385 2386 if (pf->tm_conf.root && !pf->tm_conf.committed) 2387 PMD_DRV_LOG(WARNING, 2388 "please call hierarchy_commit() " 2389 "before starting the port"); 2390 2391 return I40E_SUCCESS; 2392 2393 err_up: 2394 i40e_dev_switch_queues(pf, FALSE); 2395 i40e_dev_clear_queues(dev); 2396 2397 return ret; 2398 } 2399 2400 static void 2401 i40e_dev_stop(struct rte_eth_dev *dev) 2402 { 2403 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2404 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2405 struct i40e_vsi *main_vsi = pf->main_vsi; 2406 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2407 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2408 int i; 2409 2410 if (hw->adapter_stopped == 1) 2411 return; 2412 2413 if (dev->data->dev_conf.intr_conf.rxq == 0) { 2414 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev); 2415 rte_intr_enable(intr_handle); 2416 } 2417 2418 /* Disable all queues */ 2419 i40e_dev_switch_queues(pf, FALSE); 2420 2421 /* un-map queues with interrupt registers */ 2422 i40e_vsi_disable_queues_intr(main_vsi); 2423 i40e_vsi_queues_unbind_intr(main_vsi); 2424 2425 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2426 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi); 2427 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi); 2428 } 2429 2430 if (pf->fdir.fdir_vsi) { 2431 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi); 2432 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi); 2433 } 2434 /* Clear all queues and release memory */ 2435 i40e_dev_clear_queues(dev); 2436 2437 /* Set link down */ 2438 i40e_dev_set_link_down(dev); 2439 2440 if (!rte_intr_allow_others(intr_handle)) 2441 /* resume to the default handler */ 2442 rte_intr_callback_register(intr_handle, 2443 i40e_dev_interrupt_handler, 2444 (void *)dev); 2445 2446 /* Clean datapath event and queue/vec mapping */ 2447 rte_intr_efd_disable(intr_handle); 2448 if (intr_handle->intr_vec) { 2449 rte_free(intr_handle->intr_vec); 2450 intr_handle->intr_vec = NULL; 2451 } 2452 2453 /* reset hierarchy commit */ 2454 pf->tm_conf.committed = false; 2455 2456 hw->adapter_stopped = 1; 2457 2458 pf->adapter->rss_reta_updated = 0; 2459 } 2460 2461 static void 2462 i40e_dev_close(struct rte_eth_dev *dev) 2463 { 2464 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2465 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2466 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2467 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2468 struct i40e_mirror_rule *p_mirror; 2469 uint32_t reg; 2470 int i; 2471 int ret; 2472 2473 PMD_INIT_FUNC_TRACE(); 2474 2475 i40e_dev_stop(dev); 2476 2477 /* Remove all mirror rules */ 2478 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) { 2479 ret = i40e_aq_del_mirror_rule(hw, 2480 pf->main_vsi->veb->seid, 2481 p_mirror->rule_type, 2482 p_mirror->entries, 2483 p_mirror->num_entries, 2484 p_mirror->id); 2485 if (ret < 0) 2486 PMD_DRV_LOG(ERR, "failed to remove mirror rule: " 2487 "status = %d, aq_err = %d.", ret, 2488 hw->aq.asq_last_status); 2489 2490 /* remove mirror software resource anyway */ 2491 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules); 2492 rte_free(p_mirror); 2493 pf->nb_mirror_rule--; 2494 } 2495 2496 i40e_dev_free_queues(dev); 2497 2498 /* Disable interrupt */ 2499 i40e_pf_disable_irq0(hw); 2500 rte_intr_disable(intr_handle); 2501 2502 /* 2503 * Only legacy filter API needs the following fdir config. So when the 2504 * legacy filter API is deprecated, the following code should also be 2505 * removed. 2506 */ 2507 i40e_fdir_teardown(pf); 2508 2509 /* shutdown and destroy the HMC */ 2510 i40e_shutdown_lan_hmc(hw); 2511 2512 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2513 i40e_vsi_release(pf->vmdq[i].vsi); 2514 pf->vmdq[i].vsi = NULL; 2515 } 2516 rte_free(pf->vmdq); 2517 pf->vmdq = NULL; 2518 2519 /* release all the existing VSIs and VEBs */ 2520 i40e_vsi_release(pf->main_vsi); 2521 2522 /* shutdown the adminq */ 2523 i40e_aq_queue_shutdown(hw, true); 2524 i40e_shutdown_adminq(hw); 2525 2526 i40e_res_pool_destroy(&pf->qp_pool); 2527 i40e_res_pool_destroy(&pf->msix_pool); 2528 2529 /* Disable flexible payload in global configuration */ 2530 if (!pf->support_multi_driver) 2531 i40e_flex_payload_reg_set_default(hw); 2532 2533 /* force a PF reset to clean anything leftover */ 2534 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL); 2535 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL, 2536 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 2537 I40E_WRITE_FLUSH(hw); 2538 2539 hw->adapter_closed = 1; 2540 } 2541 2542 /* 2543 * Reset PF device only to re-initialize resources in PMD layer 2544 */ 2545 static int 2546 i40e_dev_reset(struct rte_eth_dev *dev) 2547 { 2548 int ret; 2549 2550 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2551 * its VF to make them align with it. The detailed notification 2552 * mechanism is PMD specific. As to i40e PF, it is rather complex. 2553 * To avoid unexpected behavior in VF, currently reset of PF with 2554 * SR-IOV activation is not supported. It might be supported later. 2555 */ 2556 if (dev->data->sriov.active) 2557 return -ENOTSUP; 2558 2559 ret = eth_i40e_dev_uninit(dev); 2560 if (ret) 2561 return ret; 2562 2563 ret = eth_i40e_dev_init(dev, NULL); 2564 2565 return ret; 2566 } 2567 2568 static void 2569 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev) 2570 { 2571 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2572 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2573 struct i40e_vsi *vsi = pf->main_vsi; 2574 int status; 2575 2576 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2577 true, NULL, true); 2578 if (status != I40E_SUCCESS) 2579 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous"); 2580 2581 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, 2582 TRUE, NULL); 2583 if (status != I40E_SUCCESS) 2584 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous"); 2585 2586 } 2587 2588 static void 2589 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev) 2590 { 2591 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2592 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2593 struct i40e_vsi *vsi = pf->main_vsi; 2594 int status; 2595 2596 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2597 false, NULL, true); 2598 if (status != I40E_SUCCESS) 2599 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous"); 2600 2601 /* must remain in all_multicast mode */ 2602 if (dev->data->all_multicast == 1) 2603 return; 2604 2605 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, 2606 false, NULL); 2607 if (status != I40E_SUCCESS) 2608 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous"); 2609 } 2610 2611 static void 2612 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev) 2613 { 2614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2616 struct i40e_vsi *vsi = pf->main_vsi; 2617 int ret; 2618 2619 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL); 2620 if (ret != I40E_SUCCESS) 2621 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous"); 2622 } 2623 2624 static void 2625 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev) 2626 { 2627 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2628 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2629 struct i40e_vsi *vsi = pf->main_vsi; 2630 int ret; 2631 2632 if (dev->data->promiscuous == 1) 2633 return; /* must remain in all_multicast mode */ 2634 2635 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, 2636 vsi->seid, FALSE, NULL); 2637 if (ret != I40E_SUCCESS) 2638 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous"); 2639 } 2640 2641 /* 2642 * Set device link up. 2643 */ 2644 static int 2645 i40e_dev_set_link_up(struct rte_eth_dev *dev) 2646 { 2647 /* re-apply link speed setting */ 2648 return i40e_apply_link_speed(dev); 2649 } 2650 2651 /* 2652 * Set device link down. 2653 */ 2654 static int 2655 i40e_dev_set_link_down(struct rte_eth_dev *dev) 2656 { 2657 uint8_t speed = I40E_LINK_SPEED_UNKNOWN; 2658 uint8_t abilities = 0; 2659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2660 2661 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 2662 return i40e_phy_conf_link(hw, abilities, speed, false); 2663 } 2664 2665 static __rte_always_inline void 2666 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link) 2667 { 2668 /* Link status registers and values*/ 2669 #define I40E_PRTMAC_LINKSTA 0x001E2420 2670 #define I40E_REG_LINK_UP 0x40000080 2671 #define I40E_PRTMAC_MACC 0x001E24E0 2672 #define I40E_REG_MACC_25GB 0x00020000 2673 #define I40E_REG_SPEED_MASK 0x38000000 2674 #define I40E_REG_SPEED_100MB 0x00000000 2675 #define I40E_REG_SPEED_1GB 0x08000000 2676 #define I40E_REG_SPEED_10GB 0x10000000 2677 #define I40E_REG_SPEED_20GB 0x20000000 2678 #define I40E_REG_SPEED_25_40GB 0x18000000 2679 uint32_t link_speed; 2680 uint32_t reg_val; 2681 2682 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA); 2683 link_speed = reg_val & I40E_REG_SPEED_MASK; 2684 reg_val &= I40E_REG_LINK_UP; 2685 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0; 2686 2687 if (unlikely(link->link_status == 0)) 2688 return; 2689 2690 /* Parse the link status */ 2691 switch (link_speed) { 2692 case I40E_REG_SPEED_100MB: 2693 link->link_speed = ETH_SPEED_NUM_100M; 2694 break; 2695 case I40E_REG_SPEED_1GB: 2696 link->link_speed = ETH_SPEED_NUM_1G; 2697 break; 2698 case I40E_REG_SPEED_10GB: 2699 link->link_speed = ETH_SPEED_NUM_10G; 2700 break; 2701 case I40E_REG_SPEED_20GB: 2702 link->link_speed = ETH_SPEED_NUM_20G; 2703 break; 2704 case I40E_REG_SPEED_25_40GB: 2705 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC); 2706 2707 if (reg_val & I40E_REG_MACC_25GB) 2708 link->link_speed = ETH_SPEED_NUM_25G; 2709 else 2710 link->link_speed = ETH_SPEED_NUM_40G; 2711 2712 break; 2713 default: 2714 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed); 2715 break; 2716 } 2717 } 2718 2719 static __rte_always_inline void 2720 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link, 2721 bool enable_lse, int wait_to_complete) 2722 { 2723 #define CHECK_INTERVAL 100 /* 100ms */ 2724 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 2725 uint32_t rep_cnt = MAX_REPEAT_TIME; 2726 struct i40e_link_status link_status; 2727 int status; 2728 2729 memset(&link_status, 0, sizeof(link_status)); 2730 2731 do { 2732 memset(&link_status, 0, sizeof(link_status)); 2733 2734 /* Get link status information from hardware */ 2735 status = i40e_aq_get_link_info(hw, enable_lse, 2736 &link_status, NULL); 2737 if (unlikely(status != I40E_SUCCESS)) { 2738 link->link_speed = ETH_SPEED_NUM_100M; 2739 link->link_duplex = ETH_LINK_FULL_DUPLEX; 2740 PMD_DRV_LOG(ERR, "Failed to get link info"); 2741 return; 2742 } 2743 2744 link->link_status = link_status.link_info & I40E_AQ_LINK_UP; 2745 if (!wait_to_complete || link->link_status) 2746 break; 2747 2748 rte_delay_ms(CHECK_INTERVAL); 2749 } while (--rep_cnt); 2750 2751 /* Parse the link status */ 2752 switch (link_status.link_speed) { 2753 case I40E_LINK_SPEED_100MB: 2754 link->link_speed = ETH_SPEED_NUM_100M; 2755 break; 2756 case I40E_LINK_SPEED_1GB: 2757 link->link_speed = ETH_SPEED_NUM_1G; 2758 break; 2759 case I40E_LINK_SPEED_10GB: 2760 link->link_speed = ETH_SPEED_NUM_10G; 2761 break; 2762 case I40E_LINK_SPEED_20GB: 2763 link->link_speed = ETH_SPEED_NUM_20G; 2764 break; 2765 case I40E_LINK_SPEED_25GB: 2766 link->link_speed = ETH_SPEED_NUM_25G; 2767 break; 2768 case I40E_LINK_SPEED_40GB: 2769 link->link_speed = ETH_SPEED_NUM_40G; 2770 break; 2771 default: 2772 link->link_speed = ETH_SPEED_NUM_100M; 2773 break; 2774 } 2775 } 2776 2777 int 2778 i40e_dev_link_update(struct rte_eth_dev *dev, 2779 int wait_to_complete) 2780 { 2781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2782 struct rte_eth_link link; 2783 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2784 int ret; 2785 2786 memset(&link, 0, sizeof(link)); 2787 2788 /* i40e uses full duplex only */ 2789 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2790 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2791 ETH_LINK_SPEED_FIXED); 2792 2793 if (!wait_to_complete && !enable_lse) 2794 update_link_reg(hw, &link); 2795 else 2796 update_link_aq(hw, &link, enable_lse, wait_to_complete); 2797 2798 ret = rte_eth_linkstatus_set(dev, &link); 2799 i40e_notify_all_vfs_link_status(dev); 2800 2801 return ret; 2802 } 2803 2804 /* Get all the statistics of a VSI */ 2805 void 2806 i40e_update_vsi_stats(struct i40e_vsi *vsi) 2807 { 2808 struct i40e_eth_stats *oes = &vsi->eth_stats_offset; 2809 struct i40e_eth_stats *nes = &vsi->eth_stats; 2810 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2811 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx); 2812 2813 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx), 2814 vsi->offset_loaded, &oes->rx_bytes, 2815 &nes->rx_bytes); 2816 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx), 2817 vsi->offset_loaded, &oes->rx_unicast, 2818 &nes->rx_unicast); 2819 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx), 2820 vsi->offset_loaded, &oes->rx_multicast, 2821 &nes->rx_multicast); 2822 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx), 2823 vsi->offset_loaded, &oes->rx_broadcast, 2824 &nes->rx_broadcast); 2825 /* exclude CRC bytes */ 2826 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 2827 nes->rx_broadcast) * ETHER_CRC_LEN; 2828 2829 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded, 2830 &oes->rx_discards, &nes->rx_discards); 2831 /* GLV_REPC not supported */ 2832 /* GLV_RMPC not supported */ 2833 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded, 2834 &oes->rx_unknown_protocol, 2835 &nes->rx_unknown_protocol); 2836 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx), 2837 vsi->offset_loaded, &oes->tx_bytes, 2838 &nes->tx_bytes); 2839 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx), 2840 vsi->offset_loaded, &oes->tx_unicast, 2841 &nes->tx_unicast); 2842 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx), 2843 vsi->offset_loaded, &oes->tx_multicast, 2844 &nes->tx_multicast); 2845 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx), 2846 vsi->offset_loaded, &oes->tx_broadcast, 2847 &nes->tx_broadcast); 2848 /* GLV_TDPC not supported */ 2849 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded, 2850 &oes->tx_errors, &nes->tx_errors); 2851 vsi->offset_loaded = true; 2852 2853 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************", 2854 vsi->vsi_id); 2855 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 2856 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 2857 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 2858 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 2859 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 2860 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 2861 nes->rx_unknown_protocol); 2862 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 2863 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 2864 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 2865 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 2866 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 2867 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 2868 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************", 2869 vsi->vsi_id); 2870 } 2871 2872 static void 2873 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) 2874 { 2875 unsigned int i; 2876 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */ 2877 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */ 2878 2879 /* Get rx/tx bytes of internal transfer packets */ 2880 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port), 2881 I40E_GLV_GORCL(hw->port), 2882 pf->offset_loaded, 2883 &pf->internal_stats_offset.rx_bytes, 2884 &pf->internal_stats.rx_bytes); 2885 2886 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port), 2887 I40E_GLV_GOTCL(hw->port), 2888 pf->offset_loaded, 2889 &pf->internal_stats_offset.tx_bytes, 2890 &pf->internal_stats.tx_bytes); 2891 /* Get total internal rx packet count */ 2892 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port), 2893 I40E_GLV_UPRCL(hw->port), 2894 pf->offset_loaded, 2895 &pf->internal_stats_offset.rx_unicast, 2896 &pf->internal_stats.rx_unicast); 2897 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port), 2898 I40E_GLV_MPRCL(hw->port), 2899 pf->offset_loaded, 2900 &pf->internal_stats_offset.rx_multicast, 2901 &pf->internal_stats.rx_multicast); 2902 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port), 2903 I40E_GLV_BPRCL(hw->port), 2904 pf->offset_loaded, 2905 &pf->internal_stats_offset.rx_broadcast, 2906 &pf->internal_stats.rx_broadcast); 2907 /* Get total internal tx packet count */ 2908 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port), 2909 I40E_GLV_UPTCL(hw->port), 2910 pf->offset_loaded, 2911 &pf->internal_stats_offset.tx_unicast, 2912 &pf->internal_stats.tx_unicast); 2913 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port), 2914 I40E_GLV_MPTCL(hw->port), 2915 pf->offset_loaded, 2916 &pf->internal_stats_offset.tx_multicast, 2917 &pf->internal_stats.tx_multicast); 2918 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port), 2919 I40E_GLV_BPTCL(hw->port), 2920 pf->offset_loaded, 2921 &pf->internal_stats_offset.tx_broadcast, 2922 &pf->internal_stats.tx_broadcast); 2923 2924 /* exclude CRC size */ 2925 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast + 2926 pf->internal_stats.rx_multicast + 2927 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN; 2928 2929 /* Get statistics of struct i40e_eth_stats */ 2930 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port), 2931 I40E_GLPRT_GORCL(hw->port), 2932 pf->offset_loaded, &os->eth.rx_bytes, 2933 &ns->eth.rx_bytes); 2934 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port), 2935 I40E_GLPRT_UPRCL(hw->port), 2936 pf->offset_loaded, &os->eth.rx_unicast, 2937 &ns->eth.rx_unicast); 2938 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port), 2939 I40E_GLPRT_MPRCL(hw->port), 2940 pf->offset_loaded, &os->eth.rx_multicast, 2941 &ns->eth.rx_multicast); 2942 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port), 2943 I40E_GLPRT_BPRCL(hw->port), 2944 pf->offset_loaded, &os->eth.rx_broadcast, 2945 &ns->eth.rx_broadcast); 2946 /* Workaround: CRC size should not be included in byte statistics, 2947 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet. 2948 */ 2949 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 2950 ns->eth.rx_broadcast) * ETHER_CRC_LEN; 2951 2952 /* exclude internal rx bytes 2953 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before 2954 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative 2955 * value. 2956 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L]. 2957 */ 2958 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes) 2959 ns->eth.rx_bytes = 0; 2960 else 2961 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes; 2962 2963 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast) 2964 ns->eth.rx_unicast = 0; 2965 else 2966 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast; 2967 2968 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast) 2969 ns->eth.rx_multicast = 0; 2970 else 2971 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast; 2972 2973 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast) 2974 ns->eth.rx_broadcast = 0; 2975 else 2976 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast; 2977 2978 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port), 2979 pf->offset_loaded, &os->eth.rx_discards, 2980 &ns->eth.rx_discards); 2981 /* GLPRT_REPC not supported */ 2982 /* GLPRT_RMPC not supported */ 2983 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port), 2984 pf->offset_loaded, 2985 &os->eth.rx_unknown_protocol, 2986 &ns->eth.rx_unknown_protocol); 2987 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port), 2988 I40E_GLPRT_GOTCL(hw->port), 2989 pf->offset_loaded, &os->eth.tx_bytes, 2990 &ns->eth.tx_bytes); 2991 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port), 2992 I40E_GLPRT_UPTCL(hw->port), 2993 pf->offset_loaded, &os->eth.tx_unicast, 2994 &ns->eth.tx_unicast); 2995 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port), 2996 I40E_GLPRT_MPTCL(hw->port), 2997 pf->offset_loaded, &os->eth.tx_multicast, 2998 &ns->eth.tx_multicast); 2999 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port), 3000 I40E_GLPRT_BPTCL(hw->port), 3001 pf->offset_loaded, &os->eth.tx_broadcast, 3002 &ns->eth.tx_broadcast); 3003 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 3004 ns->eth.tx_broadcast) * ETHER_CRC_LEN; 3005 3006 /* exclude internal tx bytes 3007 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before 3008 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative 3009 * value. 3010 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L]. 3011 */ 3012 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes) 3013 ns->eth.tx_bytes = 0; 3014 else 3015 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes; 3016 3017 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast) 3018 ns->eth.tx_unicast = 0; 3019 else 3020 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast; 3021 3022 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast) 3023 ns->eth.tx_multicast = 0; 3024 else 3025 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast; 3026 3027 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast) 3028 ns->eth.tx_broadcast = 0; 3029 else 3030 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast; 3031 3032 /* GLPRT_TEPC not supported */ 3033 3034 /* additional port specific stats */ 3035 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port), 3036 pf->offset_loaded, &os->tx_dropped_link_down, 3037 &ns->tx_dropped_link_down); 3038 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port), 3039 pf->offset_loaded, &os->crc_errors, 3040 &ns->crc_errors); 3041 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port), 3042 pf->offset_loaded, &os->illegal_bytes, 3043 &ns->illegal_bytes); 3044 /* GLPRT_ERRBC not supported */ 3045 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port), 3046 pf->offset_loaded, &os->mac_local_faults, 3047 &ns->mac_local_faults); 3048 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port), 3049 pf->offset_loaded, &os->mac_remote_faults, 3050 &ns->mac_remote_faults); 3051 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port), 3052 pf->offset_loaded, &os->rx_length_errors, 3053 &ns->rx_length_errors); 3054 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port), 3055 pf->offset_loaded, &os->link_xon_rx, 3056 &ns->link_xon_rx); 3057 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 3058 pf->offset_loaded, &os->link_xoff_rx, 3059 &ns->link_xoff_rx); 3060 for (i = 0; i < 8; i++) { 3061 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i), 3062 pf->offset_loaded, 3063 &os->priority_xon_rx[i], 3064 &ns->priority_xon_rx[i]); 3065 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), 3066 pf->offset_loaded, 3067 &os->priority_xoff_rx[i], 3068 &ns->priority_xoff_rx[i]); 3069 } 3070 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port), 3071 pf->offset_loaded, &os->link_xon_tx, 3072 &ns->link_xon_tx); 3073 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 3074 pf->offset_loaded, &os->link_xoff_tx, 3075 &ns->link_xoff_tx); 3076 for (i = 0; i < 8; i++) { 3077 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i), 3078 pf->offset_loaded, 3079 &os->priority_xon_tx[i], 3080 &ns->priority_xon_tx[i]); 3081 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), 3082 pf->offset_loaded, 3083 &os->priority_xoff_tx[i], 3084 &ns->priority_xoff_tx[i]); 3085 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i), 3086 pf->offset_loaded, 3087 &os->priority_xon_2_xoff[i], 3088 &ns->priority_xon_2_xoff[i]); 3089 } 3090 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port), 3091 I40E_GLPRT_PRC64L(hw->port), 3092 pf->offset_loaded, &os->rx_size_64, 3093 &ns->rx_size_64); 3094 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port), 3095 I40E_GLPRT_PRC127L(hw->port), 3096 pf->offset_loaded, &os->rx_size_127, 3097 &ns->rx_size_127); 3098 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port), 3099 I40E_GLPRT_PRC255L(hw->port), 3100 pf->offset_loaded, &os->rx_size_255, 3101 &ns->rx_size_255); 3102 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port), 3103 I40E_GLPRT_PRC511L(hw->port), 3104 pf->offset_loaded, &os->rx_size_511, 3105 &ns->rx_size_511); 3106 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port), 3107 I40E_GLPRT_PRC1023L(hw->port), 3108 pf->offset_loaded, &os->rx_size_1023, 3109 &ns->rx_size_1023); 3110 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port), 3111 I40E_GLPRT_PRC1522L(hw->port), 3112 pf->offset_loaded, &os->rx_size_1522, 3113 &ns->rx_size_1522); 3114 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port), 3115 I40E_GLPRT_PRC9522L(hw->port), 3116 pf->offset_loaded, &os->rx_size_big, 3117 &ns->rx_size_big); 3118 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port), 3119 pf->offset_loaded, &os->rx_undersize, 3120 &ns->rx_undersize); 3121 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port), 3122 pf->offset_loaded, &os->rx_fragments, 3123 &ns->rx_fragments); 3124 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port), 3125 pf->offset_loaded, &os->rx_oversize, 3126 &ns->rx_oversize); 3127 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port), 3128 pf->offset_loaded, &os->rx_jabber, 3129 &ns->rx_jabber); 3130 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port), 3131 I40E_GLPRT_PTC64L(hw->port), 3132 pf->offset_loaded, &os->tx_size_64, 3133 &ns->tx_size_64); 3134 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port), 3135 I40E_GLPRT_PTC127L(hw->port), 3136 pf->offset_loaded, &os->tx_size_127, 3137 &ns->tx_size_127); 3138 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port), 3139 I40E_GLPRT_PTC255L(hw->port), 3140 pf->offset_loaded, &os->tx_size_255, 3141 &ns->tx_size_255); 3142 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port), 3143 I40E_GLPRT_PTC511L(hw->port), 3144 pf->offset_loaded, &os->tx_size_511, 3145 &ns->tx_size_511); 3146 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port), 3147 I40E_GLPRT_PTC1023L(hw->port), 3148 pf->offset_loaded, &os->tx_size_1023, 3149 &ns->tx_size_1023); 3150 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port), 3151 I40E_GLPRT_PTC1522L(hw->port), 3152 pf->offset_loaded, &os->tx_size_1522, 3153 &ns->tx_size_1522); 3154 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port), 3155 I40E_GLPRT_PTC9522L(hw->port), 3156 pf->offset_loaded, &os->tx_size_big, 3157 &ns->tx_size_big); 3158 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index), 3159 pf->offset_loaded, 3160 &os->fd_sb_match, &ns->fd_sb_match); 3161 /* GLPRT_MSPDC not supported */ 3162 /* GLPRT_XEC not supported */ 3163 3164 pf->offset_loaded = true; 3165 3166 if (pf->main_vsi) 3167 i40e_update_vsi_stats(pf->main_vsi); 3168 } 3169 3170 /* Get all statistics of a port */ 3171 static int 3172 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3173 { 3174 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3175 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3176 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */ 3177 struct i40e_vsi *vsi; 3178 unsigned i; 3179 3180 /* call read registers - updates values, now write them to struct */ 3181 i40e_read_stats_registers(pf, hw); 3182 3183 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 3184 pf->main_vsi->eth_stats.rx_multicast + 3185 pf->main_vsi->eth_stats.rx_broadcast - 3186 pf->main_vsi->eth_stats.rx_discards; 3187 stats->opackets = ns->eth.tx_unicast + 3188 ns->eth.tx_multicast + 3189 ns->eth.tx_broadcast; 3190 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 3191 stats->obytes = ns->eth.tx_bytes; 3192 stats->oerrors = ns->eth.tx_errors + 3193 pf->main_vsi->eth_stats.tx_errors; 3194 3195 /* Rx Errors */ 3196 stats->imissed = ns->eth.rx_discards + 3197 pf->main_vsi->eth_stats.rx_discards; 3198 stats->ierrors = ns->crc_errors + 3199 ns->rx_length_errors + ns->rx_undersize + 3200 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 3201 3202 if (pf->vfs) { 3203 for (i = 0; i < pf->vf_num; i++) { 3204 vsi = pf->vfs[i].vsi; 3205 i40e_update_vsi_stats(vsi); 3206 3207 stats->ipackets += (vsi->eth_stats.rx_unicast + 3208 vsi->eth_stats.rx_multicast + 3209 vsi->eth_stats.rx_broadcast - 3210 vsi->eth_stats.rx_discards); 3211 stats->ibytes += vsi->eth_stats.rx_bytes; 3212 stats->oerrors += vsi->eth_stats.tx_errors; 3213 stats->imissed += vsi->eth_stats.rx_discards; 3214 } 3215 } 3216 3217 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************"); 3218 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 3219 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 3220 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast); 3221 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast); 3222 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards); 3223 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3224 ns->eth.rx_unknown_protocol); 3225 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 3226 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 3227 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast); 3228 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast); 3229 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards); 3230 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 3231 3232 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 3233 ns->tx_dropped_link_down); 3234 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 3235 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 3236 ns->illegal_bytes); 3237 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 3238 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 3239 ns->mac_local_faults); 3240 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 3241 ns->mac_remote_faults); 3242 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"", 3243 ns->rx_length_errors); 3244 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 3245 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 3246 for (i = 0; i < 8; i++) { 3247 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"", 3248 i, ns->priority_xon_rx[i]); 3249 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"", 3250 i, ns->priority_xoff_rx[i]); 3251 } 3252 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 3253 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 3254 for (i = 0; i < 8; i++) { 3255 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"", 3256 i, ns->priority_xon_tx[i]); 3257 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"", 3258 i, ns->priority_xoff_tx[i]); 3259 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"", 3260 i, ns->priority_xon_2_xoff[i]); 3261 } 3262 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 3263 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 3264 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 3265 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 3266 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 3267 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 3268 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 3269 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 3270 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 3271 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 3272 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 3273 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 3274 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 3275 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 3276 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 3277 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 3278 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 3279 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 3280 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"", 3281 ns->mac_short_packet_dropped); 3282 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"", 3283 ns->checksum_error); 3284 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match); 3285 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************"); 3286 return 0; 3287 } 3288 3289 /* Reset the statistics */ 3290 static void 3291 i40e_dev_stats_reset(struct rte_eth_dev *dev) 3292 { 3293 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3294 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3295 3296 /* Mark PF and VSI stats to update the offset, aka "reset" */ 3297 pf->offset_loaded = false; 3298 if (pf->main_vsi) 3299 pf->main_vsi->offset_loaded = false; 3300 3301 /* read the stats, reading current register values into offset */ 3302 i40e_read_stats_registers(pf, hw); 3303 } 3304 3305 static uint32_t 3306 i40e_xstats_calc_num(void) 3307 { 3308 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + 3309 (I40E_NB_RXQ_PRIO_XSTATS * 8) + 3310 (I40E_NB_TXQ_PRIO_XSTATS * 8); 3311 } 3312 3313 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3314 struct rte_eth_xstat_name *xstats_names, 3315 __rte_unused unsigned limit) 3316 { 3317 unsigned count = 0; 3318 unsigned i, prio; 3319 3320 if (xstats_names == NULL) 3321 return i40e_xstats_calc_num(); 3322 3323 /* Note: limit checked in rte_eth_xstats_names() */ 3324 3325 /* Get stats from i40e_eth_stats struct */ 3326 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) { 3327 snprintf(xstats_names[count].name, 3328 sizeof(xstats_names[count].name), 3329 "%s", rte_i40e_stats_strings[i].name); 3330 count++; 3331 } 3332 3333 /* Get individiual stats from i40e_hw_port struct */ 3334 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) { 3335 snprintf(xstats_names[count].name, 3336 sizeof(xstats_names[count].name), 3337 "%s", rte_i40e_hw_port_strings[i].name); 3338 count++; 3339 } 3340 3341 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) { 3342 for (prio = 0; prio < 8; prio++) { 3343 snprintf(xstats_names[count].name, 3344 sizeof(xstats_names[count].name), 3345 "rx_priority%u_%s", prio, 3346 rte_i40e_rxq_prio_strings[i].name); 3347 count++; 3348 } 3349 } 3350 3351 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) { 3352 for (prio = 0; prio < 8; prio++) { 3353 snprintf(xstats_names[count].name, 3354 sizeof(xstats_names[count].name), 3355 "tx_priority%u_%s", prio, 3356 rte_i40e_txq_prio_strings[i].name); 3357 count++; 3358 } 3359 } 3360 return count; 3361 } 3362 3363 static int 3364 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3365 unsigned n) 3366 { 3367 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3368 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3369 unsigned i, count, prio; 3370 struct i40e_hw_port_stats *hw_stats = &pf->stats; 3371 3372 count = i40e_xstats_calc_num(); 3373 if (n < count) 3374 return count; 3375 3376 i40e_read_stats_registers(pf, hw); 3377 3378 if (xstats == NULL) 3379 return 0; 3380 3381 count = 0; 3382 3383 /* Get stats from i40e_eth_stats struct */ 3384 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) { 3385 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) + 3386 rte_i40e_stats_strings[i].offset); 3387 xstats[count].id = count; 3388 count++; 3389 } 3390 3391 /* Get individiual stats from i40e_hw_port struct */ 3392 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) { 3393 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3394 rte_i40e_hw_port_strings[i].offset); 3395 xstats[count].id = count; 3396 count++; 3397 } 3398 3399 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) { 3400 for (prio = 0; prio < 8; prio++) { 3401 xstats[count].value = 3402 *(uint64_t *)(((char *)hw_stats) + 3403 rte_i40e_rxq_prio_strings[i].offset + 3404 (sizeof(uint64_t) * prio)); 3405 xstats[count].id = count; 3406 count++; 3407 } 3408 } 3409 3410 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) { 3411 for (prio = 0; prio < 8; prio++) { 3412 xstats[count].value = 3413 *(uint64_t *)(((char *)hw_stats) + 3414 rte_i40e_txq_prio_strings[i].offset + 3415 (sizeof(uint64_t) * prio)); 3416 xstats[count].id = count; 3417 count++; 3418 } 3419 } 3420 3421 return count; 3422 } 3423 3424 static int 3425 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev, 3426 __rte_unused uint16_t queue_id, 3427 __rte_unused uint8_t stat_idx, 3428 __rte_unused uint8_t is_rx) 3429 { 3430 PMD_INIT_FUNC_TRACE(); 3431 3432 return -ENOSYS; 3433 } 3434 3435 static int 3436 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3437 { 3438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3439 u32 full_ver; 3440 u8 ver, patch; 3441 u16 build; 3442 int ret; 3443 3444 full_ver = hw->nvm.oem_ver; 3445 ver = (u8)(full_ver >> 24); 3446 build = (u16)((full_ver >> 8) & 0xffff); 3447 patch = (u8)(full_ver & 0xff); 3448 3449 ret = snprintf(fw_version, fw_size, 3450 "%d.%d%d 0x%08x %d.%d.%d", 3451 ((hw->nvm.version >> 12) & 0xf), 3452 ((hw->nvm.version >> 4) & 0xff), 3453 (hw->nvm.version & 0xf), hw->nvm.eetrack, 3454 ver, build, patch); 3455 3456 ret += 1; /* add the size of '\0' */ 3457 if (fw_size < (u32)ret) 3458 return ret; 3459 else 3460 return 0; 3461 } 3462 3463 static void 3464 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3465 { 3466 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3467 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3468 struct i40e_vsi *vsi = pf->main_vsi; 3469 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3470 3471 dev_info->max_rx_queues = vsi->nb_qps; 3472 dev_info->max_tx_queues = vsi->nb_qps; 3473 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN; 3474 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX; 3475 dev_info->max_mac_addrs = vsi->max_macaddrs; 3476 dev_info->max_vfs = pci_dev->max_vfs; 3477 dev_info->rx_queue_offload_capa = 0; 3478 dev_info->rx_offload_capa = 3479 DEV_RX_OFFLOAD_VLAN_STRIP | 3480 DEV_RX_OFFLOAD_QINQ_STRIP | 3481 DEV_RX_OFFLOAD_IPV4_CKSUM | 3482 DEV_RX_OFFLOAD_UDP_CKSUM | 3483 DEV_RX_OFFLOAD_TCP_CKSUM | 3484 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3485 DEV_RX_OFFLOAD_KEEP_CRC | 3486 DEV_RX_OFFLOAD_SCATTER | 3487 DEV_RX_OFFLOAD_VLAN_EXTEND | 3488 DEV_RX_OFFLOAD_VLAN_FILTER | 3489 DEV_RX_OFFLOAD_JUMBO_FRAME; 3490 3491 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3492 dev_info->tx_offload_capa = 3493 DEV_TX_OFFLOAD_VLAN_INSERT | 3494 DEV_TX_OFFLOAD_QINQ_INSERT | 3495 DEV_TX_OFFLOAD_IPV4_CKSUM | 3496 DEV_TX_OFFLOAD_UDP_CKSUM | 3497 DEV_TX_OFFLOAD_TCP_CKSUM | 3498 DEV_TX_OFFLOAD_SCTP_CKSUM | 3499 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3500 DEV_TX_OFFLOAD_TCP_TSO | 3501 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 3502 DEV_TX_OFFLOAD_GRE_TNL_TSO | 3503 DEV_TX_OFFLOAD_IPIP_TNL_TSO | 3504 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 3505 DEV_TX_OFFLOAD_MULTI_SEGS | 3506 dev_info->tx_queue_offload_capa; 3507 dev_info->dev_capa = 3508 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 3509 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 3510 3511 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 3512 sizeof(uint32_t); 3513 dev_info->reta_size = pf->hash_lut_size; 3514 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask; 3515 3516 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3517 .rx_thresh = { 3518 .pthresh = I40E_DEFAULT_RX_PTHRESH, 3519 .hthresh = I40E_DEFAULT_RX_HTHRESH, 3520 .wthresh = I40E_DEFAULT_RX_WTHRESH, 3521 }, 3522 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH, 3523 .rx_drop_en = 0, 3524 .offloads = 0, 3525 }; 3526 3527 dev_info->default_txconf = (struct rte_eth_txconf) { 3528 .tx_thresh = { 3529 .pthresh = I40E_DEFAULT_TX_PTHRESH, 3530 .hthresh = I40E_DEFAULT_TX_HTHRESH, 3531 .wthresh = I40E_DEFAULT_TX_WTHRESH, 3532 }, 3533 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH, 3534 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH, 3535 .offloads = 0, 3536 }; 3537 3538 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3539 .nb_max = I40E_MAX_RING_DESC, 3540 .nb_min = I40E_MIN_RING_DESC, 3541 .nb_align = I40E_ALIGN_RING_DESC, 3542 }; 3543 3544 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3545 .nb_max = I40E_MAX_RING_DESC, 3546 .nb_min = I40E_MIN_RING_DESC, 3547 .nb_align = I40E_ALIGN_RING_DESC, 3548 .nb_seg_max = I40E_TX_MAX_SEG, 3549 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG, 3550 }; 3551 3552 if (pf->flags & I40E_FLAG_VMDQ) { 3553 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi; 3554 dev_info->vmdq_queue_base = dev_info->max_rx_queues; 3555 dev_info->vmdq_queue_num = pf->vmdq_nb_qps * 3556 pf->max_nb_vmdq_vsi; 3557 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE; 3558 dev_info->max_rx_queues += dev_info->vmdq_queue_num; 3559 dev_info->max_tx_queues += dev_info->vmdq_queue_num; 3560 } 3561 3562 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { 3563 /* For XL710 */ 3564 dev_info->speed_capa = ETH_LINK_SPEED_40G; 3565 dev_info->default_rxportconf.nb_queues = 2; 3566 dev_info->default_txportconf.nb_queues = 2; 3567 if (dev->data->nb_rx_queues == 1) 3568 dev_info->default_rxportconf.ring_size = 2048; 3569 else 3570 dev_info->default_rxportconf.ring_size = 1024; 3571 if (dev->data->nb_tx_queues == 1) 3572 dev_info->default_txportconf.ring_size = 1024; 3573 else 3574 dev_info->default_txportconf.ring_size = 512; 3575 3576 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) { 3577 /* For XXV710 */ 3578 dev_info->speed_capa = ETH_LINK_SPEED_25G; 3579 dev_info->default_rxportconf.nb_queues = 1; 3580 dev_info->default_txportconf.nb_queues = 1; 3581 dev_info->default_rxportconf.ring_size = 256; 3582 dev_info->default_txportconf.ring_size = 256; 3583 } else { 3584 /* For X710 */ 3585 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3586 dev_info->default_rxportconf.nb_queues = 1; 3587 dev_info->default_txportconf.nb_queues = 1; 3588 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) { 3589 dev_info->default_rxportconf.ring_size = 512; 3590 dev_info->default_txportconf.ring_size = 256; 3591 } else { 3592 dev_info->default_rxportconf.ring_size = 256; 3593 dev_info->default_txportconf.ring_size = 256; 3594 } 3595 } 3596 dev_info->default_rxportconf.burst_size = 32; 3597 dev_info->default_txportconf.burst_size = 32; 3598 } 3599 3600 static int 3601 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3602 { 3603 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3604 struct i40e_vsi *vsi = pf->main_vsi; 3605 PMD_INIT_FUNC_TRACE(); 3606 3607 if (on) 3608 return i40e_vsi_add_vlan(vsi, vlan_id); 3609 else 3610 return i40e_vsi_delete_vlan(vsi, vlan_id); 3611 } 3612 3613 static int 3614 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev, 3615 enum rte_vlan_type vlan_type, 3616 uint16_t tpid, int qinq) 3617 { 3618 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3619 uint64_t reg_r = 0; 3620 uint64_t reg_w = 0; 3621 uint16_t reg_id = 3; 3622 int ret; 3623 3624 if (qinq) { 3625 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3626 reg_id = 2; 3627 } 3628 3629 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), 3630 ®_r, NULL); 3631 if (ret != I40E_SUCCESS) { 3632 PMD_DRV_LOG(ERR, 3633 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]", 3634 reg_id); 3635 return -EIO; 3636 } 3637 PMD_DRV_LOG(DEBUG, 3638 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64, 3639 reg_id, reg_r); 3640 3641 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK)); 3642 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT); 3643 if (reg_r == reg_w) { 3644 PMD_DRV_LOG(DEBUG, "No need to write"); 3645 return 0; 3646 } 3647 3648 ret = i40e_aq_debug_write_global_register(hw, 3649 I40E_GL_SWT_L2TAGCTRL(reg_id), 3650 reg_w, NULL); 3651 if (ret != I40E_SUCCESS) { 3652 PMD_DRV_LOG(ERR, 3653 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]", 3654 reg_id); 3655 return -EIO; 3656 } 3657 PMD_DRV_LOG(DEBUG, 3658 "Global register 0x%08x is changed with value 0x%08x", 3659 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w); 3660 3661 return 0; 3662 } 3663 3664 static int 3665 i40e_vlan_tpid_set(struct rte_eth_dev *dev, 3666 enum rte_vlan_type vlan_type, 3667 uint16_t tpid) 3668 { 3669 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3670 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3671 int qinq = dev->data->dev_conf.rxmode.offloads & 3672 DEV_RX_OFFLOAD_VLAN_EXTEND; 3673 int ret = 0; 3674 3675 if ((vlan_type != ETH_VLAN_TYPE_INNER && 3676 vlan_type != ETH_VLAN_TYPE_OUTER) || 3677 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) { 3678 PMD_DRV_LOG(ERR, 3679 "Unsupported vlan type."); 3680 return -EINVAL; 3681 } 3682 3683 if (pf->support_multi_driver) { 3684 PMD_DRV_LOG(ERR, "Setting TPID is not supported."); 3685 return -ENOTSUP; 3686 } 3687 3688 /* 802.1ad frames ability is added in NVM API 1.7*/ 3689 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 3690 if (qinq) { 3691 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3692 hw->first_tag = rte_cpu_to_le_16(tpid); 3693 else if (vlan_type == ETH_VLAN_TYPE_INNER) 3694 hw->second_tag = rte_cpu_to_le_16(tpid); 3695 } else { 3696 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3697 hw->second_tag = rte_cpu_to_le_16(tpid); 3698 } 3699 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL); 3700 if (ret != I40E_SUCCESS) { 3701 PMD_DRV_LOG(ERR, 3702 "Set switch config failed aq_err: %d", 3703 hw->aq.asq_last_status); 3704 ret = -EIO; 3705 } 3706 } else 3707 /* If NVM API < 1.7, keep the register setting */ 3708 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type, 3709 tpid, qinq); 3710 3711 return ret; 3712 } 3713 3714 static int 3715 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) 3716 { 3717 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3718 struct i40e_vsi *vsi = pf->main_vsi; 3719 struct rte_eth_rxmode *rxmode; 3720 3721 rxmode = &dev->data->dev_conf.rxmode; 3722 if (mask & ETH_VLAN_FILTER_MASK) { 3723 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 3724 i40e_vsi_config_vlan_filter(vsi, TRUE); 3725 else 3726 i40e_vsi_config_vlan_filter(vsi, FALSE); 3727 } 3728 3729 if (mask & ETH_VLAN_STRIP_MASK) { 3730 /* Enable or disable VLAN stripping */ 3731 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 3732 i40e_vsi_config_vlan_stripping(vsi, TRUE); 3733 else 3734 i40e_vsi_config_vlan_stripping(vsi, FALSE); 3735 } 3736 3737 if (mask & ETH_VLAN_EXTEND_MASK) { 3738 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) { 3739 i40e_vsi_config_double_vlan(vsi, TRUE); 3740 /* Set global registers with default ethertype. */ 3741 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 3742 ETHER_TYPE_VLAN); 3743 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, 3744 ETHER_TYPE_VLAN); 3745 } 3746 else 3747 i40e_vsi_config_double_vlan(vsi, FALSE); 3748 } 3749 3750 return 0; 3751 } 3752 3753 static void 3754 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev, 3755 __rte_unused uint16_t queue, 3756 __rte_unused int on) 3757 { 3758 PMD_INIT_FUNC_TRACE(); 3759 } 3760 3761 static int 3762 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 3763 { 3764 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3765 struct i40e_vsi *vsi = pf->main_vsi; 3766 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi); 3767 struct i40e_vsi_vlan_pvid_info info; 3768 3769 memset(&info, 0, sizeof(info)); 3770 info.on = on; 3771 if (info.on) 3772 info.config.pvid = pvid; 3773 else { 3774 info.config.reject.tagged = 3775 data->dev_conf.txmode.hw_vlan_reject_tagged; 3776 info.config.reject.untagged = 3777 data->dev_conf.txmode.hw_vlan_reject_untagged; 3778 } 3779 3780 return i40e_vsi_vlan_pvid_set(vsi, &info); 3781 } 3782 3783 static int 3784 i40e_dev_led_on(struct rte_eth_dev *dev) 3785 { 3786 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3787 uint32_t mode = i40e_led_get(hw); 3788 3789 if (mode == 0) 3790 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */ 3791 3792 return 0; 3793 } 3794 3795 static int 3796 i40e_dev_led_off(struct rte_eth_dev *dev) 3797 { 3798 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3799 uint32_t mode = i40e_led_get(hw); 3800 3801 if (mode != 0) 3802 i40e_led_set(hw, 0, false); 3803 3804 return 0; 3805 } 3806 3807 static int 3808 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3809 { 3810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3811 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3812 3813 fc_conf->pause_time = pf->fc_conf.pause_time; 3814 3815 /* read out from register, in case they are modified by other port */ 3816 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = 3817 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT; 3818 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = 3819 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT; 3820 3821 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]; 3822 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]; 3823 3824 /* Return current mode according to actual setting*/ 3825 switch (hw->fc.current_mode) { 3826 case I40E_FC_FULL: 3827 fc_conf->mode = RTE_FC_FULL; 3828 break; 3829 case I40E_FC_TX_PAUSE: 3830 fc_conf->mode = RTE_FC_TX_PAUSE; 3831 break; 3832 case I40E_FC_RX_PAUSE: 3833 fc_conf->mode = RTE_FC_RX_PAUSE; 3834 break; 3835 case I40E_FC_NONE: 3836 default: 3837 fc_conf->mode = RTE_FC_NONE; 3838 }; 3839 3840 return 0; 3841 } 3842 3843 static int 3844 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3845 { 3846 uint32_t mflcn_reg, fctrl_reg, reg; 3847 uint32_t max_high_water; 3848 uint8_t i, aq_failure; 3849 int err; 3850 struct i40e_hw *hw; 3851 struct i40e_pf *pf; 3852 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = { 3853 [RTE_FC_NONE] = I40E_FC_NONE, 3854 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE, 3855 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE, 3856 [RTE_FC_FULL] = I40E_FC_FULL 3857 }; 3858 3859 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */ 3860 3861 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT; 3862 if ((fc_conf->high_water > max_high_water) || 3863 (fc_conf->high_water < fc_conf->low_water)) { 3864 PMD_INIT_LOG(ERR, 3865 "Invalid high/low water setup value in KB, High_water must be <= %d.", 3866 max_high_water); 3867 return -EINVAL; 3868 } 3869 3870 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3871 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3872 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode]; 3873 3874 pf->fc_conf.pause_time = fc_conf->pause_time; 3875 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water; 3876 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water; 3877 3878 PMD_INIT_FUNC_TRACE(); 3879 3880 /* All the link flow control related enable/disable register 3881 * configuration is handle by the F/W 3882 */ 3883 err = i40e_set_fc(hw, &aq_failure, true); 3884 if (err < 0) 3885 return -ENOSYS; 3886 3887 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { 3888 /* Configure flow control refresh threshold, 3889 * the value for stat_tx_pause_refresh_timer[8] 3890 * is used for global pause operation. 3891 */ 3892 3893 I40E_WRITE_REG(hw, 3894 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8), 3895 pf->fc_conf.pause_time); 3896 3897 /* configure the timer value included in transmitted pause 3898 * frame, 3899 * the value for stat_tx_pause_quanta[8] is used for global 3900 * pause operation 3901 */ 3902 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8), 3903 pf->fc_conf.pause_time); 3904 3905 fctrl_reg = I40E_READ_REG(hw, 3906 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL); 3907 3908 if (fc_conf->mac_ctrl_frame_fwd != 0) 3909 fctrl_reg |= I40E_PRTMAC_FWD_CTRL; 3910 else 3911 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL; 3912 3913 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL, 3914 fctrl_reg); 3915 } else { 3916 /* Configure pause time (2 TCs per register) */ 3917 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001; 3918 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++) 3919 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg); 3920 3921 /* Configure flow control refresh threshold value */ 3922 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV, 3923 pf->fc_conf.pause_time / 2); 3924 3925 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); 3926 3927 /* set or clear MFLCN.PMCF & MFLCN.DPF bits 3928 *depending on configuration 3929 */ 3930 if (fc_conf->mac_ctrl_frame_fwd != 0) { 3931 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK; 3932 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK; 3933 } else { 3934 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK; 3935 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK; 3936 } 3937 3938 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg); 3939 } 3940 3941 if (!pf->support_multi_driver) { 3942 /* config water marker both based on the packets and bytes */ 3943 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW, 3944 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] 3945 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE); 3946 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW, 3947 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] 3948 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE); 3949 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW, 3950 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] 3951 << I40E_KILOSHIFT); 3952 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW, 3953 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] 3954 << I40E_KILOSHIFT); 3955 } else { 3956 PMD_DRV_LOG(ERR, 3957 "Water marker configuration is not supported."); 3958 } 3959 3960 I40E_WRITE_FLUSH(hw); 3961 3962 return 0; 3963 } 3964 3965 static int 3966 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev, 3967 __rte_unused struct rte_eth_pfc_conf *pfc_conf) 3968 { 3969 PMD_INIT_FUNC_TRACE(); 3970 3971 return -ENOSYS; 3972 } 3973 3974 /* Add a MAC address, and update filters */ 3975 static int 3976 i40e_macaddr_add(struct rte_eth_dev *dev, 3977 struct ether_addr *mac_addr, 3978 __rte_unused uint32_t index, 3979 uint32_t pool) 3980 { 3981 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3982 struct i40e_mac_filter_info mac_filter; 3983 struct i40e_vsi *vsi; 3984 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 3985 int ret; 3986 3987 /* If VMDQ not enabled or configured, return */ 3988 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) || 3989 !pf->nb_cfg_vmdq_vsi)) { 3990 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u", 3991 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled", 3992 pool); 3993 return -ENOTSUP; 3994 } 3995 3996 if (pool > pf->nb_cfg_vmdq_vsi) { 3997 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u", 3998 pool, pf->nb_cfg_vmdq_vsi); 3999 return -EINVAL; 4000 } 4001 4002 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN); 4003 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 4004 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 4005 else 4006 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH; 4007 4008 if (pool == 0) 4009 vsi = pf->main_vsi; 4010 else 4011 vsi = pf->vmdq[pool - 1].vsi; 4012 4013 ret = i40e_vsi_add_mac(vsi, &mac_filter); 4014 if (ret != I40E_SUCCESS) { 4015 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter"); 4016 return -ENODEV; 4017 } 4018 return 0; 4019 } 4020 4021 /* Remove a MAC address, and update filters */ 4022 static void 4023 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 4024 { 4025 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4026 struct i40e_vsi *vsi; 4027 struct rte_eth_dev_data *data = dev->data; 4028 struct ether_addr *macaddr; 4029 int ret; 4030 uint32_t i; 4031 uint64_t pool_sel; 4032 4033 macaddr = &(data->mac_addrs[index]); 4034 4035 pool_sel = dev->data->mac_pool_sel[index]; 4036 4037 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) { 4038 if (pool_sel & (1ULL << i)) { 4039 if (i == 0) 4040 vsi = pf->main_vsi; 4041 else { 4042 /* No VMDQ pool enabled or configured */ 4043 if (!(pf->flags & I40E_FLAG_VMDQ) || 4044 (i > pf->nb_cfg_vmdq_vsi)) { 4045 PMD_DRV_LOG(ERR, 4046 "No VMDQ pool enabled/configured"); 4047 return; 4048 } 4049 vsi = pf->vmdq[i - 1].vsi; 4050 } 4051 ret = i40e_vsi_delete_mac(vsi, macaddr); 4052 4053 if (ret) { 4054 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter"); 4055 return; 4056 } 4057 } 4058 } 4059 } 4060 4061 /* Set perfect match or hash match of MAC and VLAN for a VF */ 4062 static int 4063 i40e_vf_mac_filter_set(struct i40e_pf *pf, 4064 struct rte_eth_mac_filter *filter, 4065 bool add) 4066 { 4067 struct i40e_hw *hw; 4068 struct i40e_mac_filter_info mac_filter; 4069 struct ether_addr old_mac; 4070 struct ether_addr *new_mac; 4071 struct i40e_pf_vf *vf = NULL; 4072 uint16_t vf_id; 4073 int ret; 4074 4075 if (pf == NULL) { 4076 PMD_DRV_LOG(ERR, "Invalid PF argument."); 4077 return -EINVAL; 4078 } 4079 hw = I40E_PF_TO_HW(pf); 4080 4081 if (filter == NULL) { 4082 PMD_DRV_LOG(ERR, "Invalid mac filter argument."); 4083 return -EINVAL; 4084 } 4085 4086 new_mac = &filter->mac_addr; 4087 4088 if (is_zero_ether_addr(new_mac)) { 4089 PMD_DRV_LOG(ERR, "Invalid ethernet address."); 4090 return -EINVAL; 4091 } 4092 4093 vf_id = filter->dst_id; 4094 4095 if (vf_id > pf->vf_num - 1 || !pf->vfs) { 4096 PMD_DRV_LOG(ERR, "Invalid argument."); 4097 return -EINVAL; 4098 } 4099 vf = &pf->vfs[vf_id]; 4100 4101 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) { 4102 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address."); 4103 return -EINVAL; 4104 } 4105 4106 if (add) { 4107 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN); 4108 rte_memcpy(hw->mac.addr, new_mac->addr_bytes, 4109 ETHER_ADDR_LEN); 4110 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr, 4111 ETHER_ADDR_LEN); 4112 4113 mac_filter.filter_type = filter->filter_type; 4114 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter); 4115 if (ret != I40E_SUCCESS) { 4116 PMD_DRV_LOG(ERR, "Failed to add MAC filter."); 4117 return -1; 4118 } 4119 ether_addr_copy(new_mac, &pf->dev_addr); 4120 } else { 4121 rte_memcpy(hw->mac.addr, hw->mac.perm_addr, 4122 ETHER_ADDR_LEN); 4123 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr); 4124 if (ret != I40E_SUCCESS) { 4125 PMD_DRV_LOG(ERR, "Failed to delete MAC filter."); 4126 return -1; 4127 } 4128 4129 /* Clear device address as it has been removed */ 4130 if (is_same_ether_addr(&(pf->dev_addr), new_mac)) 4131 memset(&pf->dev_addr, 0, sizeof(struct ether_addr)); 4132 } 4133 4134 return 0; 4135 } 4136 4137 /* MAC filter handle */ 4138 static int 4139 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op, 4140 void *arg) 4141 { 4142 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4143 struct rte_eth_mac_filter *filter; 4144 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4145 int ret = I40E_NOT_SUPPORTED; 4146 4147 filter = (struct rte_eth_mac_filter *)(arg); 4148 4149 switch (filter_op) { 4150 case RTE_ETH_FILTER_NOP: 4151 ret = I40E_SUCCESS; 4152 break; 4153 case RTE_ETH_FILTER_ADD: 4154 i40e_pf_disable_irq0(hw); 4155 if (filter->is_vf) 4156 ret = i40e_vf_mac_filter_set(pf, filter, 1); 4157 i40e_pf_enable_irq0(hw); 4158 break; 4159 case RTE_ETH_FILTER_DELETE: 4160 i40e_pf_disable_irq0(hw); 4161 if (filter->is_vf) 4162 ret = i40e_vf_mac_filter_set(pf, filter, 0); 4163 i40e_pf_enable_irq0(hw); 4164 break; 4165 default: 4166 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 4167 ret = I40E_ERR_PARAM; 4168 break; 4169 } 4170 4171 return ret; 4172 } 4173 4174 static int 4175 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4176 { 4177 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 4178 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 4179 uint32_t reg; 4180 int ret; 4181 4182 if (!lut) 4183 return -EINVAL; 4184 4185 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 4186 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE, 4187 lut, lut_size); 4188 if (ret) { 4189 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 4190 return ret; 4191 } 4192 } else { 4193 uint32_t *lut_dw = (uint32_t *)lut; 4194 uint16_t i, lut_size_dw = lut_size / 4; 4195 4196 if (vsi->type == I40E_VSI_SRIOV) { 4197 for (i = 0; i <= lut_size_dw; i++) { 4198 reg = I40E_VFQF_HLUT1(i, vsi->user_param); 4199 lut_dw[i] = i40e_read_rx_ctl(hw, reg); 4200 } 4201 } else { 4202 for (i = 0; i < lut_size_dw; i++) 4203 lut_dw[i] = I40E_READ_REG(hw, 4204 I40E_PFQF_HLUT(i)); 4205 } 4206 } 4207 4208 return 0; 4209 } 4210 4211 int 4212 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4213 { 4214 struct i40e_pf *pf; 4215 struct i40e_hw *hw; 4216 int ret; 4217 4218 if (!vsi || !lut) 4219 return -EINVAL; 4220 4221 pf = I40E_VSI_TO_PF(vsi); 4222 hw = I40E_VSI_TO_HW(vsi); 4223 4224 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 4225 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE, 4226 lut, lut_size); 4227 if (ret) { 4228 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 4229 return ret; 4230 } 4231 } else { 4232 uint32_t *lut_dw = (uint32_t *)lut; 4233 uint16_t i, lut_size_dw = lut_size / 4; 4234 4235 if (vsi->type == I40E_VSI_SRIOV) { 4236 for (i = 0; i < lut_size_dw; i++) 4237 I40E_WRITE_REG( 4238 hw, 4239 I40E_VFQF_HLUT1(i, vsi->user_param), 4240 lut_dw[i]); 4241 } else { 4242 for (i = 0; i < lut_size_dw; i++) 4243 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), 4244 lut_dw[i]); 4245 } 4246 I40E_WRITE_FLUSH(hw); 4247 } 4248 4249 return 0; 4250 } 4251 4252 static int 4253 i40e_dev_rss_reta_update(struct rte_eth_dev *dev, 4254 struct rte_eth_rss_reta_entry64 *reta_conf, 4255 uint16_t reta_size) 4256 { 4257 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4258 uint16_t i, lut_size = pf->hash_lut_size; 4259 uint16_t idx, shift; 4260 uint8_t *lut; 4261 int ret; 4262 4263 if (reta_size != lut_size || 4264 reta_size > ETH_RSS_RETA_SIZE_512) { 4265 PMD_DRV_LOG(ERR, 4266 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)", 4267 reta_size, lut_size); 4268 return -EINVAL; 4269 } 4270 4271 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 4272 if (!lut) { 4273 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4274 return -ENOMEM; 4275 } 4276 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size); 4277 if (ret) 4278 goto out; 4279 for (i = 0; i < reta_size; i++) { 4280 idx = i / RTE_RETA_GROUP_SIZE; 4281 shift = i % RTE_RETA_GROUP_SIZE; 4282 if (reta_conf[idx].mask & (1ULL << shift)) 4283 lut[i] = reta_conf[idx].reta[shift]; 4284 } 4285 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size); 4286 4287 pf->adapter->rss_reta_updated = 1; 4288 4289 out: 4290 rte_free(lut); 4291 4292 return ret; 4293 } 4294 4295 static int 4296 i40e_dev_rss_reta_query(struct rte_eth_dev *dev, 4297 struct rte_eth_rss_reta_entry64 *reta_conf, 4298 uint16_t reta_size) 4299 { 4300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4301 uint16_t i, lut_size = pf->hash_lut_size; 4302 uint16_t idx, shift; 4303 uint8_t *lut; 4304 int ret; 4305 4306 if (reta_size != lut_size || 4307 reta_size > ETH_RSS_RETA_SIZE_512) { 4308 PMD_DRV_LOG(ERR, 4309 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)", 4310 reta_size, lut_size); 4311 return -EINVAL; 4312 } 4313 4314 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 4315 if (!lut) { 4316 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4317 return -ENOMEM; 4318 } 4319 4320 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size); 4321 if (ret) 4322 goto out; 4323 for (i = 0; i < reta_size; i++) { 4324 idx = i / RTE_RETA_GROUP_SIZE; 4325 shift = i % RTE_RETA_GROUP_SIZE; 4326 if (reta_conf[idx].mask & (1ULL << shift)) 4327 reta_conf[idx].reta[shift] = lut[i]; 4328 } 4329 4330 out: 4331 rte_free(lut); 4332 4333 return ret; 4334 } 4335 4336 /** 4337 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver) 4338 * @hw: pointer to the HW structure 4339 * @mem: pointer to mem struct to fill out 4340 * @size: size of memory requested 4341 * @alignment: what to align the allocation to 4342 **/ 4343 enum i40e_status_code 4344 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4345 struct i40e_dma_mem *mem, 4346 u64 size, 4347 u32 alignment) 4348 { 4349 const struct rte_memzone *mz = NULL; 4350 char z_name[RTE_MEMZONE_NAMESIZE]; 4351 4352 if (!mem) 4353 return I40E_ERR_PARAM; 4354 4355 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand()); 4356 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 4357 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M); 4358 if (!mz) 4359 return I40E_ERR_NO_MEMORY; 4360 4361 mem->size = size; 4362 mem->va = mz->addr; 4363 mem->pa = mz->iova; 4364 mem->zone = (const void *)mz; 4365 PMD_DRV_LOG(DEBUG, 4366 "memzone %s allocated with physical address: %"PRIu64, 4367 mz->name, mem->pa); 4368 4369 return I40E_SUCCESS; 4370 } 4371 4372 /** 4373 * i40e_free_dma_mem_d - specific memory free for shared code (base driver) 4374 * @hw: pointer to the HW structure 4375 * @mem: ptr to mem struct to free 4376 **/ 4377 enum i40e_status_code 4378 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4379 struct i40e_dma_mem *mem) 4380 { 4381 if (!mem) 4382 return I40E_ERR_PARAM; 4383 4384 PMD_DRV_LOG(DEBUG, 4385 "memzone %s to be freed with physical address: %"PRIu64, 4386 ((const struct rte_memzone *)mem->zone)->name, mem->pa); 4387 rte_memzone_free((const struct rte_memzone *)mem->zone); 4388 mem->zone = NULL; 4389 mem->va = NULL; 4390 mem->pa = (u64)0; 4391 4392 return I40E_SUCCESS; 4393 } 4394 4395 /** 4396 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver) 4397 * @hw: pointer to the HW structure 4398 * @mem: pointer to mem struct to fill out 4399 * @size: size of memory requested 4400 **/ 4401 enum i40e_status_code 4402 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4403 struct i40e_virt_mem *mem, 4404 u32 size) 4405 { 4406 if (!mem) 4407 return I40E_ERR_PARAM; 4408 4409 mem->size = size; 4410 mem->va = rte_zmalloc("i40e", size, 0); 4411 4412 if (mem->va) 4413 return I40E_SUCCESS; 4414 else 4415 return I40E_ERR_NO_MEMORY; 4416 } 4417 4418 /** 4419 * i40e_free_virt_mem_d - specific memory free for shared code (base driver) 4420 * @hw: pointer to the HW structure 4421 * @mem: pointer to mem struct to free 4422 **/ 4423 enum i40e_status_code 4424 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4425 struct i40e_virt_mem *mem) 4426 { 4427 if (!mem) 4428 return I40E_ERR_PARAM; 4429 4430 rte_free(mem->va); 4431 mem->va = NULL; 4432 4433 return I40E_SUCCESS; 4434 } 4435 4436 void 4437 i40e_init_spinlock_d(struct i40e_spinlock *sp) 4438 { 4439 rte_spinlock_init(&sp->spinlock); 4440 } 4441 4442 void 4443 i40e_acquire_spinlock_d(struct i40e_spinlock *sp) 4444 { 4445 rte_spinlock_lock(&sp->spinlock); 4446 } 4447 4448 void 4449 i40e_release_spinlock_d(struct i40e_spinlock *sp) 4450 { 4451 rte_spinlock_unlock(&sp->spinlock); 4452 } 4453 4454 void 4455 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp) 4456 { 4457 return; 4458 } 4459 4460 /** 4461 * Get the hardware capabilities, which will be parsed 4462 * and saved into struct i40e_hw. 4463 */ 4464 static int 4465 i40e_get_cap(struct i40e_hw *hw) 4466 { 4467 struct i40e_aqc_list_capabilities_element_resp *buf; 4468 uint16_t len, size = 0; 4469 int ret; 4470 4471 /* Calculate a huge enough buff for saving response data temporarily */ 4472 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) * 4473 I40E_MAX_CAP_ELE_NUM; 4474 buf = rte_zmalloc("i40e", len, 0); 4475 if (!buf) { 4476 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 4477 return I40E_ERR_NO_MEMORY; 4478 } 4479 4480 /* Get, parse the capabilities and save it to hw */ 4481 ret = i40e_aq_discover_capabilities(hw, buf, len, &size, 4482 i40e_aqc_opc_list_func_capabilities, NULL); 4483 if (ret != I40E_SUCCESS) 4484 PMD_DRV_LOG(ERR, "Failed to discover capabilities"); 4485 4486 /* Free the temporary buffer after being used */ 4487 rte_free(buf); 4488 4489 return ret; 4490 } 4491 4492 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 4493 4494 static int i40e_pf_parse_vf_queue_number_handler(const char *key, 4495 const char *value, 4496 void *opaque) 4497 { 4498 struct i40e_pf *pf; 4499 unsigned long num; 4500 char *end; 4501 4502 pf = (struct i40e_pf *)opaque; 4503 RTE_SET_USED(key); 4504 4505 errno = 0; 4506 num = strtoul(value, &end, 0); 4507 if (errno != 0 || end == value || *end != 0) { 4508 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is " 4509 "kept the value = %hu", value, pf->vf_nb_qp_max); 4510 return -(EINVAL); 4511 } 4512 4513 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num)) 4514 pf->vf_nb_qp_max = (uint16_t)num; 4515 else 4516 /* here return 0 to make next valid same argument work */ 4517 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be " 4518 "power of 2 and equal or less than 16 !, Now it is " 4519 "kept the value = %hu", num, pf->vf_nb_qp_max); 4520 4521 return 0; 4522 } 4523 4524 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev) 4525 { 4526 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4527 struct rte_kvargs *kvlist; 4528 int kvargs_count; 4529 4530 /* set default queue number per VF as 4 */ 4531 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF; 4532 4533 if (dev->device->devargs == NULL) 4534 return 0; 4535 4536 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 4537 if (kvlist == NULL) 4538 return -(EINVAL); 4539 4540 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG); 4541 if (!kvargs_count) { 4542 rte_kvargs_free(kvlist); 4543 return 0; 4544 } 4545 4546 if (kvargs_count > 1) 4547 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 4548 "the first invalid or last valid one is used !", 4549 ETH_I40E_QUEUE_NUM_PER_VF_ARG); 4550 4551 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG, 4552 i40e_pf_parse_vf_queue_number_handler, pf); 4553 4554 rte_kvargs_free(kvlist); 4555 4556 return 0; 4557 } 4558 4559 static int 4560 i40e_pf_parameter_init(struct rte_eth_dev *dev) 4561 { 4562 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4563 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4564 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4565 uint16_t qp_count = 0, vsi_count = 0; 4566 4567 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) { 4568 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV"); 4569 return -EINVAL; 4570 } 4571 4572 i40e_pf_config_vf_rxq_number(dev); 4573 4574 /* Add the parameter init for LFC */ 4575 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME; 4576 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER; 4577 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER; 4578 4579 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED; 4580 pf->max_num_vsi = hw->func_caps.num_vsis; 4581 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF; 4582 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 4583 4584 /* FDir queue/VSI allocation */ 4585 pf->fdir_qp_offset = 0; 4586 if (hw->func_caps.fd) { 4587 pf->flags |= I40E_FLAG_FDIR; 4588 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR; 4589 } else { 4590 pf->fdir_nb_qps = 0; 4591 } 4592 qp_count += pf->fdir_nb_qps; 4593 vsi_count += 1; 4594 4595 /* LAN queue/VSI allocation */ 4596 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps; 4597 if (!hw->func_caps.rss) { 4598 pf->lan_nb_qps = 1; 4599 } else { 4600 pf->flags |= I40E_FLAG_RSS; 4601 if (hw->mac.type == I40E_MAC_X722) 4602 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE; 4603 pf->lan_nb_qps = pf->lan_nb_qp_max; 4604 } 4605 qp_count += pf->lan_nb_qps; 4606 vsi_count += 1; 4607 4608 /* VF queue/VSI allocation */ 4609 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps; 4610 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) { 4611 pf->flags |= I40E_FLAG_SRIOV; 4612 pf->vf_nb_qps = pf->vf_nb_qp_max; 4613 pf->vf_num = pci_dev->max_vfs; 4614 PMD_DRV_LOG(DEBUG, 4615 "%u VF VSIs, %u queues per VF VSI, in total %u queues", 4616 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num); 4617 } else { 4618 pf->vf_nb_qps = 0; 4619 pf->vf_num = 0; 4620 } 4621 qp_count += pf->vf_nb_qps * pf->vf_num; 4622 vsi_count += pf->vf_num; 4623 4624 /* VMDq queue/VSI allocation */ 4625 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num; 4626 pf->vmdq_nb_qps = 0; 4627 pf->max_nb_vmdq_vsi = 0; 4628 if (hw->func_caps.vmdq) { 4629 if (qp_count < hw->func_caps.num_tx_qp && 4630 vsi_count < hw->func_caps.num_vsis) { 4631 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp - 4632 qp_count) / pf->vmdq_nb_qp_max; 4633 4634 /* Limit the maximum number of VMDq vsi to the maximum 4635 * ethdev can support 4636 */ 4637 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi, 4638 hw->func_caps.num_vsis - vsi_count); 4639 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi, 4640 ETH_64_POOLS); 4641 if (pf->max_nb_vmdq_vsi) { 4642 pf->flags |= I40E_FLAG_VMDQ; 4643 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max; 4644 PMD_DRV_LOG(DEBUG, 4645 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues", 4646 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps, 4647 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi); 4648 } else { 4649 PMD_DRV_LOG(INFO, 4650 "No enough queues left for VMDq"); 4651 } 4652 } else { 4653 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq"); 4654 } 4655 } 4656 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi; 4657 vsi_count += pf->max_nb_vmdq_vsi; 4658 4659 if (hw->func_caps.dcb) 4660 pf->flags |= I40E_FLAG_DCB; 4661 4662 if (qp_count > hw->func_caps.num_tx_qp) { 4663 PMD_DRV_LOG(ERR, 4664 "Failed to allocate %u queues, which exceeds the hardware maximum %u", 4665 qp_count, hw->func_caps.num_tx_qp); 4666 return -EINVAL; 4667 } 4668 if (vsi_count > hw->func_caps.num_vsis) { 4669 PMD_DRV_LOG(ERR, 4670 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u", 4671 vsi_count, hw->func_caps.num_vsis); 4672 return -EINVAL; 4673 } 4674 4675 return 0; 4676 } 4677 4678 static int 4679 i40e_pf_get_switch_config(struct i40e_pf *pf) 4680 { 4681 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4682 struct i40e_aqc_get_switch_config_resp *switch_config; 4683 struct i40e_aqc_switch_config_element_resp *element; 4684 uint16_t start_seid = 0, num_reported; 4685 int ret; 4686 4687 switch_config = (struct i40e_aqc_get_switch_config_resp *)\ 4688 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0); 4689 if (!switch_config) { 4690 PMD_DRV_LOG(ERR, "Failed to allocated memory"); 4691 return -ENOMEM; 4692 } 4693 4694 /* Get the switch configurations */ 4695 ret = i40e_aq_get_switch_config(hw, switch_config, 4696 I40E_AQ_LARGE_BUF, &start_seid, NULL); 4697 if (ret != I40E_SUCCESS) { 4698 PMD_DRV_LOG(ERR, "Failed to get switch configurations"); 4699 goto fail; 4700 } 4701 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported); 4702 if (num_reported != 1) { /* The number should be 1 */ 4703 PMD_DRV_LOG(ERR, "Wrong number of switch config reported"); 4704 goto fail; 4705 } 4706 4707 /* Parse the switch configuration elements */ 4708 element = &(switch_config->element[0]); 4709 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) { 4710 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid); 4711 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid); 4712 } else 4713 PMD_DRV_LOG(INFO, "Unknown element type"); 4714 4715 fail: 4716 rte_free(switch_config); 4717 4718 return ret; 4719 } 4720 4721 static int 4722 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base, 4723 uint32_t num) 4724 { 4725 struct pool_entry *entry; 4726 4727 if (pool == NULL || num == 0) 4728 return -EINVAL; 4729 4730 entry = rte_zmalloc("i40e", sizeof(*entry), 0); 4731 if (entry == NULL) { 4732 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool"); 4733 return -ENOMEM; 4734 } 4735 4736 /* queue heap initialize */ 4737 pool->num_free = num; 4738 pool->num_alloc = 0; 4739 pool->base = base; 4740 LIST_INIT(&pool->alloc_list); 4741 LIST_INIT(&pool->free_list); 4742 4743 /* Initialize element */ 4744 entry->base = 0; 4745 entry->len = num; 4746 4747 LIST_INSERT_HEAD(&pool->free_list, entry, next); 4748 return 0; 4749 } 4750 4751 static void 4752 i40e_res_pool_destroy(struct i40e_res_pool_info *pool) 4753 { 4754 struct pool_entry *entry, *next_entry; 4755 4756 if (pool == NULL) 4757 return; 4758 4759 for (entry = LIST_FIRST(&pool->alloc_list); 4760 entry && (next_entry = LIST_NEXT(entry, next), 1); 4761 entry = next_entry) { 4762 LIST_REMOVE(entry, next); 4763 rte_free(entry); 4764 } 4765 4766 for (entry = LIST_FIRST(&pool->free_list); 4767 entry && (next_entry = LIST_NEXT(entry, next), 1); 4768 entry = next_entry) { 4769 LIST_REMOVE(entry, next); 4770 rte_free(entry); 4771 } 4772 4773 pool->num_free = 0; 4774 pool->num_alloc = 0; 4775 pool->base = 0; 4776 LIST_INIT(&pool->alloc_list); 4777 LIST_INIT(&pool->free_list); 4778 } 4779 4780 static int 4781 i40e_res_pool_free(struct i40e_res_pool_info *pool, 4782 uint32_t base) 4783 { 4784 struct pool_entry *entry, *next, *prev, *valid_entry = NULL; 4785 uint32_t pool_offset; 4786 int insert; 4787 4788 if (pool == NULL) { 4789 PMD_DRV_LOG(ERR, "Invalid parameter"); 4790 return -EINVAL; 4791 } 4792 4793 pool_offset = base - pool->base; 4794 /* Lookup in alloc list */ 4795 LIST_FOREACH(entry, &pool->alloc_list, next) { 4796 if (entry->base == pool_offset) { 4797 valid_entry = entry; 4798 LIST_REMOVE(entry, next); 4799 break; 4800 } 4801 } 4802 4803 /* Not find, return */ 4804 if (valid_entry == NULL) { 4805 PMD_DRV_LOG(ERR, "Failed to find entry"); 4806 return -EINVAL; 4807 } 4808 4809 /** 4810 * Found it, move it to free list and try to merge. 4811 * In order to make merge easier, always sort it by qbase. 4812 * Find adjacent prev and last entries. 4813 */ 4814 prev = next = NULL; 4815 LIST_FOREACH(entry, &pool->free_list, next) { 4816 if (entry->base > valid_entry->base) { 4817 next = entry; 4818 break; 4819 } 4820 prev = entry; 4821 } 4822 4823 insert = 0; 4824 /* Try to merge with next one*/ 4825 if (next != NULL) { 4826 /* Merge with next one */ 4827 if (valid_entry->base + valid_entry->len == next->base) { 4828 next->base = valid_entry->base; 4829 next->len += valid_entry->len; 4830 rte_free(valid_entry); 4831 valid_entry = next; 4832 insert = 1; 4833 } 4834 } 4835 4836 if (prev != NULL) { 4837 /* Merge with previous one */ 4838 if (prev->base + prev->len == valid_entry->base) { 4839 prev->len += valid_entry->len; 4840 /* If it merge with next one, remove next node */ 4841 if (insert == 1) { 4842 LIST_REMOVE(valid_entry, next); 4843 rte_free(valid_entry); 4844 } else { 4845 rte_free(valid_entry); 4846 insert = 1; 4847 } 4848 } 4849 } 4850 4851 /* Not find any entry to merge, insert */ 4852 if (insert == 0) { 4853 if (prev != NULL) 4854 LIST_INSERT_AFTER(prev, valid_entry, next); 4855 else if (next != NULL) 4856 LIST_INSERT_BEFORE(next, valid_entry, next); 4857 else /* It's empty list, insert to head */ 4858 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next); 4859 } 4860 4861 pool->num_free += valid_entry->len; 4862 pool->num_alloc -= valid_entry->len; 4863 4864 return 0; 4865 } 4866 4867 static int 4868 i40e_res_pool_alloc(struct i40e_res_pool_info *pool, 4869 uint16_t num) 4870 { 4871 struct pool_entry *entry, *valid_entry; 4872 4873 if (pool == NULL || num == 0) { 4874 PMD_DRV_LOG(ERR, "Invalid parameter"); 4875 return -EINVAL; 4876 } 4877 4878 if (pool->num_free < num) { 4879 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u", 4880 num, pool->num_free); 4881 return -ENOMEM; 4882 } 4883 4884 valid_entry = NULL; 4885 /* Lookup in free list and find most fit one */ 4886 LIST_FOREACH(entry, &pool->free_list, next) { 4887 if (entry->len >= num) { 4888 /* Find best one */ 4889 if (entry->len == num) { 4890 valid_entry = entry; 4891 break; 4892 } 4893 if (valid_entry == NULL || valid_entry->len > entry->len) 4894 valid_entry = entry; 4895 } 4896 } 4897 4898 /* Not find one to satisfy the request, return */ 4899 if (valid_entry == NULL) { 4900 PMD_DRV_LOG(ERR, "No valid entry found"); 4901 return -ENOMEM; 4902 } 4903 /** 4904 * The entry have equal queue number as requested, 4905 * remove it from alloc_list. 4906 */ 4907 if (valid_entry->len == num) { 4908 LIST_REMOVE(valid_entry, next); 4909 } else { 4910 /** 4911 * The entry have more numbers than requested, 4912 * create a new entry for alloc_list and minus its 4913 * queue base and number in free_list. 4914 */ 4915 entry = rte_zmalloc("res_pool", sizeof(*entry), 0); 4916 if (entry == NULL) { 4917 PMD_DRV_LOG(ERR, 4918 "Failed to allocate memory for resource pool"); 4919 return -ENOMEM; 4920 } 4921 entry->base = valid_entry->base; 4922 entry->len = num; 4923 valid_entry->base += num; 4924 valid_entry->len -= num; 4925 valid_entry = entry; 4926 } 4927 4928 /* Insert it into alloc list, not sorted */ 4929 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 4930 4931 pool->num_free -= valid_entry->len; 4932 pool->num_alloc += valid_entry->len; 4933 4934 return valid_entry->base + pool->base; 4935 } 4936 4937 /** 4938 * bitmap_is_subset - Check whether src2 is subset of src1 4939 **/ 4940 static inline int 4941 bitmap_is_subset(uint8_t src1, uint8_t src2) 4942 { 4943 return !((src1 ^ src2) & src2); 4944 } 4945 4946 static enum i40e_status_code 4947 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap) 4948 { 4949 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 4950 4951 /* If DCB is not supported, only default TC is supported */ 4952 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) { 4953 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported"); 4954 return I40E_NOT_SUPPORTED; 4955 } 4956 4957 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) { 4958 PMD_DRV_LOG(ERR, 4959 "Enabled TC map 0x%x not applicable to HW support 0x%x", 4960 hw->func_caps.enabled_tcmap, enabled_tcmap); 4961 return I40E_NOT_SUPPORTED; 4962 } 4963 return I40E_SUCCESS; 4964 } 4965 4966 int 4967 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 4968 struct i40e_vsi_vlan_pvid_info *info) 4969 { 4970 struct i40e_hw *hw; 4971 struct i40e_vsi_context ctxt; 4972 uint8_t vlan_flags = 0; 4973 int ret; 4974 4975 if (vsi == NULL || info == NULL) { 4976 PMD_DRV_LOG(ERR, "invalid parameters"); 4977 return I40E_ERR_PARAM; 4978 } 4979 4980 if (info->on) { 4981 vsi->info.pvid = info->config.pvid; 4982 /** 4983 * If insert pvid is enabled, only tagged pkts are 4984 * allowed to be sent out. 4985 */ 4986 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID | 4987 I40E_AQ_VSI_PVLAN_MODE_TAGGED; 4988 } else { 4989 vsi->info.pvid = 0; 4990 if (info->config.reject.tagged == 0) 4991 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED; 4992 4993 if (info->config.reject.untagged == 0) 4994 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED; 4995 } 4996 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID | 4997 I40E_AQ_VSI_PVLAN_MODE_MASK); 4998 vsi->info.port_vlan_flags |= vlan_flags; 4999 vsi->info.valid_sections = 5000 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5001 memset(&ctxt, 0, sizeof(ctxt)); 5002 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 5003 ctxt.seid = vsi->seid; 5004 5005 hw = I40E_VSI_TO_HW(vsi); 5006 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5007 if (ret != I40E_SUCCESS) 5008 PMD_DRV_LOG(ERR, "Failed to update VSI params"); 5009 5010 return ret; 5011 } 5012 5013 static int 5014 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap) 5015 { 5016 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5017 int i, ret; 5018 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data; 5019 5020 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 5021 if (ret != I40E_SUCCESS) 5022 return ret; 5023 5024 if (!vsi->seid) { 5025 PMD_DRV_LOG(ERR, "seid not valid"); 5026 return -EINVAL; 5027 } 5028 5029 memset(&tc_bw_data, 0, sizeof(tc_bw_data)); 5030 tc_bw_data.tc_valid_bits = enabled_tcmap; 5031 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 5032 tc_bw_data.tc_bw_credits[i] = 5033 (enabled_tcmap & (1 << i)) ? 1 : 0; 5034 5035 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL); 5036 if (ret != I40E_SUCCESS) { 5037 PMD_DRV_LOG(ERR, "Failed to configure TC BW"); 5038 return ret; 5039 } 5040 5041 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles, 5042 sizeof(vsi->info.qs_handle)); 5043 return I40E_SUCCESS; 5044 } 5045 5046 static enum i40e_status_code 5047 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi, 5048 struct i40e_aqc_vsi_properties_data *info, 5049 uint8_t enabled_tcmap) 5050 { 5051 enum i40e_status_code ret; 5052 int i, total_tc = 0; 5053 uint16_t qpnum_per_tc, bsf, qp_idx; 5054 5055 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 5056 if (ret != I40E_SUCCESS) 5057 return ret; 5058 5059 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 5060 if (enabled_tcmap & (1 << i)) 5061 total_tc++; 5062 if (total_tc == 0) 5063 total_tc = 1; 5064 vsi->enabled_tc = enabled_tcmap; 5065 5066 /* Number of queues per enabled TC */ 5067 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc); 5068 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC); 5069 bsf = rte_bsf32(qpnum_per_tc); 5070 5071 /* Adjust the queue number to actual queues that can be applied */ 5072 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1)) 5073 vsi->nb_qps = qpnum_per_tc * total_tc; 5074 5075 /** 5076 * Configure TC and queue mapping parameters, for enabled TC, 5077 * allocate qpnum_per_tc queues to this traffic. For disabled TC, 5078 * default queue will serve it. 5079 */ 5080 qp_idx = 0; 5081 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 5082 if (vsi->enabled_tc & (1 << i)) { 5083 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx << 5084 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 5085 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 5086 qp_idx += qpnum_per_tc; 5087 } else 5088 info->tc_mapping[i] = 0; 5089 } 5090 5091 /* Associate queue number with VSI */ 5092 if (vsi->type == I40E_VSI_SRIOV) { 5093 info->mapping_flags |= 5094 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 5095 for (i = 0; i < vsi->nb_qps; i++) 5096 info->queue_mapping[i] = 5097 rte_cpu_to_le_16(vsi->base_queue + i); 5098 } else { 5099 info->mapping_flags |= 5100 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG); 5101 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 5102 } 5103 info->valid_sections |= 5104 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 5105 5106 return I40E_SUCCESS; 5107 } 5108 5109 static int 5110 i40e_veb_release(struct i40e_veb *veb) 5111 { 5112 struct i40e_vsi *vsi; 5113 struct i40e_hw *hw; 5114 5115 if (veb == NULL) 5116 return -EINVAL; 5117 5118 if (!TAILQ_EMPTY(&veb->head)) { 5119 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove"); 5120 return -EACCES; 5121 } 5122 /* associate_vsi field is NULL for floating VEB */ 5123 if (veb->associate_vsi != NULL) { 5124 vsi = veb->associate_vsi; 5125 hw = I40E_VSI_TO_HW(vsi); 5126 5127 vsi->uplink_seid = veb->uplink_seid; 5128 vsi->veb = NULL; 5129 } else { 5130 veb->associate_pf->main_vsi->floating_veb = NULL; 5131 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi); 5132 } 5133 5134 i40e_aq_delete_element(hw, veb->seid, NULL); 5135 rte_free(veb); 5136 return I40E_SUCCESS; 5137 } 5138 5139 /* Setup a veb */ 5140 static struct i40e_veb * 5141 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi) 5142 { 5143 struct i40e_veb *veb; 5144 int ret; 5145 struct i40e_hw *hw; 5146 5147 if (pf == NULL) { 5148 PMD_DRV_LOG(ERR, 5149 "veb setup failed, associated PF shouldn't null"); 5150 return NULL; 5151 } 5152 hw = I40E_PF_TO_HW(pf); 5153 5154 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0); 5155 if (!veb) { 5156 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb"); 5157 goto fail; 5158 } 5159 5160 veb->associate_vsi = vsi; 5161 veb->associate_pf = pf; 5162 TAILQ_INIT(&veb->head); 5163 veb->uplink_seid = vsi ? vsi->uplink_seid : 0; 5164 5165 /* create floating veb if vsi is NULL */ 5166 if (vsi != NULL) { 5167 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid, 5168 I40E_DEFAULT_TCMAP, false, 5169 &veb->seid, false, NULL); 5170 } else { 5171 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP, 5172 true, &veb->seid, false, NULL); 5173 } 5174 5175 if (ret != I40E_SUCCESS) { 5176 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d", 5177 hw->aq.asq_last_status); 5178 goto fail; 5179 } 5180 veb->enabled_tc = I40E_DEFAULT_TCMAP; 5181 5182 /* get statistics index */ 5183 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL, 5184 &veb->stats_idx, NULL, NULL, NULL); 5185 if (ret != I40E_SUCCESS) { 5186 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d", 5187 hw->aq.asq_last_status); 5188 goto fail; 5189 } 5190 /* Get VEB bandwidth, to be implemented */ 5191 /* Now associated vsi binding to the VEB, set uplink to this VEB */ 5192 if (vsi) 5193 vsi->uplink_seid = veb->seid; 5194 5195 return veb; 5196 fail: 5197 rte_free(veb); 5198 return NULL; 5199 } 5200 5201 int 5202 i40e_vsi_release(struct i40e_vsi *vsi) 5203 { 5204 struct i40e_pf *pf; 5205 struct i40e_hw *hw; 5206 struct i40e_vsi_list *vsi_list; 5207 void *temp; 5208 int ret; 5209 struct i40e_mac_filter *f; 5210 uint16_t user_param; 5211 5212 if (!vsi) 5213 return I40E_SUCCESS; 5214 5215 if (!vsi->adapter) 5216 return -EFAULT; 5217 5218 user_param = vsi->user_param; 5219 5220 pf = I40E_VSI_TO_PF(vsi); 5221 hw = I40E_VSI_TO_HW(vsi); 5222 5223 /* VSI has child to attach, release child first */ 5224 if (vsi->veb) { 5225 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) { 5226 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS) 5227 return -1; 5228 } 5229 i40e_veb_release(vsi->veb); 5230 } 5231 5232 if (vsi->floating_veb) { 5233 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) { 5234 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS) 5235 return -1; 5236 } 5237 } 5238 5239 /* Remove all macvlan filters of the VSI */ 5240 i40e_vsi_remove_all_macvlan_filter(vsi); 5241 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) 5242 rte_free(f); 5243 5244 if (vsi->type != I40E_VSI_MAIN && 5245 ((vsi->type != I40E_VSI_SRIOV) || 5246 !pf->floating_veb_list[user_param])) { 5247 /* Remove vsi from parent's sibling list */ 5248 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) { 5249 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL"); 5250 return I40E_ERR_PARAM; 5251 } 5252 TAILQ_REMOVE(&vsi->parent_vsi->veb->head, 5253 &vsi->sib_vsi_list, list); 5254 5255 /* Remove all switch element of the VSI */ 5256 ret = i40e_aq_delete_element(hw, vsi->seid, NULL); 5257 if (ret != I40E_SUCCESS) 5258 PMD_DRV_LOG(ERR, "Failed to delete element"); 5259 } 5260 5261 if ((vsi->type == I40E_VSI_SRIOV) && 5262 pf->floating_veb_list[user_param]) { 5263 /* Remove vsi from parent's sibling list */ 5264 if (vsi->parent_vsi == NULL || 5265 vsi->parent_vsi->floating_veb == NULL) { 5266 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL"); 5267 return I40E_ERR_PARAM; 5268 } 5269 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head, 5270 &vsi->sib_vsi_list, list); 5271 5272 /* Remove all switch element of the VSI */ 5273 ret = i40e_aq_delete_element(hw, vsi->seid, NULL); 5274 if (ret != I40E_SUCCESS) 5275 PMD_DRV_LOG(ERR, "Failed to delete element"); 5276 } 5277 5278 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue); 5279 5280 if (vsi->type != I40E_VSI_SRIOV) 5281 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr); 5282 rte_free(vsi); 5283 5284 return I40E_SUCCESS; 5285 } 5286 5287 static int 5288 i40e_update_default_filter_setting(struct i40e_vsi *vsi) 5289 { 5290 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5291 struct i40e_aqc_remove_macvlan_element_data def_filter; 5292 struct i40e_mac_filter_info filter; 5293 int ret; 5294 5295 if (vsi->type != I40E_VSI_MAIN) 5296 return I40E_ERR_CONFIG; 5297 memset(&def_filter, 0, sizeof(def_filter)); 5298 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr, 5299 ETH_ADDR_LEN); 5300 def_filter.vlan_tag = 0; 5301 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 5302 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 5303 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL); 5304 if (ret != I40E_SUCCESS) { 5305 struct i40e_mac_filter *f; 5306 struct ether_addr *mac; 5307 5308 PMD_DRV_LOG(DEBUG, 5309 "Cannot remove the default macvlan filter"); 5310 /* It needs to add the permanent mac into mac list */ 5311 f = rte_zmalloc("macv_filter", sizeof(*f), 0); 5312 if (f == NULL) { 5313 PMD_DRV_LOG(ERR, "failed to allocate memory"); 5314 return I40E_ERR_NO_MEMORY; 5315 } 5316 mac = &f->mac_info.mac_addr; 5317 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr, 5318 ETH_ADDR_LEN); 5319 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5320 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 5321 vsi->mac_num++; 5322 5323 return ret; 5324 } 5325 rte_memcpy(&filter.mac_addr, 5326 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN); 5327 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5328 return i40e_vsi_add_mac(vsi, &filter); 5329 } 5330 5331 /* 5332 * i40e_vsi_get_bw_config - Query VSI BW Information 5333 * @vsi: the VSI to be queried 5334 * 5335 * Returns 0 on success, negative value on failure 5336 */ 5337 static enum i40e_status_code 5338 i40e_vsi_get_bw_config(struct i40e_vsi *vsi) 5339 { 5340 struct i40e_aqc_query_vsi_bw_config_resp bw_config; 5341 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config; 5342 struct i40e_hw *hw = &vsi->adapter->hw; 5343 i40e_status ret; 5344 int i; 5345 uint32_t bw_max; 5346 5347 memset(&bw_config, 0, sizeof(bw_config)); 5348 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); 5349 if (ret != I40E_SUCCESS) { 5350 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u", 5351 hw->aq.asq_last_status); 5352 return ret; 5353 } 5354 5355 memset(&ets_sla_config, 0, sizeof(ets_sla_config)); 5356 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, 5357 &ets_sla_config, NULL); 5358 if (ret != I40E_SUCCESS) { 5359 PMD_DRV_LOG(ERR, 5360 "VSI failed to get TC bandwdith configuration %u", 5361 hw->aq.asq_last_status); 5362 return ret; 5363 } 5364 5365 /* store and print out BW info */ 5366 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit); 5367 vsi->bw_info.bw_max = bw_config.max_bw; 5368 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit); 5369 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max); 5370 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) | 5371 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) << 5372 I40E_16_BIT_WIDTH); 5373 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 5374 vsi->bw_info.bw_ets_share_credits[i] = 5375 ets_sla_config.share_credits[i]; 5376 vsi->bw_info.bw_ets_credits[i] = 5377 rte_le_to_cpu_16(ets_sla_config.credits[i]); 5378 /* 4 bits per TC, 4th bit is reserved */ 5379 vsi->bw_info.bw_ets_max[i] = 5380 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) & 5381 RTE_LEN2MASK(3, uint8_t)); 5382 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i, 5383 vsi->bw_info.bw_ets_share_credits[i]); 5384 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i, 5385 vsi->bw_info.bw_ets_credits[i]); 5386 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i, 5387 vsi->bw_info.bw_ets_max[i]); 5388 } 5389 5390 return I40E_SUCCESS; 5391 } 5392 5393 /* i40e_enable_pf_lb 5394 * @pf: pointer to the pf structure 5395 * 5396 * allow loopback on pf 5397 */ 5398 static inline void 5399 i40e_enable_pf_lb(struct i40e_pf *pf) 5400 { 5401 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 5402 struct i40e_vsi_context ctxt; 5403 int ret; 5404 5405 /* Use the FW API if FW >= v5.0 */ 5406 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) { 5407 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback"); 5408 return; 5409 } 5410 5411 memset(&ctxt, 0, sizeof(ctxt)); 5412 ctxt.seid = pf->main_vsi_seid; 5413 ctxt.pf_num = hw->pf_id; 5414 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 5415 if (ret) { 5416 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d", 5417 ret, hw->aq.asq_last_status); 5418 return; 5419 } 5420 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 5421 ctxt.info.valid_sections = 5422 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5423 ctxt.info.switch_id |= 5424 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5425 5426 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5427 if (ret) 5428 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d", 5429 hw->aq.asq_last_status); 5430 } 5431 5432 /* Setup a VSI */ 5433 struct i40e_vsi * 5434 i40e_vsi_setup(struct i40e_pf *pf, 5435 enum i40e_vsi_type type, 5436 struct i40e_vsi *uplink_vsi, 5437 uint16_t user_param) 5438 { 5439 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 5440 struct i40e_vsi *vsi; 5441 struct i40e_mac_filter_info filter; 5442 int ret; 5443 struct i40e_vsi_context ctxt; 5444 struct ether_addr broadcast = 5445 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; 5446 5447 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV && 5448 uplink_vsi == NULL) { 5449 PMD_DRV_LOG(ERR, 5450 "VSI setup failed, VSI link shouldn't be NULL"); 5451 return NULL; 5452 } 5453 5454 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) { 5455 PMD_DRV_LOG(ERR, 5456 "VSI setup failed, MAIN VSI uplink VSI should be NULL"); 5457 return NULL; 5458 } 5459 5460 /* two situations 5461 * 1.type is not MAIN and uplink vsi is not NULL 5462 * If uplink vsi didn't setup VEB, create one first under veb field 5463 * 2.type is SRIOV and the uplink is NULL 5464 * If floating VEB is NULL, create one veb under floating veb field 5465 */ 5466 5467 if (type != I40E_VSI_MAIN && uplink_vsi != NULL && 5468 uplink_vsi->veb == NULL) { 5469 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi); 5470 5471 if (uplink_vsi->veb == NULL) { 5472 PMD_DRV_LOG(ERR, "VEB setup failed"); 5473 return NULL; 5474 } 5475 /* set ALLOWLOOPBACk on pf, when veb is created */ 5476 i40e_enable_pf_lb(pf); 5477 } 5478 5479 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL && 5480 pf->main_vsi->floating_veb == NULL) { 5481 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi); 5482 5483 if (pf->main_vsi->floating_veb == NULL) { 5484 PMD_DRV_LOG(ERR, "VEB setup failed"); 5485 return NULL; 5486 } 5487 } 5488 5489 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0); 5490 if (!vsi) { 5491 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi"); 5492 return NULL; 5493 } 5494 TAILQ_INIT(&vsi->mac_list); 5495 vsi->type = type; 5496 vsi->adapter = I40E_PF_TO_ADAPTER(pf); 5497 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX; 5498 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi; 5499 vsi->user_param = user_param; 5500 vsi->vlan_anti_spoof_on = 0; 5501 vsi->vlan_filter_on = 0; 5502 /* Allocate queues */ 5503 switch (vsi->type) { 5504 case I40E_VSI_MAIN : 5505 vsi->nb_qps = pf->lan_nb_qps; 5506 break; 5507 case I40E_VSI_SRIOV : 5508 vsi->nb_qps = pf->vf_nb_qps; 5509 break; 5510 case I40E_VSI_VMDQ2: 5511 vsi->nb_qps = pf->vmdq_nb_qps; 5512 break; 5513 case I40E_VSI_FDIR: 5514 vsi->nb_qps = pf->fdir_nb_qps; 5515 break; 5516 default: 5517 goto fail_mem; 5518 } 5519 /* 5520 * The filter status descriptor is reported in rx queue 0, 5521 * while the tx queue for fdir filter programming has no 5522 * such constraints, can be non-zero queues. 5523 * To simplify it, choose FDIR vsi use queue 0 pair. 5524 * To make sure it will use queue 0 pair, queue allocation 5525 * need be done before this function is called 5526 */ 5527 if (type != I40E_VSI_FDIR) { 5528 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps); 5529 if (ret < 0) { 5530 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d", 5531 vsi->seid, ret); 5532 goto fail_mem; 5533 } 5534 vsi->base_queue = ret; 5535 } else 5536 vsi->base_queue = I40E_FDIR_QUEUE_ID; 5537 5538 /* VF has MSIX interrupt in VF range, don't allocate here */ 5539 if (type == I40E_VSI_MAIN) { 5540 if (pf->support_multi_driver) { 5541 /* If support multi-driver, need to use INT0 instead of 5542 * allocating from msix pool. The Msix pool is init from 5543 * INT1, so it's OK just set msix_intr to 0 and nb_msix 5544 * to 1 without calling i40e_res_pool_alloc. 5545 */ 5546 vsi->msix_intr = 0; 5547 vsi->nb_msix = 1; 5548 } else { 5549 ret = i40e_res_pool_alloc(&pf->msix_pool, 5550 RTE_MIN(vsi->nb_qps, 5551 RTE_MAX_RXTX_INTR_VEC_ID)); 5552 if (ret < 0) { 5553 PMD_DRV_LOG(ERR, 5554 "VSI MAIN %d get heap failed %d", 5555 vsi->seid, ret); 5556 goto fail_queue_alloc; 5557 } 5558 vsi->msix_intr = ret; 5559 vsi->nb_msix = RTE_MIN(vsi->nb_qps, 5560 RTE_MAX_RXTX_INTR_VEC_ID); 5561 } 5562 } else if (type != I40E_VSI_SRIOV) { 5563 ret = i40e_res_pool_alloc(&pf->msix_pool, 1); 5564 if (ret < 0) { 5565 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret); 5566 goto fail_queue_alloc; 5567 } 5568 vsi->msix_intr = ret; 5569 vsi->nb_msix = 1; 5570 } else { 5571 vsi->msix_intr = 0; 5572 vsi->nb_msix = 0; 5573 } 5574 5575 /* Add VSI */ 5576 if (type == I40E_VSI_MAIN) { 5577 /* For main VSI, no need to add since it's default one */ 5578 vsi->uplink_seid = pf->mac_seid; 5579 vsi->seid = pf->main_vsi_seid; 5580 /* Bind queues with specific MSIX interrupt */ 5581 /** 5582 * Needs 2 interrupt at least, one for misc cause which will 5583 * enabled from OS side, Another for queues binding the 5584 * interrupt from device side only. 5585 */ 5586 5587 /* Get default VSI parameters from hardware */ 5588 memset(&ctxt, 0, sizeof(ctxt)); 5589 ctxt.seid = vsi->seid; 5590 ctxt.pf_num = hw->pf_id; 5591 ctxt.uplink_seid = vsi->uplink_seid; 5592 ctxt.vf_num = 0; 5593 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 5594 if (ret != I40E_SUCCESS) { 5595 PMD_DRV_LOG(ERR, "Failed to get VSI params"); 5596 goto fail_msix_alloc; 5597 } 5598 rte_memcpy(&vsi->info, &ctxt.info, 5599 sizeof(struct i40e_aqc_vsi_properties_data)); 5600 vsi->vsi_id = ctxt.vsi_number; 5601 vsi->info.valid_sections = 0; 5602 5603 /* Configure tc, enabled TC0 only */ 5604 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) != 5605 I40E_SUCCESS) { 5606 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth"); 5607 goto fail_msix_alloc; 5608 } 5609 5610 /* TC, queue mapping */ 5611 memset(&ctxt, 0, sizeof(ctxt)); 5612 vsi->info.valid_sections |= 5613 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5614 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 5615 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 5616 rte_memcpy(&ctxt.info, &vsi->info, 5617 sizeof(struct i40e_aqc_vsi_properties_data)); 5618 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5619 I40E_DEFAULT_TCMAP); 5620 if (ret != I40E_SUCCESS) { 5621 PMD_DRV_LOG(ERR, 5622 "Failed to configure TC queue mapping"); 5623 goto fail_msix_alloc; 5624 } 5625 ctxt.seid = vsi->seid; 5626 ctxt.pf_num = hw->pf_id; 5627 ctxt.uplink_seid = vsi->uplink_seid; 5628 ctxt.vf_num = 0; 5629 5630 /* Update VSI parameters */ 5631 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5632 if (ret != I40E_SUCCESS) { 5633 PMD_DRV_LOG(ERR, "Failed to update VSI params"); 5634 goto fail_msix_alloc; 5635 } 5636 5637 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping, 5638 sizeof(vsi->info.tc_mapping)); 5639 rte_memcpy(&vsi->info.queue_mapping, 5640 &ctxt.info.queue_mapping, 5641 sizeof(vsi->info.queue_mapping)); 5642 vsi->info.mapping_flags = ctxt.info.mapping_flags; 5643 vsi->info.valid_sections = 0; 5644 5645 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr, 5646 ETH_ADDR_LEN); 5647 5648 /** 5649 * Updating default filter settings are necessary to prevent 5650 * reception of tagged packets. 5651 * Some old firmware configurations load a default macvlan 5652 * filter which accepts both tagged and untagged packets. 5653 * The updating is to use a normal filter instead if needed. 5654 * For NVM 4.2.2 or after, the updating is not needed anymore. 5655 * The firmware with correct configurations load the default 5656 * macvlan filter which is expected and cannot be removed. 5657 */ 5658 i40e_update_default_filter_setting(vsi); 5659 i40e_config_qinq(hw, vsi); 5660 } else if (type == I40E_VSI_SRIOV) { 5661 memset(&ctxt, 0, sizeof(ctxt)); 5662 /** 5663 * For other VSI, the uplink_seid equals to uplink VSI's 5664 * uplink_seid since they share same VEB 5665 */ 5666 if (uplink_vsi == NULL) 5667 vsi->uplink_seid = pf->main_vsi->floating_veb->seid; 5668 else 5669 vsi->uplink_seid = uplink_vsi->uplink_seid; 5670 ctxt.pf_num = hw->pf_id; 5671 ctxt.vf_num = hw->func_caps.vf_base_id + user_param; 5672 ctxt.uplink_seid = vsi->uplink_seid; 5673 ctxt.connection_type = 0x1; 5674 ctxt.flags = I40E_AQ_VSI_TYPE_VF; 5675 5676 /* Use the VEB configuration if FW >= v5.0 */ 5677 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) { 5678 /* Configure switch ID */ 5679 ctxt.info.valid_sections |= 5680 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5681 ctxt.info.switch_id = 5682 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5683 } 5684 5685 /* Configure port/vlan */ 5686 ctxt.info.valid_sections |= 5687 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5688 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 5689 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5690 hw->func_caps.enabled_tcmap); 5691 if (ret != I40E_SUCCESS) { 5692 PMD_DRV_LOG(ERR, 5693 "Failed to configure TC queue mapping"); 5694 goto fail_msix_alloc; 5695 } 5696 5697 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap; 5698 ctxt.info.valid_sections |= 5699 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5700 /** 5701 * Since VSI is not created yet, only configure parameter, 5702 * will add vsi below. 5703 */ 5704 5705 i40e_config_qinq(hw, vsi); 5706 } else if (type == I40E_VSI_VMDQ2) { 5707 memset(&ctxt, 0, sizeof(ctxt)); 5708 /* 5709 * For other VSI, the uplink_seid equals to uplink VSI's 5710 * uplink_seid since they share same VEB 5711 */ 5712 vsi->uplink_seid = uplink_vsi->uplink_seid; 5713 ctxt.pf_num = hw->pf_id; 5714 ctxt.vf_num = 0; 5715 ctxt.uplink_seid = vsi->uplink_seid; 5716 ctxt.connection_type = 0x1; 5717 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; 5718 5719 ctxt.info.valid_sections |= 5720 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5721 /* user_param carries flag to enable loop back */ 5722 if (user_param) { 5723 ctxt.info.switch_id = 5724 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB); 5725 ctxt.info.switch_id |= 5726 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5727 } 5728 5729 /* Configure port/vlan */ 5730 ctxt.info.valid_sections |= 5731 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5732 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 5733 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5734 I40E_DEFAULT_TCMAP); 5735 if (ret != I40E_SUCCESS) { 5736 PMD_DRV_LOG(ERR, 5737 "Failed to configure TC queue mapping"); 5738 goto fail_msix_alloc; 5739 } 5740 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP; 5741 ctxt.info.valid_sections |= 5742 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5743 } else if (type == I40E_VSI_FDIR) { 5744 memset(&ctxt, 0, sizeof(ctxt)); 5745 vsi->uplink_seid = uplink_vsi->uplink_seid; 5746 ctxt.pf_num = hw->pf_id; 5747 ctxt.vf_num = 0; 5748 ctxt.uplink_seid = vsi->uplink_seid; 5749 ctxt.connection_type = 0x1; /* regular data port */ 5750 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 5751 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5752 I40E_DEFAULT_TCMAP); 5753 if (ret != I40E_SUCCESS) { 5754 PMD_DRV_LOG(ERR, 5755 "Failed to configure TC queue mapping."); 5756 goto fail_msix_alloc; 5757 } 5758 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP; 5759 ctxt.info.valid_sections |= 5760 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5761 } else { 5762 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet"); 5763 goto fail_msix_alloc; 5764 } 5765 5766 if (vsi->type != I40E_VSI_MAIN) { 5767 ret = i40e_aq_add_vsi(hw, &ctxt, NULL); 5768 if (ret != I40E_SUCCESS) { 5769 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d", 5770 hw->aq.asq_last_status); 5771 goto fail_msix_alloc; 5772 } 5773 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 5774 vsi->info.valid_sections = 0; 5775 vsi->seid = ctxt.seid; 5776 vsi->vsi_id = ctxt.vsi_number; 5777 vsi->sib_vsi_list.vsi = vsi; 5778 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) { 5779 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head, 5780 &vsi->sib_vsi_list, list); 5781 } else { 5782 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head, 5783 &vsi->sib_vsi_list, list); 5784 } 5785 } 5786 5787 /* MAC/VLAN configuration */ 5788 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN); 5789 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5790 5791 ret = i40e_vsi_add_mac(vsi, &filter); 5792 if (ret != I40E_SUCCESS) { 5793 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter"); 5794 goto fail_msix_alloc; 5795 } 5796 5797 /* Get VSI BW information */ 5798 i40e_vsi_get_bw_config(vsi); 5799 return vsi; 5800 fail_msix_alloc: 5801 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr); 5802 fail_queue_alloc: 5803 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue); 5804 fail_mem: 5805 rte_free(vsi); 5806 return NULL; 5807 } 5808 5809 /* Configure vlan filter on or off */ 5810 int 5811 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on) 5812 { 5813 int i, num; 5814 struct i40e_mac_filter *f; 5815 void *temp; 5816 struct i40e_mac_filter_info *mac_filter; 5817 enum rte_mac_filter_type desired_filter; 5818 int ret = I40E_SUCCESS; 5819 5820 if (on) { 5821 /* Filter to match MAC and VLAN */ 5822 desired_filter = RTE_MACVLAN_PERFECT_MATCH; 5823 } else { 5824 /* Filter to match only MAC */ 5825 desired_filter = RTE_MAC_PERFECT_MATCH; 5826 } 5827 5828 num = vsi->mac_num; 5829 5830 mac_filter = rte_zmalloc("mac_filter_info_data", 5831 num * sizeof(*mac_filter), 0); 5832 if (mac_filter == NULL) { 5833 PMD_DRV_LOG(ERR, "failed to allocate memory"); 5834 return I40E_ERR_NO_MEMORY; 5835 } 5836 5837 i = 0; 5838 5839 /* Remove all existing mac */ 5840 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) { 5841 mac_filter[i] = f->mac_info; 5842 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr); 5843 if (ret) { 5844 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter", 5845 on ? "enable" : "disable"); 5846 goto DONE; 5847 } 5848 i++; 5849 } 5850 5851 /* Override with new filter */ 5852 for (i = 0; i < num; i++) { 5853 mac_filter[i].filter_type = desired_filter; 5854 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]); 5855 if (ret) { 5856 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter", 5857 on ? "enable" : "disable"); 5858 goto DONE; 5859 } 5860 } 5861 5862 DONE: 5863 rte_free(mac_filter); 5864 return ret; 5865 } 5866 5867 /* Configure vlan stripping on or off */ 5868 int 5869 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on) 5870 { 5871 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5872 struct i40e_vsi_context ctxt; 5873 uint8_t vlan_flags; 5874 int ret = I40E_SUCCESS; 5875 5876 /* Check if it has been already on or off */ 5877 if (vsi->info.valid_sections & 5878 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) { 5879 if (on) { 5880 if ((vsi->info.port_vlan_flags & 5881 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0) 5882 return 0; /* already on */ 5883 } else { 5884 if ((vsi->info.port_vlan_flags & 5885 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 5886 I40E_AQ_VSI_PVLAN_EMOD_MASK) 5887 return 0; /* already off */ 5888 } 5889 } 5890 5891 if (on) 5892 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 5893 else 5894 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 5895 vsi->info.valid_sections = 5896 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5897 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK); 5898 vsi->info.port_vlan_flags |= vlan_flags; 5899 ctxt.seid = vsi->seid; 5900 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 5901 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5902 if (ret) 5903 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 5904 on ? "enable" : "disable"); 5905 5906 return ret; 5907 } 5908 5909 static int 5910 i40e_dev_init_vlan(struct rte_eth_dev *dev) 5911 { 5912 struct rte_eth_dev_data *data = dev->data; 5913 int ret; 5914 int mask = 0; 5915 5916 /* Apply vlan offload setting */ 5917 mask = ETH_VLAN_STRIP_MASK | 5918 ETH_VLAN_FILTER_MASK | 5919 ETH_VLAN_EXTEND_MASK; 5920 ret = i40e_vlan_offload_set(dev, mask); 5921 if (ret) { 5922 PMD_DRV_LOG(INFO, "Failed to update vlan offload"); 5923 return ret; 5924 } 5925 5926 /* Apply pvid setting */ 5927 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid, 5928 data->dev_conf.txmode.hw_vlan_insert_pvid); 5929 if (ret) 5930 PMD_DRV_LOG(INFO, "Failed to update VSI params"); 5931 5932 return ret; 5933 } 5934 5935 static int 5936 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on) 5937 { 5938 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5939 5940 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL); 5941 } 5942 5943 static int 5944 i40e_update_flow_control(struct i40e_hw *hw) 5945 { 5946 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX) 5947 struct i40e_link_status link_status; 5948 uint32_t rxfc = 0, txfc = 0, reg; 5949 uint8_t an_info; 5950 int ret; 5951 5952 memset(&link_status, 0, sizeof(link_status)); 5953 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL); 5954 if (ret != I40E_SUCCESS) { 5955 PMD_DRV_LOG(ERR, "Failed to get link status information"); 5956 goto write_reg; /* Disable flow control */ 5957 } 5958 5959 an_info = hw->phy.link_info.an_info; 5960 if (!(an_info & I40E_AQ_AN_COMPLETED)) { 5961 PMD_DRV_LOG(INFO, "Link auto negotiation not completed"); 5962 ret = I40E_ERR_NOT_READY; 5963 goto write_reg; /* Disable flow control */ 5964 } 5965 /** 5966 * If link auto negotiation is enabled, flow control needs to 5967 * be configured according to it 5968 */ 5969 switch (an_info & I40E_LINK_PAUSE_RXTX) { 5970 case I40E_LINK_PAUSE_RXTX: 5971 rxfc = 1; 5972 txfc = 1; 5973 hw->fc.current_mode = I40E_FC_FULL; 5974 break; 5975 case I40E_AQ_LINK_PAUSE_RX: 5976 rxfc = 1; 5977 hw->fc.current_mode = I40E_FC_RX_PAUSE; 5978 break; 5979 case I40E_AQ_LINK_PAUSE_TX: 5980 txfc = 1; 5981 hw->fc.current_mode = I40E_FC_TX_PAUSE; 5982 break; 5983 default: 5984 hw->fc.current_mode = I40E_FC_NONE; 5985 break; 5986 } 5987 5988 write_reg: 5989 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG, 5990 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT); 5991 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); 5992 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK; 5993 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT; 5994 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg); 5995 5996 return ret; 5997 } 5998 5999 /* PF setup */ 6000 static int 6001 i40e_pf_setup(struct i40e_pf *pf) 6002 { 6003 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 6004 struct i40e_filter_control_settings settings; 6005 struct i40e_vsi *vsi; 6006 int ret; 6007 6008 /* Clear all stats counters */ 6009 pf->offset_loaded = FALSE; 6010 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats)); 6011 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats)); 6012 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats)); 6013 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats)); 6014 6015 ret = i40e_pf_get_switch_config(pf); 6016 if (ret != I40E_SUCCESS) { 6017 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret); 6018 return ret; 6019 } 6020 6021 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id); 6022 if (ret) 6023 PMD_INIT_LOG(WARNING, 6024 "failed to allocate switch domain for device %d", ret); 6025 6026 if (pf->flags & I40E_FLAG_FDIR) { 6027 /* make queue allocated first, let FDIR use queue pair 0*/ 6028 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR); 6029 if (ret != I40E_FDIR_QUEUE_ID) { 6030 PMD_DRV_LOG(ERR, 6031 "queue allocation fails for FDIR: ret =%d", 6032 ret); 6033 pf->flags &= ~I40E_FLAG_FDIR; 6034 } 6035 } 6036 /* main VSI setup */ 6037 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0); 6038 if (!vsi) { 6039 PMD_DRV_LOG(ERR, "Setup of main vsi failed"); 6040 return I40E_ERR_NOT_READY; 6041 } 6042 pf->main_vsi = vsi; 6043 6044 /* Configure filter control */ 6045 memset(&settings, 0, sizeof(settings)); 6046 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128) 6047 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128; 6048 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512) 6049 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512; 6050 else { 6051 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported", 6052 hw->func_caps.rss_table_size); 6053 return I40E_ERR_PARAM; 6054 } 6055 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u", 6056 hw->func_caps.rss_table_size); 6057 pf->hash_lut_size = hw->func_caps.rss_table_size; 6058 6059 /* Enable ethtype and macvlan filters */ 6060 settings.enable_ethtype = TRUE; 6061 settings.enable_macvlan = TRUE; 6062 ret = i40e_set_filter_control(hw, &settings); 6063 if (ret) 6064 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d", 6065 ret); 6066 6067 /* Update flow control according to the auto negotiation */ 6068 i40e_update_flow_control(hw); 6069 6070 return I40E_SUCCESS; 6071 } 6072 6073 int 6074 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) 6075 { 6076 uint32_t reg; 6077 uint16_t j; 6078 6079 /** 6080 * Set or clear TX Queue Disable flags, 6081 * which is required by hardware. 6082 */ 6083 i40e_pre_tx_queue_cfg(hw, q_idx, on); 6084 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US); 6085 6086 /* Wait until the request is finished */ 6087 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6088 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6089 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx)); 6090 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^ 6091 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) 6092 & 0x1))) { 6093 break; 6094 } 6095 } 6096 if (on) { 6097 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 6098 return I40E_SUCCESS; /* already on, skip next steps */ 6099 6100 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0); 6101 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 6102 } else { 6103 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6104 return I40E_SUCCESS; /* already off, skip next steps */ 6105 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 6106 } 6107 /* Write the register */ 6108 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg); 6109 /* Check the result */ 6110 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6111 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6112 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx)); 6113 if (on) { 6114 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) && 6115 (reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6116 break; 6117 } else { 6118 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) && 6119 !(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6120 break; 6121 } 6122 } 6123 /* Check if it is timeout */ 6124 if (j >= I40E_CHK_Q_ENA_COUNT) { 6125 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]", 6126 (on ? "enable" : "disable"), q_idx); 6127 return I40E_ERR_TIMEOUT; 6128 } 6129 6130 return I40E_SUCCESS; 6131 } 6132 6133 /* Swith on or off the tx queues */ 6134 static int 6135 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on) 6136 { 6137 struct rte_eth_dev_data *dev_data = pf->dev_data; 6138 struct i40e_tx_queue *txq; 6139 struct rte_eth_dev *dev = pf->adapter->eth_dev; 6140 uint16_t i; 6141 int ret; 6142 6143 for (i = 0; i < dev_data->nb_tx_queues; i++) { 6144 txq = dev_data->tx_queues[i]; 6145 /* Don't operate the queue if not configured or 6146 * if starting only per queue */ 6147 if (!txq || !txq->q_set || (on && txq->tx_deferred_start)) 6148 continue; 6149 if (on) 6150 ret = i40e_dev_tx_queue_start(dev, i); 6151 else 6152 ret = i40e_dev_tx_queue_stop(dev, i); 6153 if ( ret != I40E_SUCCESS) 6154 return ret; 6155 } 6156 6157 return I40E_SUCCESS; 6158 } 6159 6160 int 6161 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) 6162 { 6163 uint32_t reg; 6164 uint16_t j; 6165 6166 /* Wait until the request is finished */ 6167 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6168 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6169 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); 6170 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^ 6171 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1)) 6172 break; 6173 } 6174 6175 if (on) { 6176 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 6177 return I40E_SUCCESS; /* Already on, skip next steps */ 6178 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 6179 } else { 6180 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6181 return I40E_SUCCESS; /* Already off, skip next steps */ 6182 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 6183 } 6184 6185 /* Write the register */ 6186 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg); 6187 /* Check the result */ 6188 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6189 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6190 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); 6191 if (on) { 6192 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) && 6193 (reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6194 break; 6195 } else { 6196 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) && 6197 !(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6198 break; 6199 } 6200 } 6201 6202 /* Check if it is timeout */ 6203 if (j >= I40E_CHK_Q_ENA_COUNT) { 6204 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]", 6205 (on ? "enable" : "disable"), q_idx); 6206 return I40E_ERR_TIMEOUT; 6207 } 6208 6209 return I40E_SUCCESS; 6210 } 6211 /* Switch on or off the rx queues */ 6212 static int 6213 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on) 6214 { 6215 struct rte_eth_dev_data *dev_data = pf->dev_data; 6216 struct i40e_rx_queue *rxq; 6217 struct rte_eth_dev *dev = pf->adapter->eth_dev; 6218 uint16_t i; 6219 int ret; 6220 6221 for (i = 0; i < dev_data->nb_rx_queues; i++) { 6222 rxq = dev_data->rx_queues[i]; 6223 /* Don't operate the queue if not configured or 6224 * if starting only per queue */ 6225 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start)) 6226 continue; 6227 if (on) 6228 ret = i40e_dev_rx_queue_start(dev, i); 6229 else 6230 ret = i40e_dev_rx_queue_stop(dev, i); 6231 if (ret != I40E_SUCCESS) 6232 return ret; 6233 } 6234 6235 return I40E_SUCCESS; 6236 } 6237 6238 /* Switch on or off all the rx/tx queues */ 6239 int 6240 i40e_dev_switch_queues(struct i40e_pf *pf, bool on) 6241 { 6242 int ret; 6243 6244 if (on) { 6245 /* enable rx queues before enabling tx queues */ 6246 ret = i40e_dev_switch_rx_queues(pf, on); 6247 if (ret) { 6248 PMD_DRV_LOG(ERR, "Failed to switch rx queues"); 6249 return ret; 6250 } 6251 ret = i40e_dev_switch_tx_queues(pf, on); 6252 } else { 6253 /* Stop tx queues before stopping rx queues */ 6254 ret = i40e_dev_switch_tx_queues(pf, on); 6255 if (ret) { 6256 PMD_DRV_LOG(ERR, "Failed to switch tx queues"); 6257 return ret; 6258 } 6259 ret = i40e_dev_switch_rx_queues(pf, on); 6260 } 6261 6262 return ret; 6263 } 6264 6265 /* Initialize VSI for TX */ 6266 static int 6267 i40e_dev_tx_init(struct i40e_pf *pf) 6268 { 6269 struct rte_eth_dev_data *data = pf->dev_data; 6270 uint16_t i; 6271 uint32_t ret = I40E_SUCCESS; 6272 struct i40e_tx_queue *txq; 6273 6274 for (i = 0; i < data->nb_tx_queues; i++) { 6275 txq = data->tx_queues[i]; 6276 if (!txq || !txq->q_set) 6277 continue; 6278 ret = i40e_tx_queue_init(txq); 6279 if (ret != I40E_SUCCESS) 6280 break; 6281 } 6282 if (ret == I40E_SUCCESS) 6283 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf) 6284 ->eth_dev); 6285 6286 return ret; 6287 } 6288 6289 /* Initialize VSI for RX */ 6290 static int 6291 i40e_dev_rx_init(struct i40e_pf *pf) 6292 { 6293 struct rte_eth_dev_data *data = pf->dev_data; 6294 int ret = I40E_SUCCESS; 6295 uint16_t i; 6296 struct i40e_rx_queue *rxq; 6297 6298 i40e_pf_config_mq_rx(pf); 6299 for (i = 0; i < data->nb_rx_queues; i++) { 6300 rxq = data->rx_queues[i]; 6301 if (!rxq || !rxq->q_set) 6302 continue; 6303 6304 ret = i40e_rx_queue_init(rxq); 6305 if (ret != I40E_SUCCESS) { 6306 PMD_DRV_LOG(ERR, 6307 "Failed to do RX queue initialization"); 6308 break; 6309 } 6310 } 6311 if (ret == I40E_SUCCESS) 6312 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf) 6313 ->eth_dev); 6314 6315 return ret; 6316 } 6317 6318 static int 6319 i40e_dev_rxtx_init(struct i40e_pf *pf) 6320 { 6321 int err; 6322 6323 err = i40e_dev_tx_init(pf); 6324 if (err) { 6325 PMD_DRV_LOG(ERR, "Failed to do TX initialization"); 6326 return err; 6327 } 6328 err = i40e_dev_rx_init(pf); 6329 if (err) { 6330 PMD_DRV_LOG(ERR, "Failed to do RX initialization"); 6331 return err; 6332 } 6333 6334 return err; 6335 } 6336 6337 static int 6338 i40e_vmdq_setup(struct rte_eth_dev *dev) 6339 { 6340 struct rte_eth_conf *conf = &dev->data->dev_conf; 6341 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6342 int i, err, conf_vsis, j, loop; 6343 struct i40e_vsi *vsi; 6344 struct i40e_vmdq_info *vmdq_info; 6345 struct rte_eth_vmdq_rx_conf *vmdq_conf; 6346 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 6347 6348 /* 6349 * Disable interrupt to avoid message from VF. Furthermore, it will 6350 * avoid race condition in VSI creation/destroy. 6351 */ 6352 i40e_pf_disable_irq0(hw); 6353 6354 if ((pf->flags & I40E_FLAG_VMDQ) == 0) { 6355 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ"); 6356 return -ENOTSUP; 6357 } 6358 6359 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools; 6360 if (conf_vsis > pf->max_nb_vmdq_vsi) { 6361 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u", 6362 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools, 6363 pf->max_nb_vmdq_vsi); 6364 return -ENOTSUP; 6365 } 6366 6367 if (pf->vmdq != NULL) { 6368 PMD_INIT_LOG(INFO, "VMDQ already configured"); 6369 return 0; 6370 } 6371 6372 pf->vmdq = rte_zmalloc("vmdq_info_struct", 6373 sizeof(*vmdq_info) * conf_vsis, 0); 6374 6375 if (pf->vmdq == NULL) { 6376 PMD_INIT_LOG(ERR, "Failed to allocate memory"); 6377 return -ENOMEM; 6378 } 6379 6380 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf; 6381 6382 /* Create VMDQ VSI */ 6383 for (i = 0; i < conf_vsis; i++) { 6384 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi, 6385 vmdq_conf->enable_loop_back); 6386 if (vsi == NULL) { 6387 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI"); 6388 err = -1; 6389 goto err_vsi_setup; 6390 } 6391 vmdq_info = &pf->vmdq[i]; 6392 vmdq_info->pf = pf; 6393 vmdq_info->vsi = vsi; 6394 } 6395 pf->nb_cfg_vmdq_vsi = conf_vsis; 6396 6397 /* Configure Vlan */ 6398 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT; 6399 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) { 6400 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) { 6401 if (vmdq_conf->pool_map[i].pools & (1UL << j)) { 6402 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u", 6403 vmdq_conf->pool_map[i].vlan_id, j); 6404 6405 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi, 6406 vmdq_conf->pool_map[i].vlan_id); 6407 if (err) { 6408 PMD_INIT_LOG(ERR, "Failed to add vlan"); 6409 err = -1; 6410 goto err_vsi_setup; 6411 } 6412 } 6413 } 6414 } 6415 6416 i40e_pf_enable_irq0(hw); 6417 6418 return 0; 6419 6420 err_vsi_setup: 6421 for (i = 0; i < conf_vsis; i++) 6422 if (pf->vmdq[i].vsi == NULL) 6423 break; 6424 else 6425 i40e_vsi_release(pf->vmdq[i].vsi); 6426 6427 rte_free(pf->vmdq); 6428 pf->vmdq = NULL; 6429 i40e_pf_enable_irq0(hw); 6430 return err; 6431 } 6432 6433 static void 6434 i40e_stat_update_32(struct i40e_hw *hw, 6435 uint32_t reg, 6436 bool offset_loaded, 6437 uint64_t *offset, 6438 uint64_t *stat) 6439 { 6440 uint64_t new_data; 6441 6442 new_data = (uint64_t)I40E_READ_REG(hw, reg); 6443 if (!offset_loaded) 6444 *offset = new_data; 6445 6446 if (new_data >= *offset) 6447 *stat = (uint64_t)(new_data - *offset); 6448 else 6449 *stat = (uint64_t)((new_data + 6450 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset); 6451 } 6452 6453 static void 6454 i40e_stat_update_48(struct i40e_hw *hw, 6455 uint32_t hireg, 6456 uint32_t loreg, 6457 bool offset_loaded, 6458 uint64_t *offset, 6459 uint64_t *stat) 6460 { 6461 uint64_t new_data; 6462 6463 new_data = (uint64_t)I40E_READ_REG(hw, loreg); 6464 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & 6465 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; 6466 6467 if (!offset_loaded) 6468 *offset = new_data; 6469 6470 if (new_data >= *offset) 6471 *stat = new_data - *offset; 6472 else 6473 *stat = (uint64_t)((new_data + 6474 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset); 6475 6476 *stat &= I40E_48_BIT_MASK; 6477 } 6478 6479 /* Disable IRQ0 */ 6480 void 6481 i40e_pf_disable_irq0(struct i40e_hw *hw) 6482 { 6483 /* Disable all interrupt types */ 6484 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 6485 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 6486 I40E_WRITE_FLUSH(hw); 6487 } 6488 6489 /* Enable IRQ0 */ 6490 void 6491 i40e_pf_enable_irq0(struct i40e_hw *hw) 6492 { 6493 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 6494 I40E_PFINT_DYN_CTL0_INTENA_MASK | 6495 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 6496 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 6497 I40E_WRITE_FLUSH(hw); 6498 } 6499 6500 static void 6501 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue) 6502 { 6503 /* read pending request and disable first */ 6504 i40e_pf_disable_irq0(hw); 6505 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK); 6506 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0, 6507 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK); 6508 6509 if (no_queue) 6510 /* Link no queues with irq0 */ 6511 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 6512 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); 6513 } 6514 6515 static void 6516 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev) 6517 { 6518 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6519 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6520 int i; 6521 uint16_t abs_vf_id; 6522 uint32_t index, offset, val; 6523 6524 if (!pf->vfs) 6525 return; 6526 /** 6527 * Try to find which VF trigger a reset, use absolute VF id to access 6528 * since the reg is global register. 6529 */ 6530 for (i = 0; i < pf->vf_num; i++) { 6531 abs_vf_id = hw->func_caps.vf_base_id + i; 6532 index = abs_vf_id / I40E_UINT32_BIT_SIZE; 6533 offset = abs_vf_id % I40E_UINT32_BIT_SIZE; 6534 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index)); 6535 /* VFR event occurred */ 6536 if (val & (0x1 << offset)) { 6537 int ret; 6538 6539 /* Clear the event first */ 6540 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index), 6541 (0x1 << offset)); 6542 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id); 6543 /** 6544 * Only notify a VF reset event occurred, 6545 * don't trigger another SW reset 6546 */ 6547 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0); 6548 if (ret != I40E_SUCCESS) 6549 PMD_DRV_LOG(ERR, "Failed to do VF reset"); 6550 } 6551 } 6552 } 6553 6554 static void 6555 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev) 6556 { 6557 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6558 int i; 6559 6560 for (i = 0; i < pf->vf_num; i++) 6561 i40e_notify_vf_link_status(dev, &pf->vfs[i]); 6562 } 6563 6564 static void 6565 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev) 6566 { 6567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6568 struct i40e_arq_event_info info; 6569 uint16_t pending, opcode; 6570 int ret; 6571 6572 info.buf_len = I40E_AQ_BUF_SZ; 6573 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0); 6574 if (!info.msg_buf) { 6575 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 6576 return; 6577 } 6578 6579 pending = 1; 6580 while (pending) { 6581 ret = i40e_clean_arq_element(hw, &info, &pending); 6582 6583 if (ret != I40E_SUCCESS) { 6584 PMD_DRV_LOG(INFO, 6585 "Failed to read msg from AdminQ, aq_err: %u", 6586 hw->aq.asq_last_status); 6587 break; 6588 } 6589 opcode = rte_le_to_cpu_16(info.desc.opcode); 6590 6591 switch (opcode) { 6592 case i40e_aqc_opc_send_msg_to_pf: 6593 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/ 6594 i40e_pf_host_handle_vf_msg(dev, 6595 rte_le_to_cpu_16(info.desc.retval), 6596 rte_le_to_cpu_32(info.desc.cookie_high), 6597 rte_le_to_cpu_32(info.desc.cookie_low), 6598 info.msg_buf, 6599 info.msg_len); 6600 break; 6601 case i40e_aqc_opc_get_link_status: 6602 ret = i40e_dev_link_update(dev, 0); 6603 if (!ret) 6604 _rte_eth_dev_callback_process(dev, 6605 RTE_ETH_EVENT_INTR_LSC, NULL); 6606 break; 6607 default: 6608 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 6609 opcode); 6610 break; 6611 } 6612 } 6613 rte_free(info.msg_buf); 6614 } 6615 6616 /** 6617 * Interrupt handler triggered by NIC for handling 6618 * specific interrupt. 6619 * 6620 * @param handle 6621 * Pointer to interrupt handle. 6622 * @param param 6623 * The address of parameter (struct rte_eth_dev *) regsitered before. 6624 * 6625 * @return 6626 * void 6627 */ 6628 static void 6629 i40e_dev_interrupt_handler(void *param) 6630 { 6631 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 6632 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6633 uint32_t icr0; 6634 6635 /* Disable interrupt */ 6636 i40e_pf_disable_irq0(hw); 6637 6638 /* read out interrupt causes */ 6639 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); 6640 6641 /* No interrupt event indicated */ 6642 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) { 6643 PMD_DRV_LOG(INFO, "No interrupt event"); 6644 goto done; 6645 } 6646 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) 6647 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); 6648 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) 6649 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); 6650 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) 6651 PMD_DRV_LOG(INFO, "ICR0: global reset requested"); 6652 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) 6653 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); 6654 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) 6655 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); 6656 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) 6657 PMD_DRV_LOG(ERR, "ICR0: HMC error"); 6658 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) 6659 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); 6660 6661 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 6662 PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); 6663 i40e_dev_handle_vfr_event(dev); 6664 } 6665 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 6666 PMD_DRV_LOG(INFO, "ICR0: adminq event"); 6667 i40e_dev_handle_aq_msg(dev); 6668 } 6669 6670 done: 6671 /* Enable interrupt */ 6672 i40e_pf_enable_irq0(hw); 6673 } 6674 6675 static void 6676 i40e_dev_alarm_handler(void *param) 6677 { 6678 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 6679 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6680 uint32_t icr0; 6681 6682 /* Disable interrupt */ 6683 i40e_pf_disable_irq0(hw); 6684 6685 /* read out interrupt causes */ 6686 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); 6687 6688 /* No interrupt event indicated */ 6689 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) 6690 goto done; 6691 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) 6692 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); 6693 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) 6694 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); 6695 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) 6696 PMD_DRV_LOG(INFO, "ICR0: global reset requested"); 6697 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) 6698 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); 6699 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) 6700 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); 6701 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) 6702 PMD_DRV_LOG(ERR, "ICR0: HMC error"); 6703 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) 6704 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); 6705 6706 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 6707 PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); 6708 i40e_dev_handle_vfr_event(dev); 6709 } 6710 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 6711 PMD_DRV_LOG(INFO, "ICR0: adminq event"); 6712 i40e_dev_handle_aq_msg(dev); 6713 } 6714 6715 done: 6716 /* Enable interrupt */ 6717 i40e_pf_enable_irq0(hw); 6718 rte_eal_alarm_set(I40E_ALARM_INTERVAL, 6719 i40e_dev_alarm_handler, dev); 6720 } 6721 6722 int 6723 i40e_add_macvlan_filters(struct i40e_vsi *vsi, 6724 struct i40e_macvlan_filter *filter, 6725 int total) 6726 { 6727 int ele_num, ele_buff_size; 6728 int num, actual_num, i; 6729 uint16_t flags; 6730 int ret = I40E_SUCCESS; 6731 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6732 struct i40e_aqc_add_macvlan_element_data *req_list; 6733 6734 if (filter == NULL || total == 0) 6735 return I40E_ERR_PARAM; 6736 ele_num = hw->aq.asq_buf_size / sizeof(*req_list); 6737 ele_buff_size = hw->aq.asq_buf_size; 6738 6739 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0); 6740 if (req_list == NULL) { 6741 PMD_DRV_LOG(ERR, "Fail to allocate memory"); 6742 return I40E_ERR_NO_MEMORY; 6743 } 6744 6745 num = 0; 6746 do { 6747 actual_num = (num + ele_num > total) ? (total - num) : ele_num; 6748 memset(req_list, 0, ele_buff_size); 6749 6750 for (i = 0; i < actual_num; i++) { 6751 rte_memcpy(req_list[i].mac_addr, 6752 &filter[num + i].macaddr, ETH_ADDR_LEN); 6753 req_list[i].vlan_tag = 6754 rte_cpu_to_le_16(filter[num + i].vlan_id); 6755 6756 switch (filter[num + i].filter_type) { 6757 case RTE_MAC_PERFECT_MATCH: 6758 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH | 6759 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 6760 break; 6761 case RTE_MACVLAN_PERFECT_MATCH: 6762 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 6763 break; 6764 case RTE_MAC_HASH_MATCH: 6765 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH | 6766 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 6767 break; 6768 case RTE_MACVLAN_HASH_MATCH: 6769 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH; 6770 break; 6771 default: 6772 PMD_DRV_LOG(ERR, "Invalid MAC match type"); 6773 ret = I40E_ERR_PARAM; 6774 goto DONE; 6775 } 6776 6777 req_list[i].queue_number = 0; 6778 6779 req_list[i].flags = rte_cpu_to_le_16(flags); 6780 } 6781 6782 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list, 6783 actual_num, NULL); 6784 if (ret != I40E_SUCCESS) { 6785 PMD_DRV_LOG(ERR, "Failed to add macvlan filter"); 6786 goto DONE; 6787 } 6788 num += actual_num; 6789 } while (num < total); 6790 6791 DONE: 6792 rte_free(req_list); 6793 return ret; 6794 } 6795 6796 int 6797 i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 6798 struct i40e_macvlan_filter *filter, 6799 int total) 6800 { 6801 int ele_num, ele_buff_size; 6802 int num, actual_num, i; 6803 uint16_t flags; 6804 int ret = I40E_SUCCESS; 6805 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6806 struct i40e_aqc_remove_macvlan_element_data *req_list; 6807 6808 if (filter == NULL || total == 0) 6809 return I40E_ERR_PARAM; 6810 6811 ele_num = hw->aq.asq_buf_size / sizeof(*req_list); 6812 ele_buff_size = hw->aq.asq_buf_size; 6813 6814 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0); 6815 if (req_list == NULL) { 6816 PMD_DRV_LOG(ERR, "Fail to allocate memory"); 6817 return I40E_ERR_NO_MEMORY; 6818 } 6819 6820 num = 0; 6821 do { 6822 actual_num = (num + ele_num > total) ? (total - num) : ele_num; 6823 memset(req_list, 0, ele_buff_size); 6824 6825 for (i = 0; i < actual_num; i++) { 6826 rte_memcpy(req_list[i].mac_addr, 6827 &filter[num + i].macaddr, ETH_ADDR_LEN); 6828 req_list[i].vlan_tag = 6829 rte_cpu_to_le_16(filter[num + i].vlan_id); 6830 6831 switch (filter[num + i].filter_type) { 6832 case RTE_MAC_PERFECT_MATCH: 6833 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 6834 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 6835 break; 6836 case RTE_MACVLAN_PERFECT_MATCH: 6837 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 6838 break; 6839 case RTE_MAC_HASH_MATCH: 6840 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH | 6841 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 6842 break; 6843 case RTE_MACVLAN_HASH_MATCH: 6844 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH; 6845 break; 6846 default: 6847 PMD_DRV_LOG(ERR, "Invalid MAC filter type"); 6848 ret = I40E_ERR_PARAM; 6849 goto DONE; 6850 } 6851 req_list[i].flags = rte_cpu_to_le_16(flags); 6852 } 6853 6854 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list, 6855 actual_num, NULL); 6856 if (ret != I40E_SUCCESS) { 6857 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter"); 6858 goto DONE; 6859 } 6860 num += actual_num; 6861 } while (num < total); 6862 6863 DONE: 6864 rte_free(req_list); 6865 return ret; 6866 } 6867 6868 /* Find out specific MAC filter */ 6869 static struct i40e_mac_filter * 6870 i40e_find_mac_filter(struct i40e_vsi *vsi, 6871 struct ether_addr *macaddr) 6872 { 6873 struct i40e_mac_filter *f; 6874 6875 TAILQ_FOREACH(f, &vsi->mac_list, next) { 6876 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 6877 return f; 6878 } 6879 6880 return NULL; 6881 } 6882 6883 static bool 6884 i40e_find_vlan_filter(struct i40e_vsi *vsi, 6885 uint16_t vlan_id) 6886 { 6887 uint32_t vid_idx, vid_bit; 6888 6889 if (vlan_id > ETH_VLAN_ID_MAX) 6890 return 0; 6891 6892 vid_idx = I40E_VFTA_IDX(vlan_id); 6893 vid_bit = I40E_VFTA_BIT(vlan_id); 6894 6895 if (vsi->vfta[vid_idx] & vid_bit) 6896 return 1; 6897 else 6898 return 0; 6899 } 6900 6901 static void 6902 i40e_store_vlan_filter(struct i40e_vsi *vsi, 6903 uint16_t vlan_id, bool on) 6904 { 6905 uint32_t vid_idx, vid_bit; 6906 6907 vid_idx = I40E_VFTA_IDX(vlan_id); 6908 vid_bit = I40E_VFTA_BIT(vlan_id); 6909 6910 if (on) 6911 vsi->vfta[vid_idx] |= vid_bit; 6912 else 6913 vsi->vfta[vid_idx] &= ~vid_bit; 6914 } 6915 6916 void 6917 i40e_set_vlan_filter(struct i40e_vsi *vsi, 6918 uint16_t vlan_id, bool on) 6919 { 6920 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6921 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0}; 6922 int ret; 6923 6924 if (vlan_id > ETH_VLAN_ID_MAX) 6925 return; 6926 6927 i40e_store_vlan_filter(vsi, vlan_id, on); 6928 6929 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id) 6930 return; 6931 6932 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id); 6933 6934 if (on) { 6935 ret = i40e_aq_add_vlan(hw, vsi->seid, 6936 &vlan_data, 1, NULL); 6937 if (ret != I40E_SUCCESS) 6938 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 6939 } else { 6940 ret = i40e_aq_remove_vlan(hw, vsi->seid, 6941 &vlan_data, 1, NULL); 6942 if (ret != I40E_SUCCESS) 6943 PMD_DRV_LOG(ERR, 6944 "Failed to remove vlan filter"); 6945 } 6946 } 6947 6948 /** 6949 * Find all vlan options for specific mac addr, 6950 * return with actual vlan found. 6951 */ 6952 int 6953 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 6954 struct i40e_macvlan_filter *mv_f, 6955 int num, struct ether_addr *addr) 6956 { 6957 int i; 6958 uint32_t j, k; 6959 6960 /** 6961 * Not to use i40e_find_vlan_filter to decrease the loop time, 6962 * although the code looks complex. 6963 */ 6964 if (num < vsi->vlan_num) 6965 return I40E_ERR_PARAM; 6966 6967 i = 0; 6968 for (j = 0; j < I40E_VFTA_SIZE; j++) { 6969 if (vsi->vfta[j]) { 6970 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) { 6971 if (vsi->vfta[j] & (1 << k)) { 6972 if (i > num - 1) { 6973 PMD_DRV_LOG(ERR, 6974 "vlan number doesn't match"); 6975 return I40E_ERR_PARAM; 6976 } 6977 rte_memcpy(&mv_f[i].macaddr, 6978 addr, ETH_ADDR_LEN); 6979 mv_f[i].vlan_id = 6980 j * I40E_UINT32_BIT_SIZE + k; 6981 i++; 6982 } 6983 } 6984 } 6985 } 6986 return I40E_SUCCESS; 6987 } 6988 6989 static inline int 6990 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi, 6991 struct i40e_macvlan_filter *mv_f, 6992 int num, 6993 uint16_t vlan) 6994 { 6995 int i = 0; 6996 struct i40e_mac_filter *f; 6997 6998 if (num < vsi->mac_num) 6999 return I40E_ERR_PARAM; 7000 7001 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7002 if (i > num - 1) { 7003 PMD_DRV_LOG(ERR, "buffer number not match"); 7004 return I40E_ERR_PARAM; 7005 } 7006 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr, 7007 ETH_ADDR_LEN); 7008 mv_f[i].vlan_id = vlan; 7009 mv_f[i].filter_type = f->mac_info.filter_type; 7010 i++; 7011 } 7012 7013 return I40E_SUCCESS; 7014 } 7015 7016 static int 7017 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi) 7018 { 7019 int i, j, num; 7020 struct i40e_mac_filter *f; 7021 struct i40e_macvlan_filter *mv_f; 7022 int ret = I40E_SUCCESS; 7023 7024 if (vsi == NULL || vsi->mac_num == 0) 7025 return I40E_ERR_PARAM; 7026 7027 /* Case that no vlan is set */ 7028 if (vsi->vlan_num == 0) 7029 num = vsi->mac_num; 7030 else 7031 num = vsi->mac_num * vsi->vlan_num; 7032 7033 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0); 7034 if (mv_f == NULL) { 7035 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7036 return I40E_ERR_NO_MEMORY; 7037 } 7038 7039 i = 0; 7040 if (vsi->vlan_num == 0) { 7041 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7042 rte_memcpy(&mv_f[i].macaddr, 7043 &f->mac_info.mac_addr, ETH_ADDR_LEN); 7044 mv_f[i].filter_type = f->mac_info.filter_type; 7045 mv_f[i].vlan_id = 0; 7046 i++; 7047 } 7048 } else { 7049 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7050 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i], 7051 vsi->vlan_num, &f->mac_info.mac_addr); 7052 if (ret != I40E_SUCCESS) 7053 goto DONE; 7054 for (j = i; j < i + vsi->vlan_num; j++) 7055 mv_f[j].filter_type = f->mac_info.filter_type; 7056 i += vsi->vlan_num; 7057 } 7058 } 7059 7060 ret = i40e_remove_macvlan_filters(vsi, mv_f, num); 7061 DONE: 7062 rte_free(mv_f); 7063 7064 return ret; 7065 } 7066 7067 int 7068 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan) 7069 { 7070 struct i40e_macvlan_filter *mv_f; 7071 int mac_num; 7072 int ret = I40E_SUCCESS; 7073 7074 if (!vsi || vlan > ETHER_MAX_VLAN_ID) 7075 return I40E_ERR_PARAM; 7076 7077 /* If it's already set, just return */ 7078 if (i40e_find_vlan_filter(vsi,vlan)) 7079 return I40E_SUCCESS; 7080 7081 mac_num = vsi->mac_num; 7082 7083 if (mac_num == 0) { 7084 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr"); 7085 return I40E_ERR_PARAM; 7086 } 7087 7088 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0); 7089 7090 if (mv_f == NULL) { 7091 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7092 return I40E_ERR_NO_MEMORY; 7093 } 7094 7095 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan); 7096 7097 if (ret != I40E_SUCCESS) 7098 goto DONE; 7099 7100 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num); 7101 7102 if (ret != I40E_SUCCESS) 7103 goto DONE; 7104 7105 i40e_set_vlan_filter(vsi, vlan, 1); 7106 7107 vsi->vlan_num++; 7108 ret = I40E_SUCCESS; 7109 DONE: 7110 rte_free(mv_f); 7111 return ret; 7112 } 7113 7114 int 7115 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan) 7116 { 7117 struct i40e_macvlan_filter *mv_f; 7118 int mac_num; 7119 int ret = I40E_SUCCESS; 7120 7121 /** 7122 * Vlan 0 is the generic filter for untagged packets 7123 * and can't be removed. 7124 */ 7125 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID) 7126 return I40E_ERR_PARAM; 7127 7128 /* If can't find it, just return */ 7129 if (!i40e_find_vlan_filter(vsi, vlan)) 7130 return I40E_ERR_PARAM; 7131 7132 mac_num = vsi->mac_num; 7133 7134 if (mac_num == 0) { 7135 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr"); 7136 return I40E_ERR_PARAM; 7137 } 7138 7139 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0); 7140 7141 if (mv_f == NULL) { 7142 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7143 return I40E_ERR_NO_MEMORY; 7144 } 7145 7146 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan); 7147 7148 if (ret != I40E_SUCCESS) 7149 goto DONE; 7150 7151 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num); 7152 7153 if (ret != I40E_SUCCESS) 7154 goto DONE; 7155 7156 /* This is last vlan to remove, replace all mac filter with vlan 0 */ 7157 if (vsi->vlan_num == 1) { 7158 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0); 7159 if (ret != I40E_SUCCESS) 7160 goto DONE; 7161 7162 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num); 7163 if (ret != I40E_SUCCESS) 7164 goto DONE; 7165 } 7166 7167 i40e_set_vlan_filter(vsi, vlan, 0); 7168 7169 vsi->vlan_num--; 7170 ret = I40E_SUCCESS; 7171 DONE: 7172 rte_free(mv_f); 7173 return ret; 7174 } 7175 7176 int 7177 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter) 7178 { 7179 struct i40e_mac_filter *f; 7180 struct i40e_macvlan_filter *mv_f; 7181 int i, vlan_num = 0; 7182 int ret = I40E_SUCCESS; 7183 7184 /* If it's add and we've config it, return */ 7185 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr); 7186 if (f != NULL) 7187 return I40E_SUCCESS; 7188 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) || 7189 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) { 7190 7191 /** 7192 * If vlan_num is 0, that's the first time to add mac, 7193 * set mask for vlan_id 0. 7194 */ 7195 if (vsi->vlan_num == 0) { 7196 i40e_set_vlan_filter(vsi, 0, 1); 7197 vsi->vlan_num = 1; 7198 } 7199 vlan_num = vsi->vlan_num; 7200 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) || 7201 (mac_filter->filter_type == RTE_MAC_HASH_MATCH)) 7202 vlan_num = 1; 7203 7204 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0); 7205 if (mv_f == NULL) { 7206 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7207 return I40E_ERR_NO_MEMORY; 7208 } 7209 7210 for (i = 0; i < vlan_num; i++) { 7211 mv_f[i].filter_type = mac_filter->filter_type; 7212 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr, 7213 ETH_ADDR_LEN); 7214 } 7215 7216 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH || 7217 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) { 7218 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, 7219 &mac_filter->mac_addr); 7220 if (ret != I40E_SUCCESS) 7221 goto DONE; 7222 } 7223 7224 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num); 7225 if (ret != I40E_SUCCESS) 7226 goto DONE; 7227 7228 /* Add the mac addr into mac list */ 7229 f = rte_zmalloc("macv_filter", sizeof(*f), 0); 7230 if (f == NULL) { 7231 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7232 ret = I40E_ERR_NO_MEMORY; 7233 goto DONE; 7234 } 7235 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr, 7236 ETH_ADDR_LEN); 7237 f->mac_info.filter_type = mac_filter->filter_type; 7238 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 7239 vsi->mac_num++; 7240 7241 ret = I40E_SUCCESS; 7242 DONE: 7243 rte_free(mv_f); 7244 7245 return ret; 7246 } 7247 7248 int 7249 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr) 7250 { 7251 struct i40e_mac_filter *f; 7252 struct i40e_macvlan_filter *mv_f; 7253 int i, vlan_num; 7254 enum rte_mac_filter_type filter_type; 7255 int ret = I40E_SUCCESS; 7256 7257 /* Can't find it, return an error */ 7258 f = i40e_find_mac_filter(vsi, addr); 7259 if (f == NULL) 7260 return I40E_ERR_PARAM; 7261 7262 vlan_num = vsi->vlan_num; 7263 filter_type = f->mac_info.filter_type; 7264 if (filter_type == RTE_MACVLAN_PERFECT_MATCH || 7265 filter_type == RTE_MACVLAN_HASH_MATCH) { 7266 if (vlan_num == 0) { 7267 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0"); 7268 return I40E_ERR_PARAM; 7269 } 7270 } else if (filter_type == RTE_MAC_PERFECT_MATCH || 7271 filter_type == RTE_MAC_HASH_MATCH) 7272 vlan_num = 1; 7273 7274 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0); 7275 if (mv_f == NULL) { 7276 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7277 return I40E_ERR_NO_MEMORY; 7278 } 7279 7280 for (i = 0; i < vlan_num; i++) { 7281 mv_f[i].filter_type = filter_type; 7282 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr, 7283 ETH_ADDR_LEN); 7284 } 7285 if (filter_type == RTE_MACVLAN_PERFECT_MATCH || 7286 filter_type == RTE_MACVLAN_HASH_MATCH) { 7287 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr); 7288 if (ret != I40E_SUCCESS) 7289 goto DONE; 7290 } 7291 7292 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num); 7293 if (ret != I40E_SUCCESS) 7294 goto DONE; 7295 7296 /* Remove the mac addr into mac list */ 7297 TAILQ_REMOVE(&vsi->mac_list, f, next); 7298 rte_free(f); 7299 vsi->mac_num--; 7300 7301 ret = I40E_SUCCESS; 7302 DONE: 7303 rte_free(mv_f); 7304 return ret; 7305 } 7306 7307 /* Configure hash enable flags for RSS */ 7308 uint64_t 7309 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags) 7310 { 7311 uint64_t hena = 0; 7312 int i; 7313 7314 if (!flags) 7315 return hena; 7316 7317 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) { 7318 if (flags & (1ULL << i)) 7319 hena |= adapter->pctypes_tbl[i]; 7320 } 7321 7322 return hena; 7323 } 7324 7325 /* Parse the hash enable flags */ 7326 uint64_t 7327 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags) 7328 { 7329 uint64_t rss_hf = 0; 7330 7331 if (!flags) 7332 return rss_hf; 7333 int i; 7334 7335 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) { 7336 if (flags & adapter->pctypes_tbl[i]) 7337 rss_hf |= (1ULL << i); 7338 } 7339 return rss_hf; 7340 } 7341 7342 /* Disable RSS */ 7343 static void 7344 i40e_pf_disable_rss(struct i40e_pf *pf) 7345 { 7346 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7347 7348 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); 7349 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); 7350 I40E_WRITE_FLUSH(hw); 7351 } 7352 7353 int 7354 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len) 7355 { 7356 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 7357 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7358 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ? 7359 I40E_VFQF_HKEY_MAX_INDEX : 7360 I40E_PFQF_HKEY_MAX_INDEX; 7361 int ret = 0; 7362 7363 if (!key || key_len == 0) { 7364 PMD_DRV_LOG(DEBUG, "No key to be configured"); 7365 return 0; 7366 } else if (key_len != (key_idx + 1) * 7367 sizeof(uint32_t)) { 7368 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 7369 return -EINVAL; 7370 } 7371 7372 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 7373 struct i40e_aqc_get_set_rss_key_data *key_dw = 7374 (struct i40e_aqc_get_set_rss_key_data *)key; 7375 7376 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw); 7377 if (ret) 7378 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ"); 7379 } else { 7380 uint32_t *hash_key = (uint32_t *)key; 7381 uint16_t i; 7382 7383 if (vsi->type == I40E_VSI_SRIOV) { 7384 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) 7385 I40E_WRITE_REG( 7386 hw, 7387 I40E_VFQF_HKEY1(i, vsi->user_param), 7388 hash_key[i]); 7389 7390 } else { 7391 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) 7392 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), 7393 hash_key[i]); 7394 } 7395 I40E_WRITE_FLUSH(hw); 7396 } 7397 7398 return ret; 7399 } 7400 7401 static int 7402 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len) 7403 { 7404 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 7405 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7406 uint32_t reg; 7407 int ret; 7408 7409 if (!key || !key_len) 7410 return 0; 7411 7412 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 7413 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id, 7414 (struct i40e_aqc_get_set_rss_key_data *)key); 7415 if (ret) { 7416 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ"); 7417 return ret; 7418 } 7419 } else { 7420 uint32_t *key_dw = (uint32_t *)key; 7421 uint16_t i; 7422 7423 if (vsi->type == I40E_VSI_SRIOV) { 7424 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) { 7425 reg = I40E_VFQF_HKEY1(i, vsi->user_param); 7426 key_dw[i] = i40e_read_rx_ctl(hw, reg); 7427 } 7428 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * 7429 sizeof(uint32_t); 7430 } else { 7431 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) { 7432 reg = I40E_PFQF_HKEY(i); 7433 key_dw[i] = i40e_read_rx_ctl(hw, reg); 7434 } 7435 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 7436 sizeof(uint32_t); 7437 } 7438 } 7439 return 0; 7440 } 7441 7442 static int 7443 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf) 7444 { 7445 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7446 uint64_t hena; 7447 int ret; 7448 7449 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key, 7450 rss_conf->rss_key_len); 7451 if (ret) 7452 return ret; 7453 7454 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf); 7455 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); 7456 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); 7457 I40E_WRITE_FLUSH(hw); 7458 7459 return 0; 7460 } 7461 7462 static int 7463 i40e_dev_rss_hash_update(struct rte_eth_dev *dev, 7464 struct rte_eth_rss_conf *rss_conf) 7465 { 7466 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7467 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7468 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask; 7469 uint64_t hena; 7470 7471 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); 7472 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; 7473 7474 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */ 7475 if (rss_hf != 0) /* Enable RSS */ 7476 return -EINVAL; 7477 return 0; /* Nothing to do */ 7478 } 7479 /* RSS enabled */ 7480 if (rss_hf == 0) /* Disable RSS */ 7481 return -EINVAL; 7482 7483 return i40e_hw_rss_hash_set(pf, rss_conf); 7484 } 7485 7486 static int 7487 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 7488 struct rte_eth_rss_conf *rss_conf) 7489 { 7490 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7491 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7492 uint64_t hena; 7493 int ret; 7494 7495 if (!rss_conf) 7496 return -EINVAL; 7497 7498 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key, 7499 &rss_conf->rss_key_len); 7500 if (ret) 7501 return ret; 7502 7503 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); 7504 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; 7505 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena); 7506 7507 return 0; 7508 } 7509 7510 static int 7511 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag) 7512 { 7513 switch (filter_type) { 7514 case RTE_TUNNEL_FILTER_IMAC_IVLAN: 7515 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN; 7516 break; 7517 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID: 7518 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID; 7519 break; 7520 case RTE_TUNNEL_FILTER_IMAC_TENID: 7521 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID; 7522 break; 7523 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC: 7524 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC; 7525 break; 7526 case ETH_TUNNEL_FILTER_IMAC: 7527 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC; 7528 break; 7529 case ETH_TUNNEL_FILTER_OIP: 7530 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP; 7531 break; 7532 case ETH_TUNNEL_FILTER_IIP: 7533 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP; 7534 break; 7535 default: 7536 PMD_DRV_LOG(ERR, "invalid tunnel filter type"); 7537 return -EINVAL; 7538 } 7539 7540 return 0; 7541 } 7542 7543 /* Convert tunnel filter structure */ 7544 static int 7545 i40e_tunnel_filter_convert( 7546 struct i40e_aqc_cloud_filters_element_bb *cld_filter, 7547 struct i40e_tunnel_filter *tunnel_filter) 7548 { 7549 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac, 7550 (struct ether_addr *)&tunnel_filter->input.outer_mac); 7551 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac, 7552 (struct ether_addr *)&tunnel_filter->input.inner_mac); 7553 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan; 7554 if ((rte_le_to_cpu_16(cld_filter->element.flags) & 7555 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) == 7556 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) 7557 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6; 7558 else 7559 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4; 7560 tunnel_filter->input.flags = cld_filter->element.flags; 7561 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id; 7562 tunnel_filter->queue = cld_filter->element.queue_number; 7563 rte_memcpy(tunnel_filter->input.general_fields, 7564 cld_filter->general_fields, 7565 sizeof(cld_filter->general_fields)); 7566 7567 return 0; 7568 } 7569 7570 /* Check if there exists the tunnel filter */ 7571 struct i40e_tunnel_filter * 7572 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 7573 const struct i40e_tunnel_filter_input *input) 7574 { 7575 int ret; 7576 7577 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input); 7578 if (ret < 0) 7579 return NULL; 7580 7581 return tunnel_rule->hash_map[ret]; 7582 } 7583 7584 /* Add a tunnel filter into the SW list */ 7585 static int 7586 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, 7587 struct i40e_tunnel_filter *tunnel_filter) 7588 { 7589 struct i40e_tunnel_rule *rule = &pf->tunnel; 7590 int ret; 7591 7592 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input); 7593 if (ret < 0) { 7594 PMD_DRV_LOG(ERR, 7595 "Failed to insert tunnel filter to hash table %d!", 7596 ret); 7597 return ret; 7598 } 7599 rule->hash_map[ret] = tunnel_filter; 7600 7601 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules); 7602 7603 return 0; 7604 } 7605 7606 /* Delete a tunnel filter from the SW list */ 7607 int 7608 i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 7609 struct i40e_tunnel_filter_input *input) 7610 { 7611 struct i40e_tunnel_rule *rule = &pf->tunnel; 7612 struct i40e_tunnel_filter *tunnel_filter; 7613 int ret; 7614 7615 ret = rte_hash_del_key(rule->hash_table, input); 7616 if (ret < 0) { 7617 PMD_DRV_LOG(ERR, 7618 "Failed to delete tunnel filter to hash table %d!", 7619 ret); 7620 return ret; 7621 } 7622 tunnel_filter = rule->hash_map[ret]; 7623 rule->hash_map[ret] = NULL; 7624 7625 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules); 7626 rte_free(tunnel_filter); 7627 7628 return 0; 7629 } 7630 7631 int 7632 i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 7633 struct rte_eth_tunnel_filter_conf *tunnel_filter, 7634 uint8_t add) 7635 { 7636 uint16_t ip_type; 7637 uint32_t ipv4_addr, ipv4_addr_le; 7638 uint8_t i, tun_type = 0; 7639 /* internal varialbe to convert ipv6 byte order */ 7640 uint32_t convert_ipv6[4]; 7641 int val, ret = 0; 7642 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7643 struct i40e_vsi *vsi = pf->main_vsi; 7644 struct i40e_aqc_cloud_filters_element_bb *cld_filter; 7645 struct i40e_aqc_cloud_filters_element_bb *pfilter; 7646 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 7647 struct i40e_tunnel_filter *tunnel, *node; 7648 struct i40e_tunnel_filter check_filter; /* Check if filter exists */ 7649 7650 cld_filter = rte_zmalloc("tunnel_filter", 7651 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), 7652 0); 7653 7654 if (NULL == cld_filter) { 7655 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 7656 return -ENOMEM; 7657 } 7658 pfilter = cld_filter; 7659 7660 ether_addr_copy(&tunnel_filter->outer_mac, 7661 (struct ether_addr *)&pfilter->element.outer_mac); 7662 ether_addr_copy(&tunnel_filter->inner_mac, 7663 (struct ether_addr *)&pfilter->element.inner_mac); 7664 7665 pfilter->element.inner_vlan = 7666 rte_cpu_to_le_16(tunnel_filter->inner_vlan); 7667 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) { 7668 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4; 7669 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr); 7670 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr); 7671 rte_memcpy(&pfilter->element.ipaddr.v4.data, 7672 &ipv4_addr_le, 7673 sizeof(pfilter->element.ipaddr.v4.data)); 7674 } else { 7675 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6; 7676 for (i = 0; i < 4; i++) { 7677 convert_ipv6[i] = 7678 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i])); 7679 } 7680 rte_memcpy(&pfilter->element.ipaddr.v6.data, 7681 &convert_ipv6, 7682 sizeof(pfilter->element.ipaddr.v6.data)); 7683 } 7684 7685 /* check tunneled type */ 7686 switch (tunnel_filter->tunnel_type) { 7687 case RTE_TUNNEL_TYPE_VXLAN: 7688 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN; 7689 break; 7690 case RTE_TUNNEL_TYPE_NVGRE: 7691 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC; 7692 break; 7693 case RTE_TUNNEL_TYPE_IP_IN_GRE: 7694 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; 7695 break; 7696 default: 7697 /* Other tunnel types is not supported. */ 7698 PMD_DRV_LOG(ERR, "tunnel type is not supported."); 7699 rte_free(cld_filter); 7700 return -EINVAL; 7701 } 7702 7703 val = i40e_dev_get_filter_type(tunnel_filter->filter_type, 7704 &pfilter->element.flags); 7705 if (val < 0) { 7706 rte_free(cld_filter); 7707 return -EINVAL; 7708 } 7709 7710 pfilter->element.flags |= rte_cpu_to_le_16( 7711 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | 7712 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)); 7713 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id); 7714 pfilter->element.queue_number = 7715 rte_cpu_to_le_16(tunnel_filter->queue_id); 7716 7717 /* Check if there is the filter in SW list */ 7718 memset(&check_filter, 0, sizeof(check_filter)); 7719 i40e_tunnel_filter_convert(cld_filter, &check_filter); 7720 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input); 7721 if (add && node) { 7722 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!"); 7723 rte_free(cld_filter); 7724 return -EINVAL; 7725 } 7726 7727 if (!add && !node) { 7728 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!"); 7729 rte_free(cld_filter); 7730 return -EINVAL; 7731 } 7732 7733 if (add) { 7734 ret = i40e_aq_add_cloud_filters(hw, 7735 vsi->seid, &cld_filter->element, 1); 7736 if (ret < 0) { 7737 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter."); 7738 rte_free(cld_filter); 7739 return -ENOTSUP; 7740 } 7741 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0); 7742 if (tunnel == NULL) { 7743 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 7744 rte_free(cld_filter); 7745 return -ENOMEM; 7746 } 7747 7748 rte_memcpy(tunnel, &check_filter, sizeof(check_filter)); 7749 ret = i40e_sw_tunnel_filter_insert(pf, tunnel); 7750 if (ret < 0) 7751 rte_free(tunnel); 7752 } else { 7753 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 7754 &cld_filter->element, 1); 7755 if (ret < 0) { 7756 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter."); 7757 rte_free(cld_filter); 7758 return -ENOTSUP; 7759 } 7760 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 7761 } 7762 7763 rte_free(cld_filter); 7764 return ret; 7765 } 7766 7767 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48 7768 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4 7769 #define I40E_TR_GENEVE_KEY_MASK 0x8 7770 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40 7771 #define I40E_TR_GRE_KEY_MASK 0x400 7772 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800 7773 #define I40E_TR_GRE_NO_KEY_MASK 0x8000 7774 7775 static enum 7776 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf) 7777 { 7778 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7779 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7780 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7781 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7782 enum i40e_status_code status = I40E_SUCCESS; 7783 7784 if (pf->support_multi_driver) { 7785 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported."); 7786 return I40E_NOT_SUPPORTED; 7787 } 7788 7789 memset(&filter_replace, 0, 7790 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7791 memset(&filter_replace_buf, 0, 7792 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7793 7794 /* create L1 filter */ 7795 filter_replace.old_filter_type = 7796 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; 7797 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11; 7798 filter_replace.tr_bit = 0; 7799 7800 /* Prepare the buffer, 3 entries */ 7801 filter_replace_buf.data[0] = 7802 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 7803 filter_replace_buf.data[0] |= 7804 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7805 filter_replace_buf.data[2] = 0xFF; 7806 filter_replace_buf.data[3] = 0xFF; 7807 filter_replace_buf.data[4] = 7808 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 7809 filter_replace_buf.data[4] |= 7810 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7811 filter_replace_buf.data[7] = 0xF0; 7812 filter_replace_buf.data[8] 7813 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0; 7814 filter_replace_buf.data[8] |= 7815 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7816 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK | 7817 I40E_TR_GENEVE_KEY_MASK | 7818 I40E_TR_GENERIC_UDP_TUNNEL_MASK; 7819 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK | 7820 I40E_TR_GRE_KEY_WITH_XSUM_MASK | 7821 I40E_TR_GRE_NO_KEY_MASK) >> 8; 7822 7823 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7824 &filter_replace_buf); 7825 if (!status && (filter_replace.old_filter_type != 7826 filter_replace.new_filter_type)) 7827 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 7828 " original: 0x%x, new: 0x%x", 7829 dev->device->name, 7830 filter_replace.old_filter_type, 7831 filter_replace.new_filter_type); 7832 7833 return status; 7834 } 7835 7836 static enum 7837 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) 7838 { 7839 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7840 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7841 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7842 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7843 enum i40e_status_code status = I40E_SUCCESS; 7844 7845 if (pf->support_multi_driver) { 7846 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 7847 return I40E_NOT_SUPPORTED; 7848 } 7849 7850 /* For MPLSoUDP */ 7851 memset(&filter_replace, 0, 7852 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7853 memset(&filter_replace_buf, 0, 7854 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7855 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | 7856 I40E_AQC_MIRROR_CLOUD_FILTER; 7857 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP; 7858 filter_replace.new_filter_type = 7859 I40E_AQC_ADD_CLOUD_FILTER_0X11; 7860 /* Prepare the buffer, 2 entries */ 7861 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 7862 filter_replace_buf.data[0] |= 7863 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7864 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11; 7865 filter_replace_buf.data[4] |= 7866 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7867 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7868 &filter_replace_buf); 7869 if (status < 0) 7870 return status; 7871 if (filter_replace.old_filter_type != 7872 filter_replace.new_filter_type) 7873 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 7874 " original: 0x%x, new: 0x%x", 7875 dev->device->name, 7876 filter_replace.old_filter_type, 7877 filter_replace.new_filter_type); 7878 7879 /* For MPLSoGRE */ 7880 memset(&filter_replace, 0, 7881 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7882 memset(&filter_replace_buf, 0, 7883 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7884 7885 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | 7886 I40E_AQC_MIRROR_CLOUD_FILTER; 7887 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC; 7888 filter_replace.new_filter_type = 7889 I40E_AQC_ADD_CLOUD_FILTER_0X12; 7890 /* Prepare the buffer, 2 entries */ 7891 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 7892 filter_replace_buf.data[0] |= 7893 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7894 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11; 7895 filter_replace_buf.data[4] |= 7896 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7897 7898 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7899 &filter_replace_buf); 7900 if (!status && (filter_replace.old_filter_type != 7901 filter_replace.new_filter_type)) 7902 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 7903 " original: 0x%x, new: 0x%x", 7904 dev->device->name, 7905 filter_replace.old_filter_type, 7906 filter_replace.new_filter_type); 7907 7908 return status; 7909 } 7910 7911 static enum i40e_status_code 7912 i40e_replace_gtp_l1_filter(struct i40e_pf *pf) 7913 { 7914 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7915 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7916 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7917 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7918 enum i40e_status_code status = I40E_SUCCESS; 7919 7920 if (pf->support_multi_driver) { 7921 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported."); 7922 return I40E_NOT_SUPPORTED; 7923 } 7924 7925 /* For GTP-C */ 7926 memset(&filter_replace, 0, 7927 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7928 memset(&filter_replace_buf, 0, 7929 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7930 /* create L1 filter */ 7931 filter_replace.old_filter_type = 7932 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; 7933 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12; 7934 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 | 7935 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7936 /* Prepare the buffer, 2 entries */ 7937 filter_replace_buf.data[0] = 7938 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 7939 filter_replace_buf.data[0] |= 7940 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7941 filter_replace_buf.data[2] = 0xFF; 7942 filter_replace_buf.data[3] = 0xFF; 7943 filter_replace_buf.data[4] = 7944 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 7945 filter_replace_buf.data[4] |= 7946 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7947 filter_replace_buf.data[6] = 0xFF; 7948 filter_replace_buf.data[7] = 0xFF; 7949 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7950 &filter_replace_buf); 7951 if (status < 0) 7952 return status; 7953 if (filter_replace.old_filter_type != 7954 filter_replace.new_filter_type) 7955 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 7956 " original: 0x%x, new: 0x%x", 7957 dev->device->name, 7958 filter_replace.old_filter_type, 7959 filter_replace.new_filter_type); 7960 7961 /* for GTP-U */ 7962 memset(&filter_replace, 0, 7963 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7964 memset(&filter_replace_buf, 0, 7965 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7966 /* create L1 filter */ 7967 filter_replace.old_filter_type = 7968 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY; 7969 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13; 7970 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 | 7971 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7972 /* Prepare the buffer, 2 entries */ 7973 filter_replace_buf.data[0] = 7974 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 7975 filter_replace_buf.data[0] |= 7976 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7977 filter_replace_buf.data[2] = 0xFF; 7978 filter_replace_buf.data[3] = 0xFF; 7979 filter_replace_buf.data[4] = 7980 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 7981 filter_replace_buf.data[4] |= 7982 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7983 filter_replace_buf.data[6] = 0xFF; 7984 filter_replace_buf.data[7] = 0xFF; 7985 7986 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7987 &filter_replace_buf); 7988 if (!status && (filter_replace.old_filter_type != 7989 filter_replace.new_filter_type)) 7990 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 7991 " original: 0x%x, new: 0x%x", 7992 dev->device->name, 7993 filter_replace.old_filter_type, 7994 filter_replace.new_filter_type); 7995 7996 return status; 7997 } 7998 7999 static enum 8000 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf) 8001 { 8002 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 8003 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 8004 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8005 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 8006 enum i40e_status_code status = I40E_SUCCESS; 8007 8008 if (pf->support_multi_driver) { 8009 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 8010 return I40E_NOT_SUPPORTED; 8011 } 8012 8013 /* for GTP-C */ 8014 memset(&filter_replace, 0, 8015 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8016 memset(&filter_replace_buf, 0, 8017 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8018 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 8019 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN; 8020 filter_replace.new_filter_type = 8021 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8022 /* Prepare the buffer, 2 entries */ 8023 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12; 8024 filter_replace_buf.data[0] |= 8025 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8026 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8027 filter_replace_buf.data[4] |= 8028 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8029 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8030 &filter_replace_buf); 8031 if (status < 0) 8032 return status; 8033 if (filter_replace.old_filter_type != 8034 filter_replace.new_filter_type) 8035 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8036 " original: 0x%x, new: 0x%x", 8037 dev->device->name, 8038 filter_replace.old_filter_type, 8039 filter_replace.new_filter_type); 8040 8041 /* for GTP-U */ 8042 memset(&filter_replace, 0, 8043 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8044 memset(&filter_replace_buf, 0, 8045 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8046 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 8047 filter_replace.old_filter_type = 8048 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID; 8049 filter_replace.new_filter_type = 8050 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8051 /* Prepare the buffer, 2 entries */ 8052 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13; 8053 filter_replace_buf.data[0] |= 8054 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8055 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8056 filter_replace_buf.data[4] |= 8057 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8058 8059 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8060 &filter_replace_buf); 8061 if (!status && (filter_replace.old_filter_type != 8062 filter_replace.new_filter_type)) 8063 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8064 " original: 0x%x, new: 0x%x", 8065 dev->device->name, 8066 filter_replace.old_filter_type, 8067 filter_replace.new_filter_type); 8068 8069 return status; 8070 } 8071 8072 int 8073 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 8074 struct i40e_tunnel_filter_conf *tunnel_filter, 8075 uint8_t add) 8076 { 8077 uint16_t ip_type; 8078 uint32_t ipv4_addr, ipv4_addr_le; 8079 uint8_t i, tun_type = 0; 8080 /* internal variable to convert ipv6 byte order */ 8081 uint32_t convert_ipv6[4]; 8082 int val, ret = 0; 8083 struct i40e_pf_vf *vf = NULL; 8084 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8085 struct i40e_vsi *vsi; 8086 struct i40e_aqc_cloud_filters_element_bb *cld_filter; 8087 struct i40e_aqc_cloud_filters_element_bb *pfilter; 8088 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 8089 struct i40e_tunnel_filter *tunnel, *node; 8090 struct i40e_tunnel_filter check_filter; /* Check if filter exists */ 8091 uint32_t teid_le; 8092 bool big_buffer = 0; 8093 8094 cld_filter = rte_zmalloc("tunnel_filter", 8095 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), 8096 0); 8097 8098 if (cld_filter == NULL) { 8099 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 8100 return -ENOMEM; 8101 } 8102 pfilter = cld_filter; 8103 8104 ether_addr_copy(&tunnel_filter->outer_mac, 8105 (struct ether_addr *)&pfilter->element.outer_mac); 8106 ether_addr_copy(&tunnel_filter->inner_mac, 8107 (struct ether_addr *)&pfilter->element.inner_mac); 8108 8109 pfilter->element.inner_vlan = 8110 rte_cpu_to_le_16(tunnel_filter->inner_vlan); 8111 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) { 8112 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4; 8113 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr); 8114 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr); 8115 rte_memcpy(&pfilter->element.ipaddr.v4.data, 8116 &ipv4_addr_le, 8117 sizeof(pfilter->element.ipaddr.v4.data)); 8118 } else { 8119 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6; 8120 for (i = 0; i < 4; i++) { 8121 convert_ipv6[i] = 8122 rte_cpu_to_le_32(rte_be_to_cpu_32( 8123 tunnel_filter->ip_addr.ipv6_addr[i])); 8124 } 8125 rte_memcpy(&pfilter->element.ipaddr.v6.data, 8126 &convert_ipv6, 8127 sizeof(pfilter->element.ipaddr.v6.data)); 8128 } 8129 8130 /* check tunneled type */ 8131 switch (tunnel_filter->tunnel_type) { 8132 case I40E_TUNNEL_TYPE_VXLAN: 8133 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN; 8134 break; 8135 case I40E_TUNNEL_TYPE_NVGRE: 8136 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC; 8137 break; 8138 case I40E_TUNNEL_TYPE_IP_IN_GRE: 8139 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; 8140 break; 8141 case I40E_TUNNEL_TYPE_MPLSoUDP: 8142 if (!pf->mpls_replace_flag) { 8143 i40e_replace_mpls_l1_filter(pf); 8144 i40e_replace_mpls_cloud_filter(pf); 8145 pf->mpls_replace_flag = 1; 8146 } 8147 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8148 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = 8149 teid_le >> 4; 8150 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = 8151 (teid_le & 0xF) << 12; 8152 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = 8153 0x40; 8154 big_buffer = 1; 8155 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP; 8156 break; 8157 case I40E_TUNNEL_TYPE_MPLSoGRE: 8158 if (!pf->mpls_replace_flag) { 8159 i40e_replace_mpls_l1_filter(pf); 8160 i40e_replace_mpls_cloud_filter(pf); 8161 pf->mpls_replace_flag = 1; 8162 } 8163 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8164 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = 8165 teid_le >> 4; 8166 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = 8167 (teid_le & 0xF) << 12; 8168 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = 8169 0x0; 8170 big_buffer = 1; 8171 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE; 8172 break; 8173 case I40E_TUNNEL_TYPE_GTPC: 8174 if (!pf->gtp_replace_flag) { 8175 i40e_replace_gtp_l1_filter(pf); 8176 i40e_replace_gtp_cloud_filter(pf); 8177 pf->gtp_replace_flag = 1; 8178 } 8179 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8180 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] = 8181 (teid_le >> 16) & 0xFFFF; 8182 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] = 8183 teid_le & 0xFFFF; 8184 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] = 8185 0x0; 8186 big_buffer = 1; 8187 break; 8188 case I40E_TUNNEL_TYPE_GTPU: 8189 if (!pf->gtp_replace_flag) { 8190 i40e_replace_gtp_l1_filter(pf); 8191 i40e_replace_gtp_cloud_filter(pf); 8192 pf->gtp_replace_flag = 1; 8193 } 8194 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8195 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] = 8196 (teid_le >> 16) & 0xFFFF; 8197 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] = 8198 teid_le & 0xFFFF; 8199 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] = 8200 0x0; 8201 big_buffer = 1; 8202 break; 8203 case I40E_TUNNEL_TYPE_QINQ: 8204 if (!pf->qinq_replace_flag) { 8205 ret = i40e_cloud_filter_qinq_create(pf); 8206 if (ret < 0) 8207 PMD_DRV_LOG(DEBUG, 8208 "QinQ tunnel filter already created."); 8209 pf->qinq_replace_flag = 1; 8210 } 8211 /* Add in the General fields the values of 8212 * the Outer and Inner VLAN 8213 * Big Buffer should be set, see changes in 8214 * i40e_aq_add_cloud_filters 8215 */ 8216 pfilter->general_fields[0] = tunnel_filter->inner_vlan; 8217 pfilter->general_fields[1] = tunnel_filter->outer_vlan; 8218 big_buffer = 1; 8219 break; 8220 default: 8221 /* Other tunnel types is not supported. */ 8222 PMD_DRV_LOG(ERR, "tunnel type is not supported."); 8223 rte_free(cld_filter); 8224 return -EINVAL; 8225 } 8226 8227 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP) 8228 pfilter->element.flags = 8229 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8230 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE) 8231 pfilter->element.flags = 8232 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8233 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC) 8234 pfilter->element.flags = 8235 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8236 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU) 8237 pfilter->element.flags = 8238 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8239 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ) 8240 pfilter->element.flags |= 8241 I40E_AQC_ADD_CLOUD_FILTER_0X10; 8242 else { 8243 val = i40e_dev_get_filter_type(tunnel_filter->filter_type, 8244 &pfilter->element.flags); 8245 if (val < 0) { 8246 rte_free(cld_filter); 8247 return -EINVAL; 8248 } 8249 } 8250 8251 pfilter->element.flags |= rte_cpu_to_le_16( 8252 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | 8253 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)); 8254 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8255 pfilter->element.queue_number = 8256 rte_cpu_to_le_16(tunnel_filter->queue_id); 8257 8258 if (!tunnel_filter->is_to_vf) 8259 vsi = pf->main_vsi; 8260 else { 8261 if (tunnel_filter->vf_id >= pf->vf_num) { 8262 PMD_DRV_LOG(ERR, "Invalid argument."); 8263 rte_free(cld_filter); 8264 return -EINVAL; 8265 } 8266 vf = &pf->vfs[tunnel_filter->vf_id]; 8267 vsi = vf->vsi; 8268 } 8269 8270 /* Check if there is the filter in SW list */ 8271 memset(&check_filter, 0, sizeof(check_filter)); 8272 i40e_tunnel_filter_convert(cld_filter, &check_filter); 8273 check_filter.is_to_vf = tunnel_filter->is_to_vf; 8274 check_filter.vf_id = tunnel_filter->vf_id; 8275 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input); 8276 if (add && node) { 8277 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!"); 8278 rte_free(cld_filter); 8279 return -EINVAL; 8280 } 8281 8282 if (!add && !node) { 8283 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!"); 8284 rte_free(cld_filter); 8285 return -EINVAL; 8286 } 8287 8288 if (add) { 8289 if (big_buffer) 8290 ret = i40e_aq_add_cloud_filters_bb(hw, 8291 vsi->seid, cld_filter, 1); 8292 else 8293 ret = i40e_aq_add_cloud_filters(hw, 8294 vsi->seid, &cld_filter->element, 1); 8295 if (ret < 0) { 8296 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter."); 8297 rte_free(cld_filter); 8298 return -ENOTSUP; 8299 } 8300 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0); 8301 if (tunnel == NULL) { 8302 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 8303 rte_free(cld_filter); 8304 return -ENOMEM; 8305 } 8306 8307 rte_memcpy(tunnel, &check_filter, sizeof(check_filter)); 8308 ret = i40e_sw_tunnel_filter_insert(pf, tunnel); 8309 if (ret < 0) 8310 rte_free(tunnel); 8311 } else { 8312 if (big_buffer) 8313 ret = i40e_aq_rem_cloud_filters_bb( 8314 hw, vsi->seid, cld_filter, 1); 8315 else 8316 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 8317 &cld_filter->element, 1); 8318 if (ret < 0) { 8319 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter."); 8320 rte_free(cld_filter); 8321 return -ENOTSUP; 8322 } 8323 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 8324 } 8325 8326 rte_free(cld_filter); 8327 return ret; 8328 } 8329 8330 static int 8331 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port) 8332 { 8333 uint8_t i; 8334 8335 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { 8336 if (pf->vxlan_ports[i] == port) 8337 return i; 8338 } 8339 8340 return -1; 8341 } 8342 8343 static int 8344 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port) 8345 { 8346 int idx, ret; 8347 uint8_t filter_idx; 8348 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8349 8350 idx = i40e_get_vxlan_port_idx(pf, port); 8351 8352 /* Check if port already exists */ 8353 if (idx >= 0) { 8354 PMD_DRV_LOG(ERR, "Port %d already offloaded", port); 8355 return -EINVAL; 8356 } 8357 8358 /* Now check if there is space to add the new port */ 8359 idx = i40e_get_vxlan_port_idx(pf, 0); 8360 if (idx < 0) { 8361 PMD_DRV_LOG(ERR, 8362 "Maximum number of UDP ports reached, not adding port %d", 8363 port); 8364 return -ENOSPC; 8365 } 8366 8367 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN, 8368 &filter_idx, NULL); 8369 if (ret < 0) { 8370 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port); 8371 return -1; 8372 } 8373 8374 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d", 8375 port, filter_idx); 8376 8377 /* New port: add it and mark its index in the bitmap */ 8378 pf->vxlan_ports[idx] = port; 8379 pf->vxlan_bitmap |= (1 << idx); 8380 8381 if (!(pf->flags & I40E_FLAG_VXLAN)) 8382 pf->flags |= I40E_FLAG_VXLAN; 8383 8384 return 0; 8385 } 8386 8387 static int 8388 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port) 8389 { 8390 int idx; 8391 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8392 8393 if (!(pf->flags & I40E_FLAG_VXLAN)) { 8394 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured."); 8395 return -EINVAL; 8396 } 8397 8398 idx = i40e_get_vxlan_port_idx(pf, port); 8399 8400 if (idx < 0) { 8401 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port); 8402 return -EINVAL; 8403 } 8404 8405 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) { 8406 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port); 8407 return -1; 8408 } 8409 8410 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d", 8411 port, idx); 8412 8413 pf->vxlan_ports[idx] = 0; 8414 pf->vxlan_bitmap &= ~(1 << idx); 8415 8416 if (!pf->vxlan_bitmap) 8417 pf->flags &= ~I40E_FLAG_VXLAN; 8418 8419 return 0; 8420 } 8421 8422 /* Add UDP tunneling port */ 8423 static int 8424 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8425 struct rte_eth_udp_tunnel *udp_tunnel) 8426 { 8427 int ret = 0; 8428 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8429 8430 if (udp_tunnel == NULL) 8431 return -EINVAL; 8432 8433 switch (udp_tunnel->prot_type) { 8434 case RTE_TUNNEL_TYPE_VXLAN: 8435 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port); 8436 break; 8437 8438 case RTE_TUNNEL_TYPE_GENEVE: 8439 case RTE_TUNNEL_TYPE_TEREDO: 8440 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8441 ret = -1; 8442 break; 8443 8444 default: 8445 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8446 ret = -1; 8447 break; 8448 } 8449 8450 return ret; 8451 } 8452 8453 /* Remove UDP tunneling port */ 8454 static int 8455 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8456 struct rte_eth_udp_tunnel *udp_tunnel) 8457 { 8458 int ret = 0; 8459 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8460 8461 if (udp_tunnel == NULL) 8462 return -EINVAL; 8463 8464 switch (udp_tunnel->prot_type) { 8465 case RTE_TUNNEL_TYPE_VXLAN: 8466 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port); 8467 break; 8468 case RTE_TUNNEL_TYPE_GENEVE: 8469 case RTE_TUNNEL_TYPE_TEREDO: 8470 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8471 ret = -1; 8472 break; 8473 default: 8474 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8475 ret = -1; 8476 break; 8477 } 8478 8479 return ret; 8480 } 8481 8482 /* Calculate the maximum number of contiguous PF queues that are configured */ 8483 static int 8484 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf) 8485 { 8486 struct rte_eth_dev_data *data = pf->dev_data; 8487 int i, num; 8488 struct i40e_rx_queue *rxq; 8489 8490 num = 0; 8491 for (i = 0; i < pf->lan_nb_qps; i++) { 8492 rxq = data->rx_queues[i]; 8493 if (rxq && rxq->q_set) 8494 num++; 8495 else 8496 break; 8497 } 8498 8499 return num; 8500 } 8501 8502 /* Configure RSS */ 8503 static int 8504 i40e_pf_config_rss(struct i40e_pf *pf) 8505 { 8506 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8507 struct rte_eth_rss_conf rss_conf; 8508 uint32_t i, lut = 0; 8509 uint16_t j, num; 8510 8511 /* 8512 * If both VMDQ and RSS enabled, not all of PF queues are configured. 8513 * It's necessary to calculate the actual PF queues that are configured. 8514 */ 8515 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 8516 num = i40e_pf_calc_configured_queues_num(pf); 8517 else 8518 num = pf->dev_data->nb_rx_queues; 8519 8520 num = RTE_MIN(num, I40E_MAX_Q_PER_TC); 8521 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured", 8522 num); 8523 8524 if (num == 0) { 8525 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS"); 8526 return -ENOTSUP; 8527 } 8528 8529 if (pf->adapter->rss_reta_updated == 0) { 8530 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 8531 if (j == num) 8532 j = 0; 8533 lut = (lut << 8) | (j & ((0x1 << 8534 hw->func_caps.rss_table_entry_width) - 1)); 8535 if ((i & 3) == 3) 8536 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), 8537 rte_bswap32(lut)); 8538 } 8539 } 8540 8541 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf; 8542 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) { 8543 i40e_pf_disable_rss(pf); 8544 return 0; 8545 } 8546 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < 8547 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 8548 /* Random default keys */ 8549 static uint32_t rss_key_default[] = {0x6b793944, 8550 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8, 8551 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605, 8552 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581}; 8553 8554 rss_conf.rss_key = (uint8_t *)rss_key_default; 8555 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 8556 sizeof(uint32_t); 8557 } 8558 8559 return i40e_hw_rss_hash_set(pf, &rss_conf); 8560 } 8561 8562 static int 8563 i40e_tunnel_filter_param_check(struct i40e_pf *pf, 8564 struct rte_eth_tunnel_filter_conf *filter) 8565 { 8566 if (pf == NULL || filter == NULL) { 8567 PMD_DRV_LOG(ERR, "Invalid parameter"); 8568 return -EINVAL; 8569 } 8570 8571 if (filter->queue_id >= pf->dev_data->nb_rx_queues) { 8572 PMD_DRV_LOG(ERR, "Invalid queue ID"); 8573 return -EINVAL; 8574 } 8575 8576 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) { 8577 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID"); 8578 return -EINVAL; 8579 } 8580 8581 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) && 8582 (is_zero_ether_addr(&filter->outer_mac))) { 8583 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address"); 8584 return -EINVAL; 8585 } 8586 8587 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) && 8588 (is_zero_ether_addr(&filter->inner_mac))) { 8589 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address"); 8590 return -EINVAL; 8591 } 8592 8593 return 0; 8594 } 8595 8596 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000 8597 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) 8598 static int 8599 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) 8600 { 8601 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 8602 uint32_t val, reg; 8603 int ret = -EINVAL; 8604 8605 if (pf->support_multi_driver) { 8606 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported"); 8607 return -ENOTSUP; 8608 } 8609 8610 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)); 8611 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val); 8612 8613 if (len == 3) { 8614 reg = val | I40E_GL_PRS_FVBM_MSK_ENA; 8615 } else if (len == 4) { 8616 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA; 8617 } else { 8618 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len); 8619 return ret; 8620 } 8621 8622 if (reg != val) { 8623 ret = i40e_aq_debug_write_global_register(hw, 8624 I40E_GL_PRS_FVBM(2), 8625 reg, NULL); 8626 if (ret != 0) 8627 return ret; 8628 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed " 8629 "with value 0x%08x", 8630 I40E_GL_PRS_FVBM(2), reg); 8631 } else { 8632 ret = 0; 8633 } 8634 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x", 8635 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2))); 8636 8637 return ret; 8638 } 8639 8640 static int 8641 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg) 8642 { 8643 int ret = -EINVAL; 8644 8645 if (!hw || !cfg) 8646 return -EINVAL; 8647 8648 switch (cfg->cfg_type) { 8649 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN: 8650 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len); 8651 break; 8652 default: 8653 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type); 8654 break; 8655 } 8656 8657 return ret; 8658 } 8659 8660 static int 8661 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev, 8662 enum rte_filter_op filter_op, 8663 void *arg) 8664 { 8665 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8666 int ret = I40E_ERR_PARAM; 8667 8668 switch (filter_op) { 8669 case RTE_ETH_FILTER_SET: 8670 ret = i40e_dev_global_config_set(hw, 8671 (struct rte_eth_global_cfg *)arg); 8672 break; 8673 default: 8674 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 8675 break; 8676 } 8677 8678 return ret; 8679 } 8680 8681 static int 8682 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, 8683 enum rte_filter_op filter_op, 8684 void *arg) 8685 { 8686 struct rte_eth_tunnel_filter_conf *filter; 8687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8688 int ret = I40E_SUCCESS; 8689 8690 filter = (struct rte_eth_tunnel_filter_conf *)(arg); 8691 8692 if (i40e_tunnel_filter_param_check(pf, filter) < 0) 8693 return I40E_ERR_PARAM; 8694 8695 switch (filter_op) { 8696 case RTE_ETH_FILTER_NOP: 8697 if (!(pf->flags & I40E_FLAG_VXLAN)) 8698 ret = I40E_NOT_SUPPORTED; 8699 break; 8700 case RTE_ETH_FILTER_ADD: 8701 ret = i40e_dev_tunnel_filter_set(pf, filter, 1); 8702 break; 8703 case RTE_ETH_FILTER_DELETE: 8704 ret = i40e_dev_tunnel_filter_set(pf, filter, 0); 8705 break; 8706 default: 8707 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 8708 ret = I40E_ERR_PARAM; 8709 break; 8710 } 8711 8712 return ret; 8713 } 8714 8715 static int 8716 i40e_pf_config_mq_rx(struct i40e_pf *pf) 8717 { 8718 int ret = 0; 8719 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode; 8720 8721 /* RSS setup */ 8722 if (mq_mode & ETH_MQ_RX_RSS_FLAG) 8723 ret = i40e_pf_config_rss(pf); 8724 else 8725 i40e_pf_disable_rss(pf); 8726 8727 return ret; 8728 } 8729 8730 /* Get the symmetric hash enable configurations per port */ 8731 static void 8732 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable) 8733 { 8734 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); 8735 8736 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0; 8737 } 8738 8739 /* Set the symmetric hash enable configurations per port */ 8740 static void 8741 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable) 8742 { 8743 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); 8744 8745 if (enable > 0) { 8746 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) { 8747 PMD_DRV_LOG(INFO, 8748 "Symmetric hash has already been enabled"); 8749 return; 8750 } 8751 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK; 8752 } else { 8753 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) { 8754 PMD_DRV_LOG(INFO, 8755 "Symmetric hash has already been disabled"); 8756 return; 8757 } 8758 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK; 8759 } 8760 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg); 8761 I40E_WRITE_FLUSH(hw); 8762 } 8763 8764 /* 8765 * Get global configurations of hash function type and symmetric hash enable 8766 * per flow type (pctype). Note that global configuration means it affects all 8767 * the ports on the same NIC. 8768 */ 8769 static int 8770 i40e_get_hash_filter_global_config(struct i40e_hw *hw, 8771 struct rte_eth_hash_global_conf *g_cfg) 8772 { 8773 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back; 8774 uint32_t reg; 8775 uint16_t i, j; 8776 8777 memset(g_cfg, 0, sizeof(*g_cfg)); 8778 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 8779 if (reg & I40E_GLQF_CTL_HTOEP_MASK) 8780 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ; 8781 else 8782 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR; 8783 PMD_DRV_LOG(DEBUG, "Hash function is %s", 8784 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); 8785 8786 /* 8787 * As i40e supports less than 64 flow types, only first 64 bits need to 8788 * be checked. 8789 */ 8790 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { 8791 g_cfg->valid_bit_mask[i] = 0ULL; 8792 g_cfg->sym_hash_enable_mask[i] = 0ULL; 8793 } 8794 8795 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask; 8796 8797 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) { 8798 if (!adapter->pctypes_tbl[i]) 8799 continue; 8800 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 8801 j < I40E_FILTER_PCTYPE_MAX; j++) { 8802 if (adapter->pctypes_tbl[i] & (1ULL << j)) { 8803 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j)); 8804 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) { 8805 g_cfg->sym_hash_enable_mask[0] |= 8806 (1ULL << i); 8807 } 8808 } 8809 } 8810 } 8811 8812 return 0; 8813 } 8814 8815 static int 8816 i40e_hash_global_config_check(const struct i40e_adapter *adapter, 8817 const struct rte_eth_hash_global_conf *g_cfg) 8818 { 8819 uint32_t i; 8820 uint64_t mask0, i40e_mask = adapter->flow_types_mask; 8821 8822 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ && 8823 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR && 8824 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) { 8825 PMD_DRV_LOG(ERR, "Unsupported hash function type %d", 8826 g_cfg->hash_func); 8827 return -EINVAL; 8828 } 8829 8830 /* 8831 * As i40e supports less than 64 flow types, only first 64 bits need to 8832 * be checked. 8833 */ 8834 mask0 = g_cfg->valid_bit_mask[0]; 8835 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { 8836 if (i == 0) { 8837 /* Check if any unsupported flow type configured */ 8838 if ((mask0 | i40e_mask) ^ i40e_mask) 8839 goto mask_err; 8840 } else { 8841 if (g_cfg->valid_bit_mask[i]) 8842 goto mask_err; 8843 } 8844 } 8845 8846 return 0; 8847 8848 mask_err: 8849 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured"); 8850 8851 return -EINVAL; 8852 } 8853 8854 /* 8855 * Set global configurations of hash function type and symmetric hash enable 8856 * per flow type (pctype). Note any modifying global configuration will affect 8857 * all the ports on the same NIC. 8858 */ 8859 static int 8860 i40e_set_hash_filter_global_config(struct i40e_hw *hw, 8861 struct rte_eth_hash_global_conf *g_cfg) 8862 { 8863 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back; 8864 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 8865 int ret; 8866 uint16_t i, j; 8867 uint32_t reg; 8868 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask; 8869 8870 if (pf->support_multi_driver) { 8871 PMD_DRV_LOG(ERR, "Hash global configuration is not supported."); 8872 return -ENOTSUP; 8873 } 8874 8875 /* Check the input parameters */ 8876 ret = i40e_hash_global_config_check(adapter, g_cfg); 8877 if (ret < 0) 8878 return ret; 8879 8880 /* 8881 * As i40e supports less than 64 flow types, only first 64 bits need to 8882 * be configured. 8883 */ 8884 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) { 8885 if (mask0 & (1UL << i)) { 8886 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ? 8887 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; 8888 8889 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 8890 j < I40E_FILTER_PCTYPE_MAX; j++) { 8891 if (adapter->pctypes_tbl[i] & (1ULL << j)) 8892 i40e_write_global_rx_ctl(hw, 8893 I40E_GLQF_HSYM(j), 8894 reg); 8895 } 8896 } 8897 } 8898 8899 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 8900 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) { 8901 /* Toeplitz */ 8902 if (reg & I40E_GLQF_CTL_HTOEP_MASK) { 8903 PMD_DRV_LOG(DEBUG, 8904 "Hash function already set to Toeplitz"); 8905 goto out; 8906 } 8907 reg |= I40E_GLQF_CTL_HTOEP_MASK; 8908 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { 8909 /* Simple XOR */ 8910 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) { 8911 PMD_DRV_LOG(DEBUG, 8912 "Hash function already set to Simple XOR"); 8913 goto out; 8914 } 8915 reg &= ~I40E_GLQF_CTL_HTOEP_MASK; 8916 } else 8917 /* Use the default, and keep it as it is */ 8918 goto out; 8919 8920 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg); 8921 8922 out: 8923 I40E_WRITE_FLUSH(hw); 8924 8925 return 0; 8926 } 8927 8928 /** 8929 * Valid input sets for hash and flow director filters per PCTYPE 8930 */ 8931 static uint64_t 8932 i40e_get_valid_input_set(enum i40e_filter_pctype pctype, 8933 enum rte_filter_type filter) 8934 { 8935 uint64_t valid; 8936 8937 static const uint64_t valid_hash_inset_table[] = { 8938 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 8939 I40E_INSET_DMAC | I40E_INSET_SMAC | 8940 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8941 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC | 8942 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS | 8943 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8944 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8945 I40E_INSET_FLEX_PAYLOAD, 8946 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 8947 I40E_INSET_DMAC | I40E_INSET_SMAC | 8948 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8949 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 8950 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8951 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8952 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 8953 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 8954 I40E_INSET_FLEX_PAYLOAD, 8955 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 8956 I40E_INSET_DMAC | I40E_INSET_SMAC | 8957 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8958 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 8959 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8960 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8961 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 8962 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 8963 I40E_INSET_FLEX_PAYLOAD, 8964 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 8965 I40E_INSET_DMAC | I40E_INSET_SMAC | 8966 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8967 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 8968 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8969 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8970 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 8971 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 8972 I40E_INSET_FLEX_PAYLOAD, 8973 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 8974 I40E_INSET_DMAC | I40E_INSET_SMAC | 8975 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8976 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 8977 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8978 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8979 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 8980 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 8981 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD, 8982 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 8983 I40E_INSET_DMAC | I40E_INSET_SMAC | 8984 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8985 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 8986 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8987 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8988 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 8989 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 8990 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD, 8991 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 8992 I40E_INSET_DMAC | I40E_INSET_SMAC | 8993 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 8994 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 8995 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 8996 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 8997 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 8998 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 8999 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD, 9000 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9001 I40E_INSET_DMAC | I40E_INSET_SMAC | 9002 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9003 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9004 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9005 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9006 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9007 I40E_INSET_FLEX_PAYLOAD, 9008 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9009 I40E_INSET_DMAC | I40E_INSET_SMAC | 9010 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9011 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9012 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9013 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC | 9014 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC | 9015 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD, 9016 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9017 I40E_INSET_DMAC | I40E_INSET_SMAC | 9018 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9019 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9020 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9021 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9022 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9023 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD, 9024 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9025 I40E_INSET_DMAC | I40E_INSET_SMAC | 9026 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9027 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9028 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9029 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9030 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9031 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9032 I40E_INSET_FLEX_PAYLOAD, 9033 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9034 I40E_INSET_DMAC | I40E_INSET_SMAC | 9035 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9036 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9037 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9038 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9039 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9040 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9041 I40E_INSET_FLEX_PAYLOAD, 9042 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9043 I40E_INSET_DMAC | I40E_INSET_SMAC | 9044 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9045 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9046 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9047 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9048 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9049 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9050 I40E_INSET_FLEX_PAYLOAD, 9051 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9052 I40E_INSET_DMAC | I40E_INSET_SMAC | 9053 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9054 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9055 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9056 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9057 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9058 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9059 I40E_INSET_FLEX_PAYLOAD, 9060 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9061 I40E_INSET_DMAC | I40E_INSET_SMAC | 9062 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9063 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9064 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9065 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9066 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9067 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT | 9068 I40E_INSET_FLEX_PAYLOAD, 9069 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9070 I40E_INSET_DMAC | I40E_INSET_SMAC | 9071 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9072 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9073 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9074 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9075 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID | 9076 I40E_INSET_FLEX_PAYLOAD, 9077 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9078 I40E_INSET_DMAC | I40E_INSET_SMAC | 9079 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9080 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE | 9081 I40E_INSET_FLEX_PAYLOAD, 9082 }; 9083 9084 /** 9085 * Flow director supports only fields defined in 9086 * union rte_eth_fdir_flow. 9087 */ 9088 static const uint64_t valid_fdir_inset_table[] = { 9089 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9090 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9091 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9092 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO | 9093 I40E_INSET_IPV4_TTL, 9094 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9095 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9096 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9097 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9098 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9099 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9100 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9101 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9102 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9103 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9104 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9105 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9106 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9107 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9108 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9109 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9110 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9111 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9112 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9113 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9114 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9115 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9116 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9117 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9118 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9119 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9121 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9122 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9123 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9124 I40E_INSET_SCTP_VT, 9125 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9126 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9127 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9128 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO | 9129 I40E_INSET_IPV4_TTL, 9130 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9131 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9132 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9133 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR | 9134 I40E_INSET_IPV6_HOP_LIMIT, 9135 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9136 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9137 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9138 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9139 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9140 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9141 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9142 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9143 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9144 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9145 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9146 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9147 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9148 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9149 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9150 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9151 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9152 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9153 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9154 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9155 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9156 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9157 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9158 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9159 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9160 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9162 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9163 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9164 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9165 I40E_INSET_SCTP_VT, 9166 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9167 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9168 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9169 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR | 9170 I40E_INSET_IPV6_HOP_LIMIT, 9171 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9172 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9173 I40E_INSET_LAST_ETHER_TYPE, 9174 }; 9175 9176 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) 9177 return 0; 9178 if (filter == RTE_ETH_FILTER_HASH) 9179 valid = valid_hash_inset_table[pctype]; 9180 else 9181 valid = valid_fdir_inset_table[pctype]; 9182 9183 return valid; 9184 } 9185 9186 /** 9187 * Validate if the input set is allowed for a specific PCTYPE 9188 */ 9189 int 9190 i40e_validate_input_set(enum i40e_filter_pctype pctype, 9191 enum rte_filter_type filter, uint64_t inset) 9192 { 9193 uint64_t valid; 9194 9195 valid = i40e_get_valid_input_set(pctype, filter); 9196 if (inset & (~valid)) 9197 return -EINVAL; 9198 9199 return 0; 9200 } 9201 9202 /* default input set fields combination per pctype */ 9203 uint64_t 9204 i40e_get_default_input_set(uint16_t pctype) 9205 { 9206 static const uint64_t default_inset_table[] = { 9207 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9208 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, 9209 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9210 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9211 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9212 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9213 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9214 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9215 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9216 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9217 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9218 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9219 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9220 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9221 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9222 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9223 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9224 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9225 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9226 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9227 I40E_INSET_SCTP_VT, 9228 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9229 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, 9230 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9231 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, 9232 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9233 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9234 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9235 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9236 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9237 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9238 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9239 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9240 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9241 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9242 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9243 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9244 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9245 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9246 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9247 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9248 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9249 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9250 I40E_INSET_SCTP_VT, 9251 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9252 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, 9253 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9254 I40E_INSET_LAST_ETHER_TYPE, 9255 }; 9256 9257 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) 9258 return 0; 9259 9260 return default_inset_table[pctype]; 9261 } 9262 9263 /** 9264 * Parse the input set from index to logical bit masks 9265 */ 9266 static int 9267 i40e_parse_input_set(uint64_t *inset, 9268 enum i40e_filter_pctype pctype, 9269 enum rte_eth_input_set_field *field, 9270 uint16_t size) 9271 { 9272 uint16_t i, j; 9273 int ret = -EINVAL; 9274 9275 static const struct { 9276 enum rte_eth_input_set_field field; 9277 uint64_t inset; 9278 } inset_convert_table[] = { 9279 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE}, 9280 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC}, 9281 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC}, 9282 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER}, 9283 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER}, 9284 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE}, 9285 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC}, 9286 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST}, 9287 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS}, 9288 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO}, 9289 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL}, 9290 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC}, 9291 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST}, 9292 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC}, 9293 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER, 9294 I40E_INSET_IPV6_NEXT_HDR}, 9295 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS, 9296 I40E_INSET_IPV6_HOP_LIMIT}, 9297 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT}, 9298 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT}, 9299 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT}, 9300 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT}, 9301 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT}, 9302 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT}, 9303 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG, 9304 I40E_INSET_SCTP_VT}, 9305 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC, 9306 I40E_INSET_TUNNEL_DMAC}, 9307 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN, 9308 I40E_INSET_VLAN_TUNNEL}, 9309 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY, 9310 I40E_INSET_TUNNEL_ID}, 9311 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID}, 9312 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD, 9313 I40E_INSET_FLEX_PAYLOAD_W1}, 9314 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD, 9315 I40E_INSET_FLEX_PAYLOAD_W2}, 9316 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD, 9317 I40E_INSET_FLEX_PAYLOAD_W3}, 9318 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD, 9319 I40E_INSET_FLEX_PAYLOAD_W4}, 9320 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD, 9321 I40E_INSET_FLEX_PAYLOAD_W5}, 9322 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD, 9323 I40E_INSET_FLEX_PAYLOAD_W6}, 9324 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD, 9325 I40E_INSET_FLEX_PAYLOAD_W7}, 9326 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD, 9327 I40E_INSET_FLEX_PAYLOAD_W8}, 9328 }; 9329 9330 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX) 9331 return ret; 9332 9333 /* Only one item allowed for default or all */ 9334 if (size == 1) { 9335 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) { 9336 *inset = i40e_get_default_input_set(pctype); 9337 return 0; 9338 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) { 9339 *inset = I40E_INSET_NONE; 9340 return 0; 9341 } 9342 } 9343 9344 for (i = 0, *inset = 0; i < size; i++) { 9345 for (j = 0; j < RTE_DIM(inset_convert_table); j++) { 9346 if (field[i] == inset_convert_table[j].field) { 9347 *inset |= inset_convert_table[j].inset; 9348 break; 9349 } 9350 } 9351 9352 /* It contains unsupported input set, return immediately */ 9353 if (j == RTE_DIM(inset_convert_table)) 9354 return ret; 9355 } 9356 9357 return 0; 9358 } 9359 9360 /** 9361 * Translate the input set from bit masks to register aware bit masks 9362 * and vice versa 9363 */ 9364 uint64_t 9365 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input) 9366 { 9367 uint64_t val = 0; 9368 uint16_t i; 9369 9370 struct inset_map { 9371 uint64_t inset; 9372 uint64_t inset_reg; 9373 }; 9374 9375 static const struct inset_map inset_map_common[] = { 9376 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC}, 9377 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC}, 9378 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN}, 9379 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN}, 9380 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE}, 9381 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS}, 9382 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6}, 9383 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6}, 9384 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC}, 9385 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR}, 9386 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT}, 9387 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT}, 9388 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT}, 9389 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG}, 9390 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID}, 9391 {I40E_INSET_TUNNEL_DMAC, 9392 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC}, 9393 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4}, 9394 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6}, 9395 {I40E_INSET_TUNNEL_SRC_PORT, 9396 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT}, 9397 {I40E_INSET_TUNNEL_DST_PORT, 9398 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT}, 9399 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN}, 9400 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1}, 9401 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2}, 9402 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3}, 9403 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4}, 9404 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5}, 9405 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6}, 9406 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7}, 9407 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8}, 9408 }; 9409 9410 /* some different registers map in x722*/ 9411 static const struct inset_map inset_map_diff_x722[] = { 9412 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4}, 9413 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4}, 9414 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO}, 9415 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL}, 9416 }; 9417 9418 static const struct inset_map inset_map_diff_not_x722[] = { 9419 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4}, 9420 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4}, 9421 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO}, 9422 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL}, 9423 }; 9424 9425 if (input == 0) 9426 return val; 9427 9428 /* Translate input set to register aware inset */ 9429 if (type == I40E_MAC_X722) { 9430 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) { 9431 if (input & inset_map_diff_x722[i].inset) 9432 val |= inset_map_diff_x722[i].inset_reg; 9433 } 9434 } else { 9435 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) { 9436 if (input & inset_map_diff_not_x722[i].inset) 9437 val |= inset_map_diff_not_x722[i].inset_reg; 9438 } 9439 } 9440 9441 for (i = 0; i < RTE_DIM(inset_map_common); i++) { 9442 if (input & inset_map_common[i].inset) 9443 val |= inset_map_common[i].inset_reg; 9444 } 9445 9446 return val; 9447 } 9448 9449 int 9450 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem) 9451 { 9452 uint8_t i, idx = 0; 9453 uint64_t inset_need_mask = inset; 9454 9455 static const struct { 9456 uint64_t inset; 9457 uint32_t mask; 9458 } inset_mask_map[] = { 9459 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK}, 9460 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0}, 9461 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK}, 9462 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK}, 9463 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK}, 9464 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0}, 9465 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK}, 9466 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK}, 9467 }; 9468 9469 if (!inset || !mask || !nb_elem) 9470 return 0; 9471 9472 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { 9473 /* Clear the inset bit, if no MASK is required, 9474 * for example proto + ttl 9475 */ 9476 if ((inset & inset_mask_map[i].inset) == 9477 inset_mask_map[i].inset && inset_mask_map[i].mask == 0) 9478 inset_need_mask &= ~inset_mask_map[i].inset; 9479 if (!inset_need_mask) 9480 return 0; 9481 } 9482 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { 9483 if ((inset_need_mask & inset_mask_map[i].inset) == 9484 inset_mask_map[i].inset) { 9485 if (idx >= nb_elem) { 9486 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks"); 9487 return -EINVAL; 9488 } 9489 mask[idx] = inset_mask_map[i].mask; 9490 idx++; 9491 } 9492 } 9493 9494 return idx; 9495 } 9496 9497 void 9498 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) 9499 { 9500 uint32_t reg = i40e_read_rx_ctl(hw, addr); 9501 9502 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg); 9503 if (reg != val) 9504 i40e_write_rx_ctl(hw, addr, val); 9505 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr, 9506 (uint32_t)i40e_read_rx_ctl(hw, addr)); 9507 } 9508 9509 void 9510 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) 9511 { 9512 uint32_t reg = i40e_read_rx_ctl(hw, addr); 9513 struct rte_eth_dev *dev; 9514 9515 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 9516 if (reg != val) { 9517 i40e_write_rx_ctl(hw, addr, val); 9518 PMD_DRV_LOG(WARNING, 9519 "i40e device %s changed global register [0x%08x]." 9520 " original: 0x%08x, new: 0x%08x", 9521 dev->device->name, addr, reg, 9522 (uint32_t)i40e_read_rx_ctl(hw, addr)); 9523 } 9524 } 9525 9526 static void 9527 i40e_filter_input_set_init(struct i40e_pf *pf) 9528 { 9529 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9530 enum i40e_filter_pctype pctype; 9531 uint64_t input_set, inset_reg; 9532 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9533 int num, i; 9534 uint16_t flow_type; 9535 9536 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 9537 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) { 9538 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype); 9539 9540 if (flow_type == RTE_ETH_FLOW_UNKNOWN) 9541 continue; 9542 9543 input_set = i40e_get_default_input_set(pctype); 9544 9545 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9546 I40E_INSET_MASK_NUM_REG); 9547 if (num < 0) 9548 return; 9549 if (pf->support_multi_driver && num > 0) { 9550 PMD_DRV_LOG(ERR, "Input set setting is not supported."); 9551 return; 9552 } 9553 inset_reg = i40e_translate_input_set_reg(hw->mac.type, 9554 input_set); 9555 9556 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 9557 (uint32_t)(inset_reg & UINT32_MAX)); 9558 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 9559 (uint32_t)((inset_reg >> 9560 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9561 if (!pf->support_multi_driver) { 9562 i40e_check_write_global_reg(hw, 9563 I40E_GLQF_HASH_INSET(0, pctype), 9564 (uint32_t)(inset_reg & UINT32_MAX)); 9565 i40e_check_write_global_reg(hw, 9566 I40E_GLQF_HASH_INSET(1, pctype), 9567 (uint32_t)((inset_reg >> 9568 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9569 9570 for (i = 0; i < num; i++) { 9571 i40e_check_write_global_reg(hw, 9572 I40E_GLQF_FD_MSK(i, pctype), 9573 mask_reg[i]); 9574 i40e_check_write_global_reg(hw, 9575 I40E_GLQF_HASH_MSK(i, pctype), 9576 mask_reg[i]); 9577 } 9578 /*clear unused mask registers of the pctype */ 9579 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) { 9580 i40e_check_write_global_reg(hw, 9581 I40E_GLQF_FD_MSK(i, pctype), 9582 0); 9583 i40e_check_write_global_reg(hw, 9584 I40E_GLQF_HASH_MSK(i, pctype), 9585 0); 9586 } 9587 } else { 9588 PMD_DRV_LOG(ERR, "Input set setting is not supported."); 9589 } 9590 I40E_WRITE_FLUSH(hw); 9591 9592 /* store the default input set */ 9593 if (!pf->support_multi_driver) 9594 pf->hash_input_set[pctype] = input_set; 9595 pf->fdir.input_set[pctype] = input_set; 9596 } 9597 } 9598 9599 int 9600 i40e_hash_filter_inset_select(struct i40e_hw *hw, 9601 struct rte_eth_input_set_conf *conf) 9602 { 9603 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 9604 enum i40e_filter_pctype pctype; 9605 uint64_t input_set, inset_reg = 0; 9606 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9607 int ret, i, num; 9608 9609 if (!conf) { 9610 PMD_DRV_LOG(ERR, "Invalid pointer"); 9611 return -EFAULT; 9612 } 9613 if (conf->op != RTE_ETH_INPUT_SET_SELECT && 9614 conf->op != RTE_ETH_INPUT_SET_ADD) { 9615 PMD_DRV_LOG(ERR, "Unsupported input set operation"); 9616 return -EINVAL; 9617 } 9618 9619 if (pf->support_multi_driver) { 9620 PMD_DRV_LOG(ERR, "Hash input set setting is not supported."); 9621 return -ENOTSUP; 9622 } 9623 9624 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); 9625 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 9626 PMD_DRV_LOG(ERR, "invalid flow_type input."); 9627 return -EINVAL; 9628 } 9629 9630 if (hw->mac.type == I40E_MAC_X722) { 9631 /* get translated pctype value in fd pctype register */ 9632 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw, 9633 I40E_GLQF_FD_PCTYPES((int)pctype)); 9634 } 9635 9636 ret = i40e_parse_input_set(&input_set, pctype, conf->field, 9637 conf->inset_size); 9638 if (ret) { 9639 PMD_DRV_LOG(ERR, "Failed to parse input set"); 9640 return -EINVAL; 9641 } 9642 9643 if (conf->op == RTE_ETH_INPUT_SET_ADD) { 9644 /* get inset value in register */ 9645 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype)); 9646 inset_reg <<= I40E_32_BIT_WIDTH; 9647 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype)); 9648 input_set |= pf->hash_input_set[pctype]; 9649 } 9650 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9651 I40E_INSET_MASK_NUM_REG); 9652 if (num < 0) 9653 return -EINVAL; 9654 9655 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 9656 9657 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype), 9658 (uint32_t)(inset_reg & UINT32_MAX)); 9659 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), 9660 (uint32_t)((inset_reg >> 9661 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9662 9663 for (i = 0; i < num; i++) 9664 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 9665 mask_reg[i]); 9666 /*clear unused mask registers of the pctype */ 9667 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 9668 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 9669 0); 9670 I40E_WRITE_FLUSH(hw); 9671 9672 pf->hash_input_set[pctype] = input_set; 9673 return 0; 9674 } 9675 9676 int 9677 i40e_fdir_filter_inset_select(struct i40e_pf *pf, 9678 struct rte_eth_input_set_conf *conf) 9679 { 9680 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9681 enum i40e_filter_pctype pctype; 9682 uint64_t input_set, inset_reg = 0; 9683 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9684 int ret, i, num; 9685 9686 if (!hw || !conf) { 9687 PMD_DRV_LOG(ERR, "Invalid pointer"); 9688 return -EFAULT; 9689 } 9690 if (conf->op != RTE_ETH_INPUT_SET_SELECT && 9691 conf->op != RTE_ETH_INPUT_SET_ADD) { 9692 PMD_DRV_LOG(ERR, "Unsupported input set operation"); 9693 return -EINVAL; 9694 } 9695 9696 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); 9697 9698 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 9699 PMD_DRV_LOG(ERR, "invalid flow_type input."); 9700 return -EINVAL; 9701 } 9702 9703 ret = i40e_parse_input_set(&input_set, pctype, conf->field, 9704 conf->inset_size); 9705 if (ret) { 9706 PMD_DRV_LOG(ERR, "Failed to parse input set"); 9707 return -EINVAL; 9708 } 9709 9710 /* get inset value in register */ 9711 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1)); 9712 inset_reg <<= I40E_32_BIT_WIDTH; 9713 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0)); 9714 9715 /* Can not change the inset reg for flex payload for fdir, 9716 * it is done by writing I40E_PRTQF_FD_FLXINSET 9717 * in i40e_set_flex_mask_on_pctype. 9718 */ 9719 if (conf->op == RTE_ETH_INPUT_SET_SELECT) 9720 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS; 9721 else 9722 input_set |= pf->fdir.input_set[pctype]; 9723 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9724 I40E_INSET_MASK_NUM_REG); 9725 if (num < 0) 9726 return -EINVAL; 9727 if (pf->support_multi_driver && num > 0) { 9728 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); 9729 return -ENOTSUP; 9730 } 9731 9732 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 9733 9734 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 9735 (uint32_t)(inset_reg & UINT32_MAX)); 9736 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 9737 (uint32_t)((inset_reg >> 9738 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9739 9740 if (!pf->support_multi_driver) { 9741 for (i = 0; i < num; i++) 9742 i40e_check_write_global_reg(hw, 9743 I40E_GLQF_FD_MSK(i, pctype), 9744 mask_reg[i]); 9745 /*clear unused mask registers of the pctype */ 9746 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 9747 i40e_check_write_global_reg(hw, 9748 I40E_GLQF_FD_MSK(i, pctype), 9749 0); 9750 } else { 9751 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); 9752 } 9753 I40E_WRITE_FLUSH(hw); 9754 9755 pf->fdir.input_set[pctype] = input_set; 9756 return 0; 9757 } 9758 9759 static int 9760 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) 9761 { 9762 int ret = 0; 9763 9764 if (!hw || !info) { 9765 PMD_DRV_LOG(ERR, "Invalid pointer"); 9766 return -EFAULT; 9767 } 9768 9769 switch (info->info_type) { 9770 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT: 9771 i40e_get_symmetric_hash_enable_per_port(hw, 9772 &(info->info.enable)); 9773 break; 9774 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG: 9775 ret = i40e_get_hash_filter_global_config(hw, 9776 &(info->info.global_conf)); 9777 break; 9778 default: 9779 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", 9780 info->info_type); 9781 ret = -EINVAL; 9782 break; 9783 } 9784 9785 return ret; 9786 } 9787 9788 static int 9789 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) 9790 { 9791 int ret = 0; 9792 9793 if (!hw || !info) { 9794 PMD_DRV_LOG(ERR, "Invalid pointer"); 9795 return -EFAULT; 9796 } 9797 9798 switch (info->info_type) { 9799 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT: 9800 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable); 9801 break; 9802 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG: 9803 ret = i40e_set_hash_filter_global_config(hw, 9804 &(info->info.global_conf)); 9805 break; 9806 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT: 9807 ret = i40e_hash_filter_inset_select(hw, 9808 &(info->info.input_set_conf)); 9809 break; 9810 9811 default: 9812 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", 9813 info->info_type); 9814 ret = -EINVAL; 9815 break; 9816 } 9817 9818 return ret; 9819 } 9820 9821 /* Operations for hash function */ 9822 static int 9823 i40e_hash_filter_ctrl(struct rte_eth_dev *dev, 9824 enum rte_filter_op filter_op, 9825 void *arg) 9826 { 9827 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 9828 int ret = 0; 9829 9830 switch (filter_op) { 9831 case RTE_ETH_FILTER_NOP: 9832 break; 9833 case RTE_ETH_FILTER_GET: 9834 ret = i40e_hash_filter_get(hw, 9835 (struct rte_eth_hash_filter_info *)arg); 9836 break; 9837 case RTE_ETH_FILTER_SET: 9838 ret = i40e_hash_filter_set(hw, 9839 (struct rte_eth_hash_filter_info *)arg); 9840 break; 9841 default: 9842 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported", 9843 filter_op); 9844 ret = -ENOTSUP; 9845 break; 9846 } 9847 9848 return ret; 9849 } 9850 9851 /* Convert ethertype filter structure */ 9852 static int 9853 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input, 9854 struct i40e_ethertype_filter *filter) 9855 { 9856 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN); 9857 filter->input.ether_type = input->ether_type; 9858 filter->flags = input->flags; 9859 filter->queue = input->queue; 9860 9861 return 0; 9862 } 9863 9864 /* Check if there exists the ehtertype filter */ 9865 struct i40e_ethertype_filter * 9866 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 9867 const struct i40e_ethertype_filter_input *input) 9868 { 9869 int ret; 9870 9871 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input); 9872 if (ret < 0) 9873 return NULL; 9874 9875 return ethertype_rule->hash_map[ret]; 9876 } 9877 9878 /* Add ethertype filter in SW list */ 9879 static int 9880 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf, 9881 struct i40e_ethertype_filter *filter) 9882 { 9883 struct i40e_ethertype_rule *rule = &pf->ethertype; 9884 int ret; 9885 9886 ret = rte_hash_add_key(rule->hash_table, &filter->input); 9887 if (ret < 0) { 9888 PMD_DRV_LOG(ERR, 9889 "Failed to insert ethertype filter" 9890 " to hash table %d!", 9891 ret); 9892 return ret; 9893 } 9894 rule->hash_map[ret] = filter; 9895 9896 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules); 9897 9898 return 0; 9899 } 9900 9901 /* Delete ethertype filter in SW list */ 9902 int 9903 i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 9904 struct i40e_ethertype_filter_input *input) 9905 { 9906 struct i40e_ethertype_rule *rule = &pf->ethertype; 9907 struct i40e_ethertype_filter *filter; 9908 int ret; 9909 9910 ret = rte_hash_del_key(rule->hash_table, input); 9911 if (ret < 0) { 9912 PMD_DRV_LOG(ERR, 9913 "Failed to delete ethertype filter" 9914 " to hash table %d!", 9915 ret); 9916 return ret; 9917 } 9918 filter = rule->hash_map[ret]; 9919 rule->hash_map[ret] = NULL; 9920 9921 TAILQ_REMOVE(&rule->ethertype_list, filter, rules); 9922 rte_free(filter); 9923 9924 return 0; 9925 } 9926 9927 /* 9928 * Configure ethertype filter, which can director packet by filtering 9929 * with mac address and ether_type or only ether_type 9930 */ 9931 int 9932 i40e_ethertype_filter_set(struct i40e_pf *pf, 9933 struct rte_eth_ethertype_filter *filter, 9934 bool add) 9935 { 9936 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9937 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 9938 struct i40e_ethertype_filter *ethertype_filter, *node; 9939 struct i40e_ethertype_filter check_filter; 9940 struct i40e_control_filter_stats stats; 9941 uint16_t flags = 0; 9942 int ret; 9943 9944 if (filter->queue >= pf->dev_data->nb_rx_queues) { 9945 PMD_DRV_LOG(ERR, "Invalid queue ID"); 9946 return -EINVAL; 9947 } 9948 if (filter->ether_type == ETHER_TYPE_IPv4 || 9949 filter->ether_type == ETHER_TYPE_IPv6) { 9950 PMD_DRV_LOG(ERR, 9951 "unsupported ether_type(0x%04x) in control packet filter.", 9952 filter->ether_type); 9953 return -EINVAL; 9954 } 9955 if (filter->ether_type == ETHER_TYPE_VLAN) 9956 PMD_DRV_LOG(WARNING, 9957 "filter vlan ether_type in first tag is not supported."); 9958 9959 /* Check if there is the filter in SW list */ 9960 memset(&check_filter, 0, sizeof(check_filter)); 9961 i40e_ethertype_filter_convert(filter, &check_filter); 9962 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, 9963 &check_filter.input); 9964 if (add && node) { 9965 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!"); 9966 return -EINVAL; 9967 } 9968 9969 if (!add && !node) { 9970 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!"); 9971 return -EINVAL; 9972 } 9973 9974 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC)) 9975 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 9976 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) 9977 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 9978 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 9979 9980 memset(&stats, 0, sizeof(stats)); 9981 ret = i40e_aq_add_rem_control_packet_filter(hw, 9982 filter->mac_addr.addr_bytes, 9983 filter->ether_type, flags, 9984 pf->main_vsi->seid, 9985 filter->queue, add, &stats, NULL); 9986 9987 PMD_DRV_LOG(INFO, 9988 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u", 9989 ret, stats.mac_etype_used, stats.etype_used, 9990 stats.mac_etype_free, stats.etype_free); 9991 if (ret < 0) 9992 return -ENOSYS; 9993 9994 /* Add or delete a filter in SW list */ 9995 if (add) { 9996 ethertype_filter = rte_zmalloc("ethertype_filter", 9997 sizeof(*ethertype_filter), 0); 9998 if (ethertype_filter == NULL) { 9999 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 10000 return -ENOMEM; 10001 } 10002 10003 rte_memcpy(ethertype_filter, &check_filter, 10004 sizeof(check_filter)); 10005 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter); 10006 if (ret < 0) 10007 rte_free(ethertype_filter); 10008 } else { 10009 ret = i40e_sw_ethertype_filter_del(pf, &node->input); 10010 } 10011 10012 return ret; 10013 } 10014 10015 /* 10016 * Handle operations for ethertype filter. 10017 */ 10018 static int 10019 i40e_ethertype_filter_handle(struct rte_eth_dev *dev, 10020 enum rte_filter_op filter_op, 10021 void *arg) 10022 { 10023 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10024 int ret = 0; 10025 10026 if (filter_op == RTE_ETH_FILTER_NOP) 10027 return ret; 10028 10029 if (arg == NULL) { 10030 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 10031 filter_op); 10032 return -EINVAL; 10033 } 10034 10035 switch (filter_op) { 10036 case RTE_ETH_FILTER_ADD: 10037 ret = i40e_ethertype_filter_set(pf, 10038 (struct rte_eth_ethertype_filter *)arg, 10039 TRUE); 10040 break; 10041 case RTE_ETH_FILTER_DELETE: 10042 ret = i40e_ethertype_filter_set(pf, 10043 (struct rte_eth_ethertype_filter *)arg, 10044 FALSE); 10045 break; 10046 default: 10047 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 10048 ret = -ENOSYS; 10049 break; 10050 } 10051 return ret; 10052 } 10053 10054 static int 10055 i40e_dev_filter_ctrl(struct rte_eth_dev *dev, 10056 enum rte_filter_type filter_type, 10057 enum rte_filter_op filter_op, 10058 void *arg) 10059 { 10060 int ret = 0; 10061 10062 if (dev == NULL) 10063 return -EINVAL; 10064 10065 switch (filter_type) { 10066 case RTE_ETH_FILTER_NONE: 10067 /* For global configuration */ 10068 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg); 10069 break; 10070 case RTE_ETH_FILTER_HASH: 10071 ret = i40e_hash_filter_ctrl(dev, filter_op, arg); 10072 break; 10073 case RTE_ETH_FILTER_MACVLAN: 10074 ret = i40e_mac_filter_handle(dev, filter_op, arg); 10075 break; 10076 case RTE_ETH_FILTER_ETHERTYPE: 10077 ret = i40e_ethertype_filter_handle(dev, filter_op, arg); 10078 break; 10079 case RTE_ETH_FILTER_TUNNEL: 10080 ret = i40e_tunnel_filter_handle(dev, filter_op, arg); 10081 break; 10082 case RTE_ETH_FILTER_FDIR: 10083 ret = i40e_fdir_ctrl_func(dev, filter_op, arg); 10084 break; 10085 case RTE_ETH_FILTER_GENERIC: 10086 if (filter_op != RTE_ETH_FILTER_GET) 10087 return -EINVAL; 10088 *(const void **)arg = &i40e_flow_ops; 10089 break; 10090 default: 10091 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 10092 filter_type); 10093 ret = -EINVAL; 10094 break; 10095 } 10096 10097 return ret; 10098 } 10099 10100 /* 10101 * Check and enable Extended Tag. 10102 * Enabling Extended Tag is important for 40G performance. 10103 */ 10104 static void 10105 i40e_enable_extended_tag(struct rte_eth_dev *dev) 10106 { 10107 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 10108 uint32_t buf = 0; 10109 int ret; 10110 10111 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf), 10112 PCI_DEV_CAP_REG); 10113 if (ret < 0) { 10114 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", 10115 PCI_DEV_CAP_REG); 10116 return; 10117 } 10118 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { 10119 PMD_DRV_LOG(ERR, "Does not support Extended Tag"); 10120 return; 10121 } 10122 10123 buf = 0; 10124 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf), 10125 PCI_DEV_CTRL_REG); 10126 if (ret < 0) { 10127 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", 10128 PCI_DEV_CTRL_REG); 10129 return; 10130 } 10131 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { 10132 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); 10133 return; 10134 } 10135 buf |= PCI_DEV_CTRL_EXT_TAG_MASK; 10136 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf), 10137 PCI_DEV_CTRL_REG); 10138 if (ret < 0) { 10139 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", 10140 PCI_DEV_CTRL_REG); 10141 return; 10142 } 10143 } 10144 10145 /* 10146 * As some registers wouldn't be reset unless a global hardware reset, 10147 * hardware initialization is needed to put those registers into an 10148 * expected initial state. 10149 */ 10150 static void 10151 i40e_hw_init(struct rte_eth_dev *dev) 10152 { 10153 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10154 10155 i40e_enable_extended_tag(dev); 10156 10157 /* clear the PF Queue Filter control register */ 10158 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0); 10159 10160 /* Disable symmetric hash per port */ 10161 i40e_set_symmetric_hash_enable_per_port(hw, 0); 10162 } 10163 10164 /* 10165 * For X722 it is possible to have multiple pctypes mapped to the same flowtype 10166 * however this function will return only one highest pctype index, 10167 * which is not quite correct. This is known problem of i40e driver 10168 * and needs to be fixed later. 10169 */ 10170 enum i40e_filter_pctype 10171 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type) 10172 { 10173 int i; 10174 uint64_t pctype_mask; 10175 10176 if (flow_type < I40E_FLOW_TYPE_MAX) { 10177 pctype_mask = adapter->pctypes_tbl[flow_type]; 10178 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) { 10179 if (pctype_mask & (1ULL << i)) 10180 return (enum i40e_filter_pctype)i; 10181 } 10182 } 10183 return I40E_FILTER_PCTYPE_INVALID; 10184 } 10185 10186 uint16_t 10187 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 10188 enum i40e_filter_pctype pctype) 10189 { 10190 uint16_t flowtype; 10191 uint64_t pctype_mask = 1ULL << pctype; 10192 10193 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX; 10194 flowtype++) { 10195 if (adapter->pctypes_tbl[flowtype] & pctype_mask) 10196 return flowtype; 10197 } 10198 10199 return RTE_ETH_FLOW_UNKNOWN; 10200 } 10201 10202 /* 10203 * On X710, performance number is far from the expectation on recent firmware 10204 * versions; on XL710, performance number is also far from the expectation on 10205 * recent firmware versions, if promiscuous mode is disabled, or promiscuous 10206 * mode is enabled and port MAC address is equal to the packet destination MAC 10207 * address. The fix for this issue may not be integrated in the following 10208 * firmware version. So the workaround in software driver is needed. It needs 10209 * to modify the initial values of 3 internal only registers for both X710 and 10210 * XL710. Note that the values for X710 or XL710 could be different, and the 10211 * workaround can be removed when it is fixed in firmware in the future. 10212 */ 10213 10214 /* For both X710 and XL710 */ 10215 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200 10216 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200 10217 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00 10218 10219 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200 10220 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08 10221 10222 /* For X722 */ 10223 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200 10224 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200 10225 10226 /* For X710 */ 10227 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303 10228 /* For XL710 */ 10229 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606 10230 #define I40E_GL_SWR_PM_UP_THR 0x269FBC 10231 10232 /* 10233 * GL_SWR_PM_UP_THR: 10234 * The value is not impacted from the link speed, its value is set according 10235 * to the total number of ports for a better pipe-monitor configuration. 10236 */ 10237 static bool 10238 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value) 10239 { 10240 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \ 10241 .device_id = (dev), \ 10242 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE 10243 10244 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \ 10245 .device_id = (dev), \ 10246 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE 10247 10248 static const struct { 10249 uint16_t device_id; 10250 uint32_t val; 10251 } swr_pm_table[] = { 10252 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) }, 10253 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) }, 10254 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) }, 10255 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) }, 10256 10257 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) }, 10258 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) }, 10259 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) }, 10260 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) }, 10261 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) }, 10262 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) }, 10263 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) }, 10264 }; 10265 uint32_t i; 10266 10267 if (value == NULL) { 10268 PMD_DRV_LOG(ERR, "value is NULL"); 10269 return false; 10270 } 10271 10272 for (i = 0; i < RTE_DIM(swr_pm_table); i++) { 10273 if (hw->device_id == swr_pm_table[i].device_id) { 10274 *value = swr_pm_table[i].val; 10275 10276 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR " 10277 "value - 0x%08x", 10278 hw->device_id, *value); 10279 return true; 10280 } 10281 } 10282 10283 return false; 10284 } 10285 10286 static int 10287 i40e_dev_sync_phy_type(struct i40e_hw *hw) 10288 { 10289 enum i40e_status_code status; 10290 struct i40e_aq_get_phy_abilities_resp phy_ab; 10291 int ret = -ENOTSUP; 10292 int retries = 0; 10293 10294 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, 10295 NULL); 10296 10297 while (status) { 10298 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d", 10299 status); 10300 retries++; 10301 rte_delay_us(100000); 10302 if (retries < 5) 10303 status = i40e_aq_get_phy_capabilities(hw, false, 10304 true, &phy_ab, NULL); 10305 else 10306 return ret; 10307 } 10308 return 0; 10309 } 10310 10311 static void 10312 i40e_configure_registers(struct i40e_hw *hw) 10313 { 10314 static struct { 10315 uint32_t addr; 10316 uint64_t val; 10317 } reg_table[] = { 10318 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0}, 10319 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0}, 10320 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */ 10321 }; 10322 uint64_t reg; 10323 uint32_t i; 10324 int ret; 10325 10326 for (i = 0; i < RTE_DIM(reg_table); i++) { 10327 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) { 10328 if (hw->mac.type == I40E_MAC_X722) /* For X722 */ 10329 reg_table[i].val = 10330 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE; 10331 else /* For X710/XL710/XXV710 */ 10332 if (hw->aq.fw_maj_ver < 6) 10333 reg_table[i].val = 10334 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1; 10335 else 10336 reg_table[i].val = 10337 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2; 10338 } 10339 10340 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) { 10341 if (hw->mac.type == I40E_MAC_X722) /* For X722 */ 10342 reg_table[i].val = 10343 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE; 10344 else /* For X710/XL710/XXV710 */ 10345 reg_table[i].val = 10346 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE; 10347 } 10348 10349 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) { 10350 uint32_t cfg_val; 10351 10352 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) { 10353 PMD_DRV_LOG(DEBUG, "Device 0x%x skips " 10354 "GL_SWR_PM_UP_THR value fixup", 10355 hw->device_id); 10356 continue; 10357 } 10358 10359 reg_table[i].val = cfg_val; 10360 } 10361 10362 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr, 10363 ®, NULL); 10364 if (ret < 0) { 10365 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32, 10366 reg_table[i].addr); 10367 break; 10368 } 10369 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64, 10370 reg_table[i].addr, reg); 10371 if (reg == reg_table[i].val) 10372 continue; 10373 10374 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr, 10375 reg_table[i].val, NULL); 10376 if (ret < 0) { 10377 PMD_DRV_LOG(ERR, 10378 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32, 10379 reg_table[i].val, reg_table[i].addr); 10380 break; 10381 } 10382 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of " 10383 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr); 10384 } 10385 } 10386 10387 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4)) 10388 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030 10389 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4)) 10390 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab 10391 static int 10392 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi) 10393 { 10394 uint32_t reg; 10395 int ret; 10396 10397 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) { 10398 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum"); 10399 return -EINVAL; 10400 } 10401 10402 /* Configure for double VLAN RX stripping */ 10403 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id)); 10404 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) { 10405 reg |= I40E_VSI_TSR_QINQ_CONFIG; 10406 ret = i40e_aq_debug_write_register(hw, 10407 I40E_VSI_TSR(vsi->vsi_id), 10408 reg, NULL); 10409 if (ret < 0) { 10410 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]", 10411 vsi->vsi_id); 10412 return I40E_ERR_CONFIG; 10413 } 10414 } 10415 10416 /* Configure for double VLAN TX insertion */ 10417 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id)); 10418 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) { 10419 reg = I40E_VSI_L2TAGSTXVALID_QINQ; 10420 ret = i40e_aq_debug_write_register(hw, 10421 I40E_VSI_L2TAGSTXVALID( 10422 vsi->vsi_id), reg, NULL); 10423 if (ret < 0) { 10424 PMD_DRV_LOG(ERR, 10425 "Failed to update VSI_L2TAGSTXVALID[%d]", 10426 vsi->vsi_id); 10427 return I40E_ERR_CONFIG; 10428 } 10429 } 10430 10431 return 0; 10432 } 10433 10434 /** 10435 * i40e_aq_add_mirror_rule 10436 * @hw: pointer to the hardware structure 10437 * @seid: VEB seid to add mirror rule to 10438 * @dst_id: destination vsi seid 10439 * @entries: Buffer which contains the entities to be mirrored 10440 * @count: number of entities contained in the buffer 10441 * @rule_id:the rule_id of the rule to be added 10442 * 10443 * Add a mirror rule for a given veb. 10444 * 10445 **/ 10446 static enum i40e_status_code 10447 i40e_aq_add_mirror_rule(struct i40e_hw *hw, 10448 uint16_t seid, uint16_t dst_id, 10449 uint16_t rule_type, uint16_t *entries, 10450 uint16_t count, uint16_t *rule_id) 10451 { 10452 struct i40e_aq_desc desc; 10453 struct i40e_aqc_add_delete_mirror_rule cmd; 10454 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 10455 (struct i40e_aqc_add_delete_mirror_rule_completion *) 10456 &desc.params.raw; 10457 uint16_t buff_len; 10458 enum i40e_status_code status; 10459 10460 i40e_fill_default_direct_cmd_desc(&desc, 10461 i40e_aqc_opc_add_mirror_rule); 10462 memset(&cmd, 0, sizeof(cmd)); 10463 10464 buff_len = sizeof(uint16_t) * count; 10465 desc.datalen = rte_cpu_to_le_16(buff_len); 10466 if (buff_len > 0) 10467 desc.flags |= rte_cpu_to_le_16( 10468 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 10469 cmd.rule_type = rte_cpu_to_le_16(rule_type << 10470 I40E_AQC_MIRROR_RULE_TYPE_SHIFT); 10471 cmd.num_entries = rte_cpu_to_le_16(count); 10472 cmd.seid = rte_cpu_to_le_16(seid); 10473 cmd.destination = rte_cpu_to_le_16(dst_id); 10474 10475 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd)); 10476 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL); 10477 PMD_DRV_LOG(INFO, 10478 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,", 10479 hw->aq.asq_last_status, resp->rule_id, 10480 resp->mirror_rules_used, resp->mirror_rules_free); 10481 *rule_id = rte_le_to_cpu_16(resp->rule_id); 10482 10483 return status; 10484 } 10485 10486 /** 10487 * i40e_aq_del_mirror_rule 10488 * @hw: pointer to the hardware structure 10489 * @seid: VEB seid to add mirror rule to 10490 * @entries: Buffer which contains the entities to be mirrored 10491 * @count: number of entities contained in the buffer 10492 * @rule_id:the rule_id of the rule to be delete 10493 * 10494 * Delete a mirror rule for a given veb. 10495 * 10496 **/ 10497 static enum i40e_status_code 10498 i40e_aq_del_mirror_rule(struct i40e_hw *hw, 10499 uint16_t seid, uint16_t rule_type, uint16_t *entries, 10500 uint16_t count, uint16_t rule_id) 10501 { 10502 struct i40e_aq_desc desc; 10503 struct i40e_aqc_add_delete_mirror_rule cmd; 10504 uint16_t buff_len = 0; 10505 enum i40e_status_code status; 10506 void *buff = NULL; 10507 10508 i40e_fill_default_direct_cmd_desc(&desc, 10509 i40e_aqc_opc_delete_mirror_rule); 10510 memset(&cmd, 0, sizeof(cmd)); 10511 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 10512 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF | 10513 I40E_AQ_FLAG_RD)); 10514 cmd.num_entries = count; 10515 buff_len = sizeof(uint16_t) * count; 10516 desc.datalen = rte_cpu_to_le_16(buff_len); 10517 buff = (void *)entries; 10518 } else 10519 /* rule id is filled in destination field for deleting mirror rule */ 10520 cmd.destination = rte_cpu_to_le_16(rule_id); 10521 10522 cmd.rule_type = rte_cpu_to_le_16(rule_type << 10523 I40E_AQC_MIRROR_RULE_TYPE_SHIFT); 10524 cmd.seid = rte_cpu_to_le_16(seid); 10525 10526 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd)); 10527 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL); 10528 10529 return status; 10530 } 10531 10532 /** 10533 * i40e_mirror_rule_set 10534 * @dev: pointer to the hardware structure 10535 * @mirror_conf: mirror rule info 10536 * @sw_id: mirror rule's sw_id 10537 * @on: enable/disable 10538 * 10539 * set a mirror rule. 10540 * 10541 **/ 10542 static int 10543 i40e_mirror_rule_set(struct rte_eth_dev *dev, 10544 struct rte_eth_mirror_conf *mirror_conf, 10545 uint8_t sw_id, uint8_t on) 10546 { 10547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10549 struct i40e_mirror_rule *it, *mirr_rule = NULL; 10550 struct i40e_mirror_rule *parent = NULL; 10551 uint16_t seid, dst_seid, rule_id; 10552 uint16_t i, j = 0; 10553 int ret; 10554 10555 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id); 10556 10557 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) { 10558 PMD_DRV_LOG(ERR, 10559 "mirror rule can not be configured without veb or vfs."); 10560 return -ENOSYS; 10561 } 10562 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) { 10563 PMD_DRV_LOG(ERR, "mirror table is full."); 10564 return -ENOSPC; 10565 } 10566 if (mirror_conf->dst_pool > pf->vf_num) { 10567 PMD_DRV_LOG(ERR, "invalid destination pool %u.", 10568 mirror_conf->dst_pool); 10569 return -EINVAL; 10570 } 10571 10572 seid = pf->main_vsi->veb->seid; 10573 10574 TAILQ_FOREACH(it, &pf->mirror_list, rules) { 10575 if (sw_id <= it->index) { 10576 mirr_rule = it; 10577 break; 10578 } 10579 parent = it; 10580 } 10581 if (mirr_rule && sw_id == mirr_rule->index) { 10582 if (on) { 10583 PMD_DRV_LOG(ERR, "mirror rule exists."); 10584 return -EEXIST; 10585 } else { 10586 ret = i40e_aq_del_mirror_rule(hw, seid, 10587 mirr_rule->rule_type, 10588 mirr_rule->entries, 10589 mirr_rule->num_entries, mirr_rule->id); 10590 if (ret < 0) { 10591 PMD_DRV_LOG(ERR, 10592 "failed to remove mirror rule: ret = %d, aq_err = %d.", 10593 ret, hw->aq.asq_last_status); 10594 return -ENOSYS; 10595 } 10596 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules); 10597 rte_free(mirr_rule); 10598 pf->nb_mirror_rule--; 10599 return 0; 10600 } 10601 } else if (!on) { 10602 PMD_DRV_LOG(ERR, "mirror rule doesn't exist."); 10603 return -ENOENT; 10604 } 10605 10606 mirr_rule = rte_zmalloc("i40e_mirror_rule", 10607 sizeof(struct i40e_mirror_rule) , 0); 10608 if (!mirr_rule) { 10609 PMD_DRV_LOG(ERR, "failed to allocate memory"); 10610 return I40E_ERR_NO_MEMORY; 10611 } 10612 switch (mirror_conf->rule_type) { 10613 case ETH_MIRROR_VLAN: 10614 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) { 10615 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 10616 mirr_rule->entries[j] = 10617 mirror_conf->vlan.vlan_id[i]; 10618 j++; 10619 } 10620 } 10621 if (j == 0) { 10622 PMD_DRV_LOG(ERR, "vlan is not specified."); 10623 rte_free(mirr_rule); 10624 return -EINVAL; 10625 } 10626 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN; 10627 break; 10628 case ETH_MIRROR_VIRTUAL_POOL_UP: 10629 case ETH_MIRROR_VIRTUAL_POOL_DOWN: 10630 /* check if the specified pool bit is out of range */ 10631 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) { 10632 PMD_DRV_LOG(ERR, "pool mask is out of range."); 10633 rte_free(mirr_rule); 10634 return -EINVAL; 10635 } 10636 for (i = 0, j = 0; i < pf->vf_num; i++) { 10637 if (mirror_conf->pool_mask & (1ULL << i)) { 10638 mirr_rule->entries[j] = pf->vfs[i].vsi->seid; 10639 j++; 10640 } 10641 } 10642 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) { 10643 /* add pf vsi to entries */ 10644 mirr_rule->entries[j] = pf->main_vsi_seid; 10645 j++; 10646 } 10647 if (j == 0) { 10648 PMD_DRV_LOG(ERR, "pool is not specified."); 10649 rte_free(mirr_rule); 10650 return -EINVAL; 10651 } 10652 /* egress and ingress in aq commands means from switch but not port */ 10653 mirr_rule->rule_type = 10654 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ? 10655 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS : 10656 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS; 10657 break; 10658 case ETH_MIRROR_UPLINK_PORT: 10659 /* egress and ingress in aq commands means from switch but not port*/ 10660 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS; 10661 break; 10662 case ETH_MIRROR_DOWNLINK_PORT: 10663 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS; 10664 break; 10665 default: 10666 PMD_DRV_LOG(ERR, "unsupported mirror type %d.", 10667 mirror_conf->rule_type); 10668 rte_free(mirr_rule); 10669 return -EINVAL; 10670 } 10671 10672 /* If the dst_pool is equal to vf_num, consider it as PF */ 10673 if (mirror_conf->dst_pool == pf->vf_num) 10674 dst_seid = pf->main_vsi_seid; 10675 else 10676 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid; 10677 10678 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid, 10679 mirr_rule->rule_type, mirr_rule->entries, 10680 j, &rule_id); 10681 if (ret < 0) { 10682 PMD_DRV_LOG(ERR, 10683 "failed to add mirror rule: ret = %d, aq_err = %d.", 10684 ret, hw->aq.asq_last_status); 10685 rte_free(mirr_rule); 10686 return -ENOSYS; 10687 } 10688 10689 mirr_rule->index = sw_id; 10690 mirr_rule->num_entries = j; 10691 mirr_rule->id = rule_id; 10692 mirr_rule->dst_vsi_seid = dst_seid; 10693 10694 if (parent) 10695 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules); 10696 else 10697 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules); 10698 10699 pf->nb_mirror_rule++; 10700 return 0; 10701 } 10702 10703 /** 10704 * i40e_mirror_rule_reset 10705 * @dev: pointer to the device 10706 * @sw_id: mirror rule's sw_id 10707 * 10708 * reset a mirror rule. 10709 * 10710 **/ 10711 static int 10712 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id) 10713 { 10714 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10716 struct i40e_mirror_rule *it, *mirr_rule = NULL; 10717 uint16_t seid; 10718 int ret; 10719 10720 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id); 10721 10722 seid = pf->main_vsi->veb->seid; 10723 10724 TAILQ_FOREACH(it, &pf->mirror_list, rules) { 10725 if (sw_id == it->index) { 10726 mirr_rule = it; 10727 break; 10728 } 10729 } 10730 if (mirr_rule) { 10731 ret = i40e_aq_del_mirror_rule(hw, seid, 10732 mirr_rule->rule_type, 10733 mirr_rule->entries, 10734 mirr_rule->num_entries, mirr_rule->id); 10735 if (ret < 0) { 10736 PMD_DRV_LOG(ERR, 10737 "failed to remove mirror rule: status = %d, aq_err = %d.", 10738 ret, hw->aq.asq_last_status); 10739 return -ENOSYS; 10740 } 10741 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules); 10742 rte_free(mirr_rule); 10743 pf->nb_mirror_rule--; 10744 } else { 10745 PMD_DRV_LOG(ERR, "mirror rule doesn't exist."); 10746 return -ENOENT; 10747 } 10748 return 0; 10749 } 10750 10751 static uint64_t 10752 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev) 10753 { 10754 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10755 uint64_t systim_cycles; 10756 10757 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L); 10758 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H) 10759 << 32; 10760 10761 return systim_cycles; 10762 } 10763 10764 static uint64_t 10765 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index) 10766 { 10767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10768 uint64_t rx_tstamp; 10769 10770 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index)); 10771 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index)) 10772 << 32; 10773 10774 return rx_tstamp; 10775 } 10776 10777 static uint64_t 10778 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 10779 { 10780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10781 uint64_t tx_tstamp; 10782 10783 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L); 10784 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H) 10785 << 32; 10786 10787 return tx_tstamp; 10788 } 10789 10790 static void 10791 i40e_start_timecounters(struct rte_eth_dev *dev) 10792 { 10793 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10794 struct i40e_adapter *adapter = 10795 (struct i40e_adapter *)dev->data->dev_private; 10796 struct rte_eth_link link; 10797 uint32_t tsync_inc_l; 10798 uint32_t tsync_inc_h; 10799 10800 /* Get current link speed. */ 10801 i40e_dev_link_update(dev, 1); 10802 rte_eth_linkstatus_get(dev, &link); 10803 10804 switch (link.link_speed) { 10805 case ETH_SPEED_NUM_40G: 10806 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF; 10807 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32; 10808 break; 10809 case ETH_SPEED_NUM_10G: 10810 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF; 10811 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32; 10812 break; 10813 case ETH_SPEED_NUM_1G: 10814 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF; 10815 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32; 10816 break; 10817 default: 10818 tsync_inc_l = 0x0; 10819 tsync_inc_h = 0x0; 10820 } 10821 10822 /* Set the timesync increment value. */ 10823 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l); 10824 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h); 10825 10826 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 10827 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 10828 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 10829 10830 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10831 adapter->systime_tc.cc_shift = 0; 10832 adapter->systime_tc.nsec_mask = 0; 10833 10834 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10835 adapter->rx_tstamp_tc.cc_shift = 0; 10836 adapter->rx_tstamp_tc.nsec_mask = 0; 10837 10838 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10839 adapter->tx_tstamp_tc.cc_shift = 0; 10840 adapter->tx_tstamp_tc.nsec_mask = 0; 10841 } 10842 10843 static int 10844 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 10845 { 10846 struct i40e_adapter *adapter = 10847 (struct i40e_adapter *)dev->data->dev_private; 10848 10849 adapter->systime_tc.nsec += delta; 10850 adapter->rx_tstamp_tc.nsec += delta; 10851 adapter->tx_tstamp_tc.nsec += delta; 10852 10853 return 0; 10854 } 10855 10856 static int 10857 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 10858 { 10859 uint64_t ns; 10860 struct i40e_adapter *adapter = 10861 (struct i40e_adapter *)dev->data->dev_private; 10862 10863 ns = rte_timespec_to_ns(ts); 10864 10865 /* Set the timecounters to a new value. */ 10866 adapter->systime_tc.nsec = ns; 10867 adapter->rx_tstamp_tc.nsec = ns; 10868 adapter->tx_tstamp_tc.nsec = ns; 10869 10870 return 0; 10871 } 10872 10873 static int 10874 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 10875 { 10876 uint64_t ns, systime_cycles; 10877 struct i40e_adapter *adapter = 10878 (struct i40e_adapter *)dev->data->dev_private; 10879 10880 systime_cycles = i40e_read_systime_cyclecounter(dev); 10881 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 10882 *ts = rte_ns_to_timespec(ns); 10883 10884 return 0; 10885 } 10886 10887 static int 10888 i40e_timesync_enable(struct rte_eth_dev *dev) 10889 { 10890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10891 uint32_t tsync_ctl_l; 10892 uint32_t tsync_ctl_h; 10893 10894 /* Stop the timesync system time. */ 10895 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); 10896 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); 10897 /* Reset the timesync system time value. */ 10898 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0); 10899 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0); 10900 10901 i40e_start_timecounters(dev); 10902 10903 /* Clear timesync registers. */ 10904 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); 10905 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H); 10906 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0)); 10907 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1)); 10908 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2)); 10909 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3)); 10910 10911 /* Enable timestamping of PTP packets. */ 10912 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); 10913 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA; 10914 10915 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); 10916 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA; 10917 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE; 10918 10919 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); 10920 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); 10921 10922 return 0; 10923 } 10924 10925 static int 10926 i40e_timesync_disable(struct rte_eth_dev *dev) 10927 { 10928 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10929 uint32_t tsync_ctl_l; 10930 uint32_t tsync_ctl_h; 10931 10932 /* Disable timestamping of transmitted PTP packets. */ 10933 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); 10934 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA; 10935 10936 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); 10937 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA; 10938 10939 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); 10940 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); 10941 10942 /* Reset the timesync increment value. */ 10943 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); 10944 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); 10945 10946 return 0; 10947 } 10948 10949 static int 10950 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 10951 struct timespec *timestamp, uint32_t flags) 10952 { 10953 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10954 struct i40e_adapter *adapter = 10955 (struct i40e_adapter *)dev->data->dev_private; 10956 10957 uint32_t sync_status; 10958 uint32_t index = flags & 0x03; 10959 uint64_t rx_tstamp_cycles; 10960 uint64_t ns; 10961 10962 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1); 10963 if ((sync_status & (1 << index)) == 0) 10964 return -EINVAL; 10965 10966 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index); 10967 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 10968 *timestamp = rte_ns_to_timespec(ns); 10969 10970 return 0; 10971 } 10972 10973 static int 10974 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 10975 struct timespec *timestamp) 10976 { 10977 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10978 struct i40e_adapter *adapter = 10979 (struct i40e_adapter *)dev->data->dev_private; 10980 10981 uint32_t sync_status; 10982 uint64_t tx_tstamp_cycles; 10983 uint64_t ns; 10984 10985 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); 10986 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0) 10987 return -EINVAL; 10988 10989 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev); 10990 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 10991 *timestamp = rte_ns_to_timespec(ns); 10992 10993 return 0; 10994 } 10995 10996 /* 10997 * i40e_parse_dcb_configure - parse dcb configure from user 10998 * @dev: the device being configured 10999 * @dcb_cfg: pointer of the result of parse 11000 * @*tc_map: bit map of enabled traffic classes 11001 * 11002 * Returns 0 on success, negative value on failure 11003 */ 11004 static int 11005 i40e_parse_dcb_configure(struct rte_eth_dev *dev, 11006 struct i40e_dcbx_config *dcb_cfg, 11007 uint8_t *tc_map) 11008 { 11009 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 11010 uint8_t i, tc_bw, bw_lf; 11011 11012 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config)); 11013 11014 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 11015 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) { 11016 PMD_INIT_LOG(ERR, "number of tc exceeds max."); 11017 return -EINVAL; 11018 } 11019 11020 /* assume each tc has the same bw */ 11021 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs; 11022 for (i = 0; i < dcb_rx_conf->nb_tcs; i++) 11023 dcb_cfg->etscfg.tcbwtable[i] = tc_bw; 11024 /* to ensure the sum of tcbw is equal to 100 */ 11025 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs; 11026 for (i = 0; i < bw_lf; i++) 11027 dcb_cfg->etscfg.tcbwtable[i]++; 11028 11029 /* assume each tc has the same Transmission Selection Algorithm */ 11030 for (i = 0; i < dcb_rx_conf->nb_tcs; i++) 11031 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS; 11032 11033 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11034 dcb_cfg->etscfg.prioritytable[i] = 11035 dcb_rx_conf->dcb_tc[i]; 11036 11037 /* FW needs one App to configure HW */ 11038 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM; 11039 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE; 11040 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO; 11041 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE; 11042 11043 if (dcb_rx_conf->nb_tcs == 0) 11044 *tc_map = 1; /* tc0 only */ 11045 else 11046 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t); 11047 11048 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) { 11049 dcb_cfg->pfc.willing = 0; 11050 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; 11051 dcb_cfg->pfc.pfcenable = *tc_map; 11052 } 11053 return 0; 11054 } 11055 11056 11057 static enum i40e_status_code 11058 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi, 11059 struct i40e_aqc_vsi_properties_data *info, 11060 uint8_t enabled_tcmap) 11061 { 11062 enum i40e_status_code ret; 11063 int i, total_tc = 0; 11064 uint16_t qpnum_per_tc, bsf, qp_idx; 11065 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi); 11066 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 11067 uint16_t used_queues; 11068 11069 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 11070 if (ret != I40E_SUCCESS) 11071 return ret; 11072 11073 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11074 if (enabled_tcmap & (1 << i)) 11075 total_tc++; 11076 } 11077 if (total_tc == 0) 11078 total_tc = 1; 11079 vsi->enabled_tc = enabled_tcmap; 11080 11081 /* different VSI has different queues assigned */ 11082 if (vsi->type == I40E_VSI_MAIN) 11083 used_queues = dev_data->nb_rx_queues - 11084 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 11085 else if (vsi->type == I40E_VSI_VMDQ2) 11086 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 11087 else { 11088 PMD_INIT_LOG(ERR, "unsupported VSI type."); 11089 return I40E_ERR_NO_AVAILABLE_VSI; 11090 } 11091 11092 qpnum_per_tc = used_queues / total_tc; 11093 /* Number of queues per enabled TC */ 11094 if (qpnum_per_tc == 0) { 11095 PMD_INIT_LOG(ERR, " number of queues is less that tcs."); 11096 return I40E_ERR_INVALID_QP_ID; 11097 } 11098 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc), 11099 I40E_MAX_Q_PER_TC); 11100 bsf = rte_bsf32(qpnum_per_tc); 11101 11102 /** 11103 * Configure TC and queue mapping parameters, for enabled TC, 11104 * allocate qpnum_per_tc queues to this traffic. For disabled TC, 11105 * default queue will serve it. 11106 */ 11107 qp_idx = 0; 11108 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11109 if (vsi->enabled_tc & (1 << i)) { 11110 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx << 11111 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 11112 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 11113 qp_idx += qpnum_per_tc; 11114 } else 11115 info->tc_mapping[i] = 0; 11116 } 11117 11118 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */ 11119 if (vsi->type == I40E_VSI_SRIOV) { 11120 info->mapping_flags |= 11121 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 11122 for (i = 0; i < vsi->nb_qps; i++) 11123 info->queue_mapping[i] = 11124 rte_cpu_to_le_16(vsi->base_queue + i); 11125 } else { 11126 info->mapping_flags |= 11127 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG); 11128 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 11129 } 11130 info->valid_sections |= 11131 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 11132 11133 return I40E_SUCCESS; 11134 } 11135 11136 /* 11137 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map 11138 * @veb: VEB to be configured 11139 * @tc_map: enabled TC bitmap 11140 * 11141 * Returns 0 on success, negative value on failure 11142 */ 11143 static enum i40e_status_code 11144 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map) 11145 { 11146 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw; 11147 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query; 11148 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query; 11149 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi); 11150 enum i40e_status_code ret = I40E_SUCCESS; 11151 int i; 11152 uint32_t bw_max; 11153 11154 /* Check if enabled_tc is same as existing or new TCs */ 11155 if (veb->enabled_tc == tc_map) 11156 return ret; 11157 11158 /* configure tc bandwidth */ 11159 memset(&veb_bw, 0, sizeof(veb_bw)); 11160 veb_bw.tc_valid_bits = tc_map; 11161 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 11162 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11163 if (tc_map & BIT_ULL(i)) 11164 veb_bw.tc_bw_share_credits[i] = 1; 11165 } 11166 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid, 11167 &veb_bw, NULL); 11168 if (ret) { 11169 PMD_INIT_LOG(ERR, 11170 "AQ command Config switch_comp BW allocation per TC failed = %d", 11171 hw->aq.asq_last_status); 11172 return ret; 11173 } 11174 11175 memset(&ets_query, 0, sizeof(ets_query)); 11176 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, 11177 &ets_query, NULL); 11178 if (ret != I40E_SUCCESS) { 11179 PMD_DRV_LOG(ERR, 11180 "Failed to get switch_comp ETS configuration %u", 11181 hw->aq.asq_last_status); 11182 return ret; 11183 } 11184 memset(&bw_query, 0, sizeof(bw_query)); 11185 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, 11186 &bw_query, NULL); 11187 if (ret != I40E_SUCCESS) { 11188 PMD_DRV_LOG(ERR, 11189 "Failed to get switch_comp bandwidth configuration %u", 11190 hw->aq.asq_last_status); 11191 return ret; 11192 } 11193 11194 /* store and print out BW info */ 11195 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit); 11196 veb->bw_info.bw_max = ets_query.tc_bw_max; 11197 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit); 11198 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max); 11199 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) | 11200 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) << 11201 I40E_16_BIT_WIDTH); 11202 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11203 veb->bw_info.bw_ets_share_credits[i] = 11204 bw_query.tc_bw_share_credits[i]; 11205 veb->bw_info.bw_ets_credits[i] = 11206 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]); 11207 /* 4 bits per TC, 4th bit is reserved */ 11208 veb->bw_info.bw_ets_max[i] = 11209 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) & 11210 RTE_LEN2MASK(3, uint8_t)); 11211 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i, 11212 veb->bw_info.bw_ets_share_credits[i]); 11213 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i, 11214 veb->bw_info.bw_ets_credits[i]); 11215 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i, 11216 veb->bw_info.bw_ets_max[i]); 11217 } 11218 11219 veb->enabled_tc = tc_map; 11220 11221 return ret; 11222 } 11223 11224 11225 /* 11226 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map 11227 * @vsi: VSI to be configured 11228 * @tc_map: enabled TC bitmap 11229 * 11230 * Returns 0 on success, negative value on failure 11231 */ 11232 static enum i40e_status_code 11233 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map) 11234 { 11235 struct i40e_aqc_configure_vsi_tc_bw_data bw_data; 11236 struct i40e_vsi_context ctxt; 11237 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 11238 enum i40e_status_code ret = I40E_SUCCESS; 11239 int i; 11240 11241 /* Check if enabled_tc is same as existing or new TCs */ 11242 if (vsi->enabled_tc == tc_map) 11243 return ret; 11244 11245 /* configure tc bandwidth */ 11246 memset(&bw_data, 0, sizeof(bw_data)); 11247 bw_data.tc_valid_bits = tc_map; 11248 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 11249 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11250 if (tc_map & BIT_ULL(i)) 11251 bw_data.tc_bw_credits[i] = 1; 11252 } 11253 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL); 11254 if (ret) { 11255 PMD_INIT_LOG(ERR, 11256 "AQ command Config VSI BW allocation per TC failed = %d", 11257 hw->aq.asq_last_status); 11258 goto out; 11259 } 11260 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 11261 vsi->info.qs_handle[i] = bw_data.qs_handles[i]; 11262 11263 /* Update Queue Pairs Mapping for currently enabled UPs */ 11264 ctxt.seid = vsi->seid; 11265 ctxt.pf_num = hw->pf_id; 11266 ctxt.vf_num = 0; 11267 ctxt.uplink_seid = vsi->uplink_seid; 11268 ctxt.info = vsi->info; 11269 i40e_get_cap(hw); 11270 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map); 11271 if (ret) 11272 goto out; 11273 11274 /* Update the VSI after updating the VSI queue-mapping information */ 11275 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 11276 if (ret) { 11277 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d", 11278 hw->aq.asq_last_status); 11279 goto out; 11280 } 11281 /* update the local VSI info with updated queue map */ 11282 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping, 11283 sizeof(vsi->info.tc_mapping)); 11284 rte_memcpy(&vsi->info.queue_mapping, 11285 &ctxt.info.queue_mapping, 11286 sizeof(vsi->info.queue_mapping)); 11287 vsi->info.mapping_flags = ctxt.info.mapping_flags; 11288 vsi->info.valid_sections = 0; 11289 11290 /* query and update current VSI BW information */ 11291 ret = i40e_vsi_get_bw_config(vsi); 11292 if (ret) { 11293 PMD_INIT_LOG(ERR, 11294 "Failed updating vsi bw info, err %s aq_err %s", 11295 i40e_stat_str(hw, ret), 11296 i40e_aq_str(hw, hw->aq.asq_last_status)); 11297 goto out; 11298 } 11299 11300 vsi->enabled_tc = tc_map; 11301 11302 out: 11303 return ret; 11304 } 11305 11306 /* 11307 * i40e_dcb_hw_configure - program the dcb setting to hw 11308 * @pf: pf the configuration is taken on 11309 * @new_cfg: new configuration 11310 * @tc_map: enabled TC bitmap 11311 * 11312 * Returns 0 on success, negative value on failure 11313 */ 11314 static enum i40e_status_code 11315 i40e_dcb_hw_configure(struct i40e_pf *pf, 11316 struct i40e_dcbx_config *new_cfg, 11317 uint8_t tc_map) 11318 { 11319 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 11320 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config; 11321 struct i40e_vsi *main_vsi = pf->main_vsi; 11322 struct i40e_vsi_list *vsi_list; 11323 enum i40e_status_code ret; 11324 int i; 11325 uint32_t val; 11326 11327 /* Use the FW API if FW > v4.4*/ 11328 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) || 11329 (hw->aq.fw_maj_ver >= 5))) { 11330 PMD_INIT_LOG(ERR, 11331 "FW < v4.4, can not use FW LLDP API to configure DCB"); 11332 return I40E_ERR_FIRMWARE_API_VERSION; 11333 } 11334 11335 /* Check if need reconfiguration */ 11336 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) { 11337 PMD_INIT_LOG(ERR, "No Change in DCB Config required."); 11338 return I40E_SUCCESS; 11339 } 11340 11341 /* Copy the new config to the current config */ 11342 *old_cfg = *new_cfg; 11343 old_cfg->etsrec = old_cfg->etscfg; 11344 ret = i40e_set_dcb_config(hw); 11345 if (ret) { 11346 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s", 11347 i40e_stat_str(hw, ret), 11348 i40e_aq_str(hw, hw->aq.asq_last_status)); 11349 return ret; 11350 } 11351 /* set receive Arbiter to RR mode and ETS scheme by default */ 11352 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) { 11353 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i)); 11354 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK | 11355 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK | 11356 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT); 11357 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] << 11358 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) & 11359 I40E_PRTDCB_RETSTCC_BWSHARE_MASK; 11360 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) & 11361 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK; 11362 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) & 11363 I40E_PRTDCB_RETSTCC_ETSTC_MASK; 11364 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val); 11365 } 11366 /* get local mib to check whether it is configured correctly */ 11367 /* IEEE mode */ 11368 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE; 11369 /* Get Local DCB Config */ 11370 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0, 11371 &hw->local_dcbx_config); 11372 11373 /* if Veb is created, need to update TC of it at first */ 11374 if (main_vsi->veb) { 11375 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map); 11376 if (ret) 11377 PMD_INIT_LOG(WARNING, 11378 "Failed configuring TC for VEB seid=%d", 11379 main_vsi->veb->seid); 11380 } 11381 /* Update each VSI */ 11382 i40e_vsi_config_tc(main_vsi, tc_map); 11383 if (main_vsi->veb) { 11384 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) { 11385 /* Beside main VSI and VMDQ VSIs, only enable default 11386 * TC for other VSIs 11387 */ 11388 if (vsi_list->vsi->type == I40E_VSI_VMDQ2) 11389 ret = i40e_vsi_config_tc(vsi_list->vsi, 11390 tc_map); 11391 else 11392 ret = i40e_vsi_config_tc(vsi_list->vsi, 11393 I40E_DEFAULT_TCMAP); 11394 if (ret) 11395 PMD_INIT_LOG(WARNING, 11396 "Failed configuring TC for VSI seid=%d", 11397 vsi_list->vsi->seid); 11398 /* continue */ 11399 } 11400 } 11401 return I40E_SUCCESS; 11402 } 11403 11404 /* 11405 * i40e_dcb_init_configure - initial dcb config 11406 * @dev: device being configured 11407 * @sw_dcb: indicate whether dcb is sw configured or hw offload 11408 * 11409 * Returns 0 on success, negative value on failure 11410 */ 11411 int 11412 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb) 11413 { 11414 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11415 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11416 int i, ret = 0; 11417 11418 if ((pf->flags & I40E_FLAG_DCB) == 0) { 11419 PMD_INIT_LOG(ERR, "HW doesn't support DCB"); 11420 return -ENOTSUP; 11421 } 11422 11423 /* DCB initialization: 11424 * Update DCB configuration from the Firmware and configure 11425 * LLDP MIB change event. 11426 */ 11427 if (sw_dcb == TRUE) { 11428 /* When using NVM 6.01 or later, the RX data path does 11429 * not hang if the FW LLDP is stopped. 11430 */ 11431 if (((hw->nvm.version >> 12) & 0xf) >= 6 && 11432 ((hw->nvm.version >> 4) & 0xff) >= 1) { 11433 ret = i40e_aq_stop_lldp(hw, TRUE, NULL); 11434 if (ret != I40E_SUCCESS) 11435 PMD_INIT_LOG(DEBUG, "Failed to stop lldp"); 11436 } 11437 11438 ret = i40e_init_dcb(hw); 11439 /* If lldp agent is stopped, the return value from 11440 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM 11441 * adminq status. Otherwise, it should return success. 11442 */ 11443 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS && 11444 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) { 11445 memset(&hw->local_dcbx_config, 0, 11446 sizeof(struct i40e_dcbx_config)); 11447 /* set dcb default configuration */ 11448 hw->local_dcbx_config.etscfg.willing = 0; 11449 hw->local_dcbx_config.etscfg.maxtcs = 0; 11450 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100; 11451 hw->local_dcbx_config.etscfg.tsatable[0] = 11452 I40E_IEEE_TSA_ETS; 11453 /* all UPs mapping to TC0 */ 11454 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11455 hw->local_dcbx_config.etscfg.prioritytable[i] = 0; 11456 hw->local_dcbx_config.etsrec = 11457 hw->local_dcbx_config.etscfg; 11458 hw->local_dcbx_config.pfc.willing = 0; 11459 hw->local_dcbx_config.pfc.pfccap = 11460 I40E_MAX_TRAFFIC_CLASS; 11461 /* FW needs one App to configure HW */ 11462 hw->local_dcbx_config.numapps = 1; 11463 hw->local_dcbx_config.app[0].selector = 11464 I40E_APP_SEL_ETHTYPE; 11465 hw->local_dcbx_config.app[0].priority = 3; 11466 hw->local_dcbx_config.app[0].protocolid = 11467 I40E_APP_PROTOID_FCOE; 11468 ret = i40e_set_dcb_config(hw); 11469 if (ret) { 11470 PMD_INIT_LOG(ERR, 11471 "default dcb config fails. err = %d, aq_err = %d.", 11472 ret, hw->aq.asq_last_status); 11473 return -ENOSYS; 11474 } 11475 } else { 11476 PMD_INIT_LOG(ERR, 11477 "DCB initialization in FW fails, err = %d, aq_err = %d.", 11478 ret, hw->aq.asq_last_status); 11479 return -ENOTSUP; 11480 } 11481 } else { 11482 ret = i40e_aq_start_lldp(hw, NULL); 11483 if (ret != I40E_SUCCESS) 11484 PMD_INIT_LOG(DEBUG, "Failed to start lldp"); 11485 11486 ret = i40e_init_dcb(hw); 11487 if (!ret) { 11488 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) { 11489 PMD_INIT_LOG(ERR, 11490 "HW doesn't support DCBX offload."); 11491 return -ENOTSUP; 11492 } 11493 } else { 11494 PMD_INIT_LOG(ERR, 11495 "DCBX configuration failed, err = %d, aq_err = %d.", 11496 ret, hw->aq.asq_last_status); 11497 return -ENOTSUP; 11498 } 11499 } 11500 return 0; 11501 } 11502 11503 /* 11504 * i40e_dcb_setup - setup dcb related config 11505 * @dev: device being configured 11506 * 11507 * Returns 0 on success, negative value on failure 11508 */ 11509 static int 11510 i40e_dcb_setup(struct rte_eth_dev *dev) 11511 { 11512 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11513 struct i40e_dcbx_config dcb_cfg; 11514 uint8_t tc_map = 0; 11515 int ret = 0; 11516 11517 if ((pf->flags & I40E_FLAG_DCB) == 0) { 11518 PMD_INIT_LOG(ERR, "HW doesn't support DCB"); 11519 return -ENOTSUP; 11520 } 11521 11522 if (pf->vf_num != 0) 11523 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis."); 11524 11525 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map); 11526 if (ret) { 11527 PMD_INIT_LOG(ERR, "invalid dcb config"); 11528 return -EINVAL; 11529 } 11530 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map); 11531 if (ret) { 11532 PMD_INIT_LOG(ERR, "dcb sw configure fails"); 11533 return -ENOSYS; 11534 } 11535 11536 return 0; 11537 } 11538 11539 static int 11540 i40e_dev_get_dcb_info(struct rte_eth_dev *dev, 11541 struct rte_eth_dcb_info *dcb_info) 11542 { 11543 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11544 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11545 struct i40e_vsi *vsi = pf->main_vsi; 11546 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config; 11547 uint16_t bsf, tc_mapping; 11548 int i, j = 0; 11549 11550 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 11551 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1); 11552 else 11553 dcb_info->nb_tcs = 1; 11554 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11555 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i]; 11556 for (i = 0; i < dcb_info->nb_tcs; i++) 11557 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i]; 11558 11559 /* get queue mapping if vmdq is disabled */ 11560 if (!pf->nb_cfg_vmdq_vsi) { 11561 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11562 if (!(vsi->enabled_tc & (1 << i))) 11563 continue; 11564 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]); 11565 dcb_info->tc_queue.tc_rxq[j][i].base = 11566 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >> 11567 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT; 11568 dcb_info->tc_queue.tc_txq[j][i].base = 11569 dcb_info->tc_queue.tc_rxq[j][i].base; 11570 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >> 11571 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT; 11572 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf; 11573 dcb_info->tc_queue.tc_txq[j][i].nb_queue = 11574 dcb_info->tc_queue.tc_rxq[j][i].nb_queue; 11575 } 11576 return 0; 11577 } 11578 11579 /* get queue mapping if vmdq is enabled */ 11580 do { 11581 vsi = pf->vmdq[j].vsi; 11582 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11583 if (!(vsi->enabled_tc & (1 << i))) 11584 continue; 11585 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]); 11586 dcb_info->tc_queue.tc_rxq[j][i].base = 11587 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >> 11588 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT; 11589 dcb_info->tc_queue.tc_txq[j][i].base = 11590 dcb_info->tc_queue.tc_rxq[j][i].base; 11591 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >> 11592 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT; 11593 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf; 11594 dcb_info->tc_queue.tc_txq[j][i].nb_queue = 11595 dcb_info->tc_queue.tc_rxq[j][i].nb_queue; 11596 } 11597 j++; 11598 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL)); 11599 return 0; 11600 } 11601 11602 static int 11603 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 11604 { 11605 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 11606 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 11607 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11608 uint16_t msix_intr; 11609 11610 msix_intr = intr_handle->intr_vec[queue_id]; 11611 if (msix_intr == I40E_MISC_VEC_ID) 11612 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 11613 I40E_PFINT_DYN_CTL0_INTENA_MASK | 11614 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 11615 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 11616 else 11617 I40E_WRITE_REG(hw, 11618 I40E_PFINT_DYN_CTLN(msix_intr - 11619 I40E_RX_VEC_START), 11620 I40E_PFINT_DYN_CTLN_INTENA_MASK | 11621 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 11622 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 11623 11624 I40E_WRITE_FLUSH(hw); 11625 rte_intr_enable(&pci_dev->intr_handle); 11626 11627 return 0; 11628 } 11629 11630 static int 11631 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 11632 { 11633 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 11634 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 11635 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11636 uint16_t msix_intr; 11637 11638 msix_intr = intr_handle->intr_vec[queue_id]; 11639 if (msix_intr == I40E_MISC_VEC_ID) 11640 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 11641 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 11642 else 11643 I40E_WRITE_REG(hw, 11644 I40E_PFINT_DYN_CTLN(msix_intr - 11645 I40E_RX_VEC_START), 11646 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 11647 I40E_WRITE_FLUSH(hw); 11648 11649 return 0; 11650 } 11651 11652 /** 11653 * This function is used to check if the register is valid. 11654 * Below is the valid registers list for X722 only: 11655 * 0x2b800--0x2bb00 11656 * 0x38700--0x38a00 11657 * 0x3d800--0x3db00 11658 * 0x208e00--0x209000 11659 * 0x20be00--0x20c000 11660 * 0x263c00--0x264000 11661 * 0x265c00--0x266000 11662 */ 11663 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset) 11664 { 11665 if ((type != I40E_MAC_X722) && 11666 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) || 11667 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) || 11668 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) || 11669 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) || 11670 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) || 11671 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) || 11672 (reg_offset >= 0x265c00 && reg_offset <= 0x266000))) 11673 return 0; 11674 else 11675 return 1; 11676 } 11677 11678 static int i40e_get_regs(struct rte_eth_dev *dev, 11679 struct rte_dev_reg_info *regs) 11680 { 11681 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11682 uint32_t *ptr_data = regs->data; 11683 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset; 11684 const struct i40e_reg_info *reg_info; 11685 11686 if (ptr_data == NULL) { 11687 regs->length = I40E_GLGEN_STAT_CLEAR + 4; 11688 regs->width = sizeof(uint32_t); 11689 return 0; 11690 } 11691 11692 /* The first few registers have to be read using AQ operations */ 11693 reg_idx = 0; 11694 while (i40e_regs_adminq[reg_idx].name) { 11695 reg_info = &i40e_regs_adminq[reg_idx++]; 11696 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++) 11697 for (arr_idx2 = 0; 11698 arr_idx2 <= reg_info->count2; 11699 arr_idx2++) { 11700 reg_offset = arr_idx * reg_info->stride1 + 11701 arr_idx2 * reg_info->stride2; 11702 reg_offset += reg_info->base_addr; 11703 ptr_data[reg_offset >> 2] = 11704 i40e_read_rx_ctl(hw, reg_offset); 11705 } 11706 } 11707 11708 /* The remaining registers can be read using primitives */ 11709 reg_idx = 0; 11710 while (i40e_regs_others[reg_idx].name) { 11711 reg_info = &i40e_regs_others[reg_idx++]; 11712 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++) 11713 for (arr_idx2 = 0; 11714 arr_idx2 <= reg_info->count2; 11715 arr_idx2++) { 11716 reg_offset = arr_idx * reg_info->stride1 + 11717 arr_idx2 * reg_info->stride2; 11718 reg_offset += reg_info->base_addr; 11719 if (!i40e_valid_regs(hw->mac.type, reg_offset)) 11720 ptr_data[reg_offset >> 2] = 0; 11721 else 11722 ptr_data[reg_offset >> 2] = 11723 I40E_READ_REG(hw, reg_offset); 11724 } 11725 } 11726 11727 return 0; 11728 } 11729 11730 static int i40e_get_eeprom_length(struct rte_eth_dev *dev) 11731 { 11732 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11733 11734 /* Convert word count to byte count */ 11735 return hw->nvm.sr_size << 1; 11736 } 11737 11738 static int i40e_get_eeprom(struct rte_eth_dev *dev, 11739 struct rte_dev_eeprom_info *eeprom) 11740 { 11741 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11742 uint16_t *data = eeprom->data; 11743 uint16_t offset, length, cnt_words; 11744 int ret_code; 11745 11746 offset = eeprom->offset >> 1; 11747 length = eeprom->length >> 1; 11748 cnt_words = length; 11749 11750 if (offset > hw->nvm.sr_size || 11751 offset + length > hw->nvm.sr_size) { 11752 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 11753 return -EINVAL; 11754 } 11755 11756 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 11757 11758 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data); 11759 if (ret_code != I40E_SUCCESS || cnt_words != length) { 11760 PMD_DRV_LOG(ERR, "EEPROM read failed."); 11761 return -EIO; 11762 } 11763 11764 return 0; 11765 } 11766 11767 static int i40e_get_module_info(struct rte_eth_dev *dev, 11768 struct rte_eth_dev_module_info *modinfo) 11769 { 11770 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11771 uint32_t sff8472_comp = 0; 11772 uint32_t sff8472_swap = 0; 11773 uint32_t sff8636_rev = 0; 11774 i40e_status status; 11775 uint32_t type = 0; 11776 11777 /* Check if firmware supports reading module EEPROM. */ 11778 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) { 11779 PMD_DRV_LOG(ERR, 11780 "Module EEPROM memory read not supported. " 11781 "Please update the NVM image.\n"); 11782 return -EINVAL; 11783 } 11784 11785 status = i40e_update_link_info(hw); 11786 if (status) 11787 return -EIO; 11788 11789 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) { 11790 PMD_DRV_LOG(ERR, 11791 "Cannot read module EEPROM memory. " 11792 "No module connected.\n"); 11793 return -EINVAL; 11794 } 11795 11796 type = hw->phy.link_info.module_type[0]; 11797 11798 switch (type) { 11799 case I40E_MODULE_TYPE_SFP: 11800 status = i40e_aq_get_phy_register(hw, 11801 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11802 I40E_I2C_EEPROM_DEV_ADDR, 1, 11803 I40E_MODULE_SFF_8472_COMP, 11804 &sff8472_comp, NULL); 11805 if (status) 11806 return -EIO; 11807 11808 status = i40e_aq_get_phy_register(hw, 11809 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11810 I40E_I2C_EEPROM_DEV_ADDR, 1, 11811 I40E_MODULE_SFF_8472_SWAP, 11812 &sff8472_swap, NULL); 11813 if (status) 11814 return -EIO; 11815 11816 /* Check if the module requires address swap to access 11817 * the other EEPROM memory page. 11818 */ 11819 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) { 11820 PMD_DRV_LOG(WARNING, 11821 "Module address swap to access " 11822 "page 0xA2 is not supported.\n"); 11823 modinfo->type = RTE_ETH_MODULE_SFF_8079; 11824 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 11825 } else if (sff8472_comp == 0x00) { 11826 /* Module is not SFF-8472 compliant */ 11827 modinfo->type = RTE_ETH_MODULE_SFF_8079; 11828 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 11829 } else { 11830 modinfo->type = RTE_ETH_MODULE_SFF_8472; 11831 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 11832 } 11833 break; 11834 case I40E_MODULE_TYPE_QSFP_PLUS: 11835 /* Read from memory page 0. */ 11836 status = i40e_aq_get_phy_register(hw, 11837 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11838 0, 1, 11839 I40E_MODULE_REVISION_ADDR, 11840 &sff8636_rev, NULL); 11841 if (status) 11842 return -EIO; 11843 /* Determine revision compliance byte */ 11844 if (sff8636_rev > 0x02) { 11845 /* Module is SFF-8636 compliant */ 11846 modinfo->type = RTE_ETH_MODULE_SFF_8636; 11847 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11848 } else { 11849 modinfo->type = RTE_ETH_MODULE_SFF_8436; 11850 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11851 } 11852 break; 11853 case I40E_MODULE_TYPE_QSFP28: 11854 modinfo->type = RTE_ETH_MODULE_SFF_8636; 11855 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11856 break; 11857 default: 11858 PMD_DRV_LOG(ERR, "Module type unrecognized\n"); 11859 return -EINVAL; 11860 } 11861 return 0; 11862 } 11863 11864 static int i40e_get_module_eeprom(struct rte_eth_dev *dev, 11865 struct rte_dev_eeprom_info *info) 11866 { 11867 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11868 bool is_sfp = false; 11869 i40e_status status; 11870 uint8_t *data = info->data; 11871 uint32_t value = 0; 11872 uint32_t i; 11873 11874 if (!info || !info->length || !data) 11875 return -EINVAL; 11876 11877 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP) 11878 is_sfp = true; 11879 11880 for (i = 0; i < info->length; i++) { 11881 u32 offset = i + info->offset; 11882 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0; 11883 11884 /* Check if we need to access the other memory page */ 11885 if (is_sfp) { 11886 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) { 11887 offset -= RTE_ETH_MODULE_SFF_8079_LEN; 11888 addr = I40E_I2C_EEPROM_DEV_ADDR2; 11889 } 11890 } else { 11891 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) { 11892 /* Compute memory page number and offset. */ 11893 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2; 11894 addr++; 11895 } 11896 } 11897 status = i40e_aq_get_phy_register(hw, 11898 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11899 addr, offset, 1, &value, NULL); 11900 if (status) 11901 return -EIO; 11902 data[i] = (uint8_t)value; 11903 } 11904 return 0; 11905 } 11906 11907 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, 11908 struct ether_addr *mac_addr) 11909 { 11910 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11912 struct i40e_vsi *vsi = pf->main_vsi; 11913 struct i40e_mac_filter_info mac_filter; 11914 struct i40e_mac_filter *f; 11915 int ret; 11916 11917 if (!is_valid_assigned_ether_addr(mac_addr)) { 11918 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 11919 return -EINVAL; 11920 } 11921 11922 TAILQ_FOREACH(f, &vsi->mac_list, next) { 11923 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 11924 break; 11925 } 11926 11927 if (f == NULL) { 11928 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 11929 return -EIO; 11930 } 11931 11932 mac_filter = f->mac_info; 11933 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr); 11934 if (ret != I40E_SUCCESS) { 11935 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 11936 return -EIO; 11937 } 11938 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN); 11939 ret = i40e_vsi_add_mac(vsi, &mac_filter); 11940 if (ret != I40E_SUCCESS) { 11941 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 11942 return -EIO; 11943 } 11944 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN); 11945 11946 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL, 11947 mac_addr->addr_bytes, NULL); 11948 if (ret != I40E_SUCCESS) { 11949 PMD_DRV_LOG(ERR, "Failed to change mac"); 11950 return -EIO; 11951 } 11952 11953 return 0; 11954 } 11955 11956 static int 11957 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 11958 { 11959 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11960 struct rte_eth_dev_data *dev_data = pf->dev_data; 11961 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD; 11962 int ret = 0; 11963 11964 /* check if mtu is within the allowed range */ 11965 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX)) 11966 return -EINVAL; 11967 11968 /* mtu setting is forbidden if port is start */ 11969 if (dev_data->dev_started) { 11970 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 11971 dev_data->port_id); 11972 return -EBUSY; 11973 } 11974 11975 if (frame_size > ETHER_MAX_LEN) 11976 dev_data->dev_conf.rxmode.offloads |= 11977 DEV_RX_OFFLOAD_JUMBO_FRAME; 11978 else 11979 dev_data->dev_conf.rxmode.offloads &= 11980 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 11981 11982 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 11983 11984 return ret; 11985 } 11986 11987 /* Restore ethertype filter */ 11988 static void 11989 i40e_ethertype_filter_restore(struct i40e_pf *pf) 11990 { 11991 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 11992 struct i40e_ethertype_filter_list 11993 *ethertype_list = &pf->ethertype.ethertype_list; 11994 struct i40e_ethertype_filter *f; 11995 struct i40e_control_filter_stats stats; 11996 uint16_t flags; 11997 11998 TAILQ_FOREACH(f, ethertype_list, rules) { 11999 flags = 0; 12000 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC)) 12001 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 12002 if (f->flags & RTE_ETHTYPE_FLAGS_DROP) 12003 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 12004 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 12005 12006 memset(&stats, 0, sizeof(stats)); 12007 i40e_aq_add_rem_control_packet_filter(hw, 12008 f->input.mac_addr.addr_bytes, 12009 f->input.ether_type, 12010 flags, pf->main_vsi->seid, 12011 f->queue, 1, &stats, NULL); 12012 } 12013 PMD_DRV_LOG(INFO, "Ethertype filter:" 12014 " mac_etype_used = %u, etype_used = %u," 12015 " mac_etype_free = %u, etype_free = %u", 12016 stats.mac_etype_used, stats.etype_used, 12017 stats.mac_etype_free, stats.etype_free); 12018 } 12019 12020 /* Restore tunnel filter */ 12021 static void 12022 i40e_tunnel_filter_restore(struct i40e_pf *pf) 12023 { 12024 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12025 struct i40e_vsi *vsi; 12026 struct i40e_pf_vf *vf; 12027 struct i40e_tunnel_filter_list 12028 *tunnel_list = &pf->tunnel.tunnel_list; 12029 struct i40e_tunnel_filter *f; 12030 struct i40e_aqc_cloud_filters_element_bb cld_filter; 12031 bool big_buffer = 0; 12032 12033 TAILQ_FOREACH(f, tunnel_list, rules) { 12034 if (!f->is_to_vf) 12035 vsi = pf->main_vsi; 12036 else { 12037 vf = &pf->vfs[f->vf_id]; 12038 vsi = vf->vsi; 12039 } 12040 memset(&cld_filter, 0, sizeof(cld_filter)); 12041 ether_addr_copy((struct ether_addr *)&f->input.outer_mac, 12042 (struct ether_addr *)&cld_filter.element.outer_mac); 12043 ether_addr_copy((struct ether_addr *)&f->input.inner_mac, 12044 (struct ether_addr *)&cld_filter.element.inner_mac); 12045 cld_filter.element.inner_vlan = f->input.inner_vlan; 12046 cld_filter.element.flags = f->input.flags; 12047 cld_filter.element.tenant_id = f->input.tenant_id; 12048 cld_filter.element.queue_number = f->queue; 12049 rte_memcpy(cld_filter.general_fields, 12050 f->input.general_fields, 12051 sizeof(f->input.general_fields)); 12052 12053 if (((f->input.flags & 12054 I40E_AQC_ADD_CLOUD_FILTER_0X11) == 12055 I40E_AQC_ADD_CLOUD_FILTER_0X11) || 12056 ((f->input.flags & 12057 I40E_AQC_ADD_CLOUD_FILTER_0X12) == 12058 I40E_AQC_ADD_CLOUD_FILTER_0X12) || 12059 ((f->input.flags & 12060 I40E_AQC_ADD_CLOUD_FILTER_0X10) == 12061 I40E_AQC_ADD_CLOUD_FILTER_0X10)) 12062 big_buffer = 1; 12063 12064 if (big_buffer) 12065 i40e_aq_add_cloud_filters_bb(hw, 12066 vsi->seid, &cld_filter, 1); 12067 else 12068 i40e_aq_add_cloud_filters(hw, vsi->seid, 12069 &cld_filter.element, 1); 12070 } 12071 } 12072 12073 /* Restore rss filter */ 12074 static inline void 12075 i40e_rss_filter_restore(struct i40e_pf *pf) 12076 { 12077 struct i40e_rte_flow_rss_conf *conf = 12078 &pf->rss_info; 12079 if (conf->conf.queue_num) 12080 i40e_config_rss_filter(pf, conf, TRUE); 12081 } 12082 12083 static void 12084 i40e_filter_restore(struct i40e_pf *pf) 12085 { 12086 i40e_ethertype_filter_restore(pf); 12087 i40e_tunnel_filter_restore(pf); 12088 i40e_fdir_filter_restore(pf); 12089 i40e_rss_filter_restore(pf); 12090 } 12091 12092 static bool 12093 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 12094 { 12095 if (strcmp(dev->device->driver->name, drv->driver.name)) 12096 return false; 12097 12098 return true; 12099 } 12100 12101 bool 12102 is_i40e_supported(struct rte_eth_dev *dev) 12103 { 12104 return is_device_supported(dev, &rte_i40e_pmd); 12105 } 12106 12107 struct i40e_customized_pctype* 12108 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index) 12109 { 12110 int i; 12111 12112 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) { 12113 if (pf->customized_pctype[i].index == index) 12114 return &pf->customized_pctype[i]; 12115 } 12116 return NULL; 12117 } 12118 12119 static int 12120 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg, 12121 uint32_t pkg_size, uint32_t proto_num, 12122 struct rte_pmd_i40e_proto_info *proto, 12123 enum rte_pmd_i40e_package_op op) 12124 { 12125 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12126 uint32_t pctype_num; 12127 struct rte_pmd_i40e_ptype_info *pctype; 12128 uint32_t buff_size; 12129 struct i40e_customized_pctype *new_pctype = NULL; 12130 uint8_t proto_id; 12131 uint8_t pctype_value; 12132 char name[64]; 12133 uint32_t i, j, n; 12134 int ret; 12135 12136 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12137 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12138 PMD_DRV_LOG(ERR, "Unsupported operation."); 12139 return -1; 12140 } 12141 12142 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12143 (uint8_t *)&pctype_num, sizeof(pctype_num), 12144 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM); 12145 if (ret) { 12146 PMD_DRV_LOG(ERR, "Failed to get pctype number"); 12147 return -1; 12148 } 12149 if (!pctype_num) { 12150 PMD_DRV_LOG(INFO, "No new pctype added"); 12151 return -1; 12152 } 12153 12154 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info); 12155 pctype = rte_zmalloc("new_pctype", buff_size, 0); 12156 if (!pctype) { 12157 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12158 return -1; 12159 } 12160 /* get information about new pctype list */ 12161 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12162 (uint8_t *)pctype, buff_size, 12163 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST); 12164 if (ret) { 12165 PMD_DRV_LOG(ERR, "Failed to get pctype list"); 12166 rte_free(pctype); 12167 return -1; 12168 } 12169 12170 /* Update customized pctype. */ 12171 for (i = 0; i < pctype_num; i++) { 12172 pctype_value = pctype[i].ptype_id; 12173 memset(name, 0, sizeof(name)); 12174 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) { 12175 proto_id = pctype[i].protocols[j]; 12176 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED) 12177 continue; 12178 for (n = 0; n < proto_num; n++) { 12179 if (proto[n].proto_id != proto_id) 12180 continue; 12181 strcat(name, proto[n].name); 12182 strcat(name, "_"); 12183 break; 12184 } 12185 } 12186 name[strlen(name) - 1] = '\0'; 12187 if (!strcmp(name, "GTPC")) 12188 new_pctype = 12189 i40e_find_customized_pctype(pf, 12190 I40E_CUSTOMIZED_GTPC); 12191 else if (!strcmp(name, "GTPU_IPV4")) 12192 new_pctype = 12193 i40e_find_customized_pctype(pf, 12194 I40E_CUSTOMIZED_GTPU_IPV4); 12195 else if (!strcmp(name, "GTPU_IPV6")) 12196 new_pctype = 12197 i40e_find_customized_pctype(pf, 12198 I40E_CUSTOMIZED_GTPU_IPV6); 12199 else if (!strcmp(name, "GTPU")) 12200 new_pctype = 12201 i40e_find_customized_pctype(pf, 12202 I40E_CUSTOMIZED_GTPU); 12203 if (new_pctype) { 12204 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) { 12205 new_pctype->pctype = pctype_value; 12206 new_pctype->valid = true; 12207 } else { 12208 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID; 12209 new_pctype->valid = false; 12210 } 12211 } 12212 } 12213 12214 rte_free(pctype); 12215 return 0; 12216 } 12217 12218 static int 12219 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg, 12220 uint32_t pkg_size, uint32_t proto_num, 12221 struct rte_pmd_i40e_proto_info *proto, 12222 enum rte_pmd_i40e_package_op op) 12223 { 12224 struct rte_pmd_i40e_ptype_mapping *ptype_mapping; 12225 uint16_t port_id = dev->data->port_id; 12226 uint32_t ptype_num; 12227 struct rte_pmd_i40e_ptype_info *ptype; 12228 uint32_t buff_size; 12229 uint8_t proto_id; 12230 char name[RTE_PMD_I40E_DDP_NAME_SIZE]; 12231 uint32_t i, j, n; 12232 bool in_tunnel; 12233 int ret; 12234 12235 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12236 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12237 PMD_DRV_LOG(ERR, "Unsupported operation."); 12238 return -1; 12239 } 12240 12241 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) { 12242 rte_pmd_i40e_ptype_mapping_reset(port_id); 12243 return 0; 12244 } 12245 12246 /* get information about new ptype num */ 12247 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12248 (uint8_t *)&ptype_num, sizeof(ptype_num), 12249 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM); 12250 if (ret) { 12251 PMD_DRV_LOG(ERR, "Failed to get ptype number"); 12252 return ret; 12253 } 12254 if (!ptype_num) { 12255 PMD_DRV_LOG(INFO, "No new ptype added"); 12256 return -1; 12257 } 12258 12259 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info); 12260 ptype = rte_zmalloc("new_ptype", buff_size, 0); 12261 if (!ptype) { 12262 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12263 return -1; 12264 } 12265 12266 /* get information about new ptype list */ 12267 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12268 (uint8_t *)ptype, buff_size, 12269 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST); 12270 if (ret) { 12271 PMD_DRV_LOG(ERR, "Failed to get ptype list"); 12272 rte_free(ptype); 12273 return ret; 12274 } 12275 12276 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping); 12277 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0); 12278 if (!ptype_mapping) { 12279 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12280 rte_free(ptype); 12281 return -1; 12282 } 12283 12284 /* Update ptype mapping table. */ 12285 for (i = 0; i < ptype_num; i++) { 12286 ptype_mapping[i].hw_ptype = ptype[i].ptype_id; 12287 ptype_mapping[i].sw_ptype = 0; 12288 in_tunnel = false; 12289 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) { 12290 proto_id = ptype[i].protocols[j]; 12291 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED) 12292 continue; 12293 for (n = 0; n < proto_num; n++) { 12294 if (proto[n].proto_id != proto_id) 12295 continue; 12296 memset(name, 0, sizeof(name)); 12297 strcpy(name, proto[n].name); 12298 if (!strncasecmp(name, "PPPOE", 5)) 12299 ptype_mapping[i].sw_ptype |= 12300 RTE_PTYPE_L2_ETHER_PPPOE; 12301 else if (!strncasecmp(name, "IPV4FRAG", 8) && 12302 !in_tunnel) { 12303 ptype_mapping[i].sw_ptype |= 12304 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12305 ptype_mapping[i].sw_ptype |= 12306 RTE_PTYPE_L4_FRAG; 12307 } else if (!strncasecmp(name, "IPV4FRAG", 8) && 12308 in_tunnel) { 12309 ptype_mapping[i].sw_ptype |= 12310 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 12311 ptype_mapping[i].sw_ptype |= 12312 RTE_PTYPE_INNER_L4_FRAG; 12313 } else if (!strncasecmp(name, "OIPV4", 5)) { 12314 ptype_mapping[i].sw_ptype |= 12315 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12316 in_tunnel = true; 12317 } else if (!strncasecmp(name, "IPV4", 4) && 12318 !in_tunnel) 12319 ptype_mapping[i].sw_ptype |= 12320 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12321 else if (!strncasecmp(name, "IPV4", 4) && 12322 in_tunnel) 12323 ptype_mapping[i].sw_ptype |= 12324 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 12325 else if (!strncasecmp(name, "IPV6FRAG", 8) && 12326 !in_tunnel) { 12327 ptype_mapping[i].sw_ptype |= 12328 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12329 ptype_mapping[i].sw_ptype |= 12330 RTE_PTYPE_L4_FRAG; 12331 } else if (!strncasecmp(name, "IPV6FRAG", 8) && 12332 in_tunnel) { 12333 ptype_mapping[i].sw_ptype |= 12334 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 12335 ptype_mapping[i].sw_ptype |= 12336 RTE_PTYPE_INNER_L4_FRAG; 12337 } else if (!strncasecmp(name, "OIPV6", 5)) { 12338 ptype_mapping[i].sw_ptype |= 12339 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12340 in_tunnel = true; 12341 } else if (!strncasecmp(name, "IPV6", 4) && 12342 !in_tunnel) 12343 ptype_mapping[i].sw_ptype |= 12344 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12345 else if (!strncasecmp(name, "IPV6", 4) && 12346 in_tunnel) 12347 ptype_mapping[i].sw_ptype |= 12348 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 12349 else if (!strncasecmp(name, "UDP", 3) && 12350 !in_tunnel) 12351 ptype_mapping[i].sw_ptype |= 12352 RTE_PTYPE_L4_UDP; 12353 else if (!strncasecmp(name, "UDP", 3) && 12354 in_tunnel) 12355 ptype_mapping[i].sw_ptype |= 12356 RTE_PTYPE_INNER_L4_UDP; 12357 else if (!strncasecmp(name, "TCP", 3) && 12358 !in_tunnel) 12359 ptype_mapping[i].sw_ptype |= 12360 RTE_PTYPE_L4_TCP; 12361 else if (!strncasecmp(name, "TCP", 3) && 12362 in_tunnel) 12363 ptype_mapping[i].sw_ptype |= 12364 RTE_PTYPE_INNER_L4_TCP; 12365 else if (!strncasecmp(name, "SCTP", 4) && 12366 !in_tunnel) 12367 ptype_mapping[i].sw_ptype |= 12368 RTE_PTYPE_L4_SCTP; 12369 else if (!strncasecmp(name, "SCTP", 4) && 12370 in_tunnel) 12371 ptype_mapping[i].sw_ptype |= 12372 RTE_PTYPE_INNER_L4_SCTP; 12373 else if ((!strncasecmp(name, "ICMP", 4) || 12374 !strncasecmp(name, "ICMPV6", 6)) && 12375 !in_tunnel) 12376 ptype_mapping[i].sw_ptype |= 12377 RTE_PTYPE_L4_ICMP; 12378 else if ((!strncasecmp(name, "ICMP", 4) || 12379 !strncasecmp(name, "ICMPV6", 6)) && 12380 in_tunnel) 12381 ptype_mapping[i].sw_ptype |= 12382 RTE_PTYPE_INNER_L4_ICMP; 12383 else if (!strncasecmp(name, "GTPC", 4)) { 12384 ptype_mapping[i].sw_ptype |= 12385 RTE_PTYPE_TUNNEL_GTPC; 12386 in_tunnel = true; 12387 } else if (!strncasecmp(name, "GTPU", 4)) { 12388 ptype_mapping[i].sw_ptype |= 12389 RTE_PTYPE_TUNNEL_GTPU; 12390 in_tunnel = true; 12391 } else if (!strncasecmp(name, "GRENAT", 6)) { 12392 ptype_mapping[i].sw_ptype |= 12393 RTE_PTYPE_TUNNEL_GRENAT; 12394 in_tunnel = true; 12395 } else if (!strncasecmp(name, "L2TPV2CTL", 9) || 12396 !strncasecmp(name, "L2TPV2", 6)) { 12397 ptype_mapping[i].sw_ptype |= 12398 RTE_PTYPE_TUNNEL_L2TP; 12399 in_tunnel = true; 12400 } 12401 12402 break; 12403 } 12404 } 12405 } 12406 12407 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping, 12408 ptype_num, 0); 12409 if (ret) 12410 PMD_DRV_LOG(ERR, "Failed to update mapping table."); 12411 12412 rte_free(ptype_mapping); 12413 rte_free(ptype); 12414 return ret; 12415 } 12416 12417 void 12418 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 12419 uint32_t pkg_size, enum rte_pmd_i40e_package_op op) 12420 { 12421 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12422 uint32_t proto_num; 12423 struct rte_pmd_i40e_proto_info *proto; 12424 uint32_t buff_size; 12425 uint32_t i; 12426 int ret; 12427 12428 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12429 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12430 PMD_DRV_LOG(ERR, "Unsupported operation."); 12431 return; 12432 } 12433 12434 /* get information about protocol number */ 12435 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12436 (uint8_t *)&proto_num, sizeof(proto_num), 12437 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM); 12438 if (ret) { 12439 PMD_DRV_LOG(ERR, "Failed to get protocol number"); 12440 return; 12441 } 12442 if (!proto_num) { 12443 PMD_DRV_LOG(INFO, "No new protocol added"); 12444 return; 12445 } 12446 12447 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info); 12448 proto = rte_zmalloc("new_proto", buff_size, 0); 12449 if (!proto) { 12450 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12451 return; 12452 } 12453 12454 /* get information about protocol list */ 12455 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12456 (uint8_t *)proto, buff_size, 12457 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST); 12458 if (ret) { 12459 PMD_DRV_LOG(ERR, "Failed to get protocol list"); 12460 rte_free(proto); 12461 return; 12462 } 12463 12464 /* Check if GTP is supported. */ 12465 for (i = 0; i < proto_num; i++) { 12466 if (!strncmp(proto[i].name, "GTP", 3)) { 12467 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) 12468 pf->gtp_support = true; 12469 else 12470 pf->gtp_support = false; 12471 break; 12472 } 12473 } 12474 12475 /* Update customized pctype info */ 12476 ret = i40e_update_customized_pctype(dev, pkg, pkg_size, 12477 proto_num, proto, op); 12478 if (ret) 12479 PMD_DRV_LOG(INFO, "No pctype is updated."); 12480 12481 /* Update customized ptype info */ 12482 ret = i40e_update_customized_ptype(dev, pkg, pkg_size, 12483 proto_num, proto, op); 12484 if (ret) 12485 PMD_DRV_LOG(INFO, "No ptype is updated."); 12486 12487 rte_free(proto); 12488 } 12489 12490 /* Create a QinQ cloud filter 12491 * 12492 * The Fortville NIC has limited resources for tunnel filters, 12493 * so we can only reuse existing filters. 12494 * 12495 * In step 1 we define which Field Vector fields can be used for 12496 * filter types. 12497 * As we do not have the inner tag defined as a field, 12498 * we have to define it first, by reusing one of L1 entries. 12499 * 12500 * In step 2 we are replacing one of existing filter types with 12501 * a new one for QinQ. 12502 * As we reusing L1 and replacing L2, some of the default filter 12503 * types will disappear,which depends on L1 and L2 entries we reuse. 12504 * 12505 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b) 12506 * 12507 * 1. Create L1 filter of outer vlan (12b) which will be in use 12508 * later when we define the cloud filter. 12509 * a. Valid_flags.replace_cloud = 0 12510 * b. Old_filter = 10 (Stag_Inner_Vlan) 12511 * c. New_filter = 0x10 12512 * d. TR bit = 0xff (optional, not used here) 12513 * e. Buffer – 2 entries: 12514 * i. Byte 0 = 8 (outer vlan FV index). 12515 * Byte 1 = 0 (rsv) 12516 * Byte 2-3 = 0x0fff 12517 * ii. Byte 0 = 37 (inner vlan FV index). 12518 * Byte 1 =0 (rsv) 12519 * Byte 2-3 = 0x0fff 12520 * 12521 * Step 2: 12522 * 2. Create cloud filter using two L1 filters entries: stag and 12523 * new filter(outer vlan+ inner vlan) 12524 * a. Valid_flags.replace_cloud = 1 12525 * b. Old_filter = 1 (instead of outer IP) 12526 * c. New_filter = 0x10 12527 * d. Buffer – 2 entries: 12528 * i. Byte 0 = 0x80 | 7 (valid | Stag). 12529 * Byte 1-3 = 0 (rsv) 12530 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1) 12531 * Byte 9-11 = 0 (rsv) 12532 */ 12533 static int 12534 i40e_cloud_filter_qinq_create(struct i40e_pf *pf) 12535 { 12536 int ret = -ENOTSUP; 12537 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 12538 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 12539 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12540 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 12541 12542 if (pf->support_multi_driver) { 12543 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 12544 return ret; 12545 } 12546 12547 /* Init */ 12548 memset(&filter_replace, 0, 12549 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 12550 memset(&filter_replace_buf, 0, 12551 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 12552 12553 /* create L1 filter */ 12554 filter_replace.old_filter_type = 12555 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN; 12556 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12557 filter_replace.tr_bit = 0; 12558 12559 /* Prepare the buffer, 2 entries */ 12560 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN; 12561 filter_replace_buf.data[0] |= 12562 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12563 /* Field Vector 12b mask */ 12564 filter_replace_buf.data[2] = 0xff; 12565 filter_replace_buf.data[3] = 0x0f; 12566 filter_replace_buf.data[4] = 12567 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN; 12568 filter_replace_buf.data[4] |= 12569 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12570 /* Field Vector 12b mask */ 12571 filter_replace_buf.data[6] = 0xff; 12572 filter_replace_buf.data[7] = 0x0f; 12573 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, 12574 &filter_replace_buf); 12575 if (ret != I40E_SUCCESS) 12576 return ret; 12577 12578 if (filter_replace.old_filter_type != 12579 filter_replace.new_filter_type) 12580 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 12581 " original: 0x%x, new: 0x%x", 12582 dev->device->name, 12583 filter_replace.old_filter_type, 12584 filter_replace.new_filter_type); 12585 12586 /* Apply the second L2 cloud filter */ 12587 memset(&filter_replace, 0, 12588 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 12589 memset(&filter_replace_buf, 0, 12590 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 12591 12592 /* create L2 filter, input for L2 filter will be L1 filter */ 12593 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 12594 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP; 12595 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12596 12597 /* Prepare the buffer, 2 entries */ 12598 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 12599 filter_replace_buf.data[0] |= 12600 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12601 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12602 filter_replace_buf.data[4] |= 12603 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12604 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, 12605 &filter_replace_buf); 12606 if (!ret && (filter_replace.old_filter_type != 12607 filter_replace.new_filter_type)) 12608 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 12609 " original: 0x%x, new: 0x%x", 12610 dev->device->name, 12611 filter_replace.old_filter_type, 12612 filter_replace.new_filter_type); 12613 12614 return ret; 12615 } 12616 12617 int 12618 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, 12619 const struct rte_flow_action_rss *in) 12620 { 12621 if (in->key_len > RTE_DIM(out->key) || 12622 in->queue_num > RTE_DIM(out->queue)) 12623 return -EINVAL; 12624 if (!in->key && in->key_len) 12625 return -EINVAL; 12626 out->conf = (struct rte_flow_action_rss){ 12627 .func = in->func, 12628 .level = in->level, 12629 .types = in->types, 12630 .key_len = in->key_len, 12631 .queue_num = in->queue_num, 12632 .queue = memcpy(out->queue, in->queue, 12633 sizeof(*in->queue) * in->queue_num), 12634 }; 12635 if (in->key) 12636 out->conf.key = memcpy(out->key, in->key, in->key_len); 12637 return 0; 12638 } 12639 12640 int 12641 i40e_action_rss_same(const struct rte_flow_action_rss *comp, 12642 const struct rte_flow_action_rss *with) 12643 { 12644 return (comp->func == with->func && 12645 comp->level == with->level && 12646 comp->types == with->types && 12647 comp->key_len == with->key_len && 12648 comp->queue_num == with->queue_num && 12649 !memcmp(comp->key, with->key, with->key_len) && 12650 !memcmp(comp->queue, with->queue, 12651 sizeof(*with->queue) * with->queue_num)); 12652 } 12653 12654 int 12655 i40e_config_rss_filter(struct i40e_pf *pf, 12656 struct i40e_rte_flow_rss_conf *conf, bool add) 12657 { 12658 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12659 uint32_t i, lut = 0; 12660 uint16_t j, num; 12661 struct rte_eth_rss_conf rss_conf = { 12662 .rss_key = conf->conf.key_len ? 12663 (void *)(uintptr_t)conf->conf.key : NULL, 12664 .rss_key_len = conf->conf.key_len, 12665 .rss_hf = conf->conf.types, 12666 }; 12667 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 12668 12669 if (!add) { 12670 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) { 12671 i40e_pf_disable_rss(pf); 12672 memset(rss_info, 0, 12673 sizeof(struct i40e_rte_flow_rss_conf)); 12674 return 0; 12675 } 12676 return -EINVAL; 12677 } 12678 12679 if (rss_info->conf.queue_num) 12680 return -EINVAL; 12681 12682 /* If both VMDQ and RSS enabled, not all of PF queues are configured. 12683 * It's necessary to calculate the actual PF queues that are configured. 12684 */ 12685 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 12686 num = i40e_pf_calc_configured_queues_num(pf); 12687 else 12688 num = pf->dev_data->nb_rx_queues; 12689 12690 num = RTE_MIN(num, conf->conf.queue_num); 12691 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured", 12692 num); 12693 12694 if (num == 0) { 12695 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS"); 12696 return -ENOTSUP; 12697 } 12698 12699 /* Fill in redirection table */ 12700 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 12701 if (j == num) 12702 j = 0; 12703 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 << 12704 hw->func_caps.rss_table_entry_width) - 1)); 12705 if ((i & 3) == 3) 12706 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut); 12707 } 12708 12709 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) { 12710 i40e_pf_disable_rss(pf); 12711 return 0; 12712 } 12713 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < 12714 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 12715 /* Random default keys */ 12716 static uint32_t rss_key_default[] = {0x6b793944, 12717 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8, 12718 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605, 12719 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581}; 12720 12721 rss_conf.rss_key = (uint8_t *)rss_key_default; 12722 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 12723 sizeof(uint32_t); 12724 } 12725 12726 i40e_hw_rss_hash_set(pf, &rss_conf); 12727 12728 if (i40e_rss_conf_init(rss_info, &conf->conf)) 12729 return -EINVAL; 12730 12731 return 0; 12732 } 12733 12734 RTE_INIT(i40e_init_log) 12735 { 12736 i40e_logtype_init = rte_log_register("pmd.net.i40e.init"); 12737 if (i40e_logtype_init >= 0) 12738 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE); 12739 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver"); 12740 if (i40e_logtype_driver >= 0) 12741 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE); 12742 } 12743 12744 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, 12745 ETH_I40E_FLOATING_VEB_ARG "=1" 12746 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>" 12747 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16" 12748 ETH_I40E_SUPPORT_MULTI_DRIVER "=1" 12749 ETH_I40E_USE_LATEST_VEC "=0|1"); 12750