1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <unistd.h> 10 #include <stdarg.h> 11 #include <inttypes.h> 12 #include <assert.h> 13 14 #include <rte_common.h> 15 #include <rte_eal.h> 16 #include <rte_string_fns.h> 17 #include <rte_pci.h> 18 #include <rte_bus_pci.h> 19 #include <rte_ether.h> 20 #include <rte_ethdev_driver.h> 21 #include <rte_ethdev_pci.h> 22 #include <rte_memzone.h> 23 #include <rte_malloc.h> 24 #include <rte_memcpy.h> 25 #include <rte_alarm.h> 26 #include <rte_dev.h> 27 #include <rte_tailq.h> 28 #include <rte_hash_crc.h> 29 30 #include "i40e_logs.h" 31 #include "base/i40e_prototype.h" 32 #include "base/i40e_adminq_cmd.h" 33 #include "base/i40e_type.h" 34 #include "base/i40e_register.h" 35 #include "base/i40e_dcb.h" 36 #include "i40e_ethdev.h" 37 #include "i40e_rxtx.h" 38 #include "i40e_pf.h" 39 #include "i40e_regs.h" 40 #include "rte_pmd_i40e.h" 41 42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" 43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" 44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" 45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" 46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" 47 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg" 48 49 #define I40E_CLEAR_PXE_WAIT_MS 200 50 51 /* Maximun number of capability elements */ 52 #define I40E_MAX_CAP_ELE_NUM 128 53 54 /* Wait count and interval */ 55 #define I40E_CHK_Q_ENA_COUNT 1000 56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000 57 58 /* Maximun number of VSI */ 59 #define I40E_MAX_NUM_VSIS (384UL) 60 61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */ 62 63 /* Flow control default timer */ 64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU 65 66 /* Flow control enable fwd bit */ 67 #define I40E_PRTMAC_FWD_CTRL 0x00000001 68 69 /* Receive Packet Buffer size */ 70 #define I40E_RXPBSIZE (968 * 1024) 71 72 /* Kilobytes shift */ 73 #define I40E_KILOSHIFT 10 74 75 /* Flow control default high water */ 76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT) 77 78 /* Flow control default low water */ 79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT) 80 81 /* Receive Average Packet Size in Byte*/ 82 #define I40E_PACKET_AVERAGE_SIZE 128 83 84 /* Mask of PF interrupt causes */ 85 #define I40E_PFINT_ICR0_ENA_MASK ( \ 86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \ 87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \ 88 I40E_PFINT_ICR0_ENA_GRST_MASK | \ 89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \ 90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \ 91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \ 92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \ 93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \ 94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK) 95 96 #define I40E_FLOW_TYPES ( \ 97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \ 98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ 99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ 100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ 101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ 102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \ 103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ 104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ 105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ 106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \ 107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD)) 108 109 /* Additional timesync values. */ 110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 113 #define I40E_PRTTSYN_TSYNENA 0x80000000 114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000 115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL 116 117 /** 118 * Below are values for writing un-exposed registers suggested 119 * by silicon experts 120 */ 121 /* Destination MAC address */ 122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL 123 /* Source MAC address */ 124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */ 126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */ 128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL 129 /* Single VLAN tag in the inner L2 header */ 130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL 131 /* Source IPv4 address */ 132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL 133 /* Destination IPv4 address */ 134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL 135 /* Source IPv4 address for X722 */ 136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL 137 /* Destination IPv4 address for X722 */ 138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL 139 /* IPv4 Protocol for X722 */ 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL 141 /* IPv4 Time to Live for X722 */ 142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL 143 /* IPv4 Type of Service (TOS) */ 144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL 145 /* IPv4 Protocol */ 146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL 147 /* IPv4 Time to Live */ 148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL 149 /* Source IPv6 address */ 150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL 151 /* Destination IPv6 address */ 152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL 153 /* IPv6 Traffic Class (TC) */ 154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL 155 /* IPv6 Next Header */ 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL 157 /* IPv6 Hop Limit */ 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL 159 /* Source L4 port */ 160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL 161 /* Destination L4 port */ 162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL 163 /* SCTP verification tag */ 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/ 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL 167 /* Source port of tunneling UDP */ 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL 169 /* Destination port of tunneling UDP */ 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL 171 /* UDP Tunneling ID, NVGRE/GRE key */ 172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL 173 /* Last ether type */ 174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL 175 /* Tunneling outer destination IPv4 address */ 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL 177 /* Tunneling outer destination IPv6 address */ 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL 179 /* 1st word of flex payload */ 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL 181 /* 2nd word of flex payload */ 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL 183 /* 3rd word of flex payload */ 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL 185 /* 4th word of flex payload */ 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL 187 /* 5th word of flex payload */ 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL 189 /* 6th word of flex payload */ 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL 191 /* 7th word of flex payload */ 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL 193 /* 8th word of flex payload */ 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL 195 /* all 8 words flex payload */ 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL 197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL 198 199 #define I40E_TRANSLATE_INSET 0 200 #define I40E_TRANSLATE_REG 1 201 202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL 203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL 204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL 205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL 208 209 /* PCI offset for querying capability */ 210 #define PCI_DEV_CAP_REG 0xA4 211 /* PCI offset for enabling/disabling Extended Tag */ 212 #define PCI_DEV_CTRL_REG 0xA8 213 /* Bit mask of Extended Tag capability */ 214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20 215 /* Bit shift of Extended Tag enable/disable */ 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 217 /* Bit mask of Extended Tag enable/disable */ 218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) 219 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); 222 static int i40e_dev_configure(struct rte_eth_dev *dev); 223 static int i40e_dev_start(struct rte_eth_dev *dev); 224 static void i40e_dev_stop(struct rte_eth_dev *dev); 225 static void i40e_dev_close(struct rte_eth_dev *dev); 226 static int i40e_dev_reset(struct rte_eth_dev *dev); 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev); 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev); 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev); 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev); 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev); 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev); 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev, 234 struct rte_eth_stats *stats); 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev, 236 struct rte_eth_xstat *xstats, unsigned n); 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev, 238 struct rte_eth_xstat_name *xstats_names, 239 unsigned limit); 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev); 241 static int i40e_fw_version_get(struct rte_eth_dev *dev, 242 char *fw_version, size_t fw_size); 243 static int i40e_dev_info_get(struct rte_eth_dev *dev, 244 struct rte_eth_dev_info *dev_info); 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev, 246 uint16_t vlan_id, 247 int on); 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev, 249 enum rte_vlan_type vlan_type, 250 uint16_t tpid); 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask); 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev, 253 uint16_t queue, 254 int on); 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on); 256 static int i40e_dev_led_on(struct rte_eth_dev *dev); 257 static int i40e_dev_led_off(struct rte_eth_dev *dev); 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev, 259 struct rte_eth_fc_conf *fc_conf); 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev, 261 struct rte_eth_fc_conf *fc_conf); 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev, 263 struct rte_eth_pfc_conf *pfc_conf); 264 static int i40e_macaddr_add(struct rte_eth_dev *dev, 265 struct rte_ether_addr *mac_addr, 266 uint32_t index, 267 uint32_t pool); 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev, 270 struct rte_eth_rss_reta_entry64 *reta_conf, 271 uint16_t reta_size); 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev, 273 struct rte_eth_rss_reta_entry64 *reta_conf, 274 uint16_t reta_size); 275 276 static int i40e_get_cap(struct i40e_hw *hw); 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev); 278 static int i40e_pf_setup(struct i40e_pf *pf); 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf); 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev); 281 static int i40e_dcb_setup(struct rte_eth_dev *dev); 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg, 283 bool offset_loaded, uint64_t *offset, uint64_t *stat); 284 static void i40e_stat_update_48(struct i40e_hw *hw, 285 uint32_t hireg, 286 uint32_t loreg, 287 bool offset_loaded, 288 uint64_t *offset, 289 uint64_t *stat); 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue); 291 static void i40e_dev_interrupt_handler(void *param); 292 static void i40e_dev_alarm_handler(void *param); 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool, 294 uint32_t base, uint32_t num); 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool); 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool, 297 uint32_t base); 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool, 299 uint16_t num); 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev); 301 static int i40e_veb_release(struct i40e_veb *veb); 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, 303 struct i40e_vsi *vsi); 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf); 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on); 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi, 307 struct i40e_macvlan_filter *mv_f, 308 int num, 309 uint16_t vlan); 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi); 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev, 312 struct rte_eth_rss_conf *rss_conf); 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 314 struct rte_eth_rss_conf *rss_conf); 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 316 struct rte_eth_udp_tunnel *udp_tunnel); 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 318 struct rte_eth_udp_tunnel *udp_tunnel); 319 static void i40e_filter_input_set_init(struct i40e_pf *pf); 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev, 321 enum rte_filter_op filter_op, 322 void *arg); 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, 324 enum rte_filter_type filter_type, 325 enum rte_filter_op filter_op, 326 void *arg); 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, 328 struct rte_eth_dcb_info *dcb_info); 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw); 330 static void i40e_configure_registers(struct i40e_hw *hw); 331 static void i40e_hw_init(struct rte_eth_dev *dev); 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw, 334 uint16_t seid, 335 uint16_t rule_type, 336 uint16_t *entries, 337 uint16_t count, 338 uint16_t rule_id); 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev, 340 struct rte_eth_mirror_conf *mirror_conf, 341 uint8_t sw_id, uint8_t on); 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id); 343 344 static int i40e_timesync_enable(struct rte_eth_dev *dev); 345 static int i40e_timesync_disable(struct rte_eth_dev *dev); 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 347 struct timespec *timestamp, 348 uint32_t flags); 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 350 struct timespec *timestamp); 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw); 352 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 354 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev, 356 struct timespec *timestamp); 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev, 358 const struct timespec *timestamp); 359 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 361 uint16_t queue_id); 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 363 uint16_t queue_id); 364 365 static int i40e_get_regs(struct rte_eth_dev *dev, 366 struct rte_dev_reg_info *regs); 367 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev); 369 370 static int i40e_get_eeprom(struct rte_eth_dev *dev, 371 struct rte_dev_eeprom_info *eeprom); 372 373 static int i40e_get_module_info(struct rte_eth_dev *dev, 374 struct rte_eth_dev_module_info *modinfo); 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev, 376 struct rte_dev_eeprom_info *info); 377 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, 379 struct rte_ether_addr *mac_addr); 380 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 382 383 static int i40e_ethertype_filter_convert( 384 const struct rte_eth_ethertype_filter *input, 385 struct i40e_ethertype_filter *filter); 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf, 387 struct i40e_ethertype_filter *filter); 388 389 static int i40e_tunnel_filter_convert( 390 struct i40e_aqc_cloud_filters_element_bb *cld_filter, 391 struct i40e_tunnel_filter *tunnel_filter); 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, 393 struct i40e_tunnel_filter *tunnel_filter); 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf); 395 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf); 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf); 398 static void i40e_filter_restore(struct i40e_pf *pf); 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev); 400 401 int i40e_logtype_init; 402 int i40e_logtype_driver; 403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX 404 int i40e_logtype_rx; 405 #endif 406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX 407 int i40e_logtype_tx; 408 #endif 409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE 410 int i40e_logtype_tx_free; 411 #endif 412 413 static const char *const valid_keys[] = { 414 ETH_I40E_FLOATING_VEB_ARG, 415 ETH_I40E_FLOATING_VEB_LIST_ARG, 416 ETH_I40E_SUPPORT_MULTI_DRIVER, 417 ETH_I40E_QUEUE_NUM_PER_VF_ARG, 418 ETH_I40E_USE_LATEST_VEC, 419 ETH_I40E_VF_MSG_CFG, 420 NULL}; 421 422 static const struct rte_pci_id pci_id_i40e_map[] = { 423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) }, 424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) }, 425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) }, 426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) }, 427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) }, 428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) }, 429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) }, 430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) }, 431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) }, 432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) }, 433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) }, 434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) }, 435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) }, 436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) }, 437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) }, 438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) }, 439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) }, 440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) }, 441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) }, 442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) }, 443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) }, 444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) }, 445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) }, 446 { .vendor_id = 0, /* sentinel */ }, 447 }; 448 449 static const struct eth_dev_ops i40e_eth_dev_ops = { 450 .dev_configure = i40e_dev_configure, 451 .dev_start = i40e_dev_start, 452 .dev_stop = i40e_dev_stop, 453 .dev_close = i40e_dev_close, 454 .dev_reset = i40e_dev_reset, 455 .promiscuous_enable = i40e_dev_promiscuous_enable, 456 .promiscuous_disable = i40e_dev_promiscuous_disable, 457 .allmulticast_enable = i40e_dev_allmulticast_enable, 458 .allmulticast_disable = i40e_dev_allmulticast_disable, 459 .dev_set_link_up = i40e_dev_set_link_up, 460 .dev_set_link_down = i40e_dev_set_link_down, 461 .link_update = i40e_dev_link_update, 462 .stats_get = i40e_dev_stats_get, 463 .xstats_get = i40e_dev_xstats_get, 464 .xstats_get_names = i40e_dev_xstats_get_names, 465 .stats_reset = i40e_dev_stats_reset, 466 .xstats_reset = i40e_dev_stats_reset, 467 .fw_version_get = i40e_fw_version_get, 468 .dev_infos_get = i40e_dev_info_get, 469 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get, 470 .vlan_filter_set = i40e_vlan_filter_set, 471 .vlan_tpid_set = i40e_vlan_tpid_set, 472 .vlan_offload_set = i40e_vlan_offload_set, 473 .vlan_strip_queue_set = i40e_vlan_strip_queue_set, 474 .vlan_pvid_set = i40e_vlan_pvid_set, 475 .rx_queue_start = i40e_dev_rx_queue_start, 476 .rx_queue_stop = i40e_dev_rx_queue_stop, 477 .tx_queue_start = i40e_dev_tx_queue_start, 478 .tx_queue_stop = i40e_dev_tx_queue_stop, 479 .rx_queue_setup = i40e_dev_rx_queue_setup, 480 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable, 481 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable, 482 .rx_queue_release = i40e_dev_rx_queue_release, 483 .rx_queue_count = i40e_dev_rx_queue_count, 484 .rx_descriptor_done = i40e_dev_rx_descriptor_done, 485 .rx_descriptor_status = i40e_dev_rx_descriptor_status, 486 .tx_descriptor_status = i40e_dev_tx_descriptor_status, 487 .tx_queue_setup = i40e_dev_tx_queue_setup, 488 .tx_queue_release = i40e_dev_tx_queue_release, 489 .dev_led_on = i40e_dev_led_on, 490 .dev_led_off = i40e_dev_led_off, 491 .flow_ctrl_get = i40e_flow_ctrl_get, 492 .flow_ctrl_set = i40e_flow_ctrl_set, 493 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set, 494 .mac_addr_add = i40e_macaddr_add, 495 .mac_addr_remove = i40e_macaddr_remove, 496 .reta_update = i40e_dev_rss_reta_update, 497 .reta_query = i40e_dev_rss_reta_query, 498 .rss_hash_update = i40e_dev_rss_hash_update, 499 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get, 500 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add, 501 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del, 502 .filter_ctrl = i40e_dev_filter_ctrl, 503 .rxq_info_get = i40e_rxq_info_get, 504 .txq_info_get = i40e_txq_info_get, 505 .mirror_rule_set = i40e_mirror_rule_set, 506 .mirror_rule_reset = i40e_mirror_rule_reset, 507 .timesync_enable = i40e_timesync_enable, 508 .timesync_disable = i40e_timesync_disable, 509 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp, 510 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp, 511 .get_dcb_info = i40e_dev_get_dcb_info, 512 .timesync_adjust_time = i40e_timesync_adjust_time, 513 .timesync_read_time = i40e_timesync_read_time, 514 .timesync_write_time = i40e_timesync_write_time, 515 .get_reg = i40e_get_regs, 516 .get_eeprom_length = i40e_get_eeprom_length, 517 .get_eeprom = i40e_get_eeprom, 518 .get_module_info = i40e_get_module_info, 519 .get_module_eeprom = i40e_get_module_eeprom, 520 .mac_addr_set = i40e_set_default_mac_addr, 521 .mtu_set = i40e_dev_mtu_set, 522 .tm_ops_get = i40e_tm_ops_get, 523 }; 524 525 /* store statistics names and its offset in stats structure */ 526 struct rte_i40e_xstats_name_off { 527 char name[RTE_ETH_XSTATS_NAME_SIZE]; 528 unsigned offset; 529 }; 530 531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = { 532 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)}, 533 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)}, 534 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)}, 535 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)}, 536 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats, 537 rx_unknown_protocol)}, 538 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)}, 539 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)}, 540 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)}, 541 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)}, 542 }; 543 544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \ 545 sizeof(rte_i40e_stats_strings[0])) 546 547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = { 548 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats, 549 tx_dropped_link_down)}, 550 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)}, 551 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats, 552 illegal_bytes)}, 553 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)}, 554 {"mac_local_errors", offsetof(struct i40e_hw_port_stats, 555 mac_local_faults)}, 556 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats, 557 mac_remote_faults)}, 558 {"rx_length_errors", offsetof(struct i40e_hw_port_stats, 559 rx_length_errors)}, 560 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)}, 561 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)}, 562 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)}, 563 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)}, 564 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)}, 565 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats, 566 rx_size_127)}, 567 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats, 568 rx_size_255)}, 569 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats, 570 rx_size_511)}, 571 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats, 572 rx_size_1023)}, 573 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats, 574 rx_size_1522)}, 575 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats, 576 rx_size_big)}, 577 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats, 578 rx_undersize)}, 579 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats, 580 rx_oversize)}, 581 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats, 582 mac_short_packet_dropped)}, 583 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats, 584 rx_fragments)}, 585 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)}, 586 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)}, 587 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats, 588 tx_size_127)}, 589 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats, 590 tx_size_255)}, 591 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats, 592 tx_size_511)}, 593 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats, 594 tx_size_1023)}, 595 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats, 596 tx_size_1522)}, 597 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats, 598 tx_size_big)}, 599 {"rx_flow_director_atr_match_packets", 600 offsetof(struct i40e_hw_port_stats, fd_atr_match)}, 601 {"rx_flow_director_sb_match_packets", 602 offsetof(struct i40e_hw_port_stats, fd_sb_match)}, 603 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats, 604 tx_lpi_status)}, 605 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats, 606 rx_lpi_status)}, 607 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats, 608 tx_lpi_count)}, 609 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats, 610 rx_lpi_count)}, 611 }; 612 613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \ 614 sizeof(rte_i40e_hw_port_strings[0])) 615 616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = { 617 {"xon_packets", offsetof(struct i40e_hw_port_stats, 618 priority_xon_rx)}, 619 {"xoff_packets", offsetof(struct i40e_hw_port_stats, 620 priority_xoff_rx)}, 621 }; 622 623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \ 624 sizeof(rte_i40e_rxq_prio_strings[0])) 625 626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = { 627 {"xon_packets", offsetof(struct i40e_hw_port_stats, 628 priority_xon_tx)}, 629 {"xoff_packets", offsetof(struct i40e_hw_port_stats, 630 priority_xoff_tx)}, 631 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats, 632 priority_xon_2_xoff)}, 633 }; 634 635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \ 636 sizeof(rte_i40e_txq_prio_strings[0])) 637 638 static int 639 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 640 struct rte_pci_device *pci_dev) 641 { 642 char name[RTE_ETH_NAME_MAX_LEN]; 643 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 644 int i, retval; 645 646 if (pci_dev->device.devargs) { 647 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 648 ð_da); 649 if (retval) 650 return retval; 651 } 652 653 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 654 sizeof(struct i40e_adapter), 655 eth_dev_pci_specific_init, pci_dev, 656 eth_i40e_dev_init, NULL); 657 658 if (retval || eth_da.nb_representor_ports < 1) 659 return retval; 660 661 /* probe VF representor ports */ 662 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated( 663 pci_dev->device.name); 664 665 if (pf_ethdev == NULL) 666 return -ENODEV; 667 668 for (i = 0; i < eth_da.nb_representor_ports; i++) { 669 struct i40e_vf_representor representor = { 670 .vf_id = eth_da.representor_ports[i], 671 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF( 672 pf_ethdev->data->dev_private)->switch_domain_id, 673 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER( 674 pf_ethdev->data->dev_private) 675 }; 676 677 /* representor port net_bdf_port */ 678 snprintf(name, sizeof(name), "net_%s_representor_%d", 679 pci_dev->device.name, eth_da.representor_ports[i]); 680 681 retval = rte_eth_dev_create(&pci_dev->device, name, 682 sizeof(struct i40e_vf_representor), NULL, NULL, 683 i40e_vf_representor_init, &representor); 684 685 if (retval) 686 PMD_DRV_LOG(ERR, "failed to create i40e vf " 687 "representor %s.", name); 688 } 689 690 return 0; 691 } 692 693 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev) 694 { 695 struct rte_eth_dev *ethdev; 696 697 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 698 if (!ethdev) 699 return -ENODEV; 700 701 702 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 703 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit); 704 else 705 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit); 706 } 707 708 static struct rte_pci_driver rte_i40e_pmd = { 709 .id_table = pci_id_i40e_map, 710 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 711 .probe = eth_i40e_pci_probe, 712 .remove = eth_i40e_pci_remove, 713 }; 714 715 static inline void 716 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr, 717 uint32_t reg_val) 718 { 719 uint32_t ori_reg_val; 720 struct rte_eth_dev *dev; 721 722 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr); 723 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 724 i40e_write_rx_ctl(hw, reg_addr, reg_val); 725 if (ori_reg_val != reg_val) 726 PMD_DRV_LOG(WARNING, 727 "i40e device %s changed global register [0x%08x]." 728 " original: 0x%08x, new: 0x%08x", 729 dev->device->name, reg_addr, ori_reg_val, reg_val); 730 } 731 732 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd); 733 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map); 734 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci"); 735 736 #ifndef I40E_GLQF_ORT 737 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) 738 #endif 739 #ifndef I40E_GLQF_PIT 740 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) 741 #endif 742 #ifndef I40E_GLQF_L3_MAP 743 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4)) 744 #endif 745 746 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) 747 { 748 /* 749 * Initialize registers for parsing packet type of QinQ 750 * This should be removed from code once proper 751 * configuration API is added to avoid configuration conflicts 752 * between ports of the same device. 753 */ 754 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029); 755 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420); 756 } 757 758 static inline void i40e_config_automask(struct i40e_pf *pf) 759 { 760 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 761 uint32_t val; 762 763 /* INTENA flag is not auto-cleared for interrupt */ 764 val = I40E_READ_REG(hw, I40E_GLINT_CTL); 765 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK | 766 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK; 767 768 /* If support multi-driver, PF will use INT0. */ 769 if (!pf->support_multi_driver) 770 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK; 771 772 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val); 773 } 774 775 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808 776 777 /* 778 * Add a ethertype filter to drop all flow control frames transmitted 779 * from VSIs. 780 */ 781 static void 782 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf) 783 { 784 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 785 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 786 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 787 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 788 int ret; 789 790 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL, 791 I40E_FLOW_CONTROL_ETHERTYPE, flags, 792 pf->main_vsi_seid, 0, 793 TRUE, NULL, NULL); 794 if (ret) 795 PMD_INIT_LOG(ERR, 796 "Failed to add filter to drop flow control frames from VSIs."); 797 } 798 799 static int 800 floating_veb_list_handler(__rte_unused const char *key, 801 const char *floating_veb_value, 802 void *opaque) 803 { 804 int idx = 0; 805 unsigned int count = 0; 806 char *end = NULL; 807 int min, max; 808 bool *vf_floating_veb = opaque; 809 810 while (isblank(*floating_veb_value)) 811 floating_veb_value++; 812 813 /* Reset floating VEB configuration for VFs */ 814 for (idx = 0; idx < I40E_MAX_VF; idx++) 815 vf_floating_veb[idx] = false; 816 817 min = I40E_MAX_VF; 818 do { 819 while (isblank(*floating_veb_value)) 820 floating_veb_value++; 821 if (*floating_veb_value == '\0') 822 return -1; 823 errno = 0; 824 idx = strtoul(floating_veb_value, &end, 10); 825 if (errno || end == NULL) 826 return -1; 827 while (isblank(*end)) 828 end++; 829 if (*end == '-') { 830 min = idx; 831 } else if ((*end == ';') || (*end == '\0')) { 832 max = idx; 833 if (min == I40E_MAX_VF) 834 min = idx; 835 if (max >= I40E_MAX_VF) 836 max = I40E_MAX_VF - 1; 837 for (idx = min; idx <= max; idx++) { 838 vf_floating_veb[idx] = true; 839 count++; 840 } 841 min = I40E_MAX_VF; 842 } else { 843 return -1; 844 } 845 floating_veb_value = end + 1; 846 } while (*end != '\0'); 847 848 if (count == 0) 849 return -1; 850 851 return 0; 852 } 853 854 static void 855 config_vf_floating_veb(struct rte_devargs *devargs, 856 uint16_t floating_veb, 857 bool *vf_floating_veb) 858 { 859 struct rte_kvargs *kvlist; 860 int i; 861 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG; 862 863 if (!floating_veb) 864 return; 865 /* All the VFs attach to the floating VEB by default 866 * when the floating VEB is enabled. 867 */ 868 for (i = 0; i < I40E_MAX_VF; i++) 869 vf_floating_veb[i] = true; 870 871 if (devargs == NULL) 872 return; 873 874 kvlist = rte_kvargs_parse(devargs->args, valid_keys); 875 if (kvlist == NULL) 876 return; 877 878 if (!rte_kvargs_count(kvlist, floating_veb_list)) { 879 rte_kvargs_free(kvlist); 880 return; 881 } 882 /* When the floating_veb_list parameter exists, all the VFs 883 * will attach to the legacy VEB firstly, then configure VFs 884 * to the floating VEB according to the floating_veb_list. 885 */ 886 if (rte_kvargs_process(kvlist, floating_veb_list, 887 floating_veb_list_handler, 888 vf_floating_veb) < 0) { 889 rte_kvargs_free(kvlist); 890 return; 891 } 892 rte_kvargs_free(kvlist); 893 } 894 895 static int 896 i40e_check_floating_handler(__rte_unused const char *key, 897 const char *value, 898 __rte_unused void *opaque) 899 { 900 if (strcmp(value, "1")) 901 return -1; 902 903 return 0; 904 } 905 906 static int 907 is_floating_veb_supported(struct rte_devargs *devargs) 908 { 909 struct rte_kvargs *kvlist; 910 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG; 911 912 if (devargs == NULL) 913 return 0; 914 915 kvlist = rte_kvargs_parse(devargs->args, valid_keys); 916 if (kvlist == NULL) 917 return 0; 918 919 if (!rte_kvargs_count(kvlist, floating_veb_key)) { 920 rte_kvargs_free(kvlist); 921 return 0; 922 } 923 /* Floating VEB is enabled when there's key-value: 924 * enable_floating_veb=1 925 */ 926 if (rte_kvargs_process(kvlist, floating_veb_key, 927 i40e_check_floating_handler, NULL) < 0) { 928 rte_kvargs_free(kvlist); 929 return 0; 930 } 931 rte_kvargs_free(kvlist); 932 933 return 1; 934 } 935 936 static void 937 config_floating_veb(struct rte_eth_dev *dev) 938 { 939 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 942 943 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list)); 944 945 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) { 946 pf->floating_veb = 947 is_floating_veb_supported(pci_dev->device.devargs); 948 config_vf_floating_veb(pci_dev->device.devargs, 949 pf->floating_veb, 950 pf->floating_veb_list); 951 } else { 952 pf->floating_veb = false; 953 } 954 } 955 956 #define I40E_L2_TAGS_S_TAG_SHIFT 1 957 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT) 958 959 static int 960 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev) 961 { 962 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 963 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 964 char ethertype_hash_name[RTE_HASH_NAMESIZE]; 965 int ret; 966 967 struct rte_hash_parameters ethertype_hash_params = { 968 .name = ethertype_hash_name, 969 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM, 970 .key_len = sizeof(struct i40e_ethertype_filter_input), 971 .hash_func = rte_hash_crc, 972 .hash_func_init_val = 0, 973 .socket_id = rte_socket_id(), 974 }; 975 976 /* Initialize ethertype filter rule list and hash */ 977 TAILQ_INIT(ðertype_rule->ethertype_list); 978 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE, 979 "ethertype_%s", dev->device->name); 980 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params); 981 if (!ethertype_rule->hash_table) { 982 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!"); 983 return -EINVAL; 984 } 985 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map", 986 sizeof(struct i40e_ethertype_filter *) * 987 I40E_MAX_ETHERTYPE_FILTER_NUM, 988 0); 989 if (!ethertype_rule->hash_map) { 990 PMD_INIT_LOG(ERR, 991 "Failed to allocate memory for ethertype hash map!"); 992 ret = -ENOMEM; 993 goto err_ethertype_hash_map_alloc; 994 } 995 996 return 0; 997 998 err_ethertype_hash_map_alloc: 999 rte_hash_free(ethertype_rule->hash_table); 1000 1001 return ret; 1002 } 1003 1004 static int 1005 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev) 1006 { 1007 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1008 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 1009 char tunnel_hash_name[RTE_HASH_NAMESIZE]; 1010 int ret; 1011 1012 struct rte_hash_parameters tunnel_hash_params = { 1013 .name = tunnel_hash_name, 1014 .entries = I40E_MAX_TUNNEL_FILTER_NUM, 1015 .key_len = sizeof(struct i40e_tunnel_filter_input), 1016 .hash_func = rte_hash_crc, 1017 .hash_func_init_val = 0, 1018 .socket_id = rte_socket_id(), 1019 }; 1020 1021 /* Initialize tunnel filter rule list and hash */ 1022 TAILQ_INIT(&tunnel_rule->tunnel_list); 1023 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE, 1024 "tunnel_%s", dev->device->name); 1025 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params); 1026 if (!tunnel_rule->hash_table) { 1027 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!"); 1028 return -EINVAL; 1029 } 1030 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map", 1031 sizeof(struct i40e_tunnel_filter *) * 1032 I40E_MAX_TUNNEL_FILTER_NUM, 1033 0); 1034 if (!tunnel_rule->hash_map) { 1035 PMD_INIT_LOG(ERR, 1036 "Failed to allocate memory for tunnel hash map!"); 1037 ret = -ENOMEM; 1038 goto err_tunnel_hash_map_alloc; 1039 } 1040 1041 return 0; 1042 1043 err_tunnel_hash_map_alloc: 1044 rte_hash_free(tunnel_rule->hash_table); 1045 1046 return ret; 1047 } 1048 1049 static int 1050 i40e_init_fdir_filter_list(struct rte_eth_dev *dev) 1051 { 1052 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1053 struct i40e_fdir_info *fdir_info = &pf->fdir; 1054 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1055 int ret; 1056 1057 struct rte_hash_parameters fdir_hash_params = { 1058 .name = fdir_hash_name, 1059 .entries = I40E_MAX_FDIR_FILTER_NUM, 1060 .key_len = sizeof(struct i40e_fdir_input), 1061 .hash_func = rte_hash_crc, 1062 .hash_func_init_val = 0, 1063 .socket_id = rte_socket_id(), 1064 }; 1065 1066 /* Initialize flow director filter rule list and hash */ 1067 TAILQ_INIT(&fdir_info->fdir_list); 1068 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1069 "fdir_%s", dev->device->name); 1070 fdir_info->hash_table = rte_hash_create(&fdir_hash_params); 1071 if (!fdir_info->hash_table) { 1072 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1073 return -EINVAL; 1074 } 1075 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map", 1076 sizeof(struct i40e_fdir_filter *) * 1077 I40E_MAX_FDIR_FILTER_NUM, 1078 0); 1079 if (!fdir_info->hash_map) { 1080 PMD_INIT_LOG(ERR, 1081 "Failed to allocate memory for fdir hash map!"); 1082 ret = -ENOMEM; 1083 goto err_fdir_hash_map_alloc; 1084 } 1085 return 0; 1086 1087 err_fdir_hash_map_alloc: 1088 rte_hash_free(fdir_info->hash_table); 1089 1090 return ret; 1091 } 1092 1093 static void 1094 i40e_init_customized_info(struct i40e_pf *pf) 1095 { 1096 int i; 1097 1098 /* Initialize customized pctype */ 1099 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) { 1100 pf->customized_pctype[i].index = i; 1101 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID; 1102 pf->customized_pctype[i].valid = false; 1103 } 1104 1105 pf->gtp_support = false; 1106 } 1107 1108 void 1109 i40e_init_queue_region_conf(struct rte_eth_dev *dev) 1110 { 1111 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1112 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1113 struct i40e_queue_regions *info = &pf->queue_region; 1114 uint16_t i; 1115 1116 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++) 1117 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0); 1118 1119 memset(info, 0, sizeof(struct i40e_queue_regions)); 1120 } 1121 1122 static int 1123 i40e_parse_multi_drv_handler(__rte_unused const char *key, 1124 const char *value, 1125 void *opaque) 1126 { 1127 struct i40e_pf *pf; 1128 unsigned long support_multi_driver; 1129 char *end; 1130 1131 pf = (struct i40e_pf *)opaque; 1132 1133 errno = 0; 1134 support_multi_driver = strtoul(value, &end, 10); 1135 if (errno != 0 || end == value || *end != 0) { 1136 PMD_DRV_LOG(WARNING, "Wrong global configuration"); 1137 return -(EINVAL); 1138 } 1139 1140 if (support_multi_driver == 1 || support_multi_driver == 0) 1141 pf->support_multi_driver = (bool)support_multi_driver; 1142 else 1143 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,", 1144 "enable global configuration by default." 1145 ETH_I40E_SUPPORT_MULTI_DRIVER); 1146 return 0; 1147 } 1148 1149 static int 1150 i40e_support_multi_driver(struct rte_eth_dev *dev) 1151 { 1152 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1153 struct rte_kvargs *kvlist; 1154 int kvargs_count; 1155 1156 /* Enable global configuration by default */ 1157 pf->support_multi_driver = false; 1158 1159 if (!dev->device->devargs) 1160 return 0; 1161 1162 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1163 if (!kvlist) 1164 return -EINVAL; 1165 1166 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER); 1167 if (!kvargs_count) { 1168 rte_kvargs_free(kvlist); 1169 return 0; 1170 } 1171 1172 if (kvargs_count > 1) 1173 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 1174 "the first invalid or last valid one is used !", 1175 ETH_I40E_SUPPORT_MULTI_DRIVER); 1176 1177 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER, 1178 i40e_parse_multi_drv_handler, pf) < 0) { 1179 rte_kvargs_free(kvlist); 1180 return -EINVAL; 1181 } 1182 1183 rte_kvargs_free(kvlist); 1184 return 0; 1185 } 1186 1187 static int 1188 i40e_aq_debug_write_global_register(struct i40e_hw *hw, 1189 uint32_t reg_addr, uint64_t reg_val, 1190 struct i40e_asq_cmd_details *cmd_details) 1191 { 1192 uint64_t ori_reg_val; 1193 struct rte_eth_dev *dev; 1194 int ret; 1195 1196 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL); 1197 if (ret != I40E_SUCCESS) { 1198 PMD_DRV_LOG(ERR, 1199 "Fail to debug read from 0x%08x", 1200 reg_addr); 1201 return -EIO; 1202 } 1203 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 1204 1205 if (ori_reg_val != reg_val) 1206 PMD_DRV_LOG(WARNING, 1207 "i40e device %s changed global register [0x%08x]." 1208 " original: 0x%"PRIx64", after: 0x%"PRIx64, 1209 dev->device->name, reg_addr, ori_reg_val, reg_val); 1210 1211 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details); 1212 } 1213 1214 static int 1215 i40e_parse_latest_vec_handler(__rte_unused const char *key, 1216 const char *value, 1217 void *opaque) 1218 { 1219 struct i40e_adapter *ad = opaque; 1220 int use_latest_vec; 1221 1222 use_latest_vec = atoi(value); 1223 1224 if (use_latest_vec != 0 && use_latest_vec != 1) 1225 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!"); 1226 1227 ad->use_latest_vec = (uint8_t)use_latest_vec; 1228 1229 return 0; 1230 } 1231 1232 static int 1233 i40e_use_latest_vec(struct rte_eth_dev *dev) 1234 { 1235 struct i40e_adapter *ad = 1236 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1237 struct rte_kvargs *kvlist; 1238 int kvargs_count; 1239 1240 ad->use_latest_vec = false; 1241 1242 if (!dev->device->devargs) 1243 return 0; 1244 1245 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1246 if (!kvlist) 1247 return -EINVAL; 1248 1249 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC); 1250 if (!kvargs_count) { 1251 rte_kvargs_free(kvlist); 1252 return 0; 1253 } 1254 1255 if (kvargs_count > 1) 1256 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 1257 "the first invalid or last valid one is used !", 1258 ETH_I40E_USE_LATEST_VEC); 1259 1260 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC, 1261 i40e_parse_latest_vec_handler, ad) < 0) { 1262 rte_kvargs_free(kvlist); 1263 return -EINVAL; 1264 } 1265 1266 rte_kvargs_free(kvlist); 1267 return 0; 1268 } 1269 1270 static int 1271 read_vf_msg_config(__rte_unused const char *key, 1272 const char *value, 1273 void *opaque) 1274 { 1275 struct i40e_vf_msg_cfg *cfg = opaque; 1276 1277 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period, 1278 &cfg->ignore_second) != 3) { 1279 memset(cfg, 0, sizeof(*cfg)); 1280 PMD_DRV_LOG(ERR, "format error! example: " 1281 "%s=60@120:180", ETH_I40E_VF_MSG_CFG); 1282 return -EINVAL; 1283 } 1284 1285 /* 1286 * If the message validation function been enabled, the 'period' 1287 * and 'ignore_second' must greater than 0. 1288 */ 1289 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) { 1290 memset(cfg, 0, sizeof(*cfg)); 1291 PMD_DRV_LOG(ERR, "%s error! the second and third" 1292 " number must be greater than 0!", 1293 ETH_I40E_VF_MSG_CFG); 1294 return -EINVAL; 1295 } 1296 1297 return 0; 1298 } 1299 1300 static int 1301 i40e_parse_vf_msg_config(struct rte_eth_dev *dev, 1302 struct i40e_vf_msg_cfg *msg_cfg) 1303 { 1304 struct rte_kvargs *kvlist; 1305 int kvargs_count; 1306 int ret = 0; 1307 1308 memset(msg_cfg, 0, sizeof(*msg_cfg)); 1309 1310 if (!dev->device->devargs) 1311 return ret; 1312 1313 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1314 if (!kvlist) 1315 return -EINVAL; 1316 1317 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG); 1318 if (!kvargs_count) 1319 goto free_end; 1320 1321 if (kvargs_count > 1) { 1322 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!", 1323 ETH_I40E_VF_MSG_CFG); 1324 ret = -EINVAL; 1325 goto free_end; 1326 } 1327 1328 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG, 1329 read_vf_msg_config, msg_cfg) < 0) 1330 ret = -EINVAL; 1331 1332 free_end: 1333 rte_kvargs_free(kvlist); 1334 return ret; 1335 } 1336 1337 #define I40E_ALARM_INTERVAL 50000 /* us */ 1338 1339 static int 1340 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused) 1341 { 1342 struct rte_pci_device *pci_dev; 1343 struct rte_intr_handle *intr_handle; 1344 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1345 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1346 struct i40e_vsi *vsi; 1347 int ret; 1348 uint32_t len, val; 1349 uint8_t aq_fail = 0; 1350 1351 PMD_INIT_FUNC_TRACE(); 1352 1353 dev->dev_ops = &i40e_eth_dev_ops; 1354 dev->rx_pkt_burst = i40e_recv_pkts; 1355 dev->tx_pkt_burst = i40e_xmit_pkts; 1356 dev->tx_pkt_prepare = i40e_prep_pkts; 1357 1358 /* for secondary processes, we don't initialise any further as primary 1359 * has already done this work. Only check we don't need a different 1360 * RX function */ 1361 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 1362 i40e_set_rx_function(dev); 1363 i40e_set_tx_function(dev); 1364 return 0; 1365 } 1366 i40e_set_default_ptype_table(dev); 1367 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1368 intr_handle = &pci_dev->intr_handle; 1369 1370 rte_eth_copy_pci_info(dev, pci_dev); 1371 1372 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1373 pf->adapter->eth_dev = dev; 1374 pf->dev_data = dev->data; 1375 1376 hw->back = I40E_PF_TO_ADAPTER(pf); 1377 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr); 1378 if (!hw->hw_addr) { 1379 PMD_INIT_LOG(ERR, 1380 "Hardware is not available, as address is NULL"); 1381 return -ENODEV; 1382 } 1383 1384 hw->vendor_id = pci_dev->id.vendor_id; 1385 hw->device_id = pci_dev->id.device_id; 1386 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1387 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1388 hw->bus.device = pci_dev->addr.devid; 1389 hw->bus.func = pci_dev->addr.function; 1390 hw->adapter_stopped = 0; 1391 hw->adapter_closed = 0; 1392 1393 /* 1394 * Switch Tag value should not be identical to either the First Tag 1395 * or Second Tag values. So set something other than common Ethertype 1396 * for internal switching. 1397 */ 1398 hw->switch_tag = 0xffff; 1399 1400 val = I40E_READ_REG(hw, I40E_GL_FWSTS); 1401 if (val & I40E_GL_FWSTS_FWS1B_MASK) { 1402 PMD_INIT_LOG(ERR, "\nERROR: " 1403 "Firmware recovery mode detected. Limiting functionality.\n" 1404 "Refer to the Intel(R) Ethernet Adapters and Devices " 1405 "User Guide for details on firmware recovery mode."); 1406 return -EIO; 1407 } 1408 1409 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg); 1410 /* Check if need to support multi-driver */ 1411 i40e_support_multi_driver(dev); 1412 /* Check if users want the latest supported vec path */ 1413 i40e_use_latest_vec(dev); 1414 1415 /* Make sure all is clean before doing PF reset */ 1416 i40e_clear_hw(hw); 1417 1418 /* Reset here to make sure all is clean for each PF */ 1419 ret = i40e_pf_reset(hw); 1420 if (ret) { 1421 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret); 1422 return ret; 1423 } 1424 1425 /* Initialize the shared code (base driver) */ 1426 ret = i40e_init_shared_code(hw); 1427 if (ret) { 1428 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret); 1429 return ret; 1430 } 1431 1432 /* Initialize the parameters for adminq */ 1433 i40e_init_adminq_parameter(hw); 1434 ret = i40e_init_adminq(hw); 1435 if (ret != I40E_SUCCESS) { 1436 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret); 1437 return -EIO; 1438 } 1439 /* Firmware of SFP x722 does not support adminq option */ 1440 if (hw->device_id == I40E_DEV_ID_SFP_X722) 1441 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE; 1442 1443 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x", 1444 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 1445 hw->aq.api_maj_ver, hw->aq.api_min_ver, 1446 ((hw->nvm.version >> 12) & 0xf), 1447 ((hw->nvm.version >> 4) & 0xff), 1448 (hw->nvm.version & 0xf), hw->nvm.eetrack); 1449 1450 /* Initialize the hardware */ 1451 i40e_hw_init(dev); 1452 1453 i40e_config_automask(pf); 1454 1455 i40e_set_default_pctype_table(dev); 1456 1457 /* 1458 * To work around the NVM issue, initialize registers 1459 * for packet type of QinQ by software. 1460 * It should be removed once issues are fixed in NVM. 1461 */ 1462 if (!pf->support_multi_driver) 1463 i40e_GLQF_reg_init(hw); 1464 1465 /* Initialize the input set for filters (hash and fd) to default value */ 1466 i40e_filter_input_set_init(pf); 1467 1468 /* initialise the L3_MAP register */ 1469 if (!pf->support_multi_driver) { 1470 ret = i40e_aq_debug_write_global_register(hw, 1471 I40E_GLQF_L3_MAP(40), 1472 0x00000028, NULL); 1473 if (ret) 1474 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", 1475 ret); 1476 PMD_INIT_LOG(DEBUG, 1477 "Global register 0x%08x is changed with 0x28", 1478 I40E_GLQF_L3_MAP(40)); 1479 } 1480 1481 /* Need the special FW version to support floating VEB */ 1482 config_floating_veb(dev); 1483 /* Clear PXE mode */ 1484 i40e_clear_pxe_mode(hw); 1485 i40e_dev_sync_phy_type(hw); 1486 1487 /* 1488 * On X710, performance number is far from the expectation on recent 1489 * firmware versions. The fix for this issue may not be integrated in 1490 * the following firmware version. So the workaround in software driver 1491 * is needed. It needs to modify the initial values of 3 internal only 1492 * registers. Note that the workaround can be removed when it is fixed 1493 * in firmware in the future. 1494 */ 1495 i40e_configure_registers(hw); 1496 1497 /* Get hw capabilities */ 1498 ret = i40e_get_cap(hw); 1499 if (ret != I40E_SUCCESS) { 1500 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret); 1501 goto err_get_capabilities; 1502 } 1503 1504 /* Initialize parameters for PF */ 1505 ret = i40e_pf_parameter_init(dev); 1506 if (ret != 0) { 1507 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret); 1508 goto err_parameter_init; 1509 } 1510 1511 /* Initialize the queue management */ 1512 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp); 1513 if (ret < 0) { 1514 PMD_INIT_LOG(ERR, "Failed to init queue pool"); 1515 goto err_qp_pool_init; 1516 } 1517 ret = i40e_res_pool_init(&pf->msix_pool, 1, 1518 hw->func_caps.num_msix_vectors - 1); 1519 if (ret < 0) { 1520 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 1521 goto err_msix_pool_init; 1522 } 1523 1524 /* Initialize lan hmc */ 1525 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 1526 hw->func_caps.num_rx_qp, 0, 0); 1527 if (ret != I40E_SUCCESS) { 1528 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret); 1529 goto err_init_lan_hmc; 1530 } 1531 1532 /* Configure lan hmc */ 1533 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 1534 if (ret != I40E_SUCCESS) { 1535 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret); 1536 goto err_configure_lan_hmc; 1537 } 1538 1539 /* Get and check the mac address */ 1540 i40e_get_mac_addr(hw, hw->mac.addr); 1541 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) { 1542 PMD_INIT_LOG(ERR, "mac address is not valid"); 1543 ret = -EIO; 1544 goto err_get_mac_addr; 1545 } 1546 /* Copy the permanent MAC address */ 1547 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, 1548 (struct rte_ether_addr *)hw->mac.perm_addr); 1549 1550 /* Disable flow control */ 1551 hw->fc.requested_mode = I40E_FC_NONE; 1552 i40e_set_fc(hw, &aq_fail, TRUE); 1553 1554 /* Set the global registers with default ether type value */ 1555 if (!pf->support_multi_driver) { 1556 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 1557 RTE_ETHER_TYPE_VLAN); 1558 if (ret != I40E_SUCCESS) { 1559 PMD_INIT_LOG(ERR, 1560 "Failed to set the default outer " 1561 "VLAN ether type"); 1562 goto err_setup_pf_switch; 1563 } 1564 } 1565 1566 /* PF setup, which includes VSI setup */ 1567 ret = i40e_pf_setup(pf); 1568 if (ret) { 1569 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret); 1570 goto err_setup_pf_switch; 1571 } 1572 1573 vsi = pf->main_vsi; 1574 1575 /* Disable double vlan by default */ 1576 i40e_vsi_config_double_vlan(vsi, FALSE); 1577 1578 /* Disable S-TAG identification when floating_veb is disabled */ 1579 if (!pf->floating_veb) { 1580 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN); 1581 if (ret & I40E_L2_TAGS_S_TAG_MASK) { 1582 ret &= ~I40E_L2_TAGS_S_TAG_MASK; 1583 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret); 1584 } 1585 } 1586 1587 if (!vsi->max_macaddrs) 1588 len = RTE_ETHER_ADDR_LEN; 1589 else 1590 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs; 1591 1592 /* Should be after VSI initialized */ 1593 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0); 1594 if (!dev->data->mac_addrs) { 1595 PMD_INIT_LOG(ERR, 1596 "Failed to allocated memory for storing mac address"); 1597 goto err_mac_alloc; 1598 } 1599 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 1600 &dev->data->mac_addrs[0]); 1601 1602 /* Pass the information to the rte_eth_dev_close() that it should also 1603 * release the private port resources. 1604 */ 1605 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1606 1607 /* Init dcb to sw mode by default */ 1608 ret = i40e_dcb_init_configure(dev, TRUE); 1609 if (ret != I40E_SUCCESS) { 1610 PMD_INIT_LOG(INFO, "Failed to init dcb."); 1611 pf->flags &= ~I40E_FLAG_DCB; 1612 } 1613 /* Update HW struct after DCB configuration */ 1614 i40e_get_cap(hw); 1615 1616 /* initialize pf host driver to setup SRIOV resource if applicable */ 1617 i40e_pf_host_init(dev); 1618 1619 /* register callback func to eal lib */ 1620 rte_intr_callback_register(intr_handle, 1621 i40e_dev_interrupt_handler, dev); 1622 1623 /* configure and enable device interrupt */ 1624 i40e_pf_config_irq0(hw, TRUE); 1625 i40e_pf_enable_irq0(hw); 1626 1627 /* enable uio intr after callback register */ 1628 rte_intr_enable(intr_handle); 1629 1630 /* By default disable flexible payload in global configuration */ 1631 if (!pf->support_multi_driver) 1632 i40e_flex_payload_reg_set_default(hw); 1633 1634 /* 1635 * Add an ethertype filter to drop all flow control frames transmitted 1636 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC 1637 * frames to wire. 1638 */ 1639 i40e_add_tx_flow_control_drop_filter(pf); 1640 1641 /* Set the max frame size to 0x2600 by default, 1642 * in case other drivers changed the default value. 1643 */ 1644 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL); 1645 1646 /* initialize mirror rule list */ 1647 TAILQ_INIT(&pf->mirror_list); 1648 1649 /* initialize Traffic Manager configuration */ 1650 i40e_tm_conf_init(dev); 1651 1652 /* Initialize customized information */ 1653 i40e_init_customized_info(pf); 1654 1655 ret = i40e_init_ethtype_filter_list(dev); 1656 if (ret < 0) 1657 goto err_init_ethtype_filter_list; 1658 ret = i40e_init_tunnel_filter_list(dev); 1659 if (ret < 0) 1660 goto err_init_tunnel_filter_list; 1661 ret = i40e_init_fdir_filter_list(dev); 1662 if (ret < 0) 1663 goto err_init_fdir_filter_list; 1664 1665 /* initialize queue region configuration */ 1666 i40e_init_queue_region_conf(dev); 1667 1668 /* initialize rss configuration from rte_flow */ 1669 memset(&pf->rss_info, 0, 1670 sizeof(struct i40e_rte_flow_rss_conf)); 1671 1672 /* reset all stats of the device, including pf and main vsi */ 1673 i40e_dev_stats_reset(dev); 1674 1675 return 0; 1676 1677 err_init_fdir_filter_list: 1678 rte_free(pf->tunnel.hash_table); 1679 rte_free(pf->tunnel.hash_map); 1680 err_init_tunnel_filter_list: 1681 rte_free(pf->ethertype.hash_table); 1682 rte_free(pf->ethertype.hash_map); 1683 err_init_ethtype_filter_list: 1684 rte_free(dev->data->mac_addrs); 1685 dev->data->mac_addrs = NULL; 1686 err_mac_alloc: 1687 i40e_vsi_release(pf->main_vsi); 1688 err_setup_pf_switch: 1689 err_get_mac_addr: 1690 err_configure_lan_hmc: 1691 (void)i40e_shutdown_lan_hmc(hw); 1692 err_init_lan_hmc: 1693 i40e_res_pool_destroy(&pf->msix_pool); 1694 err_msix_pool_init: 1695 i40e_res_pool_destroy(&pf->qp_pool); 1696 err_qp_pool_init: 1697 err_parameter_init: 1698 err_get_capabilities: 1699 (void)i40e_shutdown_adminq(hw); 1700 1701 return ret; 1702 } 1703 1704 static void 1705 i40e_rm_ethtype_filter_list(struct i40e_pf *pf) 1706 { 1707 struct i40e_ethertype_filter *p_ethertype; 1708 struct i40e_ethertype_rule *ethertype_rule; 1709 1710 ethertype_rule = &pf->ethertype; 1711 /* Remove all ethertype filter rules and hash */ 1712 if (ethertype_rule->hash_map) 1713 rte_free(ethertype_rule->hash_map); 1714 if (ethertype_rule->hash_table) 1715 rte_hash_free(ethertype_rule->hash_table); 1716 1717 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) { 1718 TAILQ_REMOVE(ðertype_rule->ethertype_list, 1719 p_ethertype, rules); 1720 rte_free(p_ethertype); 1721 } 1722 } 1723 1724 static void 1725 i40e_rm_tunnel_filter_list(struct i40e_pf *pf) 1726 { 1727 struct i40e_tunnel_filter *p_tunnel; 1728 struct i40e_tunnel_rule *tunnel_rule; 1729 1730 tunnel_rule = &pf->tunnel; 1731 /* Remove all tunnel director rules and hash */ 1732 if (tunnel_rule->hash_map) 1733 rte_free(tunnel_rule->hash_map); 1734 if (tunnel_rule->hash_table) 1735 rte_hash_free(tunnel_rule->hash_table); 1736 1737 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) { 1738 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules); 1739 rte_free(p_tunnel); 1740 } 1741 } 1742 1743 static void 1744 i40e_rm_fdir_filter_list(struct i40e_pf *pf) 1745 { 1746 struct i40e_fdir_filter *p_fdir; 1747 struct i40e_fdir_info *fdir_info; 1748 1749 fdir_info = &pf->fdir; 1750 /* Remove all flow director rules and hash */ 1751 if (fdir_info->hash_map) 1752 rte_free(fdir_info->hash_map); 1753 if (fdir_info->hash_table) 1754 rte_hash_free(fdir_info->hash_table); 1755 1756 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) { 1757 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules); 1758 rte_free(p_fdir); 1759 } 1760 } 1761 1762 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw) 1763 { 1764 /* 1765 * Disable by default flexible payload 1766 * for corresponding L2/L3/L4 layers. 1767 */ 1768 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000); 1769 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000); 1770 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000); 1771 } 1772 1773 static int 1774 eth_i40e_dev_uninit(struct rte_eth_dev *dev) 1775 { 1776 struct i40e_hw *hw; 1777 1778 PMD_INIT_FUNC_TRACE(); 1779 1780 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1781 return 0; 1782 1783 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1784 1785 if (hw->adapter_closed == 0) 1786 i40e_dev_close(dev); 1787 1788 return 0; 1789 } 1790 1791 static int 1792 i40e_dev_configure(struct rte_eth_dev *dev) 1793 { 1794 struct i40e_adapter *ad = 1795 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1798 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1799 int i, ret; 1800 1801 ret = i40e_dev_sync_phy_type(hw); 1802 if (ret) 1803 return ret; 1804 1805 /* Initialize to TRUE. If any of Rx queues doesn't meet the 1806 * bulk allocation or vector Rx preconditions we will reset it. 1807 */ 1808 ad->rx_bulk_alloc_allowed = true; 1809 ad->rx_vec_allowed = true; 1810 ad->tx_simple_allowed = true; 1811 ad->tx_vec_allowed = true; 1812 1813 /* Only legacy filter API needs the following fdir config. So when the 1814 * legacy filter API is deprecated, the following codes should also be 1815 * removed. 1816 */ 1817 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) { 1818 ret = i40e_fdir_setup(pf); 1819 if (ret != I40E_SUCCESS) { 1820 PMD_DRV_LOG(ERR, "Failed to setup flow director."); 1821 return -ENOTSUP; 1822 } 1823 ret = i40e_fdir_configure(dev); 1824 if (ret < 0) { 1825 PMD_DRV_LOG(ERR, "failed to configure fdir."); 1826 goto err; 1827 } 1828 } else 1829 i40e_fdir_teardown(pf); 1830 1831 ret = i40e_dev_init_vlan(dev); 1832 if (ret < 0) 1833 goto err; 1834 1835 /* VMDQ setup. 1836 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and 1837 * RSS setting have different requirements. 1838 * General PMD driver call sequence are NIC init, configure, 1839 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it 1840 * will try to lookup the VSI that specific queue belongs to if VMDQ 1841 * applicable. So, VMDQ setting has to be done before 1842 * rx/tx_queue_setup(). This function is good to place vmdq_setup. 1843 * For RSS setting, it will try to calculate actual configured RX queue 1844 * number, which will be available after rx_queue_setup(). dev_start() 1845 * function is good to place RSS setup. 1846 */ 1847 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) { 1848 ret = i40e_vmdq_setup(dev); 1849 if (ret) 1850 goto err; 1851 } 1852 1853 if (mq_mode & ETH_MQ_RX_DCB_FLAG) { 1854 ret = i40e_dcb_setup(dev); 1855 if (ret) { 1856 PMD_DRV_LOG(ERR, "failed to configure DCB."); 1857 goto err_dcb; 1858 } 1859 } 1860 1861 TAILQ_INIT(&pf->flow_list); 1862 1863 return 0; 1864 1865 err_dcb: 1866 /* need to release vmdq resource if exists */ 1867 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 1868 i40e_vsi_release(pf->vmdq[i].vsi); 1869 pf->vmdq[i].vsi = NULL; 1870 } 1871 rte_free(pf->vmdq); 1872 pf->vmdq = NULL; 1873 err: 1874 /* Need to release fdir resource if exists. 1875 * Only legacy filter API needs the following fdir config. So when the 1876 * legacy filter API is deprecated, the following code should also be 1877 * removed. 1878 */ 1879 i40e_fdir_teardown(pf); 1880 return ret; 1881 } 1882 1883 void 1884 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi) 1885 { 1886 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 1887 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1888 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1889 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1890 uint16_t msix_vect = vsi->msix_intr; 1891 uint16_t i; 1892 1893 for (i = 0; i < vsi->nb_qps; i++) { 1894 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); 1895 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); 1896 rte_wmb(); 1897 } 1898 1899 if (vsi->type != I40E_VSI_SRIOV) { 1900 if (!rte_intr_allow_others(intr_handle)) { 1901 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 1902 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); 1903 I40E_WRITE_REG(hw, 1904 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), 1905 0); 1906 } else { 1907 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 1908 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); 1909 I40E_WRITE_REG(hw, 1910 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, 1911 msix_vect - 1), 0); 1912 } 1913 } else { 1914 uint32_t reg; 1915 reg = (hw->func_caps.num_msix_vectors_vf - 1) * 1916 vsi->user_param + (msix_vect - 1); 1917 1918 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 1919 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK); 1920 } 1921 I40E_WRITE_FLUSH(hw); 1922 } 1923 1924 static void 1925 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect, 1926 int base_queue, int nb_queue, 1927 uint16_t itr_idx) 1928 { 1929 int i; 1930 uint32_t val; 1931 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 1932 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 1933 1934 /* Bind all RX queues to allocated MSIX interrupt */ 1935 for (i = 0; i < nb_queue; i++) { 1936 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 1937 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT | 1938 ((base_queue + i + 1) << 1939 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 1940 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 1941 I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1942 1943 if (i == nb_queue - 1) 1944 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK; 1945 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val); 1946 } 1947 1948 /* Write first RX queue to Link list register as the head element */ 1949 if (vsi->type != I40E_VSI_SRIOV) { 1950 uint16_t interval = 1951 i40e_calc_itr_interval(1, pf->support_multi_driver); 1952 1953 if (msix_vect == I40E_MISC_VEC_ID) { 1954 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 1955 (base_queue << 1956 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 1957 (0x0 << 1958 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 1959 I40E_WRITE_REG(hw, 1960 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT), 1961 interval); 1962 } else { 1963 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 1964 (base_queue << 1965 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 1966 (0x0 << 1967 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 1968 I40E_WRITE_REG(hw, 1969 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT, 1970 msix_vect - 1), 1971 interval); 1972 } 1973 } else { 1974 uint32_t reg; 1975 1976 if (msix_vect == I40E_MISC_VEC_ID) { 1977 I40E_WRITE_REG(hw, 1978 I40E_VPINT_LNKLST0(vsi->user_param), 1979 (base_queue << 1980 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 1981 (0x0 << 1982 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 1983 } else { 1984 /* num_msix_vectors_vf needs to minus irq0 */ 1985 reg = (hw->func_caps.num_msix_vectors_vf - 1) * 1986 vsi->user_param + (msix_vect - 1); 1987 1988 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 1989 (base_queue << 1990 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 1991 (0x0 << 1992 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 1993 } 1994 } 1995 1996 I40E_WRITE_FLUSH(hw); 1997 } 1998 1999 void 2000 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx) 2001 { 2002 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2003 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2004 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2005 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2006 uint16_t msix_vect = vsi->msix_intr; 2007 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 2008 uint16_t queue_idx = 0; 2009 int record = 0; 2010 int i; 2011 2012 for (i = 0; i < vsi->nb_qps; i++) { 2013 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0); 2014 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0); 2015 } 2016 2017 /* VF bind interrupt */ 2018 if (vsi->type == I40E_VSI_SRIOV) { 2019 __vsi_queues_bind_intr(vsi, msix_vect, 2020 vsi->base_queue, vsi->nb_qps, 2021 itr_idx); 2022 return; 2023 } 2024 2025 /* PF & VMDq bind interrupt */ 2026 if (rte_intr_dp_is_en(intr_handle)) { 2027 if (vsi->type == I40E_VSI_MAIN) { 2028 queue_idx = 0; 2029 record = 1; 2030 } else if (vsi->type == I40E_VSI_VMDQ2) { 2031 struct i40e_vsi *main_vsi = 2032 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter); 2033 queue_idx = vsi->base_queue - main_vsi->nb_qps; 2034 record = 1; 2035 } 2036 } 2037 2038 for (i = 0; i < vsi->nb_used_qps; i++) { 2039 if (nb_msix <= 1) { 2040 if (!rte_intr_allow_others(intr_handle)) 2041 /* allow to share MISC_VEC_ID */ 2042 msix_vect = I40E_MISC_VEC_ID; 2043 2044 /* no enough msix_vect, map all to one */ 2045 __vsi_queues_bind_intr(vsi, msix_vect, 2046 vsi->base_queue + i, 2047 vsi->nb_used_qps - i, 2048 itr_idx); 2049 for (; !!record && i < vsi->nb_used_qps; i++) 2050 intr_handle->intr_vec[queue_idx + i] = 2051 msix_vect; 2052 break; 2053 } 2054 /* 1:1 queue/msix_vect mapping */ 2055 __vsi_queues_bind_intr(vsi, msix_vect, 2056 vsi->base_queue + i, 1, 2057 itr_idx); 2058 if (!!record) 2059 intr_handle->intr_vec[queue_idx + i] = msix_vect; 2060 2061 msix_vect++; 2062 nb_msix--; 2063 } 2064 } 2065 2066 static void 2067 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi) 2068 { 2069 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2070 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2071 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2072 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2073 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 2074 uint16_t msix_intr, i; 2075 2076 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) 2077 for (i = 0; i < vsi->nb_msix; i++) { 2078 msix_intr = vsi->msix_intr + i; 2079 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), 2080 I40E_PFINT_DYN_CTLN_INTENA_MASK | 2081 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 2082 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 2083 } 2084 else 2085 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 2086 I40E_PFINT_DYN_CTL0_INTENA_MASK | 2087 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 2088 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 2089 2090 I40E_WRITE_FLUSH(hw); 2091 } 2092 2093 static void 2094 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi) 2095 { 2096 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2097 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2098 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2099 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2100 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 2101 uint16_t msix_intr, i; 2102 2103 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver) 2104 for (i = 0; i < vsi->nb_msix; i++) { 2105 msix_intr = vsi->msix_intr + i; 2106 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1), 2107 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 2108 } 2109 else 2110 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 2111 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 2112 2113 I40E_WRITE_FLUSH(hw); 2114 } 2115 2116 static inline uint8_t 2117 i40e_parse_link_speeds(uint16_t link_speeds) 2118 { 2119 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN; 2120 2121 if (link_speeds & ETH_LINK_SPEED_40G) 2122 link_speed |= I40E_LINK_SPEED_40GB; 2123 if (link_speeds & ETH_LINK_SPEED_25G) 2124 link_speed |= I40E_LINK_SPEED_25GB; 2125 if (link_speeds & ETH_LINK_SPEED_20G) 2126 link_speed |= I40E_LINK_SPEED_20GB; 2127 if (link_speeds & ETH_LINK_SPEED_10G) 2128 link_speed |= I40E_LINK_SPEED_10GB; 2129 if (link_speeds & ETH_LINK_SPEED_1G) 2130 link_speed |= I40E_LINK_SPEED_1GB; 2131 if (link_speeds & ETH_LINK_SPEED_100M) 2132 link_speed |= I40E_LINK_SPEED_100MB; 2133 2134 return link_speed; 2135 } 2136 2137 static int 2138 i40e_phy_conf_link(struct i40e_hw *hw, 2139 uint8_t abilities, 2140 uint8_t force_speed, 2141 bool is_up) 2142 { 2143 enum i40e_status_code status; 2144 struct i40e_aq_get_phy_abilities_resp phy_ab; 2145 struct i40e_aq_set_phy_config phy_conf; 2146 enum i40e_aq_phy_type cnt; 2147 uint8_t avail_speed; 2148 uint32_t phy_type_mask = 0; 2149 2150 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX | 2151 I40E_AQ_PHY_FLAG_PAUSE_RX | 2152 I40E_AQ_PHY_FLAG_PAUSE_RX | 2153 I40E_AQ_PHY_FLAG_LOW_POWER; 2154 int ret = -ENOTSUP; 2155 2156 /* To get phy capabilities of available speeds. */ 2157 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, 2158 NULL); 2159 if (status) { 2160 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n", 2161 status); 2162 return ret; 2163 } 2164 avail_speed = phy_ab.link_speed; 2165 2166 /* To get the current phy config. */ 2167 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab, 2168 NULL); 2169 if (status) { 2170 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n", 2171 status); 2172 return ret; 2173 } 2174 2175 /* If link needs to go up and it is in autoneg mode the speed is OK, 2176 * no need to set up again. 2177 */ 2178 if (is_up && phy_ab.phy_type != 0 && 2179 abilities & I40E_AQ_PHY_AN_ENABLED && 2180 phy_ab.link_speed != 0) 2181 return I40E_SUCCESS; 2182 2183 memset(&phy_conf, 0, sizeof(phy_conf)); 2184 2185 /* bits 0-2 use the values from get_phy_abilities_resp */ 2186 abilities &= ~mask; 2187 abilities |= phy_ab.abilities & mask; 2188 2189 phy_conf.abilities = abilities; 2190 2191 /* If link needs to go up, but the force speed is not supported, 2192 * Warn users and config the default available speeds. 2193 */ 2194 if (is_up && !(force_speed & avail_speed)) { 2195 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n"); 2196 phy_conf.link_speed = avail_speed; 2197 } else { 2198 phy_conf.link_speed = is_up ? force_speed : avail_speed; 2199 } 2200 2201 /* PHY type mask needs to include each type except PHY type extension */ 2202 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++) 2203 phy_type_mask |= 1 << cnt; 2204 2205 /* use get_phy_abilities_resp value for the rest */ 2206 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0; 2207 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR | 2208 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR | 2209 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0; 2210 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info; 2211 phy_conf.eee_capability = phy_ab.eee_capability; 2212 phy_conf.eeer = phy_ab.eeer_val; 2213 phy_conf.low_power_ctrl = phy_ab.d3_lpan; 2214 2215 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x", 2216 phy_ab.abilities, phy_ab.link_speed); 2217 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x", 2218 phy_conf.abilities, phy_conf.link_speed); 2219 2220 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL); 2221 if (status) 2222 return ret; 2223 2224 return I40E_SUCCESS; 2225 } 2226 2227 static int 2228 i40e_apply_link_speed(struct rte_eth_dev *dev) 2229 { 2230 uint8_t speed; 2231 uint8_t abilities = 0; 2232 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2233 struct rte_eth_conf *conf = &dev->data->dev_conf; 2234 2235 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) { 2236 conf->link_speeds = ETH_LINK_SPEED_40G | 2237 ETH_LINK_SPEED_25G | 2238 ETH_LINK_SPEED_20G | 2239 ETH_LINK_SPEED_10G | 2240 ETH_LINK_SPEED_1G | 2241 ETH_LINK_SPEED_100M; 2242 } 2243 speed = i40e_parse_link_speeds(conf->link_speeds); 2244 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK | 2245 I40E_AQ_PHY_AN_ENABLED | 2246 I40E_AQ_PHY_LINK_ENABLED; 2247 2248 return i40e_phy_conf_link(hw, abilities, speed, true); 2249 } 2250 2251 static int 2252 i40e_dev_start(struct rte_eth_dev *dev) 2253 { 2254 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2256 struct i40e_vsi *main_vsi = pf->main_vsi; 2257 int ret, i; 2258 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2259 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2260 uint32_t intr_vector = 0; 2261 struct i40e_vsi *vsi; 2262 2263 hw->adapter_stopped = 0; 2264 2265 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2266 PMD_INIT_LOG(ERR, 2267 "Invalid link_speeds for port %u, autonegotiation disabled", 2268 dev->data->port_id); 2269 return -EINVAL; 2270 } 2271 2272 rte_intr_disable(intr_handle); 2273 2274 if ((rte_intr_cap_multiple(intr_handle) || 2275 !RTE_ETH_DEV_SRIOV(dev).active) && 2276 dev->data->dev_conf.intr_conf.rxq != 0) { 2277 intr_vector = dev->data->nb_rx_queues; 2278 ret = rte_intr_efd_enable(intr_handle, intr_vector); 2279 if (ret) 2280 return ret; 2281 } 2282 2283 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2284 intr_handle->intr_vec = 2285 rte_zmalloc("intr_vec", 2286 dev->data->nb_rx_queues * sizeof(int), 2287 0); 2288 if (!intr_handle->intr_vec) { 2289 PMD_INIT_LOG(ERR, 2290 "Failed to allocate %d rx_queues intr_vec", 2291 dev->data->nb_rx_queues); 2292 return -ENOMEM; 2293 } 2294 } 2295 2296 /* Initialize VSI */ 2297 ret = i40e_dev_rxtx_init(pf); 2298 if (ret != I40E_SUCCESS) { 2299 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues"); 2300 goto err_up; 2301 } 2302 2303 /* Map queues with MSIX interrupt */ 2304 main_vsi->nb_used_qps = dev->data->nb_rx_queues - 2305 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 2306 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT); 2307 i40e_vsi_enable_queues_intr(main_vsi); 2308 2309 /* Map VMDQ VSI queues with MSIX interrupt */ 2310 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2311 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 2312 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi, 2313 I40E_ITR_INDEX_DEFAULT); 2314 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi); 2315 } 2316 2317 /* enable FDIR MSIX interrupt */ 2318 if (pf->fdir.fdir_vsi) { 2319 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi, 2320 I40E_ITR_INDEX_NONE); 2321 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi); 2322 } 2323 2324 /* Enable all queues which have been configured */ 2325 ret = i40e_dev_switch_queues(pf, TRUE); 2326 if (ret != I40E_SUCCESS) { 2327 PMD_DRV_LOG(ERR, "Failed to enable VSI"); 2328 goto err_up; 2329 } 2330 2331 /* Enable receiving broadcast packets */ 2332 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL); 2333 if (ret != I40E_SUCCESS) 2334 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2335 2336 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2337 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid, 2338 true, NULL); 2339 if (ret != I40E_SUCCESS) 2340 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2341 } 2342 2343 /* Enable the VLAN promiscuous mode. */ 2344 if (pf->vfs) { 2345 for (i = 0; i < pf->vf_num; i++) { 2346 vsi = pf->vfs[i].vsi; 2347 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, 2348 true, NULL); 2349 } 2350 } 2351 2352 /* Enable mac loopback mode */ 2353 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE || 2354 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) { 2355 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL); 2356 if (ret != I40E_SUCCESS) { 2357 PMD_DRV_LOG(ERR, "fail to set loopback link"); 2358 goto err_up; 2359 } 2360 } 2361 2362 /* Apply link configure */ 2363 ret = i40e_apply_link_speed(dev); 2364 if (I40E_SUCCESS != ret) { 2365 PMD_DRV_LOG(ERR, "Fail to apply link setting"); 2366 goto err_up; 2367 } 2368 2369 if (!rte_intr_allow_others(intr_handle)) { 2370 rte_intr_callback_unregister(intr_handle, 2371 i40e_dev_interrupt_handler, 2372 (void *)dev); 2373 /* configure and enable device interrupt */ 2374 i40e_pf_config_irq0(hw, FALSE); 2375 i40e_pf_enable_irq0(hw); 2376 2377 if (dev->data->dev_conf.intr_conf.lsc != 0) 2378 PMD_INIT_LOG(INFO, 2379 "lsc won't enable because of no intr multiplex"); 2380 } else { 2381 ret = i40e_aq_set_phy_int_mask(hw, 2382 ~(I40E_AQ_EVENT_LINK_UPDOWN | 2383 I40E_AQ_EVENT_MODULE_QUAL_FAIL | 2384 I40E_AQ_EVENT_MEDIA_NA), NULL); 2385 if (ret != I40E_SUCCESS) 2386 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 2387 2388 /* Call get_link_info aq commond to enable/disable LSE */ 2389 i40e_dev_link_update(dev, 0); 2390 } 2391 2392 if (dev->data->dev_conf.intr_conf.rxq == 0) { 2393 rte_eal_alarm_set(I40E_ALARM_INTERVAL, 2394 i40e_dev_alarm_handler, dev); 2395 } else { 2396 /* enable uio intr after callback register */ 2397 rte_intr_enable(intr_handle); 2398 } 2399 2400 i40e_filter_restore(pf); 2401 2402 if (pf->tm_conf.root && !pf->tm_conf.committed) 2403 PMD_DRV_LOG(WARNING, 2404 "please call hierarchy_commit() " 2405 "before starting the port"); 2406 2407 return I40E_SUCCESS; 2408 2409 err_up: 2410 i40e_dev_switch_queues(pf, FALSE); 2411 i40e_dev_clear_queues(dev); 2412 2413 return ret; 2414 } 2415 2416 static void 2417 i40e_dev_stop(struct rte_eth_dev *dev) 2418 { 2419 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2421 struct i40e_vsi *main_vsi = pf->main_vsi; 2422 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2423 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2424 int i; 2425 2426 if (hw->adapter_stopped == 1) 2427 return; 2428 2429 if (dev->data->dev_conf.intr_conf.rxq == 0) { 2430 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev); 2431 rte_intr_enable(intr_handle); 2432 } 2433 2434 /* Disable all queues */ 2435 i40e_dev_switch_queues(pf, FALSE); 2436 2437 /* un-map queues with interrupt registers */ 2438 i40e_vsi_disable_queues_intr(main_vsi); 2439 i40e_vsi_queues_unbind_intr(main_vsi); 2440 2441 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2442 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi); 2443 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi); 2444 } 2445 2446 if (pf->fdir.fdir_vsi) { 2447 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi); 2448 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi); 2449 } 2450 /* Clear all queues and release memory */ 2451 i40e_dev_clear_queues(dev); 2452 2453 /* Set link down */ 2454 i40e_dev_set_link_down(dev); 2455 2456 if (!rte_intr_allow_others(intr_handle)) 2457 /* resume to the default handler */ 2458 rte_intr_callback_register(intr_handle, 2459 i40e_dev_interrupt_handler, 2460 (void *)dev); 2461 2462 /* Clean datapath event and queue/vec mapping */ 2463 rte_intr_efd_disable(intr_handle); 2464 if (intr_handle->intr_vec) { 2465 rte_free(intr_handle->intr_vec); 2466 intr_handle->intr_vec = NULL; 2467 } 2468 2469 /* reset hierarchy commit */ 2470 pf->tm_conf.committed = false; 2471 2472 hw->adapter_stopped = 1; 2473 2474 pf->adapter->rss_reta_updated = 0; 2475 } 2476 2477 static void 2478 i40e_dev_close(struct rte_eth_dev *dev) 2479 { 2480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2481 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2482 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2483 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2484 struct i40e_mirror_rule *p_mirror; 2485 struct i40e_filter_control_settings settings; 2486 struct rte_flow *p_flow; 2487 uint32_t reg; 2488 int i; 2489 int ret; 2490 uint8_t aq_fail = 0; 2491 int retries = 0; 2492 2493 PMD_INIT_FUNC_TRACE(); 2494 2495 ret = rte_eth_switch_domain_free(pf->switch_domain_id); 2496 if (ret) 2497 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret); 2498 2499 2500 i40e_dev_stop(dev); 2501 2502 /* Remove all mirror rules */ 2503 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) { 2504 ret = i40e_aq_del_mirror_rule(hw, 2505 pf->main_vsi->veb->seid, 2506 p_mirror->rule_type, 2507 p_mirror->entries, 2508 p_mirror->num_entries, 2509 p_mirror->id); 2510 if (ret < 0) 2511 PMD_DRV_LOG(ERR, "failed to remove mirror rule: " 2512 "status = %d, aq_err = %d.", ret, 2513 hw->aq.asq_last_status); 2514 2515 /* remove mirror software resource anyway */ 2516 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules); 2517 rte_free(p_mirror); 2518 pf->nb_mirror_rule--; 2519 } 2520 2521 i40e_dev_free_queues(dev); 2522 2523 /* Disable interrupt */ 2524 i40e_pf_disable_irq0(hw); 2525 rte_intr_disable(intr_handle); 2526 2527 /* 2528 * Only legacy filter API needs the following fdir config. So when the 2529 * legacy filter API is deprecated, the following code should also be 2530 * removed. 2531 */ 2532 i40e_fdir_teardown(pf); 2533 2534 /* shutdown and destroy the HMC */ 2535 i40e_shutdown_lan_hmc(hw); 2536 2537 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) { 2538 i40e_vsi_release(pf->vmdq[i].vsi); 2539 pf->vmdq[i].vsi = NULL; 2540 } 2541 rte_free(pf->vmdq); 2542 pf->vmdq = NULL; 2543 2544 /* release all the existing VSIs and VEBs */ 2545 i40e_vsi_release(pf->main_vsi); 2546 2547 /* shutdown the adminq */ 2548 i40e_aq_queue_shutdown(hw, true); 2549 i40e_shutdown_adminq(hw); 2550 2551 i40e_res_pool_destroy(&pf->qp_pool); 2552 i40e_res_pool_destroy(&pf->msix_pool); 2553 2554 /* Disable flexible payload in global configuration */ 2555 if (!pf->support_multi_driver) 2556 i40e_flex_payload_reg_set_default(hw); 2557 2558 /* force a PF reset to clean anything leftover */ 2559 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL); 2560 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL, 2561 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 2562 I40E_WRITE_FLUSH(hw); 2563 2564 dev->dev_ops = NULL; 2565 dev->rx_pkt_burst = NULL; 2566 dev->tx_pkt_burst = NULL; 2567 2568 /* Clear PXE mode */ 2569 i40e_clear_pxe_mode(hw); 2570 2571 /* Unconfigure filter control */ 2572 memset(&settings, 0, sizeof(settings)); 2573 ret = i40e_set_filter_control(hw, &settings); 2574 if (ret) 2575 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d", 2576 ret); 2577 2578 /* Disable flow control */ 2579 hw->fc.requested_mode = I40E_FC_NONE; 2580 i40e_set_fc(hw, &aq_fail, TRUE); 2581 2582 /* uninitialize pf host driver */ 2583 i40e_pf_host_uninit(dev); 2584 2585 do { 2586 ret = rte_intr_callback_unregister(intr_handle, 2587 i40e_dev_interrupt_handler, dev); 2588 if (ret >= 0) { 2589 break; 2590 } else if (ret != -EAGAIN) { 2591 PMD_INIT_LOG(ERR, 2592 "intr callback unregister failed: %d", 2593 ret); 2594 } 2595 i40e_msec_delay(500); 2596 } while (retries++ < 5); 2597 2598 i40e_rm_ethtype_filter_list(pf); 2599 i40e_rm_tunnel_filter_list(pf); 2600 i40e_rm_fdir_filter_list(pf); 2601 2602 /* Remove all flows */ 2603 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) { 2604 TAILQ_REMOVE(&pf->flow_list, p_flow, node); 2605 rte_free(p_flow); 2606 } 2607 2608 /* Remove all Traffic Manager configuration */ 2609 i40e_tm_conf_uninit(dev); 2610 2611 hw->adapter_closed = 1; 2612 } 2613 2614 /* 2615 * Reset PF device only to re-initialize resources in PMD layer 2616 */ 2617 static int 2618 i40e_dev_reset(struct rte_eth_dev *dev) 2619 { 2620 int ret; 2621 2622 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2623 * its VF to make them align with it. The detailed notification 2624 * mechanism is PMD specific. As to i40e PF, it is rather complex. 2625 * To avoid unexpected behavior in VF, currently reset of PF with 2626 * SR-IOV activation is not supported. It might be supported later. 2627 */ 2628 if (dev->data->sriov.active) 2629 return -ENOTSUP; 2630 2631 ret = eth_i40e_dev_uninit(dev); 2632 if (ret) 2633 return ret; 2634 2635 ret = eth_i40e_dev_init(dev, NULL); 2636 2637 return ret; 2638 } 2639 2640 static int 2641 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev) 2642 { 2643 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2645 struct i40e_vsi *vsi = pf->main_vsi; 2646 int status; 2647 2648 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2649 true, NULL, true); 2650 if (status != I40E_SUCCESS) { 2651 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous"); 2652 return -EAGAIN; 2653 } 2654 2655 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, 2656 TRUE, NULL); 2657 if (status != I40E_SUCCESS) { 2658 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous"); 2659 /* Rollback unicast promiscuous mode */ 2660 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2661 false, NULL, true); 2662 return -EAGAIN; 2663 } 2664 2665 return 0; 2666 } 2667 2668 static int 2669 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev) 2670 { 2671 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2672 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2673 struct i40e_vsi *vsi = pf->main_vsi; 2674 int status; 2675 2676 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2677 false, NULL, true); 2678 if (status != I40E_SUCCESS) { 2679 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous"); 2680 return -EAGAIN; 2681 } 2682 2683 /* must remain in all_multicast mode */ 2684 if (dev->data->all_multicast == 1) 2685 return 0; 2686 2687 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, 2688 false, NULL); 2689 if (status != I40E_SUCCESS) { 2690 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous"); 2691 /* Rollback unicast promiscuous mode */ 2692 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid, 2693 true, NULL, true); 2694 return -EAGAIN; 2695 } 2696 2697 return 0; 2698 } 2699 2700 static int 2701 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev) 2702 { 2703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2704 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2705 struct i40e_vsi *vsi = pf->main_vsi; 2706 int ret; 2707 2708 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL); 2709 if (ret != I40E_SUCCESS) { 2710 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous"); 2711 return -EAGAIN; 2712 } 2713 2714 return 0; 2715 } 2716 2717 static int 2718 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev) 2719 { 2720 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2722 struct i40e_vsi *vsi = pf->main_vsi; 2723 int ret; 2724 2725 if (dev->data->promiscuous == 1) 2726 return 0; /* must remain in all_multicast mode */ 2727 2728 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, 2729 vsi->seid, FALSE, NULL); 2730 if (ret != I40E_SUCCESS) { 2731 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous"); 2732 return -EAGAIN; 2733 } 2734 2735 return 0; 2736 } 2737 2738 /* 2739 * Set device link up. 2740 */ 2741 static int 2742 i40e_dev_set_link_up(struct rte_eth_dev *dev) 2743 { 2744 /* re-apply link speed setting */ 2745 return i40e_apply_link_speed(dev); 2746 } 2747 2748 /* 2749 * Set device link down. 2750 */ 2751 static int 2752 i40e_dev_set_link_down(struct rte_eth_dev *dev) 2753 { 2754 uint8_t speed = I40E_LINK_SPEED_UNKNOWN; 2755 uint8_t abilities = 0; 2756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2757 2758 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 2759 return i40e_phy_conf_link(hw, abilities, speed, false); 2760 } 2761 2762 static __rte_always_inline void 2763 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link) 2764 { 2765 /* Link status registers and values*/ 2766 #define I40E_PRTMAC_LINKSTA 0x001E2420 2767 #define I40E_REG_LINK_UP 0x40000080 2768 #define I40E_PRTMAC_MACC 0x001E24E0 2769 #define I40E_REG_MACC_25GB 0x00020000 2770 #define I40E_REG_SPEED_MASK 0x38000000 2771 #define I40E_REG_SPEED_0 0x00000000 2772 #define I40E_REG_SPEED_1 0x08000000 2773 #define I40E_REG_SPEED_2 0x10000000 2774 #define I40E_REG_SPEED_3 0x18000000 2775 #define I40E_REG_SPEED_4 0x20000000 2776 uint32_t link_speed; 2777 uint32_t reg_val; 2778 2779 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA); 2780 link_speed = reg_val & I40E_REG_SPEED_MASK; 2781 reg_val &= I40E_REG_LINK_UP; 2782 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0; 2783 2784 if (unlikely(link->link_status == 0)) 2785 return; 2786 2787 /* Parse the link status */ 2788 switch (link_speed) { 2789 case I40E_REG_SPEED_0: 2790 link->link_speed = ETH_SPEED_NUM_100M; 2791 break; 2792 case I40E_REG_SPEED_1: 2793 link->link_speed = ETH_SPEED_NUM_1G; 2794 break; 2795 case I40E_REG_SPEED_2: 2796 if (hw->mac.type == I40E_MAC_X722) 2797 link->link_speed = ETH_SPEED_NUM_2_5G; 2798 else 2799 link->link_speed = ETH_SPEED_NUM_10G; 2800 break; 2801 case I40E_REG_SPEED_3: 2802 if (hw->mac.type == I40E_MAC_X722) { 2803 link->link_speed = ETH_SPEED_NUM_5G; 2804 } else { 2805 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC); 2806 2807 if (reg_val & I40E_REG_MACC_25GB) 2808 link->link_speed = ETH_SPEED_NUM_25G; 2809 else 2810 link->link_speed = ETH_SPEED_NUM_40G; 2811 } 2812 break; 2813 case I40E_REG_SPEED_4: 2814 if (hw->mac.type == I40E_MAC_X722) 2815 link->link_speed = ETH_SPEED_NUM_10G; 2816 else 2817 link->link_speed = ETH_SPEED_NUM_20G; 2818 break; 2819 default: 2820 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed); 2821 break; 2822 } 2823 } 2824 2825 static __rte_always_inline void 2826 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link, 2827 bool enable_lse, int wait_to_complete) 2828 { 2829 #define CHECK_INTERVAL 100 /* 100ms */ 2830 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 2831 uint32_t rep_cnt = MAX_REPEAT_TIME; 2832 struct i40e_link_status link_status; 2833 int status; 2834 2835 memset(&link_status, 0, sizeof(link_status)); 2836 2837 do { 2838 memset(&link_status, 0, sizeof(link_status)); 2839 2840 /* Get link status information from hardware */ 2841 status = i40e_aq_get_link_info(hw, enable_lse, 2842 &link_status, NULL); 2843 if (unlikely(status != I40E_SUCCESS)) { 2844 link->link_speed = ETH_SPEED_NUM_NONE; 2845 link->link_duplex = ETH_LINK_FULL_DUPLEX; 2846 PMD_DRV_LOG(ERR, "Failed to get link info"); 2847 return; 2848 } 2849 2850 link->link_status = link_status.link_info & I40E_AQ_LINK_UP; 2851 if (!wait_to_complete || link->link_status) 2852 break; 2853 2854 rte_delay_ms(CHECK_INTERVAL); 2855 } while (--rep_cnt); 2856 2857 /* Parse the link status */ 2858 switch (link_status.link_speed) { 2859 case I40E_LINK_SPEED_100MB: 2860 link->link_speed = ETH_SPEED_NUM_100M; 2861 break; 2862 case I40E_LINK_SPEED_1GB: 2863 link->link_speed = ETH_SPEED_NUM_1G; 2864 break; 2865 case I40E_LINK_SPEED_10GB: 2866 link->link_speed = ETH_SPEED_NUM_10G; 2867 break; 2868 case I40E_LINK_SPEED_20GB: 2869 link->link_speed = ETH_SPEED_NUM_20G; 2870 break; 2871 case I40E_LINK_SPEED_25GB: 2872 link->link_speed = ETH_SPEED_NUM_25G; 2873 break; 2874 case I40E_LINK_SPEED_40GB: 2875 link->link_speed = ETH_SPEED_NUM_40G; 2876 break; 2877 default: 2878 link->link_speed = ETH_SPEED_NUM_NONE; 2879 break; 2880 } 2881 } 2882 2883 int 2884 i40e_dev_link_update(struct rte_eth_dev *dev, 2885 int wait_to_complete) 2886 { 2887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2888 struct rte_eth_link link; 2889 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2890 int ret; 2891 2892 memset(&link, 0, sizeof(link)); 2893 2894 /* i40e uses full duplex only */ 2895 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2896 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2897 ETH_LINK_SPEED_FIXED); 2898 2899 if (!wait_to_complete && !enable_lse) 2900 update_link_reg(hw, &link); 2901 else 2902 update_link_aq(hw, &link, enable_lse, wait_to_complete); 2903 2904 ret = rte_eth_linkstatus_set(dev, &link); 2905 i40e_notify_all_vfs_link_status(dev); 2906 2907 return ret; 2908 } 2909 2910 /* Get all the statistics of a VSI */ 2911 void 2912 i40e_update_vsi_stats(struct i40e_vsi *vsi) 2913 { 2914 struct i40e_eth_stats *oes = &vsi->eth_stats_offset; 2915 struct i40e_eth_stats *nes = &vsi->eth_stats; 2916 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2917 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx); 2918 2919 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx), 2920 vsi->offset_loaded, &oes->rx_bytes, 2921 &nes->rx_bytes); 2922 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx), 2923 vsi->offset_loaded, &oes->rx_unicast, 2924 &nes->rx_unicast); 2925 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx), 2926 vsi->offset_loaded, &oes->rx_multicast, 2927 &nes->rx_multicast); 2928 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx), 2929 vsi->offset_loaded, &oes->rx_broadcast, 2930 &nes->rx_broadcast); 2931 /* exclude CRC bytes */ 2932 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 2933 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 2934 2935 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded, 2936 &oes->rx_discards, &nes->rx_discards); 2937 /* GLV_REPC not supported */ 2938 /* GLV_RMPC not supported */ 2939 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded, 2940 &oes->rx_unknown_protocol, 2941 &nes->rx_unknown_protocol); 2942 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx), 2943 vsi->offset_loaded, &oes->tx_bytes, 2944 &nes->tx_bytes); 2945 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx), 2946 vsi->offset_loaded, &oes->tx_unicast, 2947 &nes->tx_unicast); 2948 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx), 2949 vsi->offset_loaded, &oes->tx_multicast, 2950 &nes->tx_multicast); 2951 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx), 2952 vsi->offset_loaded, &oes->tx_broadcast, 2953 &nes->tx_broadcast); 2954 /* GLV_TDPC not supported */ 2955 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded, 2956 &oes->tx_errors, &nes->tx_errors); 2957 vsi->offset_loaded = true; 2958 2959 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************", 2960 vsi->vsi_id); 2961 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 2962 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 2963 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 2964 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 2965 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 2966 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 2967 nes->rx_unknown_protocol); 2968 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 2969 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 2970 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 2971 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 2972 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 2973 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 2974 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************", 2975 vsi->vsi_id); 2976 } 2977 2978 static void 2979 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) 2980 { 2981 unsigned int i; 2982 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */ 2983 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */ 2984 2985 /* Get rx/tx bytes of internal transfer packets */ 2986 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port), 2987 I40E_GLV_GORCL(hw->port), 2988 pf->offset_loaded, 2989 &pf->internal_stats_offset.rx_bytes, 2990 &pf->internal_stats.rx_bytes); 2991 2992 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port), 2993 I40E_GLV_GOTCL(hw->port), 2994 pf->offset_loaded, 2995 &pf->internal_stats_offset.tx_bytes, 2996 &pf->internal_stats.tx_bytes); 2997 /* Get total internal rx packet count */ 2998 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port), 2999 I40E_GLV_UPRCL(hw->port), 3000 pf->offset_loaded, 3001 &pf->internal_stats_offset.rx_unicast, 3002 &pf->internal_stats.rx_unicast); 3003 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port), 3004 I40E_GLV_MPRCL(hw->port), 3005 pf->offset_loaded, 3006 &pf->internal_stats_offset.rx_multicast, 3007 &pf->internal_stats.rx_multicast); 3008 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port), 3009 I40E_GLV_BPRCL(hw->port), 3010 pf->offset_loaded, 3011 &pf->internal_stats_offset.rx_broadcast, 3012 &pf->internal_stats.rx_broadcast); 3013 /* Get total internal tx packet count */ 3014 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port), 3015 I40E_GLV_UPTCL(hw->port), 3016 pf->offset_loaded, 3017 &pf->internal_stats_offset.tx_unicast, 3018 &pf->internal_stats.tx_unicast); 3019 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port), 3020 I40E_GLV_MPTCL(hw->port), 3021 pf->offset_loaded, 3022 &pf->internal_stats_offset.tx_multicast, 3023 &pf->internal_stats.tx_multicast); 3024 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port), 3025 I40E_GLV_BPTCL(hw->port), 3026 pf->offset_loaded, 3027 &pf->internal_stats_offset.tx_broadcast, 3028 &pf->internal_stats.tx_broadcast); 3029 3030 /* exclude CRC size */ 3031 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast + 3032 pf->internal_stats.rx_multicast + 3033 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN; 3034 3035 /* Get statistics of struct i40e_eth_stats */ 3036 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port), 3037 I40E_GLPRT_GORCL(hw->port), 3038 pf->offset_loaded, &os->eth.rx_bytes, 3039 &ns->eth.rx_bytes); 3040 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port), 3041 I40E_GLPRT_UPRCL(hw->port), 3042 pf->offset_loaded, &os->eth.rx_unicast, 3043 &ns->eth.rx_unicast); 3044 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port), 3045 I40E_GLPRT_MPRCL(hw->port), 3046 pf->offset_loaded, &os->eth.rx_multicast, 3047 &ns->eth.rx_multicast); 3048 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port), 3049 I40E_GLPRT_BPRCL(hw->port), 3050 pf->offset_loaded, &os->eth.rx_broadcast, 3051 &ns->eth.rx_broadcast); 3052 /* Workaround: CRC size should not be included in byte statistics, 3053 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 3054 * packet. 3055 */ 3056 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 3057 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 3058 3059 /* exclude internal rx bytes 3060 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before 3061 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative 3062 * value. 3063 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L]. 3064 */ 3065 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes) 3066 ns->eth.rx_bytes = 0; 3067 else 3068 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes; 3069 3070 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast) 3071 ns->eth.rx_unicast = 0; 3072 else 3073 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast; 3074 3075 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast) 3076 ns->eth.rx_multicast = 0; 3077 else 3078 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast; 3079 3080 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast) 3081 ns->eth.rx_broadcast = 0; 3082 else 3083 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast; 3084 3085 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port), 3086 pf->offset_loaded, &os->eth.rx_discards, 3087 &ns->eth.rx_discards); 3088 /* GLPRT_REPC not supported */ 3089 /* GLPRT_RMPC not supported */ 3090 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port), 3091 pf->offset_loaded, 3092 &os->eth.rx_unknown_protocol, 3093 &ns->eth.rx_unknown_protocol); 3094 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port), 3095 I40E_GLPRT_GOTCL(hw->port), 3096 pf->offset_loaded, &os->eth.tx_bytes, 3097 &ns->eth.tx_bytes); 3098 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port), 3099 I40E_GLPRT_UPTCL(hw->port), 3100 pf->offset_loaded, &os->eth.tx_unicast, 3101 &ns->eth.tx_unicast); 3102 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port), 3103 I40E_GLPRT_MPTCL(hw->port), 3104 pf->offset_loaded, &os->eth.tx_multicast, 3105 &ns->eth.tx_multicast); 3106 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port), 3107 I40E_GLPRT_BPTCL(hw->port), 3108 pf->offset_loaded, &os->eth.tx_broadcast, 3109 &ns->eth.tx_broadcast); 3110 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 3111 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 3112 3113 /* exclude internal tx bytes 3114 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before 3115 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative 3116 * value. 3117 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L]. 3118 */ 3119 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes) 3120 ns->eth.tx_bytes = 0; 3121 else 3122 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes; 3123 3124 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast) 3125 ns->eth.tx_unicast = 0; 3126 else 3127 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast; 3128 3129 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast) 3130 ns->eth.tx_multicast = 0; 3131 else 3132 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast; 3133 3134 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast) 3135 ns->eth.tx_broadcast = 0; 3136 else 3137 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast; 3138 3139 /* GLPRT_TEPC not supported */ 3140 3141 /* additional port specific stats */ 3142 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port), 3143 pf->offset_loaded, &os->tx_dropped_link_down, 3144 &ns->tx_dropped_link_down); 3145 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port), 3146 pf->offset_loaded, &os->crc_errors, 3147 &ns->crc_errors); 3148 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port), 3149 pf->offset_loaded, &os->illegal_bytes, 3150 &ns->illegal_bytes); 3151 /* GLPRT_ERRBC not supported */ 3152 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port), 3153 pf->offset_loaded, &os->mac_local_faults, 3154 &ns->mac_local_faults); 3155 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port), 3156 pf->offset_loaded, &os->mac_remote_faults, 3157 &ns->mac_remote_faults); 3158 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port), 3159 pf->offset_loaded, &os->rx_length_errors, 3160 &ns->rx_length_errors); 3161 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port), 3162 pf->offset_loaded, &os->link_xon_rx, 3163 &ns->link_xon_rx); 3164 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 3165 pf->offset_loaded, &os->link_xoff_rx, 3166 &ns->link_xoff_rx); 3167 for (i = 0; i < 8; i++) { 3168 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i), 3169 pf->offset_loaded, 3170 &os->priority_xon_rx[i], 3171 &ns->priority_xon_rx[i]); 3172 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), 3173 pf->offset_loaded, 3174 &os->priority_xoff_rx[i], 3175 &ns->priority_xoff_rx[i]); 3176 } 3177 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port), 3178 pf->offset_loaded, &os->link_xon_tx, 3179 &ns->link_xon_tx); 3180 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 3181 pf->offset_loaded, &os->link_xoff_tx, 3182 &ns->link_xoff_tx); 3183 for (i = 0; i < 8; i++) { 3184 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i), 3185 pf->offset_loaded, 3186 &os->priority_xon_tx[i], 3187 &ns->priority_xon_tx[i]); 3188 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), 3189 pf->offset_loaded, 3190 &os->priority_xoff_tx[i], 3191 &ns->priority_xoff_tx[i]); 3192 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i), 3193 pf->offset_loaded, 3194 &os->priority_xon_2_xoff[i], 3195 &ns->priority_xon_2_xoff[i]); 3196 } 3197 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port), 3198 I40E_GLPRT_PRC64L(hw->port), 3199 pf->offset_loaded, &os->rx_size_64, 3200 &ns->rx_size_64); 3201 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port), 3202 I40E_GLPRT_PRC127L(hw->port), 3203 pf->offset_loaded, &os->rx_size_127, 3204 &ns->rx_size_127); 3205 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port), 3206 I40E_GLPRT_PRC255L(hw->port), 3207 pf->offset_loaded, &os->rx_size_255, 3208 &ns->rx_size_255); 3209 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port), 3210 I40E_GLPRT_PRC511L(hw->port), 3211 pf->offset_loaded, &os->rx_size_511, 3212 &ns->rx_size_511); 3213 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port), 3214 I40E_GLPRT_PRC1023L(hw->port), 3215 pf->offset_loaded, &os->rx_size_1023, 3216 &ns->rx_size_1023); 3217 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port), 3218 I40E_GLPRT_PRC1522L(hw->port), 3219 pf->offset_loaded, &os->rx_size_1522, 3220 &ns->rx_size_1522); 3221 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port), 3222 I40E_GLPRT_PRC9522L(hw->port), 3223 pf->offset_loaded, &os->rx_size_big, 3224 &ns->rx_size_big); 3225 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port), 3226 pf->offset_loaded, &os->rx_undersize, 3227 &ns->rx_undersize); 3228 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port), 3229 pf->offset_loaded, &os->rx_fragments, 3230 &ns->rx_fragments); 3231 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port), 3232 pf->offset_loaded, &os->rx_oversize, 3233 &ns->rx_oversize); 3234 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port), 3235 pf->offset_loaded, &os->rx_jabber, 3236 &ns->rx_jabber); 3237 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port), 3238 I40E_GLPRT_PTC64L(hw->port), 3239 pf->offset_loaded, &os->tx_size_64, 3240 &ns->tx_size_64); 3241 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port), 3242 I40E_GLPRT_PTC127L(hw->port), 3243 pf->offset_loaded, &os->tx_size_127, 3244 &ns->tx_size_127); 3245 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port), 3246 I40E_GLPRT_PTC255L(hw->port), 3247 pf->offset_loaded, &os->tx_size_255, 3248 &ns->tx_size_255); 3249 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port), 3250 I40E_GLPRT_PTC511L(hw->port), 3251 pf->offset_loaded, &os->tx_size_511, 3252 &ns->tx_size_511); 3253 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port), 3254 I40E_GLPRT_PTC1023L(hw->port), 3255 pf->offset_loaded, &os->tx_size_1023, 3256 &ns->tx_size_1023); 3257 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port), 3258 I40E_GLPRT_PTC1522L(hw->port), 3259 pf->offset_loaded, &os->tx_size_1522, 3260 &ns->tx_size_1522); 3261 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port), 3262 I40E_GLPRT_PTC9522L(hw->port), 3263 pf->offset_loaded, &os->tx_size_big, 3264 &ns->tx_size_big); 3265 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index), 3266 pf->offset_loaded, 3267 &os->fd_sb_match, &ns->fd_sb_match); 3268 /* GLPRT_MSPDC not supported */ 3269 /* GLPRT_XEC not supported */ 3270 3271 pf->offset_loaded = true; 3272 3273 if (pf->main_vsi) 3274 i40e_update_vsi_stats(pf->main_vsi); 3275 } 3276 3277 /* Get all statistics of a port */ 3278 static int 3279 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3280 { 3281 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3282 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3283 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */ 3284 struct i40e_vsi *vsi; 3285 unsigned i; 3286 3287 /* call read registers - updates values, now write them to struct */ 3288 i40e_read_stats_registers(pf, hw); 3289 3290 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 3291 pf->main_vsi->eth_stats.rx_multicast + 3292 pf->main_vsi->eth_stats.rx_broadcast - 3293 pf->main_vsi->eth_stats.rx_discards; 3294 stats->opackets = ns->eth.tx_unicast + 3295 ns->eth.tx_multicast + 3296 ns->eth.tx_broadcast; 3297 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 3298 stats->obytes = ns->eth.tx_bytes; 3299 stats->oerrors = ns->eth.tx_errors + 3300 pf->main_vsi->eth_stats.tx_errors; 3301 3302 /* Rx Errors */ 3303 stats->imissed = ns->eth.rx_discards + 3304 pf->main_vsi->eth_stats.rx_discards; 3305 stats->ierrors = ns->crc_errors + 3306 ns->rx_length_errors + ns->rx_undersize + 3307 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 3308 3309 if (pf->vfs) { 3310 for (i = 0; i < pf->vf_num; i++) { 3311 vsi = pf->vfs[i].vsi; 3312 i40e_update_vsi_stats(vsi); 3313 3314 stats->ipackets += (vsi->eth_stats.rx_unicast + 3315 vsi->eth_stats.rx_multicast + 3316 vsi->eth_stats.rx_broadcast - 3317 vsi->eth_stats.rx_discards); 3318 stats->ibytes += vsi->eth_stats.rx_bytes; 3319 stats->oerrors += vsi->eth_stats.tx_errors; 3320 stats->imissed += vsi->eth_stats.rx_discards; 3321 } 3322 } 3323 3324 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************"); 3325 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 3326 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 3327 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast); 3328 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast); 3329 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards); 3330 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 3331 ns->eth.rx_unknown_protocol); 3332 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 3333 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 3334 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast); 3335 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast); 3336 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards); 3337 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 3338 3339 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 3340 ns->tx_dropped_link_down); 3341 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 3342 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 3343 ns->illegal_bytes); 3344 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 3345 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 3346 ns->mac_local_faults); 3347 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 3348 ns->mac_remote_faults); 3349 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"", 3350 ns->rx_length_errors); 3351 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 3352 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 3353 for (i = 0; i < 8; i++) { 3354 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"", 3355 i, ns->priority_xon_rx[i]); 3356 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"", 3357 i, ns->priority_xoff_rx[i]); 3358 } 3359 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 3360 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 3361 for (i = 0; i < 8; i++) { 3362 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"", 3363 i, ns->priority_xon_tx[i]); 3364 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"", 3365 i, ns->priority_xoff_tx[i]); 3366 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"", 3367 i, ns->priority_xon_2_xoff[i]); 3368 } 3369 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 3370 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 3371 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 3372 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 3373 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 3374 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 3375 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 3376 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 3377 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 3378 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 3379 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 3380 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 3381 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 3382 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 3383 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 3384 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 3385 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 3386 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 3387 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"", 3388 ns->mac_short_packet_dropped); 3389 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"", 3390 ns->checksum_error); 3391 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match); 3392 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************"); 3393 return 0; 3394 } 3395 3396 /* Reset the statistics */ 3397 static int 3398 i40e_dev_stats_reset(struct rte_eth_dev *dev) 3399 { 3400 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3401 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3402 3403 /* Mark PF and VSI stats to update the offset, aka "reset" */ 3404 pf->offset_loaded = false; 3405 if (pf->main_vsi) 3406 pf->main_vsi->offset_loaded = false; 3407 3408 /* read the stats, reading current register values into offset */ 3409 i40e_read_stats_registers(pf, hw); 3410 3411 return 0; 3412 } 3413 3414 static uint32_t 3415 i40e_xstats_calc_num(void) 3416 { 3417 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + 3418 (I40E_NB_RXQ_PRIO_XSTATS * 8) + 3419 (I40E_NB_TXQ_PRIO_XSTATS * 8); 3420 } 3421 3422 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3423 struct rte_eth_xstat_name *xstats_names, 3424 __rte_unused unsigned limit) 3425 { 3426 unsigned count = 0; 3427 unsigned i, prio; 3428 3429 if (xstats_names == NULL) 3430 return i40e_xstats_calc_num(); 3431 3432 /* Note: limit checked in rte_eth_xstats_names() */ 3433 3434 /* Get stats from i40e_eth_stats struct */ 3435 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) { 3436 strlcpy(xstats_names[count].name, 3437 rte_i40e_stats_strings[i].name, 3438 sizeof(xstats_names[count].name)); 3439 count++; 3440 } 3441 3442 /* Get individiual stats from i40e_hw_port struct */ 3443 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) { 3444 strlcpy(xstats_names[count].name, 3445 rte_i40e_hw_port_strings[i].name, 3446 sizeof(xstats_names[count].name)); 3447 count++; 3448 } 3449 3450 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) { 3451 for (prio = 0; prio < 8; prio++) { 3452 snprintf(xstats_names[count].name, 3453 sizeof(xstats_names[count].name), 3454 "rx_priority%u_%s", prio, 3455 rte_i40e_rxq_prio_strings[i].name); 3456 count++; 3457 } 3458 } 3459 3460 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) { 3461 for (prio = 0; prio < 8; prio++) { 3462 snprintf(xstats_names[count].name, 3463 sizeof(xstats_names[count].name), 3464 "tx_priority%u_%s", prio, 3465 rte_i40e_txq_prio_strings[i].name); 3466 count++; 3467 } 3468 } 3469 return count; 3470 } 3471 3472 static int 3473 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3474 unsigned n) 3475 { 3476 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3477 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3478 unsigned i, count, prio; 3479 struct i40e_hw_port_stats *hw_stats = &pf->stats; 3480 3481 count = i40e_xstats_calc_num(); 3482 if (n < count) 3483 return count; 3484 3485 i40e_read_stats_registers(pf, hw); 3486 3487 if (xstats == NULL) 3488 return 0; 3489 3490 count = 0; 3491 3492 /* Get stats from i40e_eth_stats struct */ 3493 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) { 3494 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) + 3495 rte_i40e_stats_strings[i].offset); 3496 xstats[count].id = count; 3497 count++; 3498 } 3499 3500 /* Get individiual stats from i40e_hw_port struct */ 3501 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) { 3502 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3503 rte_i40e_hw_port_strings[i].offset); 3504 xstats[count].id = count; 3505 count++; 3506 } 3507 3508 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) { 3509 for (prio = 0; prio < 8; prio++) { 3510 xstats[count].value = 3511 *(uint64_t *)(((char *)hw_stats) + 3512 rte_i40e_rxq_prio_strings[i].offset + 3513 (sizeof(uint64_t) * prio)); 3514 xstats[count].id = count; 3515 count++; 3516 } 3517 } 3518 3519 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) { 3520 for (prio = 0; prio < 8; prio++) { 3521 xstats[count].value = 3522 *(uint64_t *)(((char *)hw_stats) + 3523 rte_i40e_txq_prio_strings[i].offset + 3524 (sizeof(uint64_t) * prio)); 3525 xstats[count].id = count; 3526 count++; 3527 } 3528 } 3529 3530 return count; 3531 } 3532 3533 static int 3534 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3535 { 3536 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3537 u32 full_ver; 3538 u8 ver, patch; 3539 u16 build; 3540 int ret; 3541 3542 full_ver = hw->nvm.oem_ver; 3543 ver = (u8)(full_ver >> 24); 3544 build = (u16)((full_ver >> 8) & 0xffff); 3545 patch = (u8)(full_ver & 0xff); 3546 3547 ret = snprintf(fw_version, fw_size, 3548 "%d.%d%d 0x%08x %d.%d.%d", 3549 ((hw->nvm.version >> 12) & 0xf), 3550 ((hw->nvm.version >> 4) & 0xff), 3551 (hw->nvm.version & 0xf), hw->nvm.eetrack, 3552 ver, build, patch); 3553 3554 ret += 1; /* add the size of '\0' */ 3555 if (fw_size < (u32)ret) 3556 return ret; 3557 else 3558 return 0; 3559 } 3560 3561 /* 3562 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later, 3563 * the Rx data path does not hang if the FW LLDP is stopped. 3564 * return true if lldp need to stop 3565 * return false if we cannot disable the LLDP to avoid Rx data path blocking. 3566 */ 3567 static bool 3568 i40e_need_stop_lldp(struct rte_eth_dev *dev) 3569 { 3570 double nvm_ver; 3571 char ver_str[64] = {0}; 3572 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3573 3574 i40e_fw_version_get(dev, ver_str, 64); 3575 nvm_ver = atof(ver_str); 3576 if ((hw->mac.type == I40E_MAC_X722 || 3577 hw->mac.type == I40E_MAC_X722_VF) && 3578 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000))) 3579 return true; 3580 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000)) 3581 return true; 3582 3583 return false; 3584 } 3585 3586 static int 3587 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3588 { 3589 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3590 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3591 struct i40e_vsi *vsi = pf->main_vsi; 3592 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3593 3594 dev_info->max_rx_queues = vsi->nb_qps; 3595 dev_info->max_tx_queues = vsi->nb_qps; 3596 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN; 3597 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX; 3598 dev_info->max_mac_addrs = vsi->max_macaddrs; 3599 dev_info->max_vfs = pci_dev->max_vfs; 3600 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD; 3601 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3602 dev_info->rx_queue_offload_capa = 0; 3603 dev_info->rx_offload_capa = 3604 DEV_RX_OFFLOAD_VLAN_STRIP | 3605 DEV_RX_OFFLOAD_QINQ_STRIP | 3606 DEV_RX_OFFLOAD_IPV4_CKSUM | 3607 DEV_RX_OFFLOAD_UDP_CKSUM | 3608 DEV_RX_OFFLOAD_TCP_CKSUM | 3609 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 3610 DEV_RX_OFFLOAD_KEEP_CRC | 3611 DEV_RX_OFFLOAD_SCATTER | 3612 DEV_RX_OFFLOAD_VLAN_EXTEND | 3613 DEV_RX_OFFLOAD_VLAN_FILTER | 3614 DEV_RX_OFFLOAD_JUMBO_FRAME; 3615 3616 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 3617 dev_info->tx_offload_capa = 3618 DEV_TX_OFFLOAD_VLAN_INSERT | 3619 DEV_TX_OFFLOAD_QINQ_INSERT | 3620 DEV_TX_OFFLOAD_IPV4_CKSUM | 3621 DEV_TX_OFFLOAD_UDP_CKSUM | 3622 DEV_TX_OFFLOAD_TCP_CKSUM | 3623 DEV_TX_OFFLOAD_SCTP_CKSUM | 3624 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 3625 DEV_TX_OFFLOAD_TCP_TSO | 3626 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 3627 DEV_TX_OFFLOAD_GRE_TNL_TSO | 3628 DEV_TX_OFFLOAD_IPIP_TNL_TSO | 3629 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 3630 DEV_TX_OFFLOAD_MULTI_SEGS | 3631 dev_info->tx_queue_offload_capa; 3632 dev_info->dev_capa = 3633 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 3634 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 3635 3636 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 3637 sizeof(uint32_t); 3638 dev_info->reta_size = pf->hash_lut_size; 3639 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask; 3640 3641 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3642 .rx_thresh = { 3643 .pthresh = I40E_DEFAULT_RX_PTHRESH, 3644 .hthresh = I40E_DEFAULT_RX_HTHRESH, 3645 .wthresh = I40E_DEFAULT_RX_WTHRESH, 3646 }, 3647 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH, 3648 .rx_drop_en = 0, 3649 .offloads = 0, 3650 }; 3651 3652 dev_info->default_txconf = (struct rte_eth_txconf) { 3653 .tx_thresh = { 3654 .pthresh = I40E_DEFAULT_TX_PTHRESH, 3655 .hthresh = I40E_DEFAULT_TX_HTHRESH, 3656 .wthresh = I40E_DEFAULT_TX_WTHRESH, 3657 }, 3658 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH, 3659 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH, 3660 .offloads = 0, 3661 }; 3662 3663 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 3664 .nb_max = I40E_MAX_RING_DESC, 3665 .nb_min = I40E_MIN_RING_DESC, 3666 .nb_align = I40E_ALIGN_RING_DESC, 3667 }; 3668 3669 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 3670 .nb_max = I40E_MAX_RING_DESC, 3671 .nb_min = I40E_MIN_RING_DESC, 3672 .nb_align = I40E_ALIGN_RING_DESC, 3673 .nb_seg_max = I40E_TX_MAX_SEG, 3674 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG, 3675 }; 3676 3677 if (pf->flags & I40E_FLAG_VMDQ) { 3678 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi; 3679 dev_info->vmdq_queue_base = dev_info->max_rx_queues; 3680 dev_info->vmdq_queue_num = pf->vmdq_nb_qps * 3681 pf->max_nb_vmdq_vsi; 3682 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE; 3683 dev_info->max_rx_queues += dev_info->vmdq_queue_num; 3684 dev_info->max_tx_queues += dev_info->vmdq_queue_num; 3685 } 3686 3687 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { 3688 /* For XL710 */ 3689 dev_info->speed_capa = ETH_LINK_SPEED_40G; 3690 dev_info->default_rxportconf.nb_queues = 2; 3691 dev_info->default_txportconf.nb_queues = 2; 3692 if (dev->data->nb_rx_queues == 1) 3693 dev_info->default_rxportconf.ring_size = 2048; 3694 else 3695 dev_info->default_rxportconf.ring_size = 1024; 3696 if (dev->data->nb_tx_queues == 1) 3697 dev_info->default_txportconf.ring_size = 1024; 3698 else 3699 dev_info->default_txportconf.ring_size = 512; 3700 3701 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) { 3702 /* For XXV710 */ 3703 dev_info->speed_capa = ETH_LINK_SPEED_25G; 3704 dev_info->default_rxportconf.nb_queues = 1; 3705 dev_info->default_txportconf.nb_queues = 1; 3706 dev_info->default_rxportconf.ring_size = 256; 3707 dev_info->default_txportconf.ring_size = 256; 3708 } else { 3709 /* For X710 */ 3710 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3711 dev_info->default_rxportconf.nb_queues = 1; 3712 dev_info->default_txportconf.nb_queues = 1; 3713 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) { 3714 dev_info->default_rxportconf.ring_size = 512; 3715 dev_info->default_txportconf.ring_size = 256; 3716 } else { 3717 dev_info->default_rxportconf.ring_size = 256; 3718 dev_info->default_txportconf.ring_size = 256; 3719 } 3720 } 3721 dev_info->default_rxportconf.burst_size = 32; 3722 dev_info->default_txportconf.burst_size = 32; 3723 3724 return 0; 3725 } 3726 3727 static int 3728 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3729 { 3730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3731 struct i40e_vsi *vsi = pf->main_vsi; 3732 PMD_INIT_FUNC_TRACE(); 3733 3734 if (on) 3735 return i40e_vsi_add_vlan(vsi, vlan_id); 3736 else 3737 return i40e_vsi_delete_vlan(vsi, vlan_id); 3738 } 3739 3740 static int 3741 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev, 3742 enum rte_vlan_type vlan_type, 3743 uint16_t tpid, int qinq) 3744 { 3745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3746 uint64_t reg_r = 0; 3747 uint64_t reg_w = 0; 3748 uint16_t reg_id = 3; 3749 int ret; 3750 3751 if (qinq) { 3752 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3753 reg_id = 2; 3754 } 3755 3756 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), 3757 ®_r, NULL); 3758 if (ret != I40E_SUCCESS) { 3759 PMD_DRV_LOG(ERR, 3760 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]", 3761 reg_id); 3762 return -EIO; 3763 } 3764 PMD_DRV_LOG(DEBUG, 3765 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64, 3766 reg_id, reg_r); 3767 3768 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK)); 3769 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT); 3770 if (reg_r == reg_w) { 3771 PMD_DRV_LOG(DEBUG, "No need to write"); 3772 return 0; 3773 } 3774 3775 ret = i40e_aq_debug_write_global_register(hw, 3776 I40E_GL_SWT_L2TAGCTRL(reg_id), 3777 reg_w, NULL); 3778 if (ret != I40E_SUCCESS) { 3779 PMD_DRV_LOG(ERR, 3780 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]", 3781 reg_id); 3782 return -EIO; 3783 } 3784 PMD_DRV_LOG(DEBUG, 3785 "Global register 0x%08x is changed with value 0x%08x", 3786 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w); 3787 3788 return 0; 3789 } 3790 3791 static int 3792 i40e_vlan_tpid_set(struct rte_eth_dev *dev, 3793 enum rte_vlan_type vlan_type, 3794 uint16_t tpid) 3795 { 3796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3797 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3798 int qinq = dev->data->dev_conf.rxmode.offloads & 3799 DEV_RX_OFFLOAD_VLAN_EXTEND; 3800 int ret = 0; 3801 3802 if ((vlan_type != ETH_VLAN_TYPE_INNER && 3803 vlan_type != ETH_VLAN_TYPE_OUTER) || 3804 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) { 3805 PMD_DRV_LOG(ERR, 3806 "Unsupported vlan type."); 3807 return -EINVAL; 3808 } 3809 3810 if (pf->support_multi_driver) { 3811 PMD_DRV_LOG(ERR, "Setting TPID is not supported."); 3812 return -ENOTSUP; 3813 } 3814 3815 /* 802.1ad frames ability is added in NVM API 1.7*/ 3816 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 3817 if (qinq) { 3818 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3819 hw->first_tag = rte_cpu_to_le_16(tpid); 3820 else if (vlan_type == ETH_VLAN_TYPE_INNER) 3821 hw->second_tag = rte_cpu_to_le_16(tpid); 3822 } else { 3823 if (vlan_type == ETH_VLAN_TYPE_OUTER) 3824 hw->second_tag = rte_cpu_to_le_16(tpid); 3825 } 3826 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL); 3827 if (ret != I40E_SUCCESS) { 3828 PMD_DRV_LOG(ERR, 3829 "Set switch config failed aq_err: %d", 3830 hw->aq.asq_last_status); 3831 ret = -EIO; 3832 } 3833 } else 3834 /* If NVM API < 1.7, keep the register setting */ 3835 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type, 3836 tpid, qinq); 3837 3838 return ret; 3839 } 3840 3841 static int 3842 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) 3843 { 3844 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3845 struct i40e_vsi *vsi = pf->main_vsi; 3846 struct rte_eth_rxmode *rxmode; 3847 3848 rxmode = &dev->data->dev_conf.rxmode; 3849 if (mask & ETH_VLAN_FILTER_MASK) { 3850 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 3851 i40e_vsi_config_vlan_filter(vsi, TRUE); 3852 else 3853 i40e_vsi_config_vlan_filter(vsi, FALSE); 3854 } 3855 3856 if (mask & ETH_VLAN_STRIP_MASK) { 3857 /* Enable or disable VLAN stripping */ 3858 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 3859 i40e_vsi_config_vlan_stripping(vsi, TRUE); 3860 else 3861 i40e_vsi_config_vlan_stripping(vsi, FALSE); 3862 } 3863 3864 if (mask & ETH_VLAN_EXTEND_MASK) { 3865 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) { 3866 i40e_vsi_config_double_vlan(vsi, TRUE); 3867 /* Set global registers with default ethertype. */ 3868 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 3869 RTE_ETHER_TYPE_VLAN); 3870 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, 3871 RTE_ETHER_TYPE_VLAN); 3872 } 3873 else 3874 i40e_vsi_config_double_vlan(vsi, FALSE); 3875 } 3876 3877 return 0; 3878 } 3879 3880 static void 3881 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev, 3882 __rte_unused uint16_t queue, 3883 __rte_unused int on) 3884 { 3885 PMD_INIT_FUNC_TRACE(); 3886 } 3887 3888 static int 3889 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 3890 { 3891 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3892 struct i40e_vsi *vsi = pf->main_vsi; 3893 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi); 3894 struct i40e_vsi_vlan_pvid_info info; 3895 3896 memset(&info, 0, sizeof(info)); 3897 info.on = on; 3898 if (info.on) 3899 info.config.pvid = pvid; 3900 else { 3901 info.config.reject.tagged = 3902 data->dev_conf.txmode.hw_vlan_reject_tagged; 3903 info.config.reject.untagged = 3904 data->dev_conf.txmode.hw_vlan_reject_untagged; 3905 } 3906 3907 return i40e_vsi_vlan_pvid_set(vsi, &info); 3908 } 3909 3910 static int 3911 i40e_dev_led_on(struct rte_eth_dev *dev) 3912 { 3913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3914 uint32_t mode = i40e_led_get(hw); 3915 3916 if (mode == 0) 3917 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */ 3918 3919 return 0; 3920 } 3921 3922 static int 3923 i40e_dev_led_off(struct rte_eth_dev *dev) 3924 { 3925 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3926 uint32_t mode = i40e_led_get(hw); 3927 3928 if (mode != 0) 3929 i40e_led_set(hw, 0, false); 3930 3931 return 0; 3932 } 3933 3934 static int 3935 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3936 { 3937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3939 3940 fc_conf->pause_time = pf->fc_conf.pause_time; 3941 3942 /* read out from register, in case they are modified by other port */ 3943 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = 3944 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT; 3945 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = 3946 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT; 3947 3948 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]; 3949 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]; 3950 3951 /* Return current mode according to actual setting*/ 3952 switch (hw->fc.current_mode) { 3953 case I40E_FC_FULL: 3954 fc_conf->mode = RTE_FC_FULL; 3955 break; 3956 case I40E_FC_TX_PAUSE: 3957 fc_conf->mode = RTE_FC_TX_PAUSE; 3958 break; 3959 case I40E_FC_RX_PAUSE: 3960 fc_conf->mode = RTE_FC_RX_PAUSE; 3961 break; 3962 case I40E_FC_NONE: 3963 default: 3964 fc_conf->mode = RTE_FC_NONE; 3965 }; 3966 3967 return 0; 3968 } 3969 3970 static int 3971 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3972 { 3973 uint32_t mflcn_reg, fctrl_reg, reg; 3974 uint32_t max_high_water; 3975 uint8_t i, aq_failure; 3976 int err; 3977 struct i40e_hw *hw; 3978 struct i40e_pf *pf; 3979 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = { 3980 [RTE_FC_NONE] = I40E_FC_NONE, 3981 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE, 3982 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE, 3983 [RTE_FC_FULL] = I40E_FC_FULL 3984 }; 3985 3986 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */ 3987 3988 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT; 3989 if ((fc_conf->high_water > max_high_water) || 3990 (fc_conf->high_water < fc_conf->low_water)) { 3991 PMD_INIT_LOG(ERR, 3992 "Invalid high/low water setup value in KB, High_water must be <= %d.", 3993 max_high_water); 3994 return -EINVAL; 3995 } 3996 3997 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3998 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3999 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode]; 4000 4001 pf->fc_conf.pause_time = fc_conf->pause_time; 4002 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water; 4003 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water; 4004 4005 PMD_INIT_FUNC_TRACE(); 4006 4007 /* All the link flow control related enable/disable register 4008 * configuration is handle by the F/W 4009 */ 4010 err = i40e_set_fc(hw, &aq_failure, true); 4011 if (err < 0) 4012 return -ENOSYS; 4013 4014 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { 4015 /* Configure flow control refresh threshold, 4016 * the value for stat_tx_pause_refresh_timer[8] 4017 * is used for global pause operation. 4018 */ 4019 4020 I40E_WRITE_REG(hw, 4021 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8), 4022 pf->fc_conf.pause_time); 4023 4024 /* configure the timer value included in transmitted pause 4025 * frame, 4026 * the value for stat_tx_pause_quanta[8] is used for global 4027 * pause operation 4028 */ 4029 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8), 4030 pf->fc_conf.pause_time); 4031 4032 fctrl_reg = I40E_READ_REG(hw, 4033 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL); 4034 4035 if (fc_conf->mac_ctrl_frame_fwd != 0) 4036 fctrl_reg |= I40E_PRTMAC_FWD_CTRL; 4037 else 4038 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL; 4039 4040 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL, 4041 fctrl_reg); 4042 } else { 4043 /* Configure pause time (2 TCs per register) */ 4044 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001; 4045 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++) 4046 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg); 4047 4048 /* Configure flow control refresh threshold value */ 4049 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV, 4050 pf->fc_conf.pause_time / 2); 4051 4052 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); 4053 4054 /* set or clear MFLCN.PMCF & MFLCN.DPF bits 4055 *depending on configuration 4056 */ 4057 if (fc_conf->mac_ctrl_frame_fwd != 0) { 4058 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK; 4059 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK; 4060 } else { 4061 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK; 4062 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK; 4063 } 4064 4065 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg); 4066 } 4067 4068 if (!pf->support_multi_driver) { 4069 /* config water marker both based on the packets and bytes */ 4070 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW, 4071 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] 4072 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE); 4073 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW, 4074 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] 4075 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE); 4076 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW, 4077 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] 4078 << I40E_KILOSHIFT); 4079 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW, 4080 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] 4081 << I40E_KILOSHIFT); 4082 } else { 4083 PMD_DRV_LOG(ERR, 4084 "Water marker configuration is not supported."); 4085 } 4086 4087 I40E_WRITE_FLUSH(hw); 4088 4089 return 0; 4090 } 4091 4092 static int 4093 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev, 4094 __rte_unused struct rte_eth_pfc_conf *pfc_conf) 4095 { 4096 PMD_INIT_FUNC_TRACE(); 4097 4098 return -ENOSYS; 4099 } 4100 4101 /* Add a MAC address, and update filters */ 4102 static int 4103 i40e_macaddr_add(struct rte_eth_dev *dev, 4104 struct rte_ether_addr *mac_addr, 4105 __rte_unused uint32_t index, 4106 uint32_t pool) 4107 { 4108 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4109 struct i40e_mac_filter_info mac_filter; 4110 struct i40e_vsi *vsi; 4111 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 4112 int ret; 4113 4114 /* If VMDQ not enabled or configured, return */ 4115 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) || 4116 !pf->nb_cfg_vmdq_vsi)) { 4117 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u", 4118 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled", 4119 pool); 4120 return -ENOTSUP; 4121 } 4122 4123 if (pool > pf->nb_cfg_vmdq_vsi) { 4124 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u", 4125 pool, pf->nb_cfg_vmdq_vsi); 4126 return -EINVAL; 4127 } 4128 4129 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN); 4130 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 4131 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 4132 else 4133 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH; 4134 4135 if (pool == 0) 4136 vsi = pf->main_vsi; 4137 else 4138 vsi = pf->vmdq[pool - 1].vsi; 4139 4140 ret = i40e_vsi_add_mac(vsi, &mac_filter); 4141 if (ret != I40E_SUCCESS) { 4142 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter"); 4143 return -ENODEV; 4144 } 4145 return 0; 4146 } 4147 4148 /* Remove a MAC address, and update filters */ 4149 static void 4150 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 4151 { 4152 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4153 struct i40e_vsi *vsi; 4154 struct rte_eth_dev_data *data = dev->data; 4155 struct rte_ether_addr *macaddr; 4156 int ret; 4157 uint32_t i; 4158 uint64_t pool_sel; 4159 4160 macaddr = &(data->mac_addrs[index]); 4161 4162 pool_sel = dev->data->mac_pool_sel[index]; 4163 4164 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) { 4165 if (pool_sel & (1ULL << i)) { 4166 if (i == 0) 4167 vsi = pf->main_vsi; 4168 else { 4169 /* No VMDQ pool enabled or configured */ 4170 if (!(pf->flags & I40E_FLAG_VMDQ) || 4171 (i > pf->nb_cfg_vmdq_vsi)) { 4172 PMD_DRV_LOG(ERR, 4173 "No VMDQ pool enabled/configured"); 4174 return; 4175 } 4176 vsi = pf->vmdq[i - 1].vsi; 4177 } 4178 ret = i40e_vsi_delete_mac(vsi, macaddr); 4179 4180 if (ret) { 4181 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter"); 4182 return; 4183 } 4184 } 4185 } 4186 } 4187 4188 /* Set perfect match or hash match of MAC and VLAN for a VF */ 4189 static int 4190 i40e_vf_mac_filter_set(struct i40e_pf *pf, 4191 struct rte_eth_mac_filter *filter, 4192 bool add) 4193 { 4194 struct i40e_hw *hw; 4195 struct i40e_mac_filter_info mac_filter; 4196 struct rte_ether_addr old_mac; 4197 struct rte_ether_addr *new_mac; 4198 struct i40e_pf_vf *vf = NULL; 4199 uint16_t vf_id; 4200 int ret; 4201 4202 if (pf == NULL) { 4203 PMD_DRV_LOG(ERR, "Invalid PF argument."); 4204 return -EINVAL; 4205 } 4206 hw = I40E_PF_TO_HW(pf); 4207 4208 if (filter == NULL) { 4209 PMD_DRV_LOG(ERR, "Invalid mac filter argument."); 4210 return -EINVAL; 4211 } 4212 4213 new_mac = &filter->mac_addr; 4214 4215 if (rte_is_zero_ether_addr(new_mac)) { 4216 PMD_DRV_LOG(ERR, "Invalid ethernet address."); 4217 return -EINVAL; 4218 } 4219 4220 vf_id = filter->dst_id; 4221 4222 if (vf_id > pf->vf_num - 1 || !pf->vfs) { 4223 PMD_DRV_LOG(ERR, "Invalid argument."); 4224 return -EINVAL; 4225 } 4226 vf = &pf->vfs[vf_id]; 4227 4228 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) { 4229 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address."); 4230 return -EINVAL; 4231 } 4232 4233 if (add) { 4234 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN); 4235 rte_memcpy(hw->mac.addr, new_mac->addr_bytes, 4236 RTE_ETHER_ADDR_LEN); 4237 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr, 4238 RTE_ETHER_ADDR_LEN); 4239 4240 mac_filter.filter_type = filter->filter_type; 4241 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter); 4242 if (ret != I40E_SUCCESS) { 4243 PMD_DRV_LOG(ERR, "Failed to add MAC filter."); 4244 return -1; 4245 } 4246 rte_ether_addr_copy(new_mac, &pf->dev_addr); 4247 } else { 4248 rte_memcpy(hw->mac.addr, hw->mac.perm_addr, 4249 RTE_ETHER_ADDR_LEN); 4250 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr); 4251 if (ret != I40E_SUCCESS) { 4252 PMD_DRV_LOG(ERR, "Failed to delete MAC filter."); 4253 return -1; 4254 } 4255 4256 /* Clear device address as it has been removed */ 4257 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac)) 4258 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr)); 4259 } 4260 4261 return 0; 4262 } 4263 4264 /* MAC filter handle */ 4265 static int 4266 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op, 4267 void *arg) 4268 { 4269 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4270 struct rte_eth_mac_filter *filter; 4271 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4272 int ret = I40E_NOT_SUPPORTED; 4273 4274 filter = (struct rte_eth_mac_filter *)(arg); 4275 4276 switch (filter_op) { 4277 case RTE_ETH_FILTER_NOP: 4278 ret = I40E_SUCCESS; 4279 break; 4280 case RTE_ETH_FILTER_ADD: 4281 i40e_pf_disable_irq0(hw); 4282 if (filter->is_vf) 4283 ret = i40e_vf_mac_filter_set(pf, filter, 1); 4284 i40e_pf_enable_irq0(hw); 4285 break; 4286 case RTE_ETH_FILTER_DELETE: 4287 i40e_pf_disable_irq0(hw); 4288 if (filter->is_vf) 4289 ret = i40e_vf_mac_filter_set(pf, filter, 0); 4290 i40e_pf_enable_irq0(hw); 4291 break; 4292 default: 4293 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 4294 ret = I40E_ERR_PARAM; 4295 break; 4296 } 4297 4298 return ret; 4299 } 4300 4301 static int 4302 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4303 { 4304 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 4305 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 4306 uint32_t reg; 4307 int ret; 4308 4309 if (!lut) 4310 return -EINVAL; 4311 4312 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 4313 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, 4314 vsi->type != I40E_VSI_SRIOV, 4315 lut, lut_size); 4316 if (ret) { 4317 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 4318 return ret; 4319 } 4320 } else { 4321 uint32_t *lut_dw = (uint32_t *)lut; 4322 uint16_t i, lut_size_dw = lut_size / 4; 4323 4324 if (vsi->type == I40E_VSI_SRIOV) { 4325 for (i = 0; i <= lut_size_dw; i++) { 4326 reg = I40E_VFQF_HLUT1(i, vsi->user_param); 4327 lut_dw[i] = i40e_read_rx_ctl(hw, reg); 4328 } 4329 } else { 4330 for (i = 0; i < lut_size_dw; i++) 4331 lut_dw[i] = I40E_READ_REG(hw, 4332 I40E_PFQF_HLUT(i)); 4333 } 4334 } 4335 4336 return 0; 4337 } 4338 4339 int 4340 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 4341 { 4342 struct i40e_pf *pf; 4343 struct i40e_hw *hw; 4344 int ret; 4345 4346 if (!vsi || !lut) 4347 return -EINVAL; 4348 4349 pf = I40E_VSI_TO_PF(vsi); 4350 hw = I40E_VSI_TO_HW(vsi); 4351 4352 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 4353 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, 4354 vsi->type != I40E_VSI_SRIOV, 4355 lut, lut_size); 4356 if (ret) { 4357 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 4358 return ret; 4359 } 4360 } else { 4361 uint32_t *lut_dw = (uint32_t *)lut; 4362 uint16_t i, lut_size_dw = lut_size / 4; 4363 4364 if (vsi->type == I40E_VSI_SRIOV) { 4365 for (i = 0; i < lut_size_dw; i++) 4366 I40E_WRITE_REG( 4367 hw, 4368 I40E_VFQF_HLUT1(i, vsi->user_param), 4369 lut_dw[i]); 4370 } else { 4371 for (i = 0; i < lut_size_dw; i++) 4372 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), 4373 lut_dw[i]); 4374 } 4375 I40E_WRITE_FLUSH(hw); 4376 } 4377 4378 return 0; 4379 } 4380 4381 static int 4382 i40e_dev_rss_reta_update(struct rte_eth_dev *dev, 4383 struct rte_eth_rss_reta_entry64 *reta_conf, 4384 uint16_t reta_size) 4385 { 4386 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4387 uint16_t i, lut_size = pf->hash_lut_size; 4388 uint16_t idx, shift; 4389 uint8_t *lut; 4390 int ret; 4391 4392 if (reta_size != lut_size || 4393 reta_size > ETH_RSS_RETA_SIZE_512) { 4394 PMD_DRV_LOG(ERR, 4395 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)", 4396 reta_size, lut_size); 4397 return -EINVAL; 4398 } 4399 4400 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 4401 if (!lut) { 4402 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4403 return -ENOMEM; 4404 } 4405 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size); 4406 if (ret) 4407 goto out; 4408 for (i = 0; i < reta_size; i++) { 4409 idx = i / RTE_RETA_GROUP_SIZE; 4410 shift = i % RTE_RETA_GROUP_SIZE; 4411 if (reta_conf[idx].mask & (1ULL << shift)) 4412 lut[i] = reta_conf[idx].reta[shift]; 4413 } 4414 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size); 4415 4416 pf->adapter->rss_reta_updated = 1; 4417 4418 out: 4419 rte_free(lut); 4420 4421 return ret; 4422 } 4423 4424 static int 4425 i40e_dev_rss_reta_query(struct rte_eth_dev *dev, 4426 struct rte_eth_rss_reta_entry64 *reta_conf, 4427 uint16_t reta_size) 4428 { 4429 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4430 uint16_t i, lut_size = pf->hash_lut_size; 4431 uint16_t idx, shift; 4432 uint8_t *lut; 4433 int ret; 4434 4435 if (reta_size != lut_size || 4436 reta_size > ETH_RSS_RETA_SIZE_512) { 4437 PMD_DRV_LOG(ERR, 4438 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)", 4439 reta_size, lut_size); 4440 return -EINVAL; 4441 } 4442 4443 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 4444 if (!lut) { 4445 PMD_DRV_LOG(ERR, "No memory can be allocated"); 4446 return -ENOMEM; 4447 } 4448 4449 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size); 4450 if (ret) 4451 goto out; 4452 for (i = 0; i < reta_size; i++) { 4453 idx = i / RTE_RETA_GROUP_SIZE; 4454 shift = i % RTE_RETA_GROUP_SIZE; 4455 if (reta_conf[idx].mask & (1ULL << shift)) 4456 reta_conf[idx].reta[shift] = lut[i]; 4457 } 4458 4459 out: 4460 rte_free(lut); 4461 4462 return ret; 4463 } 4464 4465 /** 4466 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver) 4467 * @hw: pointer to the HW structure 4468 * @mem: pointer to mem struct to fill out 4469 * @size: size of memory requested 4470 * @alignment: what to align the allocation to 4471 **/ 4472 enum i40e_status_code 4473 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4474 struct i40e_dma_mem *mem, 4475 u64 size, 4476 u32 alignment) 4477 { 4478 const struct rte_memzone *mz = NULL; 4479 char z_name[RTE_MEMZONE_NAMESIZE]; 4480 4481 if (!mem) 4482 return I40E_ERR_PARAM; 4483 4484 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand()); 4485 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 4486 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M); 4487 if (!mz) 4488 return I40E_ERR_NO_MEMORY; 4489 4490 mem->size = size; 4491 mem->va = mz->addr; 4492 mem->pa = mz->iova; 4493 mem->zone = (const void *)mz; 4494 PMD_DRV_LOG(DEBUG, 4495 "memzone %s allocated with physical address: %"PRIu64, 4496 mz->name, mem->pa); 4497 4498 return I40E_SUCCESS; 4499 } 4500 4501 /** 4502 * i40e_free_dma_mem_d - specific memory free for shared code (base driver) 4503 * @hw: pointer to the HW structure 4504 * @mem: ptr to mem struct to free 4505 **/ 4506 enum i40e_status_code 4507 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4508 struct i40e_dma_mem *mem) 4509 { 4510 if (!mem) 4511 return I40E_ERR_PARAM; 4512 4513 PMD_DRV_LOG(DEBUG, 4514 "memzone %s to be freed with physical address: %"PRIu64, 4515 ((const struct rte_memzone *)mem->zone)->name, mem->pa); 4516 rte_memzone_free((const struct rte_memzone *)mem->zone); 4517 mem->zone = NULL; 4518 mem->va = NULL; 4519 mem->pa = (u64)0; 4520 4521 return I40E_SUCCESS; 4522 } 4523 4524 /** 4525 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver) 4526 * @hw: pointer to the HW structure 4527 * @mem: pointer to mem struct to fill out 4528 * @size: size of memory requested 4529 **/ 4530 enum i40e_status_code 4531 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4532 struct i40e_virt_mem *mem, 4533 u32 size) 4534 { 4535 if (!mem) 4536 return I40E_ERR_PARAM; 4537 4538 mem->size = size; 4539 mem->va = rte_zmalloc("i40e", size, 0); 4540 4541 if (mem->va) 4542 return I40E_SUCCESS; 4543 else 4544 return I40E_ERR_NO_MEMORY; 4545 } 4546 4547 /** 4548 * i40e_free_virt_mem_d - specific memory free for shared code (base driver) 4549 * @hw: pointer to the HW structure 4550 * @mem: pointer to mem struct to free 4551 **/ 4552 enum i40e_status_code 4553 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw, 4554 struct i40e_virt_mem *mem) 4555 { 4556 if (!mem) 4557 return I40E_ERR_PARAM; 4558 4559 rte_free(mem->va); 4560 mem->va = NULL; 4561 4562 return I40E_SUCCESS; 4563 } 4564 4565 void 4566 i40e_init_spinlock_d(struct i40e_spinlock *sp) 4567 { 4568 rte_spinlock_init(&sp->spinlock); 4569 } 4570 4571 void 4572 i40e_acquire_spinlock_d(struct i40e_spinlock *sp) 4573 { 4574 rte_spinlock_lock(&sp->spinlock); 4575 } 4576 4577 void 4578 i40e_release_spinlock_d(struct i40e_spinlock *sp) 4579 { 4580 rte_spinlock_unlock(&sp->spinlock); 4581 } 4582 4583 void 4584 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp) 4585 { 4586 return; 4587 } 4588 4589 /** 4590 * Get the hardware capabilities, which will be parsed 4591 * and saved into struct i40e_hw. 4592 */ 4593 static int 4594 i40e_get_cap(struct i40e_hw *hw) 4595 { 4596 struct i40e_aqc_list_capabilities_element_resp *buf; 4597 uint16_t len, size = 0; 4598 int ret; 4599 4600 /* Calculate a huge enough buff for saving response data temporarily */ 4601 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) * 4602 I40E_MAX_CAP_ELE_NUM; 4603 buf = rte_zmalloc("i40e", len, 0); 4604 if (!buf) { 4605 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 4606 return I40E_ERR_NO_MEMORY; 4607 } 4608 4609 /* Get, parse the capabilities and save it to hw */ 4610 ret = i40e_aq_discover_capabilities(hw, buf, len, &size, 4611 i40e_aqc_opc_list_func_capabilities, NULL); 4612 if (ret != I40E_SUCCESS) 4613 PMD_DRV_LOG(ERR, "Failed to discover capabilities"); 4614 4615 /* Free the temporary buffer after being used */ 4616 rte_free(buf); 4617 4618 return ret; 4619 } 4620 4621 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 4622 4623 static int i40e_pf_parse_vf_queue_number_handler(const char *key, 4624 const char *value, 4625 void *opaque) 4626 { 4627 struct i40e_pf *pf; 4628 unsigned long num; 4629 char *end; 4630 4631 pf = (struct i40e_pf *)opaque; 4632 RTE_SET_USED(key); 4633 4634 errno = 0; 4635 num = strtoul(value, &end, 0); 4636 if (errno != 0 || end == value || *end != 0) { 4637 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is " 4638 "kept the value = %hu", value, pf->vf_nb_qp_max); 4639 return -(EINVAL); 4640 } 4641 4642 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num)) 4643 pf->vf_nb_qp_max = (uint16_t)num; 4644 else 4645 /* here return 0 to make next valid same argument work */ 4646 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be " 4647 "power of 2 and equal or less than 16 !, Now it is " 4648 "kept the value = %hu", num, pf->vf_nb_qp_max); 4649 4650 return 0; 4651 } 4652 4653 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev) 4654 { 4655 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4656 struct rte_kvargs *kvlist; 4657 int kvargs_count; 4658 4659 /* set default queue number per VF as 4 */ 4660 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF; 4661 4662 if (dev->device->devargs == NULL) 4663 return 0; 4664 4665 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 4666 if (kvlist == NULL) 4667 return -(EINVAL); 4668 4669 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG); 4670 if (!kvargs_count) { 4671 rte_kvargs_free(kvlist); 4672 return 0; 4673 } 4674 4675 if (kvargs_count > 1) 4676 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only " 4677 "the first invalid or last valid one is used !", 4678 ETH_I40E_QUEUE_NUM_PER_VF_ARG); 4679 4680 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG, 4681 i40e_pf_parse_vf_queue_number_handler, pf); 4682 4683 rte_kvargs_free(kvlist); 4684 4685 return 0; 4686 } 4687 4688 static int 4689 i40e_pf_parameter_init(struct rte_eth_dev *dev) 4690 { 4691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4692 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4693 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4694 uint16_t qp_count = 0, vsi_count = 0; 4695 4696 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) { 4697 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV"); 4698 return -EINVAL; 4699 } 4700 4701 i40e_pf_config_vf_rxq_number(dev); 4702 4703 /* Add the parameter init for LFC */ 4704 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME; 4705 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER; 4706 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER; 4707 4708 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED; 4709 pf->max_num_vsi = hw->func_caps.num_vsis; 4710 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF; 4711 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 4712 4713 /* FDir queue/VSI allocation */ 4714 pf->fdir_qp_offset = 0; 4715 if (hw->func_caps.fd) { 4716 pf->flags |= I40E_FLAG_FDIR; 4717 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR; 4718 } else { 4719 pf->fdir_nb_qps = 0; 4720 } 4721 qp_count += pf->fdir_nb_qps; 4722 vsi_count += 1; 4723 4724 /* LAN queue/VSI allocation */ 4725 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps; 4726 if (!hw->func_caps.rss) { 4727 pf->lan_nb_qps = 1; 4728 } else { 4729 pf->flags |= I40E_FLAG_RSS; 4730 if (hw->mac.type == I40E_MAC_X722) 4731 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE; 4732 pf->lan_nb_qps = pf->lan_nb_qp_max; 4733 } 4734 qp_count += pf->lan_nb_qps; 4735 vsi_count += 1; 4736 4737 /* VF queue/VSI allocation */ 4738 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps; 4739 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) { 4740 pf->flags |= I40E_FLAG_SRIOV; 4741 pf->vf_nb_qps = pf->vf_nb_qp_max; 4742 pf->vf_num = pci_dev->max_vfs; 4743 PMD_DRV_LOG(DEBUG, 4744 "%u VF VSIs, %u queues per VF VSI, in total %u queues", 4745 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num); 4746 } else { 4747 pf->vf_nb_qps = 0; 4748 pf->vf_num = 0; 4749 } 4750 qp_count += pf->vf_nb_qps * pf->vf_num; 4751 vsi_count += pf->vf_num; 4752 4753 /* VMDq queue/VSI allocation */ 4754 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num; 4755 pf->vmdq_nb_qps = 0; 4756 pf->max_nb_vmdq_vsi = 0; 4757 if (hw->func_caps.vmdq) { 4758 if (qp_count < hw->func_caps.num_tx_qp && 4759 vsi_count < hw->func_caps.num_vsis) { 4760 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp - 4761 qp_count) / pf->vmdq_nb_qp_max; 4762 4763 /* Limit the maximum number of VMDq vsi to the maximum 4764 * ethdev can support 4765 */ 4766 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi, 4767 hw->func_caps.num_vsis - vsi_count); 4768 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi, 4769 ETH_64_POOLS); 4770 if (pf->max_nb_vmdq_vsi) { 4771 pf->flags |= I40E_FLAG_VMDQ; 4772 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max; 4773 PMD_DRV_LOG(DEBUG, 4774 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues", 4775 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps, 4776 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi); 4777 } else { 4778 PMD_DRV_LOG(INFO, 4779 "No enough queues left for VMDq"); 4780 } 4781 } else { 4782 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq"); 4783 } 4784 } 4785 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi; 4786 vsi_count += pf->max_nb_vmdq_vsi; 4787 4788 if (hw->func_caps.dcb) 4789 pf->flags |= I40E_FLAG_DCB; 4790 4791 if (qp_count > hw->func_caps.num_tx_qp) { 4792 PMD_DRV_LOG(ERR, 4793 "Failed to allocate %u queues, which exceeds the hardware maximum %u", 4794 qp_count, hw->func_caps.num_tx_qp); 4795 return -EINVAL; 4796 } 4797 if (vsi_count > hw->func_caps.num_vsis) { 4798 PMD_DRV_LOG(ERR, 4799 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u", 4800 vsi_count, hw->func_caps.num_vsis); 4801 return -EINVAL; 4802 } 4803 4804 return 0; 4805 } 4806 4807 static int 4808 i40e_pf_get_switch_config(struct i40e_pf *pf) 4809 { 4810 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4811 struct i40e_aqc_get_switch_config_resp *switch_config; 4812 struct i40e_aqc_switch_config_element_resp *element; 4813 uint16_t start_seid = 0, num_reported; 4814 int ret; 4815 4816 switch_config = (struct i40e_aqc_get_switch_config_resp *)\ 4817 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0); 4818 if (!switch_config) { 4819 PMD_DRV_LOG(ERR, "Failed to allocated memory"); 4820 return -ENOMEM; 4821 } 4822 4823 /* Get the switch configurations */ 4824 ret = i40e_aq_get_switch_config(hw, switch_config, 4825 I40E_AQ_LARGE_BUF, &start_seid, NULL); 4826 if (ret != I40E_SUCCESS) { 4827 PMD_DRV_LOG(ERR, "Failed to get switch configurations"); 4828 goto fail; 4829 } 4830 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported); 4831 if (num_reported != 1) { /* The number should be 1 */ 4832 PMD_DRV_LOG(ERR, "Wrong number of switch config reported"); 4833 goto fail; 4834 } 4835 4836 /* Parse the switch configuration elements */ 4837 element = &(switch_config->element[0]); 4838 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) { 4839 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid); 4840 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid); 4841 } else 4842 PMD_DRV_LOG(INFO, "Unknown element type"); 4843 4844 fail: 4845 rte_free(switch_config); 4846 4847 return ret; 4848 } 4849 4850 static int 4851 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base, 4852 uint32_t num) 4853 { 4854 struct pool_entry *entry; 4855 4856 if (pool == NULL || num == 0) 4857 return -EINVAL; 4858 4859 entry = rte_zmalloc("i40e", sizeof(*entry), 0); 4860 if (entry == NULL) { 4861 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool"); 4862 return -ENOMEM; 4863 } 4864 4865 /* queue heap initialize */ 4866 pool->num_free = num; 4867 pool->num_alloc = 0; 4868 pool->base = base; 4869 LIST_INIT(&pool->alloc_list); 4870 LIST_INIT(&pool->free_list); 4871 4872 /* Initialize element */ 4873 entry->base = 0; 4874 entry->len = num; 4875 4876 LIST_INSERT_HEAD(&pool->free_list, entry, next); 4877 return 0; 4878 } 4879 4880 static void 4881 i40e_res_pool_destroy(struct i40e_res_pool_info *pool) 4882 { 4883 struct pool_entry *entry, *next_entry; 4884 4885 if (pool == NULL) 4886 return; 4887 4888 for (entry = LIST_FIRST(&pool->alloc_list); 4889 entry && (next_entry = LIST_NEXT(entry, next), 1); 4890 entry = next_entry) { 4891 LIST_REMOVE(entry, next); 4892 rte_free(entry); 4893 } 4894 4895 for (entry = LIST_FIRST(&pool->free_list); 4896 entry && (next_entry = LIST_NEXT(entry, next), 1); 4897 entry = next_entry) { 4898 LIST_REMOVE(entry, next); 4899 rte_free(entry); 4900 } 4901 4902 pool->num_free = 0; 4903 pool->num_alloc = 0; 4904 pool->base = 0; 4905 LIST_INIT(&pool->alloc_list); 4906 LIST_INIT(&pool->free_list); 4907 } 4908 4909 static int 4910 i40e_res_pool_free(struct i40e_res_pool_info *pool, 4911 uint32_t base) 4912 { 4913 struct pool_entry *entry, *next, *prev, *valid_entry = NULL; 4914 uint32_t pool_offset; 4915 int insert; 4916 4917 if (pool == NULL) { 4918 PMD_DRV_LOG(ERR, "Invalid parameter"); 4919 return -EINVAL; 4920 } 4921 4922 pool_offset = base - pool->base; 4923 /* Lookup in alloc list */ 4924 LIST_FOREACH(entry, &pool->alloc_list, next) { 4925 if (entry->base == pool_offset) { 4926 valid_entry = entry; 4927 LIST_REMOVE(entry, next); 4928 break; 4929 } 4930 } 4931 4932 /* Not find, return */ 4933 if (valid_entry == NULL) { 4934 PMD_DRV_LOG(ERR, "Failed to find entry"); 4935 return -EINVAL; 4936 } 4937 4938 /** 4939 * Found it, move it to free list and try to merge. 4940 * In order to make merge easier, always sort it by qbase. 4941 * Find adjacent prev and last entries. 4942 */ 4943 prev = next = NULL; 4944 LIST_FOREACH(entry, &pool->free_list, next) { 4945 if (entry->base > valid_entry->base) { 4946 next = entry; 4947 break; 4948 } 4949 prev = entry; 4950 } 4951 4952 insert = 0; 4953 /* Try to merge with next one*/ 4954 if (next != NULL) { 4955 /* Merge with next one */ 4956 if (valid_entry->base + valid_entry->len == next->base) { 4957 next->base = valid_entry->base; 4958 next->len += valid_entry->len; 4959 rte_free(valid_entry); 4960 valid_entry = next; 4961 insert = 1; 4962 } 4963 } 4964 4965 if (prev != NULL) { 4966 /* Merge with previous one */ 4967 if (prev->base + prev->len == valid_entry->base) { 4968 prev->len += valid_entry->len; 4969 /* If it merge with next one, remove next node */ 4970 if (insert == 1) { 4971 LIST_REMOVE(valid_entry, next); 4972 rte_free(valid_entry); 4973 } else { 4974 rte_free(valid_entry); 4975 insert = 1; 4976 } 4977 } 4978 } 4979 4980 /* Not find any entry to merge, insert */ 4981 if (insert == 0) { 4982 if (prev != NULL) 4983 LIST_INSERT_AFTER(prev, valid_entry, next); 4984 else if (next != NULL) 4985 LIST_INSERT_BEFORE(next, valid_entry, next); 4986 else /* It's empty list, insert to head */ 4987 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next); 4988 } 4989 4990 pool->num_free += valid_entry->len; 4991 pool->num_alloc -= valid_entry->len; 4992 4993 return 0; 4994 } 4995 4996 static int 4997 i40e_res_pool_alloc(struct i40e_res_pool_info *pool, 4998 uint16_t num) 4999 { 5000 struct pool_entry *entry, *valid_entry; 5001 5002 if (pool == NULL || num == 0) { 5003 PMD_DRV_LOG(ERR, "Invalid parameter"); 5004 return -EINVAL; 5005 } 5006 5007 if (pool->num_free < num) { 5008 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u", 5009 num, pool->num_free); 5010 return -ENOMEM; 5011 } 5012 5013 valid_entry = NULL; 5014 /* Lookup in free list and find most fit one */ 5015 LIST_FOREACH(entry, &pool->free_list, next) { 5016 if (entry->len >= num) { 5017 /* Find best one */ 5018 if (entry->len == num) { 5019 valid_entry = entry; 5020 break; 5021 } 5022 if (valid_entry == NULL || valid_entry->len > entry->len) 5023 valid_entry = entry; 5024 } 5025 } 5026 5027 /* Not find one to satisfy the request, return */ 5028 if (valid_entry == NULL) { 5029 PMD_DRV_LOG(ERR, "No valid entry found"); 5030 return -ENOMEM; 5031 } 5032 /** 5033 * The entry have equal queue number as requested, 5034 * remove it from alloc_list. 5035 */ 5036 if (valid_entry->len == num) { 5037 LIST_REMOVE(valid_entry, next); 5038 } else { 5039 /** 5040 * The entry have more numbers than requested, 5041 * create a new entry for alloc_list and minus its 5042 * queue base and number in free_list. 5043 */ 5044 entry = rte_zmalloc("res_pool", sizeof(*entry), 0); 5045 if (entry == NULL) { 5046 PMD_DRV_LOG(ERR, 5047 "Failed to allocate memory for resource pool"); 5048 return -ENOMEM; 5049 } 5050 entry->base = valid_entry->base; 5051 entry->len = num; 5052 valid_entry->base += num; 5053 valid_entry->len -= num; 5054 valid_entry = entry; 5055 } 5056 5057 /* Insert it into alloc list, not sorted */ 5058 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 5059 5060 pool->num_free -= valid_entry->len; 5061 pool->num_alloc += valid_entry->len; 5062 5063 return valid_entry->base + pool->base; 5064 } 5065 5066 /** 5067 * bitmap_is_subset - Check whether src2 is subset of src1 5068 **/ 5069 static inline int 5070 bitmap_is_subset(uint8_t src1, uint8_t src2) 5071 { 5072 return !((src1 ^ src2) & src2); 5073 } 5074 5075 static enum i40e_status_code 5076 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap) 5077 { 5078 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5079 5080 /* If DCB is not supported, only default TC is supported */ 5081 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) { 5082 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported"); 5083 return I40E_NOT_SUPPORTED; 5084 } 5085 5086 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) { 5087 PMD_DRV_LOG(ERR, 5088 "Enabled TC map 0x%x not applicable to HW support 0x%x", 5089 hw->func_caps.enabled_tcmap, enabled_tcmap); 5090 return I40E_NOT_SUPPORTED; 5091 } 5092 return I40E_SUCCESS; 5093 } 5094 5095 int 5096 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, 5097 struct i40e_vsi_vlan_pvid_info *info) 5098 { 5099 struct i40e_hw *hw; 5100 struct i40e_vsi_context ctxt; 5101 uint8_t vlan_flags = 0; 5102 int ret; 5103 5104 if (vsi == NULL || info == NULL) { 5105 PMD_DRV_LOG(ERR, "invalid parameters"); 5106 return I40E_ERR_PARAM; 5107 } 5108 5109 if (info->on) { 5110 vsi->info.pvid = info->config.pvid; 5111 /** 5112 * If insert pvid is enabled, only tagged pkts are 5113 * allowed to be sent out. 5114 */ 5115 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID | 5116 I40E_AQ_VSI_PVLAN_MODE_TAGGED; 5117 } else { 5118 vsi->info.pvid = 0; 5119 if (info->config.reject.tagged == 0) 5120 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED; 5121 5122 if (info->config.reject.untagged == 0) 5123 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED; 5124 } 5125 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID | 5126 I40E_AQ_VSI_PVLAN_MODE_MASK); 5127 vsi->info.port_vlan_flags |= vlan_flags; 5128 vsi->info.valid_sections = 5129 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5130 memset(&ctxt, 0, sizeof(ctxt)); 5131 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 5132 ctxt.seid = vsi->seid; 5133 5134 hw = I40E_VSI_TO_HW(vsi); 5135 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5136 if (ret != I40E_SUCCESS) 5137 PMD_DRV_LOG(ERR, "Failed to update VSI params"); 5138 5139 return ret; 5140 } 5141 5142 static int 5143 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap) 5144 { 5145 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5146 int i, ret; 5147 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data; 5148 5149 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 5150 if (ret != I40E_SUCCESS) 5151 return ret; 5152 5153 if (!vsi->seid) { 5154 PMD_DRV_LOG(ERR, "seid not valid"); 5155 return -EINVAL; 5156 } 5157 5158 memset(&tc_bw_data, 0, sizeof(tc_bw_data)); 5159 tc_bw_data.tc_valid_bits = enabled_tcmap; 5160 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 5161 tc_bw_data.tc_bw_credits[i] = 5162 (enabled_tcmap & (1 << i)) ? 1 : 0; 5163 5164 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL); 5165 if (ret != I40E_SUCCESS) { 5166 PMD_DRV_LOG(ERR, "Failed to configure TC BW"); 5167 return ret; 5168 } 5169 5170 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles, 5171 sizeof(vsi->info.qs_handle)); 5172 return I40E_SUCCESS; 5173 } 5174 5175 static enum i40e_status_code 5176 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi, 5177 struct i40e_aqc_vsi_properties_data *info, 5178 uint8_t enabled_tcmap) 5179 { 5180 enum i40e_status_code ret; 5181 int i, total_tc = 0; 5182 uint16_t qpnum_per_tc, bsf, qp_idx; 5183 5184 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 5185 if (ret != I40E_SUCCESS) 5186 return ret; 5187 5188 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 5189 if (enabled_tcmap & (1 << i)) 5190 total_tc++; 5191 if (total_tc == 0) 5192 total_tc = 1; 5193 vsi->enabled_tc = enabled_tcmap; 5194 5195 /* Number of queues per enabled TC */ 5196 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc); 5197 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC); 5198 bsf = rte_bsf32(qpnum_per_tc); 5199 5200 /* Adjust the queue number to actual queues that can be applied */ 5201 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1)) 5202 vsi->nb_qps = qpnum_per_tc * total_tc; 5203 5204 /** 5205 * Configure TC and queue mapping parameters, for enabled TC, 5206 * allocate qpnum_per_tc queues to this traffic. For disabled TC, 5207 * default queue will serve it. 5208 */ 5209 qp_idx = 0; 5210 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 5211 if (vsi->enabled_tc & (1 << i)) { 5212 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx << 5213 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 5214 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 5215 qp_idx += qpnum_per_tc; 5216 } else 5217 info->tc_mapping[i] = 0; 5218 } 5219 5220 /* Associate queue number with VSI */ 5221 if (vsi->type == I40E_VSI_SRIOV) { 5222 info->mapping_flags |= 5223 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 5224 for (i = 0; i < vsi->nb_qps; i++) 5225 info->queue_mapping[i] = 5226 rte_cpu_to_le_16(vsi->base_queue + i); 5227 } else { 5228 info->mapping_flags |= 5229 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG); 5230 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 5231 } 5232 info->valid_sections |= 5233 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 5234 5235 return I40E_SUCCESS; 5236 } 5237 5238 static int 5239 i40e_veb_release(struct i40e_veb *veb) 5240 { 5241 struct i40e_vsi *vsi; 5242 struct i40e_hw *hw; 5243 5244 if (veb == NULL) 5245 return -EINVAL; 5246 5247 if (!TAILQ_EMPTY(&veb->head)) { 5248 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove"); 5249 return -EACCES; 5250 } 5251 /* associate_vsi field is NULL for floating VEB */ 5252 if (veb->associate_vsi != NULL) { 5253 vsi = veb->associate_vsi; 5254 hw = I40E_VSI_TO_HW(vsi); 5255 5256 vsi->uplink_seid = veb->uplink_seid; 5257 vsi->veb = NULL; 5258 } else { 5259 veb->associate_pf->main_vsi->floating_veb = NULL; 5260 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi); 5261 } 5262 5263 i40e_aq_delete_element(hw, veb->seid, NULL); 5264 rte_free(veb); 5265 return I40E_SUCCESS; 5266 } 5267 5268 /* Setup a veb */ 5269 static struct i40e_veb * 5270 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi) 5271 { 5272 struct i40e_veb *veb; 5273 int ret; 5274 struct i40e_hw *hw; 5275 5276 if (pf == NULL) { 5277 PMD_DRV_LOG(ERR, 5278 "veb setup failed, associated PF shouldn't null"); 5279 return NULL; 5280 } 5281 hw = I40E_PF_TO_HW(pf); 5282 5283 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0); 5284 if (!veb) { 5285 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb"); 5286 goto fail; 5287 } 5288 5289 veb->associate_vsi = vsi; 5290 veb->associate_pf = pf; 5291 TAILQ_INIT(&veb->head); 5292 veb->uplink_seid = vsi ? vsi->uplink_seid : 0; 5293 5294 /* create floating veb if vsi is NULL */ 5295 if (vsi != NULL) { 5296 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid, 5297 I40E_DEFAULT_TCMAP, false, 5298 &veb->seid, false, NULL); 5299 } else { 5300 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP, 5301 true, &veb->seid, false, NULL); 5302 } 5303 5304 if (ret != I40E_SUCCESS) { 5305 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d", 5306 hw->aq.asq_last_status); 5307 goto fail; 5308 } 5309 veb->enabled_tc = I40E_DEFAULT_TCMAP; 5310 5311 /* get statistics index */ 5312 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL, 5313 &veb->stats_idx, NULL, NULL, NULL); 5314 if (ret != I40E_SUCCESS) { 5315 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d", 5316 hw->aq.asq_last_status); 5317 goto fail; 5318 } 5319 /* Get VEB bandwidth, to be implemented */ 5320 /* Now associated vsi binding to the VEB, set uplink to this VEB */ 5321 if (vsi) 5322 vsi->uplink_seid = veb->seid; 5323 5324 return veb; 5325 fail: 5326 rte_free(veb); 5327 return NULL; 5328 } 5329 5330 int 5331 i40e_vsi_release(struct i40e_vsi *vsi) 5332 { 5333 struct i40e_pf *pf; 5334 struct i40e_hw *hw; 5335 struct i40e_vsi_list *vsi_list; 5336 void *temp; 5337 int ret; 5338 struct i40e_mac_filter *f; 5339 uint16_t user_param; 5340 5341 if (!vsi) 5342 return I40E_SUCCESS; 5343 5344 if (!vsi->adapter) 5345 return -EFAULT; 5346 5347 user_param = vsi->user_param; 5348 5349 pf = I40E_VSI_TO_PF(vsi); 5350 hw = I40E_VSI_TO_HW(vsi); 5351 5352 /* VSI has child to attach, release child first */ 5353 if (vsi->veb) { 5354 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) { 5355 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS) 5356 return -1; 5357 } 5358 i40e_veb_release(vsi->veb); 5359 } 5360 5361 if (vsi->floating_veb) { 5362 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) { 5363 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS) 5364 return -1; 5365 } 5366 } 5367 5368 /* Remove all macvlan filters of the VSI */ 5369 i40e_vsi_remove_all_macvlan_filter(vsi); 5370 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) 5371 rte_free(f); 5372 5373 if (vsi->type != I40E_VSI_MAIN && 5374 ((vsi->type != I40E_VSI_SRIOV) || 5375 !pf->floating_veb_list[user_param])) { 5376 /* Remove vsi from parent's sibling list */ 5377 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) { 5378 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL"); 5379 return I40E_ERR_PARAM; 5380 } 5381 TAILQ_REMOVE(&vsi->parent_vsi->veb->head, 5382 &vsi->sib_vsi_list, list); 5383 5384 /* Remove all switch element of the VSI */ 5385 ret = i40e_aq_delete_element(hw, vsi->seid, NULL); 5386 if (ret != I40E_SUCCESS) 5387 PMD_DRV_LOG(ERR, "Failed to delete element"); 5388 } 5389 5390 if ((vsi->type == I40E_VSI_SRIOV) && 5391 pf->floating_veb_list[user_param]) { 5392 /* Remove vsi from parent's sibling list */ 5393 if (vsi->parent_vsi == NULL || 5394 vsi->parent_vsi->floating_veb == NULL) { 5395 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL"); 5396 return I40E_ERR_PARAM; 5397 } 5398 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head, 5399 &vsi->sib_vsi_list, list); 5400 5401 /* Remove all switch element of the VSI */ 5402 ret = i40e_aq_delete_element(hw, vsi->seid, NULL); 5403 if (ret != I40E_SUCCESS) 5404 PMD_DRV_LOG(ERR, "Failed to delete element"); 5405 } 5406 5407 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue); 5408 5409 if (vsi->type != I40E_VSI_SRIOV) 5410 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr); 5411 rte_free(vsi); 5412 5413 return I40E_SUCCESS; 5414 } 5415 5416 static int 5417 i40e_update_default_filter_setting(struct i40e_vsi *vsi) 5418 { 5419 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 5420 struct i40e_aqc_remove_macvlan_element_data def_filter; 5421 struct i40e_mac_filter_info filter; 5422 int ret; 5423 5424 if (vsi->type != I40E_VSI_MAIN) 5425 return I40E_ERR_CONFIG; 5426 memset(&def_filter, 0, sizeof(def_filter)); 5427 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr, 5428 ETH_ADDR_LEN); 5429 def_filter.vlan_tag = 0; 5430 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 5431 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 5432 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL); 5433 if (ret != I40E_SUCCESS) { 5434 struct i40e_mac_filter *f; 5435 struct rte_ether_addr *mac; 5436 5437 PMD_DRV_LOG(DEBUG, 5438 "Cannot remove the default macvlan filter"); 5439 /* It needs to add the permanent mac into mac list */ 5440 f = rte_zmalloc("macv_filter", sizeof(*f), 0); 5441 if (f == NULL) { 5442 PMD_DRV_LOG(ERR, "failed to allocate memory"); 5443 return I40E_ERR_NO_MEMORY; 5444 } 5445 mac = &f->mac_info.mac_addr; 5446 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr, 5447 ETH_ADDR_LEN); 5448 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5449 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 5450 vsi->mac_num++; 5451 5452 return ret; 5453 } 5454 rte_memcpy(&filter.mac_addr, 5455 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN); 5456 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5457 return i40e_vsi_add_mac(vsi, &filter); 5458 } 5459 5460 /* 5461 * i40e_vsi_get_bw_config - Query VSI BW Information 5462 * @vsi: the VSI to be queried 5463 * 5464 * Returns 0 on success, negative value on failure 5465 */ 5466 static enum i40e_status_code 5467 i40e_vsi_get_bw_config(struct i40e_vsi *vsi) 5468 { 5469 struct i40e_aqc_query_vsi_bw_config_resp bw_config; 5470 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config; 5471 struct i40e_hw *hw = &vsi->adapter->hw; 5472 i40e_status ret; 5473 int i; 5474 uint32_t bw_max; 5475 5476 memset(&bw_config, 0, sizeof(bw_config)); 5477 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); 5478 if (ret != I40E_SUCCESS) { 5479 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u", 5480 hw->aq.asq_last_status); 5481 return ret; 5482 } 5483 5484 memset(&ets_sla_config, 0, sizeof(ets_sla_config)); 5485 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, 5486 &ets_sla_config, NULL); 5487 if (ret != I40E_SUCCESS) { 5488 PMD_DRV_LOG(ERR, 5489 "VSI failed to get TC bandwdith configuration %u", 5490 hw->aq.asq_last_status); 5491 return ret; 5492 } 5493 5494 /* store and print out BW info */ 5495 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit); 5496 vsi->bw_info.bw_max = bw_config.max_bw; 5497 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit); 5498 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max); 5499 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) | 5500 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) << 5501 I40E_16_BIT_WIDTH); 5502 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 5503 vsi->bw_info.bw_ets_share_credits[i] = 5504 ets_sla_config.share_credits[i]; 5505 vsi->bw_info.bw_ets_credits[i] = 5506 rte_le_to_cpu_16(ets_sla_config.credits[i]); 5507 /* 4 bits per TC, 4th bit is reserved */ 5508 vsi->bw_info.bw_ets_max[i] = 5509 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) & 5510 RTE_LEN2MASK(3, uint8_t)); 5511 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i, 5512 vsi->bw_info.bw_ets_share_credits[i]); 5513 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i, 5514 vsi->bw_info.bw_ets_credits[i]); 5515 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i, 5516 vsi->bw_info.bw_ets_max[i]); 5517 } 5518 5519 return I40E_SUCCESS; 5520 } 5521 5522 /* i40e_enable_pf_lb 5523 * @pf: pointer to the pf structure 5524 * 5525 * allow loopback on pf 5526 */ 5527 static inline void 5528 i40e_enable_pf_lb(struct i40e_pf *pf) 5529 { 5530 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 5531 struct i40e_vsi_context ctxt; 5532 int ret; 5533 5534 /* Use the FW API if FW >= v5.0 */ 5535 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) { 5536 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback"); 5537 return; 5538 } 5539 5540 memset(&ctxt, 0, sizeof(ctxt)); 5541 ctxt.seid = pf->main_vsi_seid; 5542 ctxt.pf_num = hw->pf_id; 5543 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 5544 if (ret) { 5545 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d", 5546 ret, hw->aq.asq_last_status); 5547 return; 5548 } 5549 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 5550 ctxt.info.valid_sections = 5551 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5552 ctxt.info.switch_id |= 5553 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5554 5555 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5556 if (ret) 5557 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d", 5558 hw->aq.asq_last_status); 5559 } 5560 5561 /* Setup a VSI */ 5562 struct i40e_vsi * 5563 i40e_vsi_setup(struct i40e_pf *pf, 5564 enum i40e_vsi_type type, 5565 struct i40e_vsi *uplink_vsi, 5566 uint16_t user_param) 5567 { 5568 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 5569 struct i40e_vsi *vsi; 5570 struct i40e_mac_filter_info filter; 5571 int ret; 5572 struct i40e_vsi_context ctxt; 5573 struct rte_ether_addr broadcast = 5574 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; 5575 5576 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV && 5577 uplink_vsi == NULL) { 5578 PMD_DRV_LOG(ERR, 5579 "VSI setup failed, VSI link shouldn't be NULL"); 5580 return NULL; 5581 } 5582 5583 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) { 5584 PMD_DRV_LOG(ERR, 5585 "VSI setup failed, MAIN VSI uplink VSI should be NULL"); 5586 return NULL; 5587 } 5588 5589 /* two situations 5590 * 1.type is not MAIN and uplink vsi is not NULL 5591 * If uplink vsi didn't setup VEB, create one first under veb field 5592 * 2.type is SRIOV and the uplink is NULL 5593 * If floating VEB is NULL, create one veb under floating veb field 5594 */ 5595 5596 if (type != I40E_VSI_MAIN && uplink_vsi != NULL && 5597 uplink_vsi->veb == NULL) { 5598 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi); 5599 5600 if (uplink_vsi->veb == NULL) { 5601 PMD_DRV_LOG(ERR, "VEB setup failed"); 5602 return NULL; 5603 } 5604 /* set ALLOWLOOPBACk on pf, when veb is created */ 5605 i40e_enable_pf_lb(pf); 5606 } 5607 5608 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL && 5609 pf->main_vsi->floating_veb == NULL) { 5610 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi); 5611 5612 if (pf->main_vsi->floating_veb == NULL) { 5613 PMD_DRV_LOG(ERR, "VEB setup failed"); 5614 return NULL; 5615 } 5616 } 5617 5618 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0); 5619 if (!vsi) { 5620 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi"); 5621 return NULL; 5622 } 5623 TAILQ_INIT(&vsi->mac_list); 5624 vsi->type = type; 5625 vsi->adapter = I40E_PF_TO_ADAPTER(pf); 5626 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX; 5627 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi; 5628 vsi->user_param = user_param; 5629 vsi->vlan_anti_spoof_on = 0; 5630 vsi->vlan_filter_on = 0; 5631 /* Allocate queues */ 5632 switch (vsi->type) { 5633 case I40E_VSI_MAIN : 5634 vsi->nb_qps = pf->lan_nb_qps; 5635 break; 5636 case I40E_VSI_SRIOV : 5637 vsi->nb_qps = pf->vf_nb_qps; 5638 break; 5639 case I40E_VSI_VMDQ2: 5640 vsi->nb_qps = pf->vmdq_nb_qps; 5641 break; 5642 case I40E_VSI_FDIR: 5643 vsi->nb_qps = pf->fdir_nb_qps; 5644 break; 5645 default: 5646 goto fail_mem; 5647 } 5648 /* 5649 * The filter status descriptor is reported in rx queue 0, 5650 * while the tx queue for fdir filter programming has no 5651 * such constraints, can be non-zero queues. 5652 * To simplify it, choose FDIR vsi use queue 0 pair. 5653 * To make sure it will use queue 0 pair, queue allocation 5654 * need be done before this function is called 5655 */ 5656 if (type != I40E_VSI_FDIR) { 5657 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps); 5658 if (ret < 0) { 5659 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d", 5660 vsi->seid, ret); 5661 goto fail_mem; 5662 } 5663 vsi->base_queue = ret; 5664 } else 5665 vsi->base_queue = I40E_FDIR_QUEUE_ID; 5666 5667 /* VF has MSIX interrupt in VF range, don't allocate here */ 5668 if (type == I40E_VSI_MAIN) { 5669 if (pf->support_multi_driver) { 5670 /* If support multi-driver, need to use INT0 instead of 5671 * allocating from msix pool. The Msix pool is init from 5672 * INT1, so it's OK just set msix_intr to 0 and nb_msix 5673 * to 1 without calling i40e_res_pool_alloc. 5674 */ 5675 vsi->msix_intr = 0; 5676 vsi->nb_msix = 1; 5677 } else { 5678 ret = i40e_res_pool_alloc(&pf->msix_pool, 5679 RTE_MIN(vsi->nb_qps, 5680 RTE_MAX_RXTX_INTR_VEC_ID)); 5681 if (ret < 0) { 5682 PMD_DRV_LOG(ERR, 5683 "VSI MAIN %d get heap failed %d", 5684 vsi->seid, ret); 5685 goto fail_queue_alloc; 5686 } 5687 vsi->msix_intr = ret; 5688 vsi->nb_msix = RTE_MIN(vsi->nb_qps, 5689 RTE_MAX_RXTX_INTR_VEC_ID); 5690 } 5691 } else if (type != I40E_VSI_SRIOV) { 5692 ret = i40e_res_pool_alloc(&pf->msix_pool, 1); 5693 if (ret < 0) { 5694 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret); 5695 goto fail_queue_alloc; 5696 } 5697 vsi->msix_intr = ret; 5698 vsi->nb_msix = 1; 5699 } else { 5700 vsi->msix_intr = 0; 5701 vsi->nb_msix = 0; 5702 } 5703 5704 /* Add VSI */ 5705 if (type == I40E_VSI_MAIN) { 5706 /* For main VSI, no need to add since it's default one */ 5707 vsi->uplink_seid = pf->mac_seid; 5708 vsi->seid = pf->main_vsi_seid; 5709 /* Bind queues with specific MSIX interrupt */ 5710 /** 5711 * Needs 2 interrupt at least, one for misc cause which will 5712 * enabled from OS side, Another for queues binding the 5713 * interrupt from device side only. 5714 */ 5715 5716 /* Get default VSI parameters from hardware */ 5717 memset(&ctxt, 0, sizeof(ctxt)); 5718 ctxt.seid = vsi->seid; 5719 ctxt.pf_num = hw->pf_id; 5720 ctxt.uplink_seid = vsi->uplink_seid; 5721 ctxt.vf_num = 0; 5722 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 5723 if (ret != I40E_SUCCESS) { 5724 PMD_DRV_LOG(ERR, "Failed to get VSI params"); 5725 goto fail_msix_alloc; 5726 } 5727 rte_memcpy(&vsi->info, &ctxt.info, 5728 sizeof(struct i40e_aqc_vsi_properties_data)); 5729 vsi->vsi_id = ctxt.vsi_number; 5730 vsi->info.valid_sections = 0; 5731 5732 /* Configure tc, enabled TC0 only */ 5733 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) != 5734 I40E_SUCCESS) { 5735 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth"); 5736 goto fail_msix_alloc; 5737 } 5738 5739 /* TC, queue mapping */ 5740 memset(&ctxt, 0, sizeof(ctxt)); 5741 vsi->info.valid_sections |= 5742 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5743 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 5744 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 5745 rte_memcpy(&ctxt.info, &vsi->info, 5746 sizeof(struct i40e_aqc_vsi_properties_data)); 5747 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5748 I40E_DEFAULT_TCMAP); 5749 if (ret != I40E_SUCCESS) { 5750 PMD_DRV_LOG(ERR, 5751 "Failed to configure TC queue mapping"); 5752 goto fail_msix_alloc; 5753 } 5754 ctxt.seid = vsi->seid; 5755 ctxt.pf_num = hw->pf_id; 5756 ctxt.uplink_seid = vsi->uplink_seid; 5757 ctxt.vf_num = 0; 5758 5759 /* Update VSI parameters */ 5760 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 5761 if (ret != I40E_SUCCESS) { 5762 PMD_DRV_LOG(ERR, "Failed to update VSI params"); 5763 goto fail_msix_alloc; 5764 } 5765 5766 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping, 5767 sizeof(vsi->info.tc_mapping)); 5768 rte_memcpy(&vsi->info.queue_mapping, 5769 &ctxt.info.queue_mapping, 5770 sizeof(vsi->info.queue_mapping)); 5771 vsi->info.mapping_flags = ctxt.info.mapping_flags; 5772 vsi->info.valid_sections = 0; 5773 5774 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr, 5775 ETH_ADDR_LEN); 5776 5777 /** 5778 * Updating default filter settings are necessary to prevent 5779 * reception of tagged packets. 5780 * Some old firmware configurations load a default macvlan 5781 * filter which accepts both tagged and untagged packets. 5782 * The updating is to use a normal filter instead if needed. 5783 * For NVM 4.2.2 or after, the updating is not needed anymore. 5784 * The firmware with correct configurations load the default 5785 * macvlan filter which is expected and cannot be removed. 5786 */ 5787 i40e_update_default_filter_setting(vsi); 5788 i40e_config_qinq(hw, vsi); 5789 } else if (type == I40E_VSI_SRIOV) { 5790 memset(&ctxt, 0, sizeof(ctxt)); 5791 /** 5792 * For other VSI, the uplink_seid equals to uplink VSI's 5793 * uplink_seid since they share same VEB 5794 */ 5795 if (uplink_vsi == NULL) 5796 vsi->uplink_seid = pf->main_vsi->floating_veb->seid; 5797 else 5798 vsi->uplink_seid = uplink_vsi->uplink_seid; 5799 ctxt.pf_num = hw->pf_id; 5800 ctxt.vf_num = hw->func_caps.vf_base_id + user_param; 5801 ctxt.uplink_seid = vsi->uplink_seid; 5802 ctxt.connection_type = 0x1; 5803 ctxt.flags = I40E_AQ_VSI_TYPE_VF; 5804 5805 /* Use the VEB configuration if FW >= v5.0 */ 5806 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) { 5807 /* Configure switch ID */ 5808 ctxt.info.valid_sections |= 5809 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5810 ctxt.info.switch_id = 5811 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5812 } 5813 5814 /* Configure port/vlan */ 5815 ctxt.info.valid_sections |= 5816 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5817 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 5818 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5819 hw->func_caps.enabled_tcmap); 5820 if (ret != I40E_SUCCESS) { 5821 PMD_DRV_LOG(ERR, 5822 "Failed to configure TC queue mapping"); 5823 goto fail_msix_alloc; 5824 } 5825 5826 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap; 5827 ctxt.info.valid_sections |= 5828 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5829 /** 5830 * Since VSI is not created yet, only configure parameter, 5831 * will add vsi below. 5832 */ 5833 5834 i40e_config_qinq(hw, vsi); 5835 } else if (type == I40E_VSI_VMDQ2) { 5836 memset(&ctxt, 0, sizeof(ctxt)); 5837 /* 5838 * For other VSI, the uplink_seid equals to uplink VSI's 5839 * uplink_seid since they share same VEB 5840 */ 5841 vsi->uplink_seid = uplink_vsi->uplink_seid; 5842 ctxt.pf_num = hw->pf_id; 5843 ctxt.vf_num = 0; 5844 ctxt.uplink_seid = vsi->uplink_seid; 5845 ctxt.connection_type = 0x1; 5846 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; 5847 5848 ctxt.info.valid_sections |= 5849 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5850 /* user_param carries flag to enable loop back */ 5851 if (user_param) { 5852 ctxt.info.switch_id = 5853 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB); 5854 ctxt.info.switch_id |= 5855 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 5856 } 5857 5858 /* Configure port/vlan */ 5859 ctxt.info.valid_sections |= 5860 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 5861 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 5862 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5863 I40E_DEFAULT_TCMAP); 5864 if (ret != I40E_SUCCESS) { 5865 PMD_DRV_LOG(ERR, 5866 "Failed to configure TC queue mapping"); 5867 goto fail_msix_alloc; 5868 } 5869 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP; 5870 ctxt.info.valid_sections |= 5871 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5872 } else if (type == I40E_VSI_FDIR) { 5873 memset(&ctxt, 0, sizeof(ctxt)); 5874 vsi->uplink_seid = uplink_vsi->uplink_seid; 5875 ctxt.pf_num = hw->pf_id; 5876 ctxt.vf_num = 0; 5877 ctxt.uplink_seid = vsi->uplink_seid; 5878 ctxt.connection_type = 0x1; /* regular data port */ 5879 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 5880 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info, 5881 I40E_DEFAULT_TCMAP); 5882 if (ret != I40E_SUCCESS) { 5883 PMD_DRV_LOG(ERR, 5884 "Failed to configure TC queue mapping."); 5885 goto fail_msix_alloc; 5886 } 5887 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP; 5888 ctxt.info.valid_sections |= 5889 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID); 5890 } else { 5891 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet"); 5892 goto fail_msix_alloc; 5893 } 5894 5895 if (vsi->type != I40E_VSI_MAIN) { 5896 ret = i40e_aq_add_vsi(hw, &ctxt, NULL); 5897 if (ret != I40E_SUCCESS) { 5898 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d", 5899 hw->aq.asq_last_status); 5900 goto fail_msix_alloc; 5901 } 5902 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 5903 vsi->info.valid_sections = 0; 5904 vsi->seid = ctxt.seid; 5905 vsi->vsi_id = ctxt.vsi_number; 5906 vsi->sib_vsi_list.vsi = vsi; 5907 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) { 5908 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head, 5909 &vsi->sib_vsi_list, list); 5910 } else { 5911 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head, 5912 &vsi->sib_vsi_list, list); 5913 } 5914 } 5915 5916 /* MAC/VLAN configuration */ 5917 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN); 5918 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH; 5919 5920 ret = i40e_vsi_add_mac(vsi, &filter); 5921 if (ret != I40E_SUCCESS) { 5922 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter"); 5923 goto fail_msix_alloc; 5924 } 5925 5926 /* Get VSI BW information */ 5927 i40e_vsi_get_bw_config(vsi); 5928 return vsi; 5929 fail_msix_alloc: 5930 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr); 5931 fail_queue_alloc: 5932 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue); 5933 fail_mem: 5934 rte_free(vsi); 5935 return NULL; 5936 } 5937 5938 /* Configure vlan filter on or off */ 5939 int 5940 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on) 5941 { 5942 int i, num; 5943 struct i40e_mac_filter *f; 5944 void *temp; 5945 struct i40e_mac_filter_info *mac_filter; 5946 enum rte_mac_filter_type desired_filter; 5947 int ret = I40E_SUCCESS; 5948 5949 if (on) { 5950 /* Filter to match MAC and VLAN */ 5951 desired_filter = RTE_MACVLAN_PERFECT_MATCH; 5952 } else { 5953 /* Filter to match only MAC */ 5954 desired_filter = RTE_MAC_PERFECT_MATCH; 5955 } 5956 5957 num = vsi->mac_num; 5958 5959 mac_filter = rte_zmalloc("mac_filter_info_data", 5960 num * sizeof(*mac_filter), 0); 5961 if (mac_filter == NULL) { 5962 PMD_DRV_LOG(ERR, "failed to allocate memory"); 5963 return I40E_ERR_NO_MEMORY; 5964 } 5965 5966 i = 0; 5967 5968 /* Remove all existing mac */ 5969 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) { 5970 mac_filter[i] = f->mac_info; 5971 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr); 5972 if (ret) { 5973 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter", 5974 on ? "enable" : "disable"); 5975 goto DONE; 5976 } 5977 i++; 5978 } 5979 5980 /* Override with new filter */ 5981 for (i = 0; i < num; i++) { 5982 mac_filter[i].filter_type = desired_filter; 5983 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]); 5984 if (ret) { 5985 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter", 5986 on ? "enable" : "disable"); 5987 goto DONE; 5988 } 5989 } 5990 5991 DONE: 5992 rte_free(mac_filter); 5993 return ret; 5994 } 5995 5996 /* Configure vlan stripping on or off */ 5997 int 5998 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on) 5999 { 6000 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6001 struct i40e_vsi_context ctxt; 6002 uint8_t vlan_flags; 6003 int ret = I40E_SUCCESS; 6004 6005 /* Check if it has been already on or off */ 6006 if (vsi->info.valid_sections & 6007 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) { 6008 if (on) { 6009 if ((vsi->info.port_vlan_flags & 6010 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0) 6011 return 0; /* already on */ 6012 } else { 6013 if ((vsi->info.port_vlan_flags & 6014 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 6015 I40E_AQ_VSI_PVLAN_EMOD_MASK) 6016 return 0; /* already off */ 6017 } 6018 } 6019 6020 if (on) 6021 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 6022 else 6023 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 6024 vsi->info.valid_sections = 6025 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID); 6026 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK); 6027 vsi->info.port_vlan_flags |= vlan_flags; 6028 ctxt.seid = vsi->seid; 6029 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 6030 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 6031 if (ret) 6032 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 6033 on ? "enable" : "disable"); 6034 6035 return ret; 6036 } 6037 6038 static int 6039 i40e_dev_init_vlan(struct rte_eth_dev *dev) 6040 { 6041 struct rte_eth_dev_data *data = dev->data; 6042 int ret; 6043 int mask = 0; 6044 6045 /* Apply vlan offload setting */ 6046 mask = ETH_VLAN_STRIP_MASK | 6047 ETH_VLAN_FILTER_MASK | 6048 ETH_VLAN_EXTEND_MASK; 6049 ret = i40e_vlan_offload_set(dev, mask); 6050 if (ret) { 6051 PMD_DRV_LOG(INFO, "Failed to update vlan offload"); 6052 return ret; 6053 } 6054 6055 /* Apply pvid setting */ 6056 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid, 6057 data->dev_conf.txmode.hw_vlan_insert_pvid); 6058 if (ret) 6059 PMD_DRV_LOG(INFO, "Failed to update VSI params"); 6060 6061 return ret; 6062 } 6063 6064 static int 6065 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on) 6066 { 6067 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6068 6069 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL); 6070 } 6071 6072 static int 6073 i40e_update_flow_control(struct i40e_hw *hw) 6074 { 6075 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX) 6076 struct i40e_link_status link_status; 6077 uint32_t rxfc = 0, txfc = 0, reg; 6078 uint8_t an_info; 6079 int ret; 6080 6081 memset(&link_status, 0, sizeof(link_status)); 6082 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL); 6083 if (ret != I40E_SUCCESS) { 6084 PMD_DRV_LOG(ERR, "Failed to get link status information"); 6085 goto write_reg; /* Disable flow control */ 6086 } 6087 6088 an_info = hw->phy.link_info.an_info; 6089 if (!(an_info & I40E_AQ_AN_COMPLETED)) { 6090 PMD_DRV_LOG(INFO, "Link auto negotiation not completed"); 6091 ret = I40E_ERR_NOT_READY; 6092 goto write_reg; /* Disable flow control */ 6093 } 6094 /** 6095 * If link auto negotiation is enabled, flow control needs to 6096 * be configured according to it 6097 */ 6098 switch (an_info & I40E_LINK_PAUSE_RXTX) { 6099 case I40E_LINK_PAUSE_RXTX: 6100 rxfc = 1; 6101 txfc = 1; 6102 hw->fc.current_mode = I40E_FC_FULL; 6103 break; 6104 case I40E_AQ_LINK_PAUSE_RX: 6105 rxfc = 1; 6106 hw->fc.current_mode = I40E_FC_RX_PAUSE; 6107 break; 6108 case I40E_AQ_LINK_PAUSE_TX: 6109 txfc = 1; 6110 hw->fc.current_mode = I40E_FC_TX_PAUSE; 6111 break; 6112 default: 6113 hw->fc.current_mode = I40E_FC_NONE; 6114 break; 6115 } 6116 6117 write_reg: 6118 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG, 6119 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT); 6120 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); 6121 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK; 6122 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT; 6123 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg); 6124 6125 return ret; 6126 } 6127 6128 /* PF setup */ 6129 static int 6130 i40e_pf_setup(struct i40e_pf *pf) 6131 { 6132 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 6133 struct i40e_filter_control_settings settings; 6134 struct i40e_vsi *vsi; 6135 int ret; 6136 6137 /* Clear all stats counters */ 6138 pf->offset_loaded = FALSE; 6139 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats)); 6140 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats)); 6141 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats)); 6142 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats)); 6143 6144 ret = i40e_pf_get_switch_config(pf); 6145 if (ret != I40E_SUCCESS) { 6146 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret); 6147 return ret; 6148 } 6149 6150 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id); 6151 if (ret) 6152 PMD_INIT_LOG(WARNING, 6153 "failed to allocate switch domain for device %d", ret); 6154 6155 if (pf->flags & I40E_FLAG_FDIR) { 6156 /* make queue allocated first, let FDIR use queue pair 0*/ 6157 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR); 6158 if (ret != I40E_FDIR_QUEUE_ID) { 6159 PMD_DRV_LOG(ERR, 6160 "queue allocation fails for FDIR: ret =%d", 6161 ret); 6162 pf->flags &= ~I40E_FLAG_FDIR; 6163 } 6164 } 6165 /* main VSI setup */ 6166 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0); 6167 if (!vsi) { 6168 PMD_DRV_LOG(ERR, "Setup of main vsi failed"); 6169 return I40E_ERR_NOT_READY; 6170 } 6171 pf->main_vsi = vsi; 6172 6173 /* Configure filter control */ 6174 memset(&settings, 0, sizeof(settings)); 6175 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128) 6176 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128; 6177 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512) 6178 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512; 6179 else { 6180 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported", 6181 hw->func_caps.rss_table_size); 6182 return I40E_ERR_PARAM; 6183 } 6184 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u", 6185 hw->func_caps.rss_table_size); 6186 pf->hash_lut_size = hw->func_caps.rss_table_size; 6187 6188 /* Enable ethtype and macvlan filters */ 6189 settings.enable_ethtype = TRUE; 6190 settings.enable_macvlan = TRUE; 6191 ret = i40e_set_filter_control(hw, &settings); 6192 if (ret) 6193 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d", 6194 ret); 6195 6196 /* Update flow control according to the auto negotiation */ 6197 i40e_update_flow_control(hw); 6198 6199 return I40E_SUCCESS; 6200 } 6201 6202 int 6203 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) 6204 { 6205 uint32_t reg; 6206 uint16_t j; 6207 6208 /** 6209 * Set or clear TX Queue Disable flags, 6210 * which is required by hardware. 6211 */ 6212 i40e_pre_tx_queue_cfg(hw, q_idx, on); 6213 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US); 6214 6215 /* Wait until the request is finished */ 6216 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6217 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6218 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx)); 6219 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^ 6220 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) 6221 & 0x1))) { 6222 break; 6223 } 6224 } 6225 if (on) { 6226 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 6227 return I40E_SUCCESS; /* already on, skip next steps */ 6228 6229 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0); 6230 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 6231 } else { 6232 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6233 return I40E_SUCCESS; /* already off, skip next steps */ 6234 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 6235 } 6236 /* Write the register */ 6237 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg); 6238 /* Check the result */ 6239 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6240 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6241 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx)); 6242 if (on) { 6243 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) && 6244 (reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6245 break; 6246 } else { 6247 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) && 6248 !(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 6249 break; 6250 } 6251 } 6252 /* Check if it is timeout */ 6253 if (j >= I40E_CHK_Q_ENA_COUNT) { 6254 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]", 6255 (on ? "enable" : "disable"), q_idx); 6256 return I40E_ERR_TIMEOUT; 6257 } 6258 6259 return I40E_SUCCESS; 6260 } 6261 6262 /* Swith on or off the tx queues */ 6263 static int 6264 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on) 6265 { 6266 struct rte_eth_dev_data *dev_data = pf->dev_data; 6267 struct i40e_tx_queue *txq; 6268 struct rte_eth_dev *dev = pf->adapter->eth_dev; 6269 uint16_t i; 6270 int ret; 6271 6272 for (i = 0; i < dev_data->nb_tx_queues; i++) { 6273 txq = dev_data->tx_queues[i]; 6274 /* Don't operate the queue if not configured or 6275 * if starting only per queue */ 6276 if (!txq || !txq->q_set || (on && txq->tx_deferred_start)) 6277 continue; 6278 if (on) 6279 ret = i40e_dev_tx_queue_start(dev, i); 6280 else 6281 ret = i40e_dev_tx_queue_stop(dev, i); 6282 if ( ret != I40E_SUCCESS) 6283 return ret; 6284 } 6285 6286 return I40E_SUCCESS; 6287 } 6288 6289 int 6290 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) 6291 { 6292 uint32_t reg; 6293 uint16_t j; 6294 6295 /* Wait until the request is finished */ 6296 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6297 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6298 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); 6299 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^ 6300 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1)) 6301 break; 6302 } 6303 6304 if (on) { 6305 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 6306 return I40E_SUCCESS; /* Already on, skip next steps */ 6307 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 6308 } else { 6309 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6310 return I40E_SUCCESS; /* Already off, skip next steps */ 6311 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 6312 } 6313 6314 /* Write the register */ 6315 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg); 6316 /* Check the result */ 6317 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { 6318 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); 6319 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); 6320 if (on) { 6321 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) && 6322 (reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6323 break; 6324 } else { 6325 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) && 6326 !(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 6327 break; 6328 } 6329 } 6330 6331 /* Check if it is timeout */ 6332 if (j >= I40E_CHK_Q_ENA_COUNT) { 6333 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]", 6334 (on ? "enable" : "disable"), q_idx); 6335 return I40E_ERR_TIMEOUT; 6336 } 6337 6338 return I40E_SUCCESS; 6339 } 6340 /* Switch on or off the rx queues */ 6341 static int 6342 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on) 6343 { 6344 struct rte_eth_dev_data *dev_data = pf->dev_data; 6345 struct i40e_rx_queue *rxq; 6346 struct rte_eth_dev *dev = pf->adapter->eth_dev; 6347 uint16_t i; 6348 int ret; 6349 6350 for (i = 0; i < dev_data->nb_rx_queues; i++) { 6351 rxq = dev_data->rx_queues[i]; 6352 /* Don't operate the queue if not configured or 6353 * if starting only per queue */ 6354 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start)) 6355 continue; 6356 if (on) 6357 ret = i40e_dev_rx_queue_start(dev, i); 6358 else 6359 ret = i40e_dev_rx_queue_stop(dev, i); 6360 if (ret != I40E_SUCCESS) 6361 return ret; 6362 } 6363 6364 return I40E_SUCCESS; 6365 } 6366 6367 /* Switch on or off all the rx/tx queues */ 6368 int 6369 i40e_dev_switch_queues(struct i40e_pf *pf, bool on) 6370 { 6371 int ret; 6372 6373 if (on) { 6374 /* enable rx queues before enabling tx queues */ 6375 ret = i40e_dev_switch_rx_queues(pf, on); 6376 if (ret) { 6377 PMD_DRV_LOG(ERR, "Failed to switch rx queues"); 6378 return ret; 6379 } 6380 ret = i40e_dev_switch_tx_queues(pf, on); 6381 } else { 6382 /* Stop tx queues before stopping rx queues */ 6383 ret = i40e_dev_switch_tx_queues(pf, on); 6384 if (ret) { 6385 PMD_DRV_LOG(ERR, "Failed to switch tx queues"); 6386 return ret; 6387 } 6388 ret = i40e_dev_switch_rx_queues(pf, on); 6389 } 6390 6391 return ret; 6392 } 6393 6394 /* Initialize VSI for TX */ 6395 static int 6396 i40e_dev_tx_init(struct i40e_pf *pf) 6397 { 6398 struct rte_eth_dev_data *data = pf->dev_data; 6399 uint16_t i; 6400 uint32_t ret = I40E_SUCCESS; 6401 struct i40e_tx_queue *txq; 6402 6403 for (i = 0; i < data->nb_tx_queues; i++) { 6404 txq = data->tx_queues[i]; 6405 if (!txq || !txq->q_set) 6406 continue; 6407 ret = i40e_tx_queue_init(txq); 6408 if (ret != I40E_SUCCESS) 6409 break; 6410 } 6411 if (ret == I40E_SUCCESS) 6412 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf) 6413 ->eth_dev); 6414 6415 return ret; 6416 } 6417 6418 /* Initialize VSI for RX */ 6419 static int 6420 i40e_dev_rx_init(struct i40e_pf *pf) 6421 { 6422 struct rte_eth_dev_data *data = pf->dev_data; 6423 int ret = I40E_SUCCESS; 6424 uint16_t i; 6425 struct i40e_rx_queue *rxq; 6426 6427 i40e_pf_config_mq_rx(pf); 6428 for (i = 0; i < data->nb_rx_queues; i++) { 6429 rxq = data->rx_queues[i]; 6430 if (!rxq || !rxq->q_set) 6431 continue; 6432 6433 ret = i40e_rx_queue_init(rxq); 6434 if (ret != I40E_SUCCESS) { 6435 PMD_DRV_LOG(ERR, 6436 "Failed to do RX queue initialization"); 6437 break; 6438 } 6439 } 6440 if (ret == I40E_SUCCESS) 6441 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf) 6442 ->eth_dev); 6443 6444 return ret; 6445 } 6446 6447 static int 6448 i40e_dev_rxtx_init(struct i40e_pf *pf) 6449 { 6450 int err; 6451 6452 err = i40e_dev_tx_init(pf); 6453 if (err) { 6454 PMD_DRV_LOG(ERR, "Failed to do TX initialization"); 6455 return err; 6456 } 6457 err = i40e_dev_rx_init(pf); 6458 if (err) { 6459 PMD_DRV_LOG(ERR, "Failed to do RX initialization"); 6460 return err; 6461 } 6462 6463 return err; 6464 } 6465 6466 static int 6467 i40e_vmdq_setup(struct rte_eth_dev *dev) 6468 { 6469 struct rte_eth_conf *conf = &dev->data->dev_conf; 6470 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6471 int i, err, conf_vsis, j, loop; 6472 struct i40e_vsi *vsi; 6473 struct i40e_vmdq_info *vmdq_info; 6474 struct rte_eth_vmdq_rx_conf *vmdq_conf; 6475 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 6476 6477 /* 6478 * Disable interrupt to avoid message from VF. Furthermore, it will 6479 * avoid race condition in VSI creation/destroy. 6480 */ 6481 i40e_pf_disable_irq0(hw); 6482 6483 if ((pf->flags & I40E_FLAG_VMDQ) == 0) { 6484 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ"); 6485 return -ENOTSUP; 6486 } 6487 6488 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools; 6489 if (conf_vsis > pf->max_nb_vmdq_vsi) { 6490 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u", 6491 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools, 6492 pf->max_nb_vmdq_vsi); 6493 return -ENOTSUP; 6494 } 6495 6496 if (pf->vmdq != NULL) { 6497 PMD_INIT_LOG(INFO, "VMDQ already configured"); 6498 return 0; 6499 } 6500 6501 pf->vmdq = rte_zmalloc("vmdq_info_struct", 6502 sizeof(*vmdq_info) * conf_vsis, 0); 6503 6504 if (pf->vmdq == NULL) { 6505 PMD_INIT_LOG(ERR, "Failed to allocate memory"); 6506 return -ENOMEM; 6507 } 6508 6509 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf; 6510 6511 /* Create VMDQ VSI */ 6512 for (i = 0; i < conf_vsis; i++) { 6513 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi, 6514 vmdq_conf->enable_loop_back); 6515 if (vsi == NULL) { 6516 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI"); 6517 err = -1; 6518 goto err_vsi_setup; 6519 } 6520 vmdq_info = &pf->vmdq[i]; 6521 vmdq_info->pf = pf; 6522 vmdq_info->vsi = vsi; 6523 } 6524 pf->nb_cfg_vmdq_vsi = conf_vsis; 6525 6526 /* Configure Vlan */ 6527 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT; 6528 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) { 6529 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) { 6530 if (vmdq_conf->pool_map[i].pools & (1UL << j)) { 6531 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u", 6532 vmdq_conf->pool_map[i].vlan_id, j); 6533 6534 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi, 6535 vmdq_conf->pool_map[i].vlan_id); 6536 if (err) { 6537 PMD_INIT_LOG(ERR, "Failed to add vlan"); 6538 err = -1; 6539 goto err_vsi_setup; 6540 } 6541 } 6542 } 6543 } 6544 6545 i40e_pf_enable_irq0(hw); 6546 6547 return 0; 6548 6549 err_vsi_setup: 6550 for (i = 0; i < conf_vsis; i++) 6551 if (pf->vmdq[i].vsi == NULL) 6552 break; 6553 else 6554 i40e_vsi_release(pf->vmdq[i].vsi); 6555 6556 rte_free(pf->vmdq); 6557 pf->vmdq = NULL; 6558 i40e_pf_enable_irq0(hw); 6559 return err; 6560 } 6561 6562 static void 6563 i40e_stat_update_32(struct i40e_hw *hw, 6564 uint32_t reg, 6565 bool offset_loaded, 6566 uint64_t *offset, 6567 uint64_t *stat) 6568 { 6569 uint64_t new_data; 6570 6571 new_data = (uint64_t)I40E_READ_REG(hw, reg); 6572 if (!offset_loaded) 6573 *offset = new_data; 6574 6575 if (new_data >= *offset) 6576 *stat = (uint64_t)(new_data - *offset); 6577 else 6578 *stat = (uint64_t)((new_data + 6579 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset); 6580 } 6581 6582 static void 6583 i40e_stat_update_48(struct i40e_hw *hw, 6584 uint32_t hireg, 6585 uint32_t loreg, 6586 bool offset_loaded, 6587 uint64_t *offset, 6588 uint64_t *stat) 6589 { 6590 uint64_t new_data; 6591 6592 new_data = (uint64_t)I40E_READ_REG(hw, loreg); 6593 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & 6594 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; 6595 6596 if (!offset_loaded) 6597 *offset = new_data; 6598 6599 if (new_data >= *offset) 6600 *stat = new_data - *offset; 6601 else 6602 *stat = (uint64_t)((new_data + 6603 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset); 6604 6605 *stat &= I40E_48_BIT_MASK; 6606 } 6607 6608 /* Disable IRQ0 */ 6609 void 6610 i40e_pf_disable_irq0(struct i40e_hw *hw) 6611 { 6612 /* Disable all interrupt types */ 6613 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 6614 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 6615 I40E_WRITE_FLUSH(hw); 6616 } 6617 6618 /* Enable IRQ0 */ 6619 void 6620 i40e_pf_enable_irq0(struct i40e_hw *hw) 6621 { 6622 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 6623 I40E_PFINT_DYN_CTL0_INTENA_MASK | 6624 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 6625 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 6626 I40E_WRITE_FLUSH(hw); 6627 } 6628 6629 static void 6630 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue) 6631 { 6632 /* read pending request and disable first */ 6633 i40e_pf_disable_irq0(hw); 6634 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK); 6635 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0, 6636 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK); 6637 6638 if (no_queue) 6639 /* Link no queues with irq0 */ 6640 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, 6641 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK); 6642 } 6643 6644 static void 6645 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev) 6646 { 6647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6648 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6649 int i; 6650 uint16_t abs_vf_id; 6651 uint32_t index, offset, val; 6652 6653 if (!pf->vfs) 6654 return; 6655 /** 6656 * Try to find which VF trigger a reset, use absolute VF id to access 6657 * since the reg is global register. 6658 */ 6659 for (i = 0; i < pf->vf_num; i++) { 6660 abs_vf_id = hw->func_caps.vf_base_id + i; 6661 index = abs_vf_id / I40E_UINT32_BIT_SIZE; 6662 offset = abs_vf_id % I40E_UINT32_BIT_SIZE; 6663 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index)); 6664 /* VFR event occurred */ 6665 if (val & (0x1 << offset)) { 6666 int ret; 6667 6668 /* Clear the event first */ 6669 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index), 6670 (0x1 << offset)); 6671 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id); 6672 /** 6673 * Only notify a VF reset event occurred, 6674 * don't trigger another SW reset 6675 */ 6676 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0); 6677 if (ret != I40E_SUCCESS) 6678 PMD_DRV_LOG(ERR, "Failed to do VF reset"); 6679 } 6680 } 6681 } 6682 6683 static void 6684 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev) 6685 { 6686 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6687 int i; 6688 6689 for (i = 0; i < pf->vf_num; i++) 6690 i40e_notify_vf_link_status(dev, &pf->vfs[i]); 6691 } 6692 6693 static void 6694 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev) 6695 { 6696 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6697 struct i40e_arq_event_info info; 6698 uint16_t pending, opcode; 6699 int ret; 6700 6701 info.buf_len = I40E_AQ_BUF_SZ; 6702 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0); 6703 if (!info.msg_buf) { 6704 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 6705 return; 6706 } 6707 6708 pending = 1; 6709 while (pending) { 6710 ret = i40e_clean_arq_element(hw, &info, &pending); 6711 6712 if (ret != I40E_SUCCESS) { 6713 PMD_DRV_LOG(INFO, 6714 "Failed to read msg from AdminQ, aq_err: %u", 6715 hw->aq.asq_last_status); 6716 break; 6717 } 6718 opcode = rte_le_to_cpu_16(info.desc.opcode); 6719 6720 switch (opcode) { 6721 case i40e_aqc_opc_send_msg_to_pf: 6722 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/ 6723 i40e_pf_host_handle_vf_msg(dev, 6724 rte_le_to_cpu_16(info.desc.retval), 6725 rte_le_to_cpu_32(info.desc.cookie_high), 6726 rte_le_to_cpu_32(info.desc.cookie_low), 6727 info.msg_buf, 6728 info.msg_len); 6729 break; 6730 case i40e_aqc_opc_get_link_status: 6731 ret = i40e_dev_link_update(dev, 0); 6732 if (!ret) 6733 _rte_eth_dev_callback_process(dev, 6734 RTE_ETH_EVENT_INTR_LSC, NULL); 6735 break; 6736 default: 6737 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 6738 opcode); 6739 break; 6740 } 6741 } 6742 rte_free(info.msg_buf); 6743 } 6744 6745 /** 6746 * Interrupt handler triggered by NIC for handling 6747 * specific interrupt. 6748 * 6749 * @param handle 6750 * Pointer to interrupt handle. 6751 * @param param 6752 * The address of parameter (struct rte_eth_dev *) regsitered before. 6753 * 6754 * @return 6755 * void 6756 */ 6757 static void 6758 i40e_dev_interrupt_handler(void *param) 6759 { 6760 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 6761 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6762 uint32_t icr0; 6763 6764 /* Disable interrupt */ 6765 i40e_pf_disable_irq0(hw); 6766 6767 /* read out interrupt causes */ 6768 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); 6769 6770 /* No interrupt event indicated */ 6771 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) { 6772 PMD_DRV_LOG(INFO, "No interrupt event"); 6773 goto done; 6774 } 6775 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) 6776 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); 6777 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) 6778 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); 6779 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) 6780 PMD_DRV_LOG(INFO, "ICR0: global reset requested"); 6781 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) 6782 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); 6783 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) 6784 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); 6785 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) 6786 PMD_DRV_LOG(ERR, "ICR0: HMC error"); 6787 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) 6788 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); 6789 6790 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 6791 PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); 6792 i40e_dev_handle_vfr_event(dev); 6793 } 6794 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 6795 PMD_DRV_LOG(INFO, "ICR0: adminq event"); 6796 i40e_dev_handle_aq_msg(dev); 6797 } 6798 6799 done: 6800 /* Enable interrupt */ 6801 i40e_pf_enable_irq0(hw); 6802 } 6803 6804 static void 6805 i40e_dev_alarm_handler(void *param) 6806 { 6807 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 6808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6809 uint32_t icr0; 6810 6811 /* Disable interrupt */ 6812 i40e_pf_disable_irq0(hw); 6813 6814 /* read out interrupt causes */ 6815 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0); 6816 6817 /* No interrupt event indicated */ 6818 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) 6819 goto done; 6820 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK) 6821 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error"); 6822 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) 6823 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected"); 6824 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) 6825 PMD_DRV_LOG(INFO, "ICR0: global reset requested"); 6826 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) 6827 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated"); 6828 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK) 6829 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state"); 6830 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) 6831 PMD_DRV_LOG(ERR, "ICR0: HMC error"); 6832 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK) 6833 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error"); 6834 6835 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 6836 PMD_DRV_LOG(INFO, "ICR0: VF reset detected"); 6837 i40e_dev_handle_vfr_event(dev); 6838 } 6839 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 6840 PMD_DRV_LOG(INFO, "ICR0: adminq event"); 6841 i40e_dev_handle_aq_msg(dev); 6842 } 6843 6844 done: 6845 /* Enable interrupt */ 6846 i40e_pf_enable_irq0(hw); 6847 rte_eal_alarm_set(I40E_ALARM_INTERVAL, 6848 i40e_dev_alarm_handler, dev); 6849 } 6850 6851 int 6852 i40e_add_macvlan_filters(struct i40e_vsi *vsi, 6853 struct i40e_macvlan_filter *filter, 6854 int total) 6855 { 6856 int ele_num, ele_buff_size; 6857 int num, actual_num, i; 6858 uint16_t flags; 6859 int ret = I40E_SUCCESS; 6860 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6861 struct i40e_aqc_add_macvlan_element_data *req_list; 6862 6863 if (filter == NULL || total == 0) 6864 return I40E_ERR_PARAM; 6865 ele_num = hw->aq.asq_buf_size / sizeof(*req_list); 6866 ele_buff_size = hw->aq.asq_buf_size; 6867 6868 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0); 6869 if (req_list == NULL) { 6870 PMD_DRV_LOG(ERR, "Fail to allocate memory"); 6871 return I40E_ERR_NO_MEMORY; 6872 } 6873 6874 num = 0; 6875 do { 6876 actual_num = (num + ele_num > total) ? (total - num) : ele_num; 6877 memset(req_list, 0, ele_buff_size); 6878 6879 for (i = 0; i < actual_num; i++) { 6880 rte_memcpy(req_list[i].mac_addr, 6881 &filter[num + i].macaddr, ETH_ADDR_LEN); 6882 req_list[i].vlan_tag = 6883 rte_cpu_to_le_16(filter[num + i].vlan_id); 6884 6885 switch (filter[num + i].filter_type) { 6886 case RTE_MAC_PERFECT_MATCH: 6887 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH | 6888 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 6889 break; 6890 case RTE_MACVLAN_PERFECT_MATCH: 6891 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 6892 break; 6893 case RTE_MAC_HASH_MATCH: 6894 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH | 6895 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 6896 break; 6897 case RTE_MACVLAN_HASH_MATCH: 6898 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH; 6899 break; 6900 default: 6901 PMD_DRV_LOG(ERR, "Invalid MAC match type"); 6902 ret = I40E_ERR_PARAM; 6903 goto DONE; 6904 } 6905 6906 req_list[i].queue_number = 0; 6907 6908 req_list[i].flags = rte_cpu_to_le_16(flags); 6909 } 6910 6911 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list, 6912 actual_num, NULL); 6913 if (ret != I40E_SUCCESS) { 6914 PMD_DRV_LOG(ERR, "Failed to add macvlan filter"); 6915 goto DONE; 6916 } 6917 num += actual_num; 6918 } while (num < total); 6919 6920 DONE: 6921 rte_free(req_list); 6922 return ret; 6923 } 6924 6925 int 6926 i40e_remove_macvlan_filters(struct i40e_vsi *vsi, 6927 struct i40e_macvlan_filter *filter, 6928 int total) 6929 { 6930 int ele_num, ele_buff_size; 6931 int num, actual_num, i; 6932 uint16_t flags; 6933 int ret = I40E_SUCCESS; 6934 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 6935 struct i40e_aqc_remove_macvlan_element_data *req_list; 6936 6937 if (filter == NULL || total == 0) 6938 return I40E_ERR_PARAM; 6939 6940 ele_num = hw->aq.asq_buf_size / sizeof(*req_list); 6941 ele_buff_size = hw->aq.asq_buf_size; 6942 6943 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0); 6944 if (req_list == NULL) { 6945 PMD_DRV_LOG(ERR, "Fail to allocate memory"); 6946 return I40E_ERR_NO_MEMORY; 6947 } 6948 6949 num = 0; 6950 do { 6951 actual_num = (num + ele_num > total) ? (total - num) : ele_num; 6952 memset(req_list, 0, ele_buff_size); 6953 6954 for (i = 0; i < actual_num; i++) { 6955 rte_memcpy(req_list[i].mac_addr, 6956 &filter[num + i].macaddr, ETH_ADDR_LEN); 6957 req_list[i].vlan_tag = 6958 rte_cpu_to_le_16(filter[num + i].vlan_id); 6959 6960 switch (filter[num + i].filter_type) { 6961 case RTE_MAC_PERFECT_MATCH: 6962 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 6963 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 6964 break; 6965 case RTE_MACVLAN_PERFECT_MATCH: 6966 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 6967 break; 6968 case RTE_MAC_HASH_MATCH: 6969 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH | 6970 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; 6971 break; 6972 case RTE_MACVLAN_HASH_MATCH: 6973 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH; 6974 break; 6975 default: 6976 PMD_DRV_LOG(ERR, "Invalid MAC filter type"); 6977 ret = I40E_ERR_PARAM; 6978 goto DONE; 6979 } 6980 req_list[i].flags = rte_cpu_to_le_16(flags); 6981 } 6982 6983 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list, 6984 actual_num, NULL); 6985 if (ret != I40E_SUCCESS) { 6986 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter"); 6987 goto DONE; 6988 } 6989 num += actual_num; 6990 } while (num < total); 6991 6992 DONE: 6993 rte_free(req_list); 6994 return ret; 6995 } 6996 6997 /* Find out specific MAC filter */ 6998 static struct i40e_mac_filter * 6999 i40e_find_mac_filter(struct i40e_vsi *vsi, 7000 struct rte_ether_addr *macaddr) 7001 { 7002 struct i40e_mac_filter *f; 7003 7004 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7005 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 7006 return f; 7007 } 7008 7009 return NULL; 7010 } 7011 7012 static bool 7013 i40e_find_vlan_filter(struct i40e_vsi *vsi, 7014 uint16_t vlan_id) 7015 { 7016 uint32_t vid_idx, vid_bit; 7017 7018 if (vlan_id > ETH_VLAN_ID_MAX) 7019 return 0; 7020 7021 vid_idx = I40E_VFTA_IDX(vlan_id); 7022 vid_bit = I40E_VFTA_BIT(vlan_id); 7023 7024 if (vsi->vfta[vid_idx] & vid_bit) 7025 return 1; 7026 else 7027 return 0; 7028 } 7029 7030 static void 7031 i40e_store_vlan_filter(struct i40e_vsi *vsi, 7032 uint16_t vlan_id, bool on) 7033 { 7034 uint32_t vid_idx, vid_bit; 7035 7036 vid_idx = I40E_VFTA_IDX(vlan_id); 7037 vid_bit = I40E_VFTA_BIT(vlan_id); 7038 7039 if (on) 7040 vsi->vfta[vid_idx] |= vid_bit; 7041 else 7042 vsi->vfta[vid_idx] &= ~vid_bit; 7043 } 7044 7045 void 7046 i40e_set_vlan_filter(struct i40e_vsi *vsi, 7047 uint16_t vlan_id, bool on) 7048 { 7049 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7050 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0}; 7051 int ret; 7052 7053 if (vlan_id > ETH_VLAN_ID_MAX) 7054 return; 7055 7056 i40e_store_vlan_filter(vsi, vlan_id, on); 7057 7058 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id) 7059 return; 7060 7061 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id); 7062 7063 if (on) { 7064 ret = i40e_aq_add_vlan(hw, vsi->seid, 7065 &vlan_data, 1, NULL); 7066 if (ret != I40E_SUCCESS) 7067 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 7068 } else { 7069 ret = i40e_aq_remove_vlan(hw, vsi->seid, 7070 &vlan_data, 1, NULL); 7071 if (ret != I40E_SUCCESS) 7072 PMD_DRV_LOG(ERR, 7073 "Failed to remove vlan filter"); 7074 } 7075 } 7076 7077 /** 7078 * Find all vlan options for specific mac addr, 7079 * return with actual vlan found. 7080 */ 7081 int 7082 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi, 7083 struct i40e_macvlan_filter *mv_f, 7084 int num, struct rte_ether_addr *addr) 7085 { 7086 int i; 7087 uint32_t j, k; 7088 7089 /** 7090 * Not to use i40e_find_vlan_filter to decrease the loop time, 7091 * although the code looks complex. 7092 */ 7093 if (num < vsi->vlan_num) 7094 return I40E_ERR_PARAM; 7095 7096 i = 0; 7097 for (j = 0; j < I40E_VFTA_SIZE; j++) { 7098 if (vsi->vfta[j]) { 7099 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) { 7100 if (vsi->vfta[j] & (1 << k)) { 7101 if (i > num - 1) { 7102 PMD_DRV_LOG(ERR, 7103 "vlan number doesn't match"); 7104 return I40E_ERR_PARAM; 7105 } 7106 rte_memcpy(&mv_f[i].macaddr, 7107 addr, ETH_ADDR_LEN); 7108 mv_f[i].vlan_id = 7109 j * I40E_UINT32_BIT_SIZE + k; 7110 i++; 7111 } 7112 } 7113 } 7114 } 7115 return I40E_SUCCESS; 7116 } 7117 7118 static inline int 7119 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi, 7120 struct i40e_macvlan_filter *mv_f, 7121 int num, 7122 uint16_t vlan) 7123 { 7124 int i = 0; 7125 struct i40e_mac_filter *f; 7126 7127 if (num < vsi->mac_num) 7128 return I40E_ERR_PARAM; 7129 7130 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7131 if (i > num - 1) { 7132 PMD_DRV_LOG(ERR, "buffer number not match"); 7133 return I40E_ERR_PARAM; 7134 } 7135 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr, 7136 ETH_ADDR_LEN); 7137 mv_f[i].vlan_id = vlan; 7138 mv_f[i].filter_type = f->mac_info.filter_type; 7139 i++; 7140 } 7141 7142 return I40E_SUCCESS; 7143 } 7144 7145 static int 7146 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi) 7147 { 7148 int i, j, num; 7149 struct i40e_mac_filter *f; 7150 struct i40e_macvlan_filter *mv_f; 7151 int ret = I40E_SUCCESS; 7152 7153 if (vsi == NULL || vsi->mac_num == 0) 7154 return I40E_ERR_PARAM; 7155 7156 /* Case that no vlan is set */ 7157 if (vsi->vlan_num == 0) 7158 num = vsi->mac_num; 7159 else 7160 num = vsi->mac_num * vsi->vlan_num; 7161 7162 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0); 7163 if (mv_f == NULL) { 7164 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7165 return I40E_ERR_NO_MEMORY; 7166 } 7167 7168 i = 0; 7169 if (vsi->vlan_num == 0) { 7170 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7171 rte_memcpy(&mv_f[i].macaddr, 7172 &f->mac_info.mac_addr, ETH_ADDR_LEN); 7173 mv_f[i].filter_type = f->mac_info.filter_type; 7174 mv_f[i].vlan_id = 0; 7175 i++; 7176 } 7177 } else { 7178 TAILQ_FOREACH(f, &vsi->mac_list, next) { 7179 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i], 7180 vsi->vlan_num, &f->mac_info.mac_addr); 7181 if (ret != I40E_SUCCESS) 7182 goto DONE; 7183 for (j = i; j < i + vsi->vlan_num; j++) 7184 mv_f[j].filter_type = f->mac_info.filter_type; 7185 i += vsi->vlan_num; 7186 } 7187 } 7188 7189 ret = i40e_remove_macvlan_filters(vsi, mv_f, num); 7190 DONE: 7191 rte_free(mv_f); 7192 7193 return ret; 7194 } 7195 7196 int 7197 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan) 7198 { 7199 struct i40e_macvlan_filter *mv_f; 7200 int mac_num; 7201 int ret = I40E_SUCCESS; 7202 7203 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID) 7204 return I40E_ERR_PARAM; 7205 7206 /* If it's already set, just return */ 7207 if (i40e_find_vlan_filter(vsi,vlan)) 7208 return I40E_SUCCESS; 7209 7210 mac_num = vsi->mac_num; 7211 7212 if (mac_num == 0) { 7213 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr"); 7214 return I40E_ERR_PARAM; 7215 } 7216 7217 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0); 7218 7219 if (mv_f == NULL) { 7220 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7221 return I40E_ERR_NO_MEMORY; 7222 } 7223 7224 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan); 7225 7226 if (ret != I40E_SUCCESS) 7227 goto DONE; 7228 7229 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num); 7230 7231 if (ret != I40E_SUCCESS) 7232 goto DONE; 7233 7234 i40e_set_vlan_filter(vsi, vlan, 1); 7235 7236 vsi->vlan_num++; 7237 ret = I40E_SUCCESS; 7238 DONE: 7239 rte_free(mv_f); 7240 return ret; 7241 } 7242 7243 int 7244 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan) 7245 { 7246 struct i40e_macvlan_filter *mv_f; 7247 int mac_num; 7248 int ret = I40E_SUCCESS; 7249 7250 /** 7251 * Vlan 0 is the generic filter for untagged packets 7252 * and can't be removed. 7253 */ 7254 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID) 7255 return I40E_ERR_PARAM; 7256 7257 /* If can't find it, just return */ 7258 if (!i40e_find_vlan_filter(vsi, vlan)) 7259 return I40E_ERR_PARAM; 7260 7261 mac_num = vsi->mac_num; 7262 7263 if (mac_num == 0) { 7264 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr"); 7265 return I40E_ERR_PARAM; 7266 } 7267 7268 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0); 7269 7270 if (mv_f == NULL) { 7271 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7272 return I40E_ERR_NO_MEMORY; 7273 } 7274 7275 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan); 7276 7277 if (ret != I40E_SUCCESS) 7278 goto DONE; 7279 7280 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num); 7281 7282 if (ret != I40E_SUCCESS) 7283 goto DONE; 7284 7285 /* This is last vlan to remove, replace all mac filter with vlan 0 */ 7286 if (vsi->vlan_num == 1) { 7287 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0); 7288 if (ret != I40E_SUCCESS) 7289 goto DONE; 7290 7291 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num); 7292 if (ret != I40E_SUCCESS) 7293 goto DONE; 7294 } 7295 7296 i40e_set_vlan_filter(vsi, vlan, 0); 7297 7298 vsi->vlan_num--; 7299 ret = I40E_SUCCESS; 7300 DONE: 7301 rte_free(mv_f); 7302 return ret; 7303 } 7304 7305 int 7306 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter) 7307 { 7308 struct i40e_mac_filter *f; 7309 struct i40e_macvlan_filter *mv_f; 7310 int i, vlan_num = 0; 7311 int ret = I40E_SUCCESS; 7312 7313 /* If it's add and we've config it, return */ 7314 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr); 7315 if (f != NULL) 7316 return I40E_SUCCESS; 7317 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) || 7318 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) { 7319 7320 /** 7321 * If vlan_num is 0, that's the first time to add mac, 7322 * set mask for vlan_id 0. 7323 */ 7324 if (vsi->vlan_num == 0) { 7325 i40e_set_vlan_filter(vsi, 0, 1); 7326 vsi->vlan_num = 1; 7327 } 7328 vlan_num = vsi->vlan_num; 7329 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) || 7330 (mac_filter->filter_type == RTE_MAC_HASH_MATCH)) 7331 vlan_num = 1; 7332 7333 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0); 7334 if (mv_f == NULL) { 7335 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7336 return I40E_ERR_NO_MEMORY; 7337 } 7338 7339 for (i = 0; i < vlan_num; i++) { 7340 mv_f[i].filter_type = mac_filter->filter_type; 7341 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr, 7342 ETH_ADDR_LEN); 7343 } 7344 7345 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH || 7346 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) { 7347 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, 7348 &mac_filter->mac_addr); 7349 if (ret != I40E_SUCCESS) 7350 goto DONE; 7351 } 7352 7353 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num); 7354 if (ret != I40E_SUCCESS) 7355 goto DONE; 7356 7357 /* Add the mac addr into mac list */ 7358 f = rte_zmalloc("macv_filter", sizeof(*f), 0); 7359 if (f == NULL) { 7360 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7361 ret = I40E_ERR_NO_MEMORY; 7362 goto DONE; 7363 } 7364 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr, 7365 ETH_ADDR_LEN); 7366 f->mac_info.filter_type = mac_filter->filter_type; 7367 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 7368 vsi->mac_num++; 7369 7370 ret = I40E_SUCCESS; 7371 DONE: 7372 rte_free(mv_f); 7373 7374 return ret; 7375 } 7376 7377 int 7378 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr) 7379 { 7380 struct i40e_mac_filter *f; 7381 struct i40e_macvlan_filter *mv_f; 7382 int i, vlan_num; 7383 enum rte_mac_filter_type filter_type; 7384 int ret = I40E_SUCCESS; 7385 7386 /* Can't find it, return an error */ 7387 f = i40e_find_mac_filter(vsi, addr); 7388 if (f == NULL) 7389 return I40E_ERR_PARAM; 7390 7391 vlan_num = vsi->vlan_num; 7392 filter_type = f->mac_info.filter_type; 7393 if (filter_type == RTE_MACVLAN_PERFECT_MATCH || 7394 filter_type == RTE_MACVLAN_HASH_MATCH) { 7395 if (vlan_num == 0) { 7396 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0"); 7397 return I40E_ERR_PARAM; 7398 } 7399 } else if (filter_type == RTE_MAC_PERFECT_MATCH || 7400 filter_type == RTE_MAC_HASH_MATCH) 7401 vlan_num = 1; 7402 7403 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0); 7404 if (mv_f == NULL) { 7405 PMD_DRV_LOG(ERR, "failed to allocate memory"); 7406 return I40E_ERR_NO_MEMORY; 7407 } 7408 7409 for (i = 0; i < vlan_num; i++) { 7410 mv_f[i].filter_type = filter_type; 7411 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr, 7412 ETH_ADDR_LEN); 7413 } 7414 if (filter_type == RTE_MACVLAN_PERFECT_MATCH || 7415 filter_type == RTE_MACVLAN_HASH_MATCH) { 7416 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr); 7417 if (ret != I40E_SUCCESS) 7418 goto DONE; 7419 } 7420 7421 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num); 7422 if (ret != I40E_SUCCESS) 7423 goto DONE; 7424 7425 /* Remove the mac addr into mac list */ 7426 TAILQ_REMOVE(&vsi->mac_list, f, next); 7427 rte_free(f); 7428 vsi->mac_num--; 7429 7430 ret = I40E_SUCCESS; 7431 DONE: 7432 rte_free(mv_f); 7433 return ret; 7434 } 7435 7436 /* Configure hash enable flags for RSS */ 7437 uint64_t 7438 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags) 7439 { 7440 uint64_t hena = 0; 7441 int i; 7442 7443 if (!flags) 7444 return hena; 7445 7446 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) { 7447 if (flags & (1ULL << i)) 7448 hena |= adapter->pctypes_tbl[i]; 7449 } 7450 7451 return hena; 7452 } 7453 7454 /* Parse the hash enable flags */ 7455 uint64_t 7456 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags) 7457 { 7458 uint64_t rss_hf = 0; 7459 7460 if (!flags) 7461 return rss_hf; 7462 int i; 7463 7464 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) { 7465 if (flags & adapter->pctypes_tbl[i]) 7466 rss_hf |= (1ULL << i); 7467 } 7468 return rss_hf; 7469 } 7470 7471 /* Disable RSS */ 7472 static void 7473 i40e_pf_disable_rss(struct i40e_pf *pf) 7474 { 7475 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7476 7477 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); 7478 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); 7479 I40E_WRITE_FLUSH(hw); 7480 } 7481 7482 int 7483 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len) 7484 { 7485 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 7486 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7487 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ? 7488 I40E_VFQF_HKEY_MAX_INDEX : 7489 I40E_PFQF_HKEY_MAX_INDEX; 7490 int ret = 0; 7491 7492 if (!key || key_len == 0) { 7493 PMD_DRV_LOG(DEBUG, "No key to be configured"); 7494 return 0; 7495 } else if (key_len != (key_idx + 1) * 7496 sizeof(uint32_t)) { 7497 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 7498 return -EINVAL; 7499 } 7500 7501 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 7502 struct i40e_aqc_get_set_rss_key_data *key_dw = 7503 (struct i40e_aqc_get_set_rss_key_data *)key; 7504 7505 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw); 7506 if (ret) 7507 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ"); 7508 } else { 7509 uint32_t *hash_key = (uint32_t *)key; 7510 uint16_t i; 7511 7512 if (vsi->type == I40E_VSI_SRIOV) { 7513 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) 7514 I40E_WRITE_REG( 7515 hw, 7516 I40E_VFQF_HKEY1(i, vsi->user_param), 7517 hash_key[i]); 7518 7519 } else { 7520 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) 7521 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), 7522 hash_key[i]); 7523 } 7524 I40E_WRITE_FLUSH(hw); 7525 } 7526 7527 return ret; 7528 } 7529 7530 static int 7531 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len) 7532 { 7533 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 7534 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 7535 uint32_t reg; 7536 int ret; 7537 7538 if (!key || !key_len) 7539 return 0; 7540 7541 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 7542 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id, 7543 (struct i40e_aqc_get_set_rss_key_data *)key); 7544 if (ret) { 7545 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ"); 7546 return ret; 7547 } 7548 } else { 7549 uint32_t *key_dw = (uint32_t *)key; 7550 uint16_t i; 7551 7552 if (vsi->type == I40E_VSI_SRIOV) { 7553 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) { 7554 reg = I40E_VFQF_HKEY1(i, vsi->user_param); 7555 key_dw[i] = i40e_read_rx_ctl(hw, reg); 7556 } 7557 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * 7558 sizeof(uint32_t); 7559 } else { 7560 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) { 7561 reg = I40E_PFQF_HKEY(i); 7562 key_dw[i] = i40e_read_rx_ctl(hw, reg); 7563 } 7564 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 7565 sizeof(uint32_t); 7566 } 7567 } 7568 return 0; 7569 } 7570 7571 static int 7572 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf) 7573 { 7574 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7575 uint64_t hena; 7576 int ret; 7577 7578 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key, 7579 rss_conf->rss_key_len); 7580 if (ret) 7581 return ret; 7582 7583 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf); 7584 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); 7585 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); 7586 I40E_WRITE_FLUSH(hw); 7587 7588 return 0; 7589 } 7590 7591 static int 7592 i40e_dev_rss_hash_update(struct rte_eth_dev *dev, 7593 struct rte_eth_rss_conf *rss_conf) 7594 { 7595 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7597 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask; 7598 uint64_t hena; 7599 7600 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); 7601 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; 7602 7603 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */ 7604 if (rss_hf != 0) /* Enable RSS */ 7605 return -EINVAL; 7606 return 0; /* Nothing to do */ 7607 } 7608 /* RSS enabled */ 7609 if (rss_hf == 0) /* Disable RSS */ 7610 return -EINVAL; 7611 7612 return i40e_hw_rss_hash_set(pf, rss_conf); 7613 } 7614 7615 static int 7616 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 7617 struct rte_eth_rss_conf *rss_conf) 7618 { 7619 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 7620 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7621 uint64_t hena; 7622 int ret; 7623 7624 if (!rss_conf) 7625 return -EINVAL; 7626 7627 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key, 7628 &rss_conf->rss_key_len); 7629 if (ret) 7630 return ret; 7631 7632 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)); 7633 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32; 7634 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena); 7635 7636 return 0; 7637 } 7638 7639 static int 7640 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag) 7641 { 7642 switch (filter_type) { 7643 case RTE_TUNNEL_FILTER_IMAC_IVLAN: 7644 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN; 7645 break; 7646 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID: 7647 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID; 7648 break; 7649 case RTE_TUNNEL_FILTER_IMAC_TENID: 7650 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID; 7651 break; 7652 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC: 7653 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC; 7654 break; 7655 case ETH_TUNNEL_FILTER_IMAC: 7656 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC; 7657 break; 7658 case ETH_TUNNEL_FILTER_OIP: 7659 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP; 7660 break; 7661 case ETH_TUNNEL_FILTER_IIP: 7662 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP; 7663 break; 7664 default: 7665 PMD_DRV_LOG(ERR, "invalid tunnel filter type"); 7666 return -EINVAL; 7667 } 7668 7669 return 0; 7670 } 7671 7672 /* Convert tunnel filter structure */ 7673 static int 7674 i40e_tunnel_filter_convert( 7675 struct i40e_aqc_cloud_filters_element_bb *cld_filter, 7676 struct i40e_tunnel_filter *tunnel_filter) 7677 { 7678 rte_ether_addr_copy((struct rte_ether_addr *) 7679 &cld_filter->element.outer_mac, 7680 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac); 7681 rte_ether_addr_copy((struct rte_ether_addr *) 7682 &cld_filter->element.inner_mac, 7683 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac); 7684 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan; 7685 if ((rte_le_to_cpu_16(cld_filter->element.flags) & 7686 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) == 7687 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) 7688 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6; 7689 else 7690 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4; 7691 tunnel_filter->input.flags = cld_filter->element.flags; 7692 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id; 7693 tunnel_filter->queue = cld_filter->element.queue_number; 7694 rte_memcpy(tunnel_filter->input.general_fields, 7695 cld_filter->general_fields, 7696 sizeof(cld_filter->general_fields)); 7697 7698 return 0; 7699 } 7700 7701 /* Check if there exists the tunnel filter */ 7702 struct i40e_tunnel_filter * 7703 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule, 7704 const struct i40e_tunnel_filter_input *input) 7705 { 7706 int ret; 7707 7708 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input); 7709 if (ret < 0) 7710 return NULL; 7711 7712 return tunnel_rule->hash_map[ret]; 7713 } 7714 7715 /* Add a tunnel filter into the SW list */ 7716 static int 7717 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf, 7718 struct i40e_tunnel_filter *tunnel_filter) 7719 { 7720 struct i40e_tunnel_rule *rule = &pf->tunnel; 7721 int ret; 7722 7723 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input); 7724 if (ret < 0) { 7725 PMD_DRV_LOG(ERR, 7726 "Failed to insert tunnel filter to hash table %d!", 7727 ret); 7728 return ret; 7729 } 7730 rule->hash_map[ret] = tunnel_filter; 7731 7732 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules); 7733 7734 return 0; 7735 } 7736 7737 /* Delete a tunnel filter from the SW list */ 7738 int 7739 i40e_sw_tunnel_filter_del(struct i40e_pf *pf, 7740 struct i40e_tunnel_filter_input *input) 7741 { 7742 struct i40e_tunnel_rule *rule = &pf->tunnel; 7743 struct i40e_tunnel_filter *tunnel_filter; 7744 int ret; 7745 7746 ret = rte_hash_del_key(rule->hash_table, input); 7747 if (ret < 0) { 7748 PMD_DRV_LOG(ERR, 7749 "Failed to delete tunnel filter to hash table %d!", 7750 ret); 7751 return ret; 7752 } 7753 tunnel_filter = rule->hash_map[ret]; 7754 rule->hash_map[ret] = NULL; 7755 7756 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules); 7757 rte_free(tunnel_filter); 7758 7759 return 0; 7760 } 7761 7762 int 7763 i40e_dev_tunnel_filter_set(struct i40e_pf *pf, 7764 struct rte_eth_tunnel_filter_conf *tunnel_filter, 7765 uint8_t add) 7766 { 7767 uint16_t ip_type; 7768 uint32_t ipv4_addr, ipv4_addr_le; 7769 uint8_t i, tun_type = 0; 7770 /* internal varialbe to convert ipv6 byte order */ 7771 uint32_t convert_ipv6[4]; 7772 int val, ret = 0; 7773 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7774 struct i40e_vsi *vsi = pf->main_vsi; 7775 struct i40e_aqc_cloud_filters_element_bb *cld_filter; 7776 struct i40e_aqc_cloud_filters_element_bb *pfilter; 7777 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 7778 struct i40e_tunnel_filter *tunnel, *node; 7779 struct i40e_tunnel_filter check_filter; /* Check if filter exists */ 7780 7781 cld_filter = rte_zmalloc("tunnel_filter", 7782 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), 7783 0); 7784 7785 if (NULL == cld_filter) { 7786 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 7787 return -ENOMEM; 7788 } 7789 pfilter = cld_filter; 7790 7791 rte_ether_addr_copy(&tunnel_filter->outer_mac, 7792 (struct rte_ether_addr *)&pfilter->element.outer_mac); 7793 rte_ether_addr_copy(&tunnel_filter->inner_mac, 7794 (struct rte_ether_addr *)&pfilter->element.inner_mac); 7795 7796 pfilter->element.inner_vlan = 7797 rte_cpu_to_le_16(tunnel_filter->inner_vlan); 7798 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) { 7799 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4; 7800 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr); 7801 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr); 7802 rte_memcpy(&pfilter->element.ipaddr.v4.data, 7803 &ipv4_addr_le, 7804 sizeof(pfilter->element.ipaddr.v4.data)); 7805 } else { 7806 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6; 7807 for (i = 0; i < 4; i++) { 7808 convert_ipv6[i] = 7809 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i])); 7810 } 7811 rte_memcpy(&pfilter->element.ipaddr.v6.data, 7812 &convert_ipv6, 7813 sizeof(pfilter->element.ipaddr.v6.data)); 7814 } 7815 7816 /* check tunneled type */ 7817 switch (tunnel_filter->tunnel_type) { 7818 case RTE_TUNNEL_TYPE_VXLAN: 7819 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN; 7820 break; 7821 case RTE_TUNNEL_TYPE_NVGRE: 7822 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC; 7823 break; 7824 case RTE_TUNNEL_TYPE_IP_IN_GRE: 7825 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; 7826 break; 7827 case RTE_TUNNEL_TYPE_VXLAN_GPE: 7828 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE; 7829 break; 7830 default: 7831 /* Other tunnel types is not supported. */ 7832 PMD_DRV_LOG(ERR, "tunnel type is not supported."); 7833 rte_free(cld_filter); 7834 return -EINVAL; 7835 } 7836 7837 val = i40e_dev_get_filter_type(tunnel_filter->filter_type, 7838 &pfilter->element.flags); 7839 if (val < 0) { 7840 rte_free(cld_filter); 7841 return -EINVAL; 7842 } 7843 7844 pfilter->element.flags |= rte_cpu_to_le_16( 7845 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | 7846 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)); 7847 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id); 7848 pfilter->element.queue_number = 7849 rte_cpu_to_le_16(tunnel_filter->queue_id); 7850 7851 /* Check if there is the filter in SW list */ 7852 memset(&check_filter, 0, sizeof(check_filter)); 7853 i40e_tunnel_filter_convert(cld_filter, &check_filter); 7854 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input); 7855 if (add && node) { 7856 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!"); 7857 rte_free(cld_filter); 7858 return -EINVAL; 7859 } 7860 7861 if (!add && !node) { 7862 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!"); 7863 rte_free(cld_filter); 7864 return -EINVAL; 7865 } 7866 7867 if (add) { 7868 ret = i40e_aq_add_cloud_filters(hw, 7869 vsi->seid, &cld_filter->element, 1); 7870 if (ret < 0) { 7871 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter."); 7872 rte_free(cld_filter); 7873 return -ENOTSUP; 7874 } 7875 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0); 7876 if (tunnel == NULL) { 7877 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 7878 rte_free(cld_filter); 7879 return -ENOMEM; 7880 } 7881 7882 rte_memcpy(tunnel, &check_filter, sizeof(check_filter)); 7883 ret = i40e_sw_tunnel_filter_insert(pf, tunnel); 7884 if (ret < 0) 7885 rte_free(tunnel); 7886 } else { 7887 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 7888 &cld_filter->element, 1); 7889 if (ret < 0) { 7890 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter."); 7891 rte_free(cld_filter); 7892 return -ENOTSUP; 7893 } 7894 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 7895 } 7896 7897 rte_free(cld_filter); 7898 return ret; 7899 } 7900 7901 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48 7902 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4 7903 #define I40E_TR_GENEVE_KEY_MASK 0x8 7904 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40 7905 #define I40E_TR_GRE_KEY_MASK 0x400 7906 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800 7907 #define I40E_TR_GRE_NO_KEY_MASK 0x8000 7908 7909 static enum 7910 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf) 7911 { 7912 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7913 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7914 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7915 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7916 enum i40e_status_code status = I40E_SUCCESS; 7917 7918 if (pf->support_multi_driver) { 7919 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported."); 7920 return I40E_NOT_SUPPORTED; 7921 } 7922 7923 memset(&filter_replace, 0, 7924 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7925 memset(&filter_replace_buf, 0, 7926 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7927 7928 /* create L1 filter */ 7929 filter_replace.old_filter_type = 7930 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; 7931 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11; 7932 filter_replace.tr_bit = 0; 7933 7934 /* Prepare the buffer, 3 entries */ 7935 filter_replace_buf.data[0] = 7936 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 7937 filter_replace_buf.data[0] |= 7938 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7939 filter_replace_buf.data[2] = 0xFF; 7940 filter_replace_buf.data[3] = 0xFF; 7941 filter_replace_buf.data[4] = 7942 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 7943 filter_replace_buf.data[4] |= 7944 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7945 filter_replace_buf.data[7] = 0xF0; 7946 filter_replace_buf.data[8] 7947 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0; 7948 filter_replace_buf.data[8] |= 7949 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7950 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK | 7951 I40E_TR_GENEVE_KEY_MASK | 7952 I40E_TR_GENERIC_UDP_TUNNEL_MASK; 7953 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK | 7954 I40E_TR_GRE_KEY_WITH_XSUM_MASK | 7955 I40E_TR_GRE_NO_KEY_MASK) >> 8; 7956 7957 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 7958 &filter_replace_buf); 7959 if (!status && (filter_replace.old_filter_type != 7960 filter_replace.new_filter_type)) 7961 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 7962 " original: 0x%x, new: 0x%x", 7963 dev->device->name, 7964 filter_replace.old_filter_type, 7965 filter_replace.new_filter_type); 7966 7967 return status; 7968 } 7969 7970 static enum 7971 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) 7972 { 7973 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 7974 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 7975 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 7976 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 7977 enum i40e_status_code status = I40E_SUCCESS; 7978 7979 if (pf->support_multi_driver) { 7980 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 7981 return I40E_NOT_SUPPORTED; 7982 } 7983 7984 /* For MPLSoUDP */ 7985 memset(&filter_replace, 0, 7986 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 7987 memset(&filter_replace_buf, 0, 7988 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 7989 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | 7990 I40E_AQC_MIRROR_CLOUD_FILTER; 7991 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP; 7992 filter_replace.new_filter_type = 7993 I40E_AQC_ADD_CLOUD_FILTER_0X11; 7994 /* Prepare the buffer, 2 entries */ 7995 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 7996 filter_replace_buf.data[0] |= 7997 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 7998 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11; 7999 filter_replace_buf.data[4] |= 8000 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8001 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8002 &filter_replace_buf); 8003 if (status < 0) 8004 return status; 8005 if (filter_replace.old_filter_type != 8006 filter_replace.new_filter_type) 8007 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8008 " original: 0x%x, new: 0x%x", 8009 dev->device->name, 8010 filter_replace.old_filter_type, 8011 filter_replace.new_filter_type); 8012 8013 /* For MPLSoGRE */ 8014 memset(&filter_replace, 0, 8015 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8016 memset(&filter_replace_buf, 0, 8017 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8018 8019 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | 8020 I40E_AQC_MIRROR_CLOUD_FILTER; 8021 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC; 8022 filter_replace.new_filter_type = 8023 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8024 /* Prepare the buffer, 2 entries */ 8025 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8026 filter_replace_buf.data[0] |= 8027 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8028 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11; 8029 filter_replace_buf.data[4] |= 8030 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8031 8032 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8033 &filter_replace_buf); 8034 if (!status && (filter_replace.old_filter_type != 8035 filter_replace.new_filter_type)) 8036 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8037 " original: 0x%x, new: 0x%x", 8038 dev->device->name, 8039 filter_replace.old_filter_type, 8040 filter_replace.new_filter_type); 8041 8042 return status; 8043 } 8044 8045 static enum i40e_status_code 8046 i40e_replace_gtp_l1_filter(struct i40e_pf *pf) 8047 { 8048 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 8049 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 8050 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8051 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 8052 enum i40e_status_code status = I40E_SUCCESS; 8053 8054 if (pf->support_multi_driver) { 8055 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported."); 8056 return I40E_NOT_SUPPORTED; 8057 } 8058 8059 /* For GTP-C */ 8060 memset(&filter_replace, 0, 8061 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8062 memset(&filter_replace_buf, 0, 8063 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8064 /* create L1 filter */ 8065 filter_replace.old_filter_type = 8066 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; 8067 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12; 8068 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 | 8069 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8070 /* Prepare the buffer, 2 entries */ 8071 filter_replace_buf.data[0] = 8072 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 8073 filter_replace_buf.data[0] |= 8074 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8075 filter_replace_buf.data[2] = 0xFF; 8076 filter_replace_buf.data[3] = 0xFF; 8077 filter_replace_buf.data[4] = 8078 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 8079 filter_replace_buf.data[4] |= 8080 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8081 filter_replace_buf.data[6] = 0xFF; 8082 filter_replace_buf.data[7] = 0xFF; 8083 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8084 &filter_replace_buf); 8085 if (status < 0) 8086 return status; 8087 if (filter_replace.old_filter_type != 8088 filter_replace.new_filter_type) 8089 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 8090 " original: 0x%x, new: 0x%x", 8091 dev->device->name, 8092 filter_replace.old_filter_type, 8093 filter_replace.new_filter_type); 8094 8095 /* for GTP-U */ 8096 memset(&filter_replace, 0, 8097 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8098 memset(&filter_replace_buf, 0, 8099 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8100 /* create L1 filter */ 8101 filter_replace.old_filter_type = 8102 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY; 8103 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13; 8104 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 | 8105 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8106 /* Prepare the buffer, 2 entries */ 8107 filter_replace_buf.data[0] = 8108 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; 8109 filter_replace_buf.data[0] |= 8110 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8111 filter_replace_buf.data[2] = 0xFF; 8112 filter_replace_buf.data[3] = 0xFF; 8113 filter_replace_buf.data[4] = 8114 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; 8115 filter_replace_buf.data[4] |= 8116 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8117 filter_replace_buf.data[6] = 0xFF; 8118 filter_replace_buf.data[7] = 0xFF; 8119 8120 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8121 &filter_replace_buf); 8122 if (!status && (filter_replace.old_filter_type != 8123 filter_replace.new_filter_type)) 8124 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 8125 " original: 0x%x, new: 0x%x", 8126 dev->device->name, 8127 filter_replace.old_filter_type, 8128 filter_replace.new_filter_type); 8129 8130 return status; 8131 } 8132 8133 static enum 8134 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf) 8135 { 8136 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 8137 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 8138 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8139 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 8140 enum i40e_status_code status = I40E_SUCCESS; 8141 8142 if (pf->support_multi_driver) { 8143 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 8144 return I40E_NOT_SUPPORTED; 8145 } 8146 8147 /* for GTP-C */ 8148 memset(&filter_replace, 0, 8149 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8150 memset(&filter_replace_buf, 0, 8151 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8152 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 8153 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN; 8154 filter_replace.new_filter_type = 8155 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8156 /* Prepare the buffer, 2 entries */ 8157 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12; 8158 filter_replace_buf.data[0] |= 8159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8160 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8161 filter_replace_buf.data[4] |= 8162 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8163 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8164 &filter_replace_buf); 8165 if (status < 0) 8166 return status; 8167 if (filter_replace.old_filter_type != 8168 filter_replace.new_filter_type) 8169 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8170 " original: 0x%x, new: 0x%x", 8171 dev->device->name, 8172 filter_replace.old_filter_type, 8173 filter_replace.new_filter_type); 8174 8175 /* for GTP-U */ 8176 memset(&filter_replace, 0, 8177 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 8178 memset(&filter_replace_buf, 0, 8179 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 8180 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 8181 filter_replace.old_filter_type = 8182 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID; 8183 filter_replace.new_filter_type = 8184 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8185 /* Prepare the buffer, 2 entries */ 8186 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13; 8187 filter_replace_buf.data[0] |= 8188 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8189 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 8190 filter_replace_buf.data[4] |= 8191 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 8192 8193 status = i40e_aq_replace_cloud_filters(hw, &filter_replace, 8194 &filter_replace_buf); 8195 if (!status && (filter_replace.old_filter_type != 8196 filter_replace.new_filter_type)) 8197 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 8198 " original: 0x%x, new: 0x%x", 8199 dev->device->name, 8200 filter_replace.old_filter_type, 8201 filter_replace.new_filter_type); 8202 8203 return status; 8204 } 8205 8206 int 8207 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, 8208 struct i40e_tunnel_filter_conf *tunnel_filter, 8209 uint8_t add) 8210 { 8211 uint16_t ip_type; 8212 uint32_t ipv4_addr, ipv4_addr_le; 8213 uint8_t i, tun_type = 0; 8214 /* internal variable to convert ipv6 byte order */ 8215 uint32_t convert_ipv6[4]; 8216 int val, ret = 0; 8217 struct i40e_pf_vf *vf = NULL; 8218 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8219 struct i40e_vsi *vsi; 8220 struct i40e_aqc_cloud_filters_element_bb *cld_filter; 8221 struct i40e_aqc_cloud_filters_element_bb *pfilter; 8222 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 8223 struct i40e_tunnel_filter *tunnel, *node; 8224 struct i40e_tunnel_filter check_filter; /* Check if filter exists */ 8225 uint32_t teid_le; 8226 bool big_buffer = 0; 8227 8228 cld_filter = rte_zmalloc("tunnel_filter", 8229 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), 8230 0); 8231 8232 if (cld_filter == NULL) { 8233 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 8234 return -ENOMEM; 8235 } 8236 pfilter = cld_filter; 8237 8238 rte_ether_addr_copy(&tunnel_filter->outer_mac, 8239 (struct rte_ether_addr *)&pfilter->element.outer_mac); 8240 rte_ether_addr_copy(&tunnel_filter->inner_mac, 8241 (struct rte_ether_addr *)&pfilter->element.inner_mac); 8242 8243 pfilter->element.inner_vlan = 8244 rte_cpu_to_le_16(tunnel_filter->inner_vlan); 8245 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) { 8246 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4; 8247 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr); 8248 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr); 8249 rte_memcpy(&pfilter->element.ipaddr.v4.data, 8250 &ipv4_addr_le, 8251 sizeof(pfilter->element.ipaddr.v4.data)); 8252 } else { 8253 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6; 8254 for (i = 0; i < 4; i++) { 8255 convert_ipv6[i] = 8256 rte_cpu_to_le_32(rte_be_to_cpu_32( 8257 tunnel_filter->ip_addr.ipv6_addr[i])); 8258 } 8259 rte_memcpy(&pfilter->element.ipaddr.v6.data, 8260 &convert_ipv6, 8261 sizeof(pfilter->element.ipaddr.v6.data)); 8262 } 8263 8264 /* check tunneled type */ 8265 switch (tunnel_filter->tunnel_type) { 8266 case I40E_TUNNEL_TYPE_VXLAN: 8267 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN; 8268 break; 8269 case I40E_TUNNEL_TYPE_NVGRE: 8270 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC; 8271 break; 8272 case I40E_TUNNEL_TYPE_IP_IN_GRE: 8273 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; 8274 break; 8275 case I40E_TUNNEL_TYPE_MPLSoUDP: 8276 if (!pf->mpls_replace_flag) { 8277 i40e_replace_mpls_l1_filter(pf); 8278 i40e_replace_mpls_cloud_filter(pf); 8279 pf->mpls_replace_flag = 1; 8280 } 8281 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8282 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = 8283 teid_le >> 4; 8284 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = 8285 (teid_le & 0xF) << 12; 8286 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = 8287 0x40; 8288 big_buffer = 1; 8289 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP; 8290 break; 8291 case I40E_TUNNEL_TYPE_MPLSoGRE: 8292 if (!pf->mpls_replace_flag) { 8293 i40e_replace_mpls_l1_filter(pf); 8294 i40e_replace_mpls_cloud_filter(pf); 8295 pf->mpls_replace_flag = 1; 8296 } 8297 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8298 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = 8299 teid_le >> 4; 8300 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = 8301 (teid_le & 0xF) << 12; 8302 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = 8303 0x0; 8304 big_buffer = 1; 8305 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE; 8306 break; 8307 case I40E_TUNNEL_TYPE_GTPC: 8308 if (!pf->gtp_replace_flag) { 8309 i40e_replace_gtp_l1_filter(pf); 8310 i40e_replace_gtp_cloud_filter(pf); 8311 pf->gtp_replace_flag = 1; 8312 } 8313 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8314 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] = 8315 (teid_le >> 16) & 0xFFFF; 8316 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] = 8317 teid_le & 0xFFFF; 8318 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] = 8319 0x0; 8320 big_buffer = 1; 8321 break; 8322 case I40E_TUNNEL_TYPE_GTPU: 8323 if (!pf->gtp_replace_flag) { 8324 i40e_replace_gtp_l1_filter(pf); 8325 i40e_replace_gtp_cloud_filter(pf); 8326 pf->gtp_replace_flag = 1; 8327 } 8328 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8329 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] = 8330 (teid_le >> 16) & 0xFFFF; 8331 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] = 8332 teid_le & 0xFFFF; 8333 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] = 8334 0x0; 8335 big_buffer = 1; 8336 break; 8337 case I40E_TUNNEL_TYPE_QINQ: 8338 if (!pf->qinq_replace_flag) { 8339 ret = i40e_cloud_filter_qinq_create(pf); 8340 if (ret < 0) 8341 PMD_DRV_LOG(DEBUG, 8342 "QinQ tunnel filter already created."); 8343 pf->qinq_replace_flag = 1; 8344 } 8345 /* Add in the General fields the values of 8346 * the Outer and Inner VLAN 8347 * Big Buffer should be set, see changes in 8348 * i40e_aq_add_cloud_filters 8349 */ 8350 pfilter->general_fields[0] = tunnel_filter->inner_vlan; 8351 pfilter->general_fields[1] = tunnel_filter->outer_vlan; 8352 big_buffer = 1; 8353 break; 8354 default: 8355 /* Other tunnel types is not supported. */ 8356 PMD_DRV_LOG(ERR, "tunnel type is not supported."); 8357 rte_free(cld_filter); 8358 return -EINVAL; 8359 } 8360 8361 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP) 8362 pfilter->element.flags = 8363 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8364 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE) 8365 pfilter->element.flags = 8366 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8367 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC) 8368 pfilter->element.flags = 8369 I40E_AQC_ADD_CLOUD_FILTER_0X11; 8370 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU) 8371 pfilter->element.flags = 8372 I40E_AQC_ADD_CLOUD_FILTER_0X12; 8373 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ) 8374 pfilter->element.flags |= 8375 I40E_AQC_ADD_CLOUD_FILTER_0X10; 8376 else { 8377 val = i40e_dev_get_filter_type(tunnel_filter->filter_type, 8378 &pfilter->element.flags); 8379 if (val < 0) { 8380 rte_free(cld_filter); 8381 return -EINVAL; 8382 } 8383 } 8384 8385 pfilter->element.flags |= rte_cpu_to_le_16( 8386 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | 8387 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)); 8388 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id); 8389 pfilter->element.queue_number = 8390 rte_cpu_to_le_16(tunnel_filter->queue_id); 8391 8392 if (!tunnel_filter->is_to_vf) 8393 vsi = pf->main_vsi; 8394 else { 8395 if (tunnel_filter->vf_id >= pf->vf_num) { 8396 PMD_DRV_LOG(ERR, "Invalid argument."); 8397 rte_free(cld_filter); 8398 return -EINVAL; 8399 } 8400 vf = &pf->vfs[tunnel_filter->vf_id]; 8401 vsi = vf->vsi; 8402 } 8403 8404 /* Check if there is the filter in SW list */ 8405 memset(&check_filter, 0, sizeof(check_filter)); 8406 i40e_tunnel_filter_convert(cld_filter, &check_filter); 8407 check_filter.is_to_vf = tunnel_filter->is_to_vf; 8408 check_filter.vf_id = tunnel_filter->vf_id; 8409 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input); 8410 if (add && node) { 8411 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!"); 8412 rte_free(cld_filter); 8413 return -EINVAL; 8414 } 8415 8416 if (!add && !node) { 8417 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!"); 8418 rte_free(cld_filter); 8419 return -EINVAL; 8420 } 8421 8422 if (add) { 8423 if (big_buffer) 8424 ret = i40e_aq_add_cloud_filters_bb(hw, 8425 vsi->seid, cld_filter, 1); 8426 else 8427 ret = i40e_aq_add_cloud_filters(hw, 8428 vsi->seid, &cld_filter->element, 1); 8429 if (ret < 0) { 8430 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter."); 8431 rte_free(cld_filter); 8432 return -ENOTSUP; 8433 } 8434 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0); 8435 if (tunnel == NULL) { 8436 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 8437 rte_free(cld_filter); 8438 return -ENOMEM; 8439 } 8440 8441 rte_memcpy(tunnel, &check_filter, sizeof(check_filter)); 8442 ret = i40e_sw_tunnel_filter_insert(pf, tunnel); 8443 if (ret < 0) 8444 rte_free(tunnel); 8445 } else { 8446 if (big_buffer) 8447 ret = i40e_aq_rem_cloud_filters_bb( 8448 hw, vsi->seid, cld_filter, 1); 8449 else 8450 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 8451 &cld_filter->element, 1); 8452 if (ret < 0) { 8453 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter."); 8454 rte_free(cld_filter); 8455 return -ENOTSUP; 8456 } 8457 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 8458 } 8459 8460 rte_free(cld_filter); 8461 return ret; 8462 } 8463 8464 static int 8465 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port) 8466 { 8467 uint8_t i; 8468 8469 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { 8470 if (pf->vxlan_ports[i] == port) 8471 return i; 8472 } 8473 8474 return -1; 8475 } 8476 8477 static int 8478 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type) 8479 { 8480 int idx, ret; 8481 uint8_t filter_idx; 8482 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8483 8484 idx = i40e_get_vxlan_port_idx(pf, port); 8485 8486 /* Check if port already exists */ 8487 if (idx >= 0) { 8488 PMD_DRV_LOG(ERR, "Port %d already offloaded", port); 8489 return -EINVAL; 8490 } 8491 8492 /* Now check if there is space to add the new port */ 8493 idx = i40e_get_vxlan_port_idx(pf, 0); 8494 if (idx < 0) { 8495 PMD_DRV_LOG(ERR, 8496 "Maximum number of UDP ports reached, not adding port %d", 8497 port); 8498 return -ENOSPC; 8499 } 8500 8501 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type, 8502 &filter_idx, NULL); 8503 if (ret < 0) { 8504 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port); 8505 return -1; 8506 } 8507 8508 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d", 8509 port, filter_idx); 8510 8511 /* New port: add it and mark its index in the bitmap */ 8512 pf->vxlan_ports[idx] = port; 8513 pf->vxlan_bitmap |= (1 << idx); 8514 8515 if (!(pf->flags & I40E_FLAG_VXLAN)) 8516 pf->flags |= I40E_FLAG_VXLAN; 8517 8518 return 0; 8519 } 8520 8521 static int 8522 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port) 8523 { 8524 int idx; 8525 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8526 8527 if (!(pf->flags & I40E_FLAG_VXLAN)) { 8528 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured."); 8529 return -EINVAL; 8530 } 8531 8532 idx = i40e_get_vxlan_port_idx(pf, port); 8533 8534 if (idx < 0) { 8535 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port); 8536 return -EINVAL; 8537 } 8538 8539 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) { 8540 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port); 8541 return -1; 8542 } 8543 8544 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d", 8545 port, idx); 8546 8547 pf->vxlan_ports[idx] = 0; 8548 pf->vxlan_bitmap &= ~(1 << idx); 8549 8550 if (!pf->vxlan_bitmap) 8551 pf->flags &= ~I40E_FLAG_VXLAN; 8552 8553 return 0; 8554 } 8555 8556 /* Add UDP tunneling port */ 8557 static int 8558 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8559 struct rte_eth_udp_tunnel *udp_tunnel) 8560 { 8561 int ret = 0; 8562 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8563 8564 if (udp_tunnel == NULL) 8565 return -EINVAL; 8566 8567 switch (udp_tunnel->prot_type) { 8568 case RTE_TUNNEL_TYPE_VXLAN: 8569 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port, 8570 I40E_AQC_TUNNEL_TYPE_VXLAN); 8571 break; 8572 case RTE_TUNNEL_TYPE_VXLAN_GPE: 8573 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port, 8574 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE); 8575 break; 8576 case RTE_TUNNEL_TYPE_GENEVE: 8577 case RTE_TUNNEL_TYPE_TEREDO: 8578 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8579 ret = -1; 8580 break; 8581 8582 default: 8583 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8584 ret = -1; 8585 break; 8586 } 8587 8588 return ret; 8589 } 8590 8591 /* Remove UDP tunneling port */ 8592 static int 8593 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8594 struct rte_eth_udp_tunnel *udp_tunnel) 8595 { 8596 int ret = 0; 8597 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8598 8599 if (udp_tunnel == NULL) 8600 return -EINVAL; 8601 8602 switch (udp_tunnel->prot_type) { 8603 case RTE_TUNNEL_TYPE_VXLAN: 8604 case RTE_TUNNEL_TYPE_VXLAN_GPE: 8605 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port); 8606 break; 8607 case RTE_TUNNEL_TYPE_GENEVE: 8608 case RTE_TUNNEL_TYPE_TEREDO: 8609 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8610 ret = -1; 8611 break; 8612 default: 8613 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8614 ret = -1; 8615 break; 8616 } 8617 8618 return ret; 8619 } 8620 8621 /* Calculate the maximum number of contiguous PF queues that are configured */ 8622 static int 8623 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf) 8624 { 8625 struct rte_eth_dev_data *data = pf->dev_data; 8626 int i, num; 8627 struct i40e_rx_queue *rxq; 8628 8629 num = 0; 8630 for (i = 0; i < pf->lan_nb_qps; i++) { 8631 rxq = data->rx_queues[i]; 8632 if (rxq && rxq->q_set) 8633 num++; 8634 else 8635 break; 8636 } 8637 8638 return num; 8639 } 8640 8641 /* Configure RSS */ 8642 static int 8643 i40e_pf_config_rss(struct i40e_pf *pf) 8644 { 8645 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 8646 struct rte_eth_rss_conf rss_conf; 8647 uint32_t i, lut = 0; 8648 uint16_t j, num; 8649 8650 /* 8651 * If both VMDQ and RSS enabled, not all of PF queues are configured. 8652 * It's necessary to calculate the actual PF queues that are configured. 8653 */ 8654 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 8655 num = i40e_pf_calc_configured_queues_num(pf); 8656 else 8657 num = pf->dev_data->nb_rx_queues; 8658 8659 num = RTE_MIN(num, I40E_MAX_Q_PER_TC); 8660 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured", 8661 num); 8662 8663 if (num == 0) { 8664 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS"); 8665 return -ENOTSUP; 8666 } 8667 8668 if (pf->adapter->rss_reta_updated == 0) { 8669 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 8670 if (j == num) 8671 j = 0; 8672 lut = (lut << 8) | (j & ((0x1 << 8673 hw->func_caps.rss_table_entry_width) - 1)); 8674 if ((i & 3) == 3) 8675 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), 8676 rte_bswap32(lut)); 8677 } 8678 } 8679 8680 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf; 8681 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) { 8682 i40e_pf_disable_rss(pf); 8683 return 0; 8684 } 8685 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < 8686 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 8687 /* Random default keys */ 8688 static uint32_t rss_key_default[] = {0x6b793944, 8689 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8, 8690 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605, 8691 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581}; 8692 8693 rss_conf.rss_key = (uint8_t *)rss_key_default; 8694 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 8695 sizeof(uint32_t); 8696 } 8697 8698 return i40e_hw_rss_hash_set(pf, &rss_conf); 8699 } 8700 8701 static int 8702 i40e_tunnel_filter_param_check(struct i40e_pf *pf, 8703 struct rte_eth_tunnel_filter_conf *filter) 8704 { 8705 if (pf == NULL || filter == NULL) { 8706 PMD_DRV_LOG(ERR, "Invalid parameter"); 8707 return -EINVAL; 8708 } 8709 8710 if (filter->queue_id >= pf->dev_data->nb_rx_queues) { 8711 PMD_DRV_LOG(ERR, "Invalid queue ID"); 8712 return -EINVAL; 8713 } 8714 8715 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) { 8716 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID"); 8717 return -EINVAL; 8718 } 8719 8720 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) && 8721 (rte_is_zero_ether_addr(&filter->outer_mac))) { 8722 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address"); 8723 return -EINVAL; 8724 } 8725 8726 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) && 8727 (rte_is_zero_ether_addr(&filter->inner_mac))) { 8728 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address"); 8729 return -EINVAL; 8730 } 8731 8732 return 0; 8733 } 8734 8735 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000 8736 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) 8737 static int 8738 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) 8739 { 8740 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 8741 uint32_t val, reg; 8742 int ret = -EINVAL; 8743 8744 if (pf->support_multi_driver) { 8745 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported"); 8746 return -ENOTSUP; 8747 } 8748 8749 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)); 8750 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val); 8751 8752 if (len == 3) { 8753 reg = val | I40E_GL_PRS_FVBM_MSK_ENA; 8754 } else if (len == 4) { 8755 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA; 8756 } else { 8757 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len); 8758 return ret; 8759 } 8760 8761 if (reg != val) { 8762 ret = i40e_aq_debug_write_global_register(hw, 8763 I40E_GL_PRS_FVBM(2), 8764 reg, NULL); 8765 if (ret != 0) 8766 return ret; 8767 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed " 8768 "with value 0x%08x", 8769 I40E_GL_PRS_FVBM(2), reg); 8770 } else { 8771 ret = 0; 8772 } 8773 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x", 8774 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2))); 8775 8776 return ret; 8777 } 8778 8779 static int 8780 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg) 8781 { 8782 int ret = -EINVAL; 8783 8784 if (!hw || !cfg) 8785 return -EINVAL; 8786 8787 switch (cfg->cfg_type) { 8788 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN: 8789 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len); 8790 break; 8791 default: 8792 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type); 8793 break; 8794 } 8795 8796 return ret; 8797 } 8798 8799 static int 8800 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev, 8801 enum rte_filter_op filter_op, 8802 void *arg) 8803 { 8804 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8805 int ret = I40E_ERR_PARAM; 8806 8807 switch (filter_op) { 8808 case RTE_ETH_FILTER_SET: 8809 ret = i40e_dev_global_config_set(hw, 8810 (struct rte_eth_global_cfg *)arg); 8811 break; 8812 default: 8813 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 8814 break; 8815 } 8816 8817 return ret; 8818 } 8819 8820 static int 8821 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, 8822 enum rte_filter_op filter_op, 8823 void *arg) 8824 { 8825 struct rte_eth_tunnel_filter_conf *filter; 8826 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 8827 int ret = I40E_SUCCESS; 8828 8829 filter = (struct rte_eth_tunnel_filter_conf *)(arg); 8830 8831 if (i40e_tunnel_filter_param_check(pf, filter) < 0) 8832 return I40E_ERR_PARAM; 8833 8834 switch (filter_op) { 8835 case RTE_ETH_FILTER_NOP: 8836 if (!(pf->flags & I40E_FLAG_VXLAN)) 8837 ret = I40E_NOT_SUPPORTED; 8838 break; 8839 case RTE_ETH_FILTER_ADD: 8840 ret = i40e_dev_tunnel_filter_set(pf, filter, 1); 8841 break; 8842 case RTE_ETH_FILTER_DELETE: 8843 ret = i40e_dev_tunnel_filter_set(pf, filter, 0); 8844 break; 8845 default: 8846 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 8847 ret = I40E_ERR_PARAM; 8848 break; 8849 } 8850 8851 return ret; 8852 } 8853 8854 static int 8855 i40e_pf_config_mq_rx(struct i40e_pf *pf) 8856 { 8857 int ret = 0; 8858 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode; 8859 8860 /* RSS setup */ 8861 if (mq_mode & ETH_MQ_RX_RSS_FLAG) 8862 ret = i40e_pf_config_rss(pf); 8863 else 8864 i40e_pf_disable_rss(pf); 8865 8866 return ret; 8867 } 8868 8869 /* Get the symmetric hash enable configurations per port */ 8870 static void 8871 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable) 8872 { 8873 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); 8874 8875 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0; 8876 } 8877 8878 /* Set the symmetric hash enable configurations per port */ 8879 static void 8880 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable) 8881 { 8882 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0); 8883 8884 if (enable > 0) { 8885 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) { 8886 PMD_DRV_LOG(INFO, 8887 "Symmetric hash has already been enabled"); 8888 return; 8889 } 8890 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK; 8891 } else { 8892 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) { 8893 PMD_DRV_LOG(INFO, 8894 "Symmetric hash has already been disabled"); 8895 return; 8896 } 8897 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK; 8898 } 8899 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg); 8900 I40E_WRITE_FLUSH(hw); 8901 } 8902 8903 /* 8904 * Get global configurations of hash function type and symmetric hash enable 8905 * per flow type (pctype). Note that global configuration means it affects all 8906 * the ports on the same NIC. 8907 */ 8908 static int 8909 i40e_get_hash_filter_global_config(struct i40e_hw *hw, 8910 struct rte_eth_hash_global_conf *g_cfg) 8911 { 8912 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back; 8913 uint32_t reg; 8914 uint16_t i, j; 8915 8916 memset(g_cfg, 0, sizeof(*g_cfg)); 8917 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 8918 if (reg & I40E_GLQF_CTL_HTOEP_MASK) 8919 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ; 8920 else 8921 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR; 8922 PMD_DRV_LOG(DEBUG, "Hash function is %s", 8923 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); 8924 8925 /* 8926 * As i40e supports less than 64 flow types, only first 64 bits need to 8927 * be checked. 8928 */ 8929 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { 8930 g_cfg->valid_bit_mask[i] = 0ULL; 8931 g_cfg->sym_hash_enable_mask[i] = 0ULL; 8932 } 8933 8934 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask; 8935 8936 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) { 8937 if (!adapter->pctypes_tbl[i]) 8938 continue; 8939 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 8940 j < I40E_FILTER_PCTYPE_MAX; j++) { 8941 if (adapter->pctypes_tbl[i] & (1ULL << j)) { 8942 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j)); 8943 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) { 8944 g_cfg->sym_hash_enable_mask[0] |= 8945 (1ULL << i); 8946 } 8947 } 8948 } 8949 } 8950 8951 return 0; 8952 } 8953 8954 static int 8955 i40e_hash_global_config_check(const struct i40e_adapter *adapter, 8956 const struct rte_eth_hash_global_conf *g_cfg) 8957 { 8958 uint32_t i; 8959 uint64_t mask0, i40e_mask = adapter->flow_types_mask; 8960 8961 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ && 8962 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR && 8963 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) { 8964 PMD_DRV_LOG(ERR, "Unsupported hash function type %d", 8965 g_cfg->hash_func); 8966 return -EINVAL; 8967 } 8968 8969 /* 8970 * As i40e supports less than 64 flow types, only first 64 bits need to 8971 * be checked. 8972 */ 8973 mask0 = g_cfg->valid_bit_mask[0]; 8974 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { 8975 if (i == 0) { 8976 /* Check if any unsupported flow type configured */ 8977 if ((mask0 | i40e_mask) ^ i40e_mask) 8978 goto mask_err; 8979 } else { 8980 if (g_cfg->valid_bit_mask[i]) 8981 goto mask_err; 8982 } 8983 } 8984 8985 return 0; 8986 8987 mask_err: 8988 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured"); 8989 8990 return -EINVAL; 8991 } 8992 8993 /* 8994 * Set global configurations of hash function type and symmetric hash enable 8995 * per flow type (pctype). Note any modifying global configuration will affect 8996 * all the ports on the same NIC. 8997 */ 8998 static int 8999 i40e_set_hash_filter_global_config(struct i40e_hw *hw, 9000 struct rte_eth_hash_global_conf *g_cfg) 9001 { 9002 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back; 9003 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 9004 int ret; 9005 uint16_t i, j; 9006 uint32_t reg; 9007 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask; 9008 9009 if (pf->support_multi_driver) { 9010 PMD_DRV_LOG(ERR, "Hash global configuration is not supported."); 9011 return -ENOTSUP; 9012 } 9013 9014 /* Check the input parameters */ 9015 ret = i40e_hash_global_config_check(adapter, g_cfg); 9016 if (ret < 0) 9017 return ret; 9018 9019 /* 9020 * As i40e supports less than 64 flow types, only first 64 bits need to 9021 * be configured. 9022 */ 9023 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) { 9024 if (mask0 & (1UL << i)) { 9025 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ? 9026 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; 9027 9028 for (j = I40E_FILTER_PCTYPE_INVALID + 1; 9029 j < I40E_FILTER_PCTYPE_MAX; j++) { 9030 if (adapter->pctypes_tbl[i] & (1ULL << j)) 9031 i40e_write_global_rx_ctl(hw, 9032 I40E_GLQF_HSYM(j), 9033 reg); 9034 } 9035 } 9036 } 9037 9038 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL); 9039 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) { 9040 /* Toeplitz */ 9041 if (reg & I40E_GLQF_CTL_HTOEP_MASK) { 9042 PMD_DRV_LOG(DEBUG, 9043 "Hash function already set to Toeplitz"); 9044 goto out; 9045 } 9046 reg |= I40E_GLQF_CTL_HTOEP_MASK; 9047 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { 9048 /* Simple XOR */ 9049 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) { 9050 PMD_DRV_LOG(DEBUG, 9051 "Hash function already set to Simple XOR"); 9052 goto out; 9053 } 9054 reg &= ~I40E_GLQF_CTL_HTOEP_MASK; 9055 } else 9056 /* Use the default, and keep it as it is */ 9057 goto out; 9058 9059 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg); 9060 9061 out: 9062 I40E_WRITE_FLUSH(hw); 9063 9064 return 0; 9065 } 9066 9067 /** 9068 * Valid input sets for hash and flow director filters per PCTYPE 9069 */ 9070 static uint64_t 9071 i40e_get_valid_input_set(enum i40e_filter_pctype pctype, 9072 enum rte_filter_type filter) 9073 { 9074 uint64_t valid; 9075 9076 static const uint64_t valid_hash_inset_table[] = { 9077 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9078 I40E_INSET_DMAC | I40E_INSET_SMAC | 9079 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9080 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC | 9081 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS | 9082 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9083 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9084 I40E_INSET_FLEX_PAYLOAD, 9085 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9086 I40E_INSET_DMAC | I40E_INSET_SMAC | 9087 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9088 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9089 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9090 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9091 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9092 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9093 I40E_INSET_FLEX_PAYLOAD, 9094 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9095 I40E_INSET_DMAC | I40E_INSET_SMAC | 9096 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9097 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9098 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9099 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9100 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9101 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9102 I40E_INSET_FLEX_PAYLOAD, 9103 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9104 I40E_INSET_DMAC | I40E_INSET_SMAC | 9105 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9106 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9107 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9108 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9109 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9110 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9111 I40E_INSET_FLEX_PAYLOAD, 9112 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9113 I40E_INSET_DMAC | I40E_INSET_SMAC | 9114 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9115 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9116 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9117 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9118 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9119 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9120 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD, 9121 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9122 I40E_INSET_DMAC | I40E_INSET_SMAC | 9123 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9124 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9125 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9126 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9127 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9128 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9129 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD, 9130 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9131 I40E_INSET_DMAC | I40E_INSET_SMAC | 9132 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9133 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9134 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9135 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9136 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9137 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9138 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD, 9139 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9140 I40E_INSET_DMAC | I40E_INSET_SMAC | 9141 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9142 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS | 9143 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL | 9144 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID | 9145 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9146 I40E_INSET_FLEX_PAYLOAD, 9147 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9148 I40E_INSET_DMAC | I40E_INSET_SMAC | 9149 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9150 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9151 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9152 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC | 9153 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC | 9154 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD, 9155 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9156 I40E_INSET_DMAC | I40E_INSET_SMAC | 9157 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9158 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9159 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9160 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9161 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9162 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD, 9163 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9164 I40E_INSET_DMAC | I40E_INSET_SMAC | 9165 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9166 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9167 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9168 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9169 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9170 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9171 I40E_INSET_FLEX_PAYLOAD, 9172 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9173 I40E_INSET_DMAC | I40E_INSET_SMAC | 9174 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9175 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9176 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9177 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9178 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9179 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9180 I40E_INSET_FLEX_PAYLOAD, 9181 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9182 I40E_INSET_DMAC | I40E_INSET_SMAC | 9183 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9184 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9185 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9186 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9187 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9188 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9189 I40E_INSET_FLEX_PAYLOAD, 9190 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9191 I40E_INSET_DMAC | I40E_INSET_SMAC | 9192 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9193 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9194 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9195 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9196 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9197 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS | 9198 I40E_INSET_FLEX_PAYLOAD, 9199 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9200 I40E_INSET_DMAC | I40E_INSET_SMAC | 9201 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9202 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9203 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9204 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9205 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT | 9206 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT | 9207 I40E_INSET_FLEX_PAYLOAD, 9208 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9209 I40E_INSET_DMAC | I40E_INSET_SMAC | 9210 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9211 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC | 9212 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR | 9213 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC | 9214 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID | 9215 I40E_INSET_FLEX_PAYLOAD, 9216 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9217 I40E_INSET_DMAC | I40E_INSET_SMAC | 9218 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9219 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE | 9220 I40E_INSET_FLEX_PAYLOAD, 9221 }; 9222 9223 /** 9224 * Flow director supports only fields defined in 9225 * union rte_eth_fdir_flow. 9226 */ 9227 static const uint64_t valid_fdir_inset_table[] = { 9228 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9229 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9230 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9231 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO | 9232 I40E_INSET_IPV4_TTL, 9233 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9234 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9235 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9236 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9237 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9238 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9239 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9240 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9241 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9242 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9243 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9244 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9245 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9246 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9247 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9248 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9249 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9250 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9251 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9252 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9253 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9254 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9255 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9256 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9257 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9258 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9259 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9260 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9261 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL | 9262 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9263 I40E_INSET_SCTP_VT, 9264 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9265 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9266 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9267 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO | 9268 I40E_INSET_IPV4_TTL, 9269 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9270 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9271 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9272 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR | 9273 I40E_INSET_IPV6_HOP_LIMIT, 9274 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9275 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9276 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9277 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9278 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9279 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9280 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9281 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9282 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9283 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9284 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9285 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9286 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9287 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9288 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9289 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9290 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9291 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9292 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9293 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9294 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9295 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9296 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9297 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9298 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9299 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9300 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9301 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9302 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT | 9303 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9304 I40E_INSET_SCTP_VT, 9305 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9306 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9307 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9308 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR | 9309 I40E_INSET_IPV6_HOP_LIMIT, 9310 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9311 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | 9312 I40E_INSET_LAST_ETHER_TYPE, 9313 }; 9314 9315 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) 9316 return 0; 9317 if (filter == RTE_ETH_FILTER_HASH) 9318 valid = valid_hash_inset_table[pctype]; 9319 else 9320 valid = valid_fdir_inset_table[pctype]; 9321 9322 return valid; 9323 } 9324 9325 /** 9326 * Validate if the input set is allowed for a specific PCTYPE 9327 */ 9328 int 9329 i40e_validate_input_set(enum i40e_filter_pctype pctype, 9330 enum rte_filter_type filter, uint64_t inset) 9331 { 9332 uint64_t valid; 9333 9334 valid = i40e_get_valid_input_set(pctype, filter); 9335 if (inset & (~valid)) 9336 return -EINVAL; 9337 9338 return 0; 9339 } 9340 9341 /* default input set fields combination per pctype */ 9342 uint64_t 9343 i40e_get_default_input_set(uint16_t pctype) 9344 { 9345 static const uint64_t default_inset_table[] = { 9346 [I40E_FILTER_PCTYPE_FRAG_IPV4] = 9347 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, 9348 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = 9349 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9350 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9351 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] = 9352 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9353 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9354 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] = 9355 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9356 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9357 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = 9358 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9359 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9360 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] = 9361 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9362 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9363 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = 9364 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST | 9365 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9366 I40E_INSET_SCTP_VT, 9367 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = 9368 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST, 9369 [I40E_FILTER_PCTYPE_FRAG_IPV6] = 9370 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, 9371 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = 9372 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9373 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9374 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] = 9375 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9376 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9377 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] = 9378 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9379 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9380 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = 9381 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9382 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9383 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] = 9384 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9385 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT, 9386 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = 9387 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST | 9388 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT | 9389 I40E_INSET_SCTP_VT, 9390 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = 9391 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST, 9392 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = 9393 I40E_INSET_LAST_ETHER_TYPE, 9394 }; 9395 9396 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) 9397 return 0; 9398 9399 return default_inset_table[pctype]; 9400 } 9401 9402 /** 9403 * Parse the input set from index to logical bit masks 9404 */ 9405 static int 9406 i40e_parse_input_set(uint64_t *inset, 9407 enum i40e_filter_pctype pctype, 9408 enum rte_eth_input_set_field *field, 9409 uint16_t size) 9410 { 9411 uint16_t i, j; 9412 int ret = -EINVAL; 9413 9414 static const struct { 9415 enum rte_eth_input_set_field field; 9416 uint64_t inset; 9417 } inset_convert_table[] = { 9418 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE}, 9419 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC}, 9420 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC}, 9421 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER}, 9422 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER}, 9423 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE}, 9424 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC}, 9425 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST}, 9426 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS}, 9427 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO}, 9428 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL}, 9429 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC}, 9430 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST}, 9431 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC}, 9432 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER, 9433 I40E_INSET_IPV6_NEXT_HDR}, 9434 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS, 9435 I40E_INSET_IPV6_HOP_LIMIT}, 9436 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT}, 9437 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT}, 9438 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT}, 9439 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT}, 9440 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT}, 9441 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT}, 9442 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG, 9443 I40E_INSET_SCTP_VT}, 9444 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC, 9445 I40E_INSET_TUNNEL_DMAC}, 9446 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN, 9447 I40E_INSET_VLAN_TUNNEL}, 9448 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY, 9449 I40E_INSET_TUNNEL_ID}, 9450 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID}, 9451 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD, 9452 I40E_INSET_FLEX_PAYLOAD_W1}, 9453 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD, 9454 I40E_INSET_FLEX_PAYLOAD_W2}, 9455 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD, 9456 I40E_INSET_FLEX_PAYLOAD_W3}, 9457 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD, 9458 I40E_INSET_FLEX_PAYLOAD_W4}, 9459 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD, 9460 I40E_INSET_FLEX_PAYLOAD_W5}, 9461 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD, 9462 I40E_INSET_FLEX_PAYLOAD_W6}, 9463 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD, 9464 I40E_INSET_FLEX_PAYLOAD_W7}, 9465 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD, 9466 I40E_INSET_FLEX_PAYLOAD_W8}, 9467 }; 9468 9469 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX) 9470 return ret; 9471 9472 /* Only one item allowed for default or all */ 9473 if (size == 1) { 9474 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) { 9475 *inset = i40e_get_default_input_set(pctype); 9476 return 0; 9477 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) { 9478 *inset = I40E_INSET_NONE; 9479 return 0; 9480 } 9481 } 9482 9483 for (i = 0, *inset = 0; i < size; i++) { 9484 for (j = 0; j < RTE_DIM(inset_convert_table); j++) { 9485 if (field[i] == inset_convert_table[j].field) { 9486 *inset |= inset_convert_table[j].inset; 9487 break; 9488 } 9489 } 9490 9491 /* It contains unsupported input set, return immediately */ 9492 if (j == RTE_DIM(inset_convert_table)) 9493 return ret; 9494 } 9495 9496 return 0; 9497 } 9498 9499 /** 9500 * Translate the input set from bit masks to register aware bit masks 9501 * and vice versa 9502 */ 9503 uint64_t 9504 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input) 9505 { 9506 uint64_t val = 0; 9507 uint16_t i; 9508 9509 struct inset_map { 9510 uint64_t inset; 9511 uint64_t inset_reg; 9512 }; 9513 9514 static const struct inset_map inset_map_common[] = { 9515 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC}, 9516 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC}, 9517 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN}, 9518 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN}, 9519 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE}, 9520 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS}, 9521 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6}, 9522 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6}, 9523 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC}, 9524 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR}, 9525 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT}, 9526 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT}, 9527 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT}, 9528 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG}, 9529 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID}, 9530 {I40E_INSET_TUNNEL_DMAC, 9531 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC}, 9532 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4}, 9533 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6}, 9534 {I40E_INSET_TUNNEL_SRC_PORT, 9535 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT}, 9536 {I40E_INSET_TUNNEL_DST_PORT, 9537 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT}, 9538 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN}, 9539 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1}, 9540 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2}, 9541 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3}, 9542 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4}, 9543 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5}, 9544 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6}, 9545 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7}, 9546 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8}, 9547 }; 9548 9549 /* some different registers map in x722*/ 9550 static const struct inset_map inset_map_diff_x722[] = { 9551 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4}, 9552 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4}, 9553 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO}, 9554 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL}, 9555 }; 9556 9557 static const struct inset_map inset_map_diff_not_x722[] = { 9558 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4}, 9559 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4}, 9560 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO}, 9561 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL}, 9562 }; 9563 9564 if (input == 0) 9565 return val; 9566 9567 /* Translate input set to register aware inset */ 9568 if (type == I40E_MAC_X722) { 9569 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) { 9570 if (input & inset_map_diff_x722[i].inset) 9571 val |= inset_map_diff_x722[i].inset_reg; 9572 } 9573 } else { 9574 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) { 9575 if (input & inset_map_diff_not_x722[i].inset) 9576 val |= inset_map_diff_not_x722[i].inset_reg; 9577 } 9578 } 9579 9580 for (i = 0; i < RTE_DIM(inset_map_common); i++) { 9581 if (input & inset_map_common[i].inset) 9582 val |= inset_map_common[i].inset_reg; 9583 } 9584 9585 return val; 9586 } 9587 9588 int 9589 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem) 9590 { 9591 uint8_t i, idx = 0; 9592 uint64_t inset_need_mask = inset; 9593 9594 static const struct { 9595 uint64_t inset; 9596 uint32_t mask; 9597 } inset_mask_map[] = { 9598 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK}, 9599 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0}, 9600 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK}, 9601 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK}, 9602 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK}, 9603 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0}, 9604 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK}, 9605 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK}, 9606 }; 9607 9608 if (!inset || !mask || !nb_elem) 9609 return 0; 9610 9611 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { 9612 /* Clear the inset bit, if no MASK is required, 9613 * for example proto + ttl 9614 */ 9615 if ((inset & inset_mask_map[i].inset) == 9616 inset_mask_map[i].inset && inset_mask_map[i].mask == 0) 9617 inset_need_mask &= ~inset_mask_map[i].inset; 9618 if (!inset_need_mask) 9619 return 0; 9620 } 9621 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) { 9622 if ((inset_need_mask & inset_mask_map[i].inset) == 9623 inset_mask_map[i].inset) { 9624 if (idx >= nb_elem) { 9625 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks"); 9626 return -EINVAL; 9627 } 9628 mask[idx] = inset_mask_map[i].mask; 9629 idx++; 9630 } 9631 } 9632 9633 return idx; 9634 } 9635 9636 void 9637 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) 9638 { 9639 uint32_t reg = i40e_read_rx_ctl(hw, addr); 9640 9641 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg); 9642 if (reg != val) 9643 i40e_write_rx_ctl(hw, addr, val); 9644 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr, 9645 (uint32_t)i40e_read_rx_ctl(hw, addr)); 9646 } 9647 9648 void 9649 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) 9650 { 9651 uint32_t reg = i40e_read_rx_ctl(hw, addr); 9652 struct rte_eth_dev *dev; 9653 9654 dev = ((struct i40e_adapter *)hw->back)->eth_dev; 9655 if (reg != val) { 9656 i40e_write_rx_ctl(hw, addr, val); 9657 PMD_DRV_LOG(WARNING, 9658 "i40e device %s changed global register [0x%08x]." 9659 " original: 0x%08x, new: 0x%08x", 9660 dev->device->name, addr, reg, 9661 (uint32_t)i40e_read_rx_ctl(hw, addr)); 9662 } 9663 } 9664 9665 static void 9666 i40e_filter_input_set_init(struct i40e_pf *pf) 9667 { 9668 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9669 enum i40e_filter_pctype pctype; 9670 uint64_t input_set, inset_reg; 9671 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9672 int num, i; 9673 uint16_t flow_type; 9674 9675 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 9676 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) { 9677 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype); 9678 9679 if (flow_type == RTE_ETH_FLOW_UNKNOWN) 9680 continue; 9681 9682 input_set = i40e_get_default_input_set(pctype); 9683 9684 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9685 I40E_INSET_MASK_NUM_REG); 9686 if (num < 0) 9687 return; 9688 if (pf->support_multi_driver && num > 0) { 9689 PMD_DRV_LOG(ERR, "Input set setting is not supported."); 9690 return; 9691 } 9692 inset_reg = i40e_translate_input_set_reg(hw->mac.type, 9693 input_set); 9694 9695 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 9696 (uint32_t)(inset_reg & UINT32_MAX)); 9697 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 9698 (uint32_t)((inset_reg >> 9699 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9700 if (!pf->support_multi_driver) { 9701 i40e_check_write_global_reg(hw, 9702 I40E_GLQF_HASH_INSET(0, pctype), 9703 (uint32_t)(inset_reg & UINT32_MAX)); 9704 i40e_check_write_global_reg(hw, 9705 I40E_GLQF_HASH_INSET(1, pctype), 9706 (uint32_t)((inset_reg >> 9707 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9708 9709 for (i = 0; i < num; i++) { 9710 i40e_check_write_global_reg(hw, 9711 I40E_GLQF_FD_MSK(i, pctype), 9712 mask_reg[i]); 9713 i40e_check_write_global_reg(hw, 9714 I40E_GLQF_HASH_MSK(i, pctype), 9715 mask_reg[i]); 9716 } 9717 /*clear unused mask registers of the pctype */ 9718 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) { 9719 i40e_check_write_global_reg(hw, 9720 I40E_GLQF_FD_MSK(i, pctype), 9721 0); 9722 i40e_check_write_global_reg(hw, 9723 I40E_GLQF_HASH_MSK(i, pctype), 9724 0); 9725 } 9726 } else { 9727 PMD_DRV_LOG(ERR, "Input set setting is not supported."); 9728 } 9729 I40E_WRITE_FLUSH(hw); 9730 9731 /* store the default input set */ 9732 if (!pf->support_multi_driver) 9733 pf->hash_input_set[pctype] = input_set; 9734 pf->fdir.input_set[pctype] = input_set; 9735 } 9736 } 9737 9738 int 9739 i40e_hash_filter_inset_select(struct i40e_hw *hw, 9740 struct rte_eth_input_set_conf *conf) 9741 { 9742 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf; 9743 enum i40e_filter_pctype pctype; 9744 uint64_t input_set, inset_reg = 0; 9745 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9746 int ret, i, num; 9747 9748 if (!conf) { 9749 PMD_DRV_LOG(ERR, "Invalid pointer"); 9750 return -EFAULT; 9751 } 9752 if (conf->op != RTE_ETH_INPUT_SET_SELECT && 9753 conf->op != RTE_ETH_INPUT_SET_ADD) { 9754 PMD_DRV_LOG(ERR, "Unsupported input set operation"); 9755 return -EINVAL; 9756 } 9757 9758 if (pf->support_multi_driver) { 9759 PMD_DRV_LOG(ERR, "Hash input set setting is not supported."); 9760 return -ENOTSUP; 9761 } 9762 9763 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); 9764 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 9765 PMD_DRV_LOG(ERR, "invalid flow_type input."); 9766 return -EINVAL; 9767 } 9768 9769 if (hw->mac.type == I40E_MAC_X722) { 9770 /* get translated pctype value in fd pctype register */ 9771 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw, 9772 I40E_GLQF_FD_PCTYPES((int)pctype)); 9773 } 9774 9775 ret = i40e_parse_input_set(&input_set, pctype, conf->field, 9776 conf->inset_size); 9777 if (ret) { 9778 PMD_DRV_LOG(ERR, "Failed to parse input set"); 9779 return -EINVAL; 9780 } 9781 9782 if (conf->op == RTE_ETH_INPUT_SET_ADD) { 9783 /* get inset value in register */ 9784 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype)); 9785 inset_reg <<= I40E_32_BIT_WIDTH; 9786 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype)); 9787 input_set |= pf->hash_input_set[pctype]; 9788 } 9789 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9790 I40E_INSET_MASK_NUM_REG); 9791 if (num < 0) 9792 return -EINVAL; 9793 9794 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 9795 9796 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype), 9797 (uint32_t)(inset_reg & UINT32_MAX)); 9798 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), 9799 (uint32_t)((inset_reg >> 9800 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9801 9802 for (i = 0; i < num; i++) 9803 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 9804 mask_reg[i]); 9805 /*clear unused mask registers of the pctype */ 9806 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 9807 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 9808 0); 9809 I40E_WRITE_FLUSH(hw); 9810 9811 pf->hash_input_set[pctype] = input_set; 9812 return 0; 9813 } 9814 9815 int 9816 i40e_fdir_filter_inset_select(struct i40e_pf *pf, 9817 struct rte_eth_input_set_conf *conf) 9818 { 9819 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 9820 enum i40e_filter_pctype pctype; 9821 uint64_t input_set, inset_reg = 0; 9822 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 9823 int ret, i, num; 9824 9825 if (!hw || !conf) { 9826 PMD_DRV_LOG(ERR, "Invalid pointer"); 9827 return -EFAULT; 9828 } 9829 if (conf->op != RTE_ETH_INPUT_SET_SELECT && 9830 conf->op != RTE_ETH_INPUT_SET_ADD) { 9831 PMD_DRV_LOG(ERR, "Unsupported input set operation"); 9832 return -EINVAL; 9833 } 9834 9835 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); 9836 9837 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 9838 PMD_DRV_LOG(ERR, "invalid flow_type input."); 9839 return -EINVAL; 9840 } 9841 9842 ret = i40e_parse_input_set(&input_set, pctype, conf->field, 9843 conf->inset_size); 9844 if (ret) { 9845 PMD_DRV_LOG(ERR, "Failed to parse input set"); 9846 return -EINVAL; 9847 } 9848 9849 /* get inset value in register */ 9850 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1)); 9851 inset_reg <<= I40E_32_BIT_WIDTH; 9852 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0)); 9853 9854 /* Can not change the inset reg for flex payload for fdir, 9855 * it is done by writing I40E_PRTQF_FD_FLXINSET 9856 * in i40e_set_flex_mask_on_pctype. 9857 */ 9858 if (conf->op == RTE_ETH_INPUT_SET_SELECT) 9859 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS; 9860 else 9861 input_set |= pf->fdir.input_set[pctype]; 9862 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 9863 I40E_INSET_MASK_NUM_REG); 9864 if (num < 0) 9865 return -EINVAL; 9866 if (pf->support_multi_driver && num > 0) { 9867 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); 9868 return -ENOTSUP; 9869 } 9870 9871 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 9872 9873 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 9874 (uint32_t)(inset_reg & UINT32_MAX)); 9875 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 9876 (uint32_t)((inset_reg >> 9877 I40E_32_BIT_WIDTH) & UINT32_MAX)); 9878 9879 if (!pf->support_multi_driver) { 9880 for (i = 0; i < num; i++) 9881 i40e_check_write_global_reg(hw, 9882 I40E_GLQF_FD_MSK(i, pctype), 9883 mask_reg[i]); 9884 /*clear unused mask registers of the pctype */ 9885 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 9886 i40e_check_write_global_reg(hw, 9887 I40E_GLQF_FD_MSK(i, pctype), 9888 0); 9889 } else { 9890 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported."); 9891 } 9892 I40E_WRITE_FLUSH(hw); 9893 9894 pf->fdir.input_set[pctype] = input_set; 9895 return 0; 9896 } 9897 9898 static int 9899 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) 9900 { 9901 int ret = 0; 9902 9903 if (!hw || !info) { 9904 PMD_DRV_LOG(ERR, "Invalid pointer"); 9905 return -EFAULT; 9906 } 9907 9908 switch (info->info_type) { 9909 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT: 9910 i40e_get_symmetric_hash_enable_per_port(hw, 9911 &(info->info.enable)); 9912 break; 9913 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG: 9914 ret = i40e_get_hash_filter_global_config(hw, 9915 &(info->info.global_conf)); 9916 break; 9917 default: 9918 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", 9919 info->info_type); 9920 ret = -EINVAL; 9921 break; 9922 } 9923 9924 return ret; 9925 } 9926 9927 static int 9928 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) 9929 { 9930 int ret = 0; 9931 9932 if (!hw || !info) { 9933 PMD_DRV_LOG(ERR, "Invalid pointer"); 9934 return -EFAULT; 9935 } 9936 9937 switch (info->info_type) { 9938 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT: 9939 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable); 9940 break; 9941 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG: 9942 ret = i40e_set_hash_filter_global_config(hw, 9943 &(info->info.global_conf)); 9944 break; 9945 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT: 9946 ret = i40e_hash_filter_inset_select(hw, 9947 &(info->info.input_set_conf)); 9948 break; 9949 9950 default: 9951 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", 9952 info->info_type); 9953 ret = -EINVAL; 9954 break; 9955 } 9956 9957 return ret; 9958 } 9959 9960 /* Operations for hash function */ 9961 static int 9962 i40e_hash_filter_ctrl(struct rte_eth_dev *dev, 9963 enum rte_filter_op filter_op, 9964 void *arg) 9965 { 9966 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 9967 int ret = 0; 9968 9969 switch (filter_op) { 9970 case RTE_ETH_FILTER_NOP: 9971 break; 9972 case RTE_ETH_FILTER_GET: 9973 ret = i40e_hash_filter_get(hw, 9974 (struct rte_eth_hash_filter_info *)arg); 9975 break; 9976 case RTE_ETH_FILTER_SET: 9977 ret = i40e_hash_filter_set(hw, 9978 (struct rte_eth_hash_filter_info *)arg); 9979 break; 9980 default: 9981 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported", 9982 filter_op); 9983 ret = -ENOTSUP; 9984 break; 9985 } 9986 9987 return ret; 9988 } 9989 9990 /* Convert ethertype filter structure */ 9991 static int 9992 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input, 9993 struct i40e_ethertype_filter *filter) 9994 { 9995 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, 9996 RTE_ETHER_ADDR_LEN); 9997 filter->input.ether_type = input->ether_type; 9998 filter->flags = input->flags; 9999 filter->queue = input->queue; 10000 10001 return 0; 10002 } 10003 10004 /* Check if there exists the ehtertype filter */ 10005 struct i40e_ethertype_filter * 10006 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule, 10007 const struct i40e_ethertype_filter_input *input) 10008 { 10009 int ret; 10010 10011 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input); 10012 if (ret < 0) 10013 return NULL; 10014 10015 return ethertype_rule->hash_map[ret]; 10016 } 10017 10018 /* Add ethertype filter in SW list */ 10019 static int 10020 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf, 10021 struct i40e_ethertype_filter *filter) 10022 { 10023 struct i40e_ethertype_rule *rule = &pf->ethertype; 10024 int ret; 10025 10026 ret = rte_hash_add_key(rule->hash_table, &filter->input); 10027 if (ret < 0) { 10028 PMD_DRV_LOG(ERR, 10029 "Failed to insert ethertype filter" 10030 " to hash table %d!", 10031 ret); 10032 return ret; 10033 } 10034 rule->hash_map[ret] = filter; 10035 10036 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules); 10037 10038 return 0; 10039 } 10040 10041 /* Delete ethertype filter in SW list */ 10042 int 10043 i40e_sw_ethertype_filter_del(struct i40e_pf *pf, 10044 struct i40e_ethertype_filter_input *input) 10045 { 10046 struct i40e_ethertype_rule *rule = &pf->ethertype; 10047 struct i40e_ethertype_filter *filter; 10048 int ret; 10049 10050 ret = rte_hash_del_key(rule->hash_table, input); 10051 if (ret < 0) { 10052 PMD_DRV_LOG(ERR, 10053 "Failed to delete ethertype filter" 10054 " to hash table %d!", 10055 ret); 10056 return ret; 10057 } 10058 filter = rule->hash_map[ret]; 10059 rule->hash_map[ret] = NULL; 10060 10061 TAILQ_REMOVE(&rule->ethertype_list, filter, rules); 10062 rte_free(filter); 10063 10064 return 0; 10065 } 10066 10067 /* 10068 * Configure ethertype filter, which can director packet by filtering 10069 * with mac address and ether_type or only ether_type 10070 */ 10071 int 10072 i40e_ethertype_filter_set(struct i40e_pf *pf, 10073 struct rte_eth_ethertype_filter *filter, 10074 bool add) 10075 { 10076 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 10077 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 10078 struct i40e_ethertype_filter *ethertype_filter, *node; 10079 struct i40e_ethertype_filter check_filter; 10080 struct i40e_control_filter_stats stats; 10081 uint16_t flags = 0; 10082 int ret; 10083 10084 if (filter->queue >= pf->dev_data->nb_rx_queues) { 10085 PMD_DRV_LOG(ERR, "Invalid queue ID"); 10086 return -EINVAL; 10087 } 10088 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 10089 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 10090 PMD_DRV_LOG(ERR, 10091 "unsupported ether_type(0x%04x) in control packet filter.", 10092 filter->ether_type); 10093 return -EINVAL; 10094 } 10095 if (filter->ether_type == RTE_ETHER_TYPE_VLAN) 10096 PMD_DRV_LOG(WARNING, 10097 "filter vlan ether_type in first tag is not supported."); 10098 10099 /* Check if there is the filter in SW list */ 10100 memset(&check_filter, 0, sizeof(check_filter)); 10101 i40e_ethertype_filter_convert(filter, &check_filter); 10102 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, 10103 &check_filter.input); 10104 if (add && node) { 10105 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!"); 10106 return -EINVAL; 10107 } 10108 10109 if (!add && !node) { 10110 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!"); 10111 return -EINVAL; 10112 } 10113 10114 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC)) 10115 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 10116 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) 10117 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 10118 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 10119 10120 memset(&stats, 0, sizeof(stats)); 10121 ret = i40e_aq_add_rem_control_packet_filter(hw, 10122 filter->mac_addr.addr_bytes, 10123 filter->ether_type, flags, 10124 pf->main_vsi->seid, 10125 filter->queue, add, &stats, NULL); 10126 10127 PMD_DRV_LOG(INFO, 10128 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u", 10129 ret, stats.mac_etype_used, stats.etype_used, 10130 stats.mac_etype_free, stats.etype_free); 10131 if (ret < 0) 10132 return -ENOSYS; 10133 10134 /* Add or delete a filter in SW list */ 10135 if (add) { 10136 ethertype_filter = rte_zmalloc("ethertype_filter", 10137 sizeof(*ethertype_filter), 0); 10138 if (ethertype_filter == NULL) { 10139 PMD_DRV_LOG(ERR, "Failed to alloc memory."); 10140 return -ENOMEM; 10141 } 10142 10143 rte_memcpy(ethertype_filter, &check_filter, 10144 sizeof(check_filter)); 10145 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter); 10146 if (ret < 0) 10147 rte_free(ethertype_filter); 10148 } else { 10149 ret = i40e_sw_ethertype_filter_del(pf, &node->input); 10150 } 10151 10152 return ret; 10153 } 10154 10155 /* 10156 * Handle operations for ethertype filter. 10157 */ 10158 static int 10159 i40e_ethertype_filter_handle(struct rte_eth_dev *dev, 10160 enum rte_filter_op filter_op, 10161 void *arg) 10162 { 10163 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10164 int ret = 0; 10165 10166 if (filter_op == RTE_ETH_FILTER_NOP) 10167 return ret; 10168 10169 if (arg == NULL) { 10170 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 10171 filter_op); 10172 return -EINVAL; 10173 } 10174 10175 switch (filter_op) { 10176 case RTE_ETH_FILTER_ADD: 10177 ret = i40e_ethertype_filter_set(pf, 10178 (struct rte_eth_ethertype_filter *)arg, 10179 TRUE); 10180 break; 10181 case RTE_ETH_FILTER_DELETE: 10182 ret = i40e_ethertype_filter_set(pf, 10183 (struct rte_eth_ethertype_filter *)arg, 10184 FALSE); 10185 break; 10186 default: 10187 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 10188 ret = -ENOSYS; 10189 break; 10190 } 10191 return ret; 10192 } 10193 10194 static int 10195 i40e_dev_filter_ctrl(struct rte_eth_dev *dev, 10196 enum rte_filter_type filter_type, 10197 enum rte_filter_op filter_op, 10198 void *arg) 10199 { 10200 int ret = 0; 10201 10202 if (dev == NULL) 10203 return -EINVAL; 10204 10205 switch (filter_type) { 10206 case RTE_ETH_FILTER_NONE: 10207 /* For global configuration */ 10208 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg); 10209 break; 10210 case RTE_ETH_FILTER_HASH: 10211 ret = i40e_hash_filter_ctrl(dev, filter_op, arg); 10212 break; 10213 case RTE_ETH_FILTER_MACVLAN: 10214 ret = i40e_mac_filter_handle(dev, filter_op, arg); 10215 break; 10216 case RTE_ETH_FILTER_ETHERTYPE: 10217 ret = i40e_ethertype_filter_handle(dev, filter_op, arg); 10218 break; 10219 case RTE_ETH_FILTER_TUNNEL: 10220 ret = i40e_tunnel_filter_handle(dev, filter_op, arg); 10221 break; 10222 case RTE_ETH_FILTER_FDIR: 10223 ret = i40e_fdir_ctrl_func(dev, filter_op, arg); 10224 break; 10225 case RTE_ETH_FILTER_GENERIC: 10226 if (filter_op != RTE_ETH_FILTER_GET) 10227 return -EINVAL; 10228 *(const void **)arg = &i40e_flow_ops; 10229 break; 10230 default: 10231 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 10232 filter_type); 10233 ret = -EINVAL; 10234 break; 10235 } 10236 10237 return ret; 10238 } 10239 10240 /* 10241 * Check and enable Extended Tag. 10242 * Enabling Extended Tag is important for 40G performance. 10243 */ 10244 static void 10245 i40e_enable_extended_tag(struct rte_eth_dev *dev) 10246 { 10247 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 10248 uint32_t buf = 0; 10249 int ret; 10250 10251 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf), 10252 PCI_DEV_CAP_REG); 10253 if (ret < 0) { 10254 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", 10255 PCI_DEV_CAP_REG); 10256 return; 10257 } 10258 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { 10259 PMD_DRV_LOG(ERR, "Does not support Extended Tag"); 10260 return; 10261 } 10262 10263 buf = 0; 10264 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf), 10265 PCI_DEV_CTRL_REG); 10266 if (ret < 0) { 10267 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", 10268 PCI_DEV_CTRL_REG); 10269 return; 10270 } 10271 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { 10272 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); 10273 return; 10274 } 10275 buf |= PCI_DEV_CTRL_EXT_TAG_MASK; 10276 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf), 10277 PCI_DEV_CTRL_REG); 10278 if (ret < 0) { 10279 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", 10280 PCI_DEV_CTRL_REG); 10281 return; 10282 } 10283 } 10284 10285 /* 10286 * As some registers wouldn't be reset unless a global hardware reset, 10287 * hardware initialization is needed to put those registers into an 10288 * expected initial state. 10289 */ 10290 static void 10291 i40e_hw_init(struct rte_eth_dev *dev) 10292 { 10293 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10294 10295 i40e_enable_extended_tag(dev); 10296 10297 /* clear the PF Queue Filter control register */ 10298 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0); 10299 10300 /* Disable symmetric hash per port */ 10301 i40e_set_symmetric_hash_enable_per_port(hw, 0); 10302 } 10303 10304 /* 10305 * For X722 it is possible to have multiple pctypes mapped to the same flowtype 10306 * however this function will return only one highest pctype index, 10307 * which is not quite correct. This is known problem of i40e driver 10308 * and needs to be fixed later. 10309 */ 10310 enum i40e_filter_pctype 10311 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type) 10312 { 10313 int i; 10314 uint64_t pctype_mask; 10315 10316 if (flow_type < I40E_FLOW_TYPE_MAX) { 10317 pctype_mask = adapter->pctypes_tbl[flow_type]; 10318 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) { 10319 if (pctype_mask & (1ULL << i)) 10320 return (enum i40e_filter_pctype)i; 10321 } 10322 } 10323 return I40E_FILTER_PCTYPE_INVALID; 10324 } 10325 10326 uint16_t 10327 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter, 10328 enum i40e_filter_pctype pctype) 10329 { 10330 uint16_t flowtype; 10331 uint64_t pctype_mask = 1ULL << pctype; 10332 10333 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX; 10334 flowtype++) { 10335 if (adapter->pctypes_tbl[flowtype] & pctype_mask) 10336 return flowtype; 10337 } 10338 10339 return RTE_ETH_FLOW_UNKNOWN; 10340 } 10341 10342 /* 10343 * On X710, performance number is far from the expectation on recent firmware 10344 * versions; on XL710, performance number is also far from the expectation on 10345 * recent firmware versions, if promiscuous mode is disabled, or promiscuous 10346 * mode is enabled and port MAC address is equal to the packet destination MAC 10347 * address. The fix for this issue may not be integrated in the following 10348 * firmware version. So the workaround in software driver is needed. It needs 10349 * to modify the initial values of 3 internal only registers for both X710 and 10350 * XL710. Note that the values for X710 or XL710 could be different, and the 10351 * workaround can be removed when it is fixed in firmware in the future. 10352 */ 10353 10354 /* For both X710 and XL710 */ 10355 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200 10356 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200 10357 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00 10358 10359 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200 10360 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08 10361 10362 /* For X722 */ 10363 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200 10364 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200 10365 10366 /* For X710 */ 10367 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303 10368 /* For XL710 */ 10369 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606 10370 #define I40E_GL_SWR_PM_UP_THR 0x269FBC 10371 10372 /* 10373 * GL_SWR_PM_UP_THR: 10374 * The value is not impacted from the link speed, its value is set according 10375 * to the total number of ports for a better pipe-monitor configuration. 10376 */ 10377 static bool 10378 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value) 10379 { 10380 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \ 10381 .device_id = (dev), \ 10382 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE 10383 10384 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \ 10385 .device_id = (dev), \ 10386 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE 10387 10388 static const struct { 10389 uint16_t device_id; 10390 uint32_t val; 10391 } swr_pm_table[] = { 10392 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) }, 10393 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) }, 10394 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) }, 10395 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) }, 10396 10397 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) }, 10398 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) }, 10399 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) }, 10400 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) }, 10401 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) }, 10402 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) }, 10403 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) }, 10404 }; 10405 uint32_t i; 10406 10407 if (value == NULL) { 10408 PMD_DRV_LOG(ERR, "value is NULL"); 10409 return false; 10410 } 10411 10412 for (i = 0; i < RTE_DIM(swr_pm_table); i++) { 10413 if (hw->device_id == swr_pm_table[i].device_id) { 10414 *value = swr_pm_table[i].val; 10415 10416 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR " 10417 "value - 0x%08x", 10418 hw->device_id, *value); 10419 return true; 10420 } 10421 } 10422 10423 return false; 10424 } 10425 10426 static int 10427 i40e_dev_sync_phy_type(struct i40e_hw *hw) 10428 { 10429 enum i40e_status_code status; 10430 struct i40e_aq_get_phy_abilities_resp phy_ab; 10431 int ret = -ENOTSUP; 10432 int retries = 0; 10433 10434 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab, 10435 NULL); 10436 10437 while (status) { 10438 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d", 10439 status); 10440 retries++; 10441 rte_delay_us(100000); 10442 if (retries < 5) 10443 status = i40e_aq_get_phy_capabilities(hw, false, 10444 true, &phy_ab, NULL); 10445 else 10446 return ret; 10447 } 10448 return 0; 10449 } 10450 10451 static void 10452 i40e_configure_registers(struct i40e_hw *hw) 10453 { 10454 static struct { 10455 uint32_t addr; 10456 uint64_t val; 10457 } reg_table[] = { 10458 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0}, 10459 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0}, 10460 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */ 10461 }; 10462 uint64_t reg; 10463 uint32_t i; 10464 int ret; 10465 10466 for (i = 0; i < RTE_DIM(reg_table); i++) { 10467 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) { 10468 if (hw->mac.type == I40E_MAC_X722) /* For X722 */ 10469 reg_table[i].val = 10470 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE; 10471 else /* For X710/XL710/XXV710 */ 10472 if (hw->aq.fw_maj_ver < 6) 10473 reg_table[i].val = 10474 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1; 10475 else 10476 reg_table[i].val = 10477 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2; 10478 } 10479 10480 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) { 10481 if (hw->mac.type == I40E_MAC_X722) /* For X722 */ 10482 reg_table[i].val = 10483 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE; 10484 else /* For X710/XL710/XXV710 */ 10485 reg_table[i].val = 10486 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE; 10487 } 10488 10489 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) { 10490 uint32_t cfg_val; 10491 10492 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) { 10493 PMD_DRV_LOG(DEBUG, "Device 0x%x skips " 10494 "GL_SWR_PM_UP_THR value fixup", 10495 hw->device_id); 10496 continue; 10497 } 10498 10499 reg_table[i].val = cfg_val; 10500 } 10501 10502 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr, 10503 ®, NULL); 10504 if (ret < 0) { 10505 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32, 10506 reg_table[i].addr); 10507 break; 10508 } 10509 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64, 10510 reg_table[i].addr, reg); 10511 if (reg == reg_table[i].val) 10512 continue; 10513 10514 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr, 10515 reg_table[i].val, NULL); 10516 if (ret < 0) { 10517 PMD_DRV_LOG(ERR, 10518 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32, 10519 reg_table[i].val, reg_table[i].addr); 10520 break; 10521 } 10522 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of " 10523 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr); 10524 } 10525 } 10526 10527 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4)) 10528 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030 10529 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4)) 10530 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab 10531 static int 10532 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi) 10533 { 10534 uint32_t reg; 10535 int ret; 10536 10537 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) { 10538 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum"); 10539 return -EINVAL; 10540 } 10541 10542 /* Configure for double VLAN RX stripping */ 10543 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id)); 10544 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) { 10545 reg |= I40E_VSI_TSR_QINQ_CONFIG; 10546 ret = i40e_aq_debug_write_register(hw, 10547 I40E_VSI_TSR(vsi->vsi_id), 10548 reg, NULL); 10549 if (ret < 0) { 10550 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]", 10551 vsi->vsi_id); 10552 return I40E_ERR_CONFIG; 10553 } 10554 } 10555 10556 /* Configure for double VLAN TX insertion */ 10557 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id)); 10558 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) { 10559 reg = I40E_VSI_L2TAGSTXVALID_QINQ; 10560 ret = i40e_aq_debug_write_register(hw, 10561 I40E_VSI_L2TAGSTXVALID( 10562 vsi->vsi_id), reg, NULL); 10563 if (ret < 0) { 10564 PMD_DRV_LOG(ERR, 10565 "Failed to update VSI_L2TAGSTXVALID[%d]", 10566 vsi->vsi_id); 10567 return I40E_ERR_CONFIG; 10568 } 10569 } 10570 10571 return 0; 10572 } 10573 10574 /** 10575 * i40e_aq_add_mirror_rule 10576 * @hw: pointer to the hardware structure 10577 * @seid: VEB seid to add mirror rule to 10578 * @dst_id: destination vsi seid 10579 * @entries: Buffer which contains the entities to be mirrored 10580 * @count: number of entities contained in the buffer 10581 * @rule_id:the rule_id of the rule to be added 10582 * 10583 * Add a mirror rule for a given veb. 10584 * 10585 **/ 10586 static enum i40e_status_code 10587 i40e_aq_add_mirror_rule(struct i40e_hw *hw, 10588 uint16_t seid, uint16_t dst_id, 10589 uint16_t rule_type, uint16_t *entries, 10590 uint16_t count, uint16_t *rule_id) 10591 { 10592 struct i40e_aq_desc desc; 10593 struct i40e_aqc_add_delete_mirror_rule cmd; 10594 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 10595 (struct i40e_aqc_add_delete_mirror_rule_completion *) 10596 &desc.params.raw; 10597 uint16_t buff_len; 10598 enum i40e_status_code status; 10599 10600 i40e_fill_default_direct_cmd_desc(&desc, 10601 i40e_aqc_opc_add_mirror_rule); 10602 memset(&cmd, 0, sizeof(cmd)); 10603 10604 buff_len = sizeof(uint16_t) * count; 10605 desc.datalen = rte_cpu_to_le_16(buff_len); 10606 if (buff_len > 0) 10607 desc.flags |= rte_cpu_to_le_16( 10608 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 10609 cmd.rule_type = rte_cpu_to_le_16(rule_type << 10610 I40E_AQC_MIRROR_RULE_TYPE_SHIFT); 10611 cmd.num_entries = rte_cpu_to_le_16(count); 10612 cmd.seid = rte_cpu_to_le_16(seid); 10613 cmd.destination = rte_cpu_to_le_16(dst_id); 10614 10615 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd)); 10616 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL); 10617 PMD_DRV_LOG(INFO, 10618 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,", 10619 hw->aq.asq_last_status, resp->rule_id, 10620 resp->mirror_rules_used, resp->mirror_rules_free); 10621 *rule_id = rte_le_to_cpu_16(resp->rule_id); 10622 10623 return status; 10624 } 10625 10626 /** 10627 * i40e_aq_del_mirror_rule 10628 * @hw: pointer to the hardware structure 10629 * @seid: VEB seid to add mirror rule to 10630 * @entries: Buffer which contains the entities to be mirrored 10631 * @count: number of entities contained in the buffer 10632 * @rule_id:the rule_id of the rule to be delete 10633 * 10634 * Delete a mirror rule for a given veb. 10635 * 10636 **/ 10637 static enum i40e_status_code 10638 i40e_aq_del_mirror_rule(struct i40e_hw *hw, 10639 uint16_t seid, uint16_t rule_type, uint16_t *entries, 10640 uint16_t count, uint16_t rule_id) 10641 { 10642 struct i40e_aq_desc desc; 10643 struct i40e_aqc_add_delete_mirror_rule cmd; 10644 uint16_t buff_len = 0; 10645 enum i40e_status_code status; 10646 void *buff = NULL; 10647 10648 i40e_fill_default_direct_cmd_desc(&desc, 10649 i40e_aqc_opc_delete_mirror_rule); 10650 memset(&cmd, 0, sizeof(cmd)); 10651 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 10652 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF | 10653 I40E_AQ_FLAG_RD)); 10654 cmd.num_entries = count; 10655 buff_len = sizeof(uint16_t) * count; 10656 desc.datalen = rte_cpu_to_le_16(buff_len); 10657 buff = (void *)entries; 10658 } else 10659 /* rule id is filled in destination field for deleting mirror rule */ 10660 cmd.destination = rte_cpu_to_le_16(rule_id); 10661 10662 cmd.rule_type = rte_cpu_to_le_16(rule_type << 10663 I40E_AQC_MIRROR_RULE_TYPE_SHIFT); 10664 cmd.seid = rte_cpu_to_le_16(seid); 10665 10666 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd)); 10667 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL); 10668 10669 return status; 10670 } 10671 10672 /** 10673 * i40e_mirror_rule_set 10674 * @dev: pointer to the hardware structure 10675 * @mirror_conf: mirror rule info 10676 * @sw_id: mirror rule's sw_id 10677 * @on: enable/disable 10678 * 10679 * set a mirror rule. 10680 * 10681 **/ 10682 static int 10683 i40e_mirror_rule_set(struct rte_eth_dev *dev, 10684 struct rte_eth_mirror_conf *mirror_conf, 10685 uint8_t sw_id, uint8_t on) 10686 { 10687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10688 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10689 struct i40e_mirror_rule *it, *mirr_rule = NULL; 10690 struct i40e_mirror_rule *parent = NULL; 10691 uint16_t seid, dst_seid, rule_id; 10692 uint16_t i, j = 0; 10693 int ret; 10694 10695 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id); 10696 10697 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) { 10698 PMD_DRV_LOG(ERR, 10699 "mirror rule can not be configured without veb or vfs."); 10700 return -ENOSYS; 10701 } 10702 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) { 10703 PMD_DRV_LOG(ERR, "mirror table is full."); 10704 return -ENOSPC; 10705 } 10706 if (mirror_conf->dst_pool > pf->vf_num) { 10707 PMD_DRV_LOG(ERR, "invalid destination pool %u.", 10708 mirror_conf->dst_pool); 10709 return -EINVAL; 10710 } 10711 10712 seid = pf->main_vsi->veb->seid; 10713 10714 TAILQ_FOREACH(it, &pf->mirror_list, rules) { 10715 if (sw_id <= it->index) { 10716 mirr_rule = it; 10717 break; 10718 } 10719 parent = it; 10720 } 10721 if (mirr_rule && sw_id == mirr_rule->index) { 10722 if (on) { 10723 PMD_DRV_LOG(ERR, "mirror rule exists."); 10724 return -EEXIST; 10725 } else { 10726 ret = i40e_aq_del_mirror_rule(hw, seid, 10727 mirr_rule->rule_type, 10728 mirr_rule->entries, 10729 mirr_rule->num_entries, mirr_rule->id); 10730 if (ret < 0) { 10731 PMD_DRV_LOG(ERR, 10732 "failed to remove mirror rule: ret = %d, aq_err = %d.", 10733 ret, hw->aq.asq_last_status); 10734 return -ENOSYS; 10735 } 10736 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules); 10737 rte_free(mirr_rule); 10738 pf->nb_mirror_rule--; 10739 return 0; 10740 } 10741 } else if (!on) { 10742 PMD_DRV_LOG(ERR, "mirror rule doesn't exist."); 10743 return -ENOENT; 10744 } 10745 10746 mirr_rule = rte_zmalloc("i40e_mirror_rule", 10747 sizeof(struct i40e_mirror_rule) , 0); 10748 if (!mirr_rule) { 10749 PMD_DRV_LOG(ERR, "failed to allocate memory"); 10750 return I40E_ERR_NO_MEMORY; 10751 } 10752 switch (mirror_conf->rule_type) { 10753 case ETH_MIRROR_VLAN: 10754 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) { 10755 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 10756 mirr_rule->entries[j] = 10757 mirror_conf->vlan.vlan_id[i]; 10758 j++; 10759 } 10760 } 10761 if (j == 0) { 10762 PMD_DRV_LOG(ERR, "vlan is not specified."); 10763 rte_free(mirr_rule); 10764 return -EINVAL; 10765 } 10766 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN; 10767 break; 10768 case ETH_MIRROR_VIRTUAL_POOL_UP: 10769 case ETH_MIRROR_VIRTUAL_POOL_DOWN: 10770 /* check if the specified pool bit is out of range */ 10771 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) { 10772 PMD_DRV_LOG(ERR, "pool mask is out of range."); 10773 rte_free(mirr_rule); 10774 return -EINVAL; 10775 } 10776 for (i = 0, j = 0; i < pf->vf_num; i++) { 10777 if (mirror_conf->pool_mask & (1ULL << i)) { 10778 mirr_rule->entries[j] = pf->vfs[i].vsi->seid; 10779 j++; 10780 } 10781 } 10782 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) { 10783 /* add pf vsi to entries */ 10784 mirr_rule->entries[j] = pf->main_vsi_seid; 10785 j++; 10786 } 10787 if (j == 0) { 10788 PMD_DRV_LOG(ERR, "pool is not specified."); 10789 rte_free(mirr_rule); 10790 return -EINVAL; 10791 } 10792 /* egress and ingress in aq commands means from switch but not port */ 10793 mirr_rule->rule_type = 10794 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ? 10795 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS : 10796 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS; 10797 break; 10798 case ETH_MIRROR_UPLINK_PORT: 10799 /* egress and ingress in aq commands means from switch but not port*/ 10800 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS; 10801 break; 10802 case ETH_MIRROR_DOWNLINK_PORT: 10803 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS; 10804 break; 10805 default: 10806 PMD_DRV_LOG(ERR, "unsupported mirror type %d.", 10807 mirror_conf->rule_type); 10808 rte_free(mirr_rule); 10809 return -EINVAL; 10810 } 10811 10812 /* If the dst_pool is equal to vf_num, consider it as PF */ 10813 if (mirror_conf->dst_pool == pf->vf_num) 10814 dst_seid = pf->main_vsi_seid; 10815 else 10816 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid; 10817 10818 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid, 10819 mirr_rule->rule_type, mirr_rule->entries, 10820 j, &rule_id); 10821 if (ret < 0) { 10822 PMD_DRV_LOG(ERR, 10823 "failed to add mirror rule: ret = %d, aq_err = %d.", 10824 ret, hw->aq.asq_last_status); 10825 rte_free(mirr_rule); 10826 return -ENOSYS; 10827 } 10828 10829 mirr_rule->index = sw_id; 10830 mirr_rule->num_entries = j; 10831 mirr_rule->id = rule_id; 10832 mirr_rule->dst_vsi_seid = dst_seid; 10833 10834 if (parent) 10835 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules); 10836 else 10837 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules); 10838 10839 pf->nb_mirror_rule++; 10840 return 0; 10841 } 10842 10843 /** 10844 * i40e_mirror_rule_reset 10845 * @dev: pointer to the device 10846 * @sw_id: mirror rule's sw_id 10847 * 10848 * reset a mirror rule. 10849 * 10850 **/ 10851 static int 10852 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id) 10853 { 10854 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 10855 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10856 struct i40e_mirror_rule *it, *mirr_rule = NULL; 10857 uint16_t seid; 10858 int ret; 10859 10860 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id); 10861 10862 seid = pf->main_vsi->veb->seid; 10863 10864 TAILQ_FOREACH(it, &pf->mirror_list, rules) { 10865 if (sw_id == it->index) { 10866 mirr_rule = it; 10867 break; 10868 } 10869 } 10870 if (mirr_rule) { 10871 ret = i40e_aq_del_mirror_rule(hw, seid, 10872 mirr_rule->rule_type, 10873 mirr_rule->entries, 10874 mirr_rule->num_entries, mirr_rule->id); 10875 if (ret < 0) { 10876 PMD_DRV_LOG(ERR, 10877 "failed to remove mirror rule: status = %d, aq_err = %d.", 10878 ret, hw->aq.asq_last_status); 10879 return -ENOSYS; 10880 } 10881 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules); 10882 rte_free(mirr_rule); 10883 pf->nb_mirror_rule--; 10884 } else { 10885 PMD_DRV_LOG(ERR, "mirror rule doesn't exist."); 10886 return -ENOENT; 10887 } 10888 return 0; 10889 } 10890 10891 static uint64_t 10892 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev) 10893 { 10894 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10895 uint64_t systim_cycles; 10896 10897 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L); 10898 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H) 10899 << 32; 10900 10901 return systim_cycles; 10902 } 10903 10904 static uint64_t 10905 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index) 10906 { 10907 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10908 uint64_t rx_tstamp; 10909 10910 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index)); 10911 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index)) 10912 << 32; 10913 10914 return rx_tstamp; 10915 } 10916 10917 static uint64_t 10918 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 10919 { 10920 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10921 uint64_t tx_tstamp; 10922 10923 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L); 10924 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H) 10925 << 32; 10926 10927 return tx_tstamp; 10928 } 10929 10930 static void 10931 i40e_start_timecounters(struct rte_eth_dev *dev) 10932 { 10933 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 10934 struct i40e_adapter *adapter = dev->data->dev_private; 10935 struct rte_eth_link link; 10936 uint32_t tsync_inc_l; 10937 uint32_t tsync_inc_h; 10938 10939 /* Get current link speed. */ 10940 i40e_dev_link_update(dev, 1); 10941 rte_eth_linkstatus_get(dev, &link); 10942 10943 switch (link.link_speed) { 10944 case ETH_SPEED_NUM_40G: 10945 case ETH_SPEED_NUM_25G: 10946 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF; 10947 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32; 10948 break; 10949 case ETH_SPEED_NUM_10G: 10950 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF; 10951 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32; 10952 break; 10953 case ETH_SPEED_NUM_1G: 10954 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF; 10955 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32; 10956 break; 10957 default: 10958 tsync_inc_l = 0x0; 10959 tsync_inc_h = 0x0; 10960 } 10961 10962 /* Set the timesync increment value. */ 10963 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l); 10964 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h); 10965 10966 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 10967 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 10968 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 10969 10970 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10971 adapter->systime_tc.cc_shift = 0; 10972 adapter->systime_tc.nsec_mask = 0; 10973 10974 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10975 adapter->rx_tstamp_tc.cc_shift = 0; 10976 adapter->rx_tstamp_tc.nsec_mask = 0; 10977 10978 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK; 10979 adapter->tx_tstamp_tc.cc_shift = 0; 10980 adapter->tx_tstamp_tc.nsec_mask = 0; 10981 } 10982 10983 static int 10984 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 10985 { 10986 struct i40e_adapter *adapter = dev->data->dev_private; 10987 10988 adapter->systime_tc.nsec += delta; 10989 adapter->rx_tstamp_tc.nsec += delta; 10990 adapter->tx_tstamp_tc.nsec += delta; 10991 10992 return 0; 10993 } 10994 10995 static int 10996 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 10997 { 10998 uint64_t ns; 10999 struct i40e_adapter *adapter = dev->data->dev_private; 11000 11001 ns = rte_timespec_to_ns(ts); 11002 11003 /* Set the timecounters to a new value. */ 11004 adapter->systime_tc.nsec = ns; 11005 adapter->rx_tstamp_tc.nsec = ns; 11006 adapter->tx_tstamp_tc.nsec = ns; 11007 11008 return 0; 11009 } 11010 11011 static int 11012 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 11013 { 11014 uint64_t ns, systime_cycles; 11015 struct i40e_adapter *adapter = dev->data->dev_private; 11016 11017 systime_cycles = i40e_read_systime_cyclecounter(dev); 11018 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 11019 *ts = rte_ns_to_timespec(ns); 11020 11021 return 0; 11022 } 11023 11024 static int 11025 i40e_timesync_enable(struct rte_eth_dev *dev) 11026 { 11027 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11028 uint32_t tsync_ctl_l; 11029 uint32_t tsync_ctl_h; 11030 11031 /* Stop the timesync system time. */ 11032 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); 11033 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); 11034 /* Reset the timesync system time value. */ 11035 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0); 11036 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0); 11037 11038 i40e_start_timecounters(dev); 11039 11040 /* Clear timesync registers. */ 11041 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); 11042 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H); 11043 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0)); 11044 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1)); 11045 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2)); 11046 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3)); 11047 11048 /* Enable timestamping of PTP packets. */ 11049 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); 11050 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA; 11051 11052 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); 11053 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA; 11054 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE; 11055 11056 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); 11057 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); 11058 11059 return 0; 11060 } 11061 11062 static int 11063 i40e_timesync_disable(struct rte_eth_dev *dev) 11064 { 11065 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11066 uint32_t tsync_ctl_l; 11067 uint32_t tsync_ctl_h; 11068 11069 /* Disable timestamping of transmitted PTP packets. */ 11070 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0); 11071 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA; 11072 11073 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1); 11074 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA; 11075 11076 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l); 11077 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h); 11078 11079 /* Reset the timesync increment value. */ 11080 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0); 11081 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0); 11082 11083 return 0; 11084 } 11085 11086 static int 11087 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 11088 struct timespec *timestamp, uint32_t flags) 11089 { 11090 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11091 struct i40e_adapter *adapter = dev->data->dev_private; 11092 uint32_t sync_status; 11093 uint32_t index = flags & 0x03; 11094 uint64_t rx_tstamp_cycles; 11095 uint64_t ns; 11096 11097 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1); 11098 if ((sync_status & (1 << index)) == 0) 11099 return -EINVAL; 11100 11101 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index); 11102 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 11103 *timestamp = rte_ns_to_timespec(ns); 11104 11105 return 0; 11106 } 11107 11108 static int 11109 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 11110 struct timespec *timestamp) 11111 { 11112 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11113 struct i40e_adapter *adapter = dev->data->dev_private; 11114 uint32_t sync_status; 11115 uint64_t tx_tstamp_cycles; 11116 uint64_t ns; 11117 11118 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0); 11119 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0) 11120 return -EINVAL; 11121 11122 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev); 11123 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 11124 *timestamp = rte_ns_to_timespec(ns); 11125 11126 return 0; 11127 } 11128 11129 /* 11130 * i40e_parse_dcb_configure - parse dcb configure from user 11131 * @dev: the device being configured 11132 * @dcb_cfg: pointer of the result of parse 11133 * @*tc_map: bit map of enabled traffic classes 11134 * 11135 * Returns 0 on success, negative value on failure 11136 */ 11137 static int 11138 i40e_parse_dcb_configure(struct rte_eth_dev *dev, 11139 struct i40e_dcbx_config *dcb_cfg, 11140 uint8_t *tc_map) 11141 { 11142 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 11143 uint8_t i, tc_bw, bw_lf; 11144 11145 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config)); 11146 11147 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 11148 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) { 11149 PMD_INIT_LOG(ERR, "number of tc exceeds max."); 11150 return -EINVAL; 11151 } 11152 11153 /* assume each tc has the same bw */ 11154 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs; 11155 for (i = 0; i < dcb_rx_conf->nb_tcs; i++) 11156 dcb_cfg->etscfg.tcbwtable[i] = tc_bw; 11157 /* to ensure the sum of tcbw is equal to 100 */ 11158 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs; 11159 for (i = 0; i < bw_lf; i++) 11160 dcb_cfg->etscfg.tcbwtable[i]++; 11161 11162 /* assume each tc has the same Transmission Selection Algorithm */ 11163 for (i = 0; i < dcb_rx_conf->nb_tcs; i++) 11164 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS; 11165 11166 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11167 dcb_cfg->etscfg.prioritytable[i] = 11168 dcb_rx_conf->dcb_tc[i]; 11169 11170 /* FW needs one App to configure HW */ 11171 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM; 11172 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE; 11173 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO; 11174 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE; 11175 11176 if (dcb_rx_conf->nb_tcs == 0) 11177 *tc_map = 1; /* tc0 only */ 11178 else 11179 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t); 11180 11181 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) { 11182 dcb_cfg->pfc.willing = 0; 11183 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; 11184 dcb_cfg->pfc.pfcenable = *tc_map; 11185 } 11186 return 0; 11187 } 11188 11189 11190 static enum i40e_status_code 11191 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi, 11192 struct i40e_aqc_vsi_properties_data *info, 11193 uint8_t enabled_tcmap) 11194 { 11195 enum i40e_status_code ret; 11196 int i, total_tc = 0; 11197 uint16_t qpnum_per_tc, bsf, qp_idx; 11198 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi); 11199 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi); 11200 uint16_t used_queues; 11201 11202 ret = validate_tcmap_parameter(vsi, enabled_tcmap); 11203 if (ret != I40E_SUCCESS) 11204 return ret; 11205 11206 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11207 if (enabled_tcmap & (1 << i)) 11208 total_tc++; 11209 } 11210 if (total_tc == 0) 11211 total_tc = 1; 11212 vsi->enabled_tc = enabled_tcmap; 11213 11214 /* different VSI has different queues assigned */ 11215 if (vsi->type == I40E_VSI_MAIN) 11216 used_queues = dev_data->nb_rx_queues - 11217 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 11218 else if (vsi->type == I40E_VSI_VMDQ2) 11219 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; 11220 else { 11221 PMD_INIT_LOG(ERR, "unsupported VSI type."); 11222 return I40E_ERR_NO_AVAILABLE_VSI; 11223 } 11224 11225 qpnum_per_tc = used_queues / total_tc; 11226 /* Number of queues per enabled TC */ 11227 if (qpnum_per_tc == 0) { 11228 PMD_INIT_LOG(ERR, " number of queues is less that tcs."); 11229 return I40E_ERR_INVALID_QP_ID; 11230 } 11231 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc), 11232 I40E_MAX_Q_PER_TC); 11233 bsf = rte_bsf32(qpnum_per_tc); 11234 11235 /** 11236 * Configure TC and queue mapping parameters, for enabled TC, 11237 * allocate qpnum_per_tc queues to this traffic. For disabled TC, 11238 * default queue will serve it. 11239 */ 11240 qp_idx = 0; 11241 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11242 if (vsi->enabled_tc & (1 << i)) { 11243 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx << 11244 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 11245 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 11246 qp_idx += qpnum_per_tc; 11247 } else 11248 info->tc_mapping[i] = 0; 11249 } 11250 11251 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */ 11252 if (vsi->type == I40E_VSI_SRIOV) { 11253 info->mapping_flags |= 11254 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 11255 for (i = 0; i < vsi->nb_qps; i++) 11256 info->queue_mapping[i] = 11257 rte_cpu_to_le_16(vsi->base_queue + i); 11258 } else { 11259 info->mapping_flags |= 11260 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG); 11261 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 11262 } 11263 info->valid_sections |= 11264 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 11265 11266 return I40E_SUCCESS; 11267 } 11268 11269 /* 11270 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map 11271 * @veb: VEB to be configured 11272 * @tc_map: enabled TC bitmap 11273 * 11274 * Returns 0 on success, negative value on failure 11275 */ 11276 static enum i40e_status_code 11277 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map) 11278 { 11279 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw; 11280 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query; 11281 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query; 11282 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi); 11283 enum i40e_status_code ret = I40E_SUCCESS; 11284 int i; 11285 uint32_t bw_max; 11286 11287 /* Check if enabled_tc is same as existing or new TCs */ 11288 if (veb->enabled_tc == tc_map) 11289 return ret; 11290 11291 /* configure tc bandwidth */ 11292 memset(&veb_bw, 0, sizeof(veb_bw)); 11293 veb_bw.tc_valid_bits = tc_map; 11294 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 11295 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11296 if (tc_map & BIT_ULL(i)) 11297 veb_bw.tc_bw_share_credits[i] = 1; 11298 } 11299 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid, 11300 &veb_bw, NULL); 11301 if (ret) { 11302 PMD_INIT_LOG(ERR, 11303 "AQ command Config switch_comp BW allocation per TC failed = %d", 11304 hw->aq.asq_last_status); 11305 return ret; 11306 } 11307 11308 memset(&ets_query, 0, sizeof(ets_query)); 11309 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, 11310 &ets_query, NULL); 11311 if (ret != I40E_SUCCESS) { 11312 PMD_DRV_LOG(ERR, 11313 "Failed to get switch_comp ETS configuration %u", 11314 hw->aq.asq_last_status); 11315 return ret; 11316 } 11317 memset(&bw_query, 0, sizeof(bw_query)); 11318 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, 11319 &bw_query, NULL); 11320 if (ret != I40E_SUCCESS) { 11321 PMD_DRV_LOG(ERR, 11322 "Failed to get switch_comp bandwidth configuration %u", 11323 hw->aq.asq_last_status); 11324 return ret; 11325 } 11326 11327 /* store and print out BW info */ 11328 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit); 11329 veb->bw_info.bw_max = ets_query.tc_bw_max; 11330 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit); 11331 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max); 11332 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) | 11333 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) << 11334 I40E_16_BIT_WIDTH); 11335 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11336 veb->bw_info.bw_ets_share_credits[i] = 11337 bw_query.tc_bw_share_credits[i]; 11338 veb->bw_info.bw_ets_credits[i] = 11339 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]); 11340 /* 4 bits per TC, 4th bit is reserved */ 11341 veb->bw_info.bw_ets_max[i] = 11342 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) & 11343 RTE_LEN2MASK(3, uint8_t)); 11344 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i, 11345 veb->bw_info.bw_ets_share_credits[i]); 11346 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i, 11347 veb->bw_info.bw_ets_credits[i]); 11348 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i, 11349 veb->bw_info.bw_ets_max[i]); 11350 } 11351 11352 veb->enabled_tc = tc_map; 11353 11354 return ret; 11355 } 11356 11357 11358 /* 11359 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map 11360 * @vsi: VSI to be configured 11361 * @tc_map: enabled TC bitmap 11362 * 11363 * Returns 0 on success, negative value on failure 11364 */ 11365 static enum i40e_status_code 11366 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map) 11367 { 11368 struct i40e_aqc_configure_vsi_tc_bw_data bw_data; 11369 struct i40e_vsi_context ctxt; 11370 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 11371 enum i40e_status_code ret = I40E_SUCCESS; 11372 int i; 11373 11374 /* Check if enabled_tc is same as existing or new TCs */ 11375 if (vsi->enabled_tc == tc_map) 11376 return ret; 11377 11378 /* configure tc bandwidth */ 11379 memset(&bw_data, 0, sizeof(bw_data)); 11380 bw_data.tc_valid_bits = tc_map; 11381 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 11382 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11383 if (tc_map & BIT_ULL(i)) 11384 bw_data.tc_bw_credits[i] = 1; 11385 } 11386 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL); 11387 if (ret) { 11388 PMD_INIT_LOG(ERR, 11389 "AQ command Config VSI BW allocation per TC failed = %d", 11390 hw->aq.asq_last_status); 11391 goto out; 11392 } 11393 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 11394 vsi->info.qs_handle[i] = bw_data.qs_handles[i]; 11395 11396 /* Update Queue Pairs Mapping for currently enabled UPs */ 11397 ctxt.seid = vsi->seid; 11398 ctxt.pf_num = hw->pf_id; 11399 ctxt.vf_num = 0; 11400 ctxt.uplink_seid = vsi->uplink_seid; 11401 ctxt.info = vsi->info; 11402 i40e_get_cap(hw); 11403 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map); 11404 if (ret) 11405 goto out; 11406 11407 /* Update the VSI after updating the VSI queue-mapping information */ 11408 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 11409 if (ret) { 11410 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d", 11411 hw->aq.asq_last_status); 11412 goto out; 11413 } 11414 /* update the local VSI info with updated queue map */ 11415 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping, 11416 sizeof(vsi->info.tc_mapping)); 11417 rte_memcpy(&vsi->info.queue_mapping, 11418 &ctxt.info.queue_mapping, 11419 sizeof(vsi->info.queue_mapping)); 11420 vsi->info.mapping_flags = ctxt.info.mapping_flags; 11421 vsi->info.valid_sections = 0; 11422 11423 /* query and update current VSI BW information */ 11424 ret = i40e_vsi_get_bw_config(vsi); 11425 if (ret) { 11426 PMD_INIT_LOG(ERR, 11427 "Failed updating vsi bw info, err %s aq_err %s", 11428 i40e_stat_str(hw, ret), 11429 i40e_aq_str(hw, hw->aq.asq_last_status)); 11430 goto out; 11431 } 11432 11433 vsi->enabled_tc = tc_map; 11434 11435 out: 11436 return ret; 11437 } 11438 11439 /* 11440 * i40e_dcb_hw_configure - program the dcb setting to hw 11441 * @pf: pf the configuration is taken on 11442 * @new_cfg: new configuration 11443 * @tc_map: enabled TC bitmap 11444 * 11445 * Returns 0 on success, negative value on failure 11446 */ 11447 static enum i40e_status_code 11448 i40e_dcb_hw_configure(struct i40e_pf *pf, 11449 struct i40e_dcbx_config *new_cfg, 11450 uint8_t tc_map) 11451 { 11452 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 11453 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config; 11454 struct i40e_vsi *main_vsi = pf->main_vsi; 11455 struct i40e_vsi_list *vsi_list; 11456 enum i40e_status_code ret; 11457 int i; 11458 uint32_t val; 11459 11460 /* Use the FW API if FW > v4.4*/ 11461 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) || 11462 (hw->aq.fw_maj_ver >= 5))) { 11463 PMD_INIT_LOG(ERR, 11464 "FW < v4.4, can not use FW LLDP API to configure DCB"); 11465 return I40E_ERR_FIRMWARE_API_VERSION; 11466 } 11467 11468 /* Check if need reconfiguration */ 11469 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) { 11470 PMD_INIT_LOG(ERR, "No Change in DCB Config required."); 11471 return I40E_SUCCESS; 11472 } 11473 11474 /* Copy the new config to the current config */ 11475 *old_cfg = *new_cfg; 11476 old_cfg->etsrec = old_cfg->etscfg; 11477 ret = i40e_set_dcb_config(hw); 11478 if (ret) { 11479 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s", 11480 i40e_stat_str(hw, ret), 11481 i40e_aq_str(hw, hw->aq.asq_last_status)); 11482 return ret; 11483 } 11484 /* set receive Arbiter to RR mode and ETS scheme by default */ 11485 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) { 11486 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i)); 11487 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK | 11488 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK | 11489 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT); 11490 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] << 11491 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) & 11492 I40E_PRTDCB_RETSTCC_BWSHARE_MASK; 11493 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) & 11494 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK; 11495 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) & 11496 I40E_PRTDCB_RETSTCC_ETSTC_MASK; 11497 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val); 11498 } 11499 /* get local mib to check whether it is configured correctly */ 11500 /* IEEE mode */ 11501 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE; 11502 /* Get Local DCB Config */ 11503 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0, 11504 &hw->local_dcbx_config); 11505 11506 /* if Veb is created, need to update TC of it at first */ 11507 if (main_vsi->veb) { 11508 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map); 11509 if (ret) 11510 PMD_INIT_LOG(WARNING, 11511 "Failed configuring TC for VEB seid=%d", 11512 main_vsi->veb->seid); 11513 } 11514 /* Update each VSI */ 11515 i40e_vsi_config_tc(main_vsi, tc_map); 11516 if (main_vsi->veb) { 11517 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) { 11518 /* Beside main VSI and VMDQ VSIs, only enable default 11519 * TC for other VSIs 11520 */ 11521 if (vsi_list->vsi->type == I40E_VSI_VMDQ2) 11522 ret = i40e_vsi_config_tc(vsi_list->vsi, 11523 tc_map); 11524 else 11525 ret = i40e_vsi_config_tc(vsi_list->vsi, 11526 I40E_DEFAULT_TCMAP); 11527 if (ret) 11528 PMD_INIT_LOG(WARNING, 11529 "Failed configuring TC for VSI seid=%d", 11530 vsi_list->vsi->seid); 11531 /* continue */ 11532 } 11533 } 11534 return I40E_SUCCESS; 11535 } 11536 11537 /* 11538 * i40e_dcb_init_configure - initial dcb config 11539 * @dev: device being configured 11540 * @sw_dcb: indicate whether dcb is sw configured or hw offload 11541 * 11542 * Returns 0 on success, negative value on failure 11543 */ 11544 int 11545 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb) 11546 { 11547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11549 int i, ret = 0; 11550 11551 if ((pf->flags & I40E_FLAG_DCB) == 0) { 11552 PMD_INIT_LOG(ERR, "HW doesn't support DCB"); 11553 return -ENOTSUP; 11554 } 11555 11556 /* DCB initialization: 11557 * Update DCB configuration from the Firmware and configure 11558 * LLDP MIB change event. 11559 */ 11560 if (sw_dcb == TRUE) { 11561 if (i40e_need_stop_lldp(dev)) { 11562 ret = i40e_aq_stop_lldp(hw, TRUE, NULL); 11563 if (ret != I40E_SUCCESS) 11564 PMD_INIT_LOG(DEBUG, "Failed to stop lldp"); 11565 } 11566 11567 ret = i40e_init_dcb(hw); 11568 /* If lldp agent is stopped, the return value from 11569 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM 11570 * adminq status. Otherwise, it should return success. 11571 */ 11572 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS && 11573 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) { 11574 memset(&hw->local_dcbx_config, 0, 11575 sizeof(struct i40e_dcbx_config)); 11576 /* set dcb default configuration */ 11577 hw->local_dcbx_config.etscfg.willing = 0; 11578 hw->local_dcbx_config.etscfg.maxtcs = 0; 11579 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100; 11580 hw->local_dcbx_config.etscfg.tsatable[0] = 11581 I40E_IEEE_TSA_ETS; 11582 /* all UPs mapping to TC0 */ 11583 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11584 hw->local_dcbx_config.etscfg.prioritytable[i] = 0; 11585 hw->local_dcbx_config.etsrec = 11586 hw->local_dcbx_config.etscfg; 11587 hw->local_dcbx_config.pfc.willing = 0; 11588 hw->local_dcbx_config.pfc.pfccap = 11589 I40E_MAX_TRAFFIC_CLASS; 11590 /* FW needs one App to configure HW */ 11591 hw->local_dcbx_config.numapps = 1; 11592 hw->local_dcbx_config.app[0].selector = 11593 I40E_APP_SEL_ETHTYPE; 11594 hw->local_dcbx_config.app[0].priority = 3; 11595 hw->local_dcbx_config.app[0].protocolid = 11596 I40E_APP_PROTOID_FCOE; 11597 ret = i40e_set_dcb_config(hw); 11598 if (ret) { 11599 PMD_INIT_LOG(ERR, 11600 "default dcb config fails. err = %d, aq_err = %d.", 11601 ret, hw->aq.asq_last_status); 11602 return -ENOSYS; 11603 } 11604 } else { 11605 PMD_INIT_LOG(ERR, 11606 "DCB initialization in FW fails, err = %d, aq_err = %d.", 11607 ret, hw->aq.asq_last_status); 11608 return -ENOTSUP; 11609 } 11610 } else { 11611 ret = i40e_aq_start_lldp(hw, NULL); 11612 if (ret != I40E_SUCCESS) 11613 PMD_INIT_LOG(DEBUG, "Failed to start lldp"); 11614 11615 ret = i40e_init_dcb(hw); 11616 if (!ret) { 11617 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) { 11618 PMD_INIT_LOG(ERR, 11619 "HW doesn't support DCBX offload."); 11620 return -ENOTSUP; 11621 } 11622 } else { 11623 PMD_INIT_LOG(ERR, 11624 "DCBX configuration failed, err = %d, aq_err = %d.", 11625 ret, hw->aq.asq_last_status); 11626 return -ENOTSUP; 11627 } 11628 } 11629 return 0; 11630 } 11631 11632 /* 11633 * i40e_dcb_setup - setup dcb related config 11634 * @dev: device being configured 11635 * 11636 * Returns 0 on success, negative value on failure 11637 */ 11638 static int 11639 i40e_dcb_setup(struct rte_eth_dev *dev) 11640 { 11641 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11642 struct i40e_dcbx_config dcb_cfg; 11643 uint8_t tc_map = 0; 11644 int ret = 0; 11645 11646 if ((pf->flags & I40E_FLAG_DCB) == 0) { 11647 PMD_INIT_LOG(ERR, "HW doesn't support DCB"); 11648 return -ENOTSUP; 11649 } 11650 11651 if (pf->vf_num != 0) 11652 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis."); 11653 11654 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map); 11655 if (ret) { 11656 PMD_INIT_LOG(ERR, "invalid dcb config"); 11657 return -EINVAL; 11658 } 11659 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map); 11660 if (ret) { 11661 PMD_INIT_LOG(ERR, "dcb sw configure fails"); 11662 return -ENOSYS; 11663 } 11664 11665 return 0; 11666 } 11667 11668 static int 11669 i40e_dev_get_dcb_info(struct rte_eth_dev *dev, 11670 struct rte_eth_dcb_info *dcb_info) 11671 { 11672 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 11673 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11674 struct i40e_vsi *vsi = pf->main_vsi; 11675 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config; 11676 uint16_t bsf, tc_mapping; 11677 int i, j = 0; 11678 11679 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 11680 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1); 11681 else 11682 dcb_info->nb_tcs = 1; 11683 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 11684 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i]; 11685 for (i = 0; i < dcb_info->nb_tcs; i++) 11686 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i]; 11687 11688 /* get queue mapping if vmdq is disabled */ 11689 if (!pf->nb_cfg_vmdq_vsi) { 11690 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11691 if (!(vsi->enabled_tc & (1 << i))) 11692 continue; 11693 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]); 11694 dcb_info->tc_queue.tc_rxq[j][i].base = 11695 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >> 11696 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT; 11697 dcb_info->tc_queue.tc_txq[j][i].base = 11698 dcb_info->tc_queue.tc_rxq[j][i].base; 11699 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >> 11700 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT; 11701 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf; 11702 dcb_info->tc_queue.tc_txq[j][i].nb_queue = 11703 dcb_info->tc_queue.tc_rxq[j][i].nb_queue; 11704 } 11705 return 0; 11706 } 11707 11708 /* get queue mapping if vmdq is enabled */ 11709 do { 11710 vsi = pf->vmdq[j].vsi; 11711 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 11712 if (!(vsi->enabled_tc & (1 << i))) 11713 continue; 11714 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]); 11715 dcb_info->tc_queue.tc_rxq[j][i].base = 11716 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >> 11717 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT; 11718 dcb_info->tc_queue.tc_txq[j][i].base = 11719 dcb_info->tc_queue.tc_rxq[j][i].base; 11720 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >> 11721 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT; 11722 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf; 11723 dcb_info->tc_queue.tc_txq[j][i].nb_queue = 11724 dcb_info->tc_queue.tc_rxq[j][i].nb_queue; 11725 } 11726 j++; 11727 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL)); 11728 return 0; 11729 } 11730 11731 static int 11732 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 11733 { 11734 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 11735 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 11736 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11737 uint16_t msix_intr; 11738 11739 msix_intr = intr_handle->intr_vec[queue_id]; 11740 if (msix_intr == I40E_MISC_VEC_ID) 11741 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 11742 I40E_PFINT_DYN_CTL0_INTENA_MASK | 11743 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 11744 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 11745 else 11746 I40E_WRITE_REG(hw, 11747 I40E_PFINT_DYN_CTLN(msix_intr - 11748 I40E_RX_VEC_START), 11749 I40E_PFINT_DYN_CTLN_INTENA_MASK | 11750 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 11751 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 11752 11753 I40E_WRITE_FLUSH(hw); 11754 rte_intr_ack(&pci_dev->intr_handle); 11755 11756 return 0; 11757 } 11758 11759 static int 11760 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 11761 { 11762 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 11763 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 11764 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11765 uint16_t msix_intr; 11766 11767 msix_intr = intr_handle->intr_vec[queue_id]; 11768 if (msix_intr == I40E_MISC_VEC_ID) 11769 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 11770 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); 11771 else 11772 I40E_WRITE_REG(hw, 11773 I40E_PFINT_DYN_CTLN(msix_intr - 11774 I40E_RX_VEC_START), 11775 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); 11776 I40E_WRITE_FLUSH(hw); 11777 11778 return 0; 11779 } 11780 11781 /** 11782 * This function is used to check if the register is valid. 11783 * Below is the valid registers list for X722 only: 11784 * 0x2b800--0x2bb00 11785 * 0x38700--0x38a00 11786 * 0x3d800--0x3db00 11787 * 0x208e00--0x209000 11788 * 0x20be00--0x20c000 11789 * 0x263c00--0x264000 11790 * 0x265c00--0x266000 11791 */ 11792 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset) 11793 { 11794 if ((type != I40E_MAC_X722) && 11795 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) || 11796 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) || 11797 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) || 11798 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) || 11799 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) || 11800 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) || 11801 (reg_offset >= 0x265c00 && reg_offset <= 0x266000))) 11802 return 0; 11803 else 11804 return 1; 11805 } 11806 11807 static int i40e_get_regs(struct rte_eth_dev *dev, 11808 struct rte_dev_reg_info *regs) 11809 { 11810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11811 uint32_t *ptr_data = regs->data; 11812 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset; 11813 const struct i40e_reg_info *reg_info; 11814 11815 if (ptr_data == NULL) { 11816 regs->length = I40E_GLGEN_STAT_CLEAR + 4; 11817 regs->width = sizeof(uint32_t); 11818 return 0; 11819 } 11820 11821 /* The first few registers have to be read using AQ operations */ 11822 reg_idx = 0; 11823 while (i40e_regs_adminq[reg_idx].name) { 11824 reg_info = &i40e_regs_adminq[reg_idx++]; 11825 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++) 11826 for (arr_idx2 = 0; 11827 arr_idx2 <= reg_info->count2; 11828 arr_idx2++) { 11829 reg_offset = arr_idx * reg_info->stride1 + 11830 arr_idx2 * reg_info->stride2; 11831 reg_offset += reg_info->base_addr; 11832 ptr_data[reg_offset >> 2] = 11833 i40e_read_rx_ctl(hw, reg_offset); 11834 } 11835 } 11836 11837 /* The remaining registers can be read using primitives */ 11838 reg_idx = 0; 11839 while (i40e_regs_others[reg_idx].name) { 11840 reg_info = &i40e_regs_others[reg_idx++]; 11841 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++) 11842 for (arr_idx2 = 0; 11843 arr_idx2 <= reg_info->count2; 11844 arr_idx2++) { 11845 reg_offset = arr_idx * reg_info->stride1 + 11846 arr_idx2 * reg_info->stride2; 11847 reg_offset += reg_info->base_addr; 11848 if (!i40e_valid_regs(hw->mac.type, reg_offset)) 11849 ptr_data[reg_offset >> 2] = 0; 11850 else 11851 ptr_data[reg_offset >> 2] = 11852 I40E_READ_REG(hw, reg_offset); 11853 } 11854 } 11855 11856 return 0; 11857 } 11858 11859 static int i40e_get_eeprom_length(struct rte_eth_dev *dev) 11860 { 11861 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11862 11863 /* Convert word count to byte count */ 11864 return hw->nvm.sr_size << 1; 11865 } 11866 11867 static int i40e_get_eeprom(struct rte_eth_dev *dev, 11868 struct rte_dev_eeprom_info *eeprom) 11869 { 11870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11871 uint16_t *data = eeprom->data; 11872 uint16_t offset, length, cnt_words; 11873 int ret_code; 11874 11875 offset = eeprom->offset >> 1; 11876 length = eeprom->length >> 1; 11877 cnt_words = length; 11878 11879 if (offset > hw->nvm.sr_size || 11880 offset + length > hw->nvm.sr_size) { 11881 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 11882 return -EINVAL; 11883 } 11884 11885 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 11886 11887 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data); 11888 if (ret_code != I40E_SUCCESS || cnt_words != length) { 11889 PMD_DRV_LOG(ERR, "EEPROM read failed."); 11890 return -EIO; 11891 } 11892 11893 return 0; 11894 } 11895 11896 static int i40e_get_module_info(struct rte_eth_dev *dev, 11897 struct rte_eth_dev_module_info *modinfo) 11898 { 11899 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11900 uint32_t sff8472_comp = 0; 11901 uint32_t sff8472_swap = 0; 11902 uint32_t sff8636_rev = 0; 11903 i40e_status status; 11904 uint32_t type = 0; 11905 11906 /* Check if firmware supports reading module EEPROM. */ 11907 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) { 11908 PMD_DRV_LOG(ERR, 11909 "Module EEPROM memory read not supported. " 11910 "Please update the NVM image.\n"); 11911 return -EINVAL; 11912 } 11913 11914 status = i40e_update_link_info(hw); 11915 if (status) 11916 return -EIO; 11917 11918 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) { 11919 PMD_DRV_LOG(ERR, 11920 "Cannot read module EEPROM memory. " 11921 "No module connected.\n"); 11922 return -EINVAL; 11923 } 11924 11925 type = hw->phy.link_info.module_type[0]; 11926 11927 switch (type) { 11928 case I40E_MODULE_TYPE_SFP: 11929 status = i40e_aq_get_phy_register(hw, 11930 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11931 I40E_I2C_EEPROM_DEV_ADDR, 1, 11932 I40E_MODULE_SFF_8472_COMP, 11933 &sff8472_comp, NULL); 11934 if (status) 11935 return -EIO; 11936 11937 status = i40e_aq_get_phy_register(hw, 11938 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11939 I40E_I2C_EEPROM_DEV_ADDR, 1, 11940 I40E_MODULE_SFF_8472_SWAP, 11941 &sff8472_swap, NULL); 11942 if (status) 11943 return -EIO; 11944 11945 /* Check if the module requires address swap to access 11946 * the other EEPROM memory page. 11947 */ 11948 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) { 11949 PMD_DRV_LOG(WARNING, 11950 "Module address swap to access " 11951 "page 0xA2 is not supported.\n"); 11952 modinfo->type = RTE_ETH_MODULE_SFF_8079; 11953 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 11954 } else if (sff8472_comp == 0x00) { 11955 /* Module is not SFF-8472 compliant */ 11956 modinfo->type = RTE_ETH_MODULE_SFF_8079; 11957 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 11958 } else { 11959 modinfo->type = RTE_ETH_MODULE_SFF_8472; 11960 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 11961 } 11962 break; 11963 case I40E_MODULE_TYPE_QSFP_PLUS: 11964 /* Read from memory page 0. */ 11965 status = i40e_aq_get_phy_register(hw, 11966 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 11967 0, 1, 11968 I40E_MODULE_REVISION_ADDR, 11969 &sff8636_rev, NULL); 11970 if (status) 11971 return -EIO; 11972 /* Determine revision compliance byte */ 11973 if (sff8636_rev > 0x02) { 11974 /* Module is SFF-8636 compliant */ 11975 modinfo->type = RTE_ETH_MODULE_SFF_8636; 11976 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11977 } else { 11978 modinfo->type = RTE_ETH_MODULE_SFF_8436; 11979 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11980 } 11981 break; 11982 case I40E_MODULE_TYPE_QSFP28: 11983 modinfo->type = RTE_ETH_MODULE_SFF_8636; 11984 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN; 11985 break; 11986 default: 11987 PMD_DRV_LOG(ERR, "Module type unrecognized\n"); 11988 return -EINVAL; 11989 } 11990 return 0; 11991 } 11992 11993 static int i40e_get_module_eeprom(struct rte_eth_dev *dev, 11994 struct rte_dev_eeprom_info *info) 11995 { 11996 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 11997 bool is_sfp = false; 11998 i40e_status status; 11999 uint8_t *data; 12000 uint32_t value = 0; 12001 uint32_t i; 12002 12003 if (!info || !info->length || !info->data) 12004 return -EINVAL; 12005 12006 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP) 12007 is_sfp = true; 12008 12009 data = info->data; 12010 for (i = 0; i < info->length; i++) { 12011 u32 offset = i + info->offset; 12012 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0; 12013 12014 /* Check if we need to access the other memory page */ 12015 if (is_sfp) { 12016 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) { 12017 offset -= RTE_ETH_MODULE_SFF_8079_LEN; 12018 addr = I40E_I2C_EEPROM_DEV_ADDR2; 12019 } 12020 } else { 12021 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) { 12022 /* Compute memory page number and offset. */ 12023 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2; 12024 addr++; 12025 } 12026 } 12027 status = i40e_aq_get_phy_register(hw, 12028 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, 12029 addr, offset, 1, &value, NULL); 12030 if (status) 12031 return -EIO; 12032 data[i] = (uint8_t)value; 12033 } 12034 return 0; 12035 } 12036 12037 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev, 12038 struct rte_ether_addr *mac_addr) 12039 { 12040 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 12041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12042 struct i40e_vsi *vsi = pf->main_vsi; 12043 struct i40e_mac_filter_info mac_filter; 12044 struct i40e_mac_filter *f; 12045 int ret; 12046 12047 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 12048 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 12049 return -EINVAL; 12050 } 12051 12052 TAILQ_FOREACH(f, &vsi->mac_list, next) { 12053 if (rte_is_same_ether_addr(&pf->dev_addr, 12054 &f->mac_info.mac_addr)) 12055 break; 12056 } 12057 12058 if (f == NULL) { 12059 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 12060 return -EIO; 12061 } 12062 12063 mac_filter = f->mac_info; 12064 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr); 12065 if (ret != I40E_SUCCESS) { 12066 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 12067 return -EIO; 12068 } 12069 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN); 12070 ret = i40e_vsi_add_mac(vsi, &mac_filter); 12071 if (ret != I40E_SUCCESS) { 12072 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 12073 return -EIO; 12074 } 12075 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN); 12076 12077 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL, 12078 mac_addr->addr_bytes, NULL); 12079 if (ret != I40E_SUCCESS) { 12080 PMD_DRV_LOG(ERR, "Failed to change mac"); 12081 return -EIO; 12082 } 12083 12084 return 0; 12085 } 12086 12087 static int 12088 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 12089 { 12090 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12091 struct rte_eth_dev_data *dev_data = pf->dev_data; 12092 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD; 12093 int ret = 0; 12094 12095 /* check if mtu is within the allowed range */ 12096 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX) 12097 return -EINVAL; 12098 12099 /* mtu setting is forbidden if port is start */ 12100 if (dev_data->dev_started) { 12101 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 12102 dev_data->port_id); 12103 return -EBUSY; 12104 } 12105 12106 if (frame_size > RTE_ETHER_MAX_LEN) 12107 dev_data->dev_conf.rxmode.offloads |= 12108 DEV_RX_OFFLOAD_JUMBO_FRAME; 12109 else 12110 dev_data->dev_conf.rxmode.offloads &= 12111 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 12112 12113 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 12114 12115 return ret; 12116 } 12117 12118 /* Restore ethertype filter */ 12119 static void 12120 i40e_ethertype_filter_restore(struct i40e_pf *pf) 12121 { 12122 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12123 struct i40e_ethertype_filter_list 12124 *ethertype_list = &pf->ethertype.ethertype_list; 12125 struct i40e_ethertype_filter *f; 12126 struct i40e_control_filter_stats stats; 12127 uint16_t flags; 12128 12129 TAILQ_FOREACH(f, ethertype_list, rules) { 12130 flags = 0; 12131 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC)) 12132 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 12133 if (f->flags & RTE_ETHTYPE_FLAGS_DROP) 12134 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 12135 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 12136 12137 memset(&stats, 0, sizeof(stats)); 12138 i40e_aq_add_rem_control_packet_filter(hw, 12139 f->input.mac_addr.addr_bytes, 12140 f->input.ether_type, 12141 flags, pf->main_vsi->seid, 12142 f->queue, 1, &stats, NULL); 12143 } 12144 PMD_DRV_LOG(INFO, "Ethertype filter:" 12145 " mac_etype_used = %u, etype_used = %u," 12146 " mac_etype_free = %u, etype_free = %u", 12147 stats.mac_etype_used, stats.etype_used, 12148 stats.mac_etype_free, stats.etype_free); 12149 } 12150 12151 /* Restore tunnel filter */ 12152 static void 12153 i40e_tunnel_filter_restore(struct i40e_pf *pf) 12154 { 12155 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12156 struct i40e_vsi *vsi; 12157 struct i40e_pf_vf *vf; 12158 struct i40e_tunnel_filter_list 12159 *tunnel_list = &pf->tunnel.tunnel_list; 12160 struct i40e_tunnel_filter *f; 12161 struct i40e_aqc_cloud_filters_element_bb cld_filter; 12162 bool big_buffer = 0; 12163 12164 TAILQ_FOREACH(f, tunnel_list, rules) { 12165 if (!f->is_to_vf) 12166 vsi = pf->main_vsi; 12167 else { 12168 vf = &pf->vfs[f->vf_id]; 12169 vsi = vf->vsi; 12170 } 12171 memset(&cld_filter, 0, sizeof(cld_filter)); 12172 rte_ether_addr_copy((struct rte_ether_addr *) 12173 &f->input.outer_mac, 12174 (struct rte_ether_addr *)&cld_filter.element.outer_mac); 12175 rte_ether_addr_copy((struct rte_ether_addr *) 12176 &f->input.inner_mac, 12177 (struct rte_ether_addr *)&cld_filter.element.inner_mac); 12178 cld_filter.element.inner_vlan = f->input.inner_vlan; 12179 cld_filter.element.flags = f->input.flags; 12180 cld_filter.element.tenant_id = f->input.tenant_id; 12181 cld_filter.element.queue_number = f->queue; 12182 rte_memcpy(cld_filter.general_fields, 12183 f->input.general_fields, 12184 sizeof(f->input.general_fields)); 12185 12186 if (((f->input.flags & 12187 I40E_AQC_ADD_CLOUD_FILTER_0X11) == 12188 I40E_AQC_ADD_CLOUD_FILTER_0X11) || 12189 ((f->input.flags & 12190 I40E_AQC_ADD_CLOUD_FILTER_0X12) == 12191 I40E_AQC_ADD_CLOUD_FILTER_0X12) || 12192 ((f->input.flags & 12193 I40E_AQC_ADD_CLOUD_FILTER_0X10) == 12194 I40E_AQC_ADD_CLOUD_FILTER_0X10)) 12195 big_buffer = 1; 12196 12197 if (big_buffer) 12198 i40e_aq_add_cloud_filters_bb(hw, 12199 vsi->seid, &cld_filter, 1); 12200 else 12201 i40e_aq_add_cloud_filters(hw, vsi->seid, 12202 &cld_filter.element, 1); 12203 } 12204 } 12205 12206 /* Restore rss filter */ 12207 static inline void 12208 i40e_rss_filter_restore(struct i40e_pf *pf) 12209 { 12210 struct i40e_rte_flow_rss_conf *conf = 12211 &pf->rss_info; 12212 if (conf->conf.queue_num) 12213 i40e_config_rss_filter(pf, conf, TRUE); 12214 } 12215 12216 static void 12217 i40e_filter_restore(struct i40e_pf *pf) 12218 { 12219 i40e_ethertype_filter_restore(pf); 12220 i40e_tunnel_filter_restore(pf); 12221 i40e_fdir_filter_restore(pf); 12222 i40e_rss_filter_restore(pf); 12223 } 12224 12225 bool 12226 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 12227 { 12228 if (strcmp(dev->device->driver->name, drv->driver.name)) 12229 return false; 12230 12231 return true; 12232 } 12233 12234 bool 12235 is_i40e_supported(struct rte_eth_dev *dev) 12236 { 12237 return is_device_supported(dev, &rte_i40e_pmd); 12238 } 12239 12240 struct i40e_customized_pctype* 12241 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index) 12242 { 12243 int i; 12244 12245 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) { 12246 if (pf->customized_pctype[i].index == index) 12247 return &pf->customized_pctype[i]; 12248 } 12249 return NULL; 12250 } 12251 12252 static int 12253 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg, 12254 uint32_t pkg_size, uint32_t proto_num, 12255 struct rte_pmd_i40e_proto_info *proto, 12256 enum rte_pmd_i40e_package_op op) 12257 { 12258 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12259 uint32_t pctype_num; 12260 struct rte_pmd_i40e_ptype_info *pctype; 12261 uint32_t buff_size; 12262 struct i40e_customized_pctype *new_pctype = NULL; 12263 uint8_t proto_id; 12264 uint8_t pctype_value; 12265 char name[64]; 12266 uint32_t i, j, n; 12267 int ret; 12268 12269 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12270 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12271 PMD_DRV_LOG(ERR, "Unsupported operation."); 12272 return -1; 12273 } 12274 12275 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12276 (uint8_t *)&pctype_num, sizeof(pctype_num), 12277 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM); 12278 if (ret) { 12279 PMD_DRV_LOG(ERR, "Failed to get pctype number"); 12280 return -1; 12281 } 12282 if (!pctype_num) { 12283 PMD_DRV_LOG(INFO, "No new pctype added"); 12284 return -1; 12285 } 12286 12287 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info); 12288 pctype = rte_zmalloc("new_pctype", buff_size, 0); 12289 if (!pctype) { 12290 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12291 return -1; 12292 } 12293 /* get information about new pctype list */ 12294 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12295 (uint8_t *)pctype, buff_size, 12296 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST); 12297 if (ret) { 12298 PMD_DRV_LOG(ERR, "Failed to get pctype list"); 12299 rte_free(pctype); 12300 return -1; 12301 } 12302 12303 /* Update customized pctype. */ 12304 for (i = 0; i < pctype_num; i++) { 12305 pctype_value = pctype[i].ptype_id; 12306 memset(name, 0, sizeof(name)); 12307 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) { 12308 proto_id = pctype[i].protocols[j]; 12309 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED) 12310 continue; 12311 for (n = 0; n < proto_num; n++) { 12312 if (proto[n].proto_id != proto_id) 12313 continue; 12314 strlcat(name, proto[n].name, sizeof(name)); 12315 strlcat(name, "_", sizeof(name)); 12316 break; 12317 } 12318 } 12319 name[strlen(name) - 1] = '\0'; 12320 if (!strcmp(name, "GTPC")) 12321 new_pctype = 12322 i40e_find_customized_pctype(pf, 12323 I40E_CUSTOMIZED_GTPC); 12324 else if (!strcmp(name, "GTPU_IPV4")) 12325 new_pctype = 12326 i40e_find_customized_pctype(pf, 12327 I40E_CUSTOMIZED_GTPU_IPV4); 12328 else if (!strcmp(name, "GTPU_IPV6")) 12329 new_pctype = 12330 i40e_find_customized_pctype(pf, 12331 I40E_CUSTOMIZED_GTPU_IPV6); 12332 else if (!strcmp(name, "GTPU")) 12333 new_pctype = 12334 i40e_find_customized_pctype(pf, 12335 I40E_CUSTOMIZED_GTPU); 12336 if (new_pctype) { 12337 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) { 12338 new_pctype->pctype = pctype_value; 12339 new_pctype->valid = true; 12340 } else { 12341 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID; 12342 new_pctype->valid = false; 12343 } 12344 } 12345 } 12346 12347 rte_free(pctype); 12348 return 0; 12349 } 12350 12351 static int 12352 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg, 12353 uint32_t pkg_size, uint32_t proto_num, 12354 struct rte_pmd_i40e_proto_info *proto, 12355 enum rte_pmd_i40e_package_op op) 12356 { 12357 struct rte_pmd_i40e_ptype_mapping *ptype_mapping; 12358 uint16_t port_id = dev->data->port_id; 12359 uint32_t ptype_num; 12360 struct rte_pmd_i40e_ptype_info *ptype; 12361 uint32_t buff_size; 12362 uint8_t proto_id; 12363 char name[RTE_PMD_I40E_DDP_NAME_SIZE]; 12364 uint32_t i, j, n; 12365 bool in_tunnel; 12366 int ret; 12367 12368 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12369 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12370 PMD_DRV_LOG(ERR, "Unsupported operation."); 12371 return -1; 12372 } 12373 12374 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) { 12375 rte_pmd_i40e_ptype_mapping_reset(port_id); 12376 return 0; 12377 } 12378 12379 /* get information about new ptype num */ 12380 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12381 (uint8_t *)&ptype_num, sizeof(ptype_num), 12382 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM); 12383 if (ret) { 12384 PMD_DRV_LOG(ERR, "Failed to get ptype number"); 12385 return ret; 12386 } 12387 if (!ptype_num) { 12388 PMD_DRV_LOG(INFO, "No new ptype added"); 12389 return -1; 12390 } 12391 12392 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info); 12393 ptype = rte_zmalloc("new_ptype", buff_size, 0); 12394 if (!ptype) { 12395 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12396 return -1; 12397 } 12398 12399 /* get information about new ptype list */ 12400 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12401 (uint8_t *)ptype, buff_size, 12402 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST); 12403 if (ret) { 12404 PMD_DRV_LOG(ERR, "Failed to get ptype list"); 12405 rte_free(ptype); 12406 return ret; 12407 } 12408 12409 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping); 12410 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0); 12411 if (!ptype_mapping) { 12412 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12413 rte_free(ptype); 12414 return -1; 12415 } 12416 12417 /* Update ptype mapping table. */ 12418 for (i = 0; i < ptype_num; i++) { 12419 ptype_mapping[i].hw_ptype = ptype[i].ptype_id; 12420 ptype_mapping[i].sw_ptype = 0; 12421 in_tunnel = false; 12422 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) { 12423 proto_id = ptype[i].protocols[j]; 12424 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED) 12425 continue; 12426 for (n = 0; n < proto_num; n++) { 12427 if (proto[n].proto_id != proto_id) 12428 continue; 12429 memset(name, 0, sizeof(name)); 12430 strcpy(name, proto[n].name); 12431 if (!strncasecmp(name, "PPPOE", 5)) 12432 ptype_mapping[i].sw_ptype |= 12433 RTE_PTYPE_L2_ETHER_PPPOE; 12434 else if (!strncasecmp(name, "IPV4FRAG", 8) && 12435 !in_tunnel) { 12436 ptype_mapping[i].sw_ptype |= 12437 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12438 ptype_mapping[i].sw_ptype |= 12439 RTE_PTYPE_L4_FRAG; 12440 } else if (!strncasecmp(name, "IPV4FRAG", 8) && 12441 in_tunnel) { 12442 ptype_mapping[i].sw_ptype |= 12443 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 12444 ptype_mapping[i].sw_ptype |= 12445 RTE_PTYPE_INNER_L4_FRAG; 12446 } else if (!strncasecmp(name, "OIPV4", 5)) { 12447 ptype_mapping[i].sw_ptype |= 12448 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12449 in_tunnel = true; 12450 } else if (!strncasecmp(name, "IPV4", 4) && 12451 !in_tunnel) 12452 ptype_mapping[i].sw_ptype |= 12453 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 12454 else if (!strncasecmp(name, "IPV4", 4) && 12455 in_tunnel) 12456 ptype_mapping[i].sw_ptype |= 12457 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 12458 else if (!strncasecmp(name, "IPV6FRAG", 8) && 12459 !in_tunnel) { 12460 ptype_mapping[i].sw_ptype |= 12461 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12462 ptype_mapping[i].sw_ptype |= 12463 RTE_PTYPE_L4_FRAG; 12464 } else if (!strncasecmp(name, "IPV6FRAG", 8) && 12465 in_tunnel) { 12466 ptype_mapping[i].sw_ptype |= 12467 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 12468 ptype_mapping[i].sw_ptype |= 12469 RTE_PTYPE_INNER_L4_FRAG; 12470 } else if (!strncasecmp(name, "OIPV6", 5)) { 12471 ptype_mapping[i].sw_ptype |= 12472 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12473 in_tunnel = true; 12474 } else if (!strncasecmp(name, "IPV6", 4) && 12475 !in_tunnel) 12476 ptype_mapping[i].sw_ptype |= 12477 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 12478 else if (!strncasecmp(name, "IPV6", 4) && 12479 in_tunnel) 12480 ptype_mapping[i].sw_ptype |= 12481 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 12482 else if (!strncasecmp(name, "UDP", 3) && 12483 !in_tunnel) 12484 ptype_mapping[i].sw_ptype |= 12485 RTE_PTYPE_L4_UDP; 12486 else if (!strncasecmp(name, "UDP", 3) && 12487 in_tunnel) 12488 ptype_mapping[i].sw_ptype |= 12489 RTE_PTYPE_INNER_L4_UDP; 12490 else if (!strncasecmp(name, "TCP", 3) && 12491 !in_tunnel) 12492 ptype_mapping[i].sw_ptype |= 12493 RTE_PTYPE_L4_TCP; 12494 else if (!strncasecmp(name, "TCP", 3) && 12495 in_tunnel) 12496 ptype_mapping[i].sw_ptype |= 12497 RTE_PTYPE_INNER_L4_TCP; 12498 else if (!strncasecmp(name, "SCTP", 4) && 12499 !in_tunnel) 12500 ptype_mapping[i].sw_ptype |= 12501 RTE_PTYPE_L4_SCTP; 12502 else if (!strncasecmp(name, "SCTP", 4) && 12503 in_tunnel) 12504 ptype_mapping[i].sw_ptype |= 12505 RTE_PTYPE_INNER_L4_SCTP; 12506 else if ((!strncasecmp(name, "ICMP", 4) || 12507 !strncasecmp(name, "ICMPV6", 6)) && 12508 !in_tunnel) 12509 ptype_mapping[i].sw_ptype |= 12510 RTE_PTYPE_L4_ICMP; 12511 else if ((!strncasecmp(name, "ICMP", 4) || 12512 !strncasecmp(name, "ICMPV6", 6)) && 12513 in_tunnel) 12514 ptype_mapping[i].sw_ptype |= 12515 RTE_PTYPE_INNER_L4_ICMP; 12516 else if (!strncasecmp(name, "GTPC", 4)) { 12517 ptype_mapping[i].sw_ptype |= 12518 RTE_PTYPE_TUNNEL_GTPC; 12519 in_tunnel = true; 12520 } else if (!strncasecmp(name, "GTPU", 4)) { 12521 ptype_mapping[i].sw_ptype |= 12522 RTE_PTYPE_TUNNEL_GTPU; 12523 in_tunnel = true; 12524 } else if (!strncasecmp(name, "GRENAT", 6)) { 12525 ptype_mapping[i].sw_ptype |= 12526 RTE_PTYPE_TUNNEL_GRENAT; 12527 in_tunnel = true; 12528 } else if (!strncasecmp(name, "L2TPV2CTL", 9) || 12529 !strncasecmp(name, "L2TPV2", 6)) { 12530 ptype_mapping[i].sw_ptype |= 12531 RTE_PTYPE_TUNNEL_L2TP; 12532 in_tunnel = true; 12533 } 12534 12535 break; 12536 } 12537 } 12538 } 12539 12540 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping, 12541 ptype_num, 0); 12542 if (ret) 12543 PMD_DRV_LOG(ERR, "Failed to update mapping table."); 12544 12545 rte_free(ptype_mapping); 12546 rte_free(ptype); 12547 return ret; 12548 } 12549 12550 void 12551 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg, 12552 uint32_t pkg_size, enum rte_pmd_i40e_package_op op) 12553 { 12554 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 12555 uint32_t proto_num; 12556 struct rte_pmd_i40e_proto_info *proto; 12557 uint32_t buff_size; 12558 uint32_t i; 12559 int ret; 12560 12561 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD && 12562 op != RTE_PMD_I40E_PKG_OP_WR_DEL) { 12563 PMD_DRV_LOG(ERR, "Unsupported operation."); 12564 return; 12565 } 12566 12567 /* get information about protocol number */ 12568 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12569 (uint8_t *)&proto_num, sizeof(proto_num), 12570 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM); 12571 if (ret) { 12572 PMD_DRV_LOG(ERR, "Failed to get protocol number"); 12573 return; 12574 } 12575 if (!proto_num) { 12576 PMD_DRV_LOG(INFO, "No new protocol added"); 12577 return; 12578 } 12579 12580 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info); 12581 proto = rte_zmalloc("new_proto", buff_size, 0); 12582 if (!proto) { 12583 PMD_DRV_LOG(ERR, "Failed to allocate memory"); 12584 return; 12585 } 12586 12587 /* get information about protocol list */ 12588 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size, 12589 (uint8_t *)proto, buff_size, 12590 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST); 12591 if (ret) { 12592 PMD_DRV_LOG(ERR, "Failed to get protocol list"); 12593 rte_free(proto); 12594 return; 12595 } 12596 12597 /* Check if GTP is supported. */ 12598 for (i = 0; i < proto_num; i++) { 12599 if (!strncmp(proto[i].name, "GTP", 3)) { 12600 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) 12601 pf->gtp_support = true; 12602 else 12603 pf->gtp_support = false; 12604 break; 12605 } 12606 } 12607 12608 /* Update customized pctype info */ 12609 ret = i40e_update_customized_pctype(dev, pkg, pkg_size, 12610 proto_num, proto, op); 12611 if (ret) 12612 PMD_DRV_LOG(INFO, "No pctype is updated."); 12613 12614 /* Update customized ptype info */ 12615 ret = i40e_update_customized_ptype(dev, pkg, pkg_size, 12616 proto_num, proto, op); 12617 if (ret) 12618 PMD_DRV_LOG(INFO, "No ptype is updated."); 12619 12620 rte_free(proto); 12621 } 12622 12623 /* Create a QinQ cloud filter 12624 * 12625 * The Fortville NIC has limited resources for tunnel filters, 12626 * so we can only reuse existing filters. 12627 * 12628 * In step 1 we define which Field Vector fields can be used for 12629 * filter types. 12630 * As we do not have the inner tag defined as a field, 12631 * we have to define it first, by reusing one of L1 entries. 12632 * 12633 * In step 2 we are replacing one of existing filter types with 12634 * a new one for QinQ. 12635 * As we reusing L1 and replacing L2, some of the default filter 12636 * types will disappear,which depends on L1 and L2 entries we reuse. 12637 * 12638 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b) 12639 * 12640 * 1. Create L1 filter of outer vlan (12b) which will be in use 12641 * later when we define the cloud filter. 12642 * a. Valid_flags.replace_cloud = 0 12643 * b. Old_filter = 10 (Stag_Inner_Vlan) 12644 * c. New_filter = 0x10 12645 * d. TR bit = 0xff (optional, not used here) 12646 * e. Buffer – 2 entries: 12647 * i. Byte 0 = 8 (outer vlan FV index). 12648 * Byte 1 = 0 (rsv) 12649 * Byte 2-3 = 0x0fff 12650 * ii. Byte 0 = 37 (inner vlan FV index). 12651 * Byte 1 =0 (rsv) 12652 * Byte 2-3 = 0x0fff 12653 * 12654 * Step 2: 12655 * 2. Create cloud filter using two L1 filters entries: stag and 12656 * new filter(outer vlan+ inner vlan) 12657 * a. Valid_flags.replace_cloud = 1 12658 * b. Old_filter = 1 (instead of outer IP) 12659 * c. New_filter = 0x10 12660 * d. Buffer – 2 entries: 12661 * i. Byte 0 = 0x80 | 7 (valid | Stag). 12662 * Byte 1-3 = 0 (rsv) 12663 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1) 12664 * Byte 9-11 = 0 (rsv) 12665 */ 12666 static int 12667 i40e_cloud_filter_qinq_create(struct i40e_pf *pf) 12668 { 12669 int ret = -ENOTSUP; 12670 struct i40e_aqc_replace_cloud_filters_cmd filter_replace; 12671 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; 12672 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12673 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev; 12674 12675 if (pf->support_multi_driver) { 12676 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported."); 12677 return ret; 12678 } 12679 12680 /* Init */ 12681 memset(&filter_replace, 0, 12682 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 12683 memset(&filter_replace_buf, 0, 12684 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 12685 12686 /* create L1 filter */ 12687 filter_replace.old_filter_type = 12688 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN; 12689 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12690 filter_replace.tr_bit = 0; 12691 12692 /* Prepare the buffer, 2 entries */ 12693 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN; 12694 filter_replace_buf.data[0] |= 12695 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12696 /* Field Vector 12b mask */ 12697 filter_replace_buf.data[2] = 0xff; 12698 filter_replace_buf.data[3] = 0x0f; 12699 filter_replace_buf.data[4] = 12700 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN; 12701 filter_replace_buf.data[4] |= 12702 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12703 /* Field Vector 12b mask */ 12704 filter_replace_buf.data[6] = 0xff; 12705 filter_replace_buf.data[7] = 0x0f; 12706 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, 12707 &filter_replace_buf); 12708 if (ret != I40E_SUCCESS) 12709 return ret; 12710 12711 if (filter_replace.old_filter_type != 12712 filter_replace.new_filter_type) 12713 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type." 12714 " original: 0x%x, new: 0x%x", 12715 dev->device->name, 12716 filter_replace.old_filter_type, 12717 filter_replace.new_filter_type); 12718 12719 /* Apply the second L2 cloud filter */ 12720 memset(&filter_replace, 0, 12721 sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); 12722 memset(&filter_replace_buf, 0, 12723 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); 12724 12725 /* create L2 filter, input for L2 filter will be L1 filter */ 12726 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER; 12727 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP; 12728 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12729 12730 /* Prepare the buffer, 2 entries */ 12731 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; 12732 filter_replace_buf.data[0] |= 12733 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12734 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10; 12735 filter_replace_buf.data[4] |= 12736 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; 12737 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, 12738 &filter_replace_buf); 12739 if (!ret && (filter_replace.old_filter_type != 12740 filter_replace.new_filter_type)) 12741 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type." 12742 " original: 0x%x, new: 0x%x", 12743 dev->device->name, 12744 filter_replace.old_filter_type, 12745 filter_replace.new_filter_type); 12746 12747 return ret; 12748 } 12749 12750 int 12751 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out, 12752 const struct rte_flow_action_rss *in) 12753 { 12754 if (in->key_len > RTE_DIM(out->key) || 12755 in->queue_num > RTE_DIM(out->queue)) 12756 return -EINVAL; 12757 if (!in->key && in->key_len) 12758 return -EINVAL; 12759 out->conf = (struct rte_flow_action_rss){ 12760 .func = in->func, 12761 .level = in->level, 12762 .types = in->types, 12763 .key_len = in->key_len, 12764 .queue_num = in->queue_num, 12765 .queue = memcpy(out->queue, in->queue, 12766 sizeof(*in->queue) * in->queue_num), 12767 }; 12768 if (in->key) 12769 out->conf.key = memcpy(out->key, in->key, in->key_len); 12770 return 0; 12771 } 12772 12773 int 12774 i40e_action_rss_same(const struct rte_flow_action_rss *comp, 12775 const struct rte_flow_action_rss *with) 12776 { 12777 return (comp->func == with->func && 12778 comp->level == with->level && 12779 comp->types == with->types && 12780 comp->key_len == with->key_len && 12781 comp->queue_num == with->queue_num && 12782 !memcmp(comp->key, with->key, with->key_len) && 12783 !memcmp(comp->queue, with->queue, 12784 sizeof(*with->queue) * with->queue_num)); 12785 } 12786 12787 int 12788 i40e_config_rss_filter(struct i40e_pf *pf, 12789 struct i40e_rte_flow_rss_conf *conf, bool add) 12790 { 12791 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 12792 uint32_t i, lut = 0; 12793 uint16_t j, num; 12794 struct rte_eth_rss_conf rss_conf = { 12795 .rss_key = conf->conf.key_len ? 12796 (void *)(uintptr_t)conf->conf.key : NULL, 12797 .rss_key_len = conf->conf.key_len, 12798 .rss_hf = conf->conf.types, 12799 }; 12800 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 12801 12802 if (!add) { 12803 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) { 12804 i40e_pf_disable_rss(pf); 12805 memset(rss_info, 0, 12806 sizeof(struct i40e_rte_flow_rss_conf)); 12807 return 0; 12808 } 12809 return -EINVAL; 12810 } 12811 12812 /* If both VMDQ and RSS enabled, not all of PF queues are configured. 12813 * It's necessary to calculate the actual PF queues that are configured. 12814 */ 12815 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) 12816 num = i40e_pf_calc_configured_queues_num(pf); 12817 else 12818 num = pf->dev_data->nb_rx_queues; 12819 12820 num = RTE_MIN(num, conf->conf.queue_num); 12821 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured", 12822 num); 12823 12824 if (num == 0) { 12825 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS"); 12826 return -ENOTSUP; 12827 } 12828 12829 /* Fill in redirection table */ 12830 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) { 12831 if (j == num) 12832 j = 0; 12833 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 << 12834 hw->func_caps.rss_table_entry_width) - 1)); 12835 if ((i & 3) == 3) 12836 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut); 12837 } 12838 12839 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) { 12840 i40e_pf_disable_rss(pf); 12841 return 0; 12842 } 12843 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < 12844 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 12845 /* Random default keys */ 12846 static uint32_t rss_key_default[] = {0x6b793944, 12847 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8, 12848 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605, 12849 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581}; 12850 12851 rss_conf.rss_key = (uint8_t *)rss_key_default; 12852 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 12853 sizeof(uint32_t); 12854 PMD_DRV_LOG(INFO, 12855 "No valid RSS key config for i40e, using default\n"); 12856 } 12857 12858 i40e_hw_rss_hash_set(pf, &rss_conf); 12859 12860 if (i40e_rss_conf_init(rss_info, &conf->conf)) 12861 return -EINVAL; 12862 12863 return 0; 12864 } 12865 12866 RTE_INIT(i40e_init_log) 12867 { 12868 i40e_logtype_init = rte_log_register("pmd.net.i40e.init"); 12869 if (i40e_logtype_init >= 0) 12870 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE); 12871 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver"); 12872 if (i40e_logtype_driver >= 0) 12873 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE); 12874 12875 #ifdef RTE_LIBRTE_I40E_DEBUG_RX 12876 i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx"); 12877 if (i40e_logtype_rx >= 0) 12878 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG); 12879 #endif 12880 12881 #ifdef RTE_LIBRTE_I40E_DEBUG_TX 12882 i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx"); 12883 if (i40e_logtype_tx >= 0) 12884 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG); 12885 #endif 12886 12887 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE 12888 i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free"); 12889 if (i40e_logtype_tx_free >= 0) 12890 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG); 12891 #endif 12892 } 12893 12894 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, 12895 ETH_I40E_FLOATING_VEB_ARG "=1" 12896 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>" 12897 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16" 12898 ETH_I40E_SUPPORT_MULTI_DRIVER "=1" 12899 ETH_I40E_USE_LATEST_VEC "=0|1"); 12900