1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #include "i40e_type.h" 6 #include "i40e_adminq.h" 7 #include "i40e_prototype.h" 8 #include "virtchnl.h" 9 10 /** 11 * i40e_set_mac_type - Sets MAC type 12 * @hw: pointer to the HW structure 13 * 14 * This function sets the mac type of the adapter based on the 15 * vendor ID and device ID stored in the hw structure. 16 **/ 17 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 18 { 19 enum i40e_status_code status = I40E_SUCCESS; 20 21 DEBUGFUNC("i40e_set_mac_type\n"); 22 23 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 24 switch (hw->device_id) { 25 case I40E_DEV_ID_SFP_XL710: 26 case I40E_DEV_ID_QEMU: 27 case I40E_DEV_ID_KX_B: 28 case I40E_DEV_ID_KX_C: 29 case I40E_DEV_ID_QSFP_A: 30 case I40E_DEV_ID_QSFP_B: 31 case I40E_DEV_ID_QSFP_C: 32 case I40E_DEV_ID_10G_BASE_T: 33 case I40E_DEV_ID_10G_BASE_T4: 34 case I40E_DEV_ID_10G_BASE_T_BC: 35 case I40E_DEV_ID_10G_B: 36 case I40E_DEV_ID_10G_SFP: 37 case I40E_DEV_ID_5G_BASE_T_BC: 38 case I40E_DEV_ID_20G_KR2: 39 case I40E_DEV_ID_20G_KR2_A: 40 case I40E_DEV_ID_25G_B: 41 case I40E_DEV_ID_25G_SFP28: 42 case I40E_DEV_ID_X710_N3000: 43 case I40E_DEV_ID_XXV710_N3000: 44 hw->mac.type = I40E_MAC_XL710; 45 break; 46 #ifdef X722_A0_SUPPORT 47 case I40E_DEV_ID_X722_A0: 48 #endif 49 case I40E_DEV_ID_KX_X722: 50 case I40E_DEV_ID_QSFP_X722: 51 case I40E_DEV_ID_SFP_X722: 52 case I40E_DEV_ID_1G_BASE_T_X722: 53 case I40E_DEV_ID_10G_BASE_T_X722: 54 case I40E_DEV_ID_SFP_I_X722: 55 hw->mac.type = I40E_MAC_X722; 56 break; 57 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 58 case I40E_DEV_ID_X722_VF: 59 #ifdef X722_A0_SUPPORT 60 case I40E_DEV_ID_X722_A0_VF: 61 #endif 62 hw->mac.type = I40E_MAC_X722_VF; 63 break; 64 #endif /* INTEGRATED_VF || VF_DRIVER */ 65 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 66 case I40E_DEV_ID_VF: 67 case I40E_DEV_ID_VF_HV: 68 case I40E_DEV_ID_ADAPTIVE_VF: 69 hw->mac.type = I40E_MAC_VF; 70 break; 71 #endif 72 default: 73 hw->mac.type = I40E_MAC_GENERIC; 74 break; 75 } 76 } else { 77 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 78 } 79 80 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 81 hw->mac.type, status); 82 return status; 83 } 84 85 /** 86 * i40e_aq_str - convert AQ err code to a string 87 * @hw: pointer to the HW structure 88 * @aq_err: the AQ error code to convert 89 **/ 90 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 91 { 92 switch (aq_err) { 93 case I40E_AQ_RC_OK: 94 return "OK"; 95 case I40E_AQ_RC_EPERM: 96 return "I40E_AQ_RC_EPERM"; 97 case I40E_AQ_RC_ENOENT: 98 return "I40E_AQ_RC_ENOENT"; 99 case I40E_AQ_RC_ESRCH: 100 return "I40E_AQ_RC_ESRCH"; 101 case I40E_AQ_RC_EINTR: 102 return "I40E_AQ_RC_EINTR"; 103 case I40E_AQ_RC_EIO: 104 return "I40E_AQ_RC_EIO"; 105 case I40E_AQ_RC_ENXIO: 106 return "I40E_AQ_RC_ENXIO"; 107 case I40E_AQ_RC_E2BIG: 108 return "I40E_AQ_RC_E2BIG"; 109 case I40E_AQ_RC_EAGAIN: 110 return "I40E_AQ_RC_EAGAIN"; 111 case I40E_AQ_RC_ENOMEM: 112 return "I40E_AQ_RC_ENOMEM"; 113 case I40E_AQ_RC_EACCES: 114 return "I40E_AQ_RC_EACCES"; 115 case I40E_AQ_RC_EFAULT: 116 return "I40E_AQ_RC_EFAULT"; 117 case I40E_AQ_RC_EBUSY: 118 return "I40E_AQ_RC_EBUSY"; 119 case I40E_AQ_RC_EEXIST: 120 return "I40E_AQ_RC_EEXIST"; 121 case I40E_AQ_RC_EINVAL: 122 return "I40E_AQ_RC_EINVAL"; 123 case I40E_AQ_RC_ENOTTY: 124 return "I40E_AQ_RC_ENOTTY"; 125 case I40E_AQ_RC_ENOSPC: 126 return "I40E_AQ_RC_ENOSPC"; 127 case I40E_AQ_RC_ENOSYS: 128 return "I40E_AQ_RC_ENOSYS"; 129 case I40E_AQ_RC_ERANGE: 130 return "I40E_AQ_RC_ERANGE"; 131 case I40E_AQ_RC_EFLUSHED: 132 return "I40E_AQ_RC_EFLUSHED"; 133 case I40E_AQ_RC_BAD_ADDR: 134 return "I40E_AQ_RC_BAD_ADDR"; 135 case I40E_AQ_RC_EMODE: 136 return "I40E_AQ_RC_EMODE"; 137 case I40E_AQ_RC_EFBIG: 138 return "I40E_AQ_RC_EFBIG"; 139 } 140 141 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 142 return hw->err_str; 143 } 144 145 /** 146 * i40e_stat_str - convert status err code to a string 147 * @hw: pointer to the HW structure 148 * @stat_err: the status error code to convert 149 **/ 150 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 151 { 152 switch (stat_err) { 153 case I40E_SUCCESS: 154 return "OK"; 155 case I40E_ERR_NVM: 156 return "I40E_ERR_NVM"; 157 case I40E_ERR_NVM_CHECKSUM: 158 return "I40E_ERR_NVM_CHECKSUM"; 159 case I40E_ERR_PHY: 160 return "I40E_ERR_PHY"; 161 case I40E_ERR_CONFIG: 162 return "I40E_ERR_CONFIG"; 163 case I40E_ERR_PARAM: 164 return "I40E_ERR_PARAM"; 165 case I40E_ERR_MAC_TYPE: 166 return "I40E_ERR_MAC_TYPE"; 167 case I40E_ERR_UNKNOWN_PHY: 168 return "I40E_ERR_UNKNOWN_PHY"; 169 case I40E_ERR_LINK_SETUP: 170 return "I40E_ERR_LINK_SETUP"; 171 case I40E_ERR_ADAPTER_STOPPED: 172 return "I40E_ERR_ADAPTER_STOPPED"; 173 case I40E_ERR_INVALID_MAC_ADDR: 174 return "I40E_ERR_INVALID_MAC_ADDR"; 175 case I40E_ERR_DEVICE_NOT_SUPPORTED: 176 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 177 case I40E_ERR_MASTER_REQUESTS_PENDING: 178 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 179 case I40E_ERR_INVALID_LINK_SETTINGS: 180 return "I40E_ERR_INVALID_LINK_SETTINGS"; 181 case I40E_ERR_AUTONEG_NOT_COMPLETE: 182 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 183 case I40E_ERR_RESET_FAILED: 184 return "I40E_ERR_RESET_FAILED"; 185 case I40E_ERR_SWFW_SYNC: 186 return "I40E_ERR_SWFW_SYNC"; 187 case I40E_ERR_NO_AVAILABLE_VSI: 188 return "I40E_ERR_NO_AVAILABLE_VSI"; 189 case I40E_ERR_NO_MEMORY: 190 return "I40E_ERR_NO_MEMORY"; 191 case I40E_ERR_BAD_PTR: 192 return "I40E_ERR_BAD_PTR"; 193 case I40E_ERR_RING_FULL: 194 return "I40E_ERR_RING_FULL"; 195 case I40E_ERR_INVALID_PD_ID: 196 return "I40E_ERR_INVALID_PD_ID"; 197 case I40E_ERR_INVALID_QP_ID: 198 return "I40E_ERR_INVALID_QP_ID"; 199 case I40E_ERR_INVALID_CQ_ID: 200 return "I40E_ERR_INVALID_CQ_ID"; 201 case I40E_ERR_INVALID_CEQ_ID: 202 return "I40E_ERR_INVALID_CEQ_ID"; 203 case I40E_ERR_INVALID_AEQ_ID: 204 return "I40E_ERR_INVALID_AEQ_ID"; 205 case I40E_ERR_INVALID_SIZE: 206 return "I40E_ERR_INVALID_SIZE"; 207 case I40E_ERR_INVALID_ARP_INDEX: 208 return "I40E_ERR_INVALID_ARP_INDEX"; 209 case I40E_ERR_INVALID_FPM_FUNC_ID: 210 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 211 case I40E_ERR_QP_INVALID_MSG_SIZE: 212 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 213 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 214 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 215 case I40E_ERR_INVALID_FRAG_COUNT: 216 return "I40E_ERR_INVALID_FRAG_COUNT"; 217 case I40E_ERR_QUEUE_EMPTY: 218 return "I40E_ERR_QUEUE_EMPTY"; 219 case I40E_ERR_INVALID_ALIGNMENT: 220 return "I40E_ERR_INVALID_ALIGNMENT"; 221 case I40E_ERR_FLUSHED_QUEUE: 222 return "I40E_ERR_FLUSHED_QUEUE"; 223 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 224 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 225 case I40E_ERR_INVALID_IMM_DATA_SIZE: 226 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 227 case I40E_ERR_TIMEOUT: 228 return "I40E_ERR_TIMEOUT"; 229 case I40E_ERR_OPCODE_MISMATCH: 230 return "I40E_ERR_OPCODE_MISMATCH"; 231 case I40E_ERR_CQP_COMPL_ERROR: 232 return "I40E_ERR_CQP_COMPL_ERROR"; 233 case I40E_ERR_INVALID_VF_ID: 234 return "I40E_ERR_INVALID_VF_ID"; 235 case I40E_ERR_INVALID_HMCFN_ID: 236 return "I40E_ERR_INVALID_HMCFN_ID"; 237 case I40E_ERR_BACKING_PAGE_ERROR: 238 return "I40E_ERR_BACKING_PAGE_ERROR"; 239 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 240 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 241 case I40E_ERR_INVALID_PBLE_INDEX: 242 return "I40E_ERR_INVALID_PBLE_INDEX"; 243 case I40E_ERR_INVALID_SD_INDEX: 244 return "I40E_ERR_INVALID_SD_INDEX"; 245 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 246 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 247 case I40E_ERR_INVALID_SD_TYPE: 248 return "I40E_ERR_INVALID_SD_TYPE"; 249 case I40E_ERR_MEMCPY_FAILED: 250 return "I40E_ERR_MEMCPY_FAILED"; 251 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 252 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 253 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 254 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 255 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 256 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 257 case I40E_ERR_SRQ_ENABLED: 258 return "I40E_ERR_SRQ_ENABLED"; 259 case I40E_ERR_ADMIN_QUEUE_ERROR: 260 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 261 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 262 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 263 case I40E_ERR_BUF_TOO_SHORT: 264 return "I40E_ERR_BUF_TOO_SHORT"; 265 case I40E_ERR_ADMIN_QUEUE_FULL: 266 return "I40E_ERR_ADMIN_QUEUE_FULL"; 267 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 268 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 269 case I40E_ERR_BAD_IWARP_CQE: 270 return "I40E_ERR_BAD_IWARP_CQE"; 271 case I40E_ERR_NVM_BLANK_MODE: 272 return "I40E_ERR_NVM_BLANK_MODE"; 273 case I40E_ERR_NOT_IMPLEMENTED: 274 return "I40E_ERR_NOT_IMPLEMENTED"; 275 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 276 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 277 case I40E_ERR_DIAG_TEST_FAILED: 278 return "I40E_ERR_DIAG_TEST_FAILED"; 279 case I40E_ERR_NOT_READY: 280 return "I40E_ERR_NOT_READY"; 281 case I40E_NOT_SUPPORTED: 282 return "I40E_NOT_SUPPORTED"; 283 case I40E_ERR_FIRMWARE_API_VERSION: 284 return "I40E_ERR_FIRMWARE_API_VERSION"; 285 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 286 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 287 } 288 289 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 290 return hw->err_str; 291 } 292 293 /** 294 * i40e_debug_aq 295 * @hw: debug mask related to admin queue 296 * @mask: debug mask 297 * @desc: pointer to admin queue descriptor 298 * @buffer: pointer to command buffer 299 * @buf_len: max length of buffer 300 * 301 * Dumps debug log about adminq command with descriptor contents. 302 **/ 303 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 304 void *buffer, u16 buf_len) 305 { 306 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 307 u32 effective_mask = hw->debug_mask & mask; 308 u8 *buf = (u8 *)buffer; 309 u16 len; 310 u16 i; 311 312 if (!effective_mask || !desc) 313 return; 314 315 len = LE16_TO_CPU(aq_desc->datalen); 316 317 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 318 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 319 LE16_TO_CPU(aq_desc->opcode), 320 LE16_TO_CPU(aq_desc->flags), 321 LE16_TO_CPU(aq_desc->datalen), 322 LE16_TO_CPU(aq_desc->retval)); 323 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 324 "\tcookie (h,l) 0x%08X 0x%08X\n", 325 LE32_TO_CPU(aq_desc->cookie_high), 326 LE32_TO_CPU(aq_desc->cookie_low)); 327 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 328 "\tparam (0,1) 0x%08X 0x%08X\n", 329 LE32_TO_CPU(aq_desc->params.internal.param0), 330 LE32_TO_CPU(aq_desc->params.internal.param1)); 331 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 332 "\taddr (h,l) 0x%08X 0x%08X\n", 333 LE32_TO_CPU(aq_desc->params.external.addr_high), 334 LE32_TO_CPU(aq_desc->params.external.addr_low)); 335 336 if (buffer && (buf_len != 0) && (len != 0) && 337 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 338 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 339 if (buf_len < len) 340 len = buf_len; 341 /* write the full 16-byte chunks */ 342 for (i = 0; i < (len - 16); i += 16) 343 i40e_debug(hw, mask, 344 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 345 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 346 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 347 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 348 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 349 /* the most we could have left is 16 bytes, pad with zeros */ 350 if (i < len) { 351 char d_buf[16]; 352 int j, i_sav; 353 354 i_sav = i; 355 memset(d_buf, 0, sizeof(d_buf)); 356 for (j = 0; i < len; j++, i++) 357 d_buf[j] = buf[i]; 358 i40e_debug(hw, mask, 359 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 360 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 361 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 362 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 363 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 364 } 365 } 366 } 367 368 /** 369 * i40e_check_asq_alive 370 * @hw: pointer to the hw struct 371 * 372 * Returns true if Queue is enabled else false. 373 **/ 374 bool i40e_check_asq_alive(struct i40e_hw *hw) 375 { 376 if (hw->aq.asq.len) 377 #ifdef PF_DRIVER 378 #ifdef INTEGRATED_VF 379 if (!i40e_is_vf(hw)) 380 return !!(rd32(hw, hw->aq.asq.len) & 381 I40E_PF_ATQLEN_ATQENABLE_MASK); 382 #else 383 return !!(rd32(hw, hw->aq.asq.len) & 384 I40E_PF_ATQLEN_ATQENABLE_MASK); 385 #endif /* INTEGRATED_VF */ 386 #endif /* PF_DRIVER */ 387 #ifdef VF_DRIVER 388 #ifdef INTEGRATED_VF 389 if (i40e_is_vf(hw)) 390 return !!(rd32(hw, hw->aq.asq.len) & 391 I40E_VF_ATQLEN1_ATQENABLE_MASK); 392 #else 393 return !!(rd32(hw, hw->aq.asq.len) & 394 I40E_VF_ATQLEN1_ATQENABLE_MASK); 395 #endif /* INTEGRATED_VF */ 396 #endif /* VF_DRIVER */ 397 return false; 398 } 399 400 /** 401 * i40e_aq_queue_shutdown 402 * @hw: pointer to the hw struct 403 * @unloading: is the driver unloading itself 404 * 405 * Tell the Firmware that we're shutting down the AdminQ and whether 406 * or not the driver is unloading as well. 407 **/ 408 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 409 bool unloading) 410 { 411 struct i40e_aq_desc desc; 412 struct i40e_aqc_queue_shutdown *cmd = 413 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 414 enum i40e_status_code status; 415 416 i40e_fill_default_direct_cmd_desc(&desc, 417 i40e_aqc_opc_queue_shutdown); 418 419 if (unloading) 420 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 421 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 422 423 return status; 424 } 425 426 /** 427 * i40e_aq_get_set_rss_lut 428 * @hw: pointer to the hardware structure 429 * @vsi_id: vsi fw index 430 * @pf_lut: for PF table set true, for VSI table set false 431 * @lut: pointer to the lut buffer provided by the caller 432 * @lut_size: size of the lut buffer 433 * @set: set true to set the table, false to get the table 434 * 435 * Internal function to get or set RSS look up table 436 **/ 437 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 438 u16 vsi_id, bool pf_lut, 439 u8 *lut, u16 lut_size, 440 bool set) 441 { 442 enum i40e_status_code status; 443 struct i40e_aq_desc desc; 444 struct i40e_aqc_get_set_rss_lut *cmd_resp = 445 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 446 447 if (set) 448 i40e_fill_default_direct_cmd_desc(&desc, 449 i40e_aqc_opc_set_rss_lut); 450 else 451 i40e_fill_default_direct_cmd_desc(&desc, 452 i40e_aqc_opc_get_rss_lut); 453 454 /* Indirect command */ 455 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 456 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 457 458 cmd_resp->vsi_id = 459 CPU_TO_LE16((u16)((vsi_id << 460 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 461 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 462 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 463 464 if (pf_lut) 465 cmd_resp->flags |= CPU_TO_LE16((u16) 466 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 467 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 468 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 469 else 470 cmd_resp->flags |= CPU_TO_LE16((u16) 471 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 472 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 473 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 474 475 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 476 477 return status; 478 } 479 480 /** 481 * i40e_aq_get_rss_lut 482 * @hw: pointer to the hardware structure 483 * @vsi_id: vsi fw index 484 * @pf_lut: for PF table set true, for VSI table set false 485 * @lut: pointer to the lut buffer provided by the caller 486 * @lut_size: size of the lut buffer 487 * 488 * get the RSS lookup table, PF or VSI type 489 **/ 490 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 491 bool pf_lut, u8 *lut, u16 lut_size) 492 { 493 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 494 false); 495 } 496 497 /** 498 * i40e_aq_set_rss_lut 499 * @hw: pointer to the hardware structure 500 * @vsi_id: vsi fw index 501 * @pf_lut: for PF table set true, for VSI table set false 502 * @lut: pointer to the lut buffer provided by the caller 503 * @lut_size: size of the lut buffer 504 * 505 * set the RSS lookup table, PF or VSI type 506 **/ 507 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 508 bool pf_lut, u8 *lut, u16 lut_size) 509 { 510 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 511 } 512 513 /** 514 * i40e_aq_get_set_rss_key 515 * @hw: pointer to the hw struct 516 * @vsi_id: vsi fw index 517 * @key: pointer to key info struct 518 * @set: set true to set the key, false to get the key 519 * 520 * get the RSS key per VSI 521 **/ 522 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 523 u16 vsi_id, 524 struct i40e_aqc_get_set_rss_key_data *key, 525 bool set) 526 { 527 enum i40e_status_code status; 528 struct i40e_aq_desc desc; 529 struct i40e_aqc_get_set_rss_key *cmd_resp = 530 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 531 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 532 533 if (set) 534 i40e_fill_default_direct_cmd_desc(&desc, 535 i40e_aqc_opc_set_rss_key); 536 else 537 i40e_fill_default_direct_cmd_desc(&desc, 538 i40e_aqc_opc_get_rss_key); 539 540 /* Indirect command */ 541 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 542 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 543 544 cmd_resp->vsi_id = 545 CPU_TO_LE16((u16)((vsi_id << 546 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 547 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 548 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 549 550 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 551 552 return status; 553 } 554 555 /** 556 * i40e_aq_get_rss_key 557 * @hw: pointer to the hw struct 558 * @vsi_id: vsi fw index 559 * @key: pointer to key info struct 560 * 561 **/ 562 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 563 u16 vsi_id, 564 struct i40e_aqc_get_set_rss_key_data *key) 565 { 566 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 567 } 568 569 /** 570 * i40e_aq_set_rss_key 571 * @hw: pointer to the hw struct 572 * @vsi_id: vsi fw index 573 * @key: pointer to key info struct 574 * 575 * set the RSS key per VSI 576 **/ 577 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 578 u16 vsi_id, 579 struct i40e_aqc_get_set_rss_key_data *key) 580 { 581 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 582 } 583 584 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 585 * hardware to a bit-field that can be used by SW to more easily determine the 586 * packet type. 587 * 588 * Macros are used to shorten the table lines and make this table human 589 * readable. 590 * 591 * We store the PTYPE in the top byte of the bit field - this is just so that 592 * we can check that the table doesn't have a row missing, as the index into 593 * the table should be the PTYPE. 594 * 595 * Typical work flow: 596 * 597 * IF NOT i40e_ptype_lookup[ptype].known 598 * THEN 599 * Packet is unknown 600 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 601 * Use the rest of the fields to look at the tunnels, inner protocols, etc 602 * ELSE 603 * Use the enum i40e_rx_l2_ptype to decode the packet type 604 * ENDIF 605 */ 606 607 /* macro to make the table lines short */ 608 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 609 { PTYPE, \ 610 1, \ 611 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 612 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 613 I40E_RX_PTYPE_##OUTER_FRAG, \ 614 I40E_RX_PTYPE_TUNNEL_##T, \ 615 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 616 I40E_RX_PTYPE_##TEF, \ 617 I40E_RX_PTYPE_INNER_PROT_##I, \ 618 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 619 620 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 621 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 622 623 /* shorter macros makes the table fit but are terse */ 624 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 625 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 626 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 627 628 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 629 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 630 /* L2 Packet types */ 631 I40E_PTT_UNUSED_ENTRY(0), 632 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 633 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 634 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 635 I40E_PTT_UNUSED_ENTRY(4), 636 I40E_PTT_UNUSED_ENTRY(5), 637 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 638 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 639 I40E_PTT_UNUSED_ENTRY(8), 640 I40E_PTT_UNUSED_ENTRY(9), 641 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 642 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 643 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 644 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 645 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 646 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 647 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 648 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 649 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 650 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 651 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 652 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 653 654 /* Non Tunneled IPv4 */ 655 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 656 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 657 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 658 I40E_PTT_UNUSED_ENTRY(25), 659 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 660 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 661 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 662 663 /* IPv4 --> IPv4 */ 664 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 665 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 666 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 667 I40E_PTT_UNUSED_ENTRY(32), 668 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 669 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 670 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 671 672 /* IPv4 --> IPv6 */ 673 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 674 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 675 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 676 I40E_PTT_UNUSED_ENTRY(39), 677 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 678 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 679 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 680 681 /* IPv4 --> GRE/NAT */ 682 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 683 684 /* IPv4 --> GRE/NAT --> IPv4 */ 685 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 686 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 687 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 688 I40E_PTT_UNUSED_ENTRY(47), 689 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 690 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 691 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 692 693 /* IPv4 --> GRE/NAT --> IPv6 */ 694 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 695 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 696 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 697 I40E_PTT_UNUSED_ENTRY(54), 698 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 699 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 700 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 701 702 /* IPv4 --> GRE/NAT --> MAC */ 703 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 704 705 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 706 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 707 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 708 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 709 I40E_PTT_UNUSED_ENTRY(62), 710 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 711 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 712 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 713 714 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 715 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 716 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 717 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 718 I40E_PTT_UNUSED_ENTRY(69), 719 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 720 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 721 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 722 723 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 724 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 725 726 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 727 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 728 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 729 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 730 I40E_PTT_UNUSED_ENTRY(77), 731 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 732 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 733 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 734 735 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 736 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 737 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 738 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 739 I40E_PTT_UNUSED_ENTRY(84), 740 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 741 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 742 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 743 744 /* Non Tunneled IPv6 */ 745 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 746 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 747 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 748 I40E_PTT_UNUSED_ENTRY(91), 749 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 750 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 751 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 752 753 /* IPv6 --> IPv4 */ 754 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 755 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 756 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 757 I40E_PTT_UNUSED_ENTRY(98), 758 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 759 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 760 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 761 762 /* IPv6 --> IPv6 */ 763 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 764 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 765 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 766 I40E_PTT_UNUSED_ENTRY(105), 767 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 768 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 769 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 770 771 /* IPv6 --> GRE/NAT */ 772 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 773 774 /* IPv6 --> GRE/NAT -> IPv4 */ 775 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 776 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 777 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 778 I40E_PTT_UNUSED_ENTRY(113), 779 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 780 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 781 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 782 783 /* IPv6 --> GRE/NAT -> IPv6 */ 784 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 785 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 786 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 787 I40E_PTT_UNUSED_ENTRY(120), 788 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 789 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 790 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 791 792 /* IPv6 --> GRE/NAT -> MAC */ 793 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 794 795 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 796 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 797 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 798 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 799 I40E_PTT_UNUSED_ENTRY(128), 800 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 801 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 802 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 803 804 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 805 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 806 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 807 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 808 I40E_PTT_UNUSED_ENTRY(135), 809 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 810 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 811 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 812 813 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 814 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 815 816 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 817 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 818 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 819 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 820 I40E_PTT_UNUSED_ENTRY(143), 821 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 822 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 823 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 824 825 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 826 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 827 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 828 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 829 I40E_PTT_UNUSED_ENTRY(150), 830 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 831 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 832 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 833 834 /* unused entries */ 835 I40E_PTT_UNUSED_ENTRY(154), 836 I40E_PTT_UNUSED_ENTRY(155), 837 I40E_PTT_UNUSED_ENTRY(156), 838 I40E_PTT_UNUSED_ENTRY(157), 839 I40E_PTT_UNUSED_ENTRY(158), 840 I40E_PTT_UNUSED_ENTRY(159), 841 842 I40E_PTT_UNUSED_ENTRY(160), 843 I40E_PTT_UNUSED_ENTRY(161), 844 I40E_PTT_UNUSED_ENTRY(162), 845 I40E_PTT_UNUSED_ENTRY(163), 846 I40E_PTT_UNUSED_ENTRY(164), 847 I40E_PTT_UNUSED_ENTRY(165), 848 I40E_PTT_UNUSED_ENTRY(166), 849 I40E_PTT_UNUSED_ENTRY(167), 850 I40E_PTT_UNUSED_ENTRY(168), 851 I40E_PTT_UNUSED_ENTRY(169), 852 853 I40E_PTT_UNUSED_ENTRY(170), 854 I40E_PTT_UNUSED_ENTRY(171), 855 I40E_PTT_UNUSED_ENTRY(172), 856 I40E_PTT_UNUSED_ENTRY(173), 857 I40E_PTT_UNUSED_ENTRY(174), 858 I40E_PTT_UNUSED_ENTRY(175), 859 I40E_PTT_UNUSED_ENTRY(176), 860 I40E_PTT_UNUSED_ENTRY(177), 861 I40E_PTT_UNUSED_ENTRY(178), 862 I40E_PTT_UNUSED_ENTRY(179), 863 864 I40E_PTT_UNUSED_ENTRY(180), 865 I40E_PTT_UNUSED_ENTRY(181), 866 I40E_PTT_UNUSED_ENTRY(182), 867 I40E_PTT_UNUSED_ENTRY(183), 868 I40E_PTT_UNUSED_ENTRY(184), 869 I40E_PTT_UNUSED_ENTRY(185), 870 I40E_PTT_UNUSED_ENTRY(186), 871 I40E_PTT_UNUSED_ENTRY(187), 872 I40E_PTT_UNUSED_ENTRY(188), 873 I40E_PTT_UNUSED_ENTRY(189), 874 875 I40E_PTT_UNUSED_ENTRY(190), 876 I40E_PTT_UNUSED_ENTRY(191), 877 I40E_PTT_UNUSED_ENTRY(192), 878 I40E_PTT_UNUSED_ENTRY(193), 879 I40E_PTT_UNUSED_ENTRY(194), 880 I40E_PTT_UNUSED_ENTRY(195), 881 I40E_PTT_UNUSED_ENTRY(196), 882 I40E_PTT_UNUSED_ENTRY(197), 883 I40E_PTT_UNUSED_ENTRY(198), 884 I40E_PTT_UNUSED_ENTRY(199), 885 886 I40E_PTT_UNUSED_ENTRY(200), 887 I40E_PTT_UNUSED_ENTRY(201), 888 I40E_PTT_UNUSED_ENTRY(202), 889 I40E_PTT_UNUSED_ENTRY(203), 890 I40E_PTT_UNUSED_ENTRY(204), 891 I40E_PTT_UNUSED_ENTRY(205), 892 I40E_PTT_UNUSED_ENTRY(206), 893 I40E_PTT_UNUSED_ENTRY(207), 894 I40E_PTT_UNUSED_ENTRY(208), 895 I40E_PTT_UNUSED_ENTRY(209), 896 897 I40E_PTT_UNUSED_ENTRY(210), 898 I40E_PTT_UNUSED_ENTRY(211), 899 I40E_PTT_UNUSED_ENTRY(212), 900 I40E_PTT_UNUSED_ENTRY(213), 901 I40E_PTT_UNUSED_ENTRY(214), 902 I40E_PTT_UNUSED_ENTRY(215), 903 I40E_PTT_UNUSED_ENTRY(216), 904 I40E_PTT_UNUSED_ENTRY(217), 905 I40E_PTT_UNUSED_ENTRY(218), 906 I40E_PTT_UNUSED_ENTRY(219), 907 908 I40E_PTT_UNUSED_ENTRY(220), 909 I40E_PTT_UNUSED_ENTRY(221), 910 I40E_PTT_UNUSED_ENTRY(222), 911 I40E_PTT_UNUSED_ENTRY(223), 912 I40E_PTT_UNUSED_ENTRY(224), 913 I40E_PTT_UNUSED_ENTRY(225), 914 I40E_PTT_UNUSED_ENTRY(226), 915 I40E_PTT_UNUSED_ENTRY(227), 916 I40E_PTT_UNUSED_ENTRY(228), 917 I40E_PTT_UNUSED_ENTRY(229), 918 919 I40E_PTT_UNUSED_ENTRY(230), 920 I40E_PTT_UNUSED_ENTRY(231), 921 I40E_PTT_UNUSED_ENTRY(232), 922 I40E_PTT_UNUSED_ENTRY(233), 923 I40E_PTT_UNUSED_ENTRY(234), 924 I40E_PTT_UNUSED_ENTRY(235), 925 I40E_PTT_UNUSED_ENTRY(236), 926 I40E_PTT_UNUSED_ENTRY(237), 927 I40E_PTT_UNUSED_ENTRY(238), 928 I40E_PTT_UNUSED_ENTRY(239), 929 930 I40E_PTT_UNUSED_ENTRY(240), 931 I40E_PTT_UNUSED_ENTRY(241), 932 I40E_PTT_UNUSED_ENTRY(242), 933 I40E_PTT_UNUSED_ENTRY(243), 934 I40E_PTT_UNUSED_ENTRY(244), 935 I40E_PTT_UNUSED_ENTRY(245), 936 I40E_PTT_UNUSED_ENTRY(246), 937 I40E_PTT_UNUSED_ENTRY(247), 938 I40E_PTT_UNUSED_ENTRY(248), 939 I40E_PTT_UNUSED_ENTRY(249), 940 941 I40E_PTT_UNUSED_ENTRY(250), 942 I40E_PTT_UNUSED_ENTRY(251), 943 I40E_PTT_UNUSED_ENTRY(252), 944 I40E_PTT_UNUSED_ENTRY(253), 945 I40E_PTT_UNUSED_ENTRY(254), 946 I40E_PTT_UNUSED_ENTRY(255) 947 }; 948 949 950 /** 951 * i40e_validate_mac_addr - Validate unicast MAC address 952 * @mac_addr: pointer to MAC address 953 * 954 * Tests a MAC address to ensure it is a valid Individual Address 955 **/ 956 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 957 { 958 enum i40e_status_code status = I40E_SUCCESS; 959 960 DEBUGFUNC("i40e_validate_mac_addr"); 961 962 /* Broadcast addresses ARE multicast addresses 963 * Make sure it is not a multicast address 964 * Reject the zero address 965 */ 966 if (I40E_IS_MULTICAST(mac_addr) || 967 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 968 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 969 status = I40E_ERR_INVALID_MAC_ADDR; 970 971 return status; 972 } 973 #ifdef PF_DRIVER 974 975 /** 976 * i40e_init_shared_code - Initialize the shared code 977 * @hw: pointer to hardware structure 978 * 979 * This assigns the MAC type and PHY code and inits the NVM. 980 * Does not touch the hardware. This function must be called prior to any 981 * other function in the shared code. The i40e_hw structure should be 982 * memset to 0 prior to calling this function. The following fields in 983 * hw structure should be filled in prior to calling this function: 984 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 985 * subsystem_vendor_id, and revision_id 986 **/ 987 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 988 { 989 enum i40e_status_code status = I40E_SUCCESS; 990 u32 port, ari, func_rid; 991 992 DEBUGFUNC("i40e_init_shared_code"); 993 994 i40e_set_mac_type(hw); 995 996 switch (hw->mac.type) { 997 case I40E_MAC_XL710: 998 case I40E_MAC_X722: 999 break; 1000 default: 1001 return I40E_ERR_DEVICE_NOT_SUPPORTED; 1002 } 1003 1004 hw->phy.get_link_info = true; 1005 1006 /* Determine port number and PF number*/ 1007 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 1008 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1009 hw->port = (u8)port; 1010 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 1011 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1012 func_rid = rd32(hw, I40E_PF_FUNC_RID); 1013 if (ari) 1014 hw->pf_id = (u8)(func_rid & 0xff); 1015 else 1016 hw->pf_id = (u8)(func_rid & 0x7); 1017 1018 if (hw->mac.type == I40E_MAC_X722) 1019 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 1020 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 1021 /* NVMUpdate features structure initialization */ 1022 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR; 1023 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR; 1024 hw->nvmupd_features.size = sizeof(hw->nvmupd_features); 1025 i40e_memset(hw->nvmupd_features.features, 0x0, 1026 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN * 1027 sizeof(*hw->nvmupd_features.features), 1028 I40E_NONDMA_MEM); 1029 1030 /* No features supported at the moment */ 1031 hw->nvmupd_features.features[0] = 0; 1032 1033 status = i40e_init_nvm(hw); 1034 return status; 1035 } 1036 1037 /** 1038 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1039 * @hw: pointer to the hw struct 1040 * @flags: a return indicator of what addresses were added to the addr store 1041 * @addrs: the requestor's mac addr store 1042 * @cmd_details: pointer to command details structure or NULL 1043 **/ 1044 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1045 u16 *flags, 1046 struct i40e_aqc_mac_address_read_data *addrs, 1047 struct i40e_asq_cmd_details *cmd_details) 1048 { 1049 struct i40e_aq_desc desc; 1050 struct i40e_aqc_mac_address_read *cmd_data = 1051 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1052 enum i40e_status_code status; 1053 1054 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1055 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1056 1057 status = i40e_asq_send_command(hw, &desc, addrs, 1058 sizeof(*addrs), cmd_details); 1059 *flags = LE16_TO_CPU(cmd_data->command_flags); 1060 1061 return status; 1062 } 1063 1064 /** 1065 * i40e_aq_mac_address_write - Change the MAC addresses 1066 * @hw: pointer to the hw struct 1067 * @flags: indicates which MAC to be written 1068 * @mac_addr: address to write 1069 * @cmd_details: pointer to command details structure or NULL 1070 **/ 1071 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1072 u16 flags, u8 *mac_addr, 1073 struct i40e_asq_cmd_details *cmd_details) 1074 { 1075 struct i40e_aq_desc desc; 1076 struct i40e_aqc_mac_address_write *cmd_data = 1077 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1078 enum i40e_status_code status; 1079 1080 i40e_fill_default_direct_cmd_desc(&desc, 1081 i40e_aqc_opc_mac_address_write); 1082 cmd_data->command_flags = CPU_TO_LE16(flags); 1083 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1084 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1085 ((u32)mac_addr[3] << 16) | 1086 ((u32)mac_addr[4] << 8) | 1087 mac_addr[5]); 1088 1089 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1090 1091 return status; 1092 } 1093 1094 /** 1095 * i40e_get_mac_addr - get MAC address 1096 * @hw: pointer to the HW structure 1097 * @mac_addr: pointer to MAC address 1098 * 1099 * Reads the adapter's MAC address from register 1100 **/ 1101 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1102 { 1103 struct i40e_aqc_mac_address_read_data addrs; 1104 enum i40e_status_code status; 1105 u16 flags = 0; 1106 1107 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1108 1109 if (flags & I40E_AQC_LAN_ADDR_VALID) 1110 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1111 I40E_NONDMA_TO_NONDMA); 1112 1113 return status; 1114 } 1115 1116 /** 1117 * i40e_get_port_mac_addr - get Port MAC address 1118 * @hw: pointer to the HW structure 1119 * @mac_addr: pointer to Port MAC address 1120 * 1121 * Reads the adapter's Port MAC address 1122 **/ 1123 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1124 { 1125 struct i40e_aqc_mac_address_read_data addrs; 1126 enum i40e_status_code status; 1127 u16 flags = 0; 1128 1129 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1130 if (status) 1131 return status; 1132 1133 if (flags & I40E_AQC_PORT_ADDR_VALID) 1134 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1135 I40E_NONDMA_TO_NONDMA); 1136 else 1137 status = I40E_ERR_INVALID_MAC_ADDR; 1138 1139 return status; 1140 } 1141 1142 /** 1143 * i40e_pre_tx_queue_cfg - pre tx queue configure 1144 * @hw: pointer to the HW structure 1145 * @queue: target pf queue index 1146 * @enable: state change request 1147 * 1148 * Handles hw requirement to indicate intention to enable 1149 * or disable target queue. 1150 **/ 1151 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1152 { 1153 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1154 u32 reg_block = 0; 1155 u32 reg_val; 1156 1157 if (abs_queue_idx >= 128) { 1158 reg_block = abs_queue_idx / 128; 1159 abs_queue_idx %= 128; 1160 } 1161 1162 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1163 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1164 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1165 1166 if (enable) 1167 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1168 else 1169 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1170 1171 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1172 } 1173 1174 /** 1175 * i40e_get_san_mac_addr - get SAN MAC address 1176 * @hw: pointer to the HW structure 1177 * @mac_addr: pointer to SAN MAC address 1178 * 1179 * Reads the adapter's SAN MAC address from NVM 1180 **/ 1181 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw, 1182 u8 *mac_addr) 1183 { 1184 struct i40e_aqc_mac_address_read_data addrs; 1185 enum i40e_status_code status; 1186 u16 flags = 0; 1187 1188 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1189 if (status) 1190 return status; 1191 1192 if (flags & I40E_AQC_SAN_ADDR_VALID) 1193 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac), 1194 I40E_NONDMA_TO_NONDMA); 1195 else 1196 status = I40E_ERR_INVALID_MAC_ADDR; 1197 1198 return status; 1199 } 1200 1201 /** 1202 * i40e_read_pba_string - Reads part number string from EEPROM 1203 * @hw: pointer to hardware structure 1204 * @pba_num: stores the part number string from the EEPROM 1205 * @pba_num_size: part number string buffer length 1206 * 1207 * Reads the part number string from the EEPROM. 1208 **/ 1209 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1210 u32 pba_num_size) 1211 { 1212 enum i40e_status_code status = I40E_SUCCESS; 1213 u16 pba_word = 0; 1214 u16 pba_size = 0; 1215 u16 pba_ptr = 0; 1216 u16 i = 0; 1217 1218 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1219 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1220 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1221 return status; 1222 } 1223 1224 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1225 if (status != I40E_SUCCESS) { 1226 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1227 return status; 1228 } 1229 1230 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1231 if (status != I40E_SUCCESS) { 1232 DEBUGOUT("Failed to read PBA Block size.\n"); 1233 return status; 1234 } 1235 1236 /* Subtract one to get PBA word count (PBA Size word is included in 1237 * total size) 1238 */ 1239 pba_size--; 1240 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1241 DEBUGOUT("Buffer to small for PBA data.\n"); 1242 return I40E_ERR_PARAM; 1243 } 1244 1245 for (i = 0; i < pba_size; i++) { 1246 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1247 if (status != I40E_SUCCESS) { 1248 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1249 return status; 1250 } 1251 1252 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1253 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1254 } 1255 pba_num[(pba_size * 2)] = '\0'; 1256 1257 return status; 1258 } 1259 1260 /** 1261 * i40e_get_media_type - Gets media type 1262 * @hw: pointer to the hardware structure 1263 **/ 1264 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1265 { 1266 enum i40e_media_type media; 1267 1268 switch (hw->phy.link_info.phy_type) { 1269 case I40E_PHY_TYPE_10GBASE_SR: 1270 case I40E_PHY_TYPE_10GBASE_LR: 1271 case I40E_PHY_TYPE_1000BASE_SX: 1272 case I40E_PHY_TYPE_1000BASE_LX: 1273 case I40E_PHY_TYPE_40GBASE_SR4: 1274 case I40E_PHY_TYPE_40GBASE_LR4: 1275 case I40E_PHY_TYPE_25GBASE_LR: 1276 case I40E_PHY_TYPE_25GBASE_SR: 1277 media = I40E_MEDIA_TYPE_FIBER; 1278 break; 1279 case I40E_PHY_TYPE_100BASE_TX: 1280 case I40E_PHY_TYPE_1000BASE_T: 1281 case I40E_PHY_TYPE_2_5GBASE_T: 1282 case I40E_PHY_TYPE_5GBASE_T: 1283 case I40E_PHY_TYPE_10GBASE_T: 1284 media = I40E_MEDIA_TYPE_BASET; 1285 break; 1286 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1287 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1288 case I40E_PHY_TYPE_10GBASE_CR1: 1289 case I40E_PHY_TYPE_40GBASE_CR4: 1290 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1291 case I40E_PHY_TYPE_40GBASE_AOC: 1292 case I40E_PHY_TYPE_10GBASE_AOC: 1293 case I40E_PHY_TYPE_25GBASE_CR: 1294 case I40E_PHY_TYPE_25GBASE_AOC: 1295 case I40E_PHY_TYPE_25GBASE_ACC: 1296 media = I40E_MEDIA_TYPE_DA; 1297 break; 1298 case I40E_PHY_TYPE_1000BASE_KX: 1299 case I40E_PHY_TYPE_10GBASE_KX4: 1300 case I40E_PHY_TYPE_10GBASE_KR: 1301 case I40E_PHY_TYPE_40GBASE_KR4: 1302 case I40E_PHY_TYPE_20GBASE_KR2: 1303 case I40E_PHY_TYPE_25GBASE_KR: 1304 media = I40E_MEDIA_TYPE_BACKPLANE; 1305 break; 1306 case I40E_PHY_TYPE_SGMII: 1307 case I40E_PHY_TYPE_XAUI: 1308 case I40E_PHY_TYPE_XFI: 1309 case I40E_PHY_TYPE_XLAUI: 1310 case I40E_PHY_TYPE_XLPPI: 1311 default: 1312 media = I40E_MEDIA_TYPE_UNKNOWN; 1313 break; 1314 } 1315 1316 return media; 1317 } 1318 1319 /** 1320 * i40e_poll_globr - Poll for Global Reset completion 1321 * @hw: pointer to the hardware structure 1322 * @retry_limit: how many times to retry before failure 1323 **/ 1324 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw, 1325 u32 retry_limit) 1326 { 1327 u32 cnt, reg = 0; 1328 1329 for (cnt = 0; cnt < retry_limit; cnt++) { 1330 reg = rd32(hw, I40E_GLGEN_RSTAT); 1331 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1332 return I40E_SUCCESS; 1333 i40e_msec_delay(100); 1334 } 1335 1336 DEBUGOUT("Global reset failed.\n"); 1337 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg); 1338 1339 return I40E_ERR_RESET_FAILED; 1340 } 1341 1342 #define I40E_PF_RESET_WAIT_COUNT 200 1343 /** 1344 * i40e_pf_reset - Reset the PF 1345 * @hw: pointer to the hardware structure 1346 * 1347 * Assuming someone else has triggered a global reset, 1348 * assure the global reset is complete and then reset the PF 1349 **/ 1350 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1351 { 1352 u32 cnt = 0; 1353 u32 cnt1 = 0; 1354 u32 reg = 0; 1355 u32 grst_del; 1356 1357 /* Poll for Global Reset steady state in case of recent GRST. 1358 * The grst delay value is in 100ms units, and we'll wait a 1359 * couple counts longer to be sure we don't just miss the end. 1360 */ 1361 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1362 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1363 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1364 1365 grst_del = min(grst_del * 20, 160U); 1366 1367 for (cnt = 0; cnt < grst_del; cnt++) { 1368 reg = rd32(hw, I40E_GLGEN_RSTAT); 1369 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1370 break; 1371 i40e_msec_delay(100); 1372 } 1373 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1374 DEBUGOUT("Global reset polling failed to complete.\n"); 1375 return I40E_ERR_RESET_FAILED; 1376 } 1377 1378 /* Now Wait for the FW to be ready */ 1379 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1380 reg = rd32(hw, I40E_GLNVM_ULD); 1381 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1382 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1383 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1384 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1385 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1386 break; 1387 } 1388 i40e_msec_delay(10); 1389 } 1390 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1391 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1392 DEBUGOUT("wait for FW Reset complete timedout\n"); 1393 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1394 return I40E_ERR_RESET_FAILED; 1395 } 1396 1397 /* If there was a Global Reset in progress when we got here, 1398 * we don't need to do the PF Reset 1399 */ 1400 if (!cnt) { 1401 u32 reg2 = 0; 1402 1403 reg = rd32(hw, I40E_PFGEN_CTRL); 1404 wr32(hw, I40E_PFGEN_CTRL, 1405 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1406 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1407 reg = rd32(hw, I40E_PFGEN_CTRL); 1408 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1409 break; 1410 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1411 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 1412 break; 1413 i40e_msec_delay(1); 1414 } 1415 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1416 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS) 1417 return I40E_ERR_RESET_FAILED; 1418 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1419 DEBUGOUT("PF reset polling failed to complete.\n"); 1420 return I40E_ERR_RESET_FAILED; 1421 } 1422 } 1423 1424 i40e_clear_pxe_mode(hw); 1425 1426 1427 return I40E_SUCCESS; 1428 } 1429 1430 /** 1431 * i40e_clear_hw - clear out any left over hw state 1432 * @hw: pointer to the hw struct 1433 * 1434 * Clear queues and interrupts, typically called at init time, 1435 * but after the capabilities have been found so we know how many 1436 * queues and msix vectors have been allocated. 1437 **/ 1438 void i40e_clear_hw(struct i40e_hw *hw) 1439 { 1440 u32 num_queues, base_queue; 1441 u32 num_pf_int; 1442 u32 num_vf_int; 1443 u32 num_vfs; 1444 u32 i, j; 1445 u32 val; 1446 u32 eol = 0x7ff; 1447 1448 /* get number of interrupts, queues, and vfs */ 1449 val = rd32(hw, I40E_GLPCI_CNF2); 1450 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1451 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1452 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1453 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1454 1455 val = rd32(hw, I40E_PFLAN_QALLOC); 1456 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1457 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1458 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1459 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1460 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1461 num_queues = (j - base_queue) + 1; 1462 else 1463 num_queues = 0; 1464 1465 val = rd32(hw, I40E_PF_VT_PFALLOC); 1466 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1467 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1468 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1469 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1470 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1471 num_vfs = (j - i) + 1; 1472 else 1473 num_vfs = 0; 1474 1475 /* stop all the interrupts */ 1476 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1477 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1478 for (i = 0; i < num_pf_int - 2; i++) 1479 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1480 1481 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1482 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1483 wr32(hw, I40E_PFINT_LNKLST0, val); 1484 for (i = 0; i < num_pf_int - 2; i++) 1485 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1486 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1487 for (i = 0; i < num_vfs; i++) 1488 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1489 for (i = 0; i < num_vf_int - 2; i++) 1490 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1491 1492 /* warn the HW of the coming Tx disables */ 1493 for (i = 0; i < num_queues; i++) { 1494 u32 abs_queue_idx = base_queue + i; 1495 u32 reg_block = 0; 1496 1497 if (abs_queue_idx >= 128) { 1498 reg_block = abs_queue_idx / 128; 1499 abs_queue_idx %= 128; 1500 } 1501 1502 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1503 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1504 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1505 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1506 1507 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1508 } 1509 i40e_usec_delay(400); 1510 1511 /* stop all the queues */ 1512 for (i = 0; i < num_queues; i++) { 1513 wr32(hw, I40E_QINT_TQCTL(i), 0); 1514 wr32(hw, I40E_QTX_ENA(i), 0); 1515 wr32(hw, I40E_QINT_RQCTL(i), 0); 1516 wr32(hw, I40E_QRX_ENA(i), 0); 1517 } 1518 1519 /* short wait for all queue disables to settle */ 1520 i40e_usec_delay(50); 1521 } 1522 1523 /** 1524 * i40e_clear_pxe_mode - clear pxe operations mode 1525 * @hw: pointer to the hw struct 1526 * 1527 * Make sure all PXE mode settings are cleared, including things 1528 * like descriptor fetch/write-back mode. 1529 **/ 1530 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1531 { 1532 if (i40e_check_asq_alive(hw)) 1533 i40e_aq_clear_pxe_mode(hw, NULL); 1534 } 1535 1536 /** 1537 * i40e_led_is_mine - helper to find matching led 1538 * @hw: pointer to the hw struct 1539 * @idx: index into GPIO registers 1540 * 1541 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1542 */ 1543 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1544 { 1545 u32 gpio_val = 0; 1546 u32 port; 1547 1548 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 1549 !hw->func_caps.led[idx]) 1550 return 0; 1551 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1552 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1553 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1554 1555 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1556 * if it is not our port then ignore 1557 */ 1558 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1559 (port != hw->port)) 1560 return 0; 1561 1562 return gpio_val; 1563 } 1564 1565 #define I40E_COMBINED_ACTIVITY 0xA 1566 #define I40E_FILTER_ACTIVITY 0xE 1567 #define I40E_LINK_ACTIVITY 0xC 1568 #define I40E_MAC_ACTIVITY 0xD 1569 #define I40E_FW_LED BIT(4) 1570 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 1571 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 1572 1573 #define I40E_LED0 22 1574 1575 #define I40E_PIN_FUNC_SDP 0x0 1576 #define I40E_PIN_FUNC_LED 0x1 1577 1578 /** 1579 * i40e_led_get - return current on/off mode 1580 * @hw: pointer to the hw struct 1581 * 1582 * The value returned is the 'mode' field as defined in the 1583 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1584 * values are variations of possible behaviors relating to 1585 * blink, link, and wire. 1586 **/ 1587 u32 i40e_led_get(struct i40e_hw *hw) 1588 { 1589 u32 current_mode = 0; 1590 u32 mode = 0; 1591 int i; 1592 1593 /* as per the documentation GPIO 22-29 are the LED 1594 * GPIO pins named LED0..LED7 1595 */ 1596 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1597 u32 gpio_val = i40e_led_is_mine(hw, i); 1598 1599 if (!gpio_val) 1600 continue; 1601 1602 /* ignore gpio LED src mode entries related to the activity 1603 * LEDs 1604 */ 1605 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1606 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1607 switch (current_mode) { 1608 case I40E_COMBINED_ACTIVITY: 1609 case I40E_FILTER_ACTIVITY: 1610 case I40E_MAC_ACTIVITY: 1611 case I40E_LINK_ACTIVITY: 1612 continue; 1613 default: 1614 break; 1615 } 1616 1617 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1618 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1619 break; 1620 } 1621 1622 return mode; 1623 } 1624 1625 /** 1626 * i40e_led_set - set new on/off mode 1627 * @hw: pointer to the hw struct 1628 * @mode: 0=off, 0xf=on (else see manual for mode details) 1629 * @blink: true if the LED should blink when on, false if steady 1630 * 1631 * if this function is used to turn on the blink it should 1632 * be used to disable the blink when restoring the original state. 1633 **/ 1634 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1635 { 1636 u32 current_mode = 0; 1637 int i; 1638 1639 if (mode & ~I40E_LED_MODE_VALID) { 1640 DEBUGOUT1("invalid mode passed in %X\n", mode); 1641 return; 1642 } 1643 1644 /* as per the documentation GPIO 22-29 are the LED 1645 * GPIO pins named LED0..LED7 1646 */ 1647 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1648 u32 gpio_val = i40e_led_is_mine(hw, i); 1649 1650 if (!gpio_val) 1651 continue; 1652 1653 /* ignore gpio LED src mode entries related to the activity 1654 * LEDs 1655 */ 1656 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1657 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1658 switch (current_mode) { 1659 case I40E_COMBINED_ACTIVITY: 1660 case I40E_FILTER_ACTIVITY: 1661 case I40E_MAC_ACTIVITY: 1662 case I40E_LINK_ACTIVITY: 1663 continue; 1664 default: 1665 break; 1666 } 1667 1668 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 1669 u32 pin_func = 0; 1670 1671 if (mode & I40E_FW_LED) 1672 pin_func = I40E_PIN_FUNC_SDP; 1673 else 1674 pin_func = I40E_PIN_FUNC_LED; 1675 1676 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 1677 gpio_val |= ((pin_func << 1678 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) & 1679 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK); 1680 } 1681 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1682 /* this & is a bit of paranoia, but serves as a range check */ 1683 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1684 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1685 1686 if (blink) 1687 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1688 else 1689 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1690 1691 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1692 break; 1693 } 1694 } 1695 1696 /* Admin command wrappers */ 1697 1698 /** 1699 * i40e_aq_get_phy_capabilities 1700 * @hw: pointer to the hw struct 1701 * @abilities: structure for PHY capabilities to be filled 1702 * @qualified_modules: report Qualified Modules 1703 * @report_init: report init capabilities (active are default) 1704 * @cmd_details: pointer to command details structure or NULL 1705 * 1706 * Returns the various PHY abilities supported on the Port. 1707 **/ 1708 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1709 bool qualified_modules, bool report_init, 1710 struct i40e_aq_get_phy_abilities_resp *abilities, 1711 struct i40e_asq_cmd_details *cmd_details) 1712 { 1713 struct i40e_aq_desc desc; 1714 enum i40e_status_code status; 1715 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1716 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1717 1718 if (!abilities) 1719 return I40E_ERR_PARAM; 1720 1721 do { 1722 i40e_fill_default_direct_cmd_desc(&desc, 1723 i40e_aqc_opc_get_phy_abilities); 1724 1725 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1726 if (abilities_size > I40E_AQ_LARGE_BUF) 1727 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1728 1729 if (qualified_modules) 1730 desc.params.external.param0 |= 1731 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1732 1733 if (report_init) 1734 desc.params.external.param0 |= 1735 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1736 1737 status = i40e_asq_send_command(hw, &desc, abilities, 1738 abilities_size, cmd_details); 1739 1740 switch (hw->aq.asq_last_status) { 1741 case I40E_AQ_RC_EIO: 1742 status = I40E_ERR_UNKNOWN_PHY; 1743 break; 1744 case I40E_AQ_RC_EAGAIN: 1745 i40e_msec_delay(1); 1746 total_delay++; 1747 status = I40E_ERR_TIMEOUT; 1748 break; 1749 /* also covers I40E_AQ_RC_OK */ 1750 default: 1751 break; 1752 } 1753 1754 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && 1755 (total_delay < max_delay)); 1756 1757 if (status != I40E_SUCCESS) 1758 return status; 1759 1760 if (report_init) { 1761 if (hw->mac.type == I40E_MAC_XL710 && 1762 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1763 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1764 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1765 } else { 1766 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1767 hw->phy.phy_types |= 1768 ((u64)abilities->phy_type_ext << 32); 1769 } 1770 } 1771 1772 return status; 1773 } 1774 1775 /** 1776 * i40e_aq_set_phy_config 1777 * @hw: pointer to the hw struct 1778 * @config: structure with PHY configuration to be set 1779 * @cmd_details: pointer to command details structure or NULL 1780 * 1781 * Set the various PHY configuration parameters 1782 * supported on the Port.One or more of the Set PHY config parameters may be 1783 * ignored in an MFP mode as the PF may not have the privilege to set some 1784 * of the PHY Config parameters. This status will be indicated by the 1785 * command response. 1786 **/ 1787 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1788 struct i40e_aq_set_phy_config *config, 1789 struct i40e_asq_cmd_details *cmd_details) 1790 { 1791 struct i40e_aq_desc desc; 1792 struct i40e_aq_set_phy_config *cmd = 1793 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1794 enum i40e_status_code status; 1795 1796 if (!config) 1797 return I40E_ERR_PARAM; 1798 1799 i40e_fill_default_direct_cmd_desc(&desc, 1800 i40e_aqc_opc_set_phy_config); 1801 1802 *cmd = *config; 1803 1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1805 1806 return status; 1807 } 1808 1809 /** 1810 * i40e_set_fc 1811 * @hw: pointer to the hw struct 1812 * @aq_failures: buffer to return AdminQ failure information 1813 * @atomic_restart: whether to enable atomic link restart 1814 * 1815 * Set the requested flow control mode using set_phy_config. 1816 **/ 1817 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1818 bool atomic_restart) 1819 { 1820 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1821 struct i40e_aq_get_phy_abilities_resp abilities; 1822 struct i40e_aq_set_phy_config config; 1823 enum i40e_status_code status; 1824 u8 pause_mask = 0x0; 1825 1826 *aq_failures = 0x0; 1827 1828 switch (fc_mode) { 1829 case I40E_FC_FULL: 1830 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1831 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1832 break; 1833 case I40E_FC_RX_PAUSE: 1834 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1835 break; 1836 case I40E_FC_TX_PAUSE: 1837 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1838 break; 1839 default: 1840 break; 1841 } 1842 1843 /* Get the current phy config */ 1844 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1845 NULL); 1846 if (status) { 1847 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1848 return status; 1849 } 1850 1851 memset(&config, 0, sizeof(config)); 1852 /* clear the old pause settings */ 1853 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1854 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1855 /* set the new abilities */ 1856 config.abilities |= pause_mask; 1857 /* If the abilities have changed, then set the new config */ 1858 if (config.abilities != abilities.abilities) { 1859 /* Auto restart link so settings take effect */ 1860 if (atomic_restart) 1861 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1862 /* Copy over all the old settings */ 1863 config.phy_type = abilities.phy_type; 1864 config.phy_type_ext = abilities.phy_type_ext; 1865 config.link_speed = abilities.link_speed; 1866 config.eee_capability = abilities.eee_capability; 1867 config.eeer = abilities.eeer_val; 1868 config.low_power_ctrl = abilities.d3_lpan; 1869 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1870 I40E_AQ_PHY_FEC_CONFIG_MASK; 1871 status = i40e_aq_set_phy_config(hw, &config, NULL); 1872 1873 if (status) 1874 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1875 } 1876 /* Update the link info */ 1877 status = i40e_update_link_info(hw); 1878 if (status) { 1879 /* Wait a little bit (on 40G cards it sometimes takes a really 1880 * long time for link to come back from the atomic reset) 1881 * and try once more 1882 */ 1883 i40e_msec_delay(1000); 1884 status = i40e_update_link_info(hw); 1885 } 1886 if (status) 1887 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1888 1889 return status; 1890 } 1891 1892 /** 1893 * i40e_aq_set_mac_config 1894 * @hw: pointer to the hw struct 1895 * @max_frame_size: Maximum Frame Size to be supported by the port 1896 * @crc_en: Tell HW to append a CRC to outgoing frames 1897 * @pacing: Pacing configurations 1898 * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked 1899 * @cmd_details: pointer to command details structure or NULL 1900 * 1901 * Configure MAC settings for frame size, jumbo frame support and the 1902 * addition of a CRC by the hardware. 1903 **/ 1904 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1905 u16 max_frame_size, 1906 bool crc_en, u16 pacing, 1907 bool auto_drop_blocking_packets, 1908 struct i40e_asq_cmd_details *cmd_details) 1909 { 1910 struct i40e_aq_desc desc; 1911 struct i40e_aq_set_mac_config *cmd = 1912 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1913 enum i40e_status_code status; 1914 1915 if (max_frame_size == 0) 1916 return I40E_ERR_PARAM; 1917 1918 i40e_fill_default_direct_cmd_desc(&desc, 1919 i40e_aqc_opc_set_mac_config); 1920 1921 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1922 cmd->params = ((u8)pacing & 0x0F) << 3; 1923 if (crc_en) 1924 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1925 1926 if (auto_drop_blocking_packets) { 1927 if (hw->flags & I40E_HW_FLAG_DROP_MODE) 1928 cmd->params |= 1929 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN; 1930 else 1931 i40e_debug(hw, I40E_DEBUG_ALL, 1932 "This FW api version does not support drop mode.\n"); 1933 } 1934 1935 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF 1936 cmd->fc_refresh_threshold = 1937 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD); 1938 1939 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1940 1941 return status; 1942 } 1943 1944 /** 1945 * i40e_aq_clear_pxe_mode 1946 * @hw: pointer to the hw struct 1947 * @cmd_details: pointer to command details structure or NULL 1948 * 1949 * Tell the firmware that the driver is taking over from PXE 1950 **/ 1951 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1952 struct i40e_asq_cmd_details *cmd_details) 1953 { 1954 enum i40e_status_code status; 1955 struct i40e_aq_desc desc; 1956 struct i40e_aqc_clear_pxe *cmd = 1957 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1958 1959 i40e_fill_default_direct_cmd_desc(&desc, 1960 i40e_aqc_opc_clear_pxe_mode); 1961 1962 cmd->rx_cnt = 0x2; 1963 1964 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1965 1966 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1967 1968 return status; 1969 } 1970 1971 /** 1972 * i40e_aq_set_link_restart_an 1973 * @hw: pointer to the hw struct 1974 * @enable_link: if true: enable link, if false: disable link 1975 * @cmd_details: pointer to command details structure or NULL 1976 * 1977 * Sets up the link and restarts the Auto-Negotiation over the link. 1978 **/ 1979 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1980 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1981 { 1982 struct i40e_aq_desc desc; 1983 struct i40e_aqc_set_link_restart_an *cmd = 1984 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1985 enum i40e_status_code status; 1986 1987 i40e_fill_default_direct_cmd_desc(&desc, 1988 i40e_aqc_opc_set_link_restart_an); 1989 1990 cmd->command = I40E_AQ_PHY_RESTART_AN; 1991 if (enable_link) 1992 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1993 else 1994 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1995 1996 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1997 1998 return status; 1999 } 2000 2001 /** 2002 * i40e_aq_get_link_info 2003 * @hw: pointer to the hw struct 2004 * @enable_lse: enable/disable LinkStatusEvent reporting 2005 * @link: pointer to link status structure - optional 2006 * @cmd_details: pointer to command details structure or NULL 2007 * 2008 * Returns the link status of the adapter. 2009 **/ 2010 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 2011 bool enable_lse, struct i40e_link_status *link, 2012 struct i40e_asq_cmd_details *cmd_details) 2013 { 2014 struct i40e_aq_desc desc; 2015 struct i40e_aqc_get_link_status *resp = 2016 (struct i40e_aqc_get_link_status *)&desc.params.raw; 2017 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 2018 enum i40e_status_code status; 2019 bool tx_pause, rx_pause; 2020 u16 command_flags; 2021 2022 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 2023 2024 if (enable_lse) 2025 command_flags = I40E_AQ_LSE_ENABLE; 2026 else 2027 command_flags = I40E_AQ_LSE_DISABLE; 2028 resp->command_flags = CPU_TO_LE16(command_flags); 2029 2030 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2031 2032 if (status != I40E_SUCCESS) 2033 goto aq_get_link_info_exit; 2034 2035 /* save off old link status information */ 2036 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 2037 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 2038 2039 /* update link status */ 2040 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 2041 hw->phy.media_type = i40e_get_media_type(hw); 2042 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 2043 hw_link_info->link_info = resp->link_info; 2044 hw_link_info->an_info = resp->an_info; 2045 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 2046 I40E_AQ_CONFIG_FEC_RS_ENA); 2047 hw_link_info->ext_info = resp->ext_info; 2048 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 2049 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 2050 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 2051 2052 /* update fc info */ 2053 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 2054 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 2055 if (tx_pause & rx_pause) 2056 hw->fc.current_mode = I40E_FC_FULL; 2057 else if (tx_pause) 2058 hw->fc.current_mode = I40E_FC_TX_PAUSE; 2059 else if (rx_pause) 2060 hw->fc.current_mode = I40E_FC_RX_PAUSE; 2061 else 2062 hw->fc.current_mode = I40E_FC_NONE; 2063 2064 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 2065 hw_link_info->crc_enable = true; 2066 else 2067 hw_link_info->crc_enable = false; 2068 2069 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 2070 hw_link_info->lse_enable = true; 2071 else 2072 hw_link_info->lse_enable = false; 2073 2074 if ((hw->mac.type == I40E_MAC_XL710) && 2075 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 2076 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 2077 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 2078 2079 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE && 2080 hw->mac.type != I40E_MAC_X722) { 2081 __le32 tmp; 2082 2083 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), 2084 I40E_NONDMA_TO_NONDMA); 2085 hw->phy.phy_types = LE32_TO_CPU(tmp); 2086 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 2087 } 2088 2089 /* save link status information */ 2090 if (link) 2091 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 2092 I40E_NONDMA_TO_NONDMA); 2093 2094 /* flag cleared so helper functions don't call AQ again */ 2095 hw->phy.get_link_info = false; 2096 2097 aq_get_link_info_exit: 2098 return status; 2099 } 2100 2101 /** 2102 * i40e_aq_set_phy_int_mask 2103 * @hw: pointer to the hw struct 2104 * @mask: interrupt mask to be set 2105 * @cmd_details: pointer to command details structure or NULL 2106 * 2107 * Set link interrupt mask. 2108 **/ 2109 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 2110 u16 mask, 2111 struct i40e_asq_cmd_details *cmd_details) 2112 { 2113 struct i40e_aq_desc desc; 2114 struct i40e_aqc_set_phy_int_mask *cmd = 2115 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 2116 enum i40e_status_code status; 2117 2118 i40e_fill_default_direct_cmd_desc(&desc, 2119 i40e_aqc_opc_set_phy_int_mask); 2120 2121 cmd->event_mask = CPU_TO_LE16(mask); 2122 2123 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2124 2125 return status; 2126 } 2127 2128 /** 2129 * i40e_aq_get_local_advt_reg 2130 * @hw: pointer to the hw struct 2131 * @advt_reg: local AN advertisement register value 2132 * @cmd_details: pointer to command details structure or NULL 2133 * 2134 * Get the Local AN advertisement register value. 2135 **/ 2136 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 2137 u64 *advt_reg, 2138 struct i40e_asq_cmd_details *cmd_details) 2139 { 2140 struct i40e_aq_desc desc; 2141 struct i40e_aqc_an_advt_reg *resp = 2142 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2143 enum i40e_status_code status; 2144 2145 i40e_fill_default_direct_cmd_desc(&desc, 2146 i40e_aqc_opc_get_local_advt_reg); 2147 2148 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2149 2150 if (status != I40E_SUCCESS) 2151 goto aq_get_local_advt_reg_exit; 2152 2153 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2154 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2155 2156 aq_get_local_advt_reg_exit: 2157 return status; 2158 } 2159 2160 /** 2161 * i40e_aq_set_local_advt_reg 2162 * @hw: pointer to the hw struct 2163 * @advt_reg: local AN advertisement register value 2164 * @cmd_details: pointer to command details structure or NULL 2165 * 2166 * Get the Local AN advertisement register value. 2167 **/ 2168 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2169 u64 advt_reg, 2170 struct i40e_asq_cmd_details *cmd_details) 2171 { 2172 struct i40e_aq_desc desc; 2173 struct i40e_aqc_an_advt_reg *cmd = 2174 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2175 enum i40e_status_code status; 2176 2177 i40e_fill_default_direct_cmd_desc(&desc, 2178 i40e_aqc_opc_get_local_advt_reg); 2179 2180 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2181 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2182 2183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2184 2185 return status; 2186 } 2187 2188 /** 2189 * i40e_aq_get_partner_advt 2190 * @hw: pointer to the hw struct 2191 * @advt_reg: AN partner advertisement register value 2192 * @cmd_details: pointer to command details structure or NULL 2193 * 2194 * Get the link partner AN advertisement register value. 2195 **/ 2196 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2197 u64 *advt_reg, 2198 struct i40e_asq_cmd_details *cmd_details) 2199 { 2200 struct i40e_aq_desc desc; 2201 struct i40e_aqc_an_advt_reg *resp = 2202 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2203 enum i40e_status_code status; 2204 2205 i40e_fill_default_direct_cmd_desc(&desc, 2206 i40e_aqc_opc_get_partner_advt); 2207 2208 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2209 2210 if (status != I40E_SUCCESS) 2211 goto aq_get_partner_advt_exit; 2212 2213 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2214 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2215 2216 aq_get_partner_advt_exit: 2217 return status; 2218 } 2219 2220 /** 2221 * i40e_aq_set_lb_modes 2222 * @hw: pointer to the hw struct 2223 * @lb_modes: loopback mode to be set 2224 * @cmd_details: pointer to command details structure or NULL 2225 * 2226 * Sets loopback modes. 2227 **/ 2228 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 2229 u16 lb_modes, 2230 struct i40e_asq_cmd_details *cmd_details) 2231 { 2232 struct i40e_aq_desc desc; 2233 struct i40e_aqc_set_lb_mode *cmd = 2234 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2235 enum i40e_status_code status; 2236 2237 i40e_fill_default_direct_cmd_desc(&desc, 2238 i40e_aqc_opc_set_lb_modes); 2239 2240 cmd->lb_mode = CPU_TO_LE16(lb_modes); 2241 2242 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2243 2244 return status; 2245 } 2246 2247 /** 2248 * i40e_aq_set_phy_debug 2249 * @hw: pointer to the hw struct 2250 * @cmd_flags: debug command flags 2251 * @cmd_details: pointer to command details structure or NULL 2252 * 2253 * Reset the external PHY. 2254 **/ 2255 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2256 struct i40e_asq_cmd_details *cmd_details) 2257 { 2258 struct i40e_aq_desc desc; 2259 struct i40e_aqc_set_phy_debug *cmd = 2260 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2261 enum i40e_status_code status; 2262 2263 i40e_fill_default_direct_cmd_desc(&desc, 2264 i40e_aqc_opc_set_phy_debug); 2265 2266 cmd->command_flags = cmd_flags; 2267 2268 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2269 2270 return status; 2271 } 2272 2273 /** 2274 * i40e_hw_ver_ge 2275 * @hw: pointer to the hw struct 2276 * @maj: api major value 2277 * @min: api minor value 2278 * 2279 * Assert whether current HW api version is greater/equal than provided. 2280 **/ 2281 static bool i40e_hw_ver_ge(struct i40e_hw *hw, u16 maj, u16 min) 2282 { 2283 if (hw->aq.api_maj_ver > maj || 2284 (hw->aq.api_maj_ver == maj && hw->aq.api_min_ver >= min)) 2285 return true; 2286 return false; 2287 } 2288 2289 /** 2290 * i40e_aq_add_vsi 2291 * @hw: pointer to the hw struct 2292 * @vsi_ctx: pointer to a vsi context struct 2293 * @cmd_details: pointer to command details structure or NULL 2294 * 2295 * Add a VSI context to the hardware. 2296 **/ 2297 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2298 struct i40e_vsi_context *vsi_ctx, 2299 struct i40e_asq_cmd_details *cmd_details) 2300 { 2301 struct i40e_aq_desc desc; 2302 struct i40e_aqc_add_get_update_vsi *cmd = 2303 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2304 struct i40e_aqc_add_get_update_vsi_completion *resp = 2305 (struct i40e_aqc_add_get_update_vsi_completion *) 2306 &desc.params.raw; 2307 enum i40e_status_code status; 2308 2309 i40e_fill_default_direct_cmd_desc(&desc, 2310 i40e_aqc_opc_add_vsi); 2311 2312 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2313 cmd->connection_type = vsi_ctx->connection_type; 2314 cmd->vf_id = vsi_ctx->vf_num; 2315 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2316 2317 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2318 2319 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2320 sizeof(vsi_ctx->info), cmd_details); 2321 2322 if (status != I40E_SUCCESS) 2323 goto aq_add_vsi_exit; 2324 2325 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2326 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2327 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2328 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2329 2330 aq_add_vsi_exit: 2331 return status; 2332 } 2333 2334 /** 2335 * i40e_aq_set_default_vsi 2336 * @hw: pointer to the hw struct 2337 * @seid: vsi number 2338 * @cmd_details: pointer to command details structure or NULL 2339 **/ 2340 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2341 u16 seid, 2342 struct i40e_asq_cmd_details *cmd_details) 2343 { 2344 struct i40e_aq_desc desc; 2345 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2346 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2347 &desc.params.raw; 2348 enum i40e_status_code status; 2349 2350 i40e_fill_default_direct_cmd_desc(&desc, 2351 i40e_aqc_opc_set_vsi_promiscuous_modes); 2352 2353 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2354 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2355 cmd->seid = CPU_TO_LE16(seid); 2356 2357 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2358 2359 return status; 2360 } 2361 2362 /** 2363 * i40e_aq_clear_default_vsi 2364 * @hw: pointer to the hw struct 2365 * @seid: vsi number 2366 * @cmd_details: pointer to command details structure or NULL 2367 **/ 2368 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2369 u16 seid, 2370 struct i40e_asq_cmd_details *cmd_details) 2371 { 2372 struct i40e_aq_desc desc; 2373 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2374 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2375 &desc.params.raw; 2376 enum i40e_status_code status; 2377 2378 i40e_fill_default_direct_cmd_desc(&desc, 2379 i40e_aqc_opc_set_vsi_promiscuous_modes); 2380 2381 cmd->promiscuous_flags = CPU_TO_LE16(0); 2382 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2383 cmd->seid = CPU_TO_LE16(seid); 2384 2385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2386 2387 return status; 2388 } 2389 2390 /** 2391 * i40e_aq_set_vsi_unicast_promiscuous 2392 * @hw: pointer to the hw struct 2393 * @seid: vsi number 2394 * @set: set unicast promiscuous enable/disable 2395 * @cmd_details: pointer to command details structure or NULL 2396 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2397 **/ 2398 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2399 u16 seid, bool set, 2400 struct i40e_asq_cmd_details *cmd_details, 2401 bool rx_only_promisc) 2402 { 2403 struct i40e_aq_desc desc; 2404 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2405 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2406 enum i40e_status_code status; 2407 u16 flags = 0; 2408 2409 i40e_fill_default_direct_cmd_desc(&desc, 2410 i40e_aqc_opc_set_vsi_promiscuous_modes); 2411 2412 if (set) { 2413 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2414 if (rx_only_promisc && i40e_hw_ver_ge(hw, 1, 5)) 2415 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 2416 } 2417 2418 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2419 2420 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2421 if (i40e_hw_ver_ge(hw, 1, 5)) 2422 cmd->valid_flags |= 2423 CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 2424 2425 cmd->seid = CPU_TO_LE16(seid); 2426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2427 2428 return status; 2429 } 2430 2431 /** 2432 * i40e_aq_set_vsi_multicast_promiscuous 2433 * @hw: pointer to the hw struct 2434 * @seid: vsi number 2435 * @set: set multicast promiscuous enable/disable 2436 * @cmd_details: pointer to command details structure or NULL 2437 **/ 2438 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2439 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2440 { 2441 struct i40e_aq_desc desc; 2442 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2443 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2444 enum i40e_status_code status; 2445 u16 flags = 0; 2446 2447 i40e_fill_default_direct_cmd_desc(&desc, 2448 i40e_aqc_opc_set_vsi_promiscuous_modes); 2449 2450 if (set) 2451 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2452 2453 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2454 2455 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2456 2457 cmd->seid = CPU_TO_LE16(seid); 2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2459 2460 return status; 2461 } 2462 2463 /** 2464 * i40e_aq_set_vsi_full_promiscuous 2465 * @hw: pointer to the hw struct 2466 * @seid: VSI number 2467 * @set: set promiscuous enable/disable 2468 * @cmd_details: pointer to command details structure or NULL 2469 **/ 2470 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw, 2471 u16 seid, bool set, 2472 struct i40e_asq_cmd_details *cmd_details) 2473 { 2474 struct i40e_aq_desc desc; 2475 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2476 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2477 enum i40e_status_code status; 2478 u16 flags = 0; 2479 2480 i40e_fill_default_direct_cmd_desc(&desc, 2481 i40e_aqc_opc_set_vsi_promiscuous_modes); 2482 2483 if (set) 2484 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST | 2485 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2486 I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2487 2488 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2489 2490 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST | 2491 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2492 I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2493 2494 cmd->seid = CPU_TO_LE16(seid); 2495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2496 2497 return status; 2498 } 2499 2500 /** 2501 * i40e_aq_set_vsi_mc_promisc_on_vlan 2502 * @hw: pointer to the hw struct 2503 * @seid: vsi number 2504 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2505 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2506 * @cmd_details: pointer to command details structure or NULL 2507 **/ 2508 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2509 u16 seid, bool enable, u16 vid, 2510 struct i40e_asq_cmd_details *cmd_details) 2511 { 2512 struct i40e_aq_desc desc; 2513 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2514 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2515 enum i40e_status_code status; 2516 u16 flags = 0; 2517 2518 i40e_fill_default_direct_cmd_desc(&desc, 2519 i40e_aqc_opc_set_vsi_promiscuous_modes); 2520 2521 if (enable) 2522 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2523 2524 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2525 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2526 cmd->seid = CPU_TO_LE16(seid); 2527 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2528 2529 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2530 2531 return status; 2532 } 2533 2534 /** 2535 * i40e_aq_set_vsi_uc_promisc_on_vlan 2536 * @hw: pointer to the hw struct 2537 * @seid: vsi number 2538 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2539 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2540 * @cmd_details: pointer to command details structure or NULL 2541 **/ 2542 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2543 u16 seid, bool enable, u16 vid, 2544 struct i40e_asq_cmd_details *cmd_details) 2545 { 2546 struct i40e_aq_desc desc; 2547 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2548 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2549 enum i40e_status_code status; 2550 u16 flags = 0; 2551 2552 i40e_fill_default_direct_cmd_desc(&desc, 2553 i40e_aqc_opc_set_vsi_promiscuous_modes); 2554 2555 if (enable) { 2556 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2557 if (i40e_hw_ver_ge(hw, 1, 5)) 2558 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 2559 } 2560 2561 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2562 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2563 if (i40e_hw_ver_ge(hw, 1, 5)) 2564 cmd->valid_flags |= 2565 CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 2566 cmd->seid = CPU_TO_LE16(seid); 2567 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2568 2569 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2570 2571 return status; 2572 } 2573 2574 /** 2575 * i40e_aq_set_vsi_bc_promisc_on_vlan 2576 * @hw: pointer to the hw struct 2577 * @seid: vsi number 2578 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2579 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2580 * @cmd_details: pointer to command details structure or NULL 2581 **/ 2582 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2583 u16 seid, bool enable, u16 vid, 2584 struct i40e_asq_cmd_details *cmd_details) 2585 { 2586 struct i40e_aq_desc desc; 2587 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2588 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2589 enum i40e_status_code status; 2590 u16 flags = 0; 2591 2592 i40e_fill_default_direct_cmd_desc(&desc, 2593 i40e_aqc_opc_set_vsi_promiscuous_modes); 2594 2595 if (enable) 2596 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2597 2598 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2599 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2600 cmd->seid = CPU_TO_LE16(seid); 2601 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2602 2603 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2604 2605 return status; 2606 } 2607 2608 /** 2609 * i40e_aq_set_vsi_broadcast 2610 * @hw: pointer to the hw struct 2611 * @seid: vsi number 2612 * @set_filter: true to set filter, false to clear filter 2613 * @cmd_details: pointer to command details structure or NULL 2614 * 2615 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2616 **/ 2617 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2618 u16 seid, bool set_filter, 2619 struct i40e_asq_cmd_details *cmd_details) 2620 { 2621 struct i40e_aq_desc desc; 2622 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2623 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2624 enum i40e_status_code status; 2625 2626 i40e_fill_default_direct_cmd_desc(&desc, 2627 i40e_aqc_opc_set_vsi_promiscuous_modes); 2628 2629 if (set_filter) 2630 cmd->promiscuous_flags 2631 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2632 else 2633 cmd->promiscuous_flags 2634 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2635 2636 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2637 cmd->seid = CPU_TO_LE16(seid); 2638 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2639 2640 return status; 2641 } 2642 2643 /** 2644 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2645 * @hw: pointer to the hw struct 2646 * @seid: vsi number 2647 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2648 * @cmd_details: pointer to command details structure or NULL 2649 **/ 2650 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2651 u16 seid, bool enable, 2652 struct i40e_asq_cmd_details *cmd_details) 2653 { 2654 struct i40e_aq_desc desc; 2655 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2656 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2657 enum i40e_status_code status; 2658 u16 flags = 0; 2659 2660 i40e_fill_default_direct_cmd_desc(&desc, 2661 i40e_aqc_opc_set_vsi_promiscuous_modes); 2662 if (enable) 2663 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2664 2665 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2666 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2667 cmd->seid = CPU_TO_LE16(seid); 2668 2669 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2670 2671 return status; 2672 } 2673 2674 /** 2675 * i40e_get_vsi_params - get VSI configuration info 2676 * @hw: pointer to the hw struct 2677 * @vsi_ctx: pointer to a vsi context struct 2678 * @cmd_details: pointer to command details structure or NULL 2679 **/ 2680 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2681 struct i40e_vsi_context *vsi_ctx, 2682 struct i40e_asq_cmd_details *cmd_details) 2683 { 2684 struct i40e_aq_desc desc; 2685 struct i40e_aqc_add_get_update_vsi *cmd = 2686 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2687 struct i40e_aqc_add_get_update_vsi_completion *resp = 2688 (struct i40e_aqc_add_get_update_vsi_completion *) 2689 &desc.params.raw; 2690 enum i40e_status_code status; 2691 2692 UNREFERENCED_1PARAMETER(cmd_details); 2693 i40e_fill_default_direct_cmd_desc(&desc, 2694 i40e_aqc_opc_get_vsi_parameters); 2695 2696 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2697 2698 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2699 2700 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2701 sizeof(vsi_ctx->info), NULL); 2702 2703 if (status != I40E_SUCCESS) 2704 goto aq_get_vsi_params_exit; 2705 2706 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2707 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2708 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2709 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2710 2711 aq_get_vsi_params_exit: 2712 return status; 2713 } 2714 2715 /** 2716 * i40e_aq_update_vsi_params 2717 * @hw: pointer to the hw struct 2718 * @vsi_ctx: pointer to a vsi context struct 2719 * @cmd_details: pointer to command details structure or NULL 2720 * 2721 * Update a VSI context. 2722 **/ 2723 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2724 struct i40e_vsi_context *vsi_ctx, 2725 struct i40e_asq_cmd_details *cmd_details) 2726 { 2727 struct i40e_aq_desc desc; 2728 struct i40e_aqc_add_get_update_vsi *cmd = 2729 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2730 struct i40e_aqc_add_get_update_vsi_completion *resp = 2731 (struct i40e_aqc_add_get_update_vsi_completion *) 2732 &desc.params.raw; 2733 enum i40e_status_code status; 2734 2735 i40e_fill_default_direct_cmd_desc(&desc, 2736 i40e_aqc_opc_update_vsi_parameters); 2737 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2738 2739 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2740 2741 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2742 sizeof(vsi_ctx->info), cmd_details); 2743 2744 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2745 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2746 2747 return status; 2748 } 2749 2750 /** 2751 * i40e_aq_get_switch_config 2752 * @hw: pointer to the hardware structure 2753 * @buf: pointer to the result buffer 2754 * @buf_size: length of input buffer 2755 * @start_seid: seid to start for the report, 0 == beginning 2756 * @cmd_details: pointer to command details structure or NULL 2757 * 2758 * Fill the buf with switch configuration returned from AdminQ command 2759 **/ 2760 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2761 struct i40e_aqc_get_switch_config_resp *buf, 2762 u16 buf_size, u16 *start_seid, 2763 struct i40e_asq_cmd_details *cmd_details) 2764 { 2765 struct i40e_aq_desc desc; 2766 struct i40e_aqc_switch_seid *scfg = 2767 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2768 enum i40e_status_code status; 2769 2770 i40e_fill_default_direct_cmd_desc(&desc, 2771 i40e_aqc_opc_get_switch_config); 2772 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2773 if (buf_size > I40E_AQ_LARGE_BUF) 2774 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2775 scfg->seid = CPU_TO_LE16(*start_seid); 2776 2777 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2778 *start_seid = LE16_TO_CPU(scfg->seid); 2779 2780 return status; 2781 } 2782 2783 /** 2784 * i40e_aq_set_switch_config 2785 * @hw: pointer to the hardware structure 2786 * @flags: bit flag values to set 2787 * @mode: cloud filter mode 2788 * @valid_flags: which bit flags to set 2789 * @cmd_details: pointer to command details structure or NULL 2790 * 2791 * Set switch configuration bits 2792 **/ 2793 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2794 u16 flags, u16 valid_flags, u8 mode, 2795 struct i40e_asq_cmd_details *cmd_details) 2796 { 2797 struct i40e_aq_desc desc; 2798 struct i40e_aqc_set_switch_config *scfg = 2799 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2800 enum i40e_status_code status; 2801 2802 i40e_fill_default_direct_cmd_desc(&desc, 2803 i40e_aqc_opc_set_switch_config); 2804 scfg->flags = CPU_TO_LE16(flags); 2805 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2806 scfg->mode = mode; 2807 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2808 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); 2809 scfg->first_tag = CPU_TO_LE16(hw->first_tag); 2810 scfg->second_tag = CPU_TO_LE16(hw->second_tag); 2811 } 2812 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2813 2814 return status; 2815 } 2816 2817 /** 2818 * i40e_aq_get_firmware_version 2819 * @hw: pointer to the hw struct 2820 * @fw_major_version: firmware major version 2821 * @fw_minor_version: firmware minor version 2822 * @fw_build: firmware build number 2823 * @api_major_version: major queue version 2824 * @api_minor_version: minor queue version 2825 * @cmd_details: pointer to command details structure or NULL 2826 * 2827 * Get the firmware version from the admin queue commands 2828 **/ 2829 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2830 u16 *fw_major_version, u16 *fw_minor_version, 2831 u32 *fw_build, 2832 u16 *api_major_version, u16 *api_minor_version, 2833 struct i40e_asq_cmd_details *cmd_details) 2834 { 2835 struct i40e_aq_desc desc; 2836 struct i40e_aqc_get_version *resp = 2837 (struct i40e_aqc_get_version *)&desc.params.raw; 2838 enum i40e_status_code status; 2839 2840 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2841 2842 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2843 2844 if (status == I40E_SUCCESS) { 2845 if (fw_major_version != NULL) 2846 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2847 if (fw_minor_version != NULL) 2848 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2849 if (fw_build != NULL) 2850 *fw_build = LE32_TO_CPU(resp->fw_build); 2851 if (api_major_version != NULL) 2852 *api_major_version = LE16_TO_CPU(resp->api_major); 2853 if (api_minor_version != NULL) 2854 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2855 2856 /* A workaround to fix the API version in SW */ 2857 if (api_major_version && api_minor_version && 2858 fw_major_version && fw_minor_version && 2859 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2860 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2861 (*fw_major_version > 4))) 2862 *api_minor_version = 2; 2863 } 2864 2865 return status; 2866 } 2867 2868 /** 2869 * i40e_aq_send_driver_version 2870 * @hw: pointer to the hw struct 2871 * @dv: driver's major, minor version 2872 * @cmd_details: pointer to command details structure or NULL 2873 * 2874 * Send the driver version to the firmware 2875 **/ 2876 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2877 struct i40e_driver_version *dv, 2878 struct i40e_asq_cmd_details *cmd_details) 2879 { 2880 struct i40e_aq_desc desc; 2881 struct i40e_aqc_driver_version *cmd = 2882 (struct i40e_aqc_driver_version *)&desc.params.raw; 2883 enum i40e_status_code status; 2884 u16 len; 2885 2886 if (dv == NULL) 2887 return I40E_ERR_PARAM; 2888 2889 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2890 2891 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2892 cmd->driver_major_ver = dv->major_version; 2893 cmd->driver_minor_ver = dv->minor_version; 2894 cmd->driver_build_ver = dv->build_version; 2895 cmd->driver_subbuild_ver = dv->subbuild_version; 2896 2897 len = 0; 2898 while (len < sizeof(dv->driver_string) && 2899 (dv->driver_string[len] < 0x80) && 2900 dv->driver_string[len]) 2901 len++; 2902 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2903 len, cmd_details); 2904 2905 return status; 2906 } 2907 2908 /** 2909 * i40e_get_link_status - get status of the HW network link 2910 * @hw: pointer to the hw struct 2911 * @link_up: pointer to bool (true/false = linkup/linkdown) 2912 * 2913 * Variable link_up true if link is up, false if link is down. 2914 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2915 * 2916 * Side effect: LinkStatusEvent reporting becomes enabled 2917 **/ 2918 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2919 { 2920 enum i40e_status_code status = I40E_SUCCESS; 2921 2922 if (hw->phy.get_link_info) { 2923 status = i40e_update_link_info(hw); 2924 2925 if (status != I40E_SUCCESS) 2926 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2927 status); 2928 } 2929 2930 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2931 2932 return status; 2933 } 2934 2935 /** 2936 * i40e_updatelink_status - update status of the HW network link 2937 * @hw: pointer to the hw struct 2938 **/ 2939 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2940 { 2941 struct i40e_aq_get_phy_abilities_resp abilities; 2942 enum i40e_status_code status = I40E_SUCCESS; 2943 2944 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2945 if (status) 2946 return status; 2947 2948 /* extra checking needed to ensure link info to user is timely */ 2949 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2950 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2951 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2952 status = i40e_aq_get_phy_capabilities(hw, false, false, 2953 &abilities, NULL); 2954 if (status) 2955 return status; 2956 2957 if (abilities.fec_cfg_curr_mod_ext_info & 2958 I40E_AQ_ENABLE_FEC_AUTO) 2959 hw->phy.link_info.req_fec_info = 2960 (I40E_AQ_REQUEST_FEC_KR | 2961 I40E_AQ_REQUEST_FEC_RS); 2962 else 2963 hw->phy.link_info.req_fec_info = 2964 abilities.fec_cfg_curr_mod_ext_info & 2965 (I40E_AQ_REQUEST_FEC_KR | 2966 I40E_AQ_REQUEST_FEC_RS); 2967 2968 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2969 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2970 } 2971 return status; 2972 } 2973 2974 2975 /** 2976 * i40e_get_link_speed 2977 * @hw: pointer to the hw struct 2978 * 2979 * Returns the link speed of the adapter. 2980 **/ 2981 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2982 { 2983 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2984 enum i40e_status_code status = I40E_SUCCESS; 2985 2986 if (hw->phy.get_link_info) { 2987 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2988 2989 if (status != I40E_SUCCESS) 2990 goto i40e_link_speed_exit; 2991 } 2992 2993 speed = hw->phy.link_info.link_speed; 2994 2995 i40e_link_speed_exit: 2996 return speed; 2997 } 2998 2999 /** 3000 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 3001 * @hw: pointer to the hw struct 3002 * @uplink_seid: the MAC or other gizmo SEID 3003 * @downlink_seid: the VSI SEID 3004 * @enabled_tc: bitmap of TCs to be enabled 3005 * @default_port: true for default port VSI, false for control port 3006 * @veb_seid: pointer to where to put the resulting VEB SEID 3007 * @enable_stats: true to turn on VEB stats 3008 * @cmd_details: pointer to command details structure or NULL 3009 * 3010 * This asks the FW to add a VEB between the uplink and downlink 3011 * elements. If the uplink SEID is 0, this will be a floating VEB. 3012 **/ 3013 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 3014 u16 downlink_seid, u8 enabled_tc, 3015 bool default_port, u16 *veb_seid, 3016 bool enable_stats, 3017 struct i40e_asq_cmd_details *cmd_details) 3018 { 3019 struct i40e_aq_desc desc; 3020 struct i40e_aqc_add_veb *cmd = 3021 (struct i40e_aqc_add_veb *)&desc.params.raw; 3022 struct i40e_aqc_add_veb_completion *resp = 3023 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 3024 enum i40e_status_code status; 3025 u16 veb_flags = 0; 3026 3027 /* SEIDs need to either both be set or both be 0 for floating VEB */ 3028 if (!!uplink_seid != !!downlink_seid) 3029 return I40E_ERR_PARAM; 3030 3031 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 3032 3033 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 3034 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 3035 cmd->enable_tcs = enabled_tc; 3036 if (!uplink_seid) 3037 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 3038 if (default_port) 3039 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 3040 else 3041 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 3042 3043 /* reverse logic here: set the bitflag to disable the stats */ 3044 if (!enable_stats) 3045 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 3046 3047 cmd->veb_flags = CPU_TO_LE16(veb_flags); 3048 3049 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3050 3051 if (!status && veb_seid) 3052 *veb_seid = LE16_TO_CPU(resp->veb_seid); 3053 3054 return status; 3055 } 3056 3057 /** 3058 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 3059 * @hw: pointer to the hw struct 3060 * @veb_seid: the SEID of the VEB to query 3061 * @switch_id: the uplink switch id 3062 * @floating: set to true if the VEB is floating 3063 * @statistic_index: index of the stats counter block for this VEB 3064 * @vebs_used: number of VEB's used by function 3065 * @vebs_free: total VEB's not reserved by any function 3066 * @cmd_details: pointer to command details structure or NULL 3067 * 3068 * This retrieves the parameters for a particular VEB, specified by 3069 * uplink_seid, and returns them to the caller. 3070 **/ 3071 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 3072 u16 veb_seid, u16 *switch_id, 3073 bool *floating, u16 *statistic_index, 3074 u16 *vebs_used, u16 *vebs_free, 3075 struct i40e_asq_cmd_details *cmd_details) 3076 { 3077 struct i40e_aq_desc desc; 3078 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 3079 (struct i40e_aqc_get_veb_parameters_completion *) 3080 &desc.params.raw; 3081 enum i40e_status_code status; 3082 3083 if (veb_seid == 0) 3084 return I40E_ERR_PARAM; 3085 3086 i40e_fill_default_direct_cmd_desc(&desc, 3087 i40e_aqc_opc_get_veb_parameters); 3088 cmd_resp->seid = CPU_TO_LE16(veb_seid); 3089 3090 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3091 if (status) 3092 goto get_veb_exit; 3093 3094 if (switch_id) 3095 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 3096 if (statistic_index) 3097 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 3098 if (vebs_used) 3099 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 3100 if (vebs_free) 3101 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 3102 if (floating) { 3103 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 3104 3105 if (flags & I40E_AQC_ADD_VEB_FLOATING) 3106 *floating = true; 3107 else 3108 *floating = false; 3109 } 3110 3111 get_veb_exit: 3112 return status; 3113 } 3114 3115 /** 3116 * i40e_aq_add_macvlan 3117 * @hw: pointer to the hw struct 3118 * @seid: VSI for the mac address 3119 * @mv_list: list of macvlans to be added 3120 * @count: length of the list 3121 * @cmd_details: pointer to command details structure or NULL 3122 * 3123 * Add MAC/VLAN addresses to the HW filtering 3124 **/ 3125 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 3126 struct i40e_aqc_add_macvlan_element_data *mv_list, 3127 u16 count, struct i40e_asq_cmd_details *cmd_details) 3128 { 3129 struct i40e_aq_desc desc; 3130 struct i40e_aqc_macvlan *cmd = 3131 (struct i40e_aqc_macvlan *)&desc.params.raw; 3132 enum i40e_status_code status; 3133 u16 buf_size; 3134 int i; 3135 3136 if (count == 0 || !mv_list || !hw) 3137 return I40E_ERR_PARAM; 3138 3139 buf_size = count * sizeof(*mv_list); 3140 3141 /* prep the rest of the request */ 3142 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 3143 cmd->num_addresses = CPU_TO_LE16(count); 3144 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3145 cmd->seid[1] = 0; 3146 cmd->seid[2] = 0; 3147 3148 for (i = 0; i < count; i++) 3149 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 3150 mv_list[i].flags |= 3151 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 3152 3153 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3154 if (buf_size > I40E_AQ_LARGE_BUF) 3155 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3156 3157 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3158 cmd_details); 3159 3160 return status; 3161 } 3162 3163 /** 3164 * i40e_aq_remove_macvlan 3165 * @hw: pointer to the hw struct 3166 * @seid: VSI for the mac address 3167 * @mv_list: list of macvlans to be removed 3168 * @count: length of the list 3169 * @cmd_details: pointer to command details structure or NULL 3170 * 3171 * Remove MAC/VLAN addresses from the HW filtering 3172 **/ 3173 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 3174 struct i40e_aqc_remove_macvlan_element_data *mv_list, 3175 u16 count, struct i40e_asq_cmd_details *cmd_details) 3176 { 3177 struct i40e_aq_desc desc; 3178 struct i40e_aqc_macvlan *cmd = 3179 (struct i40e_aqc_macvlan *)&desc.params.raw; 3180 enum i40e_status_code status; 3181 u16 buf_size; 3182 3183 if (count == 0 || !mv_list || !hw) 3184 return I40E_ERR_PARAM; 3185 3186 buf_size = count * sizeof(*mv_list); 3187 3188 /* prep the rest of the request */ 3189 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3190 cmd->num_addresses = CPU_TO_LE16(count); 3191 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3192 cmd->seid[1] = 0; 3193 cmd->seid[2] = 0; 3194 3195 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3196 if (buf_size > I40E_AQ_LARGE_BUF) 3197 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3198 3199 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3200 cmd_details); 3201 3202 return status; 3203 } 3204 3205 /** 3206 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3207 * @hw: pointer to the hw struct 3208 * @opcode: AQ opcode for add or delete mirror rule 3209 * @sw_seid: Switch SEID (to which rule refers) 3210 * @rule_type: Rule Type (ingress/egress/VLAN) 3211 * @id: Destination VSI SEID or Rule ID 3212 * @count: length of the list 3213 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3214 * @cmd_details: pointer to command details structure or NULL 3215 * @rule_id: Rule ID returned from FW 3216 * @rules_used: Number of rules used in internal switch 3217 * @rules_free: Number of rules free in internal switch 3218 * 3219 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3220 * VEBs/VEPA elements only 3221 **/ 3222 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3223 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3224 u16 count, __le16 *mr_list, 3225 struct i40e_asq_cmd_details *cmd_details, 3226 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3227 { 3228 struct i40e_aq_desc desc; 3229 struct i40e_aqc_add_delete_mirror_rule *cmd = 3230 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3231 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3232 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3233 enum i40e_status_code status; 3234 u16 buf_size; 3235 3236 buf_size = count * sizeof(*mr_list); 3237 3238 /* prep the rest of the request */ 3239 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3240 cmd->seid = CPU_TO_LE16(sw_seid); 3241 cmd->rule_type = CPU_TO_LE16(rule_type & 3242 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3243 cmd->num_entries = CPU_TO_LE16(count); 3244 /* Dest VSI for add, rule_id for delete */ 3245 cmd->destination = CPU_TO_LE16(id); 3246 if (mr_list) { 3247 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3248 I40E_AQ_FLAG_RD)); 3249 if (buf_size > I40E_AQ_LARGE_BUF) 3250 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3251 } 3252 3253 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3254 cmd_details); 3255 if (status == I40E_SUCCESS || 3256 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3257 if (rule_id) 3258 *rule_id = LE16_TO_CPU(resp->rule_id); 3259 if (rules_used) 3260 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3261 if (rules_free) 3262 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3263 } 3264 return status; 3265 } 3266 3267 /** 3268 * i40e_aq_add_mirrorrule - add a mirror rule 3269 * @hw: pointer to the hw struct 3270 * @sw_seid: Switch SEID (to which rule refers) 3271 * @rule_type: Rule Type (ingress/egress/VLAN) 3272 * @dest_vsi: SEID of VSI to which packets will be mirrored 3273 * @count: length of the list 3274 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3275 * @cmd_details: pointer to command details structure or NULL 3276 * @rule_id: Rule ID returned from FW 3277 * @rules_used: Number of rules used in internal switch 3278 * @rules_free: Number of rules free in internal switch 3279 * 3280 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3281 **/ 3282 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3283 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3284 struct i40e_asq_cmd_details *cmd_details, 3285 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3286 { 3287 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3288 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3289 if (count == 0 || !mr_list) 3290 return I40E_ERR_PARAM; 3291 } 3292 3293 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3294 rule_type, dest_vsi, count, mr_list, 3295 cmd_details, rule_id, rules_used, rules_free); 3296 } 3297 3298 /** 3299 * i40e_aq_delete_mirrorrule - delete a mirror rule 3300 * @hw: pointer to the hw struct 3301 * @sw_seid: Switch SEID (to which rule refers) 3302 * @rule_type: Rule Type (ingress/egress/VLAN) 3303 * @count: length of the list 3304 * @rule_id: Rule ID that is returned in the receive desc as part of 3305 * add_mirrorrule. 3306 * @mr_list: list of mirrored VLAN IDs to be removed 3307 * @cmd_details: pointer to command details structure or NULL 3308 * @rules_used: Number of rules used in internal switch 3309 * @rules_free: Number of rules free in internal switch 3310 * 3311 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3312 **/ 3313 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3314 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3315 struct i40e_asq_cmd_details *cmd_details, 3316 u16 *rules_used, u16 *rules_free) 3317 { 3318 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3319 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3320 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3321 * mirroring. For other rule_type, count and rule_type should 3322 * not matter. 3323 */ 3324 if (count == 0 || !mr_list) 3325 return I40E_ERR_PARAM; 3326 } 3327 3328 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3329 rule_type, rule_id, count, mr_list, 3330 cmd_details, NULL, rules_used, rules_free); 3331 } 3332 3333 /** 3334 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3335 * @hw: pointer to the hw struct 3336 * @seid: VSI for the vlan filters 3337 * @v_list: list of vlan filters to be added 3338 * @count: length of the list 3339 * @cmd_details: pointer to command details structure or NULL 3340 **/ 3341 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3342 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3343 u8 count, struct i40e_asq_cmd_details *cmd_details) 3344 { 3345 struct i40e_aq_desc desc; 3346 struct i40e_aqc_macvlan *cmd = 3347 (struct i40e_aqc_macvlan *)&desc.params.raw; 3348 enum i40e_status_code status; 3349 u16 buf_size; 3350 3351 if (count == 0 || !v_list || !hw) 3352 return I40E_ERR_PARAM; 3353 3354 buf_size = count * sizeof(*v_list); 3355 3356 /* prep the rest of the request */ 3357 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3358 cmd->num_addresses = CPU_TO_LE16(count); 3359 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3360 cmd->seid[1] = 0; 3361 cmd->seid[2] = 0; 3362 3363 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3364 if (buf_size > I40E_AQ_LARGE_BUF) 3365 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3366 3367 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3368 cmd_details); 3369 3370 return status; 3371 } 3372 3373 /** 3374 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3375 * @hw: pointer to the hw struct 3376 * @seid: VSI for the vlan filters 3377 * @v_list: list of macvlans to be removed 3378 * @count: length of the list 3379 * @cmd_details: pointer to command details structure or NULL 3380 **/ 3381 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3382 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3383 u8 count, struct i40e_asq_cmd_details *cmd_details) 3384 { 3385 struct i40e_aq_desc desc; 3386 struct i40e_aqc_macvlan *cmd = 3387 (struct i40e_aqc_macvlan *)&desc.params.raw; 3388 enum i40e_status_code status; 3389 u16 buf_size; 3390 3391 if (count == 0 || !v_list || !hw) 3392 return I40E_ERR_PARAM; 3393 3394 buf_size = count * sizeof(*v_list); 3395 3396 /* prep the rest of the request */ 3397 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3398 cmd->num_addresses = CPU_TO_LE16(count); 3399 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3400 cmd->seid[1] = 0; 3401 cmd->seid[2] = 0; 3402 3403 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3404 if (buf_size > I40E_AQ_LARGE_BUF) 3405 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3406 3407 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3408 cmd_details); 3409 3410 return status; 3411 } 3412 3413 /** 3414 * i40e_aq_send_msg_to_vf 3415 * @hw: pointer to the hardware structure 3416 * @vfid: vf id to send msg 3417 * @v_opcode: opcodes for VF-PF communication 3418 * @v_retval: return error code 3419 * @msg: pointer to the msg buffer 3420 * @msglen: msg length 3421 * @cmd_details: pointer to command details 3422 * 3423 * send msg to vf 3424 **/ 3425 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3426 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3427 struct i40e_asq_cmd_details *cmd_details) 3428 { 3429 struct i40e_aq_desc desc; 3430 struct i40e_aqc_pf_vf_message *cmd = 3431 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3432 enum i40e_status_code status; 3433 3434 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3435 cmd->id = CPU_TO_LE32(vfid); 3436 desc.cookie_high = CPU_TO_LE32(v_opcode); 3437 desc.cookie_low = CPU_TO_LE32(v_retval); 3438 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3439 if (msglen) { 3440 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3441 I40E_AQ_FLAG_RD)); 3442 if (msglen > I40E_AQ_LARGE_BUF) 3443 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3444 desc.datalen = CPU_TO_LE16(msglen); 3445 } 3446 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3447 3448 return status; 3449 } 3450 3451 /** 3452 * i40e_aq_debug_read_register 3453 * @hw: pointer to the hw struct 3454 * @reg_addr: register address 3455 * @reg_val: register value 3456 * @cmd_details: pointer to command details structure or NULL 3457 * 3458 * Read the register using the admin queue commands 3459 **/ 3460 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3461 u32 reg_addr, u64 *reg_val, 3462 struct i40e_asq_cmd_details *cmd_details) 3463 { 3464 struct i40e_aq_desc desc; 3465 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3466 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3467 enum i40e_status_code status; 3468 3469 if (reg_val == NULL) 3470 return I40E_ERR_PARAM; 3471 3472 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3473 3474 cmd_resp->address = CPU_TO_LE32(reg_addr); 3475 3476 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3477 3478 if (status == I40E_SUCCESS) { 3479 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3480 (u64)LE32_TO_CPU(cmd_resp->value_low); 3481 } 3482 3483 return status; 3484 } 3485 3486 /** 3487 * i40e_aq_debug_write_register 3488 * @hw: pointer to the hw struct 3489 * @reg_addr: register address 3490 * @reg_val: register value 3491 * @cmd_details: pointer to command details structure or NULL 3492 * 3493 * Write to a register using the admin queue commands 3494 **/ 3495 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3496 u32 reg_addr, u64 reg_val, 3497 struct i40e_asq_cmd_details *cmd_details) 3498 { 3499 struct i40e_aq_desc desc; 3500 struct i40e_aqc_debug_reg_read_write *cmd = 3501 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3502 enum i40e_status_code status; 3503 3504 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3505 3506 cmd->address = CPU_TO_LE32(reg_addr); 3507 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3508 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3509 3510 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3511 3512 return status; 3513 } 3514 3515 /** 3516 * i40e_aq_request_resource 3517 * @hw: pointer to the hw struct 3518 * @resource: resource id 3519 * @access: access type 3520 * @sdp_number: resource number 3521 * @timeout: the maximum time in ms that the driver may hold the resource 3522 * @cmd_details: pointer to command details structure or NULL 3523 * 3524 * requests common resource using the admin queue commands 3525 **/ 3526 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3527 enum i40e_aq_resources_ids resource, 3528 enum i40e_aq_resource_access_type access, 3529 u8 sdp_number, u64 *timeout, 3530 struct i40e_asq_cmd_details *cmd_details) 3531 { 3532 struct i40e_aq_desc desc; 3533 struct i40e_aqc_request_resource *cmd_resp = 3534 (struct i40e_aqc_request_resource *)&desc.params.raw; 3535 enum i40e_status_code status; 3536 3537 DEBUGFUNC("i40e_aq_request_resource"); 3538 3539 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3540 3541 cmd_resp->resource_id = CPU_TO_LE16(resource); 3542 cmd_resp->access_type = CPU_TO_LE16(access); 3543 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3544 3545 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3546 /* The completion specifies the maximum time in ms that the driver 3547 * may hold the resource in the Timeout field. 3548 * If the resource is held by someone else, the command completes with 3549 * busy return value and the timeout field indicates the maximum time 3550 * the current owner of the resource has to free it. 3551 */ 3552 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3553 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3554 3555 return status; 3556 } 3557 3558 /** 3559 * i40e_aq_release_resource 3560 * @hw: pointer to the hw struct 3561 * @resource: resource id 3562 * @sdp_number: resource number 3563 * @cmd_details: pointer to command details structure or NULL 3564 * 3565 * release common resource using the admin queue commands 3566 **/ 3567 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3568 enum i40e_aq_resources_ids resource, 3569 u8 sdp_number, 3570 struct i40e_asq_cmd_details *cmd_details) 3571 { 3572 struct i40e_aq_desc desc; 3573 struct i40e_aqc_request_resource *cmd = 3574 (struct i40e_aqc_request_resource *)&desc.params.raw; 3575 enum i40e_status_code status; 3576 3577 DEBUGFUNC("i40e_aq_release_resource"); 3578 3579 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3580 3581 cmd->resource_id = CPU_TO_LE16(resource); 3582 cmd->resource_number = CPU_TO_LE32(sdp_number); 3583 3584 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3585 3586 return status; 3587 } 3588 3589 /** 3590 * i40e_aq_read_nvm 3591 * @hw: pointer to the hw struct 3592 * @module_pointer: module pointer location in words from the NVM beginning 3593 * @offset: byte offset from the module beginning 3594 * @length: length of the section to be read (in bytes from the offset) 3595 * @data: command buffer (size [bytes] = length) 3596 * @last_command: tells if this is the last command in a series 3597 * @cmd_details: pointer to command details structure or NULL 3598 * 3599 * Read the NVM using the admin queue commands 3600 **/ 3601 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3602 u32 offset, u16 length, void *data, 3603 bool last_command, 3604 struct i40e_asq_cmd_details *cmd_details) 3605 { 3606 struct i40e_aq_desc desc; 3607 struct i40e_aqc_nvm_update *cmd = 3608 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3609 enum i40e_status_code status; 3610 3611 DEBUGFUNC("i40e_aq_read_nvm"); 3612 3613 /* In offset the highest byte must be zeroed. */ 3614 if (offset & 0xFF000000) { 3615 status = I40E_ERR_PARAM; 3616 goto i40e_aq_read_nvm_exit; 3617 } 3618 3619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3620 3621 /* If this is the last command in a series, set the proper flag. */ 3622 if (last_command) 3623 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3624 cmd->module_pointer = module_pointer; 3625 cmd->offset = CPU_TO_LE32(offset); 3626 cmd->length = CPU_TO_LE16(length); 3627 3628 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3629 if (length > I40E_AQ_LARGE_BUF) 3630 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3631 3632 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3633 3634 i40e_aq_read_nvm_exit: 3635 return status; 3636 } 3637 3638 /** 3639 * i40e_aq_read_nvm_config - read an nvm config block 3640 * @hw: pointer to the hw struct 3641 * @cmd_flags: NVM access admin command bits 3642 * @field_id: field or feature id 3643 * @data: buffer for result 3644 * @buf_size: buffer size 3645 * @element_count: pointer to count of elements read by FW 3646 * @cmd_details: pointer to command details structure or NULL 3647 **/ 3648 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3649 u8 cmd_flags, u32 field_id, void *data, 3650 u16 buf_size, u16 *element_count, 3651 struct i40e_asq_cmd_details *cmd_details) 3652 { 3653 struct i40e_aq_desc desc; 3654 struct i40e_aqc_nvm_config_read *cmd = 3655 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3656 enum i40e_status_code status; 3657 3658 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3659 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3660 if (buf_size > I40E_AQ_LARGE_BUF) 3661 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3662 3663 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3664 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3665 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3666 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3667 else 3668 cmd->element_id_msw = 0; 3669 3670 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3671 3672 if (!status && element_count) 3673 *element_count = LE16_TO_CPU(cmd->element_count); 3674 3675 return status; 3676 } 3677 3678 /** 3679 * i40e_aq_write_nvm_config - write an nvm config block 3680 * @hw: pointer to the hw struct 3681 * @cmd_flags: NVM access admin command bits 3682 * @data: buffer for result 3683 * @buf_size: buffer size 3684 * @element_count: count of elements to be written 3685 * @cmd_details: pointer to command details structure or NULL 3686 **/ 3687 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3688 u8 cmd_flags, void *data, u16 buf_size, 3689 u16 element_count, 3690 struct i40e_asq_cmd_details *cmd_details) 3691 { 3692 struct i40e_aq_desc desc; 3693 struct i40e_aqc_nvm_config_write *cmd = 3694 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3695 enum i40e_status_code status; 3696 3697 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3698 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3699 if (buf_size > I40E_AQ_LARGE_BUF) 3700 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3701 3702 cmd->element_count = CPU_TO_LE16(element_count); 3703 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3704 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3705 3706 return status; 3707 } 3708 3709 /** 3710 * i40e_aq_nvm_update_in_process 3711 * @hw: pointer to the hw struct 3712 * @update_flow_state: True indicates that update flow starts, false that ends 3713 * @cmd_details: pointer to command details structure or NULL 3714 * 3715 * Indicate NVM update in process. 3716 **/ 3717 enum i40e_status_code 3718 i40e_aq_nvm_update_in_process(struct i40e_hw *hw, 3719 bool update_flow_state, 3720 struct i40e_asq_cmd_details *cmd_details) 3721 { 3722 struct i40e_aq_desc desc; 3723 struct i40e_aqc_nvm_update_in_process *cmd = 3724 (struct i40e_aqc_nvm_update_in_process *)&desc.params.raw; 3725 enum i40e_status_code status; 3726 3727 i40e_fill_default_direct_cmd_desc(&desc, 3728 i40e_aqc_opc_nvm_update_in_process); 3729 3730 cmd->command = I40E_AQ_UPDATE_FLOW_END; 3731 3732 if (update_flow_state) 3733 cmd->command |= I40E_AQ_UPDATE_FLOW_START; 3734 3735 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3736 3737 return status; 3738 } 3739 3740 /** 3741 * i40e_aq_min_rollback_rev_update - triggers an ow after update 3742 * @hw: pointer to the hw struct 3743 * @mode: opt-in mode, 1b for single module update, 0b for bulk update 3744 * @module: module to be updated. Ignored if mode is 0b 3745 * @min_rrev: value of the new minimal version. Ignored if mode is 0b 3746 * @cmd_details: pointer to command details structure or NULL 3747 **/ 3748 enum i40e_status_code 3749 i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module, 3750 u32 min_rrev, 3751 struct i40e_asq_cmd_details *cmd_details) 3752 { 3753 struct i40e_aq_desc desc; 3754 struct i40e_aqc_rollback_revision_update *cmd = 3755 (struct i40e_aqc_rollback_revision_update *)&desc.params.raw; 3756 enum i40e_status_code status; 3757 3758 i40e_fill_default_direct_cmd_desc(&desc, 3759 i40e_aqc_opc_rollback_revision_update); 3760 cmd->optin_mode = mode; 3761 cmd->module_selected = module; 3762 cmd->min_rrev = min_rrev; 3763 3764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3765 3766 return status; 3767 } 3768 3769 /** 3770 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3771 * @hw: pointer to the hw struct 3772 * @buff: buffer for result 3773 * @buff_size: buffer size 3774 * @cmd_details: pointer to command details structure or NULL 3775 **/ 3776 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3777 void *buff, u16 buff_size, 3778 struct i40e_asq_cmd_details *cmd_details) 3779 { 3780 struct i40e_aq_desc desc; 3781 enum i40e_status_code status; 3782 3783 UNREFERENCED_2PARAMETER(buff, buff_size); 3784 3785 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3786 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3787 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3788 status = I40E_ERR_NOT_IMPLEMENTED; 3789 3790 return status; 3791 } 3792 3793 /** 3794 * i40e_aq_erase_nvm 3795 * @hw: pointer to the hw struct 3796 * @module_pointer: module pointer location in words from the NVM beginning 3797 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3798 * @length: length of the section to be erased (expressed in 4 KB) 3799 * @last_command: tells if this is the last command in a series 3800 * @cmd_details: pointer to command details structure or NULL 3801 * 3802 * Erase the NVM sector using the admin queue commands 3803 **/ 3804 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3805 u32 offset, u16 length, bool last_command, 3806 struct i40e_asq_cmd_details *cmd_details) 3807 { 3808 struct i40e_aq_desc desc; 3809 struct i40e_aqc_nvm_update *cmd = 3810 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3811 enum i40e_status_code status; 3812 3813 DEBUGFUNC("i40e_aq_erase_nvm"); 3814 3815 /* In offset the highest byte must be zeroed. */ 3816 if (offset & 0xFF000000) { 3817 status = I40E_ERR_PARAM; 3818 goto i40e_aq_erase_nvm_exit; 3819 } 3820 3821 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3822 3823 /* If this is the last command in a series, set the proper flag. */ 3824 if (last_command) 3825 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3826 cmd->module_pointer = module_pointer; 3827 cmd->offset = CPU_TO_LE32(offset); 3828 cmd->length = CPU_TO_LE16(length); 3829 3830 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3831 3832 i40e_aq_erase_nvm_exit: 3833 return status; 3834 } 3835 3836 /** 3837 * i40e_parse_discover_capabilities 3838 * @hw: pointer to the hw struct 3839 * @buff: pointer to a buffer containing device/function capability records 3840 * @cap_count: number of capability records in the list 3841 * @list_type_opc: type of capabilities list to parse 3842 * 3843 * Parse the device/function capabilities list. 3844 **/ 3845 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3846 u32 cap_count, 3847 enum i40e_admin_queue_opc list_type_opc) 3848 { 3849 struct i40e_aqc_list_capabilities_element_resp *cap; 3850 u32 valid_functions, num_functions; 3851 u32 number, logical_id, phys_id; 3852 struct i40e_hw_capabilities *p; 3853 enum i40e_status_code status; 3854 u16 id, ocp_cfg_word0; 3855 u8 major_rev; 3856 u32 i = 0; 3857 3858 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3859 3860 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3861 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3862 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3863 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3864 else 3865 return; 3866 3867 for (i = 0; i < cap_count; i++, cap++) { 3868 id = LE16_TO_CPU(cap->id); 3869 number = LE32_TO_CPU(cap->number); 3870 logical_id = LE32_TO_CPU(cap->logical_id); 3871 phys_id = LE32_TO_CPU(cap->phys_id); 3872 major_rev = cap->major_rev; 3873 3874 switch (id) { 3875 case I40E_AQ_CAP_ID_SWITCH_MODE: 3876 p->switch_mode = number; 3877 i40e_debug(hw, I40E_DEBUG_INIT, 3878 "HW Capability: Switch mode = %d\n", 3879 p->switch_mode); 3880 break; 3881 case I40E_AQ_CAP_ID_MNG_MODE: 3882 p->management_mode = number; 3883 if (major_rev > 1) { 3884 p->mng_protocols_over_mctp = logical_id; 3885 i40e_debug(hw, I40E_DEBUG_INIT, 3886 "HW Capability: Protocols over MCTP = %d\n", 3887 p->mng_protocols_over_mctp); 3888 } else { 3889 p->mng_protocols_over_mctp = 0; 3890 } 3891 i40e_debug(hw, I40E_DEBUG_INIT, 3892 "HW Capability: Management Mode = %d\n", 3893 p->management_mode); 3894 break; 3895 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3896 p->npar_enable = number; 3897 i40e_debug(hw, I40E_DEBUG_INIT, 3898 "HW Capability: NPAR enable = %d\n", 3899 p->npar_enable); 3900 break; 3901 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3902 p->os2bmc = number; 3903 i40e_debug(hw, I40E_DEBUG_INIT, 3904 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3905 break; 3906 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3907 p->valid_functions = number; 3908 i40e_debug(hw, I40E_DEBUG_INIT, 3909 "HW Capability: Valid Functions = %d\n", 3910 p->valid_functions); 3911 break; 3912 case I40E_AQ_CAP_ID_SRIOV: 3913 if (number == 1) 3914 p->sr_iov_1_1 = true; 3915 i40e_debug(hw, I40E_DEBUG_INIT, 3916 "HW Capability: SR-IOV = %d\n", 3917 p->sr_iov_1_1); 3918 break; 3919 case I40E_AQ_CAP_ID_VF: 3920 p->num_vfs = number; 3921 p->vf_base_id = logical_id; 3922 i40e_debug(hw, I40E_DEBUG_INIT, 3923 "HW Capability: VF count = %d\n", 3924 p->num_vfs); 3925 i40e_debug(hw, I40E_DEBUG_INIT, 3926 "HW Capability: VF base_id = %d\n", 3927 p->vf_base_id); 3928 break; 3929 case I40E_AQ_CAP_ID_VMDQ: 3930 if (number == 1) 3931 p->vmdq = true; 3932 i40e_debug(hw, I40E_DEBUG_INIT, 3933 "HW Capability: VMDQ = %d\n", p->vmdq); 3934 break; 3935 case I40E_AQ_CAP_ID_8021QBG: 3936 if (number == 1) 3937 p->evb_802_1_qbg = true; 3938 i40e_debug(hw, I40E_DEBUG_INIT, 3939 "HW Capability: 802.1Qbg = %d\n", number); 3940 break; 3941 case I40E_AQ_CAP_ID_8021QBR: 3942 if (number == 1) 3943 p->evb_802_1_qbh = true; 3944 i40e_debug(hw, I40E_DEBUG_INIT, 3945 "HW Capability: 802.1Qbh = %d\n", number); 3946 break; 3947 case I40E_AQ_CAP_ID_VSI: 3948 p->num_vsis = number; 3949 i40e_debug(hw, I40E_DEBUG_INIT, 3950 "HW Capability: VSI count = %d\n", 3951 p->num_vsis); 3952 break; 3953 case I40E_AQ_CAP_ID_DCB: 3954 if (number == 1) { 3955 p->dcb = true; 3956 p->enabled_tcmap = logical_id; 3957 p->maxtc = phys_id; 3958 } 3959 i40e_debug(hw, I40E_DEBUG_INIT, 3960 "HW Capability: DCB = %d\n", p->dcb); 3961 i40e_debug(hw, I40E_DEBUG_INIT, 3962 "HW Capability: TC Mapping = %d\n", 3963 logical_id); 3964 i40e_debug(hw, I40E_DEBUG_INIT, 3965 "HW Capability: TC Max = %d\n", p->maxtc); 3966 break; 3967 case I40E_AQ_CAP_ID_FCOE: 3968 if (number == 1) 3969 p->fcoe = true; 3970 i40e_debug(hw, I40E_DEBUG_INIT, 3971 "HW Capability: FCOE = %d\n", p->fcoe); 3972 break; 3973 case I40E_AQ_CAP_ID_ISCSI: 3974 if (number == 1) 3975 p->iscsi = true; 3976 i40e_debug(hw, I40E_DEBUG_INIT, 3977 "HW Capability: iSCSI = %d\n", p->iscsi); 3978 break; 3979 case I40E_AQ_CAP_ID_RSS: 3980 p->rss = true; 3981 p->rss_table_size = number; 3982 p->rss_table_entry_width = logical_id; 3983 i40e_debug(hw, I40E_DEBUG_INIT, 3984 "HW Capability: RSS = %d\n", p->rss); 3985 i40e_debug(hw, I40E_DEBUG_INIT, 3986 "HW Capability: RSS table size = %d\n", 3987 p->rss_table_size); 3988 i40e_debug(hw, I40E_DEBUG_INIT, 3989 "HW Capability: RSS table width = %d\n", 3990 p->rss_table_entry_width); 3991 break; 3992 case I40E_AQ_CAP_ID_RXQ: 3993 p->num_rx_qp = number; 3994 p->base_queue = phys_id; 3995 i40e_debug(hw, I40E_DEBUG_INIT, 3996 "HW Capability: Rx QP = %d\n", number); 3997 i40e_debug(hw, I40E_DEBUG_INIT, 3998 "HW Capability: base_queue = %d\n", 3999 p->base_queue); 4000 break; 4001 case I40E_AQ_CAP_ID_TXQ: 4002 p->num_tx_qp = number; 4003 p->base_queue = phys_id; 4004 i40e_debug(hw, I40E_DEBUG_INIT, 4005 "HW Capability: Tx QP = %d\n", number); 4006 i40e_debug(hw, I40E_DEBUG_INIT, 4007 "HW Capability: base_queue = %d\n", 4008 p->base_queue); 4009 break; 4010 case I40E_AQ_CAP_ID_MSIX: 4011 p->num_msix_vectors = number; 4012 i40e_debug(hw, I40E_DEBUG_INIT, 4013 "HW Capability: MSIX vector count = %d\n", 4014 p->num_msix_vectors); 4015 break; 4016 case I40E_AQ_CAP_ID_VF_MSIX: 4017 p->num_msix_vectors_vf = number; 4018 i40e_debug(hw, I40E_DEBUG_INIT, 4019 "HW Capability: MSIX VF vector count = %d\n", 4020 p->num_msix_vectors_vf); 4021 break; 4022 case I40E_AQ_CAP_ID_FLEX10: 4023 if (major_rev == 1) { 4024 if (number == 1) { 4025 p->flex10_enable = true; 4026 p->flex10_capable = true; 4027 } 4028 } else { 4029 /* Capability revision >= 2 */ 4030 if (number & 1) 4031 p->flex10_enable = true; 4032 if (number & 2) 4033 p->flex10_capable = true; 4034 } 4035 p->flex10_mode = logical_id; 4036 p->flex10_status = phys_id; 4037 i40e_debug(hw, I40E_DEBUG_INIT, 4038 "HW Capability: Flex10 mode = %d\n", 4039 p->flex10_mode); 4040 i40e_debug(hw, I40E_DEBUG_INIT, 4041 "HW Capability: Flex10 status = %d\n", 4042 p->flex10_status); 4043 break; 4044 case I40E_AQ_CAP_ID_CEM: 4045 if (number == 1) 4046 p->mgmt_cem = true; 4047 i40e_debug(hw, I40E_DEBUG_INIT, 4048 "HW Capability: CEM = %d\n", p->mgmt_cem); 4049 break; 4050 case I40E_AQ_CAP_ID_IWARP: 4051 if (number == 1) 4052 p->iwarp = true; 4053 i40e_debug(hw, I40E_DEBUG_INIT, 4054 "HW Capability: iWARP = %d\n", p->iwarp); 4055 break; 4056 case I40E_AQ_CAP_ID_LED: 4057 if (phys_id < I40E_HW_CAP_MAX_GPIO) 4058 p->led[phys_id] = true; 4059 i40e_debug(hw, I40E_DEBUG_INIT, 4060 "HW Capability: LED - PIN %d\n", phys_id); 4061 break; 4062 case I40E_AQ_CAP_ID_SDP: 4063 if (phys_id < I40E_HW_CAP_MAX_GPIO) 4064 p->sdp[phys_id] = true; 4065 i40e_debug(hw, I40E_DEBUG_INIT, 4066 "HW Capability: SDP - PIN %d\n", phys_id); 4067 break; 4068 case I40E_AQ_CAP_ID_MDIO: 4069 if (number == 1) { 4070 p->mdio_port_num = phys_id; 4071 p->mdio_port_mode = logical_id; 4072 } 4073 i40e_debug(hw, I40E_DEBUG_INIT, 4074 "HW Capability: MDIO port number = %d\n", 4075 p->mdio_port_num); 4076 i40e_debug(hw, I40E_DEBUG_INIT, 4077 "HW Capability: MDIO port mode = %d\n", 4078 p->mdio_port_mode); 4079 break; 4080 case I40E_AQ_CAP_ID_1588: 4081 if (number == 1) 4082 p->ieee_1588 = true; 4083 i40e_debug(hw, I40E_DEBUG_INIT, 4084 "HW Capability: IEEE 1588 = %d\n", 4085 p->ieee_1588); 4086 break; 4087 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 4088 p->fd = true; 4089 p->fd_filters_guaranteed = number; 4090 p->fd_filters_best_effort = logical_id; 4091 i40e_debug(hw, I40E_DEBUG_INIT, 4092 "HW Capability: Flow Director = 1\n"); 4093 i40e_debug(hw, I40E_DEBUG_INIT, 4094 "HW Capability: Guaranteed FD filters = %d\n", 4095 p->fd_filters_guaranteed); 4096 break; 4097 case I40E_AQ_CAP_ID_WSR_PROT: 4098 p->wr_csr_prot = (u64)number; 4099 p->wr_csr_prot |= (u64)logical_id << 32; 4100 i40e_debug(hw, I40E_DEBUG_INIT, 4101 "HW Capability: wr_csr_prot = 0x%llX\n\n", 4102 (p->wr_csr_prot & 0xffff)); 4103 break; 4104 case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS: 4105 p->dis_unused_ports = (bool)number; 4106 i40e_debug(hw, I40E_DEBUG_INIT, 4107 "HW Capability: dis_unused_ports = %d\n\n", 4108 p->dis_unused_ports); 4109 break; 4110 case I40E_AQ_CAP_ID_NVM_MGMT: 4111 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 4112 p->sec_rev_disabled = true; 4113 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 4114 p->update_disabled = true; 4115 break; 4116 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 4117 hw->num_wol_proxy_filters = (u16)number; 4118 hw->wol_proxy_vsi_seid = (u16)logical_id; 4119 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 4120 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 4121 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 4122 else 4123 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 4124 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 4125 i40e_debug(hw, I40E_DEBUG_INIT, 4126 "HW Capability: WOL proxy filters = %d\n", 4127 hw->num_wol_proxy_filters); 4128 break; 4129 default: 4130 break; 4131 } 4132 } 4133 4134 if (p->fcoe) 4135 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 4136 4137 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 4138 p->fcoe = false; 4139 4140 /* count the enabled ports (aka the "not disabled" ports) */ 4141 hw->num_ports = 0; 4142 for (i = 0; i < 4; i++) { 4143 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 4144 u64 port_cfg = 0; 4145 4146 /* use AQ read to get the physical register offset instead 4147 * of the port relative offset 4148 */ 4149 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 4150 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 4151 hw->num_ports++; 4152 } 4153 4154 /* OCP cards case: if a mezz is removed the ethernet port is at 4155 * disabled state in PRTGEN_CNF register. Additional NVM read is 4156 * needed in order to check if we are dealing with OCP card. 4157 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 4158 * physical ports results in wrong partition id calculation and thus 4159 * not supporting WoL. 4160 */ 4161 if (hw->mac.type == I40E_MAC_X722) { 4162 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) { 4163 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 4164 2 * I40E_SR_OCP_CFG_WORD0, 4165 sizeof(ocp_cfg_word0), 4166 &ocp_cfg_word0, true, NULL); 4167 if (status == I40E_SUCCESS && 4168 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 4169 hw->num_ports = 4; 4170 i40e_release_nvm(hw); 4171 } 4172 } 4173 4174 valid_functions = p->valid_functions; 4175 num_functions = 0; 4176 while (valid_functions) { 4177 if (valid_functions & 1) 4178 num_functions++; 4179 valid_functions >>= 1; 4180 } 4181 4182 /* partition id is 1-based, and functions are evenly spread 4183 * across the ports as partitions 4184 */ 4185 if (hw->num_ports != 0) { 4186 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 4187 hw->num_partitions = num_functions / hw->num_ports; 4188 } 4189 4190 /* additional HW specific goodies that might 4191 * someday be HW version specific 4192 */ 4193 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 4194 } 4195 4196 /** 4197 * i40e_aq_discover_capabilities 4198 * @hw: pointer to the hw struct 4199 * @buff: a virtual buffer to hold the capabilities 4200 * @buff_size: Size of the virtual buffer 4201 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 4202 * @list_type_opc: capabilities type to discover - pass in the command opcode 4203 * @cmd_details: pointer to command details structure or NULL 4204 * 4205 * Get the device capabilities descriptions from the firmware 4206 **/ 4207 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 4208 void *buff, u16 buff_size, u16 *data_size, 4209 enum i40e_admin_queue_opc list_type_opc, 4210 struct i40e_asq_cmd_details *cmd_details) 4211 { 4212 struct i40e_aqc_list_capabilites *cmd; 4213 struct i40e_aq_desc desc; 4214 enum i40e_status_code status = I40E_SUCCESS; 4215 4216 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 4217 4218 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 4219 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 4220 status = I40E_ERR_PARAM; 4221 goto exit; 4222 } 4223 4224 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 4225 4226 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4227 if (buff_size > I40E_AQ_LARGE_BUF) 4228 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4229 4230 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4231 *data_size = LE16_TO_CPU(desc.datalen); 4232 4233 if (status) 4234 goto exit; 4235 4236 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 4237 list_type_opc); 4238 4239 exit: 4240 return status; 4241 } 4242 4243 /** 4244 * i40e_aq_update_nvm 4245 * @hw: pointer to the hw struct 4246 * @module_pointer: module pointer location in words from the NVM beginning 4247 * @offset: byte offset from the module beginning 4248 * @length: length of the section to be written (in bytes from the offset) 4249 * @data: command buffer (size [bytes] = length) 4250 * @last_command: tells if this is the last command in a series 4251 * @preservation_flags: Preservation mode flags 4252 * @cmd_details: pointer to command details structure or NULL 4253 * 4254 * Update the NVM using the admin queue commands 4255 **/ 4256 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 4257 u32 offset, u16 length, void *data, 4258 bool last_command, u8 preservation_flags, 4259 struct i40e_asq_cmd_details *cmd_details) 4260 { 4261 struct i40e_aq_desc desc; 4262 struct i40e_aqc_nvm_update *cmd = 4263 (struct i40e_aqc_nvm_update *)&desc.params.raw; 4264 enum i40e_status_code status; 4265 4266 DEBUGFUNC("i40e_aq_update_nvm"); 4267 4268 /* In offset the highest byte must be zeroed. */ 4269 if (offset & 0xFF000000) { 4270 status = I40E_ERR_PARAM; 4271 goto i40e_aq_update_nvm_exit; 4272 } 4273 4274 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4275 4276 /* If this is the last command in a series, set the proper flag. */ 4277 if (last_command) 4278 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 4279 if (hw->mac.type == I40E_MAC_X722) { 4280 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 4281 cmd->command_flags |= 4282 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 4283 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4284 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 4285 cmd->command_flags |= 4286 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 4287 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4288 } 4289 cmd->module_pointer = module_pointer; 4290 cmd->offset = CPU_TO_LE32(offset); 4291 cmd->length = CPU_TO_LE16(length); 4292 4293 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4294 if (length > I40E_AQ_LARGE_BUF) 4295 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4296 4297 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4298 4299 i40e_aq_update_nvm_exit: 4300 return status; 4301 } 4302 4303 /** 4304 * i40e_aq_rearrange_nvm 4305 * @hw: pointer to the hw struct 4306 * @rearrange_nvm: defines direction of rearrangement 4307 * @cmd_details: pointer to command details structure or NULL 4308 * 4309 * Rearrange NVM structure, available only for transition FW 4310 **/ 4311 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw, 4312 u8 rearrange_nvm, 4313 struct i40e_asq_cmd_details *cmd_details) 4314 { 4315 struct i40e_aqc_nvm_update *cmd; 4316 enum i40e_status_code status; 4317 struct i40e_aq_desc desc; 4318 4319 DEBUGFUNC("i40e_aq_rearrange_nvm"); 4320 4321 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw; 4322 4323 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4324 4325 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT | 4326 I40E_AQ_NVM_REARRANGE_TO_STRUCT); 4327 4328 if (!rearrange_nvm) { 4329 status = I40E_ERR_PARAM; 4330 goto i40e_aq_rearrange_nvm_exit; 4331 } 4332 4333 cmd->command_flags |= rearrange_nvm; 4334 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4335 4336 i40e_aq_rearrange_nvm_exit: 4337 return status; 4338 } 4339 4340 /** 4341 * i40e_aq_get_lldp_mib 4342 * @hw: pointer to the hw struct 4343 * @bridge_type: type of bridge requested 4344 * @mib_type: Local, Remote or both Local and Remote MIBs 4345 * @buff: pointer to a user supplied buffer to store the MIB block 4346 * @buff_size: size of the buffer (in bytes) 4347 * @local_len : length of the returned Local LLDP MIB 4348 * @remote_len: length of the returned Remote LLDP MIB 4349 * @cmd_details: pointer to command details structure or NULL 4350 * 4351 * Requests the complete LLDP MIB (entire packet). 4352 **/ 4353 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4354 u8 mib_type, void *buff, u16 buff_size, 4355 u16 *local_len, u16 *remote_len, 4356 struct i40e_asq_cmd_details *cmd_details) 4357 { 4358 struct i40e_aq_desc desc; 4359 struct i40e_aqc_lldp_get_mib *cmd = 4360 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4361 struct i40e_aqc_lldp_get_mib *resp = 4362 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4363 enum i40e_status_code status; 4364 4365 if (buff_size == 0 || !buff) 4366 return I40E_ERR_PARAM; 4367 4368 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4369 /* Indirect Command */ 4370 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4371 4372 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4373 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4374 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4375 4376 desc.datalen = CPU_TO_LE16(buff_size); 4377 4378 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4379 if (buff_size > I40E_AQ_LARGE_BUF) 4380 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4381 4382 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4383 if (!status) { 4384 if (local_len != NULL) 4385 *local_len = LE16_TO_CPU(resp->local_len); 4386 if (remote_len != NULL) 4387 *remote_len = LE16_TO_CPU(resp->remote_len); 4388 } 4389 4390 return status; 4391 } 4392 4393 /** 4394 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4395 * @hw: pointer to the hw struct 4396 * @mib_type: Local, Remote or both Local and Remote MIBs 4397 * @buff: pointer to a user supplied buffer to store the MIB block 4398 * @buff_size: size of the buffer (in bytes) 4399 * @cmd_details: pointer to command details structure or NULL 4400 * 4401 * Set the LLDP MIB. 4402 **/ 4403 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4404 u8 mib_type, void *buff, u16 buff_size, 4405 struct i40e_asq_cmd_details *cmd_details) 4406 { 4407 struct i40e_aq_desc desc; 4408 struct i40e_aqc_lldp_set_local_mib *cmd = 4409 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4410 enum i40e_status_code status; 4411 4412 if (buff_size == 0 || !buff) 4413 return I40E_ERR_PARAM; 4414 4415 i40e_fill_default_direct_cmd_desc(&desc, 4416 i40e_aqc_opc_lldp_set_local_mib); 4417 /* Indirect Command */ 4418 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4419 if (buff_size > I40E_AQ_LARGE_BUF) 4420 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4421 desc.datalen = CPU_TO_LE16(buff_size); 4422 4423 cmd->type = mib_type; 4424 cmd->length = CPU_TO_LE16(buff_size); 4425 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff)); 4426 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 4427 4428 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4429 return status; 4430 } 4431 4432 /** 4433 * i40e_aq_cfg_lldp_mib_change_event 4434 * @hw: pointer to the hw struct 4435 * @enable_update: Enable or Disable event posting 4436 * @cmd_details: pointer to command details structure or NULL 4437 * 4438 * Enable or Disable posting of an event on ARQ when LLDP MIB 4439 * associated with the interface changes 4440 **/ 4441 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4442 bool enable_update, 4443 struct i40e_asq_cmd_details *cmd_details) 4444 { 4445 struct i40e_aq_desc desc; 4446 struct i40e_aqc_lldp_update_mib *cmd = 4447 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4448 enum i40e_status_code status; 4449 4450 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4451 4452 if (!enable_update) 4453 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4454 4455 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4456 4457 return status; 4458 } 4459 4460 /** 4461 * i40e_aq_restore_lldp 4462 * @hw: pointer to the hw struct 4463 * @setting: pointer to factory setting variable or NULL 4464 * @restore: True if factory settings should be restored 4465 * @cmd_details: pointer to command details structure or NULL 4466 * 4467 * Restore LLDP Agent factory settings if @restore set to True. In other case 4468 * only returns factory setting in AQ response. 4469 **/ 4470 enum i40e_status_code 4471 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore, 4472 struct i40e_asq_cmd_details *cmd_details) 4473 { 4474 struct i40e_aq_desc desc; 4475 struct i40e_aqc_lldp_restore *cmd = 4476 (struct i40e_aqc_lldp_restore *)&desc.params.raw; 4477 enum i40e_status_code status; 4478 4479 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) { 4480 i40e_debug(hw, I40E_DEBUG_ALL, 4481 "Restore LLDP not supported by current FW version.\n"); 4482 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4483 } 4484 4485 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore); 4486 4487 if (restore) 4488 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE; 4489 4490 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4491 4492 if (setting) 4493 *setting = cmd->command & 1; 4494 4495 return status; 4496 } 4497 4498 /** 4499 * i40e_aq_stop_lldp 4500 * @hw: pointer to the hw struct 4501 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4502 * @persist: True if stop of LLDP should be persistent across power cycles 4503 * @cmd_details: pointer to command details structure or NULL 4504 * 4505 * Stop or Shutdown the embedded LLDP Agent 4506 **/ 4507 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4508 bool persist, 4509 struct i40e_asq_cmd_details *cmd_details) 4510 { 4511 struct i40e_aq_desc desc; 4512 struct i40e_aqc_lldp_stop *cmd = 4513 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4514 enum i40e_status_code status; 4515 4516 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4517 4518 if (shutdown_agent) 4519 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4520 4521 if (persist) { 4522 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 4523 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 4524 else 4525 i40e_debug(hw, I40E_DEBUG_ALL, 4526 "Persistent Stop LLDP not supported by current FW version.\n"); 4527 } 4528 4529 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4530 4531 return status; 4532 } 4533 4534 /** 4535 * i40e_aq_start_lldp 4536 * @hw: pointer to the hw struct 4537 * @persist: True if start of LLDP should be persistent across power cycles 4538 * @cmd_details: pointer to command details structure or NULL 4539 * 4540 * Start the embedded LLDP Agent on all ports. 4541 **/ 4542 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4543 bool persist, 4544 struct i40e_asq_cmd_details *cmd_details) 4545 { 4546 struct i40e_aq_desc desc; 4547 struct i40e_aqc_lldp_start *cmd = 4548 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4549 enum i40e_status_code status; 4550 4551 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4552 4553 cmd->command = I40E_AQ_LLDP_AGENT_START; 4554 4555 if (persist) { 4556 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 4557 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 4558 else 4559 i40e_debug(hw, I40E_DEBUG_ALL, 4560 "Persistent Start LLDP not supported by current FW version.\n"); 4561 } 4562 4563 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4564 4565 return status; 4566 } 4567 4568 /** 4569 * i40e_aq_set_dcb_parameters 4570 * @hw: pointer to the hw struct 4571 * @cmd_details: pointer to command details structure or NULL 4572 * @dcb_enable: True if DCB configuration needs to be applied 4573 * 4574 **/ 4575 enum i40e_status_code 4576 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 4577 struct i40e_asq_cmd_details *cmd_details) 4578 { 4579 struct i40e_aq_desc desc; 4580 struct i40e_aqc_set_dcb_parameters *cmd = 4581 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 4582 enum i40e_status_code status; 4583 4584 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) 4585 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4586 4587 i40e_fill_default_direct_cmd_desc(&desc, 4588 i40e_aqc_opc_set_dcb_parameters); 4589 4590 if (dcb_enable) { 4591 cmd->valid_flags = I40E_DCB_VALID; 4592 cmd->command = I40E_AQ_DCB_SET_AGENT; 4593 } 4594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4595 4596 return status; 4597 } 4598 4599 /** 4600 * i40e_aq_get_cee_dcb_config 4601 * @hw: pointer to the hw struct 4602 * @buff: response buffer that stores CEE operational configuration 4603 * @buff_size: size of the buffer passed 4604 * @cmd_details: pointer to command details structure or NULL 4605 * 4606 * Get CEE DCBX mode operational configuration from firmware 4607 **/ 4608 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4609 void *buff, u16 buff_size, 4610 struct i40e_asq_cmd_details *cmd_details) 4611 { 4612 struct i40e_aq_desc desc; 4613 enum i40e_status_code status; 4614 4615 if (buff_size == 0 || !buff) 4616 return I40E_ERR_PARAM; 4617 4618 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4619 4620 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4621 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4622 cmd_details); 4623 4624 return status; 4625 } 4626 4627 /** 4628 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4629 * @hw: pointer to the hw struct 4630 * @start_agent: True if DCBx Agent needs to be Started 4631 * False if DCBx Agent needs to be Stopped 4632 * @cmd_details: pointer to command details structure or NULL 4633 * 4634 * Start/Stop the embedded dcbx Agent 4635 **/ 4636 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4637 bool start_agent, 4638 struct i40e_asq_cmd_details *cmd_details) 4639 { 4640 struct i40e_aq_desc desc; 4641 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4642 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4643 &desc.params.raw; 4644 enum i40e_status_code status; 4645 4646 i40e_fill_default_direct_cmd_desc(&desc, 4647 i40e_aqc_opc_lldp_stop_start_spec_agent); 4648 4649 if (start_agent) 4650 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4651 4652 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4653 4654 return status; 4655 } 4656 4657 /** 4658 * i40e_aq_add_udp_tunnel 4659 * @hw: pointer to the hw struct 4660 * @udp_port: the UDP port to add in Host byte order 4661 * @protocol_index: protocol index type 4662 * @filter_index: pointer to filter index 4663 * @cmd_details: pointer to command details structure or NULL 4664 * 4665 * Note: Firmware expects the udp_port value to be in Little Endian format, 4666 * and this function will call CPU_TO_LE16 to convert from Host byte order to 4667 * Little Endian order. 4668 **/ 4669 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4670 u16 udp_port, u8 protocol_index, 4671 u8 *filter_index, 4672 struct i40e_asq_cmd_details *cmd_details) 4673 { 4674 struct i40e_aq_desc desc; 4675 struct i40e_aqc_add_udp_tunnel *cmd = 4676 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4677 struct i40e_aqc_del_udp_tunnel_completion *resp = 4678 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4679 enum i40e_status_code status; 4680 4681 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4682 4683 cmd->udp_port = CPU_TO_LE16(udp_port); 4684 cmd->protocol_type = protocol_index; 4685 4686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4687 4688 if (!status && filter_index) 4689 *filter_index = resp->index; 4690 4691 return status; 4692 } 4693 4694 /** 4695 * i40e_aq_del_udp_tunnel 4696 * @hw: pointer to the hw struct 4697 * @index: filter index 4698 * @cmd_details: pointer to command details structure or NULL 4699 **/ 4700 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4701 struct i40e_asq_cmd_details *cmd_details) 4702 { 4703 struct i40e_aq_desc desc; 4704 struct i40e_aqc_remove_udp_tunnel *cmd = 4705 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4706 enum i40e_status_code status; 4707 4708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4709 4710 cmd->index = index; 4711 4712 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4713 4714 return status; 4715 } 4716 4717 /** 4718 * i40e_aq_get_switch_resource_alloc (0x0204) 4719 * @hw: pointer to the hw struct 4720 * @num_entries: pointer to u8 to store the number of resource entries returned 4721 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4722 * to store the resource information for all resource types. Each 4723 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4724 * @count: size, in bytes, of the buffer provided 4725 * @cmd_details: pointer to command details structure or NULL 4726 * 4727 * Query the resources allocated to a function. 4728 **/ 4729 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4730 u8 *num_entries, 4731 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4732 u16 count, 4733 struct i40e_asq_cmd_details *cmd_details) 4734 { 4735 struct i40e_aq_desc desc; 4736 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4737 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4738 enum i40e_status_code status; 4739 u16 length = count * sizeof(*buf); 4740 4741 i40e_fill_default_direct_cmd_desc(&desc, 4742 i40e_aqc_opc_get_switch_resource_alloc); 4743 4744 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4745 if (length > I40E_AQ_LARGE_BUF) 4746 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4747 4748 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4749 4750 if (!status && num_entries) 4751 *num_entries = cmd_resp->num_entries; 4752 4753 return status; 4754 } 4755 4756 /** 4757 * i40e_aq_delete_element - Delete switch element 4758 * @hw: pointer to the hw struct 4759 * @seid: the SEID to delete from the switch 4760 * @cmd_details: pointer to command details structure or NULL 4761 * 4762 * This deletes a switch element from the switch. 4763 **/ 4764 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4765 struct i40e_asq_cmd_details *cmd_details) 4766 { 4767 struct i40e_aq_desc desc; 4768 struct i40e_aqc_switch_seid *cmd = 4769 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4770 enum i40e_status_code status; 4771 4772 if (seid == 0) 4773 return I40E_ERR_PARAM; 4774 4775 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4776 4777 cmd->seid = CPU_TO_LE16(seid); 4778 4779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4780 4781 return status; 4782 } 4783 4784 /** 4785 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4786 * @hw: pointer to the hw struct 4787 * @flags: component flags 4788 * @mac_seid: uplink seid (MAC SEID) 4789 * @vsi_seid: connected vsi seid 4790 * @ret_seid: seid of create pv component 4791 * 4792 * This instantiates an i40e port virtualizer with specified flags. 4793 * Depending on specified flags the port virtualizer can act as a 4794 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4795 */ 4796 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4797 u16 mac_seid, u16 vsi_seid, 4798 u16 *ret_seid) 4799 { 4800 struct i40e_aq_desc desc; 4801 struct i40e_aqc_add_update_pv *cmd = 4802 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4803 struct i40e_aqc_add_update_pv_completion *resp = 4804 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4805 enum i40e_status_code status; 4806 4807 if (vsi_seid == 0) 4808 return I40E_ERR_PARAM; 4809 4810 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4811 cmd->command_flags = CPU_TO_LE16(flags); 4812 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4813 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4814 4815 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4816 if (!status && ret_seid) 4817 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4818 4819 return status; 4820 } 4821 4822 /** 4823 * i40e_aq_add_tag - Add an S/E-tag 4824 * @hw: pointer to the hw struct 4825 * @direct_to_queue: should s-tag direct flow to a specific queue 4826 * @vsi_seid: VSI SEID to use this tag 4827 * @tag: value of the tag 4828 * @queue_num: queue number, only valid is direct_to_queue is true 4829 * @tags_used: return value, number of tags in use by this PF 4830 * @tags_free: return value, number of unallocated tags 4831 * @cmd_details: pointer to command details structure or NULL 4832 * 4833 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4834 * the number of tags allocated by the PF, and the number of unallocated 4835 * tags available. 4836 **/ 4837 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4838 u16 vsi_seid, u16 tag, u16 queue_num, 4839 u16 *tags_used, u16 *tags_free, 4840 struct i40e_asq_cmd_details *cmd_details) 4841 { 4842 struct i40e_aq_desc desc; 4843 struct i40e_aqc_add_tag *cmd = 4844 (struct i40e_aqc_add_tag *)&desc.params.raw; 4845 struct i40e_aqc_add_remove_tag_completion *resp = 4846 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4847 enum i40e_status_code status; 4848 4849 if (vsi_seid == 0) 4850 return I40E_ERR_PARAM; 4851 4852 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4853 4854 cmd->seid = CPU_TO_LE16(vsi_seid); 4855 cmd->tag = CPU_TO_LE16(tag); 4856 if (direct_to_queue) { 4857 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4858 cmd->queue_number = CPU_TO_LE16(queue_num); 4859 } 4860 4861 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4862 4863 if (!status) { 4864 if (tags_used != NULL) 4865 *tags_used = LE16_TO_CPU(resp->tags_used); 4866 if (tags_free != NULL) 4867 *tags_free = LE16_TO_CPU(resp->tags_free); 4868 } 4869 4870 return status; 4871 } 4872 4873 /** 4874 * i40e_aq_remove_tag - Remove an S- or E-tag 4875 * @hw: pointer to the hw struct 4876 * @vsi_seid: VSI SEID this tag is associated with 4877 * @tag: value of the S-tag to delete 4878 * @tags_used: return value, number of tags in use by this PF 4879 * @tags_free: return value, number of unallocated tags 4880 * @cmd_details: pointer to command details structure or NULL 4881 * 4882 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4883 * the number of tags allocated by the PF, and the number of unallocated 4884 * tags available. 4885 **/ 4886 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4887 u16 tag, u16 *tags_used, u16 *tags_free, 4888 struct i40e_asq_cmd_details *cmd_details) 4889 { 4890 struct i40e_aq_desc desc; 4891 struct i40e_aqc_remove_tag *cmd = 4892 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4893 struct i40e_aqc_add_remove_tag_completion *resp = 4894 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4895 enum i40e_status_code status; 4896 4897 if (vsi_seid == 0) 4898 return I40E_ERR_PARAM; 4899 4900 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4901 4902 cmd->seid = CPU_TO_LE16(vsi_seid); 4903 cmd->tag = CPU_TO_LE16(tag); 4904 4905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4906 4907 if (!status) { 4908 if (tags_used != NULL) 4909 *tags_used = LE16_TO_CPU(resp->tags_used); 4910 if (tags_free != NULL) 4911 *tags_free = LE16_TO_CPU(resp->tags_free); 4912 } 4913 4914 return status; 4915 } 4916 4917 /** 4918 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4919 * @hw: pointer to the hw struct 4920 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4921 * @etag: value of E-tag to add 4922 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4923 * @buf: address of indirect buffer 4924 * @tags_used: return value, number of E-tags in use by this port 4925 * @tags_free: return value, number of unallocated M-tags 4926 * @cmd_details: pointer to command details structure or NULL 4927 * 4928 * This associates a multicast E-tag to a port virtualizer. It will return 4929 * the number of tags allocated by the PF, and the number of unallocated 4930 * tags available. 4931 * 4932 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4933 * num_tags_in_buf long. 4934 **/ 4935 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4936 u16 etag, u8 num_tags_in_buf, void *buf, 4937 u16 *tags_used, u16 *tags_free, 4938 struct i40e_asq_cmd_details *cmd_details) 4939 { 4940 struct i40e_aq_desc desc; 4941 struct i40e_aqc_add_remove_mcast_etag *cmd = 4942 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4943 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4944 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4945 enum i40e_status_code status; 4946 u16 length = sizeof(u16) * num_tags_in_buf; 4947 4948 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4949 return I40E_ERR_PARAM; 4950 4951 i40e_fill_default_direct_cmd_desc(&desc, 4952 i40e_aqc_opc_add_multicast_etag); 4953 4954 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4955 cmd->etag = CPU_TO_LE16(etag); 4956 cmd->num_unicast_etags = num_tags_in_buf; 4957 4958 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4959 4960 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4961 4962 if (!status) { 4963 if (tags_used != NULL) 4964 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4965 if (tags_free != NULL) 4966 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4967 } 4968 4969 return status; 4970 } 4971 4972 /** 4973 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4974 * @hw: pointer to the hw struct 4975 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4976 * @etag: value of the E-tag to remove 4977 * @tags_used: return value, number of tags in use by this port 4978 * @tags_free: return value, number of unallocated tags 4979 * @cmd_details: pointer to command details structure or NULL 4980 * 4981 * This deletes an E-tag from the port virtualizer. It will return 4982 * the number of tags allocated by the port, and the number of unallocated 4983 * tags available. 4984 **/ 4985 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4986 u16 etag, u16 *tags_used, u16 *tags_free, 4987 struct i40e_asq_cmd_details *cmd_details) 4988 { 4989 struct i40e_aq_desc desc; 4990 struct i40e_aqc_add_remove_mcast_etag *cmd = 4991 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4992 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4993 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4994 enum i40e_status_code status; 4995 4996 4997 if (pv_seid == 0) 4998 return I40E_ERR_PARAM; 4999 5000 i40e_fill_default_direct_cmd_desc(&desc, 5001 i40e_aqc_opc_remove_multicast_etag); 5002 5003 cmd->pv_seid = CPU_TO_LE16(pv_seid); 5004 cmd->etag = CPU_TO_LE16(etag); 5005 5006 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5007 5008 if (!status) { 5009 if (tags_used != NULL) 5010 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 5011 if (tags_free != NULL) 5012 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 5013 } 5014 5015 return status; 5016 } 5017 5018 /** 5019 * i40e_aq_update_tag - Update an S/E-tag 5020 * @hw: pointer to the hw struct 5021 * @vsi_seid: VSI SEID using this S-tag 5022 * @old_tag: old tag value 5023 * @new_tag: new tag value 5024 * @tags_used: return value, number of tags in use by this PF 5025 * @tags_free: return value, number of unallocated tags 5026 * @cmd_details: pointer to command details structure or NULL 5027 * 5028 * This updates the value of the tag currently attached to this VSI 5029 * in the switch complex. It will return the number of tags allocated 5030 * by the PF, and the number of unallocated tags available. 5031 **/ 5032 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 5033 u16 old_tag, u16 new_tag, u16 *tags_used, 5034 u16 *tags_free, 5035 struct i40e_asq_cmd_details *cmd_details) 5036 { 5037 struct i40e_aq_desc desc; 5038 struct i40e_aqc_update_tag *cmd = 5039 (struct i40e_aqc_update_tag *)&desc.params.raw; 5040 struct i40e_aqc_update_tag_completion *resp = 5041 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 5042 enum i40e_status_code status; 5043 5044 if (vsi_seid == 0) 5045 return I40E_ERR_PARAM; 5046 5047 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 5048 5049 cmd->seid = CPU_TO_LE16(vsi_seid); 5050 cmd->old_tag = CPU_TO_LE16(old_tag); 5051 cmd->new_tag = CPU_TO_LE16(new_tag); 5052 5053 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5054 5055 if (!status) { 5056 if (tags_used != NULL) 5057 *tags_used = LE16_TO_CPU(resp->tags_used); 5058 if (tags_free != NULL) 5059 *tags_free = LE16_TO_CPU(resp->tags_free); 5060 } 5061 5062 return status; 5063 } 5064 5065 /** 5066 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 5067 * @hw: pointer to the hw struct 5068 * @tcmap: TC map for request/release any ignore PFC condition 5069 * @request: request or release ignore PFC condition 5070 * @tcmap_ret: return TCs for which PFC is currently ignored 5071 * @cmd_details: pointer to command details structure or NULL 5072 * 5073 * This sends out request/release to ignore PFC condition for a TC. 5074 * It will return the TCs for which PFC is currently ignored. 5075 **/ 5076 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 5077 bool request, u8 *tcmap_ret, 5078 struct i40e_asq_cmd_details *cmd_details) 5079 { 5080 struct i40e_aq_desc desc; 5081 struct i40e_aqc_pfc_ignore *cmd_resp = 5082 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 5083 enum i40e_status_code status; 5084 5085 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 5086 5087 if (request) 5088 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 5089 5090 cmd_resp->tc_bitmap = tcmap; 5091 5092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5093 5094 if (!status) { 5095 if (tcmap_ret != NULL) 5096 *tcmap_ret = cmd_resp->tc_bitmap; 5097 } 5098 5099 return status; 5100 } 5101 5102 /** 5103 * i40e_aq_dcb_updated - DCB Updated Command 5104 * @hw: pointer to the hw struct 5105 * @cmd_details: pointer to command details structure or NULL 5106 * 5107 * When LLDP is handled in PF this command is used by the PF 5108 * to notify EMP that a DCB setting is modified. 5109 * When LLDP is handled in EMP this command is used by the PF 5110 * to notify EMP whenever one of the following parameters get 5111 * modified: 5112 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 5113 * - PCIRTT in PRTDCB_GENC.PCIRTT 5114 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 5115 * EMP will return when the shared RPB settings have been 5116 * recomputed and modified. The retval field in the descriptor 5117 * will be set to 0 when RPB is modified. 5118 **/ 5119 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 5120 struct i40e_asq_cmd_details *cmd_details) 5121 { 5122 struct i40e_aq_desc desc; 5123 enum i40e_status_code status; 5124 5125 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 5126 5127 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5128 5129 return status; 5130 } 5131 5132 /** 5133 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 5134 * @hw: pointer to the hw struct 5135 * @seid: defines the SEID of the switch for which the stats are requested 5136 * @vlan_id: the VLAN ID for which the statistics are requested 5137 * @stat_index: index of the statistics counters block assigned to this VLAN 5138 * @cmd_details: pointer to command details structure or NULL 5139 * 5140 * XL710 supports 128 smonVlanStats counters.This command is used to 5141 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 5142 * switch. 5143 **/ 5144 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 5145 u16 vlan_id, u16 *stat_index, 5146 struct i40e_asq_cmd_details *cmd_details) 5147 { 5148 struct i40e_aq_desc desc; 5149 struct i40e_aqc_add_remove_statistics *cmd_resp = 5150 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5151 enum i40e_status_code status; 5152 5153 if ((seid == 0) || (stat_index == NULL)) 5154 return I40E_ERR_PARAM; 5155 5156 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 5157 5158 cmd_resp->seid = CPU_TO_LE16(seid); 5159 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 5160 5161 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5162 5163 if (!status && stat_index) 5164 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 5165 5166 return status; 5167 } 5168 5169 /** 5170 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 5171 * @hw: pointer to the hw struct 5172 * @seid: defines the SEID of the switch for which the stats are requested 5173 * @vlan_id: the VLAN ID for which the statistics are requested 5174 * @stat_index: index of the statistics counters block assigned to this VLAN 5175 * @cmd_details: pointer to command details structure or NULL 5176 * 5177 * XL710 supports 128 smonVlanStats counters.This command is used to 5178 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 5179 * switch. 5180 **/ 5181 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 5182 u16 vlan_id, u16 stat_index, 5183 struct i40e_asq_cmd_details *cmd_details) 5184 { 5185 struct i40e_aq_desc desc; 5186 struct i40e_aqc_add_remove_statistics *cmd = 5187 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5188 enum i40e_status_code status; 5189 5190 if (seid == 0) 5191 return I40E_ERR_PARAM; 5192 5193 i40e_fill_default_direct_cmd_desc(&desc, 5194 i40e_aqc_opc_remove_statistics); 5195 5196 cmd->seid = CPU_TO_LE16(seid); 5197 cmd->vlan = CPU_TO_LE16(vlan_id); 5198 cmd->stat_index = CPU_TO_LE16(stat_index); 5199 5200 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5201 5202 return status; 5203 } 5204 5205 /** 5206 * i40e_aq_set_port_parameters - set physical port parameters. 5207 * @hw: pointer to the hw struct 5208 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 5209 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 5210 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 5211 * @double_vlan: if set double VLAN is enabled 5212 * @cmd_details: pointer to command details structure or NULL 5213 **/ 5214 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 5215 u16 bad_frame_vsi, bool save_bad_pac, 5216 bool pad_short_pac, bool double_vlan, 5217 struct i40e_asq_cmd_details *cmd_details) 5218 { 5219 struct i40e_aqc_set_port_parameters *cmd; 5220 enum i40e_status_code status; 5221 struct i40e_aq_desc desc; 5222 u16 command_flags = 0; 5223 5224 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 5225 5226 i40e_fill_default_direct_cmd_desc(&desc, 5227 i40e_aqc_opc_set_port_parameters); 5228 5229 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 5230 if (save_bad_pac) 5231 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 5232 if (pad_short_pac) 5233 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 5234 if (double_vlan) 5235 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 5236 cmd->command_flags = CPU_TO_LE16(command_flags); 5237 5238 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5239 5240 return status; 5241 } 5242 5243 /** 5244 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 5245 * @hw: pointer to the hw struct 5246 * @seid: seid for the physical port/switching component/vsi 5247 * @buff: Indirect buffer to hold data parameters and response 5248 * @buff_size: Indirect buffer size 5249 * @opcode: Tx scheduler AQ command opcode 5250 * @cmd_details: pointer to command details structure or NULL 5251 * 5252 * Generic command handler for Tx scheduler AQ commands 5253 **/ 5254 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 5255 void *buff, u16 buff_size, 5256 enum i40e_admin_queue_opc opcode, 5257 struct i40e_asq_cmd_details *cmd_details) 5258 { 5259 struct i40e_aq_desc desc; 5260 struct i40e_aqc_tx_sched_ind *cmd = 5261 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 5262 enum i40e_status_code status; 5263 bool cmd_param_flag = false; 5264 5265 switch (opcode) { 5266 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 5267 case i40e_aqc_opc_configure_vsi_tc_bw: 5268 case i40e_aqc_opc_enable_switching_comp_ets: 5269 case i40e_aqc_opc_modify_switching_comp_ets: 5270 case i40e_aqc_opc_disable_switching_comp_ets: 5271 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5272 case i40e_aqc_opc_configure_switching_comp_bw_config: 5273 cmd_param_flag = true; 5274 break; 5275 case i40e_aqc_opc_query_vsi_bw_config: 5276 case i40e_aqc_opc_query_vsi_ets_sla_config: 5277 case i40e_aqc_opc_query_switching_comp_ets_config: 5278 case i40e_aqc_opc_query_port_ets_config: 5279 case i40e_aqc_opc_query_switching_comp_bw_config: 5280 cmd_param_flag = false; 5281 break; 5282 default: 5283 return I40E_ERR_PARAM; 5284 } 5285 5286 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5287 5288 /* Indirect command */ 5289 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5290 if (cmd_param_flag) 5291 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5292 if (buff_size > I40E_AQ_LARGE_BUF) 5293 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5294 5295 desc.datalen = CPU_TO_LE16(buff_size); 5296 5297 cmd->vsi_seid = CPU_TO_LE16(seid); 5298 5299 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5300 5301 return status; 5302 } 5303 5304 /** 5305 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5306 * @hw: pointer to the hw struct 5307 * @seid: VSI seid 5308 * @credit: BW limit credits (0 = disabled) 5309 * @max_credit: Max BW limit credits 5310 * @cmd_details: pointer to command details structure or NULL 5311 **/ 5312 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5313 u16 seid, u16 credit, u8 max_credit, 5314 struct i40e_asq_cmd_details *cmd_details) 5315 { 5316 struct i40e_aq_desc desc; 5317 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5318 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5319 enum i40e_status_code status; 5320 5321 i40e_fill_default_direct_cmd_desc(&desc, 5322 i40e_aqc_opc_configure_vsi_bw_limit); 5323 5324 cmd->vsi_seid = CPU_TO_LE16(seid); 5325 cmd->credit = CPU_TO_LE16(credit); 5326 cmd->max_credit = max_credit; 5327 5328 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5329 5330 return status; 5331 } 5332 5333 /** 5334 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5335 * @hw: pointer to the hw struct 5336 * @seid: switching component seid 5337 * @credit: BW limit credits (0 = disabled) 5338 * @max_bw: Max BW limit credits 5339 * @cmd_details: pointer to command details structure or NULL 5340 **/ 5341 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5342 u16 seid, u16 credit, u8 max_bw, 5343 struct i40e_asq_cmd_details *cmd_details) 5344 { 5345 struct i40e_aq_desc desc; 5346 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5347 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5348 enum i40e_status_code status; 5349 5350 i40e_fill_default_direct_cmd_desc(&desc, 5351 i40e_aqc_opc_configure_switching_comp_bw_limit); 5352 5353 cmd->seid = CPU_TO_LE16(seid); 5354 cmd->credit = CPU_TO_LE16(credit); 5355 cmd->max_bw = max_bw; 5356 5357 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5358 5359 return status; 5360 } 5361 5362 /** 5363 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5364 * @hw: pointer to the hw struct 5365 * @seid: VSI seid 5366 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5367 * @cmd_details: pointer to command details structure or NULL 5368 **/ 5369 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5370 u16 seid, 5371 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5372 struct i40e_asq_cmd_details *cmd_details) 5373 { 5374 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5375 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5376 cmd_details); 5377 } 5378 5379 /** 5380 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5381 * @hw: pointer to the hw struct 5382 * @seid: VSI seid 5383 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5384 * @cmd_details: pointer to command details structure or NULL 5385 **/ 5386 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5387 u16 seid, 5388 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5389 struct i40e_asq_cmd_details *cmd_details) 5390 { 5391 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5392 i40e_aqc_opc_configure_vsi_tc_bw, 5393 cmd_details); 5394 } 5395 5396 /** 5397 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 5398 * @hw: pointer to the hw struct 5399 * @seid: seid of the switching component connected to Physical Port 5400 * @ets_data: Buffer holding ETS parameters 5401 * @opcode: Tx scheduler AQ command opcode 5402 * @cmd_details: pointer to command details structure or NULL 5403 **/ 5404 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 5405 u16 seid, 5406 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 5407 enum i40e_admin_queue_opc opcode, 5408 struct i40e_asq_cmd_details *cmd_details) 5409 { 5410 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 5411 sizeof(*ets_data), opcode, cmd_details); 5412 } 5413 5414 /** 5415 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 5416 * @hw: pointer to the hw struct 5417 * @seid: seid of the switching component 5418 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 5419 * @cmd_details: pointer to command details structure or NULL 5420 **/ 5421 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 5422 u16 seid, 5423 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 5424 struct i40e_asq_cmd_details *cmd_details) 5425 { 5426 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5427 i40e_aqc_opc_configure_switching_comp_bw_config, 5428 cmd_details); 5429 } 5430 5431 /** 5432 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5433 * @hw: pointer to the hw struct 5434 * @seid: seid of the switching component 5435 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5436 * @cmd_details: pointer to command details structure or NULL 5437 **/ 5438 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5439 struct i40e_hw *hw, u16 seid, 5440 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5441 struct i40e_asq_cmd_details *cmd_details) 5442 { 5443 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5444 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5445 cmd_details); 5446 } 5447 5448 /** 5449 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5450 * @hw: pointer to the hw struct 5451 * @seid: seid of the VSI 5452 * @bw_data: Buffer to hold VSI BW configuration 5453 * @cmd_details: pointer to command details structure or NULL 5454 **/ 5455 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5456 u16 seid, 5457 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5458 struct i40e_asq_cmd_details *cmd_details) 5459 { 5460 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5461 i40e_aqc_opc_query_vsi_bw_config, 5462 cmd_details); 5463 } 5464 5465 /** 5466 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5467 * @hw: pointer to the hw struct 5468 * @seid: seid of the VSI 5469 * @bw_data: Buffer to hold VSI BW configuration per TC 5470 * @cmd_details: pointer to command details structure or NULL 5471 **/ 5472 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5473 u16 seid, 5474 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5475 struct i40e_asq_cmd_details *cmd_details) 5476 { 5477 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5478 i40e_aqc_opc_query_vsi_ets_sla_config, 5479 cmd_details); 5480 } 5481 5482 /** 5483 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5484 * @hw: pointer to the hw struct 5485 * @seid: seid of the switching component 5486 * @bw_data: Buffer to hold switching component's per TC BW config 5487 * @cmd_details: pointer to command details structure or NULL 5488 **/ 5489 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5490 u16 seid, 5491 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5492 struct i40e_asq_cmd_details *cmd_details) 5493 { 5494 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5495 i40e_aqc_opc_query_switching_comp_ets_config, 5496 cmd_details); 5497 } 5498 5499 /** 5500 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5501 * @hw: pointer to the hw struct 5502 * @seid: seid of the VSI or switching component connected to Physical Port 5503 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5504 * @cmd_details: pointer to command details structure or NULL 5505 **/ 5506 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5507 u16 seid, 5508 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5509 struct i40e_asq_cmd_details *cmd_details) 5510 { 5511 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5512 i40e_aqc_opc_query_port_ets_config, 5513 cmd_details); 5514 } 5515 5516 /** 5517 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5518 * @hw: pointer to the hw struct 5519 * @seid: seid of the switching component 5520 * @bw_data: Buffer to hold switching component's BW configuration 5521 * @cmd_details: pointer to command details structure or NULL 5522 **/ 5523 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5524 u16 seid, 5525 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5526 struct i40e_asq_cmd_details *cmd_details) 5527 { 5528 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5529 i40e_aqc_opc_query_switching_comp_bw_config, 5530 cmd_details); 5531 } 5532 5533 /** 5534 * i40e_validate_filter_settings 5535 * @hw: pointer to the hardware structure 5536 * @settings: Filter control settings 5537 * 5538 * Check and validate the filter control settings passed. 5539 * The function checks for the valid filter/context sizes being 5540 * passed for FCoE and PE. 5541 * 5542 * Returns I40E_SUCCESS if the values passed are valid and within 5543 * range else returns an error. 5544 **/ 5545 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5546 struct i40e_filter_control_settings *settings) 5547 { 5548 u32 fcoe_cntx_size, fcoe_filt_size; 5549 u32 pe_cntx_size, pe_filt_size; 5550 u32 fcoe_fmax; 5551 5552 u32 val; 5553 5554 /* Validate FCoE settings passed */ 5555 switch (settings->fcoe_filt_num) { 5556 case I40E_HASH_FILTER_SIZE_1K: 5557 case I40E_HASH_FILTER_SIZE_2K: 5558 case I40E_HASH_FILTER_SIZE_4K: 5559 case I40E_HASH_FILTER_SIZE_8K: 5560 case I40E_HASH_FILTER_SIZE_16K: 5561 case I40E_HASH_FILTER_SIZE_32K: 5562 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5563 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5564 break; 5565 default: 5566 return I40E_ERR_PARAM; 5567 } 5568 5569 switch (settings->fcoe_cntx_num) { 5570 case I40E_DMA_CNTX_SIZE_512: 5571 case I40E_DMA_CNTX_SIZE_1K: 5572 case I40E_DMA_CNTX_SIZE_2K: 5573 case I40E_DMA_CNTX_SIZE_4K: 5574 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5575 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5576 break; 5577 default: 5578 return I40E_ERR_PARAM; 5579 } 5580 5581 /* Validate PE settings passed */ 5582 switch (settings->pe_filt_num) { 5583 case I40E_HASH_FILTER_SIZE_1K: 5584 case I40E_HASH_FILTER_SIZE_2K: 5585 case I40E_HASH_FILTER_SIZE_4K: 5586 case I40E_HASH_FILTER_SIZE_8K: 5587 case I40E_HASH_FILTER_SIZE_16K: 5588 case I40E_HASH_FILTER_SIZE_32K: 5589 case I40E_HASH_FILTER_SIZE_64K: 5590 case I40E_HASH_FILTER_SIZE_128K: 5591 case I40E_HASH_FILTER_SIZE_256K: 5592 case I40E_HASH_FILTER_SIZE_512K: 5593 case I40E_HASH_FILTER_SIZE_1M: 5594 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5595 pe_filt_size <<= (u32)settings->pe_filt_num; 5596 break; 5597 default: 5598 return I40E_ERR_PARAM; 5599 } 5600 5601 switch (settings->pe_cntx_num) { 5602 case I40E_DMA_CNTX_SIZE_512: 5603 case I40E_DMA_CNTX_SIZE_1K: 5604 case I40E_DMA_CNTX_SIZE_2K: 5605 case I40E_DMA_CNTX_SIZE_4K: 5606 case I40E_DMA_CNTX_SIZE_8K: 5607 case I40E_DMA_CNTX_SIZE_16K: 5608 case I40E_DMA_CNTX_SIZE_32K: 5609 case I40E_DMA_CNTX_SIZE_64K: 5610 case I40E_DMA_CNTX_SIZE_128K: 5611 case I40E_DMA_CNTX_SIZE_256K: 5612 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5613 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5614 break; 5615 default: 5616 return I40E_ERR_PARAM; 5617 } 5618 5619 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5620 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5621 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5622 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5623 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5624 return I40E_ERR_INVALID_SIZE; 5625 5626 return I40E_SUCCESS; 5627 } 5628 5629 /** 5630 * i40e_set_filter_control 5631 * @hw: pointer to the hardware structure 5632 * @settings: Filter control settings 5633 * 5634 * Set the Queue Filters for PE/FCoE and enable filters required 5635 * for a single PF. It is expected that these settings are programmed 5636 * at the driver initialization time. 5637 **/ 5638 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5639 struct i40e_filter_control_settings *settings) 5640 { 5641 enum i40e_status_code ret = I40E_SUCCESS; 5642 u32 hash_lut_size = 0; 5643 u32 val; 5644 5645 if (!settings) 5646 return I40E_ERR_PARAM; 5647 5648 /* Validate the input settings */ 5649 ret = i40e_validate_filter_settings(hw, settings); 5650 if (ret) 5651 return ret; 5652 5653 /* Read the PF Queue Filter control register */ 5654 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5655 5656 /* Program required PE hash buckets for the PF */ 5657 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5658 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5659 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5660 /* Program required PE contexts for the PF */ 5661 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5662 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5663 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5664 5665 /* Program required FCoE hash buckets for the PF */ 5666 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5667 val |= ((u32)settings->fcoe_filt_num << 5668 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5669 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5670 /* Program required FCoE DDP contexts for the PF */ 5671 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5672 val |= ((u32)settings->fcoe_cntx_num << 5673 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5674 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5675 5676 /* Program Hash LUT size for the PF */ 5677 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5678 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5679 hash_lut_size = 1; 5680 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5681 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5682 5683 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5684 if (settings->enable_fdir) 5685 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5686 if (settings->enable_ethtype) 5687 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5688 if (settings->enable_macvlan) 5689 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5690 5691 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5692 5693 return I40E_SUCCESS; 5694 } 5695 5696 /** 5697 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5698 * @hw: pointer to the hw struct 5699 * @mac_addr: MAC address to use in the filter 5700 * @ethtype: Ethertype to use in the filter 5701 * @flags: Flags that needs to be applied to the filter 5702 * @vsi_seid: seid of the control VSI 5703 * @queue: VSI queue number to send the packet to 5704 * @is_add: Add control packet filter if True else remove 5705 * @stats: Structure to hold information on control filter counts 5706 * @cmd_details: pointer to command details structure or NULL 5707 * 5708 * This command will Add or Remove control packet filter for a control VSI. 5709 * In return it will update the total number of perfect filter count in 5710 * the stats member. 5711 **/ 5712 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5713 u8 *mac_addr, u16 ethtype, u16 flags, 5714 u16 vsi_seid, u16 queue, bool is_add, 5715 struct i40e_control_filter_stats *stats, 5716 struct i40e_asq_cmd_details *cmd_details) 5717 { 5718 struct i40e_aq_desc desc; 5719 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5720 (struct i40e_aqc_add_remove_control_packet_filter *) 5721 &desc.params.raw; 5722 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5723 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5724 &desc.params.raw; 5725 enum i40e_status_code status; 5726 5727 if (vsi_seid == 0) 5728 return I40E_ERR_PARAM; 5729 5730 if (is_add) { 5731 i40e_fill_default_direct_cmd_desc(&desc, 5732 i40e_aqc_opc_add_control_packet_filter); 5733 cmd->queue = CPU_TO_LE16(queue); 5734 } else { 5735 i40e_fill_default_direct_cmd_desc(&desc, 5736 i40e_aqc_opc_remove_control_packet_filter); 5737 } 5738 5739 if (mac_addr) 5740 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, 5741 I40E_NONDMA_TO_NONDMA); 5742 5743 cmd->etype = CPU_TO_LE16(ethtype); 5744 cmd->flags = CPU_TO_LE16(flags); 5745 cmd->seid = CPU_TO_LE16(vsi_seid); 5746 5747 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5748 5749 if (!status && stats) { 5750 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5751 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5752 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5753 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5754 } 5755 5756 return status; 5757 } 5758 5759 /** 5760 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5761 * @hw: pointer to the hw struct 5762 * @seid: VSI seid to add ethertype filter from 5763 **/ 5764 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5765 u16 seid) 5766 { 5767 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5768 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5769 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5770 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5771 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5772 enum i40e_status_code status; 5773 5774 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5775 seid, 0, true, NULL, 5776 NULL); 5777 if (status) 5778 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5779 } 5780 5781 /** 5782 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5783 * @filters: list of cloud filters 5784 * @filter_count: length of list 5785 * 5786 * There's an issue in the device where the Geneve VNI layout needs 5787 * to be shifted 1 byte over from the VxLAN VNI 5788 **/ 5789 STATIC void i40e_fix_up_geneve_vni( 5790 struct i40e_aqc_cloud_filters_element_data *filters, 5791 u8 filter_count) 5792 { 5793 struct i40e_aqc_cloud_filters_element_data *f = filters; 5794 int i; 5795 5796 for (i = 0; i < filter_count; i++) { 5797 u16 tnl_type; 5798 u32 ti; 5799 5800 tnl_type = (LE16_TO_CPU(f[i].flags) & 5801 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5802 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5803 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5804 ti = LE32_TO_CPU(f[i].tenant_id); 5805 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5806 } 5807 } 5808 } 5809 5810 /** 5811 * i40e_aq_add_cloud_filters 5812 * @hw: pointer to the hardware structure 5813 * @seid: VSI seid to add cloud filters from 5814 * @filters: Buffer which contains the filters to be added 5815 * @filter_count: number of filters contained in the buffer 5816 * 5817 * Set the cloud filters for a given VSI. The contents of the 5818 * i40e_aqc_cloud_filters_element_data are filled 5819 * in by the caller of the function. 5820 * 5821 **/ 5822 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5823 u16 seid, 5824 struct i40e_aqc_cloud_filters_element_data *filters, 5825 u8 filter_count) 5826 { 5827 struct i40e_aq_desc desc; 5828 struct i40e_aqc_add_remove_cloud_filters *cmd = 5829 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5830 enum i40e_status_code status; 5831 u16 buff_len; 5832 5833 i40e_fill_default_direct_cmd_desc(&desc, 5834 i40e_aqc_opc_add_cloud_filters); 5835 5836 buff_len = filter_count * sizeof(*filters); 5837 desc.datalen = CPU_TO_LE16(buff_len); 5838 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5839 cmd->num_filters = filter_count; 5840 cmd->seid = CPU_TO_LE16(seid); 5841 5842 i40e_fix_up_geneve_vni(filters, filter_count); 5843 5844 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5845 5846 return status; 5847 } 5848 5849 /** 5850 * i40e_aq_add_cloud_filters_bb 5851 * @hw: pointer to the hardware structure 5852 * @seid: VSI seid to add cloud filters from 5853 * @filters: Buffer which contains the filters in big buffer to be added 5854 * @filter_count: number of filters contained in the buffer 5855 * 5856 * Set the cloud filters for a given VSI. The contents of the 5857 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5858 * the function. 5859 * 5860 **/ 5861 enum i40e_status_code 5862 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5863 struct i40e_aqc_cloud_filters_element_bb *filters, 5864 u8 filter_count) 5865 { 5866 struct i40e_aq_desc desc; 5867 struct i40e_aqc_add_remove_cloud_filters *cmd = 5868 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5869 enum i40e_status_code status; 5870 u16 buff_len; 5871 int i; 5872 5873 i40e_fill_default_direct_cmd_desc(&desc, 5874 i40e_aqc_opc_add_cloud_filters); 5875 5876 buff_len = filter_count * sizeof(*filters); 5877 desc.datalen = CPU_TO_LE16(buff_len); 5878 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5879 cmd->num_filters = filter_count; 5880 cmd->seid = CPU_TO_LE16(seid); 5881 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5882 5883 for (i = 0; i < filter_count; i++) { 5884 u16 tnl_type; 5885 u32 ti; 5886 5887 tnl_type = (LE16_TO_CPU(filters[i].element.flags) & 5888 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5889 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5890 5891 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5892 * one more byte further than normally used for Tenant ID in 5893 * other tunnel types. 5894 */ 5895 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5896 ti = LE32_TO_CPU(filters[i].element.tenant_id); 5897 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8); 5898 } 5899 } 5900 5901 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5902 5903 return status; 5904 } 5905 5906 /** 5907 * i40e_aq_rem_cloud_filters 5908 * @hw: pointer to the hardware structure 5909 * @seid: VSI seid to remove cloud filters from 5910 * @filters: Buffer which contains the filters to be removed 5911 * @filter_count: number of filters contained in the buffer 5912 * 5913 * Remove the cloud filters for a given VSI. The contents of the 5914 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5915 * of the function. 5916 * 5917 **/ 5918 enum i40e_status_code 5919 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5920 struct i40e_aqc_cloud_filters_element_data *filters, 5921 u8 filter_count) 5922 { 5923 struct i40e_aq_desc desc; 5924 struct i40e_aqc_add_remove_cloud_filters *cmd = 5925 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5926 enum i40e_status_code status; 5927 u16 buff_len; 5928 5929 i40e_fill_default_direct_cmd_desc(&desc, 5930 i40e_aqc_opc_remove_cloud_filters); 5931 5932 buff_len = filter_count * sizeof(*filters); 5933 desc.datalen = CPU_TO_LE16(buff_len); 5934 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5935 cmd->num_filters = filter_count; 5936 cmd->seid = CPU_TO_LE16(seid); 5937 5938 i40e_fix_up_geneve_vni(filters, filter_count); 5939 5940 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5941 5942 return status; 5943 } 5944 5945 /** 5946 * i40e_aq_rem_cloud_filters_bb 5947 * @hw: pointer to the hardware structure 5948 * @seid: VSI seid to remove cloud filters from 5949 * @filters: Buffer which contains the filters in big buffer to be removed 5950 * @filter_count: number of filters contained in the buffer 5951 * 5952 * Remove the big buffer cloud filters for a given VSI. The contents of the 5953 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5954 * function. 5955 * 5956 **/ 5957 enum i40e_status_code 5958 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5959 struct i40e_aqc_cloud_filters_element_bb *filters, 5960 u8 filter_count) 5961 { 5962 struct i40e_aq_desc desc; 5963 struct i40e_aqc_add_remove_cloud_filters *cmd = 5964 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5965 enum i40e_status_code status; 5966 u16 buff_len; 5967 int i; 5968 5969 i40e_fill_default_direct_cmd_desc(&desc, 5970 i40e_aqc_opc_remove_cloud_filters); 5971 5972 buff_len = filter_count * sizeof(*filters); 5973 desc.datalen = CPU_TO_LE16(buff_len); 5974 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5975 cmd->num_filters = filter_count; 5976 cmd->seid = CPU_TO_LE16(seid); 5977 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5978 5979 for (i = 0; i < filter_count; i++) { 5980 u16 tnl_type; 5981 u32 ti; 5982 5983 tnl_type = (LE16_TO_CPU(filters[i].element.flags) & 5984 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5985 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5986 5987 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5988 * one more byte further than normally used for Tenant ID in 5989 * other tunnel types. 5990 */ 5991 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5992 ti = LE32_TO_CPU(filters[i].element.tenant_id); 5993 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8); 5994 } 5995 } 5996 5997 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5998 5999 return status; 6000 } 6001 6002 /** 6003 * i40e_aq_replace_cloud_filters - Replace cloud filter command 6004 * @hw: pointer to the hw struct 6005 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct 6006 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct 6007 * 6008 **/ 6009 enum 6010 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw, 6011 struct i40e_aqc_replace_cloud_filters_cmd *filters, 6012 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf) 6013 { 6014 struct i40e_aq_desc desc; 6015 struct i40e_aqc_replace_cloud_filters_cmd *cmd = 6016 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw; 6017 enum i40e_status_code status = I40E_SUCCESS; 6018 int i = 0; 6019 6020 /* X722 doesn't support this command */ 6021 if (hw->mac.type == I40E_MAC_X722) 6022 return I40E_ERR_DEVICE_NOT_SUPPORTED; 6023 6024 /* need FW version greater than 6.00 */ 6025 if (hw->aq.fw_maj_ver < 6) 6026 return I40E_NOT_SUPPORTED; 6027 6028 i40e_fill_default_direct_cmd_desc(&desc, 6029 i40e_aqc_opc_replace_cloud_filters); 6030 6031 desc.datalen = CPU_TO_LE16(32); 6032 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 6033 cmd->old_filter_type = filters->old_filter_type; 6034 cmd->new_filter_type = filters->new_filter_type; 6035 cmd->valid_flags = filters->valid_flags; 6036 cmd->tr_bit = filters->tr_bit; 6037 cmd->tr_bit2 = filters->tr_bit2; 6038 6039 status = i40e_asq_send_command(hw, &desc, cmd_buf, 6040 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL); 6041 6042 /* for get cloud filters command */ 6043 for (i = 0; i < 32; i += 4) { 6044 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i]; 6045 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1]; 6046 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2]; 6047 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3]; 6048 } 6049 6050 return status; 6051 } 6052 6053 6054 /** 6055 * i40e_aq_alternate_write 6056 * @hw: pointer to the hardware structure 6057 * @reg_addr0: address of first dword to be read 6058 * @reg_val0: value to be written under 'reg_addr0' 6059 * @reg_addr1: address of second dword to be read 6060 * @reg_val1: value to be written under 'reg_addr1' 6061 * 6062 * Write one or two dwords to alternate structure. Fields are indicated 6063 * by 'reg_addr0' and 'reg_addr1' register numbers. 6064 * 6065 **/ 6066 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 6067 u32 reg_addr0, u32 reg_val0, 6068 u32 reg_addr1, u32 reg_val1) 6069 { 6070 struct i40e_aq_desc desc; 6071 struct i40e_aqc_alternate_write *cmd_resp = 6072 (struct i40e_aqc_alternate_write *)&desc.params.raw; 6073 enum i40e_status_code status; 6074 6075 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 6076 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 6077 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 6078 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 6079 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 6080 6081 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6082 6083 return status; 6084 } 6085 6086 /** 6087 * i40e_aq_alternate_write_indirect 6088 * @hw: pointer to the hardware structure 6089 * @addr: address of a first register to be modified 6090 * @dw_count: number of alternate structure fields to write 6091 * @buffer: pointer to the command buffer 6092 * 6093 * Write 'dw_count' dwords from 'buffer' to alternate structure 6094 * starting at 'addr'. 6095 * 6096 **/ 6097 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 6098 u32 addr, u32 dw_count, void *buffer) 6099 { 6100 struct i40e_aq_desc desc; 6101 struct i40e_aqc_alternate_ind_write *cmd_resp = 6102 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 6103 enum i40e_status_code status; 6104 6105 if (buffer == NULL) 6106 return I40E_ERR_PARAM; 6107 6108 /* Indirect command */ 6109 i40e_fill_default_direct_cmd_desc(&desc, 6110 i40e_aqc_opc_alternate_write_indirect); 6111 6112 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 6113 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 6114 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 6115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6116 6117 cmd_resp->address = CPU_TO_LE32(addr); 6118 cmd_resp->length = CPU_TO_LE32(dw_count); 6119 6120 status = i40e_asq_send_command(hw, &desc, buffer, 6121 I40E_LO_DWORD(4*dw_count), NULL); 6122 6123 return status; 6124 } 6125 6126 /** 6127 * i40e_aq_alternate_read 6128 * @hw: pointer to the hardware structure 6129 * @reg_addr0: address of first dword to be read 6130 * @reg_val0: pointer for data read from 'reg_addr0' 6131 * @reg_addr1: address of second dword to be read 6132 * @reg_val1: pointer for data read from 'reg_addr1' 6133 * 6134 * Read one or two dwords from alternate structure. Fields are indicated 6135 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 6136 * is not passed then only register at 'reg_addr0' is read. 6137 * 6138 **/ 6139 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 6140 u32 reg_addr0, u32 *reg_val0, 6141 u32 reg_addr1, u32 *reg_val1) 6142 { 6143 struct i40e_aq_desc desc; 6144 struct i40e_aqc_alternate_write *cmd_resp = 6145 (struct i40e_aqc_alternate_write *)&desc.params.raw; 6146 enum i40e_status_code status; 6147 6148 if (reg_val0 == NULL) 6149 return I40E_ERR_PARAM; 6150 6151 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 6152 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 6153 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 6154 6155 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6156 6157 if (status == I40E_SUCCESS) { 6158 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 6159 6160 if (reg_val1 != NULL) 6161 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 6162 } 6163 6164 return status; 6165 } 6166 6167 /** 6168 * i40e_aq_alternate_read_indirect 6169 * @hw: pointer to the hardware structure 6170 * @addr: address of the alternate structure field 6171 * @dw_count: number of alternate structure fields to read 6172 * @buffer: pointer to the command buffer 6173 * 6174 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 6175 * place them in 'buffer'. The buffer should be allocated by caller. 6176 * 6177 **/ 6178 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 6179 u32 addr, u32 dw_count, void *buffer) 6180 { 6181 struct i40e_aq_desc desc; 6182 struct i40e_aqc_alternate_ind_write *cmd_resp = 6183 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 6184 enum i40e_status_code status; 6185 6186 if (buffer == NULL) 6187 return I40E_ERR_PARAM; 6188 6189 /* Indirect command */ 6190 i40e_fill_default_direct_cmd_desc(&desc, 6191 i40e_aqc_opc_alternate_read_indirect); 6192 6193 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 6194 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 6195 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 6196 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6197 6198 cmd_resp->address = CPU_TO_LE32(addr); 6199 cmd_resp->length = CPU_TO_LE32(dw_count); 6200 6201 status = i40e_asq_send_command(hw, &desc, buffer, 6202 I40E_LO_DWORD(4*dw_count), NULL); 6203 6204 return status; 6205 } 6206 6207 /** 6208 * i40e_aq_alternate_clear 6209 * @hw: pointer to the HW structure. 6210 * 6211 * Clear the alternate structures of the port from which the function 6212 * is called. 6213 * 6214 **/ 6215 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 6216 { 6217 struct i40e_aq_desc desc; 6218 enum i40e_status_code status; 6219 6220 i40e_fill_default_direct_cmd_desc(&desc, 6221 i40e_aqc_opc_alternate_clear_port); 6222 6223 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6224 6225 return status; 6226 } 6227 6228 /** 6229 * i40e_aq_alternate_write_done 6230 * @hw: pointer to the HW structure. 6231 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 6232 * @reset_needed: indicates the SW should trigger GLOBAL reset 6233 * 6234 * Indicates to the FW that alternate structures have been changed. 6235 * 6236 **/ 6237 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 6238 u8 bios_mode, bool *reset_needed) 6239 { 6240 struct i40e_aq_desc desc; 6241 struct i40e_aqc_alternate_write_done *cmd = 6242 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 6243 enum i40e_status_code status; 6244 6245 if (reset_needed == NULL) 6246 return I40E_ERR_PARAM; 6247 6248 i40e_fill_default_direct_cmd_desc(&desc, 6249 i40e_aqc_opc_alternate_write_done); 6250 6251 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 6252 6253 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6254 if (!status && reset_needed) 6255 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 6256 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 6257 6258 return status; 6259 } 6260 6261 /** 6262 * i40e_aq_set_oem_mode 6263 * @hw: pointer to the HW structure. 6264 * @oem_mode: the OEM mode to be used 6265 * 6266 * Sets the device to a specific operating mode. Currently the only supported 6267 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 6268 * 6269 **/ 6270 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 6271 u8 oem_mode) 6272 { 6273 struct i40e_aq_desc desc; 6274 struct i40e_aqc_alternate_write_done *cmd = 6275 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 6276 enum i40e_status_code status; 6277 6278 i40e_fill_default_direct_cmd_desc(&desc, 6279 i40e_aqc_opc_alternate_set_mode); 6280 6281 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 6282 6283 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6284 6285 return status; 6286 } 6287 6288 /** 6289 * i40e_aq_resume_port_tx 6290 * @hw: pointer to the hardware structure 6291 * @cmd_details: pointer to command details structure or NULL 6292 * 6293 * Resume port's Tx traffic 6294 **/ 6295 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 6296 struct i40e_asq_cmd_details *cmd_details) 6297 { 6298 struct i40e_aq_desc desc; 6299 enum i40e_status_code status; 6300 6301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 6302 6303 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6304 6305 return status; 6306 } 6307 6308 /** 6309 * i40e_set_pci_config_data - store PCI bus info 6310 * @hw: pointer to hardware structure 6311 * @link_status: the link status word from PCI config space 6312 * 6313 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 6314 **/ 6315 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 6316 { 6317 hw->bus.type = i40e_bus_type_pci_express; 6318 6319 switch (link_status & I40E_PCI_LINK_WIDTH) { 6320 case I40E_PCI_LINK_WIDTH_1: 6321 hw->bus.width = i40e_bus_width_pcie_x1; 6322 break; 6323 case I40E_PCI_LINK_WIDTH_2: 6324 hw->bus.width = i40e_bus_width_pcie_x2; 6325 break; 6326 case I40E_PCI_LINK_WIDTH_4: 6327 hw->bus.width = i40e_bus_width_pcie_x4; 6328 break; 6329 case I40E_PCI_LINK_WIDTH_8: 6330 hw->bus.width = i40e_bus_width_pcie_x8; 6331 break; 6332 default: 6333 hw->bus.width = i40e_bus_width_unknown; 6334 break; 6335 } 6336 6337 switch (link_status & I40E_PCI_LINK_SPEED) { 6338 case I40E_PCI_LINK_SPEED_2500: 6339 hw->bus.speed = i40e_bus_speed_2500; 6340 break; 6341 case I40E_PCI_LINK_SPEED_5000: 6342 hw->bus.speed = i40e_bus_speed_5000; 6343 break; 6344 case I40E_PCI_LINK_SPEED_8000: 6345 hw->bus.speed = i40e_bus_speed_8000; 6346 break; 6347 default: 6348 hw->bus.speed = i40e_bus_speed_unknown; 6349 break; 6350 } 6351 } 6352 6353 /** 6354 * i40e_aq_debug_dump 6355 * @hw: pointer to the hardware structure 6356 * @cluster_id: specific cluster to dump 6357 * @table_id: table id within cluster 6358 * @start_index: index of line in the block to read 6359 * @buff_size: dump buffer size 6360 * @buff: dump buffer 6361 * @ret_buff_size: actual buffer size returned 6362 * @ret_next_table: next block to read 6363 * @ret_next_index: next index to read 6364 * @cmd_details: pointer to command details structure or NULL 6365 * 6366 * Dump internal FW/HW data for debug purposes. 6367 * 6368 **/ 6369 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 6370 u8 table_id, u32 start_index, u16 buff_size, 6371 void *buff, u16 *ret_buff_size, 6372 u8 *ret_next_table, u32 *ret_next_index, 6373 struct i40e_asq_cmd_details *cmd_details) 6374 { 6375 struct i40e_aq_desc desc; 6376 struct i40e_aqc_debug_dump_internals *cmd = 6377 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6378 struct i40e_aqc_debug_dump_internals *resp = 6379 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6380 enum i40e_status_code status; 6381 6382 if (buff_size == 0 || !buff) 6383 return I40E_ERR_PARAM; 6384 6385 i40e_fill_default_direct_cmd_desc(&desc, 6386 i40e_aqc_opc_debug_dump_internals); 6387 /* Indirect Command */ 6388 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6389 if (buff_size > I40E_AQ_LARGE_BUF) 6390 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6391 6392 cmd->cluster_id = cluster_id; 6393 cmd->table_id = table_id; 6394 cmd->idx = CPU_TO_LE32(start_index); 6395 6396 desc.datalen = CPU_TO_LE16(buff_size); 6397 6398 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 6399 if (!status) { 6400 if (ret_buff_size != NULL) 6401 *ret_buff_size = LE16_TO_CPU(desc.datalen); 6402 if (ret_next_table != NULL) 6403 *ret_next_table = resp->table_id; 6404 if (ret_next_index != NULL) 6405 *ret_next_index = LE32_TO_CPU(resp->idx); 6406 } 6407 6408 return status; 6409 } 6410 6411 6412 /** 6413 * i40e_enable_eee 6414 * @hw: pointer to the hardware structure 6415 * @enable: state of Energy Efficient Ethernet mode to be set 6416 * 6417 * Enables or disables Energy Efficient Ethernet (EEE) mode 6418 * accordingly to @enable parameter. 6419 **/ 6420 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable) 6421 { 6422 struct i40e_aq_get_phy_abilities_resp abilities; 6423 struct i40e_aq_set_phy_config config; 6424 enum i40e_status_code status; 6425 __le16 eee_capability; 6426 6427 /* Get initial PHY capabilities */ 6428 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, 6429 NULL); 6430 if (status) 6431 goto err; 6432 6433 /* Check whether NIC configuration is compatible with Energy Efficient 6434 * Ethernet (EEE) mode. 6435 */ 6436 if (abilities.eee_capability == 0) { 6437 status = I40E_ERR_CONFIG; 6438 goto err; 6439 } 6440 6441 /* Cache initial EEE capability */ 6442 eee_capability = abilities.eee_capability; 6443 6444 /* Get current configuration */ 6445 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 6446 NULL); 6447 if (status) 6448 goto err; 6449 6450 /* Cache current configuration */ 6451 config.phy_type = abilities.phy_type; 6452 config.phy_type_ext = abilities.phy_type_ext; 6453 config.link_speed = abilities.link_speed; 6454 config.abilities = abilities.abilities | 6455 I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 6456 config.eeer = abilities.eeer_val; 6457 config.low_power_ctrl = abilities.d3_lpan; 6458 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 6459 I40E_AQ_PHY_FEC_CONFIG_MASK; 6460 6461 /* Set desired EEE state */ 6462 if (enable) { 6463 config.eee_capability = eee_capability; 6464 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK; 6465 } else { 6466 config.eee_capability = 0; 6467 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK; 6468 } 6469 6470 /* Save modified config */ 6471 status = i40e_aq_set_phy_config(hw, &config, NULL); 6472 err: 6473 return status; 6474 } 6475 6476 /** 6477 * i40e_read_bw_from_alt_ram 6478 * @hw: pointer to the hardware structure 6479 * @max_bw: pointer for max_bw read 6480 * @min_bw: pointer for min_bw read 6481 * @min_valid: pointer for bool that is true if min_bw is a valid value 6482 * @max_valid: pointer for bool that is true if max_bw is a valid value 6483 * 6484 * Read bw from the alternate ram for the given pf 6485 **/ 6486 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 6487 u32 *max_bw, u32 *min_bw, 6488 bool *min_valid, bool *max_valid) 6489 { 6490 enum i40e_status_code status; 6491 u32 max_bw_addr, min_bw_addr; 6492 6493 /* Calculate the address of the min/max bw registers */ 6494 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6495 I40E_ALT_STRUCT_MAX_BW_OFFSET + 6496 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6497 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6498 I40E_ALT_STRUCT_MIN_BW_OFFSET + 6499 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6500 6501 /* Read the bandwidths from alt ram */ 6502 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 6503 min_bw_addr, min_bw); 6504 6505 if (*min_bw & I40E_ALT_BW_VALID_MASK) 6506 *min_valid = true; 6507 else 6508 *min_valid = false; 6509 6510 if (*max_bw & I40E_ALT_BW_VALID_MASK) 6511 *max_valid = true; 6512 else 6513 *max_valid = false; 6514 6515 return status; 6516 } 6517 6518 /** 6519 * i40e_aq_configure_partition_bw 6520 * @hw: pointer to the hardware structure 6521 * @bw_data: Buffer holding valid pfs and bw limits 6522 * @cmd_details: pointer to command details 6523 * 6524 * Configure partitions guaranteed/max bw 6525 **/ 6526 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 6527 struct i40e_aqc_configure_partition_bw_data *bw_data, 6528 struct i40e_asq_cmd_details *cmd_details) 6529 { 6530 enum i40e_status_code status; 6531 struct i40e_aq_desc desc; 6532 u16 bwd_size = sizeof(*bw_data); 6533 6534 i40e_fill_default_direct_cmd_desc(&desc, 6535 i40e_aqc_opc_configure_partition_bw); 6536 6537 /* Indirect command */ 6538 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6539 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6540 6541 desc.datalen = CPU_TO_LE16(bwd_size); 6542 6543 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6544 6545 return status; 6546 } 6547 6548 /** 6549 * i40e_read_phy_register_clause22 6550 * @hw: pointer to the HW structure 6551 * @reg: register address in the page 6552 * @phy_addr: PHY address on MDIO interface 6553 * @value: PHY register value 6554 * 6555 * Reads specified PHY register value 6556 **/ 6557 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6558 u16 reg, u8 phy_addr, u16 *value) 6559 { 6560 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6561 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6562 u32 command = 0; 6563 u16 retry = 1000; 6564 6565 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6566 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6567 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6568 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6569 (I40E_GLGEN_MSCA_MDICMD_MASK); 6570 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6571 do { 6572 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6573 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6574 status = I40E_SUCCESS; 6575 break; 6576 } 6577 i40e_usec_delay(10); 6578 retry--; 6579 } while (retry); 6580 6581 if (status) { 6582 i40e_debug(hw, I40E_DEBUG_PHY, 6583 "PHY: Can't write command to external PHY.\n"); 6584 } else { 6585 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6586 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6587 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6588 } 6589 6590 return status; 6591 } 6592 6593 /** 6594 * i40e_write_phy_register_clause22 6595 * @hw: pointer to the HW structure 6596 * @reg: register address in the page 6597 * @phy_addr: PHY address on MDIO interface 6598 * @value: PHY register value 6599 * 6600 * Writes specified PHY register value 6601 **/ 6602 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6603 u16 reg, u8 phy_addr, u16 value) 6604 { 6605 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6606 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6607 u32 command = 0; 6608 u16 retry = 1000; 6609 6610 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6611 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6612 6613 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6614 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6615 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6616 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6617 (I40E_GLGEN_MSCA_MDICMD_MASK); 6618 6619 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6620 do { 6621 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6622 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6623 status = I40E_SUCCESS; 6624 break; 6625 } 6626 i40e_usec_delay(10); 6627 retry--; 6628 } while (retry); 6629 6630 return status; 6631 } 6632 6633 /** 6634 * i40e_read_phy_register_clause45 6635 * @hw: pointer to the HW structure 6636 * @page: registers page number 6637 * @reg: register address in the page 6638 * @phy_addr: PHY address on MDIO interface 6639 * @value: PHY register value 6640 * 6641 * Reads specified PHY register value 6642 **/ 6643 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6644 u8 page, u16 reg, u8 phy_addr, u16 *value) 6645 { 6646 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6647 u32 command = 0; 6648 u16 retry = 1000; 6649 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6650 6651 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6652 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6653 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6654 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6655 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6656 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6657 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6658 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6659 do { 6660 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6661 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6662 status = I40E_SUCCESS; 6663 break; 6664 } 6665 i40e_usec_delay(10); 6666 retry--; 6667 } while (retry); 6668 6669 if (status) { 6670 i40e_debug(hw, I40E_DEBUG_PHY, 6671 "PHY: Can't write command to external PHY.\n"); 6672 goto phy_read_end; 6673 } 6674 6675 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6676 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6677 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6678 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6679 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6680 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6681 status = I40E_ERR_TIMEOUT; 6682 retry = 1000; 6683 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6684 do { 6685 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6686 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6687 status = I40E_SUCCESS; 6688 break; 6689 } 6690 i40e_usec_delay(10); 6691 retry--; 6692 } while (retry); 6693 6694 if (!status) { 6695 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6696 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6697 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6698 } else { 6699 i40e_debug(hw, I40E_DEBUG_PHY, 6700 "PHY: Can't read register value from external PHY.\n"); 6701 } 6702 6703 phy_read_end: 6704 return status; 6705 } 6706 6707 /** 6708 * i40e_write_phy_register_clause45 6709 * @hw: pointer to the HW structure 6710 * @page: registers page number 6711 * @reg: register address in the page 6712 * @phy_addr: PHY address on MDIO interface 6713 * @value: PHY register value 6714 * 6715 * Writes value to specified PHY register 6716 **/ 6717 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6718 u8 page, u16 reg, u8 phy_addr, u16 value) 6719 { 6720 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6721 u32 command = 0; 6722 u16 retry = 1000; 6723 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6724 6725 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6726 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6727 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6728 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6729 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6730 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6731 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6732 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6733 do { 6734 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6735 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6736 status = I40E_SUCCESS; 6737 break; 6738 } 6739 i40e_usec_delay(10); 6740 retry--; 6741 } while (retry); 6742 if (status) { 6743 i40e_debug(hw, I40E_DEBUG_PHY, 6744 "PHY: Can't write command to external PHY.\n"); 6745 goto phy_write_end; 6746 } 6747 6748 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6749 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6750 6751 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6752 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6753 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6754 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6755 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6756 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6757 status = I40E_ERR_TIMEOUT; 6758 retry = 1000; 6759 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6760 do { 6761 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6762 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6763 status = I40E_SUCCESS; 6764 break; 6765 } 6766 i40e_usec_delay(10); 6767 retry--; 6768 } while (retry); 6769 6770 phy_write_end: 6771 return status; 6772 } 6773 6774 /** 6775 * i40e_write_phy_register 6776 * @hw: pointer to the HW structure 6777 * @page: registers page number 6778 * @reg: register address in the page 6779 * @phy_addr: PHY address on MDIO interface 6780 * @value: PHY register value 6781 * 6782 * Writes value to specified PHY register 6783 **/ 6784 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6785 u8 page, u16 reg, u8 phy_addr, u16 value) 6786 { 6787 enum i40e_status_code status; 6788 6789 switch (hw->device_id) { 6790 case I40E_DEV_ID_1G_BASE_T_X722: 6791 status = i40e_write_phy_register_clause22(hw, 6792 reg, phy_addr, value); 6793 break; 6794 case I40E_DEV_ID_10G_BASE_T: 6795 case I40E_DEV_ID_10G_BASE_T4: 6796 case I40E_DEV_ID_10G_BASE_T_BC: 6797 case I40E_DEV_ID_5G_BASE_T_BC: 6798 case I40E_DEV_ID_10G_BASE_T_X722: 6799 case I40E_DEV_ID_25G_B: 6800 case I40E_DEV_ID_25G_SFP28: 6801 status = i40e_write_phy_register_clause45(hw, 6802 page, reg, phy_addr, value); 6803 break; 6804 default: 6805 status = I40E_ERR_UNKNOWN_PHY; 6806 break; 6807 } 6808 6809 return status; 6810 } 6811 6812 /** 6813 * i40e_read_phy_register 6814 * @hw: pointer to the HW structure 6815 * @page: registers page number 6816 * @reg: register address in the page 6817 * @phy_addr: PHY address on MDIO interface 6818 * @value: PHY register value 6819 * 6820 * Reads specified PHY register value 6821 **/ 6822 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6823 u8 page, u16 reg, u8 phy_addr, u16 *value) 6824 { 6825 enum i40e_status_code status; 6826 6827 switch (hw->device_id) { 6828 case I40E_DEV_ID_1G_BASE_T_X722: 6829 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6830 value); 6831 break; 6832 case I40E_DEV_ID_10G_BASE_T: 6833 case I40E_DEV_ID_10G_BASE_T4: 6834 case I40E_DEV_ID_5G_BASE_T_BC: 6835 case I40E_DEV_ID_10G_BASE_T_X722: 6836 case I40E_DEV_ID_25G_B: 6837 case I40E_DEV_ID_25G_SFP28: 6838 status = i40e_read_phy_register_clause45(hw, page, reg, 6839 phy_addr, value); 6840 break; 6841 default: 6842 status = I40E_ERR_UNKNOWN_PHY; 6843 break; 6844 } 6845 6846 return status; 6847 } 6848 6849 /** 6850 * i40e_get_phy_address 6851 * @hw: pointer to the HW structure 6852 * @dev_num: PHY port num that address we want 6853 * 6854 * Gets PHY address for current port 6855 **/ 6856 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6857 { 6858 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6859 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6860 6861 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6862 } 6863 6864 /** 6865 * i40e_blink_phy_led 6866 * @hw: pointer to the HW structure 6867 * @time: time how long led will blinks in secs 6868 * @interval: gap between LED on and off in msecs 6869 * 6870 * Blinks PHY link LED 6871 **/ 6872 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6873 u32 time, u32 interval) 6874 { 6875 enum i40e_status_code status = I40E_SUCCESS; 6876 u32 i; 6877 u16 led_ctl = 0; 6878 u16 gpio_led_port; 6879 u16 led_reg; 6880 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6881 u8 phy_addr = 0; 6882 u8 port_num; 6883 6884 i = rd32(hw, I40E_PFGEN_PORTNUM); 6885 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6886 phy_addr = i40e_get_phy_address(hw, port_num); 6887 6888 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6889 led_addr++) { 6890 status = i40e_read_phy_register_clause45(hw, 6891 I40E_PHY_COM_REG_PAGE, 6892 led_addr, phy_addr, 6893 &led_reg); 6894 if (status) 6895 goto phy_blinking_end; 6896 led_ctl = led_reg; 6897 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6898 led_reg = 0; 6899 status = i40e_write_phy_register_clause45(hw, 6900 I40E_PHY_COM_REG_PAGE, 6901 led_addr, phy_addr, 6902 led_reg); 6903 if (status) 6904 goto phy_blinking_end; 6905 break; 6906 } 6907 } 6908 6909 if (time > 0 && interval > 0) { 6910 for (i = 0; i < time * 1000; i += interval) { 6911 status = i40e_read_phy_register_clause45(hw, 6912 I40E_PHY_COM_REG_PAGE, 6913 led_addr, phy_addr, &led_reg); 6914 if (status) 6915 goto restore_config; 6916 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6917 led_reg = 0; 6918 else 6919 led_reg = I40E_PHY_LED_MANUAL_ON; 6920 status = i40e_write_phy_register_clause45(hw, 6921 I40E_PHY_COM_REG_PAGE, 6922 led_addr, phy_addr, led_reg); 6923 if (status) 6924 goto restore_config; 6925 i40e_msec_delay(interval); 6926 } 6927 } 6928 6929 restore_config: 6930 status = i40e_write_phy_register_clause45(hw, 6931 I40E_PHY_COM_REG_PAGE, 6932 led_addr, phy_addr, led_ctl); 6933 6934 phy_blinking_end: 6935 return status; 6936 } 6937 6938 /** 6939 * i40e_led_get_reg - read LED register 6940 * @hw: pointer to the HW structure 6941 * @led_addr: LED register address 6942 * @reg_val: read register value 6943 **/ 6944 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 6945 u32 *reg_val) 6946 { 6947 enum i40e_status_code status; 6948 u8 phy_addr = 0; 6949 6950 *reg_val = 0; 6951 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6952 status = i40e_aq_get_phy_register(hw, 6953 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6954 I40E_PHY_COM_REG_PAGE, true, 6955 I40E_PHY_LED_PROV_REG_1, 6956 reg_val, NULL); 6957 } else { 6958 phy_addr = i40e_get_phy_address(hw, hw->port); 6959 status = i40e_read_phy_register_clause45(hw, 6960 I40E_PHY_COM_REG_PAGE, 6961 led_addr, phy_addr, 6962 (u16 *)reg_val); 6963 } 6964 return status; 6965 } 6966 6967 /** 6968 * i40e_led_set_reg - write LED register 6969 * @hw: pointer to the HW structure 6970 * @led_addr: LED register address 6971 * @reg_val: register value to write 6972 **/ 6973 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 6974 u32 reg_val) 6975 { 6976 enum i40e_status_code status; 6977 u8 phy_addr = 0; 6978 6979 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6980 status = i40e_aq_set_phy_register(hw, 6981 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6982 I40E_PHY_COM_REG_PAGE, true, 6983 I40E_PHY_LED_PROV_REG_1, 6984 reg_val, NULL); 6985 } else { 6986 phy_addr = i40e_get_phy_address(hw, hw->port); 6987 status = i40e_write_phy_register_clause45(hw, 6988 I40E_PHY_COM_REG_PAGE, 6989 led_addr, phy_addr, 6990 (u16)reg_val); 6991 } 6992 6993 return status; 6994 } 6995 6996 /** 6997 * i40e_led_get_phy - return current on/off mode 6998 * @hw: pointer to the hw struct 6999 * @led_addr: address of led register to use 7000 * @val: original value of register to use 7001 * 7002 **/ 7003 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 7004 u16 *val) 7005 { 7006 enum i40e_status_code status = I40E_SUCCESS; 7007 u16 gpio_led_port; 7008 u32 reg_val_aq; 7009 u16 temp_addr; 7010 u8 phy_addr = 0; 7011 u16 reg_val; 7012 7013 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 7014 status = i40e_aq_get_phy_register(hw, 7015 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 7016 I40E_PHY_COM_REG_PAGE, true, 7017 I40E_PHY_LED_PROV_REG_1, 7018 ®_val_aq, NULL); 7019 if (status == I40E_SUCCESS) 7020 *val = (u16)reg_val_aq; 7021 return status; 7022 } 7023 temp_addr = I40E_PHY_LED_PROV_REG_1; 7024 phy_addr = i40e_get_phy_address(hw, hw->port); 7025 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 7026 temp_addr++) { 7027 status = i40e_read_phy_register_clause45(hw, 7028 I40E_PHY_COM_REG_PAGE, 7029 temp_addr, phy_addr, 7030 ®_val); 7031 if (status) 7032 return status; 7033 *val = reg_val; 7034 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 7035 *led_addr = temp_addr; 7036 break; 7037 } 7038 } 7039 return status; 7040 } 7041 7042 /** 7043 * i40e_led_set_phy 7044 * @hw: pointer to the HW structure 7045 * @on: true or false 7046 * @led_addr: address of led register to use 7047 * @mode: original val plus bit for set or ignore 7048 * 7049 * Set led's on or off when controlled by the PHY 7050 * 7051 **/ 7052 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 7053 u16 led_addr, u32 mode) 7054 { 7055 enum i40e_status_code status = I40E_SUCCESS; 7056 u32 led_ctl = 0; 7057 u32 led_reg = 0; 7058 7059 status = i40e_led_get_reg(hw, led_addr, &led_reg); 7060 if (status) 7061 return status; 7062 led_ctl = led_reg; 7063 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 7064 led_reg = 0; 7065 status = i40e_led_set_reg(hw, led_addr, led_reg); 7066 if (status) 7067 return status; 7068 } 7069 status = i40e_led_get_reg(hw, led_addr, &led_reg); 7070 if (status) 7071 goto restore_config; 7072 if (on) 7073 led_reg = I40E_PHY_LED_MANUAL_ON; 7074 else 7075 led_reg = 0; 7076 status = i40e_led_set_reg(hw, led_addr, led_reg); 7077 if (status) 7078 goto restore_config; 7079 if (mode & I40E_PHY_LED_MODE_ORIG) { 7080 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 7081 status = i40e_led_set_reg(hw, led_addr, led_ctl); 7082 } 7083 return status; 7084 7085 restore_config: 7086 status = i40e_led_set_reg(hw, led_addr, led_ctl); 7087 return status; 7088 } 7089 #endif /* PF_DRIVER */ 7090 /** 7091 * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register 7092 * @hw: pointer to the hw struct 7093 * @stat: pointer to structure with status of rx and tx lpi 7094 * 7095 * Read LPI state directly from external PHY register or from MAC 7096 * register, depending on device ID and current link speed. 7097 */ 7098 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw, 7099 struct i40e_hw_port_stats *stat) 7100 { 7101 enum i40e_status_code ret = I40E_SUCCESS; 7102 bool eee_mrvl_phy; 7103 bool eee_bcm_phy; 7104 u32 val; 7105 7106 stat->rx_lpi_status = 0; 7107 stat->tx_lpi_status = 0; 7108 7109 eee_bcm_phy = 7110 (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC || 7111 hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) && 7112 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB || 7113 hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB); 7114 eee_mrvl_phy = 7115 hw->device_id == I40E_DEV_ID_1G_BASE_T_X722; 7116 7117 if (eee_bcm_phy || eee_mrvl_phy) { 7118 /* read Clause 45 PCS Status 1 register */ 7119 ret = i40e_aq_get_phy_register(hw, 7120 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 7121 I40E_BCM_PHY_PCS_STATUS1_PAGE, 7122 true, 7123 I40E_BCM_PHY_PCS_STATUS1_REG, 7124 &val, NULL); 7125 7126 if (ret != I40E_SUCCESS) 7127 return ret; 7128 7129 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI); 7130 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI); 7131 7132 return ret; 7133 } 7134 7135 val = rd32(hw, I40E_PRTPM_EEE_STAT); 7136 stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> 7137 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; 7138 stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> 7139 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; 7140 7141 return ret; 7142 } 7143 7144 /** 7145 * i40e_get_lpi_counters - read LPI counters from EEE statistics 7146 * @hw: pointer to the hw struct 7147 * @tx_counter: pointer to memory for TX LPI counter 7148 * @rx_counter: pointer to memory for RX LPI counter 7149 * @is_clear: returns true if counters are clear after read 7150 * 7151 * Read Low Power Idle (LPI) mode counters from Energy Efficient 7152 * Ethernet (EEE) statistics. 7153 **/ 7154 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw, 7155 u32 *tx_counter, u32 *rx_counter, 7156 bool *is_clear) 7157 { 7158 /* only X710-T*L requires special handling of counters 7159 * for other devices we just read the MAC registers 7160 */ 7161 if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC || 7162 hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) && 7163 hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) { 7164 enum i40e_status_code retval; 7165 u32 cmd_status = 0; 7166 7167 *is_clear = false; 7168 retval = i40e_aq_run_phy_activity(hw, 7169 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND, 7170 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT, 7171 &cmd_status, tx_counter, rx_counter, NULL); 7172 7173 if (!retval && cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC) 7174 retval = I40E_ERR_ADMIN_QUEUE_ERROR; 7175 7176 return retval; 7177 } 7178 7179 *is_clear = true; 7180 *tx_counter = rd32(hw, I40E_PRTPM_TLPIC); 7181 *rx_counter = rd32(hw, I40E_PRTPM_RLPIC); 7182 7183 return I40E_SUCCESS; 7184 } 7185 7186 /** 7187 * i40e_get_lpi_duration - read LPI time duration from EEE statistics 7188 * @hw: pointer to the hw struct 7189 * @stat: pointer to structure with status of rx and tx lpi 7190 * @tx_duration: pointer to memory for TX LPI time duration 7191 * @rx_duration: pointer to memory for RX LPI time duration 7192 * 7193 * Read Low Power Idle (LPI) mode time duration from Energy Efficient 7194 * Ethernet (EEE) statistics. 7195 */ 7196 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw, 7197 struct i40e_hw_port_stats *stat, 7198 u64 *tx_duration, u64 *rx_duration) 7199 { 7200 u32 tx_time_dur, rx_time_dur; 7201 enum i40e_status_code retval; 7202 u32 cmd_status; 7203 7204 if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC && 7205 hw->device_id != I40E_DEV_ID_5G_BASE_T_BC) 7206 return I40E_ERR_NOT_IMPLEMENTED; 7207 7208 retval = i40e_aq_run_phy_activity 7209 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND, 7210 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR, 7211 &cmd_status, &tx_time_dur, &rx_time_dur, NULL); 7212 7213 if (retval) 7214 return retval; 7215 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) != 7216 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC) 7217 return I40E_ERR_ADMIN_QUEUE_ERROR; 7218 7219 if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB && 7220 !tx_time_dur && !rx_time_dur && 7221 stat->tx_lpi_status && stat->rx_lpi_status) { 7222 retval = i40e_aq_run_phy_activity 7223 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND, 7224 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR, 7225 &cmd_status, 7226 &tx_time_dur, &rx_time_dur, NULL); 7227 7228 if (retval) 7229 return retval; 7230 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) != 7231 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC) 7232 return I40E_ERR_ADMIN_QUEUE_ERROR; 7233 tx_time_dur = 0; 7234 rx_time_dur = 0; 7235 } 7236 7237 *tx_duration = tx_time_dur; 7238 *rx_duration = rx_time_dur; 7239 7240 return retval; 7241 } 7242 7243 /** 7244 * i40e_lpi_stat_update - update LPI counters with values relative to offset 7245 * @hw: pointer to the hw struct 7246 * @offset_loaded: flag indicating need of writing current value to offset 7247 * @tx_offset: pointer to offset of TX LPI counter 7248 * @tx_stat: pointer to value of TX LPI counter 7249 * @rx_offset: pointer to offset of RX LPI counter 7250 * @rx_stat: pointer to value of RX LPI counter 7251 * 7252 * Update Low Power Idle (LPI) mode counters while having regard to passed 7253 * offsets. 7254 **/ 7255 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw, 7256 bool offset_loaded, u64 *tx_offset, 7257 u64 *tx_stat, u64 *rx_offset, 7258 u64 *rx_stat) 7259 { 7260 enum i40e_status_code retval; 7261 u32 tx_counter, rx_counter; 7262 bool is_clear; 7263 7264 retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear); 7265 if (retval) 7266 goto err; 7267 7268 if (is_clear) { 7269 *tx_stat += tx_counter; 7270 *rx_stat += rx_counter; 7271 } else { 7272 if (!offset_loaded) { 7273 *tx_offset = tx_counter; 7274 *rx_offset = rx_counter; 7275 } 7276 7277 *tx_stat = (tx_counter >= *tx_offset) ? 7278 (u32)(tx_counter - *tx_offset) : 7279 (u32)((tx_counter + BIT_ULL(32)) - *tx_offset); 7280 *rx_stat = (rx_counter >= *rx_offset) ? 7281 (u32)(rx_counter - *rx_offset) : 7282 (u32)((rx_counter + BIT_ULL(32)) - *rx_offset); 7283 } 7284 err: 7285 return retval; 7286 } 7287 7288 /** 7289 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 7290 * @hw: pointer to the hw struct 7291 * @reg_addr: register address 7292 * @reg_val: ptr to register value 7293 * @cmd_details: pointer to command details structure or NULL 7294 * 7295 * Use the firmware to read the Rx control register, 7296 * especially useful if the Rx unit is under heavy pressure 7297 **/ 7298 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 7299 u32 reg_addr, u32 *reg_val, 7300 struct i40e_asq_cmd_details *cmd_details) 7301 { 7302 struct i40e_aq_desc desc; 7303 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 7304 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 7305 enum i40e_status_code status; 7306 7307 if (reg_val == NULL) 7308 return I40E_ERR_PARAM; 7309 7310 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 7311 7312 cmd_resp->address = CPU_TO_LE32(reg_addr); 7313 7314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7315 7316 if (status == I40E_SUCCESS) 7317 *reg_val = LE32_TO_CPU(cmd_resp->value); 7318 7319 return status; 7320 } 7321 7322 /** 7323 * i40e_read_rx_ctl - read from an Rx control register 7324 * @hw: pointer to the hw struct 7325 * @reg_addr: register address 7326 **/ 7327 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 7328 { 7329 enum i40e_status_code status = I40E_SUCCESS; 7330 bool use_register; 7331 int retry = 5; 7332 u32 val = 0; 7333 7334 use_register = (((hw->aq.api_maj_ver == 1) && 7335 (hw->aq.api_min_ver < 5)) || 7336 (hw->mac.type == I40E_MAC_X722)); 7337 if (!use_register) { 7338 do_retry: 7339 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 7340 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 7341 i40e_msec_delay(1); 7342 retry--; 7343 goto do_retry; 7344 } 7345 } 7346 7347 /* if the AQ access failed, try the old-fashioned way */ 7348 if (status || use_register) 7349 val = rd32(hw, reg_addr); 7350 7351 return val; 7352 } 7353 7354 /** 7355 * i40e_aq_rx_ctl_write_register 7356 * @hw: pointer to the hw struct 7357 * @reg_addr: register address 7358 * @reg_val: register value 7359 * @cmd_details: pointer to command details structure or NULL 7360 * 7361 * Use the firmware to write to an Rx control register, 7362 * especially useful if the Rx unit is under heavy pressure 7363 **/ 7364 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 7365 u32 reg_addr, u32 reg_val, 7366 struct i40e_asq_cmd_details *cmd_details) 7367 { 7368 struct i40e_aq_desc desc; 7369 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 7370 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 7371 enum i40e_status_code status; 7372 7373 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 7374 7375 cmd->address = CPU_TO_LE32(reg_addr); 7376 cmd->value = CPU_TO_LE32(reg_val); 7377 7378 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7379 7380 return status; 7381 } 7382 7383 /** 7384 * i40e_write_rx_ctl - write to an Rx control register 7385 * @hw: pointer to the hw struct 7386 * @reg_addr: register address 7387 * @reg_val: register value 7388 **/ 7389 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 7390 { 7391 enum i40e_status_code status = I40E_SUCCESS; 7392 bool use_register; 7393 int retry = 5; 7394 7395 use_register = (((hw->aq.api_maj_ver == 1) && 7396 (hw->aq.api_min_ver < 5)) || 7397 (hw->mac.type == I40E_MAC_X722)); 7398 if (!use_register) { 7399 do_retry: 7400 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 7401 reg_val, NULL); 7402 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 7403 i40e_msec_delay(1); 7404 retry--; 7405 goto do_retry; 7406 } 7407 } 7408 7409 /* if the AQ access failed, try the old-fashioned way */ 7410 if (status || use_register) 7411 wr32(hw, reg_addr, reg_val); 7412 } 7413 7414 /** 7415 * i40e_mdio_if_number_selection - MDIO I/F number selection 7416 * @hw: pointer to the hw struct 7417 * @set_mdio: use MDIO I/F number specified by mdio_num 7418 * @mdio_num: MDIO I/F number 7419 * @cmd: pointer to PHY Register command structure 7420 **/ 7421 static void 7422 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num, 7423 struct i40e_aqc_phy_register_access *cmd) 7424 { 7425 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) { 7426 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED) 7427 cmd->cmd_flags |= 7428 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 7429 ((mdio_num << 7430 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) & 7431 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK); 7432 else 7433 i40e_debug(hw, I40E_DEBUG_PHY, 7434 "MDIO I/F number selection not supported by current FW version.\n"); 7435 } 7436 } 7437 7438 /** 7439 * i40e_aq_set_phy_register_ext 7440 * @hw: pointer to the hw struct 7441 * @phy_select: select which phy should be accessed 7442 * @dev_addr: PHY device address 7443 * @page_change: enable auto page change 7444 * @set_mdio: use MDIO I/F number specified by mdio_num 7445 * @mdio_num: MDIO I/F number 7446 * @reg_addr: PHY register address 7447 * @reg_val: new register value 7448 * @cmd_details: pointer to command details structure or NULL 7449 * 7450 * Write the external PHY register. 7451 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 7452 * may use simple wrapper i40e_aq_set_phy_register. 7453 **/ 7454 enum i40e_status_code 7455 i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 7456 u8 phy_select, u8 dev_addr, bool page_change, 7457 bool set_mdio, u8 mdio_num, 7458 u32 reg_addr, u32 reg_val, 7459 struct i40e_asq_cmd_details *cmd_details) 7460 { 7461 struct i40e_aq_desc desc; 7462 struct i40e_aqc_phy_register_access *cmd = 7463 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 7464 enum i40e_status_code status; 7465 7466 i40e_fill_default_direct_cmd_desc(&desc, 7467 i40e_aqc_opc_set_phy_register); 7468 7469 cmd->phy_interface = phy_select; 7470 cmd->dev_addres = dev_addr; 7471 cmd->reg_address = CPU_TO_LE32(reg_addr); 7472 cmd->reg_value = CPU_TO_LE32(reg_val); 7473 7474 if (!page_change) 7475 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 7476 7477 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 7478 7479 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7480 7481 return status; 7482 } 7483 7484 /** 7485 * i40e_aq_get_phy_register_ext 7486 * @hw: pointer to the hw struct 7487 * @phy_select: select which phy should be accessed 7488 * @dev_addr: PHY device address 7489 * @page_change: enable auto page change 7490 * @set_mdio: use MDIO I/F number specified by mdio_num 7491 * @mdio_num: MDIO I/F number 7492 * @reg_addr: PHY register address 7493 * @reg_val: read register value 7494 * @cmd_details: pointer to command details structure or NULL 7495 * 7496 * Read the external PHY register. 7497 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 7498 * may use simple wrapper i40e_aq_get_phy_register. 7499 **/ 7500 enum i40e_status_code 7501 i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 7502 u8 phy_select, u8 dev_addr, bool page_change, 7503 bool set_mdio, u8 mdio_num, 7504 u32 reg_addr, u32 *reg_val, 7505 struct i40e_asq_cmd_details *cmd_details) 7506 { 7507 struct i40e_aq_desc desc; 7508 struct i40e_aqc_phy_register_access *cmd = 7509 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 7510 enum i40e_status_code status; 7511 7512 i40e_fill_default_direct_cmd_desc(&desc, 7513 i40e_aqc_opc_get_phy_register); 7514 7515 cmd->phy_interface = phy_select; 7516 cmd->dev_addres = dev_addr; 7517 cmd->reg_address = CPU_TO_LE32(reg_addr); 7518 7519 if (!page_change) 7520 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 7521 7522 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 7523 7524 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7525 if (!status) 7526 *reg_val = LE32_TO_CPU(cmd->reg_value); 7527 7528 return status; 7529 } 7530 7531 /** 7532 * i40e_aq_run_phy_activity 7533 * @hw: pointer to the hw struct 7534 * @activity_id: ID of DNL activity to run 7535 * @dnl_opcode: opcode passed to DNL script 7536 * @cmd_status: pointer to memory to write return value of DNL script 7537 * @data0: pointer to memory for first 4 bytes of data returned by DNL script 7538 * @data1: pointer to memory for last 4 bytes of data returned by DNL script 7539 * @cmd_details: pointer to command details structure or NULL 7540 * 7541 * Run DNL admin command. 7542 **/ 7543 enum i40e_status_code 7544 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode, 7545 u32 *cmd_status, u32 *data0, u32 *data1, 7546 struct i40e_asq_cmd_details *cmd_details) 7547 { 7548 struct i40e_aqc_run_phy_activity *cmd; 7549 enum i40e_status_code retval; 7550 struct i40e_aq_desc desc; 7551 7552 cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw; 7553 7554 if (!cmd_status || !data0 || !data1) { 7555 retval = I40E_ERR_PARAM; 7556 goto err; 7557 } 7558 7559 i40e_fill_default_direct_cmd_desc(&desc, 7560 i40e_aqc_opc_run_phy_activity); 7561 7562 cmd->activity_id = CPU_TO_LE16(activity_id); 7563 cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode); 7564 7565 retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7566 if (retval) 7567 goto err; 7568 7569 *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status); 7570 *data0 = LE32_TO_CPU(cmd->params.resp.data0); 7571 *data1 = LE32_TO_CPU(cmd->params.resp.data1); 7572 err: 7573 return retval; 7574 } 7575 7576 #ifdef VF_DRIVER 7577 7578 /** 7579 * i40e_aq_send_msg_to_pf 7580 * @hw: pointer to the hardware structure 7581 * @v_opcode: opcodes for VF-PF communication 7582 * @v_retval: return error code 7583 * @msg: pointer to the msg buffer 7584 * @msglen: msg length 7585 * @cmd_details: pointer to command details 7586 * 7587 * Send message to PF driver using admin queue. By default, this message 7588 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 7589 * completion before returning. 7590 **/ 7591 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 7592 enum virtchnl_ops v_opcode, 7593 enum i40e_status_code v_retval, 7594 u8 *msg, u16 msglen, 7595 struct i40e_asq_cmd_details *cmd_details) 7596 { 7597 struct i40e_aq_desc desc; 7598 struct i40e_asq_cmd_details details; 7599 enum i40e_status_code status; 7600 7601 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 7602 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 7603 desc.cookie_high = CPU_TO_LE32(v_opcode); 7604 desc.cookie_low = CPU_TO_LE32(v_retval); 7605 if (msglen) { 7606 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 7607 | I40E_AQ_FLAG_RD)); 7608 if (msglen > I40E_AQ_LARGE_BUF) 7609 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7610 desc.datalen = CPU_TO_LE16(msglen); 7611 } 7612 if (!cmd_details) { 7613 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 7614 details.async = true; 7615 cmd_details = &details; 7616 } 7617 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 7618 msglen, cmd_details); 7619 return status; 7620 } 7621 7622 /** 7623 * i40e_vf_parse_hw_config 7624 * @hw: pointer to the hardware structure 7625 * @msg: pointer to the virtual channel VF resource structure 7626 * 7627 * Given a VF resource message from the PF, populate the hw struct 7628 * with appropriate information. 7629 **/ 7630 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 7631 struct virtchnl_vf_resource *msg) 7632 { 7633 struct virtchnl_vsi_resource *vsi_res; 7634 int i; 7635 7636 vsi_res = &msg->vsi_res[0]; 7637 7638 hw->dev_caps.num_vsis = msg->num_vsis; 7639 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 7640 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 7641 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 7642 hw->dev_caps.dcb = msg->vf_cap_flags & 7643 VIRTCHNL_VF_OFFLOAD_L2; 7644 hw->dev_caps.iwarp = (msg->vf_cap_flags & 7645 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 7646 for (i = 0; i < msg->num_vsis; i++) { 7647 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) { 7648 i40e_memcpy(hw->mac.perm_addr, 7649 vsi_res->default_mac_addr, 7650 ETH_ALEN, 7651 I40E_NONDMA_TO_NONDMA); 7652 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 7653 ETH_ALEN, 7654 I40E_NONDMA_TO_NONDMA); 7655 } 7656 vsi_res++; 7657 } 7658 } 7659 7660 /** 7661 * i40e_vf_reset 7662 * @hw: pointer to the hardware structure 7663 * 7664 * Send a VF_RESET message to the PF. Does not wait for response from PF 7665 * as none will be forthcoming. Immediately after calling this function, 7666 * the admin queue should be shut down and (optionally) reinitialized. 7667 **/ 7668 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 7669 { 7670 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, 7671 I40E_SUCCESS, NULL, 0, NULL); 7672 } 7673 #endif /* VF_DRIVER */ 7674 7675 /** 7676 * i40e_aq_set_arp_proxy_config 7677 * @hw: pointer to the HW structure 7678 * @proxy_config: pointer to proxy config command table struct 7679 * @cmd_details: pointer to command details 7680 * 7681 * Set ARP offload parameters from pre-populated 7682 * i40e_aqc_arp_proxy_data struct 7683 **/ 7684 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 7685 struct i40e_aqc_arp_proxy_data *proxy_config, 7686 struct i40e_asq_cmd_details *cmd_details) 7687 { 7688 struct i40e_aq_desc desc; 7689 enum i40e_status_code status; 7690 7691 if (!proxy_config) 7692 return I40E_ERR_PARAM; 7693 7694 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 7695 7696 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7697 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7698 desc.params.external.addr_high = 7699 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config)); 7700 desc.params.external.addr_low = 7701 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config)); 7702 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data)); 7703 7704 status = i40e_asq_send_command(hw, &desc, proxy_config, 7705 sizeof(struct i40e_aqc_arp_proxy_data), 7706 cmd_details); 7707 7708 return status; 7709 } 7710 7711 /** 7712 * i40e_aq_opc_set_ns_proxy_table_entry 7713 * @hw: pointer to the HW structure 7714 * @ns_proxy_table_entry: pointer to NS table entry command struct 7715 * @cmd_details: pointer to command details 7716 * 7717 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 7718 * from pre-populated i40e_aqc_ns_proxy_data struct 7719 **/ 7720 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 7721 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 7722 struct i40e_asq_cmd_details *cmd_details) 7723 { 7724 struct i40e_aq_desc desc; 7725 enum i40e_status_code status; 7726 7727 if (!ns_proxy_table_entry) 7728 return I40E_ERR_PARAM; 7729 7730 i40e_fill_default_direct_cmd_desc(&desc, 7731 i40e_aqc_opc_set_ns_proxy_table_entry); 7732 7733 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7734 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7735 desc.params.external.addr_high = 7736 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry)); 7737 desc.params.external.addr_low = 7738 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry)); 7739 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data)); 7740 7741 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 7742 sizeof(struct i40e_aqc_ns_proxy_data), 7743 cmd_details); 7744 7745 return status; 7746 } 7747 7748 /** 7749 * i40e_aq_set_clear_wol_filter 7750 * @hw: pointer to the hw struct 7751 * @filter_index: index of filter to modify (0-7) 7752 * @filter: buffer containing filter to be set 7753 * @set_filter: true to set filter, false to clear filter 7754 * @no_wol_tco: if true, pass through packets cannot cause wake-up 7755 * if false, pass through packets may cause wake-up 7756 * @filter_valid: true if filter action is valid 7757 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid 7758 * @cmd_details: pointer to command details structure or NULL 7759 * 7760 * Set or clear WoL filter for port attached to the PF 7761 **/ 7762 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 7763 u8 filter_index, 7764 struct i40e_aqc_set_wol_filter_data *filter, 7765 bool set_filter, bool no_wol_tco, 7766 bool filter_valid, bool no_wol_tco_valid, 7767 struct i40e_asq_cmd_details *cmd_details) 7768 { 7769 struct i40e_aq_desc desc; 7770 struct i40e_aqc_set_wol_filter *cmd = 7771 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 7772 enum i40e_status_code status; 7773 u16 cmd_flags = 0; 7774 u16 valid_flags = 0; 7775 u16 buff_len = 0; 7776 7777 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 7778 7779 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 7780 return I40E_ERR_PARAM; 7781 cmd->filter_index = CPU_TO_LE16(filter_index); 7782 7783 if (set_filter) { 7784 if (!filter) 7785 return I40E_ERR_PARAM; 7786 7787 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 7788 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR; 7789 } 7790 7791 if (no_wol_tco) 7792 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 7793 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 7794 7795 if (filter_valid) 7796 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 7797 if (no_wol_tco_valid) 7798 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 7799 cmd->valid_flags = CPU_TO_LE16(valid_flags); 7800 7801 buff_len = sizeof(*filter); 7802 desc.datalen = CPU_TO_LE16(buff_len); 7803 7804 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7805 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7806 7807 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter)); 7808 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter)); 7809 7810 status = i40e_asq_send_command(hw, &desc, filter, 7811 buff_len, cmd_details); 7812 7813 return status; 7814 } 7815 7816 /** 7817 * i40e_aq_get_wake_event_reason 7818 * @hw: pointer to the hw struct 7819 * @wake_reason: return value, index of matching filter 7820 * @cmd_details: pointer to command details structure or NULL 7821 * 7822 * Get information for the reason of a Wake Up event 7823 **/ 7824 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 7825 u16 *wake_reason, 7826 struct i40e_asq_cmd_details *cmd_details) 7827 { 7828 struct i40e_aq_desc desc; 7829 struct i40e_aqc_get_wake_reason_completion *resp = 7830 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 7831 enum i40e_status_code status; 7832 7833 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 7834 7835 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7836 7837 if (status == I40E_SUCCESS) 7838 *wake_reason = LE16_TO_CPU(resp->wake_reason); 7839 7840 return status; 7841 } 7842 7843 /** 7844 * i40e_aq_clear_all_wol_filters 7845 * @hw: pointer to the hw struct 7846 * @cmd_details: pointer to command details structure or NULL 7847 * 7848 * Get information for the reason of a Wake Up event 7849 **/ 7850 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw, 7851 struct i40e_asq_cmd_details *cmd_details) 7852 { 7853 struct i40e_aq_desc desc; 7854 enum i40e_status_code status; 7855 7856 i40e_fill_default_direct_cmd_desc(&desc, 7857 i40e_aqc_opc_clear_all_wol_filters); 7858 7859 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7860 7861 return status; 7862 } 7863 7864 /** 7865 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 7866 * @hw: pointer to the hw struct 7867 * @buff: command buffer (size in bytes = buff_size) 7868 * @buff_size: buffer size in bytes 7869 * @track_id: package tracking id 7870 * @error_offset: returns error offset 7871 * @error_info: returns error information 7872 * @cmd_details: pointer to command details structure or NULL 7873 **/ 7874 enum 7875 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 7876 u16 buff_size, u32 track_id, 7877 u32 *error_offset, u32 *error_info, 7878 struct i40e_asq_cmd_details *cmd_details) 7879 { 7880 struct i40e_aq_desc desc; 7881 struct i40e_aqc_write_personalization_profile *cmd = 7882 (struct i40e_aqc_write_personalization_profile *) 7883 &desc.params.raw; 7884 struct i40e_aqc_write_ddp_resp *resp; 7885 enum i40e_status_code status; 7886 7887 i40e_fill_default_direct_cmd_desc(&desc, 7888 i40e_aqc_opc_write_personalization_profile); 7889 7890 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 7891 if (buff_size > I40E_AQ_LARGE_BUF) 7892 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7893 7894 desc.datalen = CPU_TO_LE16(buff_size); 7895 7896 cmd->profile_track_id = CPU_TO_LE32(track_id); 7897 7898 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 7899 if (!status) { 7900 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 7901 if (error_offset) 7902 *error_offset = LE32_TO_CPU(resp->error_offset); 7903 if (error_info) 7904 *error_info = LE32_TO_CPU(resp->error_info); 7905 } 7906 7907 return status; 7908 } 7909 7910 /** 7911 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 7912 * @hw: pointer to the hw struct 7913 * @buff: command buffer (size in bytes = buff_size) 7914 * @buff_size: buffer size in bytes 7915 * @flags: AdminQ command flags 7916 * @cmd_details: pointer to command details structure or NULL 7917 **/ 7918 enum 7919 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 7920 u16 buff_size, u8 flags, 7921 struct i40e_asq_cmd_details *cmd_details) 7922 { 7923 struct i40e_aq_desc desc; 7924 struct i40e_aqc_get_applied_profiles *cmd = 7925 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 7926 enum i40e_status_code status; 7927 7928 i40e_fill_default_direct_cmd_desc(&desc, 7929 i40e_aqc_opc_get_personalization_profile_list); 7930 7931 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7932 if (buff_size > I40E_AQ_LARGE_BUF) 7933 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7934 desc.datalen = CPU_TO_LE16(buff_size); 7935 7936 cmd->flags = flags; 7937 7938 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 7939 7940 return status; 7941 } 7942 7943 /** 7944 * i40e_find_segment_in_package 7945 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 7946 * @pkg_hdr: pointer to the package header to be searched 7947 * 7948 * This function searches a package file for a particular segment type. On 7949 * success it returns a pointer to the segment header, otherwise it will 7950 * return NULL. 7951 **/ 7952 struct i40e_generic_seg_header * 7953 i40e_find_segment_in_package(u32 segment_type, 7954 struct i40e_package_header *pkg_hdr) 7955 { 7956 struct i40e_generic_seg_header *segment; 7957 u32 i; 7958 7959 /* Search all package segments for the requested segment type */ 7960 for (i = 0; i < pkg_hdr->segment_count; i++) { 7961 segment = 7962 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 7963 pkg_hdr->segment_offset[i]); 7964 7965 if (segment->type == segment_type) 7966 return segment; 7967 } 7968 7969 return NULL; 7970 } 7971 7972 /* Get section table in profile */ 7973 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 7974 do { \ 7975 struct i40e_profile_segment *p = (profile); \ 7976 u32 count; \ 7977 u32 *nvm; \ 7978 count = p->device_table_count; \ 7979 nvm = (u32 *)&p->device_table[count]; \ 7980 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 7981 } while (0) 7982 7983 /* Get section header in profile */ 7984 #define I40E_SECTION_HEADER(profile, offset) \ 7985 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 7986 7987 /** 7988 * i40e_find_section_in_profile 7989 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE) 7990 * @profile: pointer to the i40e segment header to be searched 7991 * 7992 * This function searches i40e segment for a particular section type. On 7993 * success it returns a pointer to the section header, otherwise it will 7994 * return NULL. 7995 **/ 7996 struct i40e_profile_section_header * 7997 i40e_find_section_in_profile(u32 section_type, 7998 struct i40e_profile_segment *profile) 7999 { 8000 struct i40e_profile_section_header *sec; 8001 struct i40e_section_table *sec_tbl; 8002 u32 sec_off; 8003 u32 i; 8004 8005 if (profile->header.type != SEGMENT_TYPE_I40E) 8006 return NULL; 8007 8008 I40E_SECTION_TABLE(profile, sec_tbl); 8009 8010 for (i = 0; i < sec_tbl->section_count; i++) { 8011 sec_off = sec_tbl->section_offset[i]; 8012 sec = I40E_SECTION_HEADER(profile, sec_off); 8013 if (sec->section.type == section_type) 8014 return sec; 8015 } 8016 8017 return NULL; 8018 } 8019 8020 /** 8021 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 8022 * @hw: pointer to the hw struct 8023 * @aq: command buffer containing all data to execute AQ 8024 **/ 8025 STATIC enum 8026 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw, 8027 struct i40e_profile_aq_section *aq) 8028 { 8029 enum i40e_status_code status; 8030 struct i40e_aq_desc desc; 8031 u8 *msg = NULL; 8032 u16 msglen; 8033 8034 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 8035 desc.flags |= CPU_TO_LE16(aq->flags); 8036 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw), 8037 I40E_NONDMA_TO_NONDMA); 8038 8039 msglen = aq->datalen; 8040 if (msglen) { 8041 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 8042 I40E_AQ_FLAG_RD)); 8043 if (msglen > I40E_AQ_LARGE_BUF) 8044 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 8045 desc.datalen = CPU_TO_LE16(msglen); 8046 msg = &aq->data[0]; 8047 } 8048 8049 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 8050 8051 if (status != I40E_SUCCESS) { 8052 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8053 "unable to exec DDP AQ opcode %u, error %d\n", 8054 aq->opcode, status); 8055 return status; 8056 } 8057 8058 /* copy returned desc to aq_buf */ 8059 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw), 8060 I40E_NONDMA_TO_NONDMA); 8061 8062 return I40E_SUCCESS; 8063 } 8064 8065 /** 8066 * i40e_validate_profile 8067 * @hw: pointer to the hardware structure 8068 * @profile: pointer to the profile segment of the package to be validated 8069 * @track_id: package tracking id 8070 * @rollback: flag if the profile is for rollback. 8071 * 8072 * Validates supported devices and profile's sections. 8073 */ 8074 STATIC enum i40e_status_code 8075 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 8076 u32 track_id, bool rollback) 8077 { 8078 struct i40e_profile_section_header *sec = NULL; 8079 enum i40e_status_code status = I40E_SUCCESS; 8080 struct i40e_section_table *sec_tbl; 8081 u32 vendor_dev_id; 8082 u32 dev_cnt; 8083 u32 sec_off; 8084 u32 i; 8085 8086 if (track_id == I40E_DDP_TRACKID_INVALID) { 8087 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 8088 return I40E_NOT_SUPPORTED; 8089 } 8090 8091 dev_cnt = profile->device_table_count; 8092 for (i = 0; i < dev_cnt; i++) { 8093 vendor_dev_id = profile->device_table[i].vendor_dev_id; 8094 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID && 8095 hw->device_id == (vendor_dev_id & 0xFFFF)) 8096 break; 8097 } 8098 if (dev_cnt && (i == dev_cnt)) { 8099 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8100 "Device doesn't support DDP\n"); 8101 return I40E_ERR_DEVICE_NOT_SUPPORTED; 8102 } 8103 8104 I40E_SECTION_TABLE(profile, sec_tbl); 8105 8106 /* Validate sections types */ 8107 for (i = 0; i < sec_tbl->section_count; i++) { 8108 sec_off = sec_tbl->section_offset[i]; 8109 sec = I40E_SECTION_HEADER(profile, sec_off); 8110 if (rollback) { 8111 if (sec->section.type == SECTION_TYPE_MMIO || 8112 sec->section.type == SECTION_TYPE_AQ || 8113 sec->section.type == SECTION_TYPE_RB_AQ) { 8114 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8115 "Not a roll-back package\n"); 8116 return I40E_NOT_SUPPORTED; 8117 } 8118 } else { 8119 if (sec->section.type == SECTION_TYPE_RB_AQ || 8120 sec->section.type == SECTION_TYPE_RB_MMIO) { 8121 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8122 "Not an original package\n"); 8123 return I40E_NOT_SUPPORTED; 8124 } 8125 } 8126 } 8127 8128 return status; 8129 } 8130 8131 /** 8132 * i40e_write_profile 8133 * @hw: pointer to the hardware structure 8134 * @profile: pointer to the profile segment of the package to be downloaded 8135 * @track_id: package tracking id 8136 * 8137 * Handles the download of a complete package. 8138 */ 8139 enum i40e_status_code 8140 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 8141 u32 track_id) 8142 { 8143 enum i40e_status_code status = I40E_SUCCESS; 8144 struct i40e_section_table *sec_tbl; 8145 struct i40e_profile_section_header *sec = NULL; 8146 struct i40e_profile_aq_section *ddp_aq; 8147 u32 section_size = 0; 8148 u32 offset = 0, info = 0; 8149 u32 sec_off; 8150 u32 i; 8151 8152 status = i40e_validate_profile(hw, profile, track_id, false); 8153 if (status) 8154 return status; 8155 8156 I40E_SECTION_TABLE(profile, sec_tbl); 8157 8158 for (i = 0; i < sec_tbl->section_count; i++) { 8159 sec_off = sec_tbl->section_offset[i]; 8160 sec = I40E_SECTION_HEADER(profile, sec_off); 8161 /* Process generic admin command */ 8162 if (sec->section.type == SECTION_TYPE_AQ) { 8163 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 8164 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 8165 if (status) { 8166 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8167 "Failed to execute aq: section %d, opcode %u\n", 8168 i, ddp_aq->opcode); 8169 break; 8170 } 8171 sec->section.type = SECTION_TYPE_RB_AQ; 8172 } 8173 8174 /* Skip any non-mmio sections */ 8175 if (sec->section.type != SECTION_TYPE_MMIO) 8176 continue; 8177 8178 section_size = sec->section.size + 8179 sizeof(struct i40e_profile_section_header); 8180 8181 /* Write MMIO section */ 8182 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 8183 track_id, &offset, &info, NULL); 8184 if (status) { 8185 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8186 "Failed to write profile: section %d, offset %d, info %d\n", 8187 i, offset, info); 8188 break; 8189 } 8190 } 8191 return status; 8192 } 8193 8194 /** 8195 * i40e_rollback_profile 8196 * @hw: pointer to the hardware structure 8197 * @profile: pointer to the profile segment of the package to be removed 8198 * @track_id: package tracking id 8199 * 8200 * Rolls back previously loaded package. 8201 */ 8202 enum i40e_status_code 8203 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 8204 u32 track_id) 8205 { 8206 struct i40e_profile_section_header *sec = NULL; 8207 enum i40e_status_code status = I40E_SUCCESS; 8208 struct i40e_section_table *sec_tbl; 8209 u32 offset = 0, info = 0; 8210 u32 section_size = 0; 8211 u32 sec_off; 8212 int i; 8213 8214 status = i40e_validate_profile(hw, profile, track_id, true); 8215 if (status) 8216 return status; 8217 8218 I40E_SECTION_TABLE(profile, sec_tbl); 8219 8220 /* For rollback write sections in reverse */ 8221 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 8222 sec_off = sec_tbl->section_offset[i]; 8223 sec = I40E_SECTION_HEADER(profile, sec_off); 8224 8225 /* Skip any non-rollback sections */ 8226 if (sec->section.type != SECTION_TYPE_RB_MMIO) 8227 continue; 8228 8229 section_size = sec->section.size + 8230 sizeof(struct i40e_profile_section_header); 8231 8232 /* Write roll-back MMIO section */ 8233 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 8234 track_id, &offset, &info, NULL); 8235 if (status) { 8236 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8237 "Failed to write profile: section %d, offset %d, info %d\n", 8238 i, offset, info); 8239 break; 8240 } 8241 } 8242 return status; 8243 } 8244 8245 /** 8246 * i40e_add_pinfo_to_list 8247 * @hw: pointer to the hardware structure 8248 * @profile: pointer to the profile segment of the package 8249 * @profile_info_sec: buffer for information section 8250 * @track_id: package tracking id 8251 * 8252 * Register a profile to the list of loaded profiles. 8253 */ 8254 enum i40e_status_code 8255 i40e_add_pinfo_to_list(struct i40e_hw *hw, 8256 struct i40e_profile_segment *profile, 8257 u8 *profile_info_sec, u32 track_id) 8258 { 8259 enum i40e_status_code status = I40E_SUCCESS; 8260 struct i40e_profile_section_header *sec = NULL; 8261 struct i40e_profile_info *pinfo; 8262 u32 offset = 0, info = 0; 8263 8264 sec = (struct i40e_profile_section_header *)profile_info_sec; 8265 sec->tbl_size = 1; 8266 sec->data_end = sizeof(struct i40e_profile_section_header) + 8267 sizeof(struct i40e_profile_info); 8268 sec->section.type = SECTION_TYPE_INFO; 8269 sec->section.offset = sizeof(struct i40e_profile_section_header); 8270 sec->section.size = sizeof(struct i40e_profile_info); 8271 pinfo = (struct i40e_profile_info *)(profile_info_sec + 8272 sec->section.offset); 8273 pinfo->track_id = track_id; 8274 pinfo->version = profile->version; 8275 pinfo->op = I40E_DDP_ADD_TRACKID; 8276 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE, 8277 I40E_NONDMA_TO_NONDMA); 8278 8279 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 8280 track_id, &offset, &info, NULL); 8281 return status; 8282 } 8283