1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #include <inttypes.h> 6 7 #include "i40e_type.h" 8 #include "i40e_adminq.h" 9 #include "i40e_prototype.h" 10 #include "virtchnl.h" 11 12 /** 13 * i40e_set_mac_type - Sets MAC type 14 * @hw: pointer to the HW structure 15 * 16 * This function sets the mac type of the adapter based on the 17 * vendor ID and device ID stored in the hw structure. 18 **/ 19 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 20 { 21 enum i40e_status_code status = I40E_SUCCESS; 22 23 DEBUGFUNC("i40e_set_mac_type\n"); 24 25 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 26 switch (hw->device_id) { 27 case I40E_DEV_ID_SFP_XL710: 28 case I40E_DEV_ID_QEMU: 29 case I40E_DEV_ID_KX_B: 30 case I40E_DEV_ID_KX_C: 31 case I40E_DEV_ID_QSFP_A: 32 case I40E_DEV_ID_QSFP_B: 33 case I40E_DEV_ID_QSFP_C: 34 case I40E_DEV_ID_10G_BASE_T: 35 case I40E_DEV_ID_10G_BASE_T4: 36 case I40E_DEV_ID_10G_BASE_T_BC: 37 case I40E_DEV_ID_10G_B: 38 case I40E_DEV_ID_10G_SFP: 39 case I40E_DEV_ID_5G_BASE_T_BC: 40 case I40E_DEV_ID_20G_KR2: 41 case I40E_DEV_ID_20G_KR2_A: 42 case I40E_DEV_ID_25G_B: 43 case I40E_DEV_ID_25G_SFP28: 44 case I40E_DEV_ID_X710_N3000: 45 case I40E_DEV_ID_XXV710_N3000: 46 hw->mac.type = I40E_MAC_XL710; 47 break; 48 #ifdef X722_A0_SUPPORT 49 case I40E_DEV_ID_X722_A0: 50 #endif 51 case I40E_DEV_ID_KX_X722: 52 case I40E_DEV_ID_QSFP_X722: 53 case I40E_DEV_ID_SFP_X722: 54 case I40E_DEV_ID_1G_BASE_T_X722: 55 case I40E_DEV_ID_10G_BASE_T_X722: 56 case I40E_DEV_ID_SFP_I_X722: 57 hw->mac.type = I40E_MAC_X722; 58 break; 59 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 60 case I40E_DEV_ID_X722_VF: 61 #ifdef X722_A0_SUPPORT 62 case I40E_DEV_ID_X722_A0_VF: 63 #endif 64 hw->mac.type = I40E_MAC_X722_VF; 65 break; 66 #endif /* INTEGRATED_VF || VF_DRIVER */ 67 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 68 case I40E_DEV_ID_VF: 69 case I40E_DEV_ID_VF_HV: 70 case I40E_DEV_ID_ADAPTIVE_VF: 71 hw->mac.type = I40E_MAC_VF; 72 break; 73 #endif 74 default: 75 hw->mac.type = I40E_MAC_GENERIC; 76 break; 77 } 78 } else { 79 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 80 } 81 82 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 83 hw->mac.type, status); 84 return status; 85 } 86 87 /** 88 * i40e_aq_str - convert AQ err code to a string 89 * @hw: pointer to the HW structure 90 * @aq_err: the AQ error code to convert 91 **/ 92 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 93 { 94 switch (aq_err) { 95 case I40E_AQ_RC_OK: 96 return "OK"; 97 case I40E_AQ_RC_EPERM: 98 return "I40E_AQ_RC_EPERM"; 99 case I40E_AQ_RC_ENOENT: 100 return "I40E_AQ_RC_ENOENT"; 101 case I40E_AQ_RC_ESRCH: 102 return "I40E_AQ_RC_ESRCH"; 103 case I40E_AQ_RC_EINTR: 104 return "I40E_AQ_RC_EINTR"; 105 case I40E_AQ_RC_EIO: 106 return "I40E_AQ_RC_EIO"; 107 case I40E_AQ_RC_ENXIO: 108 return "I40E_AQ_RC_ENXIO"; 109 case I40E_AQ_RC_E2BIG: 110 return "I40E_AQ_RC_E2BIG"; 111 case I40E_AQ_RC_EAGAIN: 112 return "I40E_AQ_RC_EAGAIN"; 113 case I40E_AQ_RC_ENOMEM: 114 return "I40E_AQ_RC_ENOMEM"; 115 case I40E_AQ_RC_EACCES: 116 return "I40E_AQ_RC_EACCES"; 117 case I40E_AQ_RC_EFAULT: 118 return "I40E_AQ_RC_EFAULT"; 119 case I40E_AQ_RC_EBUSY: 120 return "I40E_AQ_RC_EBUSY"; 121 case I40E_AQ_RC_EEXIST: 122 return "I40E_AQ_RC_EEXIST"; 123 case I40E_AQ_RC_EINVAL: 124 return "I40E_AQ_RC_EINVAL"; 125 case I40E_AQ_RC_ENOTTY: 126 return "I40E_AQ_RC_ENOTTY"; 127 case I40E_AQ_RC_ENOSPC: 128 return "I40E_AQ_RC_ENOSPC"; 129 case I40E_AQ_RC_ENOSYS: 130 return "I40E_AQ_RC_ENOSYS"; 131 case I40E_AQ_RC_ERANGE: 132 return "I40E_AQ_RC_ERANGE"; 133 case I40E_AQ_RC_EFLUSHED: 134 return "I40E_AQ_RC_EFLUSHED"; 135 case I40E_AQ_RC_BAD_ADDR: 136 return "I40E_AQ_RC_BAD_ADDR"; 137 case I40E_AQ_RC_EMODE: 138 return "I40E_AQ_RC_EMODE"; 139 case I40E_AQ_RC_EFBIG: 140 return "I40E_AQ_RC_EFBIG"; 141 } 142 143 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 144 return hw->err_str; 145 } 146 147 /** 148 * i40e_stat_str - convert status err code to a string 149 * @hw: pointer to the HW structure 150 * @stat_err: the status error code to convert 151 **/ 152 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 153 { 154 switch (stat_err) { 155 case I40E_SUCCESS: 156 return "OK"; 157 case I40E_ERR_NVM: 158 return "I40E_ERR_NVM"; 159 case I40E_ERR_NVM_CHECKSUM: 160 return "I40E_ERR_NVM_CHECKSUM"; 161 case I40E_ERR_PHY: 162 return "I40E_ERR_PHY"; 163 case I40E_ERR_CONFIG: 164 return "I40E_ERR_CONFIG"; 165 case I40E_ERR_PARAM: 166 return "I40E_ERR_PARAM"; 167 case I40E_ERR_MAC_TYPE: 168 return "I40E_ERR_MAC_TYPE"; 169 case I40E_ERR_UNKNOWN_PHY: 170 return "I40E_ERR_UNKNOWN_PHY"; 171 case I40E_ERR_LINK_SETUP: 172 return "I40E_ERR_LINK_SETUP"; 173 case I40E_ERR_ADAPTER_STOPPED: 174 return "I40E_ERR_ADAPTER_STOPPED"; 175 case I40E_ERR_INVALID_MAC_ADDR: 176 return "I40E_ERR_INVALID_MAC_ADDR"; 177 case I40E_ERR_DEVICE_NOT_SUPPORTED: 178 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 179 case I40E_ERR_MASTER_REQUESTS_PENDING: 180 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 181 case I40E_ERR_INVALID_LINK_SETTINGS: 182 return "I40E_ERR_INVALID_LINK_SETTINGS"; 183 case I40E_ERR_AUTONEG_NOT_COMPLETE: 184 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 185 case I40E_ERR_RESET_FAILED: 186 return "I40E_ERR_RESET_FAILED"; 187 case I40E_ERR_SWFW_SYNC: 188 return "I40E_ERR_SWFW_SYNC"; 189 case I40E_ERR_NO_AVAILABLE_VSI: 190 return "I40E_ERR_NO_AVAILABLE_VSI"; 191 case I40E_ERR_NO_MEMORY: 192 return "I40E_ERR_NO_MEMORY"; 193 case I40E_ERR_BAD_PTR: 194 return "I40E_ERR_BAD_PTR"; 195 case I40E_ERR_RING_FULL: 196 return "I40E_ERR_RING_FULL"; 197 case I40E_ERR_INVALID_PD_ID: 198 return "I40E_ERR_INVALID_PD_ID"; 199 case I40E_ERR_INVALID_QP_ID: 200 return "I40E_ERR_INVALID_QP_ID"; 201 case I40E_ERR_INVALID_CQ_ID: 202 return "I40E_ERR_INVALID_CQ_ID"; 203 case I40E_ERR_INVALID_CEQ_ID: 204 return "I40E_ERR_INVALID_CEQ_ID"; 205 case I40E_ERR_INVALID_AEQ_ID: 206 return "I40E_ERR_INVALID_AEQ_ID"; 207 case I40E_ERR_INVALID_SIZE: 208 return "I40E_ERR_INVALID_SIZE"; 209 case I40E_ERR_INVALID_ARP_INDEX: 210 return "I40E_ERR_INVALID_ARP_INDEX"; 211 case I40E_ERR_INVALID_FPM_FUNC_ID: 212 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 213 case I40E_ERR_QP_INVALID_MSG_SIZE: 214 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 215 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 216 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 217 case I40E_ERR_INVALID_FRAG_COUNT: 218 return "I40E_ERR_INVALID_FRAG_COUNT"; 219 case I40E_ERR_QUEUE_EMPTY: 220 return "I40E_ERR_QUEUE_EMPTY"; 221 case I40E_ERR_INVALID_ALIGNMENT: 222 return "I40E_ERR_INVALID_ALIGNMENT"; 223 case I40E_ERR_FLUSHED_QUEUE: 224 return "I40E_ERR_FLUSHED_QUEUE"; 225 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 226 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 227 case I40E_ERR_INVALID_IMM_DATA_SIZE: 228 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 229 case I40E_ERR_TIMEOUT: 230 return "I40E_ERR_TIMEOUT"; 231 case I40E_ERR_OPCODE_MISMATCH: 232 return "I40E_ERR_OPCODE_MISMATCH"; 233 case I40E_ERR_CQP_COMPL_ERROR: 234 return "I40E_ERR_CQP_COMPL_ERROR"; 235 case I40E_ERR_INVALID_VF_ID: 236 return "I40E_ERR_INVALID_VF_ID"; 237 case I40E_ERR_INVALID_HMCFN_ID: 238 return "I40E_ERR_INVALID_HMCFN_ID"; 239 case I40E_ERR_BACKING_PAGE_ERROR: 240 return "I40E_ERR_BACKING_PAGE_ERROR"; 241 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 242 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 243 case I40E_ERR_INVALID_PBLE_INDEX: 244 return "I40E_ERR_INVALID_PBLE_INDEX"; 245 case I40E_ERR_INVALID_SD_INDEX: 246 return "I40E_ERR_INVALID_SD_INDEX"; 247 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 248 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 249 case I40E_ERR_INVALID_SD_TYPE: 250 return "I40E_ERR_INVALID_SD_TYPE"; 251 case I40E_ERR_MEMCPY_FAILED: 252 return "I40E_ERR_MEMCPY_FAILED"; 253 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 254 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 255 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 256 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 257 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 258 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 259 case I40E_ERR_SRQ_ENABLED: 260 return "I40E_ERR_SRQ_ENABLED"; 261 case I40E_ERR_ADMIN_QUEUE_ERROR: 262 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 263 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 264 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 265 case I40E_ERR_BUF_TOO_SHORT: 266 return "I40E_ERR_BUF_TOO_SHORT"; 267 case I40E_ERR_ADMIN_QUEUE_FULL: 268 return "I40E_ERR_ADMIN_QUEUE_FULL"; 269 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 270 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 271 case I40E_ERR_BAD_IWARP_CQE: 272 return "I40E_ERR_BAD_IWARP_CQE"; 273 case I40E_ERR_NVM_BLANK_MODE: 274 return "I40E_ERR_NVM_BLANK_MODE"; 275 case I40E_ERR_NOT_IMPLEMENTED: 276 return "I40E_ERR_NOT_IMPLEMENTED"; 277 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 278 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 279 case I40E_ERR_DIAG_TEST_FAILED: 280 return "I40E_ERR_DIAG_TEST_FAILED"; 281 case I40E_ERR_NOT_READY: 282 return "I40E_ERR_NOT_READY"; 283 case I40E_NOT_SUPPORTED: 284 return "I40E_NOT_SUPPORTED"; 285 case I40E_ERR_FIRMWARE_API_VERSION: 286 return "I40E_ERR_FIRMWARE_API_VERSION"; 287 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 288 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 289 } 290 291 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 292 return hw->err_str; 293 } 294 295 /** 296 * i40e_debug_aq 297 * @hw: debug mask related to admin queue 298 * @mask: debug mask 299 * @desc: pointer to admin queue descriptor 300 * @buffer: pointer to command buffer 301 * @buf_len: max length of buffer 302 * 303 * Dumps debug log about adminq command with descriptor contents. 304 **/ 305 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 306 void *buffer, u16 buf_len) 307 { 308 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 309 u32 effective_mask = hw->debug_mask & mask; 310 u8 *buf = (u8 *)buffer; 311 u16 len; 312 u16 i; 313 314 if (!effective_mask || !desc) 315 return; 316 317 len = LE16_TO_CPU(aq_desc->datalen); 318 319 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 321 LE16_TO_CPU(aq_desc->opcode), 322 LE16_TO_CPU(aq_desc->flags), 323 LE16_TO_CPU(aq_desc->datalen), 324 LE16_TO_CPU(aq_desc->retval)); 325 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 326 "\tcookie (h,l) 0x%08X 0x%08X\n", 327 LE32_TO_CPU(aq_desc->cookie_high), 328 LE32_TO_CPU(aq_desc->cookie_low)); 329 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 330 "\tparam (0,1) 0x%08X 0x%08X\n", 331 LE32_TO_CPU(aq_desc->params.internal.param0), 332 LE32_TO_CPU(aq_desc->params.internal.param1)); 333 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 334 "\taddr (h,l) 0x%08X 0x%08X\n", 335 LE32_TO_CPU(aq_desc->params.external.addr_high), 336 LE32_TO_CPU(aq_desc->params.external.addr_low)); 337 338 if (buffer && (buf_len != 0) && (len != 0) && 339 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 340 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 341 if (buf_len < len) 342 len = buf_len; 343 /* write the full 16-byte chunks */ 344 for (i = 0; i < (len - 16); i += 16) 345 i40e_debug(hw, mask, 346 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 347 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 348 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 349 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 350 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 351 /* the most we could have left is 16 bytes, pad with zeros */ 352 if (i < len) { 353 char d_buf[16]; 354 int j, i_sav; 355 356 i_sav = i; 357 memset(d_buf, 0, sizeof(d_buf)); 358 for (j = 0; i < len; j++, i++) 359 d_buf[j] = buf[i]; 360 i40e_debug(hw, mask, 361 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 362 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 363 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 364 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 365 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 366 } 367 } 368 } 369 370 /** 371 * i40e_check_asq_alive 372 * @hw: pointer to the hw struct 373 * 374 * Returns true if Queue is enabled else false. 375 **/ 376 bool i40e_check_asq_alive(struct i40e_hw *hw) 377 { 378 if (hw->aq.asq.len) 379 #ifdef PF_DRIVER 380 #ifdef INTEGRATED_VF 381 if (!i40e_is_vf(hw)) 382 return !!(rd32(hw, hw->aq.asq.len) & 383 I40E_PF_ATQLEN_ATQENABLE_MASK); 384 #else 385 return !!(rd32(hw, hw->aq.asq.len) & 386 I40E_PF_ATQLEN_ATQENABLE_MASK); 387 #endif /* INTEGRATED_VF */ 388 #endif /* PF_DRIVER */ 389 #ifdef VF_DRIVER 390 #ifdef INTEGRATED_VF 391 if (i40e_is_vf(hw)) 392 return !!(rd32(hw, hw->aq.asq.len) & 393 I40E_VF_ATQLEN1_ATQENABLE_MASK); 394 #else 395 return !!(rd32(hw, hw->aq.asq.len) & 396 I40E_VF_ATQLEN1_ATQENABLE_MASK); 397 #endif /* INTEGRATED_VF */ 398 #endif /* VF_DRIVER */ 399 return false; 400 } 401 402 /** 403 * i40e_aq_queue_shutdown 404 * @hw: pointer to the hw struct 405 * @unloading: is the driver unloading itself 406 * 407 * Tell the Firmware that we're shutting down the AdminQ and whether 408 * or not the driver is unloading as well. 409 **/ 410 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 411 bool unloading) 412 { 413 struct i40e_aq_desc desc; 414 struct i40e_aqc_queue_shutdown *cmd = 415 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 416 enum i40e_status_code status; 417 418 i40e_fill_default_direct_cmd_desc(&desc, 419 i40e_aqc_opc_queue_shutdown); 420 421 if (unloading) 422 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 423 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 424 425 return status; 426 } 427 428 /** 429 * i40e_aq_get_set_rss_lut 430 * @hw: pointer to the hardware structure 431 * @vsi_id: vsi fw index 432 * @pf_lut: for PF table set true, for VSI table set false 433 * @lut: pointer to the lut buffer provided by the caller 434 * @lut_size: size of the lut buffer 435 * @set: set true to set the table, false to get the table 436 * 437 * Internal function to get or set RSS look up table 438 **/ 439 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 440 u16 vsi_id, bool pf_lut, 441 u8 *lut, u16 lut_size, 442 bool set) 443 { 444 enum i40e_status_code status; 445 struct i40e_aq_desc desc; 446 struct i40e_aqc_get_set_rss_lut *cmd_resp = 447 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 448 449 if (set) 450 i40e_fill_default_direct_cmd_desc(&desc, 451 i40e_aqc_opc_set_rss_lut); 452 else 453 i40e_fill_default_direct_cmd_desc(&desc, 454 i40e_aqc_opc_get_rss_lut); 455 456 /* Indirect command */ 457 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 458 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 459 460 cmd_resp->vsi_id = 461 CPU_TO_LE16((u16)((vsi_id << 462 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 463 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 464 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 465 466 if (pf_lut) 467 cmd_resp->flags |= CPU_TO_LE16((u16) 468 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 469 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 470 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 471 else 472 cmd_resp->flags |= CPU_TO_LE16((u16) 473 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 474 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 475 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 476 477 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 478 479 return status; 480 } 481 482 /** 483 * i40e_aq_get_rss_lut 484 * @hw: pointer to the hardware structure 485 * @vsi_id: vsi fw index 486 * @pf_lut: for PF table set true, for VSI table set false 487 * @lut: pointer to the lut buffer provided by the caller 488 * @lut_size: size of the lut buffer 489 * 490 * get the RSS lookup table, PF or VSI type 491 **/ 492 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 493 bool pf_lut, u8 *lut, u16 lut_size) 494 { 495 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 496 false); 497 } 498 499 /** 500 * i40e_aq_set_rss_lut 501 * @hw: pointer to the hardware structure 502 * @vsi_id: vsi fw index 503 * @pf_lut: for PF table set true, for VSI table set false 504 * @lut: pointer to the lut buffer provided by the caller 505 * @lut_size: size of the lut buffer 506 * 507 * set the RSS lookup table, PF or VSI type 508 **/ 509 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 510 bool pf_lut, u8 *lut, u16 lut_size) 511 { 512 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 513 } 514 515 /** 516 * i40e_aq_get_set_rss_key 517 * @hw: pointer to the hw struct 518 * @vsi_id: vsi fw index 519 * @key: pointer to key info struct 520 * @set: set true to set the key, false to get the key 521 * 522 * get the RSS key per VSI 523 **/ 524 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 525 u16 vsi_id, 526 struct i40e_aqc_get_set_rss_key_data *key, 527 bool set) 528 { 529 enum i40e_status_code status; 530 struct i40e_aq_desc desc; 531 struct i40e_aqc_get_set_rss_key *cmd_resp = 532 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 533 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 534 535 if (set) 536 i40e_fill_default_direct_cmd_desc(&desc, 537 i40e_aqc_opc_set_rss_key); 538 else 539 i40e_fill_default_direct_cmd_desc(&desc, 540 i40e_aqc_opc_get_rss_key); 541 542 /* Indirect command */ 543 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 544 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 545 546 cmd_resp->vsi_id = 547 CPU_TO_LE16((u16)((vsi_id << 548 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 549 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 550 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 551 552 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 553 554 return status; 555 } 556 557 /** 558 * i40e_aq_get_rss_key 559 * @hw: pointer to the hw struct 560 * @vsi_id: vsi fw index 561 * @key: pointer to key info struct 562 * 563 **/ 564 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 565 u16 vsi_id, 566 struct i40e_aqc_get_set_rss_key_data *key) 567 { 568 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 569 } 570 571 /** 572 * i40e_aq_set_rss_key 573 * @hw: pointer to the hw struct 574 * @vsi_id: vsi fw index 575 * @key: pointer to key info struct 576 * 577 * set the RSS key per VSI 578 **/ 579 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 580 u16 vsi_id, 581 struct i40e_aqc_get_set_rss_key_data *key) 582 { 583 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 584 } 585 586 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 587 * hardware to a bit-field that can be used by SW to more easily determine the 588 * packet type. 589 * 590 * Macros are used to shorten the table lines and make this table human 591 * readable. 592 * 593 * We store the PTYPE in the top byte of the bit field - this is just so that 594 * we can check that the table doesn't have a row missing, as the index into 595 * the table should be the PTYPE. 596 * 597 * Typical work flow: 598 * 599 * IF NOT i40e_ptype_lookup[ptype].known 600 * THEN 601 * Packet is unknown 602 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 603 * Use the rest of the fields to look at the tunnels, inner protocols, etc 604 * ELSE 605 * Use the enum i40e_rx_l2_ptype to decode the packet type 606 * ENDIF 607 */ 608 609 /* macro to make the table lines short */ 610 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 611 { PTYPE, \ 612 1, \ 613 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 614 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 615 I40E_RX_PTYPE_##OUTER_FRAG, \ 616 I40E_RX_PTYPE_TUNNEL_##T, \ 617 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 618 I40E_RX_PTYPE_##TEF, \ 619 I40E_RX_PTYPE_INNER_PROT_##I, \ 620 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 621 622 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 623 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 624 625 /* shorter macros makes the table fit but are terse */ 626 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 627 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 628 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 629 630 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 631 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 632 /* L2 Packet types */ 633 I40E_PTT_UNUSED_ENTRY(0), 634 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 635 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 636 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 637 I40E_PTT_UNUSED_ENTRY(4), 638 I40E_PTT_UNUSED_ENTRY(5), 639 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 640 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 641 I40E_PTT_UNUSED_ENTRY(8), 642 I40E_PTT_UNUSED_ENTRY(9), 643 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 644 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 645 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 646 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 647 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 648 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 649 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 650 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 651 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 652 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 653 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 654 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 655 656 /* Non Tunneled IPv4 */ 657 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 658 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 659 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 660 I40E_PTT_UNUSED_ENTRY(25), 661 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 662 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 663 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 664 665 /* IPv4 --> IPv4 */ 666 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 667 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 668 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(32), 670 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 671 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 672 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 673 674 /* IPv4 --> IPv6 */ 675 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 676 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 677 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 678 I40E_PTT_UNUSED_ENTRY(39), 679 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 680 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 681 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 682 683 /* IPv4 --> GRE/NAT */ 684 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 685 686 /* IPv4 --> GRE/NAT --> IPv4 */ 687 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 688 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 689 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(47), 691 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 692 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 693 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 694 695 /* IPv4 --> GRE/NAT --> IPv6 */ 696 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 697 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 698 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 699 I40E_PTT_UNUSED_ENTRY(54), 700 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 701 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 702 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 703 704 /* IPv4 --> GRE/NAT --> MAC */ 705 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 706 707 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 708 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 709 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 710 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 711 I40E_PTT_UNUSED_ENTRY(62), 712 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 713 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 714 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 715 716 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 717 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 718 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 719 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 720 I40E_PTT_UNUSED_ENTRY(69), 721 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 722 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 723 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 724 725 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 726 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 727 728 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 729 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 730 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 731 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 732 I40E_PTT_UNUSED_ENTRY(77), 733 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 734 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 735 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 736 737 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 738 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 739 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 740 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 741 I40E_PTT_UNUSED_ENTRY(84), 742 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 743 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 744 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 745 746 /* Non Tunneled IPv6 */ 747 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 748 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 749 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 750 I40E_PTT_UNUSED_ENTRY(91), 751 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 752 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 753 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 754 755 /* IPv6 --> IPv4 */ 756 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 757 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 758 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(98), 760 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 761 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 762 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 763 764 /* IPv6 --> IPv6 */ 765 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 766 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 767 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 768 I40E_PTT_UNUSED_ENTRY(105), 769 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 770 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 771 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 772 773 /* IPv6 --> GRE/NAT */ 774 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 775 776 /* IPv6 --> GRE/NAT -> IPv4 */ 777 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 778 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 779 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(113), 781 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 782 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 783 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> IPv6 */ 786 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 787 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 788 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 789 I40E_PTT_UNUSED_ENTRY(120), 790 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 791 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 792 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 793 794 /* IPv6 --> GRE/NAT -> MAC */ 795 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 796 797 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 798 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 799 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 800 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 801 I40E_PTT_UNUSED_ENTRY(128), 802 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 803 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 804 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 805 806 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 807 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 808 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 809 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 810 I40E_PTT_UNUSED_ENTRY(135), 811 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 812 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 813 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 814 815 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 816 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 817 818 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 819 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 820 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 821 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 822 I40E_PTT_UNUSED_ENTRY(143), 823 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 824 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 825 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 826 827 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 828 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 829 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 830 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 831 I40E_PTT_UNUSED_ENTRY(150), 832 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 833 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 834 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 835 836 /* unused entries */ 837 I40E_PTT_UNUSED_ENTRY(154), 838 I40E_PTT_UNUSED_ENTRY(155), 839 I40E_PTT_UNUSED_ENTRY(156), 840 I40E_PTT_UNUSED_ENTRY(157), 841 I40E_PTT_UNUSED_ENTRY(158), 842 I40E_PTT_UNUSED_ENTRY(159), 843 844 I40E_PTT_UNUSED_ENTRY(160), 845 I40E_PTT_UNUSED_ENTRY(161), 846 I40E_PTT_UNUSED_ENTRY(162), 847 I40E_PTT_UNUSED_ENTRY(163), 848 I40E_PTT_UNUSED_ENTRY(164), 849 I40E_PTT_UNUSED_ENTRY(165), 850 I40E_PTT_UNUSED_ENTRY(166), 851 I40E_PTT_UNUSED_ENTRY(167), 852 I40E_PTT_UNUSED_ENTRY(168), 853 I40E_PTT_UNUSED_ENTRY(169), 854 855 I40E_PTT_UNUSED_ENTRY(170), 856 I40E_PTT_UNUSED_ENTRY(171), 857 I40E_PTT_UNUSED_ENTRY(172), 858 I40E_PTT_UNUSED_ENTRY(173), 859 I40E_PTT_UNUSED_ENTRY(174), 860 I40E_PTT_UNUSED_ENTRY(175), 861 I40E_PTT_UNUSED_ENTRY(176), 862 I40E_PTT_UNUSED_ENTRY(177), 863 I40E_PTT_UNUSED_ENTRY(178), 864 I40E_PTT_UNUSED_ENTRY(179), 865 866 I40E_PTT_UNUSED_ENTRY(180), 867 I40E_PTT_UNUSED_ENTRY(181), 868 I40E_PTT_UNUSED_ENTRY(182), 869 I40E_PTT_UNUSED_ENTRY(183), 870 I40E_PTT_UNUSED_ENTRY(184), 871 I40E_PTT_UNUSED_ENTRY(185), 872 I40E_PTT_UNUSED_ENTRY(186), 873 I40E_PTT_UNUSED_ENTRY(187), 874 I40E_PTT_UNUSED_ENTRY(188), 875 I40E_PTT_UNUSED_ENTRY(189), 876 877 I40E_PTT_UNUSED_ENTRY(190), 878 I40E_PTT_UNUSED_ENTRY(191), 879 I40E_PTT_UNUSED_ENTRY(192), 880 I40E_PTT_UNUSED_ENTRY(193), 881 I40E_PTT_UNUSED_ENTRY(194), 882 I40E_PTT_UNUSED_ENTRY(195), 883 I40E_PTT_UNUSED_ENTRY(196), 884 I40E_PTT_UNUSED_ENTRY(197), 885 I40E_PTT_UNUSED_ENTRY(198), 886 I40E_PTT_UNUSED_ENTRY(199), 887 888 I40E_PTT_UNUSED_ENTRY(200), 889 I40E_PTT_UNUSED_ENTRY(201), 890 I40E_PTT_UNUSED_ENTRY(202), 891 I40E_PTT_UNUSED_ENTRY(203), 892 I40E_PTT_UNUSED_ENTRY(204), 893 I40E_PTT_UNUSED_ENTRY(205), 894 I40E_PTT_UNUSED_ENTRY(206), 895 I40E_PTT_UNUSED_ENTRY(207), 896 I40E_PTT_UNUSED_ENTRY(208), 897 I40E_PTT_UNUSED_ENTRY(209), 898 899 I40E_PTT_UNUSED_ENTRY(210), 900 I40E_PTT_UNUSED_ENTRY(211), 901 I40E_PTT_UNUSED_ENTRY(212), 902 I40E_PTT_UNUSED_ENTRY(213), 903 I40E_PTT_UNUSED_ENTRY(214), 904 I40E_PTT_UNUSED_ENTRY(215), 905 I40E_PTT_UNUSED_ENTRY(216), 906 I40E_PTT_UNUSED_ENTRY(217), 907 I40E_PTT_UNUSED_ENTRY(218), 908 I40E_PTT_UNUSED_ENTRY(219), 909 910 I40E_PTT_UNUSED_ENTRY(220), 911 I40E_PTT_UNUSED_ENTRY(221), 912 I40E_PTT_UNUSED_ENTRY(222), 913 I40E_PTT_UNUSED_ENTRY(223), 914 I40E_PTT_UNUSED_ENTRY(224), 915 I40E_PTT_UNUSED_ENTRY(225), 916 I40E_PTT_UNUSED_ENTRY(226), 917 I40E_PTT_UNUSED_ENTRY(227), 918 I40E_PTT_UNUSED_ENTRY(228), 919 I40E_PTT_UNUSED_ENTRY(229), 920 921 I40E_PTT_UNUSED_ENTRY(230), 922 I40E_PTT_UNUSED_ENTRY(231), 923 I40E_PTT_UNUSED_ENTRY(232), 924 I40E_PTT_UNUSED_ENTRY(233), 925 I40E_PTT_UNUSED_ENTRY(234), 926 I40E_PTT_UNUSED_ENTRY(235), 927 I40E_PTT_UNUSED_ENTRY(236), 928 I40E_PTT_UNUSED_ENTRY(237), 929 I40E_PTT_UNUSED_ENTRY(238), 930 I40E_PTT_UNUSED_ENTRY(239), 931 932 I40E_PTT_UNUSED_ENTRY(240), 933 I40E_PTT_UNUSED_ENTRY(241), 934 I40E_PTT_UNUSED_ENTRY(242), 935 I40E_PTT_UNUSED_ENTRY(243), 936 I40E_PTT_UNUSED_ENTRY(244), 937 I40E_PTT_UNUSED_ENTRY(245), 938 I40E_PTT_UNUSED_ENTRY(246), 939 I40E_PTT_UNUSED_ENTRY(247), 940 I40E_PTT_UNUSED_ENTRY(248), 941 I40E_PTT_UNUSED_ENTRY(249), 942 943 I40E_PTT_UNUSED_ENTRY(250), 944 I40E_PTT_UNUSED_ENTRY(251), 945 I40E_PTT_UNUSED_ENTRY(252), 946 I40E_PTT_UNUSED_ENTRY(253), 947 I40E_PTT_UNUSED_ENTRY(254), 948 I40E_PTT_UNUSED_ENTRY(255) 949 }; 950 951 952 /** 953 * i40e_validate_mac_addr - Validate unicast MAC address 954 * @mac_addr: pointer to MAC address 955 * 956 * Tests a MAC address to ensure it is a valid Individual Address 957 **/ 958 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 959 { 960 enum i40e_status_code status = I40E_SUCCESS; 961 962 DEBUGFUNC("i40e_validate_mac_addr"); 963 964 /* Broadcast addresses ARE multicast addresses 965 * Make sure it is not a multicast address 966 * Reject the zero address 967 */ 968 if (I40E_IS_MULTICAST(mac_addr) || 969 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 970 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 971 status = I40E_ERR_INVALID_MAC_ADDR; 972 973 return status; 974 } 975 #ifdef PF_DRIVER 976 977 /** 978 * i40e_init_shared_code - Initialize the shared code 979 * @hw: pointer to hardware structure 980 * 981 * This assigns the MAC type and PHY code and inits the NVM. 982 * Does not touch the hardware. This function must be called prior to any 983 * other function in the shared code. The i40e_hw structure should be 984 * memset to 0 prior to calling this function. The following fields in 985 * hw structure should be filled in prior to calling this function: 986 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 987 * subsystem_vendor_id, and revision_id 988 **/ 989 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 990 { 991 enum i40e_status_code status = I40E_SUCCESS; 992 u32 port, ari, func_rid; 993 994 DEBUGFUNC("i40e_init_shared_code"); 995 996 i40e_set_mac_type(hw); 997 998 switch (hw->mac.type) { 999 case I40E_MAC_XL710: 1000 case I40E_MAC_X722: 1001 break; 1002 default: 1003 return I40E_ERR_DEVICE_NOT_SUPPORTED; 1004 } 1005 1006 hw->phy.get_link_info = true; 1007 1008 /* Determine port number and PF number*/ 1009 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 1010 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1011 hw->port = (u8)port; 1012 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 1013 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1014 func_rid = rd32(hw, I40E_PF_FUNC_RID); 1015 if (ari) 1016 hw->pf_id = (u8)(func_rid & 0xff); 1017 else 1018 hw->pf_id = (u8)(func_rid & 0x7); 1019 1020 if (hw->mac.type == I40E_MAC_X722) 1021 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 1022 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 1023 /* NVMUpdate features structure initialization */ 1024 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR; 1025 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR; 1026 hw->nvmupd_features.size = sizeof(hw->nvmupd_features); 1027 i40e_memset(hw->nvmupd_features.features, 0x0, 1028 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN * 1029 sizeof(*hw->nvmupd_features.features), 1030 I40E_NONDMA_MEM); 1031 1032 /* No features supported at the moment */ 1033 hw->nvmupd_features.features[0] = 0; 1034 1035 status = i40e_init_nvm(hw); 1036 return status; 1037 } 1038 1039 /** 1040 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1041 * @hw: pointer to the hw struct 1042 * @flags: a return indicator of what addresses were added to the addr store 1043 * @addrs: the requestor's mac addr store 1044 * @cmd_details: pointer to command details structure or NULL 1045 **/ 1046 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1047 u16 *flags, 1048 struct i40e_aqc_mac_address_read_data *addrs, 1049 struct i40e_asq_cmd_details *cmd_details) 1050 { 1051 struct i40e_aq_desc desc; 1052 struct i40e_aqc_mac_address_read *cmd_data = 1053 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1054 enum i40e_status_code status; 1055 1056 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1057 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1058 1059 status = i40e_asq_send_command(hw, &desc, addrs, 1060 sizeof(*addrs), cmd_details); 1061 *flags = LE16_TO_CPU(cmd_data->command_flags); 1062 1063 return status; 1064 } 1065 1066 /** 1067 * i40e_aq_mac_address_write - Change the MAC addresses 1068 * @hw: pointer to the hw struct 1069 * @flags: indicates which MAC to be written 1070 * @mac_addr: address to write 1071 * @cmd_details: pointer to command details structure or NULL 1072 **/ 1073 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1074 u16 flags, u8 *mac_addr, 1075 struct i40e_asq_cmd_details *cmd_details) 1076 { 1077 struct i40e_aq_desc desc; 1078 struct i40e_aqc_mac_address_write *cmd_data = 1079 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1080 enum i40e_status_code status; 1081 1082 i40e_fill_default_direct_cmd_desc(&desc, 1083 i40e_aqc_opc_mac_address_write); 1084 cmd_data->command_flags = CPU_TO_LE16(flags); 1085 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1086 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1087 ((u32)mac_addr[3] << 16) | 1088 ((u32)mac_addr[4] << 8) | 1089 mac_addr[5]); 1090 1091 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1092 1093 return status; 1094 } 1095 1096 /** 1097 * i40e_get_mac_addr - get MAC address 1098 * @hw: pointer to the HW structure 1099 * @mac_addr: pointer to MAC address 1100 * 1101 * Reads the adapter's MAC address from register 1102 **/ 1103 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1104 { 1105 struct i40e_aqc_mac_address_read_data addrs; 1106 enum i40e_status_code status; 1107 u16 flags = 0; 1108 1109 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1110 1111 if (flags & I40E_AQC_LAN_ADDR_VALID) 1112 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1113 I40E_NONDMA_TO_NONDMA); 1114 1115 return status; 1116 } 1117 1118 /** 1119 * i40e_get_port_mac_addr - get Port MAC address 1120 * @hw: pointer to the HW structure 1121 * @mac_addr: pointer to Port MAC address 1122 * 1123 * Reads the adapter's Port MAC address 1124 **/ 1125 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1126 { 1127 struct i40e_aqc_mac_address_read_data addrs; 1128 enum i40e_status_code status; 1129 u16 flags = 0; 1130 1131 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1132 if (status) 1133 return status; 1134 1135 if (flags & I40E_AQC_PORT_ADDR_VALID) 1136 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1137 I40E_NONDMA_TO_NONDMA); 1138 else 1139 status = I40E_ERR_INVALID_MAC_ADDR; 1140 1141 return status; 1142 } 1143 1144 /** 1145 * i40e_pre_tx_queue_cfg - pre tx queue configure 1146 * @hw: pointer to the HW structure 1147 * @queue: target pf queue index 1148 * @enable: state change request 1149 * 1150 * Handles hw requirement to indicate intention to enable 1151 * or disable target queue. 1152 **/ 1153 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1154 { 1155 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1156 u32 reg_block = 0; 1157 u32 reg_val; 1158 1159 if (abs_queue_idx >= 128) { 1160 reg_block = abs_queue_idx / 128; 1161 abs_queue_idx %= 128; 1162 } 1163 1164 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1165 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1166 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1167 1168 if (enable) 1169 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1170 else 1171 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1172 1173 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1174 } 1175 1176 /** 1177 * i40e_get_san_mac_addr - get SAN MAC address 1178 * @hw: pointer to the HW structure 1179 * @mac_addr: pointer to SAN MAC address 1180 * 1181 * Reads the adapter's SAN MAC address from NVM 1182 **/ 1183 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw, 1184 u8 *mac_addr) 1185 { 1186 struct i40e_aqc_mac_address_read_data addrs; 1187 enum i40e_status_code status; 1188 u16 flags = 0; 1189 1190 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1191 if (status) 1192 return status; 1193 1194 if (flags & I40E_AQC_SAN_ADDR_VALID) 1195 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac), 1196 I40E_NONDMA_TO_NONDMA); 1197 else 1198 status = I40E_ERR_INVALID_MAC_ADDR; 1199 1200 return status; 1201 } 1202 1203 /** 1204 * i40e_read_pba_string - Reads part number string from EEPROM 1205 * @hw: pointer to hardware structure 1206 * @pba_num: stores the part number string from the EEPROM 1207 * @pba_num_size: part number string buffer length 1208 * 1209 * Reads the part number string from the EEPROM. 1210 **/ 1211 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1212 u32 pba_num_size) 1213 { 1214 enum i40e_status_code status = I40E_SUCCESS; 1215 u16 pba_word = 0; 1216 u16 pba_size = 0; 1217 u16 pba_ptr = 0; 1218 u16 i = 0; 1219 1220 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1221 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1222 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1223 return status; 1224 } 1225 1226 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1227 if (status != I40E_SUCCESS) { 1228 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1229 return status; 1230 } 1231 1232 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1233 if (status != I40E_SUCCESS) { 1234 DEBUGOUT("Failed to read PBA Block size.\n"); 1235 return status; 1236 } 1237 1238 /* Subtract one to get PBA word count (PBA Size word is included in 1239 * total size) 1240 */ 1241 pba_size--; 1242 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1243 DEBUGOUT("Buffer to small for PBA data.\n"); 1244 return I40E_ERR_PARAM; 1245 } 1246 1247 for (i = 0; i < pba_size; i++) { 1248 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1249 if (status != I40E_SUCCESS) { 1250 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1251 return status; 1252 } 1253 1254 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1255 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1256 } 1257 pba_num[(pba_size * 2)] = '\0'; 1258 1259 return status; 1260 } 1261 1262 /** 1263 * i40e_get_media_type - Gets media type 1264 * @hw: pointer to the hardware structure 1265 **/ 1266 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1267 { 1268 enum i40e_media_type media; 1269 1270 switch (hw->phy.link_info.phy_type) { 1271 case I40E_PHY_TYPE_10GBASE_SR: 1272 case I40E_PHY_TYPE_10GBASE_LR: 1273 case I40E_PHY_TYPE_1000BASE_SX: 1274 case I40E_PHY_TYPE_1000BASE_LX: 1275 case I40E_PHY_TYPE_40GBASE_SR4: 1276 case I40E_PHY_TYPE_40GBASE_LR4: 1277 case I40E_PHY_TYPE_25GBASE_LR: 1278 case I40E_PHY_TYPE_25GBASE_SR: 1279 case I40E_PHY_TYPE_10GBASE_AOC: 1280 case I40E_PHY_TYPE_25GBASE_AOC: 1281 case I40E_PHY_TYPE_40GBASE_AOC: 1282 media = I40E_MEDIA_TYPE_FIBER; 1283 break; 1284 case I40E_PHY_TYPE_100BASE_TX: 1285 case I40E_PHY_TYPE_1000BASE_T: 1286 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS: 1287 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS: 1288 case I40E_PHY_TYPE_10GBASE_T: 1289 media = I40E_MEDIA_TYPE_BASET; 1290 break; 1291 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1292 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1293 case I40E_PHY_TYPE_10GBASE_CR1: 1294 case I40E_PHY_TYPE_40GBASE_CR4: 1295 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1296 case I40E_PHY_TYPE_25GBASE_CR: 1297 case I40E_PHY_TYPE_25GBASE_ACC: 1298 media = I40E_MEDIA_TYPE_DA; 1299 break; 1300 case I40E_PHY_TYPE_1000BASE_KX: 1301 case I40E_PHY_TYPE_10GBASE_KX4: 1302 case I40E_PHY_TYPE_10GBASE_KR: 1303 case I40E_PHY_TYPE_40GBASE_KR4: 1304 case I40E_PHY_TYPE_20GBASE_KR2: 1305 case I40E_PHY_TYPE_25GBASE_KR: 1306 media = I40E_MEDIA_TYPE_BACKPLANE; 1307 break; 1308 case I40E_PHY_TYPE_SGMII: 1309 case I40E_PHY_TYPE_XAUI: 1310 case I40E_PHY_TYPE_XFI: 1311 case I40E_PHY_TYPE_XLAUI: 1312 case I40E_PHY_TYPE_XLPPI: 1313 default: 1314 media = I40E_MEDIA_TYPE_UNKNOWN; 1315 break; 1316 } 1317 1318 return media; 1319 } 1320 1321 /** 1322 * i40e_poll_globr - Poll for Global Reset completion 1323 * @hw: pointer to the hardware structure 1324 * @retry_limit: how many times to retry before failure 1325 **/ 1326 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw, 1327 u32 retry_limit) 1328 { 1329 u32 cnt, reg = 0; 1330 1331 for (cnt = 0; cnt < retry_limit; cnt++) { 1332 reg = rd32(hw, I40E_GLGEN_RSTAT); 1333 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1334 return I40E_SUCCESS; 1335 i40e_msec_delay(100); 1336 } 1337 1338 DEBUGOUT("Global reset failed.\n"); 1339 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg); 1340 1341 return I40E_ERR_RESET_FAILED; 1342 } 1343 1344 #define I40E_PF_RESET_WAIT_COUNT 1000 1345 /** 1346 * i40e_pf_reset - Reset the PF 1347 * @hw: pointer to the hardware structure 1348 * 1349 * Assuming someone else has triggered a global reset, 1350 * assure the global reset is complete and then reset the PF 1351 **/ 1352 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1353 { 1354 u32 cnt = 0; 1355 u32 cnt1 = 0; 1356 u32 reg = 0; 1357 u32 grst_del; 1358 1359 /* Poll for Global Reset steady state in case of recent GRST. 1360 * The grst delay value is in 100ms units, and we'll wait a 1361 * couple counts longer to be sure we don't just miss the end. 1362 */ 1363 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1364 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1365 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1366 1367 grst_del = min(grst_del * 20, 160U); 1368 1369 for (cnt = 0; cnt < grst_del; cnt++) { 1370 reg = rd32(hw, I40E_GLGEN_RSTAT); 1371 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1372 break; 1373 i40e_msec_delay(100); 1374 } 1375 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1376 DEBUGOUT("Global reset polling failed to complete.\n"); 1377 return I40E_ERR_RESET_FAILED; 1378 } 1379 1380 /* Now Wait for the FW to be ready */ 1381 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1382 reg = rd32(hw, I40E_GLNVM_ULD); 1383 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1384 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1385 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1386 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1387 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1388 break; 1389 } 1390 i40e_msec_delay(10); 1391 } 1392 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1393 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1394 DEBUGOUT("wait for FW Reset complete timedout\n"); 1395 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1396 return I40E_ERR_RESET_FAILED; 1397 } 1398 1399 /* If there was a Global Reset in progress when we got here, 1400 * we don't need to do the PF Reset 1401 */ 1402 if (!cnt) { 1403 u32 reg2 = 0; 1404 1405 reg = rd32(hw, I40E_PFGEN_CTRL); 1406 wr32(hw, I40E_PFGEN_CTRL, 1407 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1408 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1409 reg = rd32(hw, I40E_PFGEN_CTRL); 1410 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1411 break; 1412 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1413 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 1414 break; 1415 i40e_msec_delay(1); 1416 } 1417 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1418 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS) 1419 return I40E_ERR_RESET_FAILED; 1420 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1421 DEBUGOUT("PF reset polling failed to complete.\n"); 1422 return I40E_ERR_RESET_FAILED; 1423 } 1424 } 1425 1426 i40e_clear_pxe_mode(hw); 1427 1428 1429 return I40E_SUCCESS; 1430 } 1431 1432 /** 1433 * i40e_clear_hw - clear out any left over hw state 1434 * @hw: pointer to the hw struct 1435 * 1436 * Clear queues and interrupts, typically called at init time, 1437 * but after the capabilities have been found so we know how many 1438 * queues and msix vectors have been allocated. 1439 **/ 1440 void i40e_clear_hw(struct i40e_hw *hw) 1441 { 1442 u32 num_queues, base_queue; 1443 u32 num_pf_int; 1444 u32 num_vf_int; 1445 u32 num_vfs; 1446 u32 i, j; 1447 u32 val; 1448 u32 eol = 0x7ff; 1449 1450 /* get number of interrupts, queues, and vfs */ 1451 val = rd32(hw, I40E_GLPCI_CNF2); 1452 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1453 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1454 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1455 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1456 1457 val = rd32(hw, I40E_PFLAN_QALLOC); 1458 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1459 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1460 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1461 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1462 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1463 num_queues = (j - base_queue) + 1; 1464 else 1465 num_queues = 0; 1466 1467 val = rd32(hw, I40E_PF_VT_PFALLOC); 1468 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1469 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1470 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1471 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1472 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1473 num_vfs = (j - i) + 1; 1474 else 1475 num_vfs = 0; 1476 1477 /* stop all the interrupts */ 1478 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1479 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1480 for (i = 0; i < num_pf_int - 2; i++) 1481 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1482 1483 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1484 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1485 wr32(hw, I40E_PFINT_LNKLST0, val); 1486 for (i = 0; i < num_pf_int - 2; i++) 1487 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1488 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1489 for (i = 0; i < num_vfs; i++) 1490 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1491 for (i = 0; i < num_vf_int - 2; i++) 1492 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1493 1494 /* warn the HW of the coming Tx disables */ 1495 for (i = 0; i < num_queues; i++) { 1496 u32 abs_queue_idx = base_queue + i; 1497 u32 reg_block = 0; 1498 1499 if (abs_queue_idx >= 128) { 1500 reg_block = abs_queue_idx / 128; 1501 abs_queue_idx %= 128; 1502 } 1503 1504 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1505 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1506 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1507 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1508 1509 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1510 } 1511 i40e_usec_delay(400); 1512 1513 /* stop all the queues */ 1514 for (i = 0; i < num_queues; i++) { 1515 wr32(hw, I40E_QINT_TQCTL(i), 0); 1516 wr32(hw, I40E_QTX_ENA(i), 0); 1517 wr32(hw, I40E_QINT_RQCTL(i), 0); 1518 wr32(hw, I40E_QRX_ENA(i), 0); 1519 } 1520 1521 /* short wait for all queue disables to settle */ 1522 i40e_usec_delay(50); 1523 } 1524 1525 /** 1526 * i40e_clear_pxe_mode - clear pxe operations mode 1527 * @hw: pointer to the hw struct 1528 * 1529 * Make sure all PXE mode settings are cleared, including things 1530 * like descriptor fetch/write-back mode. 1531 **/ 1532 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1533 { 1534 if (i40e_check_asq_alive(hw)) 1535 i40e_aq_clear_pxe_mode(hw, NULL); 1536 } 1537 1538 /** 1539 * i40e_led_is_mine - helper to find matching led 1540 * @hw: pointer to the hw struct 1541 * @idx: index into GPIO registers 1542 * 1543 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1544 */ 1545 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1546 { 1547 u32 gpio_val = 0; 1548 u32 port; 1549 1550 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 1551 !hw->func_caps.led[idx]) 1552 return 0; 1553 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1554 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1555 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1556 1557 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1558 * if it is not our port then ignore 1559 */ 1560 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1561 (port != hw->port)) 1562 return 0; 1563 1564 return gpio_val; 1565 } 1566 1567 #define I40E_COMBINED_ACTIVITY 0xA 1568 #define I40E_FILTER_ACTIVITY 0xE 1569 #define I40E_LINK_ACTIVITY 0xC 1570 #define I40E_MAC_ACTIVITY 0xD 1571 #define I40E_FW_LED BIT(4) 1572 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 1573 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 1574 1575 #define I40E_LED0 22 1576 1577 #define I40E_PIN_FUNC_SDP 0x0 1578 #define I40E_PIN_FUNC_LED 0x1 1579 1580 /** 1581 * i40e_led_get - return current on/off mode 1582 * @hw: pointer to the hw struct 1583 * 1584 * The value returned is the 'mode' field as defined in the 1585 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1586 * values are variations of possible behaviors relating to 1587 * blink, link, and wire. 1588 **/ 1589 u32 i40e_led_get(struct i40e_hw *hw) 1590 { 1591 u32 current_mode = 0; 1592 u32 mode = 0; 1593 int i; 1594 1595 /* as per the documentation GPIO 22-29 are the LED 1596 * GPIO pins named LED0..LED7 1597 */ 1598 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1599 u32 gpio_val = i40e_led_is_mine(hw, i); 1600 1601 if (!gpio_val) 1602 continue; 1603 1604 /* ignore gpio LED src mode entries related to the activity 1605 * LEDs 1606 */ 1607 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1608 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1609 switch (current_mode) { 1610 case I40E_COMBINED_ACTIVITY: 1611 case I40E_FILTER_ACTIVITY: 1612 case I40E_MAC_ACTIVITY: 1613 case I40E_LINK_ACTIVITY: 1614 continue; 1615 default: 1616 break; 1617 } 1618 1619 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1620 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1621 break; 1622 } 1623 1624 return mode; 1625 } 1626 1627 /** 1628 * i40e_led_set - set new on/off mode 1629 * @hw: pointer to the hw struct 1630 * @mode: 0=off, 0xf=on (else see manual for mode details) 1631 * @blink: true if the LED should blink when on, false if steady 1632 * 1633 * if this function is used to turn on the blink it should 1634 * be used to disable the blink when restoring the original state. 1635 **/ 1636 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1637 { 1638 u32 current_mode = 0; 1639 int i; 1640 1641 if (mode & ~I40E_LED_MODE_VALID) { 1642 DEBUGOUT1("invalid mode passed in %X\n", mode); 1643 return; 1644 } 1645 1646 /* as per the documentation GPIO 22-29 are the LED 1647 * GPIO pins named LED0..LED7 1648 */ 1649 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1650 u32 gpio_val = i40e_led_is_mine(hw, i); 1651 1652 if (!gpio_val) 1653 continue; 1654 1655 /* ignore gpio LED src mode entries related to the activity 1656 * LEDs 1657 */ 1658 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1659 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1660 switch (current_mode) { 1661 case I40E_COMBINED_ACTIVITY: 1662 case I40E_FILTER_ACTIVITY: 1663 case I40E_MAC_ACTIVITY: 1664 case I40E_LINK_ACTIVITY: 1665 continue; 1666 default: 1667 break; 1668 } 1669 1670 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 1671 u32 pin_func = 0; 1672 1673 if (mode & I40E_FW_LED) 1674 pin_func = I40E_PIN_FUNC_SDP; 1675 else 1676 pin_func = I40E_PIN_FUNC_LED; 1677 1678 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 1679 gpio_val |= ((pin_func << 1680 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) & 1681 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK); 1682 } 1683 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1684 /* this & is a bit of paranoia, but serves as a range check */ 1685 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1686 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1687 1688 if (blink) 1689 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1690 else 1691 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1692 1693 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1694 break; 1695 } 1696 } 1697 1698 /* Admin command wrappers */ 1699 1700 /** 1701 * i40e_aq_get_phy_capabilities 1702 * @hw: pointer to the hw struct 1703 * @abilities: structure for PHY capabilities to be filled 1704 * @qualified_modules: report Qualified Modules 1705 * @report_init: report init capabilities (active are default) 1706 * @cmd_details: pointer to command details structure or NULL 1707 * 1708 * Returns the various PHY abilities supported on the Port. 1709 **/ 1710 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1711 bool qualified_modules, bool report_init, 1712 struct i40e_aq_get_phy_abilities_resp *abilities, 1713 struct i40e_asq_cmd_details *cmd_details) 1714 { 1715 struct i40e_aq_desc desc; 1716 enum i40e_status_code status; 1717 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1718 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1719 1720 if (!abilities) 1721 return I40E_ERR_PARAM; 1722 1723 do { 1724 i40e_fill_default_direct_cmd_desc(&desc, 1725 i40e_aqc_opc_get_phy_abilities); 1726 1727 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1728 if (abilities_size > I40E_AQ_LARGE_BUF) 1729 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1730 1731 if (qualified_modules) 1732 desc.params.external.param0 |= 1733 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1734 1735 if (report_init) 1736 desc.params.external.param0 |= 1737 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1738 1739 status = i40e_asq_send_command(hw, &desc, abilities, 1740 abilities_size, cmd_details); 1741 1742 switch (hw->aq.asq_last_status) { 1743 case I40E_AQ_RC_EIO: 1744 status = I40E_ERR_UNKNOWN_PHY; 1745 break; 1746 case I40E_AQ_RC_EAGAIN: 1747 i40e_msec_delay(1); 1748 total_delay++; 1749 status = I40E_ERR_TIMEOUT; 1750 break; 1751 /* also covers I40E_AQ_RC_OK */ 1752 default: 1753 break; 1754 } 1755 1756 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && 1757 (total_delay < max_delay)); 1758 1759 if (status != I40E_SUCCESS) 1760 return status; 1761 1762 if (report_init) { 1763 if (hw->mac.type == I40E_MAC_XL710 && 1764 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1765 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1766 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1767 } else { 1768 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1769 hw->phy.phy_types |= 1770 ((u64)abilities->phy_type_ext << 32); 1771 } 1772 } 1773 1774 return status; 1775 } 1776 1777 /** 1778 * i40e_aq_set_phy_config 1779 * @hw: pointer to the hw struct 1780 * @config: structure with PHY configuration to be set 1781 * @cmd_details: pointer to command details structure or NULL 1782 * 1783 * Set the various PHY configuration parameters 1784 * supported on the Port.One or more of the Set PHY config parameters may be 1785 * ignored in an MFP mode as the PF may not have the privilege to set some 1786 * of the PHY Config parameters. This status will be indicated by the 1787 * command response. 1788 **/ 1789 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1790 struct i40e_aq_set_phy_config *config, 1791 struct i40e_asq_cmd_details *cmd_details) 1792 { 1793 struct i40e_aq_desc desc; 1794 struct i40e_aq_set_phy_config *cmd = 1795 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1796 enum i40e_status_code status; 1797 1798 if (!config) 1799 return I40E_ERR_PARAM; 1800 1801 i40e_fill_default_direct_cmd_desc(&desc, 1802 i40e_aqc_opc_set_phy_config); 1803 1804 *cmd = *config; 1805 1806 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1807 1808 return status; 1809 } 1810 1811 /** 1812 * i40e_set_fc 1813 * @hw: pointer to the hw struct 1814 * @aq_failures: buffer to return AdminQ failure information 1815 * @atomic_restart: whether to enable atomic link restart 1816 * 1817 * Set the requested flow control mode using set_phy_config. 1818 **/ 1819 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1820 bool atomic_restart) 1821 { 1822 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1823 struct i40e_aq_get_phy_abilities_resp abilities; 1824 struct i40e_aq_set_phy_config config; 1825 enum i40e_status_code status; 1826 u8 pause_mask = 0x0; 1827 1828 *aq_failures = 0x0; 1829 1830 switch (fc_mode) { 1831 case I40E_FC_FULL: 1832 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1833 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1834 break; 1835 case I40E_FC_RX_PAUSE: 1836 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1837 break; 1838 case I40E_FC_TX_PAUSE: 1839 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1840 break; 1841 default: 1842 break; 1843 } 1844 1845 /* Get the current phy config */ 1846 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1847 NULL); 1848 if (status) { 1849 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1850 return status; 1851 } 1852 1853 memset(&config, 0, sizeof(config)); 1854 /* clear the old pause settings */ 1855 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1856 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1857 /* set the new abilities */ 1858 config.abilities |= pause_mask; 1859 /* If the abilities have changed, then set the new config */ 1860 if (config.abilities != abilities.abilities) { 1861 /* Auto restart link so settings take effect */ 1862 if (atomic_restart) 1863 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1864 /* Copy over all the old settings */ 1865 config.phy_type = abilities.phy_type; 1866 config.phy_type_ext = abilities.phy_type_ext; 1867 config.link_speed = abilities.link_speed; 1868 config.eee_capability = abilities.eee_capability; 1869 config.eeer = abilities.eeer_val; 1870 config.low_power_ctrl = abilities.d3_lpan; 1871 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1872 I40E_AQ_PHY_FEC_CONFIG_MASK; 1873 status = i40e_aq_set_phy_config(hw, &config, NULL); 1874 1875 if (status) 1876 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1877 } 1878 /* Update the link info */ 1879 status = i40e_update_link_info(hw); 1880 if (status) { 1881 /* Wait a little bit (on 40G cards it sometimes takes a really 1882 * long time for link to come back from the atomic reset) 1883 * and try once more 1884 */ 1885 i40e_msec_delay(1000); 1886 status = i40e_update_link_info(hw); 1887 } 1888 if (status) 1889 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1890 1891 return status; 1892 } 1893 1894 /** 1895 * i40e_aq_set_mac_config 1896 * @hw: pointer to the hw struct 1897 * @max_frame_size: Maximum Frame Size to be supported by the port 1898 * @crc_en: Tell HW to append a CRC to outgoing frames 1899 * @pacing: Pacing configurations 1900 * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked 1901 * @cmd_details: pointer to command details structure or NULL 1902 * 1903 * Configure MAC settings for frame size, jumbo frame support and the 1904 * addition of a CRC by the hardware. 1905 **/ 1906 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1907 u16 max_frame_size, 1908 bool crc_en, u16 pacing, 1909 bool auto_drop_blocking_packets, 1910 struct i40e_asq_cmd_details *cmd_details) 1911 { 1912 struct i40e_aq_desc desc; 1913 struct i40e_aq_set_mac_config *cmd = 1914 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1915 enum i40e_status_code status; 1916 1917 if (max_frame_size == 0) 1918 return I40E_ERR_PARAM; 1919 1920 i40e_fill_default_direct_cmd_desc(&desc, 1921 i40e_aqc_opc_set_mac_config); 1922 1923 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1924 cmd->params = ((u8)pacing & 0x0F) << 3; 1925 if (crc_en) 1926 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1927 1928 if (auto_drop_blocking_packets) { 1929 if (hw->flags & I40E_HW_FLAG_DROP_MODE) 1930 cmd->params |= 1931 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN; 1932 else 1933 i40e_debug(hw, I40E_DEBUG_ALL, 1934 "This FW api version does not support drop mode.\n"); 1935 } 1936 1937 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF 1938 cmd->fc_refresh_threshold = 1939 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD); 1940 1941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1942 1943 return status; 1944 } 1945 1946 /** 1947 * i40e_aq_clear_pxe_mode 1948 * @hw: pointer to the hw struct 1949 * @cmd_details: pointer to command details structure or NULL 1950 * 1951 * Tell the firmware that the driver is taking over from PXE 1952 **/ 1953 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1954 struct i40e_asq_cmd_details *cmd_details) 1955 { 1956 enum i40e_status_code status; 1957 struct i40e_aq_desc desc; 1958 struct i40e_aqc_clear_pxe *cmd = 1959 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1960 1961 i40e_fill_default_direct_cmd_desc(&desc, 1962 i40e_aqc_opc_clear_pxe_mode); 1963 1964 cmd->rx_cnt = 0x2; 1965 1966 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1967 1968 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1969 1970 return status; 1971 } 1972 1973 /** 1974 * i40e_aq_set_link_restart_an 1975 * @hw: pointer to the hw struct 1976 * @enable_link: if true: enable link, if false: disable link 1977 * @cmd_details: pointer to command details structure or NULL 1978 * 1979 * Sets up the link and restarts the Auto-Negotiation over the link. 1980 **/ 1981 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1982 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1983 { 1984 struct i40e_aq_desc desc; 1985 struct i40e_aqc_set_link_restart_an *cmd = 1986 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1987 enum i40e_status_code status; 1988 1989 i40e_fill_default_direct_cmd_desc(&desc, 1990 i40e_aqc_opc_set_link_restart_an); 1991 1992 cmd->command = I40E_AQ_PHY_RESTART_AN; 1993 if (enable_link) 1994 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1995 else 1996 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1997 1998 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1999 2000 return status; 2001 } 2002 2003 /** 2004 * i40e_aq_get_link_info 2005 * @hw: pointer to the hw struct 2006 * @enable_lse: enable/disable LinkStatusEvent reporting 2007 * @link: pointer to link status structure - optional 2008 * @cmd_details: pointer to command details structure or NULL 2009 * 2010 * Returns the link status of the adapter. 2011 **/ 2012 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 2013 bool enable_lse, struct i40e_link_status *link, 2014 struct i40e_asq_cmd_details *cmd_details) 2015 { 2016 struct i40e_aq_desc desc; 2017 struct i40e_aqc_get_link_status *resp = 2018 (struct i40e_aqc_get_link_status *)&desc.params.raw; 2019 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 2020 enum i40e_status_code status; 2021 bool tx_pause, rx_pause; 2022 u16 command_flags; 2023 2024 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 2025 2026 if (enable_lse) 2027 command_flags = I40E_AQ_LSE_ENABLE; 2028 else 2029 command_flags = I40E_AQ_LSE_DISABLE; 2030 resp->command_flags = CPU_TO_LE16(command_flags); 2031 2032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2033 2034 if (status != I40E_SUCCESS) 2035 goto aq_get_link_info_exit; 2036 2037 /* save off old link status information */ 2038 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 2039 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 2040 2041 /* update link status */ 2042 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 2043 hw->phy.media_type = i40e_get_media_type(hw); 2044 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 2045 hw_link_info->link_info = resp->link_info; 2046 hw_link_info->an_info = resp->an_info; 2047 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 2048 I40E_AQ_CONFIG_FEC_RS_ENA); 2049 hw_link_info->ext_info = resp->ext_info; 2050 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 2051 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 2052 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 2053 2054 /* update fc info */ 2055 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 2056 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 2057 if (tx_pause & rx_pause) 2058 hw->fc.current_mode = I40E_FC_FULL; 2059 else if (tx_pause) 2060 hw->fc.current_mode = I40E_FC_TX_PAUSE; 2061 else if (rx_pause) 2062 hw->fc.current_mode = I40E_FC_RX_PAUSE; 2063 else 2064 hw->fc.current_mode = I40E_FC_NONE; 2065 2066 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 2067 hw_link_info->crc_enable = true; 2068 else 2069 hw_link_info->crc_enable = false; 2070 2071 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 2072 hw_link_info->lse_enable = true; 2073 else 2074 hw_link_info->lse_enable = false; 2075 2076 if ((hw->mac.type == I40E_MAC_XL710) && 2077 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 2078 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 2079 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 2080 2081 /* 'Get Link Status' response data structure from X722 FW has 2082 * different format and does not contain this information 2083 */ 2084 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE && 2085 hw->mac.type != I40E_MAC_X722) { 2086 __le32 tmp; 2087 2088 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), 2089 I40E_NONDMA_TO_NONDMA); 2090 hw->phy.phy_types = LE32_TO_CPU(tmp); 2091 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 2092 } 2093 2094 /* save link status information */ 2095 if (link) 2096 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 2097 I40E_NONDMA_TO_NONDMA); 2098 2099 /* flag cleared so helper functions don't call AQ again */ 2100 hw->phy.get_link_info = false; 2101 2102 aq_get_link_info_exit: 2103 return status; 2104 } 2105 2106 /** 2107 * i40e_aq_set_phy_int_mask 2108 * @hw: pointer to the hw struct 2109 * @mask: interrupt mask to be set 2110 * @cmd_details: pointer to command details structure or NULL 2111 * 2112 * Set link interrupt mask. 2113 **/ 2114 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 2115 u16 mask, 2116 struct i40e_asq_cmd_details *cmd_details) 2117 { 2118 struct i40e_aq_desc desc; 2119 struct i40e_aqc_set_phy_int_mask *cmd = 2120 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 2121 enum i40e_status_code status; 2122 2123 i40e_fill_default_direct_cmd_desc(&desc, 2124 i40e_aqc_opc_set_phy_int_mask); 2125 2126 cmd->event_mask = CPU_TO_LE16(mask); 2127 2128 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2129 2130 return status; 2131 } 2132 2133 /** 2134 * i40e_aq_get_local_advt_reg 2135 * @hw: pointer to the hw struct 2136 * @advt_reg: local AN advertisement register value 2137 * @cmd_details: pointer to command details structure or NULL 2138 * 2139 * Get the Local AN advertisement register value. 2140 **/ 2141 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 2142 u64 *advt_reg, 2143 struct i40e_asq_cmd_details *cmd_details) 2144 { 2145 struct i40e_aq_desc desc; 2146 struct i40e_aqc_an_advt_reg *resp = 2147 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2148 enum i40e_status_code status; 2149 2150 i40e_fill_default_direct_cmd_desc(&desc, 2151 i40e_aqc_opc_get_local_advt_reg); 2152 2153 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2154 2155 if (status != I40E_SUCCESS) 2156 goto aq_get_local_advt_reg_exit; 2157 2158 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2159 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2160 2161 aq_get_local_advt_reg_exit: 2162 return status; 2163 } 2164 2165 /** 2166 * i40e_aq_set_local_advt_reg 2167 * @hw: pointer to the hw struct 2168 * @advt_reg: local AN advertisement register value 2169 * @cmd_details: pointer to command details structure or NULL 2170 * 2171 * Get the Local AN advertisement register value. 2172 **/ 2173 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2174 u64 advt_reg, 2175 struct i40e_asq_cmd_details *cmd_details) 2176 { 2177 struct i40e_aq_desc desc; 2178 struct i40e_aqc_an_advt_reg *cmd = 2179 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2180 enum i40e_status_code status; 2181 2182 i40e_fill_default_direct_cmd_desc(&desc, 2183 i40e_aqc_opc_get_local_advt_reg); 2184 2185 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2186 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2187 2188 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2189 2190 return status; 2191 } 2192 2193 /** 2194 * i40e_aq_get_partner_advt 2195 * @hw: pointer to the hw struct 2196 * @advt_reg: AN partner advertisement register value 2197 * @cmd_details: pointer to command details structure or NULL 2198 * 2199 * Get the link partner AN advertisement register value. 2200 **/ 2201 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2202 u64 *advt_reg, 2203 struct i40e_asq_cmd_details *cmd_details) 2204 { 2205 struct i40e_aq_desc desc; 2206 struct i40e_aqc_an_advt_reg *resp = 2207 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2208 enum i40e_status_code status; 2209 2210 i40e_fill_default_direct_cmd_desc(&desc, 2211 i40e_aqc_opc_get_partner_advt); 2212 2213 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2214 2215 if (status != I40E_SUCCESS) 2216 goto aq_get_partner_advt_exit; 2217 2218 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2219 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2220 2221 aq_get_partner_advt_exit: 2222 return status; 2223 } 2224 2225 /** 2226 * i40e_aq_set_lb_modes 2227 * @hw: pointer to the hw struct 2228 * @lb_modes: loopback mode to be set 2229 * @cmd_details: pointer to command details structure or NULL 2230 * 2231 * Sets loopback modes. 2232 **/ 2233 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 2234 u16 lb_modes, 2235 struct i40e_asq_cmd_details *cmd_details) 2236 { 2237 struct i40e_aq_desc desc; 2238 struct i40e_aqc_set_lb_mode *cmd = 2239 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2240 enum i40e_status_code status; 2241 2242 i40e_fill_default_direct_cmd_desc(&desc, 2243 i40e_aqc_opc_set_lb_modes); 2244 2245 cmd->lb_mode = CPU_TO_LE16(lb_modes); 2246 2247 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2248 2249 return status; 2250 } 2251 2252 /** 2253 * i40e_aq_set_phy_debug 2254 * @hw: pointer to the hw struct 2255 * @cmd_flags: debug command flags 2256 * @cmd_details: pointer to command details structure or NULL 2257 * 2258 * Reset the external PHY. 2259 **/ 2260 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2261 struct i40e_asq_cmd_details *cmd_details) 2262 { 2263 struct i40e_aq_desc desc; 2264 struct i40e_aqc_set_phy_debug *cmd = 2265 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2266 enum i40e_status_code status; 2267 2268 i40e_fill_default_direct_cmd_desc(&desc, 2269 i40e_aqc_opc_set_phy_debug); 2270 2271 cmd->command_flags = cmd_flags; 2272 2273 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2274 2275 return status; 2276 } 2277 2278 /** 2279 * i40e_hw_ver_ge 2280 * @hw: pointer to the hw struct 2281 * @maj: api major value 2282 * @min: api minor value 2283 * 2284 * Assert whether current HW api version is greater/equal than provided. 2285 **/ 2286 static bool i40e_hw_ver_ge(struct i40e_hw *hw, u16 maj, u16 min) 2287 { 2288 if (hw->aq.api_maj_ver > maj || 2289 (hw->aq.api_maj_ver == maj && hw->aq.api_min_ver >= min)) 2290 return true; 2291 return false; 2292 } 2293 2294 /** 2295 * i40e_aq_add_vsi 2296 * @hw: pointer to the hw struct 2297 * @vsi_ctx: pointer to a vsi context struct 2298 * @cmd_details: pointer to command details structure or NULL 2299 * 2300 * Add a VSI context to the hardware. 2301 **/ 2302 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2303 struct i40e_vsi_context *vsi_ctx, 2304 struct i40e_asq_cmd_details *cmd_details) 2305 { 2306 struct i40e_aq_desc desc; 2307 struct i40e_aqc_add_get_update_vsi *cmd = 2308 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2309 struct i40e_aqc_add_get_update_vsi_completion *resp = 2310 (struct i40e_aqc_add_get_update_vsi_completion *) 2311 &desc.params.raw; 2312 enum i40e_status_code status; 2313 2314 i40e_fill_default_direct_cmd_desc(&desc, 2315 i40e_aqc_opc_add_vsi); 2316 2317 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2318 cmd->connection_type = vsi_ctx->connection_type; 2319 cmd->vf_id = vsi_ctx->vf_num; 2320 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2321 2322 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2323 2324 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2325 sizeof(vsi_ctx->info), cmd_details); 2326 2327 if (status != I40E_SUCCESS) 2328 goto aq_add_vsi_exit; 2329 2330 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2331 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2332 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2333 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2334 2335 aq_add_vsi_exit: 2336 return status; 2337 } 2338 2339 /** 2340 * i40e_aq_set_default_vsi 2341 * @hw: pointer to the hw struct 2342 * @seid: vsi number 2343 * @cmd_details: pointer to command details structure or NULL 2344 **/ 2345 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2346 u16 seid, 2347 struct i40e_asq_cmd_details *cmd_details) 2348 { 2349 struct i40e_aq_desc desc; 2350 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2351 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2352 &desc.params.raw; 2353 enum i40e_status_code status; 2354 2355 i40e_fill_default_direct_cmd_desc(&desc, 2356 i40e_aqc_opc_set_vsi_promiscuous_modes); 2357 2358 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2359 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2360 cmd->seid = CPU_TO_LE16(seid); 2361 2362 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2363 2364 return status; 2365 } 2366 2367 /** 2368 * i40e_aq_clear_default_vsi 2369 * @hw: pointer to the hw struct 2370 * @seid: vsi number 2371 * @cmd_details: pointer to command details structure or NULL 2372 **/ 2373 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2374 u16 seid, 2375 struct i40e_asq_cmd_details *cmd_details) 2376 { 2377 struct i40e_aq_desc desc; 2378 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2379 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2380 &desc.params.raw; 2381 enum i40e_status_code status; 2382 2383 i40e_fill_default_direct_cmd_desc(&desc, 2384 i40e_aqc_opc_set_vsi_promiscuous_modes); 2385 2386 cmd->promiscuous_flags = CPU_TO_LE16(0); 2387 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2388 cmd->seid = CPU_TO_LE16(seid); 2389 2390 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2391 2392 return status; 2393 } 2394 2395 /** 2396 * i40e_aq_set_vsi_unicast_promiscuous 2397 * @hw: pointer to the hw struct 2398 * @seid: vsi number 2399 * @set: set unicast promiscuous enable/disable 2400 * @cmd_details: pointer to command details structure or NULL 2401 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2402 **/ 2403 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2404 u16 seid, bool set, 2405 struct i40e_asq_cmd_details *cmd_details, 2406 bool rx_only_promisc) 2407 { 2408 struct i40e_aq_desc desc; 2409 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2410 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2411 enum i40e_status_code status; 2412 u16 flags = 0; 2413 2414 i40e_fill_default_direct_cmd_desc(&desc, 2415 i40e_aqc_opc_set_vsi_promiscuous_modes); 2416 2417 if (set) { 2418 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2419 if (rx_only_promisc && i40e_hw_ver_ge(hw, 1, 5)) 2420 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 2421 } 2422 2423 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2424 2425 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2426 if (i40e_hw_ver_ge(hw, 1, 5)) 2427 cmd->valid_flags |= 2428 CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 2429 2430 cmd->seid = CPU_TO_LE16(seid); 2431 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2432 2433 return status; 2434 } 2435 2436 /** 2437 * i40e_aq_set_vsi_multicast_promiscuous 2438 * @hw: pointer to the hw struct 2439 * @seid: vsi number 2440 * @set: set multicast promiscuous enable/disable 2441 * @cmd_details: pointer to command details structure or NULL 2442 **/ 2443 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2444 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2445 { 2446 struct i40e_aq_desc desc; 2447 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2448 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2449 enum i40e_status_code status; 2450 u16 flags = 0; 2451 2452 i40e_fill_default_direct_cmd_desc(&desc, 2453 i40e_aqc_opc_set_vsi_promiscuous_modes); 2454 2455 if (set) 2456 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2457 2458 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2459 2460 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2461 2462 cmd->seid = CPU_TO_LE16(seid); 2463 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2464 2465 return status; 2466 } 2467 2468 /** 2469 * i40e_aq_set_vsi_full_promiscuous 2470 * @hw: pointer to the hw struct 2471 * @seid: VSI number 2472 * @set: set promiscuous enable/disable 2473 * @cmd_details: pointer to command details structure or NULL 2474 **/ 2475 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw, 2476 u16 seid, bool set, 2477 struct i40e_asq_cmd_details *cmd_details) 2478 { 2479 struct i40e_aq_desc desc; 2480 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2481 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2482 enum i40e_status_code status; 2483 u16 flags = 0; 2484 2485 i40e_fill_default_direct_cmd_desc(&desc, 2486 i40e_aqc_opc_set_vsi_promiscuous_modes); 2487 2488 if (set) 2489 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST | 2490 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2491 I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2492 2493 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2494 2495 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST | 2496 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2497 I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2498 2499 cmd->seid = CPU_TO_LE16(seid); 2500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2501 2502 return status; 2503 } 2504 2505 /** 2506 * i40e_aq_set_vsi_mc_promisc_on_vlan 2507 * @hw: pointer to the hw struct 2508 * @seid: vsi number 2509 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2510 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2511 * @cmd_details: pointer to command details structure or NULL 2512 **/ 2513 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2514 u16 seid, bool enable, u16 vid, 2515 struct i40e_asq_cmd_details *cmd_details) 2516 { 2517 struct i40e_aq_desc desc; 2518 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2519 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2520 enum i40e_status_code status; 2521 u16 flags = 0; 2522 2523 i40e_fill_default_direct_cmd_desc(&desc, 2524 i40e_aqc_opc_set_vsi_promiscuous_modes); 2525 2526 if (enable) 2527 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2528 2529 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2530 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2531 cmd->seid = CPU_TO_LE16(seid); 2532 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2533 2534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2535 2536 return status; 2537 } 2538 2539 /** 2540 * i40e_aq_set_vsi_uc_promisc_on_vlan 2541 * @hw: pointer to the hw struct 2542 * @seid: vsi number 2543 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2544 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2545 * @cmd_details: pointer to command details structure or NULL 2546 **/ 2547 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2548 u16 seid, bool enable, u16 vid, 2549 struct i40e_asq_cmd_details *cmd_details) 2550 { 2551 struct i40e_aq_desc desc; 2552 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2553 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2554 enum i40e_status_code status; 2555 u16 flags = 0; 2556 2557 i40e_fill_default_direct_cmd_desc(&desc, 2558 i40e_aqc_opc_set_vsi_promiscuous_modes); 2559 2560 if (enable) { 2561 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2562 if (i40e_hw_ver_ge(hw, 1, 5)) 2563 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 2564 } 2565 2566 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2567 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2568 if (i40e_hw_ver_ge(hw, 1, 5)) 2569 cmd->valid_flags |= 2570 CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 2571 cmd->seid = CPU_TO_LE16(seid); 2572 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2573 2574 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2575 2576 return status; 2577 } 2578 2579 /** 2580 * i40e_aq_set_vsi_bc_promisc_on_vlan 2581 * @hw: pointer to the hw struct 2582 * @seid: vsi number 2583 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2584 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2585 * @cmd_details: pointer to command details structure or NULL 2586 **/ 2587 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2588 u16 seid, bool enable, u16 vid, 2589 struct i40e_asq_cmd_details *cmd_details) 2590 { 2591 struct i40e_aq_desc desc; 2592 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2593 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2594 enum i40e_status_code status; 2595 u16 flags = 0; 2596 2597 i40e_fill_default_direct_cmd_desc(&desc, 2598 i40e_aqc_opc_set_vsi_promiscuous_modes); 2599 2600 if (enable) 2601 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2602 2603 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2604 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2605 cmd->seid = CPU_TO_LE16(seid); 2606 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2607 2608 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2609 2610 return status; 2611 } 2612 2613 /** 2614 * i40e_aq_set_vsi_broadcast 2615 * @hw: pointer to the hw struct 2616 * @seid: vsi number 2617 * @set_filter: true to set filter, false to clear filter 2618 * @cmd_details: pointer to command details structure or NULL 2619 * 2620 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2621 **/ 2622 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2623 u16 seid, bool set_filter, 2624 struct i40e_asq_cmd_details *cmd_details) 2625 { 2626 struct i40e_aq_desc desc; 2627 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2628 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2629 enum i40e_status_code status; 2630 2631 i40e_fill_default_direct_cmd_desc(&desc, 2632 i40e_aqc_opc_set_vsi_promiscuous_modes); 2633 2634 if (set_filter) 2635 cmd->promiscuous_flags 2636 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2637 else 2638 cmd->promiscuous_flags 2639 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2640 2641 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2642 cmd->seid = CPU_TO_LE16(seid); 2643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2644 2645 return status; 2646 } 2647 2648 /** 2649 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2650 * @hw: pointer to the hw struct 2651 * @seid: vsi number 2652 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2653 * @cmd_details: pointer to command details structure or NULL 2654 **/ 2655 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2656 u16 seid, bool enable, 2657 struct i40e_asq_cmd_details *cmd_details) 2658 { 2659 struct i40e_aq_desc desc; 2660 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2661 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2662 enum i40e_status_code status; 2663 u16 flags = 0; 2664 2665 i40e_fill_default_direct_cmd_desc(&desc, 2666 i40e_aqc_opc_set_vsi_promiscuous_modes); 2667 if (enable) 2668 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2669 2670 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2671 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2672 cmd->seid = CPU_TO_LE16(seid); 2673 2674 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2675 2676 return status; 2677 } 2678 2679 /** 2680 * i40e_aq_get_vsi_params - get VSI configuration info 2681 * @hw: pointer to the hw struct 2682 * @vsi_ctx: pointer to a vsi context struct 2683 * @cmd_details: pointer to command details structure or NULL 2684 **/ 2685 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2686 struct i40e_vsi_context *vsi_ctx, 2687 struct i40e_asq_cmd_details *cmd_details) 2688 { 2689 struct i40e_aq_desc desc; 2690 struct i40e_aqc_add_get_update_vsi *cmd = 2691 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2692 struct i40e_aqc_add_get_update_vsi_completion *resp = 2693 (struct i40e_aqc_add_get_update_vsi_completion *) 2694 &desc.params.raw; 2695 enum i40e_status_code status; 2696 2697 UNREFERENCED_1PARAMETER(cmd_details); 2698 i40e_fill_default_direct_cmd_desc(&desc, 2699 i40e_aqc_opc_get_vsi_parameters); 2700 2701 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2702 2703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2704 2705 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2706 sizeof(vsi_ctx->info), NULL); 2707 2708 if (status != I40E_SUCCESS) 2709 goto aq_get_vsi_params_exit; 2710 2711 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2712 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2713 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2714 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2715 2716 aq_get_vsi_params_exit: 2717 return status; 2718 } 2719 2720 /** 2721 * i40e_aq_update_vsi_params 2722 * @hw: pointer to the hw struct 2723 * @vsi_ctx: pointer to a vsi context struct 2724 * @cmd_details: pointer to command details structure or NULL 2725 * 2726 * Update a VSI context. 2727 **/ 2728 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2729 struct i40e_vsi_context *vsi_ctx, 2730 struct i40e_asq_cmd_details *cmd_details) 2731 { 2732 struct i40e_aq_desc desc; 2733 struct i40e_aqc_add_get_update_vsi *cmd = 2734 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2735 struct i40e_aqc_add_get_update_vsi_completion *resp = 2736 (struct i40e_aqc_add_get_update_vsi_completion *) 2737 &desc.params.raw; 2738 enum i40e_status_code status; 2739 2740 i40e_fill_default_direct_cmd_desc(&desc, 2741 i40e_aqc_opc_update_vsi_parameters); 2742 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2743 2744 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2745 2746 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2747 sizeof(vsi_ctx->info), cmd_details); 2748 2749 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2750 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2751 2752 return status; 2753 } 2754 2755 /** 2756 * i40e_aq_get_switch_config 2757 * @hw: pointer to the hardware structure 2758 * @buf: pointer to the result buffer 2759 * @buf_size: length of input buffer 2760 * @start_seid: seid to start for the report, 0 == beginning 2761 * @cmd_details: pointer to command details structure or NULL 2762 * 2763 * Fill the buf with switch configuration returned from AdminQ command 2764 **/ 2765 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2766 struct i40e_aqc_get_switch_config_resp *buf, 2767 u16 buf_size, u16 *start_seid, 2768 struct i40e_asq_cmd_details *cmd_details) 2769 { 2770 struct i40e_aq_desc desc; 2771 struct i40e_aqc_switch_seid *scfg = 2772 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2773 enum i40e_status_code status; 2774 2775 i40e_fill_default_direct_cmd_desc(&desc, 2776 i40e_aqc_opc_get_switch_config); 2777 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2778 if (buf_size > I40E_AQ_LARGE_BUF) 2779 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2780 scfg->seid = CPU_TO_LE16(*start_seid); 2781 2782 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2783 *start_seid = LE16_TO_CPU(scfg->seid); 2784 2785 return status; 2786 } 2787 2788 /** 2789 * i40e_aq_set_switch_config 2790 * @hw: pointer to the hardware structure 2791 * @flags: bit flag values to set 2792 * @mode: cloud filter mode 2793 * @valid_flags: which bit flags to set 2794 * @cmd_details: pointer to command details structure or NULL 2795 * 2796 * Set switch configuration bits 2797 **/ 2798 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2799 u16 flags, u16 valid_flags, u8 mode, 2800 struct i40e_asq_cmd_details *cmd_details) 2801 { 2802 struct i40e_aq_desc desc; 2803 struct i40e_aqc_set_switch_config *scfg = 2804 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2805 enum i40e_status_code status; 2806 2807 i40e_fill_default_direct_cmd_desc(&desc, 2808 i40e_aqc_opc_set_switch_config); 2809 scfg->flags = CPU_TO_LE16(flags); 2810 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2811 scfg->mode = mode; 2812 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2813 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); 2814 scfg->first_tag = CPU_TO_LE16(hw->first_tag); 2815 scfg->second_tag = CPU_TO_LE16(hw->second_tag); 2816 } 2817 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2818 2819 return status; 2820 } 2821 2822 /** 2823 * i40e_aq_get_firmware_version 2824 * @hw: pointer to the hw struct 2825 * @fw_major_version: firmware major version 2826 * @fw_minor_version: firmware minor version 2827 * @fw_build: firmware build number 2828 * @api_major_version: major queue version 2829 * @api_minor_version: minor queue version 2830 * @cmd_details: pointer to command details structure or NULL 2831 * 2832 * Get the firmware version from the admin queue commands 2833 **/ 2834 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2835 u16 *fw_major_version, u16 *fw_minor_version, 2836 u32 *fw_build, 2837 u16 *api_major_version, u16 *api_minor_version, 2838 struct i40e_asq_cmd_details *cmd_details) 2839 { 2840 struct i40e_aq_desc desc; 2841 struct i40e_aqc_get_version *resp = 2842 (struct i40e_aqc_get_version *)&desc.params.raw; 2843 enum i40e_status_code status; 2844 2845 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2846 2847 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2848 2849 if (status == I40E_SUCCESS) { 2850 if (fw_major_version != NULL) 2851 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2852 if (fw_minor_version != NULL) 2853 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2854 if (fw_build != NULL) 2855 *fw_build = LE32_TO_CPU(resp->fw_build); 2856 if (api_major_version != NULL) 2857 *api_major_version = LE16_TO_CPU(resp->api_major); 2858 if (api_minor_version != NULL) 2859 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2860 2861 /* A workaround to fix the API version in SW */ 2862 if (api_major_version && api_minor_version && 2863 fw_major_version && fw_minor_version && 2864 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2865 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2866 (*fw_major_version > 4))) 2867 *api_minor_version = 2; 2868 } 2869 2870 return status; 2871 } 2872 2873 /** 2874 * i40e_aq_send_driver_version 2875 * @hw: pointer to the hw struct 2876 * @dv: driver's major, minor version 2877 * @cmd_details: pointer to command details structure or NULL 2878 * 2879 * Send the driver version to the firmware 2880 **/ 2881 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2882 struct i40e_driver_version *dv, 2883 struct i40e_asq_cmd_details *cmd_details) 2884 { 2885 struct i40e_aq_desc desc; 2886 struct i40e_aqc_driver_version *cmd = 2887 (struct i40e_aqc_driver_version *)&desc.params.raw; 2888 enum i40e_status_code status; 2889 u16 len; 2890 2891 if (dv == NULL) 2892 return I40E_ERR_PARAM; 2893 2894 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2895 2896 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2897 cmd->driver_major_ver = dv->major_version; 2898 cmd->driver_minor_ver = dv->minor_version; 2899 cmd->driver_build_ver = dv->build_version; 2900 cmd->driver_subbuild_ver = dv->subbuild_version; 2901 2902 len = 0; 2903 while (len < sizeof(dv->driver_string) && 2904 (dv->driver_string[len] < 0x80) && 2905 dv->driver_string[len]) 2906 len++; 2907 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2908 len, cmd_details); 2909 2910 return status; 2911 } 2912 2913 /** 2914 * i40e_get_link_status - get status of the HW network link 2915 * @hw: pointer to the hw struct 2916 * @link_up: pointer to bool (true/false = linkup/linkdown) 2917 * 2918 * Variable link_up true if link is up, false if link is down. 2919 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2920 * 2921 * Side effect: LinkStatusEvent reporting becomes enabled 2922 **/ 2923 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2924 { 2925 enum i40e_status_code status = I40E_SUCCESS; 2926 2927 if (hw->phy.get_link_info) { 2928 status = i40e_update_link_info(hw); 2929 2930 if (status != I40E_SUCCESS) 2931 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2932 status); 2933 } 2934 2935 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2936 2937 return status; 2938 } 2939 2940 /** 2941 * i40e_update_link_info - update status of the HW network link 2942 * @hw: pointer to the hw struct 2943 **/ 2944 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2945 { 2946 struct i40e_aq_get_phy_abilities_resp abilities; 2947 enum i40e_status_code status = I40E_SUCCESS; 2948 2949 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2950 if (status) 2951 return status; 2952 2953 /* extra checking needed to ensure link info to user is timely */ 2954 if (((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2955 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2956 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) || 2957 hw->mac.type == I40E_MAC_X722) { 2958 status = i40e_aq_get_phy_capabilities(hw, false, 2959 hw->mac.type == 2960 I40E_MAC_X722, 2961 &abilities, NULL); 2962 if (status) 2963 return status; 2964 2965 if (abilities.fec_cfg_curr_mod_ext_info & 2966 I40E_AQ_ENABLE_FEC_AUTO) 2967 hw->phy.link_info.req_fec_info = 2968 (I40E_AQ_REQUEST_FEC_KR | 2969 I40E_AQ_REQUEST_FEC_RS); 2970 else 2971 hw->phy.link_info.req_fec_info = 2972 abilities.fec_cfg_curr_mod_ext_info & 2973 (I40E_AQ_REQUEST_FEC_KR | 2974 I40E_AQ_REQUEST_FEC_RS); 2975 2976 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2977 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2978 } 2979 return status; 2980 } 2981 2982 2983 /** 2984 * i40e_get_link_speed 2985 * @hw: pointer to the hw struct 2986 * 2987 * Returns the link speed of the adapter. 2988 **/ 2989 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2990 { 2991 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2992 enum i40e_status_code status = I40E_SUCCESS; 2993 2994 if (hw->phy.get_link_info) { 2995 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2996 2997 if (status != I40E_SUCCESS) 2998 goto i40e_link_speed_exit; 2999 } 3000 3001 speed = hw->phy.link_info.link_speed; 3002 3003 i40e_link_speed_exit: 3004 return speed; 3005 } 3006 3007 /** 3008 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 3009 * @hw: pointer to the hw struct 3010 * @uplink_seid: the MAC or other gizmo SEID 3011 * @downlink_seid: the VSI SEID 3012 * @enabled_tc: bitmap of TCs to be enabled 3013 * @default_port: true for default port VSI, false for control port 3014 * @veb_seid: pointer to where to put the resulting VEB SEID 3015 * @enable_stats: true to turn on VEB stats 3016 * @cmd_details: pointer to command details structure or NULL 3017 * 3018 * This asks the FW to add a VEB between the uplink and downlink 3019 * elements. If the uplink SEID is 0, this will be a floating VEB. 3020 **/ 3021 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 3022 u16 downlink_seid, u8 enabled_tc, 3023 bool default_port, u16 *veb_seid, 3024 bool enable_stats, 3025 struct i40e_asq_cmd_details *cmd_details) 3026 { 3027 struct i40e_aq_desc desc; 3028 struct i40e_aqc_add_veb *cmd = 3029 (struct i40e_aqc_add_veb *)&desc.params.raw; 3030 struct i40e_aqc_add_veb_completion *resp = 3031 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 3032 enum i40e_status_code status; 3033 u16 veb_flags = 0; 3034 3035 /* SEIDs need to either both be set or both be 0 for floating VEB */ 3036 if (!!uplink_seid != !!downlink_seid) 3037 return I40E_ERR_PARAM; 3038 3039 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 3040 3041 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 3042 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 3043 cmd->enable_tcs = enabled_tc; 3044 if (!uplink_seid) 3045 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 3046 if (default_port) 3047 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 3048 else 3049 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 3050 3051 /* reverse logic here: set the bitflag to disable the stats */ 3052 if (!enable_stats) 3053 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 3054 3055 cmd->veb_flags = CPU_TO_LE16(veb_flags); 3056 3057 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3058 3059 if (!status && veb_seid) 3060 *veb_seid = LE16_TO_CPU(resp->veb_seid); 3061 3062 return status; 3063 } 3064 3065 /** 3066 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 3067 * @hw: pointer to the hw struct 3068 * @veb_seid: the SEID of the VEB to query 3069 * @switch_id: the uplink switch id 3070 * @floating: set to true if the VEB is floating 3071 * @statistic_index: index of the stats counter block for this VEB 3072 * @vebs_used: number of VEB's used by function 3073 * @vebs_free: total VEB's not reserved by any function 3074 * @cmd_details: pointer to command details structure or NULL 3075 * 3076 * This retrieves the parameters for a particular VEB, specified by 3077 * uplink_seid, and returns them to the caller. 3078 **/ 3079 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 3080 u16 veb_seid, u16 *switch_id, 3081 bool *floating, u16 *statistic_index, 3082 u16 *vebs_used, u16 *vebs_free, 3083 struct i40e_asq_cmd_details *cmd_details) 3084 { 3085 struct i40e_aq_desc desc; 3086 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 3087 (struct i40e_aqc_get_veb_parameters_completion *) 3088 &desc.params.raw; 3089 enum i40e_status_code status; 3090 3091 if (veb_seid == 0) 3092 return I40E_ERR_PARAM; 3093 3094 i40e_fill_default_direct_cmd_desc(&desc, 3095 i40e_aqc_opc_get_veb_parameters); 3096 cmd_resp->seid = CPU_TO_LE16(veb_seid); 3097 3098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3099 if (status) 3100 goto get_veb_exit; 3101 3102 if (switch_id) 3103 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 3104 if (statistic_index) 3105 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 3106 if (vebs_used) 3107 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 3108 if (vebs_free) 3109 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 3110 if (floating) { 3111 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 3112 3113 if (flags & I40E_AQC_ADD_VEB_FLOATING) 3114 *floating = true; 3115 else 3116 *floating = false; 3117 } 3118 3119 get_veb_exit: 3120 return status; 3121 } 3122 3123 /** 3124 * i40e_prepare_add_macvlan 3125 * @mv_list: list of macvlans to be added 3126 * @desc: pointer to AQ descriptor structure 3127 * @count: length of the list 3128 * @seid: VSI for the mac address 3129 * 3130 * Internal helper function that prepares the add macvlan request 3131 * and returns the buffer size. 3132 **/ 3133 static u16 3134 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list, 3135 struct i40e_aq_desc *desc, u16 count, u16 seid) 3136 { 3137 struct i40e_aqc_macvlan *cmd = 3138 (struct i40e_aqc_macvlan *)&desc->params.raw; 3139 u16 buf_size; 3140 int i; 3141 3142 buf_size = count * sizeof(*mv_list); 3143 3144 /* prep the rest of the request */ 3145 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan); 3146 cmd->num_addresses = CPU_TO_LE16(count); 3147 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3148 cmd->seid[1] = 0; 3149 cmd->seid[2] = 0; 3150 3151 for (i = 0; i < count; i++) 3152 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 3153 mv_list[i].flags |= 3154 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 3155 3156 desc->flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3157 if (buf_size > I40E_AQ_LARGE_BUF) 3158 desc->flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3159 3160 return buf_size; 3161 } 3162 3163 /** 3164 * i40e_aq_add_macvlan 3165 * @hw: pointer to the hw struct 3166 * @seid: VSI for the mac address 3167 * @mv_list: list of macvlans to be added 3168 * @count: length of the list 3169 * @cmd_details: pointer to command details structure or NULL 3170 * 3171 * Add MAC/VLAN addresses to the HW filtering 3172 **/ 3173 enum i40e_status_code 3174 i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 3175 struct i40e_aqc_add_macvlan_element_data *mv_list, 3176 u16 count, struct i40e_asq_cmd_details *cmd_details) 3177 { 3178 struct i40e_aq_desc desc; 3179 enum i40e_status_code status; 3180 u16 buf_size; 3181 3182 if (count == 0 || !mv_list || !hw) 3183 return I40E_ERR_PARAM; 3184 3185 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 3186 3187 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3188 cmd_details); 3189 3190 return status; 3191 } 3192 3193 /** 3194 * i40e_aq_add_macvlan_v2 3195 * @hw: pointer to the hw struct 3196 * @seid: VSI for the mac address 3197 * @mv_list: list of macvlans to be added 3198 * @count: length of the list 3199 * @cmd_details: pointer to command details structure or NULL 3200 * @aq_status: pointer to Admin Queue status return value 3201 * 3202 * Add MAC/VLAN addresses to the HW filtering. 3203 * The _v2 version returns the last Admin Queue status in aq_status 3204 * to avoid race conditions in access to hw->aq.asq_last_status. 3205 * It also calls _v2 versions of asq_send_command functions to 3206 * get the aq_status on the stack. 3207 **/ 3208 enum i40e_status_code 3209 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid, 3210 struct i40e_aqc_add_macvlan_element_data *mv_list, 3211 u16 count, struct i40e_asq_cmd_details *cmd_details, 3212 enum i40e_admin_queue_err *aq_status) 3213 { 3214 struct i40e_aq_desc desc; 3215 enum i40e_status_code status; 3216 u16 buf_size; 3217 3218 if (count == 0 || !mv_list || !hw) 3219 return I40E_ERR_PARAM; 3220 3221 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 3222 3223 status = i40e_asq_send_command_v2(hw, &desc, mv_list, buf_size, 3224 cmd_details, aq_status); 3225 3226 return status; 3227 } 3228 3229 /** 3230 * i40e_aq_remove_macvlan 3231 * @hw: pointer to the hw struct 3232 * @seid: VSI for the mac address 3233 * @mv_list: list of macvlans to be removed 3234 * @count: length of the list 3235 * @cmd_details: pointer to command details structure or NULL 3236 * 3237 * Remove MAC/VLAN addresses from the HW filtering 3238 **/ 3239 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 3240 struct i40e_aqc_remove_macvlan_element_data *mv_list, 3241 u16 count, struct i40e_asq_cmd_details *cmd_details) 3242 { 3243 struct i40e_aq_desc desc; 3244 struct i40e_aqc_macvlan *cmd = 3245 (struct i40e_aqc_macvlan *)&desc.params.raw; 3246 enum i40e_status_code status; 3247 u16 buf_size; 3248 3249 if (count == 0 || !mv_list || !hw) 3250 return I40E_ERR_PARAM; 3251 3252 buf_size = count * sizeof(*mv_list); 3253 3254 /* prep the rest of the request */ 3255 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3256 cmd->num_addresses = CPU_TO_LE16(count); 3257 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3258 cmd->seid[1] = 0; 3259 cmd->seid[2] = 0; 3260 3261 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3262 if (buf_size > I40E_AQ_LARGE_BUF) 3263 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3264 3265 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3266 cmd_details); 3267 3268 return status; 3269 } 3270 3271 /** 3272 * i40e_aq_remove_macvlan_v2 3273 * @hw: pointer to the hw struct 3274 * @seid: VSI for the mac address 3275 * @mv_list: list of macvlans to be removed 3276 * @count: length of the list 3277 * @cmd_details: pointer to command details structure or NULL 3278 * @aq_status: pointer to Admin Queue status return value 3279 * 3280 * Remove MAC/VLAN addresses from the HW filtering. 3281 * The _v2 version returns the last Admin Queue status in aq_status 3282 * to avoid race conditions in access to hw->aq.asq_last_status. 3283 * It also calls _v2 versions of asq_send_command functions to 3284 * get the aq_status on the stack. 3285 **/ 3286 enum i40e_status_code 3287 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid, 3288 struct i40e_aqc_remove_macvlan_element_data *mv_list, 3289 u16 count, struct i40e_asq_cmd_details *cmd_details, 3290 enum i40e_admin_queue_err *aq_status) 3291 { 3292 struct i40e_aq_desc desc; 3293 struct i40e_aqc_macvlan *cmd = 3294 (struct i40e_aqc_macvlan *)&desc.params.raw; 3295 enum i40e_status_code status; 3296 u16 buf_size; 3297 3298 if (count == 0 || !mv_list || !hw) 3299 return I40E_ERR_PARAM; 3300 3301 buf_size = count * sizeof(*mv_list); 3302 3303 /* prep the rest of the request */ 3304 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3305 cmd->num_addresses = CPU_TO_LE16(count); 3306 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3307 cmd->seid[1] = 0; 3308 cmd->seid[2] = 0; 3309 3310 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3311 if (buf_size > I40E_AQ_LARGE_BUF) 3312 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3313 3314 status = i40e_asq_send_command_v2(hw, &desc, mv_list, buf_size, 3315 cmd_details, aq_status); 3316 3317 return status; 3318 } 3319 3320 /** 3321 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3322 * @hw: pointer to the hw struct 3323 * @opcode: AQ opcode for add or delete mirror rule 3324 * @sw_seid: Switch SEID (to which rule refers) 3325 * @rule_type: Rule Type (ingress/egress/VLAN) 3326 * @id: Destination VSI SEID or Rule ID 3327 * @count: length of the list 3328 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3329 * @cmd_details: pointer to command details structure or NULL 3330 * @rule_id: Rule ID returned from FW 3331 * @rules_used: Number of rules used in internal switch 3332 * @rules_free: Number of rules free in internal switch 3333 * 3334 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3335 * VEBs/VEPA elements only 3336 **/ 3337 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3338 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3339 u16 count, __le16 *mr_list, 3340 struct i40e_asq_cmd_details *cmd_details, 3341 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3342 { 3343 struct i40e_aq_desc desc; 3344 struct i40e_aqc_add_delete_mirror_rule *cmd = 3345 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3346 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3347 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3348 enum i40e_status_code status; 3349 u16 buf_size; 3350 3351 buf_size = count * sizeof(*mr_list); 3352 3353 /* prep the rest of the request */ 3354 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3355 cmd->seid = CPU_TO_LE16(sw_seid); 3356 cmd->rule_type = CPU_TO_LE16(rule_type & 3357 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3358 cmd->num_entries = CPU_TO_LE16(count); 3359 /* Dest VSI for add, rule_id for delete */ 3360 cmd->destination = CPU_TO_LE16(id); 3361 if (mr_list) { 3362 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3363 I40E_AQ_FLAG_RD)); 3364 if (buf_size > I40E_AQ_LARGE_BUF) 3365 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3366 } 3367 3368 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3369 cmd_details); 3370 if (status == I40E_SUCCESS || 3371 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3372 if (rule_id) 3373 *rule_id = LE16_TO_CPU(resp->rule_id); 3374 if (rules_used) 3375 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3376 if (rules_free) 3377 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3378 } 3379 return status; 3380 } 3381 3382 /** 3383 * i40e_aq_add_mirrorrule - add a mirror rule 3384 * @hw: pointer to the hw struct 3385 * @sw_seid: Switch SEID (to which rule refers) 3386 * @rule_type: Rule Type (ingress/egress/VLAN) 3387 * @dest_vsi: SEID of VSI to which packets will be mirrored 3388 * @count: length of the list 3389 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3390 * @cmd_details: pointer to command details structure or NULL 3391 * @rule_id: Rule ID returned from FW 3392 * @rules_used: Number of rules used in internal switch 3393 * @rules_free: Number of rules free in internal switch 3394 * 3395 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3396 **/ 3397 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3398 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3399 struct i40e_asq_cmd_details *cmd_details, 3400 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3401 { 3402 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3403 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3404 if (count == 0 || !mr_list) 3405 return I40E_ERR_PARAM; 3406 } 3407 3408 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3409 rule_type, dest_vsi, count, mr_list, 3410 cmd_details, rule_id, rules_used, rules_free); 3411 } 3412 3413 /** 3414 * i40e_aq_delete_mirrorrule - delete a mirror rule 3415 * @hw: pointer to the hw struct 3416 * @sw_seid: Switch SEID (to which rule refers) 3417 * @rule_type: Rule Type (ingress/egress/VLAN) 3418 * @count: length of the list 3419 * @rule_id: Rule ID that is returned in the receive desc as part of 3420 * add_mirrorrule. 3421 * @mr_list: list of mirrored VLAN IDs to be removed 3422 * @cmd_details: pointer to command details structure or NULL 3423 * @rules_used: Number of rules used in internal switch 3424 * @rules_free: Number of rules free in internal switch 3425 * 3426 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3427 **/ 3428 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3429 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3430 struct i40e_asq_cmd_details *cmd_details, 3431 u16 *rules_used, u16 *rules_free) 3432 { 3433 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3434 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3435 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3436 * mirroring. For other rule_type, count and rule_type should 3437 * not matter. 3438 */ 3439 if (count == 0 || !mr_list) 3440 return I40E_ERR_PARAM; 3441 } 3442 3443 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3444 rule_type, rule_id, count, mr_list, 3445 cmd_details, NULL, rules_used, rules_free); 3446 } 3447 3448 /** 3449 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3450 * @hw: pointer to the hw struct 3451 * @seid: VSI for the vlan filters 3452 * @v_list: list of vlan filters to be added 3453 * @count: length of the list 3454 * @cmd_details: pointer to command details structure or NULL 3455 **/ 3456 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3457 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3458 u8 count, struct i40e_asq_cmd_details *cmd_details) 3459 { 3460 struct i40e_aq_desc desc; 3461 struct i40e_aqc_macvlan *cmd = 3462 (struct i40e_aqc_macvlan *)&desc.params.raw; 3463 enum i40e_status_code status; 3464 u16 buf_size; 3465 3466 if (count == 0 || !v_list || !hw) 3467 return I40E_ERR_PARAM; 3468 3469 buf_size = count * sizeof(*v_list); 3470 3471 /* prep the rest of the request */ 3472 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3473 cmd->num_addresses = CPU_TO_LE16(count); 3474 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3475 cmd->seid[1] = 0; 3476 cmd->seid[2] = 0; 3477 3478 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3479 if (buf_size > I40E_AQ_LARGE_BUF) 3480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3481 3482 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3483 cmd_details); 3484 3485 return status; 3486 } 3487 3488 /** 3489 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3490 * @hw: pointer to the hw struct 3491 * @seid: VSI for the vlan filters 3492 * @v_list: list of macvlans to be removed 3493 * @count: length of the list 3494 * @cmd_details: pointer to command details structure or NULL 3495 **/ 3496 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3497 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3498 u8 count, struct i40e_asq_cmd_details *cmd_details) 3499 { 3500 struct i40e_aq_desc desc; 3501 struct i40e_aqc_macvlan *cmd = 3502 (struct i40e_aqc_macvlan *)&desc.params.raw; 3503 enum i40e_status_code status; 3504 u16 buf_size; 3505 3506 if (count == 0 || !v_list || !hw) 3507 return I40E_ERR_PARAM; 3508 3509 buf_size = count * sizeof(*v_list); 3510 3511 /* prep the rest of the request */ 3512 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3513 cmd->num_addresses = CPU_TO_LE16(count); 3514 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3515 cmd->seid[1] = 0; 3516 cmd->seid[2] = 0; 3517 3518 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3519 if (buf_size > I40E_AQ_LARGE_BUF) 3520 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3521 3522 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3523 cmd_details); 3524 3525 return status; 3526 } 3527 3528 /** 3529 * i40e_aq_send_msg_to_vf 3530 * @hw: pointer to the hardware structure 3531 * @vfid: vf id to send msg 3532 * @v_opcode: opcodes for VF-PF communication 3533 * @v_retval: return error code 3534 * @msg: pointer to the msg buffer 3535 * @msglen: msg length 3536 * @cmd_details: pointer to command details 3537 * 3538 * send msg to vf 3539 **/ 3540 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3541 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3542 struct i40e_asq_cmd_details *cmd_details) 3543 { 3544 struct i40e_aq_desc desc; 3545 struct i40e_aqc_pf_vf_message *cmd = 3546 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3547 enum i40e_status_code status; 3548 3549 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3550 cmd->id = CPU_TO_LE32(vfid); 3551 desc.cookie_high = CPU_TO_LE32(v_opcode); 3552 desc.cookie_low = CPU_TO_LE32(v_retval); 3553 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3554 if (msglen) { 3555 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3556 I40E_AQ_FLAG_RD)); 3557 if (msglen > I40E_AQ_LARGE_BUF) 3558 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3559 desc.datalen = CPU_TO_LE16(msglen); 3560 } 3561 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3562 3563 return status; 3564 } 3565 3566 /** 3567 * i40e_aq_debug_read_register 3568 * @hw: pointer to the hw struct 3569 * @reg_addr: register address 3570 * @reg_val: register value 3571 * @cmd_details: pointer to command details structure or NULL 3572 * 3573 * Read the register using the admin queue commands 3574 **/ 3575 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3576 u32 reg_addr, u64 *reg_val, 3577 struct i40e_asq_cmd_details *cmd_details) 3578 { 3579 struct i40e_aq_desc desc; 3580 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3581 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3582 enum i40e_status_code status; 3583 3584 if (reg_val == NULL) 3585 return I40E_ERR_PARAM; 3586 3587 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3588 3589 cmd_resp->address = CPU_TO_LE32(reg_addr); 3590 3591 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3592 3593 if (status == I40E_SUCCESS) { 3594 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3595 (u64)LE32_TO_CPU(cmd_resp->value_low); 3596 } 3597 3598 return status; 3599 } 3600 3601 /** 3602 * i40e_aq_debug_write_register 3603 * @hw: pointer to the hw struct 3604 * @reg_addr: register address 3605 * @reg_val: register value 3606 * @cmd_details: pointer to command details structure or NULL 3607 * 3608 * Write to a register using the admin queue commands 3609 **/ 3610 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3611 u32 reg_addr, u64 reg_val, 3612 struct i40e_asq_cmd_details *cmd_details) 3613 { 3614 struct i40e_aq_desc desc; 3615 struct i40e_aqc_debug_reg_read_write *cmd = 3616 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3617 enum i40e_status_code status; 3618 3619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3620 3621 cmd->address = CPU_TO_LE32(reg_addr); 3622 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3623 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3624 3625 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3626 3627 return status; 3628 } 3629 3630 /** 3631 * i40e_aq_request_resource 3632 * @hw: pointer to the hw struct 3633 * @resource: resource id 3634 * @access: access type 3635 * @sdp_number: resource number 3636 * @timeout: the maximum time in ms that the driver may hold the resource 3637 * @cmd_details: pointer to command details structure or NULL 3638 * 3639 * requests common resource using the admin queue commands 3640 **/ 3641 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3642 enum i40e_aq_resources_ids resource, 3643 enum i40e_aq_resource_access_type access, 3644 u8 sdp_number, u64 *timeout, 3645 struct i40e_asq_cmd_details *cmd_details) 3646 { 3647 struct i40e_aq_desc desc; 3648 struct i40e_aqc_request_resource *cmd_resp = 3649 (struct i40e_aqc_request_resource *)&desc.params.raw; 3650 enum i40e_status_code status; 3651 3652 DEBUGFUNC("i40e_aq_request_resource"); 3653 3654 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3655 3656 cmd_resp->resource_id = CPU_TO_LE16(resource); 3657 cmd_resp->access_type = CPU_TO_LE16(access); 3658 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3659 3660 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3661 /* The completion specifies the maximum time in ms that the driver 3662 * may hold the resource in the Timeout field. 3663 * If the resource is held by someone else, the command completes with 3664 * busy return value and the timeout field indicates the maximum time 3665 * the current owner of the resource has to free it. 3666 */ 3667 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3668 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3669 3670 return status; 3671 } 3672 3673 /** 3674 * i40e_aq_release_resource 3675 * @hw: pointer to the hw struct 3676 * @resource: resource id 3677 * @sdp_number: resource number 3678 * @cmd_details: pointer to command details structure or NULL 3679 * 3680 * release common resource using the admin queue commands 3681 **/ 3682 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3683 enum i40e_aq_resources_ids resource, 3684 u8 sdp_number, 3685 struct i40e_asq_cmd_details *cmd_details) 3686 { 3687 struct i40e_aq_desc desc; 3688 struct i40e_aqc_request_resource *cmd = 3689 (struct i40e_aqc_request_resource *)&desc.params.raw; 3690 enum i40e_status_code status; 3691 3692 DEBUGFUNC("i40e_aq_release_resource"); 3693 3694 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3695 3696 cmd->resource_id = CPU_TO_LE16(resource); 3697 cmd->resource_number = CPU_TO_LE32(sdp_number); 3698 3699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3700 3701 return status; 3702 } 3703 3704 /** 3705 * i40e_aq_read_nvm 3706 * @hw: pointer to the hw struct 3707 * @module_pointer: module pointer location in words from the NVM beginning 3708 * @offset: byte offset from the module beginning 3709 * @length: length of the section to be read (in bytes from the offset) 3710 * @data: command buffer (size [bytes] = length) 3711 * @last_command: tells if this is the last command in a series 3712 * @cmd_details: pointer to command details structure or NULL 3713 * 3714 * Read the NVM using the admin queue commands 3715 **/ 3716 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3717 u32 offset, u16 length, void *data, 3718 bool last_command, 3719 struct i40e_asq_cmd_details *cmd_details) 3720 { 3721 struct i40e_aq_desc desc; 3722 struct i40e_aqc_nvm_update *cmd = 3723 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3724 enum i40e_status_code status; 3725 3726 DEBUGFUNC("i40e_aq_read_nvm"); 3727 3728 /* In offset the highest byte must be zeroed. */ 3729 if (offset & 0xFF000000) { 3730 status = I40E_ERR_PARAM; 3731 goto i40e_aq_read_nvm_exit; 3732 } 3733 3734 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3735 3736 /* If this is the last command in a series, set the proper flag. */ 3737 if (last_command) 3738 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3739 cmd->module_pointer = module_pointer; 3740 cmd->offset = CPU_TO_LE32(offset); 3741 cmd->length = CPU_TO_LE16(length); 3742 3743 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3744 if (length > I40E_AQ_LARGE_BUF) 3745 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3746 3747 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3748 3749 i40e_aq_read_nvm_exit: 3750 return status; 3751 } 3752 3753 /** 3754 * i40e_aq_read_nvm_config - read an nvm config block 3755 * @hw: pointer to the hw struct 3756 * @cmd_flags: NVM access admin command bits 3757 * @field_id: field or feature id 3758 * @data: buffer for result 3759 * @buf_size: buffer size 3760 * @element_count: pointer to count of elements read by FW 3761 * @cmd_details: pointer to command details structure or NULL 3762 **/ 3763 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3764 u8 cmd_flags, u32 field_id, void *data, 3765 u16 buf_size, u16 *element_count, 3766 struct i40e_asq_cmd_details *cmd_details) 3767 { 3768 struct i40e_aq_desc desc; 3769 struct i40e_aqc_nvm_config_read *cmd = 3770 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3771 enum i40e_status_code status; 3772 3773 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3774 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3775 if (buf_size > I40E_AQ_LARGE_BUF) 3776 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3777 3778 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3779 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3780 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3781 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3782 else 3783 cmd->element_id_msw = 0; 3784 3785 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3786 3787 if (!status && element_count) 3788 *element_count = LE16_TO_CPU(cmd->element_count); 3789 3790 return status; 3791 } 3792 3793 /** 3794 * i40e_aq_write_nvm_config - write an nvm config block 3795 * @hw: pointer to the hw struct 3796 * @cmd_flags: NVM access admin command bits 3797 * @data: buffer for result 3798 * @buf_size: buffer size 3799 * @element_count: count of elements to be written 3800 * @cmd_details: pointer to command details structure or NULL 3801 **/ 3802 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3803 u8 cmd_flags, void *data, u16 buf_size, 3804 u16 element_count, 3805 struct i40e_asq_cmd_details *cmd_details) 3806 { 3807 struct i40e_aq_desc desc; 3808 struct i40e_aqc_nvm_config_write *cmd = 3809 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3810 enum i40e_status_code status; 3811 3812 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3813 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3814 if (buf_size > I40E_AQ_LARGE_BUF) 3815 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3816 3817 cmd->element_count = CPU_TO_LE16(element_count); 3818 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3819 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3820 3821 return status; 3822 } 3823 3824 /** 3825 * i40e_aq_nvm_update_in_process 3826 * @hw: pointer to the hw struct 3827 * @update_flow_state: True indicates that update flow starts, false that ends 3828 * @cmd_details: pointer to command details structure or NULL 3829 * 3830 * Indicate NVM update in process. 3831 **/ 3832 enum i40e_status_code 3833 i40e_aq_nvm_update_in_process(struct i40e_hw *hw, 3834 bool update_flow_state, 3835 struct i40e_asq_cmd_details *cmd_details) 3836 { 3837 struct i40e_aq_desc desc; 3838 struct i40e_aqc_nvm_update_in_process *cmd = 3839 (struct i40e_aqc_nvm_update_in_process *)&desc.params.raw; 3840 enum i40e_status_code status; 3841 3842 i40e_fill_default_direct_cmd_desc(&desc, 3843 i40e_aqc_opc_nvm_update_in_process); 3844 3845 cmd->command = I40E_AQ_UPDATE_FLOW_END; 3846 3847 if (update_flow_state) 3848 cmd->command |= I40E_AQ_UPDATE_FLOW_START; 3849 3850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3851 3852 return status; 3853 } 3854 3855 /** 3856 * i40e_aq_min_rollback_rev_update - triggers an ow after update 3857 * @hw: pointer to the hw struct 3858 * @mode: opt-in mode, 1b for single module update, 0b for bulk update 3859 * @module: module to be updated. Ignored if mode is 0b 3860 * @min_rrev: value of the new minimal version. Ignored if mode is 0b 3861 * @cmd_details: pointer to command details structure or NULL 3862 **/ 3863 enum i40e_status_code 3864 i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module, 3865 u32 min_rrev, 3866 struct i40e_asq_cmd_details *cmd_details) 3867 { 3868 struct i40e_aq_desc desc; 3869 struct i40e_aqc_rollback_revision_update *cmd = 3870 (struct i40e_aqc_rollback_revision_update *)&desc.params.raw; 3871 enum i40e_status_code status; 3872 3873 i40e_fill_default_direct_cmd_desc(&desc, 3874 i40e_aqc_opc_rollback_revision_update); 3875 cmd->optin_mode = mode; 3876 cmd->module_selected = module; 3877 cmd->min_rrev = min_rrev; 3878 3879 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3880 3881 return status; 3882 } 3883 3884 /** 3885 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3886 * @hw: pointer to the hw struct 3887 * @buff: buffer for result 3888 * @buff_size: buffer size 3889 * @cmd_details: pointer to command details structure or NULL 3890 **/ 3891 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3892 void *buff, u16 buff_size, 3893 struct i40e_asq_cmd_details *cmd_details) 3894 { 3895 struct i40e_aq_desc desc; 3896 enum i40e_status_code status; 3897 3898 UNREFERENCED_2PARAMETER(buff, buff_size); 3899 3900 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3901 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3902 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3903 status = I40E_ERR_NOT_IMPLEMENTED; 3904 3905 return status; 3906 } 3907 3908 /** 3909 * i40e_aq_erase_nvm 3910 * @hw: pointer to the hw struct 3911 * @module_pointer: module pointer location in words from the NVM beginning 3912 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3913 * @length: length of the section to be erased (expressed in 4 KB) 3914 * @last_command: tells if this is the last command in a series 3915 * @cmd_details: pointer to command details structure or NULL 3916 * 3917 * Erase the NVM sector using the admin queue commands 3918 **/ 3919 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3920 u32 offset, u16 length, bool last_command, 3921 struct i40e_asq_cmd_details *cmd_details) 3922 { 3923 struct i40e_aq_desc desc; 3924 struct i40e_aqc_nvm_update *cmd = 3925 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3926 enum i40e_status_code status; 3927 3928 DEBUGFUNC("i40e_aq_erase_nvm"); 3929 3930 /* In offset the highest byte must be zeroed. */ 3931 if (offset & 0xFF000000) { 3932 status = I40E_ERR_PARAM; 3933 goto i40e_aq_erase_nvm_exit; 3934 } 3935 3936 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3937 3938 /* If this is the last command in a series, set the proper flag. */ 3939 if (last_command) 3940 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3941 cmd->module_pointer = module_pointer; 3942 cmd->offset = CPU_TO_LE32(offset); 3943 cmd->length = CPU_TO_LE16(length); 3944 3945 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3946 3947 i40e_aq_erase_nvm_exit: 3948 return status; 3949 } 3950 3951 /** 3952 * i40e_parse_discover_capabilities 3953 * @hw: pointer to the hw struct 3954 * @buff: pointer to a buffer containing device/function capability records 3955 * @cap_count: number of capability records in the list 3956 * @list_type_opc: type of capabilities list to parse 3957 * 3958 * Parse the device/function capabilities list. 3959 **/ 3960 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3961 u32 cap_count, 3962 enum i40e_admin_queue_opc list_type_opc) 3963 { 3964 struct i40e_aqc_list_capabilities_element_resp *cap; 3965 u32 valid_functions, num_functions; 3966 u32 number, logical_id, phys_id; 3967 struct i40e_hw_capabilities *p; 3968 enum i40e_status_code status; 3969 u16 id, ocp_cfg_word0; 3970 u8 major_rev; 3971 u32 i = 0; 3972 3973 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3974 3975 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3976 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3977 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3978 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3979 else 3980 return; 3981 3982 for (i = 0; i < cap_count; i++, cap++) { 3983 id = LE16_TO_CPU(cap->id); 3984 number = LE32_TO_CPU(cap->number); 3985 logical_id = LE32_TO_CPU(cap->logical_id); 3986 phys_id = LE32_TO_CPU(cap->phys_id); 3987 major_rev = cap->major_rev; 3988 3989 switch (id) { 3990 case I40E_AQ_CAP_ID_SWITCH_MODE: 3991 p->switch_mode = number; 3992 i40e_debug(hw, I40E_DEBUG_INIT, 3993 "HW Capability: Switch mode = %d\n", 3994 p->switch_mode); 3995 break; 3996 case I40E_AQ_CAP_ID_MNG_MODE: 3997 p->management_mode = number; 3998 if (major_rev > 1) { 3999 p->mng_protocols_over_mctp = logical_id; 4000 i40e_debug(hw, I40E_DEBUG_INIT, 4001 "HW Capability: Protocols over MCTP = %d\n", 4002 p->mng_protocols_over_mctp); 4003 } else { 4004 p->mng_protocols_over_mctp = 0; 4005 } 4006 i40e_debug(hw, I40E_DEBUG_INIT, 4007 "HW Capability: Management Mode = %d\n", 4008 p->management_mode); 4009 break; 4010 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 4011 p->npar_enable = number; 4012 i40e_debug(hw, I40E_DEBUG_INIT, 4013 "HW Capability: NPAR enable = %d\n", 4014 p->npar_enable); 4015 break; 4016 case I40E_AQ_CAP_ID_OS2BMC_CAP: 4017 p->os2bmc = number; 4018 i40e_debug(hw, I40E_DEBUG_INIT, 4019 "HW Capability: OS2BMC = %d\n", p->os2bmc); 4020 break; 4021 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 4022 p->valid_functions = number; 4023 i40e_debug(hw, I40E_DEBUG_INIT, 4024 "HW Capability: Valid Functions = %d\n", 4025 p->valid_functions); 4026 break; 4027 case I40E_AQ_CAP_ID_SRIOV: 4028 if (number == 1) 4029 p->sr_iov_1_1 = true; 4030 i40e_debug(hw, I40E_DEBUG_INIT, 4031 "HW Capability: SR-IOV = %d\n", 4032 p->sr_iov_1_1); 4033 break; 4034 case I40E_AQ_CAP_ID_VF: 4035 p->num_vfs = number; 4036 p->vf_base_id = logical_id; 4037 i40e_debug(hw, I40E_DEBUG_INIT, 4038 "HW Capability: VF count = %d\n", 4039 p->num_vfs); 4040 i40e_debug(hw, I40E_DEBUG_INIT, 4041 "HW Capability: VF base_id = %d\n", 4042 p->vf_base_id); 4043 break; 4044 case I40E_AQ_CAP_ID_VMDQ: 4045 if (number == 1) 4046 p->vmdq = true; 4047 i40e_debug(hw, I40E_DEBUG_INIT, 4048 "HW Capability: VMDQ = %d\n", p->vmdq); 4049 break; 4050 case I40E_AQ_CAP_ID_8021QBG: 4051 if (number == 1) 4052 p->evb_802_1_qbg = true; 4053 i40e_debug(hw, I40E_DEBUG_INIT, 4054 "HW Capability: 802.1Qbg = %d\n", number); 4055 break; 4056 case I40E_AQ_CAP_ID_8021QBR: 4057 if (number == 1) 4058 p->evb_802_1_qbh = true; 4059 i40e_debug(hw, I40E_DEBUG_INIT, 4060 "HW Capability: 802.1Qbh = %d\n", number); 4061 break; 4062 case I40E_AQ_CAP_ID_VSI: 4063 p->num_vsis = number; 4064 i40e_debug(hw, I40E_DEBUG_INIT, 4065 "HW Capability: VSI count = %d\n", 4066 p->num_vsis); 4067 break; 4068 case I40E_AQ_CAP_ID_DCB: 4069 if (number == 1) { 4070 p->dcb = true; 4071 p->enabled_tcmap = logical_id; 4072 p->maxtc = phys_id; 4073 } 4074 i40e_debug(hw, I40E_DEBUG_INIT, 4075 "HW Capability: DCB = %d\n", p->dcb); 4076 i40e_debug(hw, I40E_DEBUG_INIT, 4077 "HW Capability: TC Mapping = %d\n", 4078 logical_id); 4079 i40e_debug(hw, I40E_DEBUG_INIT, 4080 "HW Capability: TC Max = %d\n", p->maxtc); 4081 break; 4082 case I40E_AQ_CAP_ID_FCOE: 4083 if (number == 1) 4084 p->fcoe = true; 4085 i40e_debug(hw, I40E_DEBUG_INIT, 4086 "HW Capability: FCOE = %d\n", p->fcoe); 4087 break; 4088 case I40E_AQ_CAP_ID_ISCSI: 4089 if (number == 1) 4090 p->iscsi = true; 4091 i40e_debug(hw, I40E_DEBUG_INIT, 4092 "HW Capability: iSCSI = %d\n", p->iscsi); 4093 break; 4094 case I40E_AQ_CAP_ID_RSS: 4095 p->rss = true; 4096 p->rss_table_size = number; 4097 p->rss_table_entry_width = logical_id; 4098 i40e_debug(hw, I40E_DEBUG_INIT, 4099 "HW Capability: RSS = %d\n", p->rss); 4100 i40e_debug(hw, I40E_DEBUG_INIT, 4101 "HW Capability: RSS table size = %d\n", 4102 p->rss_table_size); 4103 i40e_debug(hw, I40E_DEBUG_INIT, 4104 "HW Capability: RSS table width = %d\n", 4105 p->rss_table_entry_width); 4106 break; 4107 case I40E_AQ_CAP_ID_RXQ: 4108 p->num_rx_qp = number; 4109 p->base_queue = phys_id; 4110 i40e_debug(hw, I40E_DEBUG_INIT, 4111 "HW Capability: Rx QP = %d\n", number); 4112 i40e_debug(hw, I40E_DEBUG_INIT, 4113 "HW Capability: base_queue = %d\n", 4114 p->base_queue); 4115 break; 4116 case I40E_AQ_CAP_ID_TXQ: 4117 p->num_tx_qp = number; 4118 p->base_queue = phys_id; 4119 i40e_debug(hw, I40E_DEBUG_INIT, 4120 "HW Capability: Tx QP = %d\n", number); 4121 i40e_debug(hw, I40E_DEBUG_INIT, 4122 "HW Capability: base_queue = %d\n", 4123 p->base_queue); 4124 break; 4125 case I40E_AQ_CAP_ID_MSIX: 4126 p->num_msix_vectors = number; 4127 i40e_debug(hw, I40E_DEBUG_INIT, 4128 "HW Capability: MSIX vector count = %d\n", 4129 p->num_msix_vectors); 4130 break; 4131 case I40E_AQ_CAP_ID_VF_MSIX: 4132 p->num_msix_vectors_vf = number; 4133 i40e_debug(hw, I40E_DEBUG_INIT, 4134 "HW Capability: MSIX VF vector count = %d\n", 4135 p->num_msix_vectors_vf); 4136 break; 4137 case I40E_AQ_CAP_ID_FLEX10: 4138 if (major_rev == 1) { 4139 if (number == 1) { 4140 p->flex10_enable = true; 4141 p->flex10_capable = true; 4142 } 4143 } else { 4144 /* Capability revision >= 2 */ 4145 if (number & 1) 4146 p->flex10_enable = true; 4147 if (number & 2) 4148 p->flex10_capable = true; 4149 } 4150 p->flex10_mode = logical_id; 4151 p->flex10_status = phys_id; 4152 i40e_debug(hw, I40E_DEBUG_INIT, 4153 "HW Capability: Flex10 mode = %d\n", 4154 p->flex10_mode); 4155 i40e_debug(hw, I40E_DEBUG_INIT, 4156 "HW Capability: Flex10 status = %d\n", 4157 p->flex10_status); 4158 break; 4159 case I40E_AQ_CAP_ID_CEM: 4160 if (number == 1) 4161 p->mgmt_cem = true; 4162 i40e_debug(hw, I40E_DEBUG_INIT, 4163 "HW Capability: CEM = %d\n", p->mgmt_cem); 4164 break; 4165 case I40E_AQ_CAP_ID_IWARP: 4166 if (number == 1) 4167 p->iwarp = true; 4168 i40e_debug(hw, I40E_DEBUG_INIT, 4169 "HW Capability: iWARP = %d\n", p->iwarp); 4170 break; 4171 case I40E_AQ_CAP_ID_LED: 4172 if (phys_id < I40E_HW_CAP_MAX_GPIO) 4173 p->led[phys_id] = true; 4174 i40e_debug(hw, I40E_DEBUG_INIT, 4175 "HW Capability: LED - PIN %d\n", phys_id); 4176 break; 4177 case I40E_AQ_CAP_ID_SDP: 4178 if (phys_id < I40E_HW_CAP_MAX_GPIO) 4179 p->sdp[phys_id] = true; 4180 i40e_debug(hw, I40E_DEBUG_INIT, 4181 "HW Capability: SDP - PIN %d\n", phys_id); 4182 break; 4183 case I40E_AQ_CAP_ID_MDIO: 4184 if (number == 1) { 4185 p->mdio_port_num = phys_id; 4186 p->mdio_port_mode = logical_id; 4187 } 4188 i40e_debug(hw, I40E_DEBUG_INIT, 4189 "HW Capability: MDIO port number = %d\n", 4190 p->mdio_port_num); 4191 i40e_debug(hw, I40E_DEBUG_INIT, 4192 "HW Capability: MDIO port mode = %d\n", 4193 p->mdio_port_mode); 4194 break; 4195 case I40E_AQ_CAP_ID_1588: 4196 if (number == 1) 4197 p->ieee_1588 = true; 4198 i40e_debug(hw, I40E_DEBUG_INIT, 4199 "HW Capability: IEEE 1588 = %d\n", 4200 p->ieee_1588); 4201 break; 4202 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 4203 p->fd = true; 4204 p->fd_filters_guaranteed = number; 4205 p->fd_filters_best_effort = logical_id; 4206 i40e_debug(hw, I40E_DEBUG_INIT, 4207 "HW Capability: Flow Director = 1\n"); 4208 i40e_debug(hw, I40E_DEBUG_INIT, 4209 "HW Capability: Guaranteed FD filters = %d\n", 4210 p->fd_filters_guaranteed); 4211 break; 4212 case I40E_AQ_CAP_ID_WSR_PROT: 4213 p->wr_csr_prot = (u64)number; 4214 p->wr_csr_prot |= (u64)logical_id << 32; 4215 i40e_debug(hw, I40E_DEBUG_INIT, 4216 "HW Capability: wr_csr_prot = 0x%" PRIX64 "\n\n", 4217 (p->wr_csr_prot & 0xffff)); 4218 break; 4219 case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS: 4220 p->dis_unused_ports = (bool)number; 4221 i40e_debug(hw, I40E_DEBUG_INIT, 4222 "HW Capability: dis_unused_ports = %d\n\n", 4223 p->dis_unused_ports); 4224 break; 4225 case I40E_AQ_CAP_ID_NVM_MGMT: 4226 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 4227 p->sec_rev_disabled = true; 4228 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 4229 p->update_disabled = true; 4230 break; 4231 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 4232 hw->num_wol_proxy_filters = (u16)number; 4233 hw->wol_proxy_vsi_seid = (u16)logical_id; 4234 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 4235 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 4236 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 4237 else 4238 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 4239 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 4240 i40e_debug(hw, I40E_DEBUG_INIT, 4241 "HW Capability: WOL proxy filters = %d\n", 4242 hw->num_wol_proxy_filters); 4243 break; 4244 default: 4245 break; 4246 } 4247 } 4248 4249 if (p->fcoe) 4250 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 4251 4252 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 4253 p->fcoe = false; 4254 4255 /* count the enabled ports (aka the "not disabled" ports) */ 4256 hw->num_ports = 0; 4257 for (i = 0; i < 4; i++) { 4258 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 4259 u64 port_cfg = 0; 4260 4261 /* use AQ read to get the physical register offset instead 4262 * of the port relative offset 4263 */ 4264 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 4265 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 4266 hw->num_ports++; 4267 } 4268 4269 /* OCP cards case: if a mezz is removed the ethernet port is at 4270 * disabled state in PRTGEN_CNF register. Additional NVM read is 4271 * needed in order to check if we are dealing with OCP card. 4272 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 4273 * physical ports results in wrong partition id calculation and thus 4274 * not supporting WoL. 4275 */ 4276 if (hw->mac.type == I40E_MAC_X722) { 4277 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) { 4278 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 4279 2 * I40E_SR_OCP_CFG_WORD0, 4280 sizeof(ocp_cfg_word0), 4281 &ocp_cfg_word0, true, NULL); 4282 if (status == I40E_SUCCESS && 4283 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 4284 hw->num_ports = 4; 4285 i40e_release_nvm(hw); 4286 } 4287 } 4288 4289 valid_functions = p->valid_functions; 4290 num_functions = 0; 4291 while (valid_functions) { 4292 if (valid_functions & 1) 4293 num_functions++; 4294 valid_functions >>= 1; 4295 } 4296 4297 /* partition id is 1-based, and functions are evenly spread 4298 * across the ports as partitions 4299 */ 4300 if (hw->num_ports != 0) { 4301 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 4302 hw->num_partitions = num_functions / hw->num_ports; 4303 } 4304 4305 /* additional HW specific goodies that might 4306 * someday be HW version specific 4307 */ 4308 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 4309 } 4310 4311 /** 4312 * i40e_aq_discover_capabilities 4313 * @hw: pointer to the hw struct 4314 * @buff: a virtual buffer to hold the capabilities 4315 * @buff_size: Size of the virtual buffer 4316 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 4317 * @list_type_opc: capabilities type to discover - pass in the command opcode 4318 * @cmd_details: pointer to command details structure or NULL 4319 * 4320 * Get the device capabilities descriptions from the firmware 4321 **/ 4322 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 4323 void *buff, u16 buff_size, u16 *data_size, 4324 enum i40e_admin_queue_opc list_type_opc, 4325 struct i40e_asq_cmd_details *cmd_details) 4326 { 4327 struct i40e_aqc_list_capabilites *cmd; 4328 struct i40e_aq_desc desc; 4329 enum i40e_status_code status = I40E_SUCCESS; 4330 4331 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 4332 4333 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 4334 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 4335 status = I40E_ERR_PARAM; 4336 goto exit; 4337 } 4338 4339 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 4340 4341 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4342 if (buff_size > I40E_AQ_LARGE_BUF) 4343 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4344 4345 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4346 *data_size = LE16_TO_CPU(desc.datalen); 4347 4348 if (status) 4349 goto exit; 4350 4351 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 4352 list_type_opc); 4353 4354 exit: 4355 return status; 4356 } 4357 4358 /** 4359 * i40e_aq_update_nvm 4360 * @hw: pointer to the hw struct 4361 * @module_pointer: module pointer location in words from the NVM beginning 4362 * @offset: byte offset from the module beginning 4363 * @length: length of the section to be written (in bytes from the offset) 4364 * @data: command buffer (size [bytes] = length) 4365 * @last_command: tells if this is the last command in a series 4366 * @preservation_flags: Preservation mode flags 4367 * @cmd_details: pointer to command details structure or NULL 4368 * 4369 * Update the NVM using the admin queue commands 4370 **/ 4371 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 4372 u32 offset, u16 length, void *data, 4373 bool last_command, u8 preservation_flags, 4374 struct i40e_asq_cmd_details *cmd_details) 4375 { 4376 struct i40e_aq_desc desc; 4377 struct i40e_aqc_nvm_update *cmd = 4378 (struct i40e_aqc_nvm_update *)&desc.params.raw; 4379 enum i40e_status_code status; 4380 4381 DEBUGFUNC("i40e_aq_update_nvm"); 4382 4383 /* In offset the highest byte must be zeroed. */ 4384 if (offset & 0xFF000000) { 4385 status = I40E_ERR_PARAM; 4386 goto i40e_aq_update_nvm_exit; 4387 } 4388 4389 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4390 4391 /* If this is the last command in a series, set the proper flag. */ 4392 if (last_command) 4393 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 4394 if (hw->mac.type == I40E_MAC_X722) { 4395 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 4396 cmd->command_flags |= 4397 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 4398 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4399 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 4400 cmd->command_flags |= 4401 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 4402 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4403 } 4404 cmd->module_pointer = module_pointer; 4405 cmd->offset = CPU_TO_LE32(offset); 4406 cmd->length = CPU_TO_LE16(length); 4407 4408 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4409 if (length > I40E_AQ_LARGE_BUF) 4410 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4411 4412 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4413 4414 i40e_aq_update_nvm_exit: 4415 return status; 4416 } 4417 4418 /** 4419 * i40e_aq_rearrange_nvm 4420 * @hw: pointer to the hw struct 4421 * @rearrange_nvm: defines direction of rearrangement 4422 * @cmd_details: pointer to command details structure or NULL 4423 * 4424 * Rearrange NVM structure, available only for transition FW 4425 **/ 4426 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw, 4427 u8 rearrange_nvm, 4428 struct i40e_asq_cmd_details *cmd_details) 4429 { 4430 struct i40e_aqc_nvm_update *cmd; 4431 enum i40e_status_code status; 4432 struct i40e_aq_desc desc; 4433 4434 DEBUGFUNC("i40e_aq_rearrange_nvm"); 4435 4436 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw; 4437 4438 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4439 4440 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT | 4441 I40E_AQ_NVM_REARRANGE_TO_STRUCT); 4442 4443 if (!rearrange_nvm) { 4444 status = I40E_ERR_PARAM; 4445 goto i40e_aq_rearrange_nvm_exit; 4446 } 4447 4448 cmd->command_flags |= rearrange_nvm; 4449 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4450 4451 i40e_aq_rearrange_nvm_exit: 4452 return status; 4453 } 4454 4455 /** 4456 * i40e_aq_get_lldp_mib 4457 * @hw: pointer to the hw struct 4458 * @bridge_type: type of bridge requested 4459 * @mib_type: Local, Remote or both Local and Remote MIBs 4460 * @buff: pointer to a user supplied buffer to store the MIB block 4461 * @buff_size: size of the buffer (in bytes) 4462 * @local_len : length of the returned Local LLDP MIB 4463 * @remote_len: length of the returned Remote LLDP MIB 4464 * @cmd_details: pointer to command details structure or NULL 4465 * 4466 * Requests the complete LLDP MIB (entire packet). 4467 **/ 4468 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4469 u8 mib_type, void *buff, u16 buff_size, 4470 u16 *local_len, u16 *remote_len, 4471 struct i40e_asq_cmd_details *cmd_details) 4472 { 4473 struct i40e_aq_desc desc; 4474 struct i40e_aqc_lldp_get_mib *cmd = 4475 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4476 struct i40e_aqc_lldp_get_mib *resp = 4477 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4478 enum i40e_status_code status; 4479 4480 if (buff_size == 0 || !buff) 4481 return I40E_ERR_PARAM; 4482 4483 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4484 /* Indirect Command */ 4485 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4486 4487 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4488 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4489 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4490 4491 desc.datalen = CPU_TO_LE16(buff_size); 4492 4493 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4494 if (buff_size > I40E_AQ_LARGE_BUF) 4495 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4496 4497 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4498 if (!status) { 4499 if (local_len != NULL) 4500 *local_len = LE16_TO_CPU(resp->local_len); 4501 if (remote_len != NULL) 4502 *remote_len = LE16_TO_CPU(resp->remote_len); 4503 } 4504 4505 return status; 4506 } 4507 4508 /** 4509 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4510 * @hw: pointer to the hw struct 4511 * @mib_type: Local, Remote or both Local and Remote MIBs 4512 * @buff: pointer to a user supplied buffer to store the MIB block 4513 * @buff_size: size of the buffer (in bytes) 4514 * @cmd_details: pointer to command details structure or NULL 4515 * 4516 * Set the LLDP MIB. 4517 **/ 4518 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4519 u8 mib_type, void *buff, u16 buff_size, 4520 struct i40e_asq_cmd_details *cmd_details) 4521 { 4522 struct i40e_aq_desc desc; 4523 struct i40e_aqc_lldp_set_local_mib *cmd = 4524 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4525 enum i40e_status_code status; 4526 4527 if (buff_size == 0 || !buff) 4528 return I40E_ERR_PARAM; 4529 4530 i40e_fill_default_direct_cmd_desc(&desc, 4531 i40e_aqc_opc_lldp_set_local_mib); 4532 /* Indirect Command */ 4533 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4534 if (buff_size > I40E_AQ_LARGE_BUF) 4535 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4536 desc.datalen = CPU_TO_LE16(buff_size); 4537 4538 cmd->type = mib_type; 4539 cmd->length = CPU_TO_LE16(buff_size); 4540 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff)); 4541 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 4542 4543 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4544 return status; 4545 } 4546 4547 /** 4548 * i40e_aq_cfg_lldp_mib_change_event 4549 * @hw: pointer to the hw struct 4550 * @enable_update: Enable or Disable event posting 4551 * @cmd_details: pointer to command details structure or NULL 4552 * 4553 * Enable or Disable posting of an event on ARQ when LLDP MIB 4554 * associated with the interface changes 4555 **/ 4556 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4557 bool enable_update, 4558 struct i40e_asq_cmd_details *cmd_details) 4559 { 4560 struct i40e_aq_desc desc; 4561 struct i40e_aqc_lldp_update_mib *cmd = 4562 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4563 enum i40e_status_code status; 4564 4565 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4566 4567 if (!enable_update) 4568 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4569 4570 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4571 4572 return status; 4573 } 4574 4575 /** 4576 * i40e_aq_restore_lldp 4577 * @hw: pointer to the hw struct 4578 * @setting: pointer to factory setting variable or NULL 4579 * @restore: True if factory settings should be restored 4580 * @cmd_details: pointer to command details structure or NULL 4581 * 4582 * Restore LLDP Agent factory settings if @restore set to True. In other case 4583 * only returns factory setting in AQ response. 4584 **/ 4585 enum i40e_status_code 4586 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore, 4587 struct i40e_asq_cmd_details *cmd_details) 4588 { 4589 struct i40e_aq_desc desc; 4590 struct i40e_aqc_lldp_restore *cmd = 4591 (struct i40e_aqc_lldp_restore *)&desc.params.raw; 4592 enum i40e_status_code status; 4593 4594 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) { 4595 i40e_debug(hw, I40E_DEBUG_ALL, 4596 "Restore LLDP not supported by current FW version.\n"); 4597 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4598 } 4599 4600 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore); 4601 4602 if (restore) 4603 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE; 4604 4605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4606 4607 if (setting) 4608 *setting = cmd->command & 1; 4609 4610 return status; 4611 } 4612 4613 /** 4614 * i40e_aq_stop_lldp 4615 * @hw: pointer to the hw struct 4616 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4617 * @persist: True if stop of LLDP should be persistent across power cycles 4618 * @cmd_details: pointer to command details structure or NULL 4619 * 4620 * Stop or Shutdown the embedded LLDP Agent 4621 **/ 4622 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4623 bool persist, 4624 struct i40e_asq_cmd_details *cmd_details) 4625 { 4626 struct i40e_aq_desc desc; 4627 struct i40e_aqc_lldp_stop *cmd = 4628 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4629 enum i40e_status_code status; 4630 4631 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4632 4633 if (shutdown_agent) 4634 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4635 4636 if (persist) { 4637 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 4638 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 4639 else 4640 i40e_debug(hw, I40E_DEBUG_ALL, 4641 "Persistent Stop LLDP not supported by current FW version.\n"); 4642 } 4643 4644 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4645 4646 return status; 4647 } 4648 4649 /** 4650 * i40e_aq_start_lldp 4651 * @hw: pointer to the hw struct 4652 * @persist: True if start of LLDP should be persistent across power cycles 4653 * @cmd_details: pointer to command details structure or NULL 4654 * 4655 * Start the embedded LLDP Agent on all ports. 4656 **/ 4657 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4658 bool persist, 4659 struct i40e_asq_cmd_details *cmd_details) 4660 { 4661 struct i40e_aq_desc desc; 4662 struct i40e_aqc_lldp_start *cmd = 4663 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4664 enum i40e_status_code status; 4665 4666 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4667 4668 cmd->command = I40E_AQ_LLDP_AGENT_START; 4669 4670 if (persist) { 4671 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 4672 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 4673 else 4674 i40e_debug(hw, I40E_DEBUG_ALL, 4675 "Persistent Start LLDP not supported by current FW version.\n"); 4676 } 4677 4678 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4679 4680 return status; 4681 } 4682 4683 /** 4684 * i40e_aq_set_dcb_parameters 4685 * @hw: pointer to the hw struct 4686 * @cmd_details: pointer to command details structure or NULL 4687 * @dcb_enable: True if DCB configuration needs to be applied 4688 * 4689 **/ 4690 enum i40e_status_code 4691 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 4692 struct i40e_asq_cmd_details *cmd_details) 4693 { 4694 struct i40e_aq_desc desc; 4695 struct i40e_aqc_set_dcb_parameters *cmd = 4696 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 4697 enum i40e_status_code status; 4698 4699 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) 4700 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4701 4702 i40e_fill_default_direct_cmd_desc(&desc, 4703 i40e_aqc_opc_set_dcb_parameters); 4704 4705 if (dcb_enable) { 4706 cmd->valid_flags = I40E_DCB_VALID; 4707 cmd->command = I40E_AQ_DCB_SET_AGENT; 4708 } 4709 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4710 4711 return status; 4712 } 4713 4714 /** 4715 * i40e_aq_get_cee_dcb_config 4716 * @hw: pointer to the hw struct 4717 * @buff: response buffer that stores CEE operational configuration 4718 * @buff_size: size of the buffer passed 4719 * @cmd_details: pointer to command details structure or NULL 4720 * 4721 * Get CEE DCBX mode operational configuration from firmware 4722 **/ 4723 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4724 void *buff, u16 buff_size, 4725 struct i40e_asq_cmd_details *cmd_details) 4726 { 4727 struct i40e_aq_desc desc; 4728 enum i40e_status_code status; 4729 4730 if (buff_size == 0 || !buff) 4731 return I40E_ERR_PARAM; 4732 4733 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4734 4735 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4736 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4737 cmd_details); 4738 4739 return status; 4740 } 4741 4742 /** 4743 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4744 * @hw: pointer to the hw struct 4745 * @start_agent: True if DCBx Agent needs to be Started 4746 * False if DCBx Agent needs to be Stopped 4747 * @cmd_details: pointer to command details structure or NULL 4748 * 4749 * Start/Stop the embedded dcbx Agent 4750 **/ 4751 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4752 bool start_agent, 4753 struct i40e_asq_cmd_details *cmd_details) 4754 { 4755 struct i40e_aq_desc desc; 4756 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4757 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4758 &desc.params.raw; 4759 enum i40e_status_code status; 4760 4761 i40e_fill_default_direct_cmd_desc(&desc, 4762 i40e_aqc_opc_lldp_stop_start_spec_agent); 4763 4764 if (start_agent) 4765 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4766 4767 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4768 4769 return status; 4770 } 4771 4772 /** 4773 * i40e_aq_add_udp_tunnel 4774 * @hw: pointer to the hw struct 4775 * @udp_port: the UDP port to add in Host byte order 4776 * @protocol_index: protocol index type 4777 * @filter_index: pointer to filter index 4778 * @cmd_details: pointer to command details structure or NULL 4779 * 4780 * Note: Firmware expects the udp_port value to be in Little Endian format, 4781 * and this function will call CPU_TO_LE16 to convert from Host byte order to 4782 * Little Endian order. 4783 **/ 4784 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4785 u16 udp_port, u8 protocol_index, 4786 u8 *filter_index, 4787 struct i40e_asq_cmd_details *cmd_details) 4788 { 4789 struct i40e_aq_desc desc; 4790 struct i40e_aqc_add_udp_tunnel *cmd = 4791 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4792 struct i40e_aqc_del_udp_tunnel_completion *resp = 4793 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4794 enum i40e_status_code status; 4795 4796 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4797 4798 cmd->udp_port = CPU_TO_LE16(udp_port); 4799 cmd->protocol_type = protocol_index; 4800 4801 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4802 4803 if (!status && filter_index) 4804 *filter_index = resp->index; 4805 4806 return status; 4807 } 4808 4809 /** 4810 * i40e_aq_del_udp_tunnel 4811 * @hw: pointer to the hw struct 4812 * @index: filter index 4813 * @cmd_details: pointer to command details structure or NULL 4814 **/ 4815 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4816 struct i40e_asq_cmd_details *cmd_details) 4817 { 4818 struct i40e_aq_desc desc; 4819 struct i40e_aqc_remove_udp_tunnel *cmd = 4820 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4821 enum i40e_status_code status; 4822 4823 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4824 4825 cmd->index = index; 4826 4827 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4828 4829 return status; 4830 } 4831 4832 /** 4833 * i40e_aq_get_switch_resource_alloc - command (0x0204) to get allocations 4834 * @hw: pointer to the hw struct 4835 * @num_entries: pointer to u8 to store the number of resource entries returned 4836 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4837 * to store the resource information for all resource types. Each 4838 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4839 * @count: size, in bytes, of the buffer provided 4840 * @cmd_details: pointer to command details structure or NULL 4841 * 4842 * Query the resources allocated to a function. 4843 **/ 4844 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4845 u8 *num_entries, 4846 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4847 u16 count, 4848 struct i40e_asq_cmd_details *cmd_details) 4849 { 4850 struct i40e_aq_desc desc; 4851 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4852 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4853 enum i40e_status_code status; 4854 u16 length = count * sizeof(*buf); 4855 4856 i40e_fill_default_direct_cmd_desc(&desc, 4857 i40e_aqc_opc_get_switch_resource_alloc); 4858 4859 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4860 if (length > I40E_AQ_LARGE_BUF) 4861 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4862 4863 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4864 4865 if (!status && num_entries) 4866 *num_entries = cmd_resp->num_entries; 4867 4868 return status; 4869 } 4870 4871 /** 4872 * i40e_aq_delete_element - Delete switch element 4873 * @hw: pointer to the hw struct 4874 * @seid: the SEID to delete from the switch 4875 * @cmd_details: pointer to command details structure or NULL 4876 * 4877 * This deletes a switch element from the switch. 4878 **/ 4879 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4880 struct i40e_asq_cmd_details *cmd_details) 4881 { 4882 struct i40e_aq_desc desc; 4883 struct i40e_aqc_switch_seid *cmd = 4884 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4885 enum i40e_status_code status; 4886 4887 if (seid == 0) 4888 return I40E_ERR_PARAM; 4889 4890 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4891 4892 cmd->seid = CPU_TO_LE16(seid); 4893 4894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4895 4896 return status; 4897 } 4898 4899 /** 4900 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4901 * @hw: pointer to the hw struct 4902 * @flags: component flags 4903 * @mac_seid: uplink seid (MAC SEID) 4904 * @vsi_seid: connected vsi seid 4905 * @ret_seid: seid of create pv component 4906 * 4907 * This instantiates an i40e port virtualizer with specified flags. 4908 * Depending on specified flags the port virtualizer can act as a 4909 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4910 */ 4911 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4912 u16 mac_seid, u16 vsi_seid, 4913 u16 *ret_seid) 4914 { 4915 struct i40e_aq_desc desc; 4916 struct i40e_aqc_add_update_pv *cmd = 4917 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4918 struct i40e_aqc_add_update_pv_completion *resp = 4919 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4920 enum i40e_status_code status; 4921 4922 if (vsi_seid == 0) 4923 return I40E_ERR_PARAM; 4924 4925 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4926 cmd->command_flags = CPU_TO_LE16(flags); 4927 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4928 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4929 4930 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4931 if (!status && ret_seid) 4932 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4933 4934 return status; 4935 } 4936 4937 /** 4938 * i40e_aq_add_tag - Add an S/E-tag 4939 * @hw: pointer to the hw struct 4940 * @direct_to_queue: should s-tag direct flow to a specific queue 4941 * @vsi_seid: VSI SEID to use this tag 4942 * @tag: value of the tag 4943 * @queue_num: queue number, only valid is direct_to_queue is true 4944 * @tags_used: return value, number of tags in use by this PF 4945 * @tags_free: return value, number of unallocated tags 4946 * @cmd_details: pointer to command details structure or NULL 4947 * 4948 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4949 * the number of tags allocated by the PF, and the number of unallocated 4950 * tags available. 4951 **/ 4952 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4953 u16 vsi_seid, u16 tag, u16 queue_num, 4954 u16 *tags_used, u16 *tags_free, 4955 struct i40e_asq_cmd_details *cmd_details) 4956 { 4957 struct i40e_aq_desc desc; 4958 struct i40e_aqc_add_tag *cmd = 4959 (struct i40e_aqc_add_tag *)&desc.params.raw; 4960 struct i40e_aqc_add_remove_tag_completion *resp = 4961 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4962 enum i40e_status_code status; 4963 4964 if (vsi_seid == 0) 4965 return I40E_ERR_PARAM; 4966 4967 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4968 4969 cmd->seid = CPU_TO_LE16(vsi_seid); 4970 cmd->tag = CPU_TO_LE16(tag); 4971 if (direct_to_queue) { 4972 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4973 cmd->queue_number = CPU_TO_LE16(queue_num); 4974 } 4975 4976 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4977 4978 if (!status) { 4979 if (tags_used != NULL) 4980 *tags_used = LE16_TO_CPU(resp->tags_used); 4981 if (tags_free != NULL) 4982 *tags_free = LE16_TO_CPU(resp->tags_free); 4983 } 4984 4985 return status; 4986 } 4987 4988 /** 4989 * i40e_aq_remove_tag - Remove an S- or E-tag 4990 * @hw: pointer to the hw struct 4991 * @vsi_seid: VSI SEID this tag is associated with 4992 * @tag: value of the S-tag to delete 4993 * @tags_used: return value, number of tags in use by this PF 4994 * @tags_free: return value, number of unallocated tags 4995 * @cmd_details: pointer to command details structure or NULL 4996 * 4997 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4998 * the number of tags allocated by the PF, and the number of unallocated 4999 * tags available. 5000 **/ 5001 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 5002 u16 tag, u16 *tags_used, u16 *tags_free, 5003 struct i40e_asq_cmd_details *cmd_details) 5004 { 5005 struct i40e_aq_desc desc; 5006 struct i40e_aqc_remove_tag *cmd = 5007 (struct i40e_aqc_remove_tag *)&desc.params.raw; 5008 struct i40e_aqc_add_remove_tag_completion *resp = 5009 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 5010 enum i40e_status_code status; 5011 5012 if (vsi_seid == 0) 5013 return I40E_ERR_PARAM; 5014 5015 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 5016 5017 cmd->seid = CPU_TO_LE16(vsi_seid); 5018 cmd->tag = CPU_TO_LE16(tag); 5019 5020 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5021 5022 if (!status) { 5023 if (tags_used != NULL) 5024 *tags_used = LE16_TO_CPU(resp->tags_used); 5025 if (tags_free != NULL) 5026 *tags_free = LE16_TO_CPU(resp->tags_free); 5027 } 5028 5029 return status; 5030 } 5031 5032 /** 5033 * i40e_aq_add_mcast_etag - Add a multicast E-tag 5034 * @hw: pointer to the hw struct 5035 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 5036 * @etag: value of E-tag to add 5037 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 5038 * @buf: address of indirect buffer 5039 * @tags_used: return value, number of E-tags in use by this port 5040 * @tags_free: return value, number of unallocated M-tags 5041 * @cmd_details: pointer to command details structure or NULL 5042 * 5043 * This associates a multicast E-tag to a port virtualizer. It will return 5044 * the number of tags allocated by the PF, and the number of unallocated 5045 * tags available. 5046 * 5047 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 5048 * num_tags_in_buf long. 5049 **/ 5050 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 5051 u16 etag, u8 num_tags_in_buf, void *buf, 5052 u16 *tags_used, u16 *tags_free, 5053 struct i40e_asq_cmd_details *cmd_details) 5054 { 5055 struct i40e_aq_desc desc; 5056 struct i40e_aqc_add_remove_mcast_etag *cmd = 5057 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 5058 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 5059 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 5060 enum i40e_status_code status; 5061 u16 length = sizeof(u16) * num_tags_in_buf; 5062 5063 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 5064 return I40E_ERR_PARAM; 5065 5066 i40e_fill_default_direct_cmd_desc(&desc, 5067 i40e_aqc_opc_add_multicast_etag); 5068 5069 cmd->pv_seid = CPU_TO_LE16(pv_seid); 5070 cmd->etag = CPU_TO_LE16(etag); 5071 cmd->num_unicast_etags = num_tags_in_buf; 5072 5073 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5074 5075 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 5076 5077 if (!status) { 5078 if (tags_used != NULL) 5079 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 5080 if (tags_free != NULL) 5081 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 5082 } 5083 5084 return status; 5085 } 5086 5087 /** 5088 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 5089 * @hw: pointer to the hw struct 5090 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 5091 * @etag: value of the E-tag to remove 5092 * @tags_used: return value, number of tags in use by this port 5093 * @tags_free: return value, number of unallocated tags 5094 * @cmd_details: pointer to command details structure or NULL 5095 * 5096 * This deletes an E-tag from the port virtualizer. It will return 5097 * the number of tags allocated by the port, and the number of unallocated 5098 * tags available. 5099 **/ 5100 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 5101 u16 etag, u16 *tags_used, u16 *tags_free, 5102 struct i40e_asq_cmd_details *cmd_details) 5103 { 5104 struct i40e_aq_desc desc; 5105 struct i40e_aqc_add_remove_mcast_etag *cmd = 5106 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 5107 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 5108 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 5109 enum i40e_status_code status; 5110 5111 5112 if (pv_seid == 0) 5113 return I40E_ERR_PARAM; 5114 5115 i40e_fill_default_direct_cmd_desc(&desc, 5116 i40e_aqc_opc_remove_multicast_etag); 5117 5118 cmd->pv_seid = CPU_TO_LE16(pv_seid); 5119 cmd->etag = CPU_TO_LE16(etag); 5120 5121 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5122 5123 if (!status) { 5124 if (tags_used != NULL) 5125 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 5126 if (tags_free != NULL) 5127 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 5128 } 5129 5130 return status; 5131 } 5132 5133 /** 5134 * i40e_aq_update_tag - Update an S/E-tag 5135 * @hw: pointer to the hw struct 5136 * @vsi_seid: VSI SEID using this S-tag 5137 * @old_tag: old tag value 5138 * @new_tag: new tag value 5139 * @tags_used: return value, number of tags in use by this PF 5140 * @tags_free: return value, number of unallocated tags 5141 * @cmd_details: pointer to command details structure or NULL 5142 * 5143 * This updates the value of the tag currently attached to this VSI 5144 * in the switch complex. It will return the number of tags allocated 5145 * by the PF, and the number of unallocated tags available. 5146 **/ 5147 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 5148 u16 old_tag, u16 new_tag, u16 *tags_used, 5149 u16 *tags_free, 5150 struct i40e_asq_cmd_details *cmd_details) 5151 { 5152 struct i40e_aq_desc desc; 5153 struct i40e_aqc_update_tag *cmd = 5154 (struct i40e_aqc_update_tag *)&desc.params.raw; 5155 struct i40e_aqc_update_tag_completion *resp = 5156 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 5157 enum i40e_status_code status; 5158 5159 if (vsi_seid == 0) 5160 return I40E_ERR_PARAM; 5161 5162 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 5163 5164 cmd->seid = CPU_TO_LE16(vsi_seid); 5165 cmd->old_tag = CPU_TO_LE16(old_tag); 5166 cmd->new_tag = CPU_TO_LE16(new_tag); 5167 5168 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5169 5170 if (!status) { 5171 if (tags_used != NULL) 5172 *tags_used = LE16_TO_CPU(resp->tags_used); 5173 if (tags_free != NULL) 5174 *tags_free = LE16_TO_CPU(resp->tags_free); 5175 } 5176 5177 return status; 5178 } 5179 5180 /** 5181 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 5182 * @hw: pointer to the hw struct 5183 * @tcmap: TC map for request/release any ignore PFC condition 5184 * @request: request or release ignore PFC condition 5185 * @tcmap_ret: return TCs for which PFC is currently ignored 5186 * @cmd_details: pointer to command details structure or NULL 5187 * 5188 * This sends out request/release to ignore PFC condition for a TC. 5189 * It will return the TCs for which PFC is currently ignored. 5190 **/ 5191 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 5192 bool request, u8 *tcmap_ret, 5193 struct i40e_asq_cmd_details *cmd_details) 5194 { 5195 struct i40e_aq_desc desc; 5196 struct i40e_aqc_pfc_ignore *cmd_resp = 5197 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 5198 enum i40e_status_code status; 5199 5200 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 5201 5202 if (request) 5203 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 5204 5205 cmd_resp->tc_bitmap = tcmap; 5206 5207 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5208 5209 if (!status) { 5210 if (tcmap_ret != NULL) 5211 *tcmap_ret = cmd_resp->tc_bitmap; 5212 } 5213 5214 return status; 5215 } 5216 5217 /** 5218 * i40e_aq_dcb_updated - DCB Updated Command 5219 * @hw: pointer to the hw struct 5220 * @cmd_details: pointer to command details structure or NULL 5221 * 5222 * When LLDP is handled in PF this command is used by the PF 5223 * to notify EMP that a DCB setting is modified. 5224 * When LLDP is handled in EMP this command is used by the PF 5225 * to notify EMP whenever one of the following parameters get 5226 * modified: 5227 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 5228 * - PCIRTT in PRTDCB_GENC.PCIRTT 5229 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 5230 * EMP will return when the shared RPB settings have been 5231 * recomputed and modified. The retval field in the descriptor 5232 * will be set to 0 when RPB is modified. 5233 **/ 5234 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 5235 struct i40e_asq_cmd_details *cmd_details) 5236 { 5237 struct i40e_aq_desc desc; 5238 enum i40e_status_code status; 5239 5240 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 5241 5242 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5243 5244 return status; 5245 } 5246 5247 /** 5248 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 5249 * @hw: pointer to the hw struct 5250 * @seid: defines the SEID of the switch for which the stats are requested 5251 * @vlan_id: the VLAN ID for which the statistics are requested 5252 * @stat_index: index of the statistics counters block assigned to this VLAN 5253 * @cmd_details: pointer to command details structure or NULL 5254 * 5255 * XL710 supports 128 smonVlanStats counters.This command is used to 5256 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 5257 * switch. 5258 **/ 5259 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 5260 u16 vlan_id, u16 *stat_index, 5261 struct i40e_asq_cmd_details *cmd_details) 5262 { 5263 struct i40e_aq_desc desc; 5264 struct i40e_aqc_add_remove_statistics *cmd_resp = 5265 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5266 enum i40e_status_code status; 5267 5268 if ((seid == 0) || (stat_index == NULL)) 5269 return I40E_ERR_PARAM; 5270 5271 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 5272 5273 cmd_resp->seid = CPU_TO_LE16(seid); 5274 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 5275 5276 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5277 5278 if (!status && stat_index) 5279 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 5280 5281 return status; 5282 } 5283 5284 /** 5285 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 5286 * @hw: pointer to the hw struct 5287 * @seid: defines the SEID of the switch for which the stats are requested 5288 * @vlan_id: the VLAN ID for which the statistics are requested 5289 * @stat_index: index of the statistics counters block assigned to this VLAN 5290 * @cmd_details: pointer to command details structure or NULL 5291 * 5292 * XL710 supports 128 smonVlanStats counters.This command is used to 5293 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 5294 * switch. 5295 **/ 5296 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 5297 u16 vlan_id, u16 stat_index, 5298 struct i40e_asq_cmd_details *cmd_details) 5299 { 5300 struct i40e_aq_desc desc; 5301 struct i40e_aqc_add_remove_statistics *cmd = 5302 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5303 enum i40e_status_code status; 5304 5305 if (seid == 0) 5306 return I40E_ERR_PARAM; 5307 5308 i40e_fill_default_direct_cmd_desc(&desc, 5309 i40e_aqc_opc_remove_statistics); 5310 5311 cmd->seid = CPU_TO_LE16(seid); 5312 cmd->vlan = CPU_TO_LE16(vlan_id); 5313 cmd->stat_index = CPU_TO_LE16(stat_index); 5314 5315 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5316 5317 return status; 5318 } 5319 5320 /** 5321 * i40e_aq_set_port_parameters - set physical port parameters. 5322 * @hw: pointer to the hw struct 5323 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 5324 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 5325 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 5326 * @double_vlan: if set double VLAN is enabled 5327 * @cmd_details: pointer to command details structure or NULL 5328 **/ 5329 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 5330 u16 bad_frame_vsi, bool save_bad_pac, 5331 bool pad_short_pac, bool double_vlan, 5332 struct i40e_asq_cmd_details *cmd_details) 5333 { 5334 struct i40e_aqc_set_port_parameters *cmd; 5335 enum i40e_status_code status; 5336 struct i40e_aq_desc desc; 5337 u16 command_flags = 0; 5338 5339 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 5340 5341 i40e_fill_default_direct_cmd_desc(&desc, 5342 i40e_aqc_opc_set_port_parameters); 5343 5344 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 5345 if (save_bad_pac) 5346 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 5347 if (pad_short_pac) 5348 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 5349 if (double_vlan) 5350 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 5351 cmd->command_flags = CPU_TO_LE16(command_flags); 5352 5353 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5354 5355 return status; 5356 } 5357 5358 /** 5359 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 5360 * @hw: pointer to the hw struct 5361 * @seid: seid for the physical port/switching component/vsi 5362 * @buff: Indirect buffer to hold data parameters and response 5363 * @buff_size: Indirect buffer size 5364 * @opcode: Tx scheduler AQ command opcode 5365 * @cmd_details: pointer to command details structure or NULL 5366 * 5367 * Generic command handler for Tx scheduler AQ commands 5368 **/ 5369 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 5370 void *buff, u16 buff_size, 5371 enum i40e_admin_queue_opc opcode, 5372 struct i40e_asq_cmd_details *cmd_details) 5373 { 5374 struct i40e_aq_desc desc; 5375 struct i40e_aqc_tx_sched_ind *cmd = 5376 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 5377 enum i40e_status_code status; 5378 bool cmd_param_flag = false; 5379 5380 switch (opcode) { 5381 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 5382 case i40e_aqc_opc_configure_vsi_tc_bw: 5383 case i40e_aqc_opc_enable_switching_comp_ets: 5384 case i40e_aqc_opc_modify_switching_comp_ets: 5385 case i40e_aqc_opc_disable_switching_comp_ets: 5386 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5387 case i40e_aqc_opc_configure_switching_comp_bw_config: 5388 cmd_param_flag = true; 5389 break; 5390 case i40e_aqc_opc_query_vsi_bw_config: 5391 case i40e_aqc_opc_query_vsi_ets_sla_config: 5392 case i40e_aqc_opc_query_switching_comp_ets_config: 5393 case i40e_aqc_opc_query_port_ets_config: 5394 case i40e_aqc_opc_query_switching_comp_bw_config: 5395 cmd_param_flag = false; 5396 break; 5397 default: 5398 return I40E_ERR_PARAM; 5399 } 5400 5401 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5402 5403 /* Indirect command */ 5404 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5405 if (cmd_param_flag) 5406 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5407 if (buff_size > I40E_AQ_LARGE_BUF) 5408 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5409 5410 desc.datalen = CPU_TO_LE16(buff_size); 5411 5412 cmd->vsi_seid = CPU_TO_LE16(seid); 5413 5414 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5415 5416 return status; 5417 } 5418 5419 /** 5420 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5421 * @hw: pointer to the hw struct 5422 * @seid: VSI seid 5423 * @credit: BW limit credits (0 = disabled) 5424 * @max_credit: Max BW limit credits 5425 * @cmd_details: pointer to command details structure or NULL 5426 **/ 5427 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5428 u16 seid, u16 credit, u8 max_credit, 5429 struct i40e_asq_cmd_details *cmd_details) 5430 { 5431 struct i40e_aq_desc desc; 5432 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5433 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5434 enum i40e_status_code status; 5435 5436 i40e_fill_default_direct_cmd_desc(&desc, 5437 i40e_aqc_opc_configure_vsi_bw_limit); 5438 5439 cmd->vsi_seid = CPU_TO_LE16(seid); 5440 cmd->credit = CPU_TO_LE16(credit); 5441 cmd->max_credit = max_credit; 5442 5443 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5444 5445 return status; 5446 } 5447 5448 /** 5449 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5450 * @hw: pointer to the hw struct 5451 * @seid: switching component seid 5452 * @credit: BW limit credits (0 = disabled) 5453 * @max_bw: Max BW limit credits 5454 * @cmd_details: pointer to command details structure or NULL 5455 **/ 5456 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5457 u16 seid, u16 credit, u8 max_bw, 5458 struct i40e_asq_cmd_details *cmd_details) 5459 { 5460 struct i40e_aq_desc desc; 5461 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5462 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5463 enum i40e_status_code status; 5464 5465 i40e_fill_default_direct_cmd_desc(&desc, 5466 i40e_aqc_opc_configure_switching_comp_bw_limit); 5467 5468 cmd->seid = CPU_TO_LE16(seid); 5469 cmd->credit = CPU_TO_LE16(credit); 5470 cmd->max_bw = max_bw; 5471 5472 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5473 5474 return status; 5475 } 5476 5477 /** 5478 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5479 * @hw: pointer to the hw struct 5480 * @seid: VSI seid 5481 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5482 * @cmd_details: pointer to command details structure or NULL 5483 **/ 5484 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5485 u16 seid, 5486 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5487 struct i40e_asq_cmd_details *cmd_details) 5488 { 5489 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5490 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5491 cmd_details); 5492 } 5493 5494 /** 5495 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5496 * @hw: pointer to the hw struct 5497 * @seid: VSI seid 5498 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5499 * @cmd_details: pointer to command details structure or NULL 5500 **/ 5501 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5502 u16 seid, 5503 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5504 struct i40e_asq_cmd_details *cmd_details) 5505 { 5506 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5507 i40e_aqc_opc_configure_vsi_tc_bw, 5508 cmd_details); 5509 } 5510 5511 /** 5512 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 5513 * @hw: pointer to the hw struct 5514 * @seid: seid of the switching component connected to Physical Port 5515 * @ets_data: Buffer holding ETS parameters 5516 * @opcode: Tx scheduler AQ command opcode 5517 * @cmd_details: pointer to command details structure or NULL 5518 **/ 5519 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 5520 u16 seid, 5521 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 5522 enum i40e_admin_queue_opc opcode, 5523 struct i40e_asq_cmd_details *cmd_details) 5524 { 5525 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 5526 sizeof(*ets_data), opcode, cmd_details); 5527 } 5528 5529 /** 5530 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 5531 * @hw: pointer to the hw struct 5532 * @seid: seid of the switching component 5533 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 5534 * @cmd_details: pointer to command details structure or NULL 5535 **/ 5536 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 5537 u16 seid, 5538 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 5539 struct i40e_asq_cmd_details *cmd_details) 5540 { 5541 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5542 i40e_aqc_opc_configure_switching_comp_bw_config, 5543 cmd_details); 5544 } 5545 5546 /** 5547 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5548 * @hw: pointer to the hw struct 5549 * @seid: seid of the switching component 5550 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5551 * @cmd_details: pointer to command details structure or NULL 5552 **/ 5553 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5554 struct i40e_hw *hw, u16 seid, 5555 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5556 struct i40e_asq_cmd_details *cmd_details) 5557 { 5558 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5559 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5560 cmd_details); 5561 } 5562 5563 /** 5564 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5565 * @hw: pointer to the hw struct 5566 * @seid: seid of the VSI 5567 * @bw_data: Buffer to hold VSI BW configuration 5568 * @cmd_details: pointer to command details structure or NULL 5569 **/ 5570 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5571 u16 seid, 5572 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5573 struct i40e_asq_cmd_details *cmd_details) 5574 { 5575 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5576 i40e_aqc_opc_query_vsi_bw_config, 5577 cmd_details); 5578 } 5579 5580 /** 5581 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5582 * @hw: pointer to the hw struct 5583 * @seid: seid of the VSI 5584 * @bw_data: Buffer to hold VSI BW configuration per TC 5585 * @cmd_details: pointer to command details structure or NULL 5586 **/ 5587 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5588 u16 seid, 5589 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5590 struct i40e_asq_cmd_details *cmd_details) 5591 { 5592 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5593 i40e_aqc_opc_query_vsi_ets_sla_config, 5594 cmd_details); 5595 } 5596 5597 /** 5598 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5599 * @hw: pointer to the hw struct 5600 * @seid: seid of the switching component 5601 * @bw_data: Buffer to hold switching component's per TC BW config 5602 * @cmd_details: pointer to command details structure or NULL 5603 **/ 5604 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5605 u16 seid, 5606 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5607 struct i40e_asq_cmd_details *cmd_details) 5608 { 5609 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5610 i40e_aqc_opc_query_switching_comp_ets_config, 5611 cmd_details); 5612 } 5613 5614 /** 5615 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5616 * @hw: pointer to the hw struct 5617 * @seid: seid of the VSI or switching component connected to Physical Port 5618 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5619 * @cmd_details: pointer to command details structure or NULL 5620 **/ 5621 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5622 u16 seid, 5623 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5624 struct i40e_asq_cmd_details *cmd_details) 5625 { 5626 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5627 i40e_aqc_opc_query_port_ets_config, 5628 cmd_details); 5629 } 5630 5631 /** 5632 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5633 * @hw: pointer to the hw struct 5634 * @seid: seid of the switching component 5635 * @bw_data: Buffer to hold switching component's BW configuration 5636 * @cmd_details: pointer to command details structure or NULL 5637 **/ 5638 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5639 u16 seid, 5640 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5641 struct i40e_asq_cmd_details *cmd_details) 5642 { 5643 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5644 i40e_aqc_opc_query_switching_comp_bw_config, 5645 cmd_details); 5646 } 5647 5648 /** 5649 * i40e_validate_filter_settings 5650 * @hw: pointer to the hardware structure 5651 * @settings: Filter control settings 5652 * 5653 * Check and validate the filter control settings passed. 5654 * The function checks for the valid filter/context sizes being 5655 * passed for FCoE and PE. 5656 * 5657 * Returns I40E_SUCCESS if the values passed are valid and within 5658 * range else returns an error. 5659 **/ 5660 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5661 struct i40e_filter_control_settings *settings) 5662 { 5663 u32 fcoe_cntx_size, fcoe_filt_size; 5664 u32 pe_cntx_size, pe_filt_size; 5665 u32 fcoe_fmax; 5666 5667 u32 val; 5668 5669 /* Validate FCoE settings passed */ 5670 switch (settings->fcoe_filt_num) { 5671 case I40E_HASH_FILTER_SIZE_1K: 5672 case I40E_HASH_FILTER_SIZE_2K: 5673 case I40E_HASH_FILTER_SIZE_4K: 5674 case I40E_HASH_FILTER_SIZE_8K: 5675 case I40E_HASH_FILTER_SIZE_16K: 5676 case I40E_HASH_FILTER_SIZE_32K: 5677 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5678 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5679 break; 5680 default: 5681 return I40E_ERR_PARAM; 5682 } 5683 5684 switch (settings->fcoe_cntx_num) { 5685 case I40E_DMA_CNTX_SIZE_512: 5686 case I40E_DMA_CNTX_SIZE_1K: 5687 case I40E_DMA_CNTX_SIZE_2K: 5688 case I40E_DMA_CNTX_SIZE_4K: 5689 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5690 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5691 break; 5692 default: 5693 return I40E_ERR_PARAM; 5694 } 5695 5696 /* Validate PE settings passed */ 5697 switch (settings->pe_filt_num) { 5698 case I40E_HASH_FILTER_SIZE_1K: 5699 case I40E_HASH_FILTER_SIZE_2K: 5700 case I40E_HASH_FILTER_SIZE_4K: 5701 case I40E_HASH_FILTER_SIZE_8K: 5702 case I40E_HASH_FILTER_SIZE_16K: 5703 case I40E_HASH_FILTER_SIZE_32K: 5704 case I40E_HASH_FILTER_SIZE_64K: 5705 case I40E_HASH_FILTER_SIZE_128K: 5706 case I40E_HASH_FILTER_SIZE_256K: 5707 case I40E_HASH_FILTER_SIZE_512K: 5708 case I40E_HASH_FILTER_SIZE_1M: 5709 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5710 pe_filt_size <<= (u32)settings->pe_filt_num; 5711 break; 5712 default: 5713 return I40E_ERR_PARAM; 5714 } 5715 5716 switch (settings->pe_cntx_num) { 5717 case I40E_DMA_CNTX_SIZE_512: 5718 case I40E_DMA_CNTX_SIZE_1K: 5719 case I40E_DMA_CNTX_SIZE_2K: 5720 case I40E_DMA_CNTX_SIZE_4K: 5721 case I40E_DMA_CNTX_SIZE_8K: 5722 case I40E_DMA_CNTX_SIZE_16K: 5723 case I40E_DMA_CNTX_SIZE_32K: 5724 case I40E_DMA_CNTX_SIZE_64K: 5725 case I40E_DMA_CNTX_SIZE_128K: 5726 case I40E_DMA_CNTX_SIZE_256K: 5727 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5728 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5729 break; 5730 default: 5731 return I40E_ERR_PARAM; 5732 } 5733 5734 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5735 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5736 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5737 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5738 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5739 return I40E_ERR_INVALID_SIZE; 5740 5741 return I40E_SUCCESS; 5742 } 5743 5744 /** 5745 * i40e_set_filter_control 5746 * @hw: pointer to the hardware structure 5747 * @settings: Filter control settings 5748 * 5749 * Set the Queue Filters for PE/FCoE and enable filters required 5750 * for a single PF. It is expected that these settings are programmed 5751 * at the driver initialization time. 5752 **/ 5753 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5754 struct i40e_filter_control_settings *settings) 5755 { 5756 enum i40e_status_code ret = I40E_SUCCESS; 5757 u32 hash_lut_size = 0; 5758 u32 val; 5759 5760 if (!settings) 5761 return I40E_ERR_PARAM; 5762 5763 /* Validate the input settings */ 5764 ret = i40e_validate_filter_settings(hw, settings); 5765 if (ret) 5766 return ret; 5767 5768 /* Read the PF Queue Filter control register */ 5769 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5770 5771 /* Program required PE hash buckets for the PF */ 5772 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5773 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5774 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5775 /* Program required PE contexts for the PF */ 5776 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5777 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5778 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5779 5780 /* Program required FCoE hash buckets for the PF */ 5781 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5782 val |= ((u32)settings->fcoe_filt_num << 5783 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5784 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5785 /* Program required FCoE DDP contexts for the PF */ 5786 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5787 val |= ((u32)settings->fcoe_cntx_num << 5788 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5789 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5790 5791 /* Program Hash LUT size for the PF */ 5792 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5793 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5794 hash_lut_size = 1; 5795 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5796 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5797 5798 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5799 if (settings->enable_fdir) 5800 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5801 if (settings->enable_ethtype) 5802 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5803 if (settings->enable_macvlan) 5804 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5805 5806 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5807 5808 return I40E_SUCCESS; 5809 } 5810 5811 /** 5812 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5813 * @hw: pointer to the hw struct 5814 * @mac_addr: MAC address to use in the filter 5815 * @ethtype: Ethertype to use in the filter 5816 * @flags: Flags that needs to be applied to the filter 5817 * @vsi_seid: seid of the control VSI 5818 * @queue: VSI queue number to send the packet to 5819 * @is_add: Add control packet filter if True else remove 5820 * @stats: Structure to hold information on control filter counts 5821 * @cmd_details: pointer to command details structure or NULL 5822 * 5823 * This command will Add or Remove control packet filter for a control VSI. 5824 * In return it will update the total number of perfect filter count in 5825 * the stats member. 5826 **/ 5827 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5828 u8 *mac_addr, u16 ethtype, u16 flags, 5829 u16 vsi_seid, u16 queue, bool is_add, 5830 struct i40e_control_filter_stats *stats, 5831 struct i40e_asq_cmd_details *cmd_details) 5832 { 5833 struct i40e_aq_desc desc; 5834 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5835 (struct i40e_aqc_add_remove_control_packet_filter *) 5836 &desc.params.raw; 5837 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5838 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5839 &desc.params.raw; 5840 enum i40e_status_code status; 5841 5842 if (vsi_seid == 0) 5843 return I40E_ERR_PARAM; 5844 5845 if (is_add) { 5846 i40e_fill_default_direct_cmd_desc(&desc, 5847 i40e_aqc_opc_add_control_packet_filter); 5848 cmd->queue = CPU_TO_LE16(queue); 5849 } else { 5850 i40e_fill_default_direct_cmd_desc(&desc, 5851 i40e_aqc_opc_remove_control_packet_filter); 5852 } 5853 5854 if (mac_addr) 5855 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, 5856 I40E_NONDMA_TO_NONDMA); 5857 5858 cmd->etype = CPU_TO_LE16(ethtype); 5859 cmd->flags = CPU_TO_LE16(flags); 5860 cmd->seid = CPU_TO_LE16(vsi_seid); 5861 5862 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5863 5864 if (!status && stats) { 5865 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5866 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5867 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5868 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5869 } 5870 5871 return status; 5872 } 5873 5874 /** 5875 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5876 * @hw: pointer to the hw struct 5877 * @seid: VSI seid to add ethertype filter from 5878 **/ 5879 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5880 u16 seid) 5881 { 5882 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5883 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5884 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5885 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5886 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5887 enum i40e_status_code status; 5888 5889 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5890 seid, 0, true, NULL, 5891 NULL); 5892 if (status) 5893 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5894 } 5895 5896 /** 5897 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5898 * @filters: list of cloud filters 5899 * @filter_count: length of list 5900 * 5901 * There's an issue in the device where the Geneve VNI layout needs 5902 * to be shifted 1 byte over from the VxLAN VNI 5903 **/ 5904 STATIC void i40e_fix_up_geneve_vni( 5905 struct i40e_aqc_cloud_filters_element_data *filters, 5906 u8 filter_count) 5907 { 5908 struct i40e_aqc_cloud_filters_element_data *f = filters; 5909 int i; 5910 5911 for (i = 0; i < filter_count; i++) { 5912 u16 tnl_type; 5913 u32 ti; 5914 5915 tnl_type = (LE16_TO_CPU(f[i].flags) & 5916 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5917 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5918 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5919 ti = LE32_TO_CPU(f[i].tenant_id); 5920 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5921 } 5922 } 5923 } 5924 5925 /** 5926 * i40e_aq_add_cloud_filters 5927 * @hw: pointer to the hardware structure 5928 * @seid: VSI seid to add cloud filters from 5929 * @filters: Buffer which contains the filters to be added 5930 * @filter_count: number of filters contained in the buffer 5931 * 5932 * Set the cloud filters for a given VSI. The contents of the 5933 * i40e_aqc_cloud_filters_element_data are filled 5934 * in by the caller of the function. 5935 * 5936 **/ 5937 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5938 u16 seid, 5939 struct i40e_aqc_cloud_filters_element_data *filters, 5940 u8 filter_count) 5941 { 5942 struct i40e_aq_desc desc; 5943 struct i40e_aqc_add_remove_cloud_filters *cmd = 5944 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5945 enum i40e_status_code status; 5946 u16 buff_len; 5947 5948 i40e_fill_default_direct_cmd_desc(&desc, 5949 i40e_aqc_opc_add_cloud_filters); 5950 5951 buff_len = filter_count * sizeof(*filters); 5952 desc.datalen = CPU_TO_LE16(buff_len); 5953 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5954 cmd->num_filters = filter_count; 5955 cmd->seid = CPU_TO_LE16(seid); 5956 5957 i40e_fix_up_geneve_vni(filters, filter_count); 5958 5959 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5960 5961 return status; 5962 } 5963 5964 /** 5965 * i40e_aq_add_cloud_filters_bb 5966 * @hw: pointer to the hardware structure 5967 * @seid: VSI seid to add cloud filters from 5968 * @filters: Buffer which contains the filters in big buffer to be added 5969 * @filter_count: number of filters contained in the buffer 5970 * 5971 * Set the cloud filters for a given VSI. The contents of the 5972 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of 5973 * the function. 5974 * 5975 **/ 5976 enum i40e_status_code 5977 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5978 struct i40e_aqc_cloud_filters_element_bb *filters, 5979 u8 filter_count) 5980 { 5981 struct i40e_aq_desc desc; 5982 struct i40e_aqc_add_remove_cloud_filters *cmd = 5983 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5984 enum i40e_status_code status; 5985 u16 buff_len; 5986 int i; 5987 5988 i40e_fill_default_direct_cmd_desc(&desc, 5989 i40e_aqc_opc_add_cloud_filters); 5990 5991 buff_len = filter_count * sizeof(*filters); 5992 desc.datalen = CPU_TO_LE16(buff_len); 5993 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5994 cmd->num_filters = filter_count; 5995 cmd->seid = CPU_TO_LE16(seid); 5996 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5997 5998 for (i = 0; i < filter_count; i++) { 5999 u16 tnl_type; 6000 u32 ti; 6001 6002 tnl_type = (LE16_TO_CPU(filters[i].element.flags) & 6003 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 6004 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 6005 6006 /* Due to hardware eccentricities, the VNI for Geneve is shifted 6007 * one more byte further than normally used for Tenant ID in 6008 * other tunnel types. 6009 */ 6010 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 6011 ti = LE32_TO_CPU(filters[i].element.tenant_id); 6012 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8); 6013 } 6014 } 6015 6016 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 6017 6018 return status; 6019 } 6020 6021 /** 6022 * i40e_aq_rem_cloud_filters 6023 * @hw: pointer to the hardware structure 6024 * @seid: VSI seid to remove cloud filters from 6025 * @filters: Buffer which contains the filters to be removed 6026 * @filter_count: number of filters contained in the buffer 6027 * 6028 * Remove the cloud filters for a given VSI. The contents of the 6029 * i40e_aqc_cloud_filters_element_data are filled in by the caller 6030 * of the function. 6031 * 6032 **/ 6033 enum i40e_status_code 6034 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 6035 struct i40e_aqc_cloud_filters_element_data *filters, 6036 u8 filter_count) 6037 { 6038 struct i40e_aq_desc desc; 6039 struct i40e_aqc_add_remove_cloud_filters *cmd = 6040 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 6041 enum i40e_status_code status; 6042 u16 buff_len; 6043 6044 i40e_fill_default_direct_cmd_desc(&desc, 6045 i40e_aqc_opc_remove_cloud_filters); 6046 6047 buff_len = filter_count * sizeof(*filters); 6048 desc.datalen = CPU_TO_LE16(buff_len); 6049 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 6050 cmd->num_filters = filter_count; 6051 cmd->seid = CPU_TO_LE16(seid); 6052 6053 i40e_fix_up_geneve_vni(filters, filter_count); 6054 6055 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 6056 6057 return status; 6058 } 6059 6060 /** 6061 * i40e_aq_rem_cloud_filters_bb 6062 * @hw: pointer to the hardware structure 6063 * @seid: VSI seid to remove cloud filters from 6064 * @filters: Buffer which contains the filters in big buffer to be removed 6065 * @filter_count: number of filters contained in the buffer 6066 * 6067 * Remove the big buffer cloud filters for a given VSI. The contents of the 6068 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 6069 * function. 6070 * 6071 **/ 6072 enum i40e_status_code 6073 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 6074 struct i40e_aqc_cloud_filters_element_bb *filters, 6075 u8 filter_count) 6076 { 6077 struct i40e_aq_desc desc; 6078 struct i40e_aqc_add_remove_cloud_filters *cmd = 6079 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 6080 enum i40e_status_code status; 6081 u16 buff_len; 6082 int i; 6083 6084 i40e_fill_default_direct_cmd_desc(&desc, 6085 i40e_aqc_opc_remove_cloud_filters); 6086 6087 buff_len = filter_count * sizeof(*filters); 6088 desc.datalen = CPU_TO_LE16(buff_len); 6089 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 6090 cmd->num_filters = filter_count; 6091 cmd->seid = CPU_TO_LE16(seid); 6092 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 6093 6094 for (i = 0; i < filter_count; i++) { 6095 u16 tnl_type; 6096 u32 ti; 6097 6098 tnl_type = (LE16_TO_CPU(filters[i].element.flags) & 6099 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 6100 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 6101 6102 /* Due to hardware eccentricities, the VNI for Geneve is shifted 6103 * one more byte further than normally used for Tenant ID in 6104 * other tunnel types. 6105 */ 6106 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 6107 ti = LE32_TO_CPU(filters[i].element.tenant_id); 6108 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8); 6109 } 6110 } 6111 6112 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 6113 6114 return status; 6115 } 6116 6117 /** 6118 * i40e_aq_replace_cloud_filters - Replace cloud filter command 6119 * @hw: pointer to the hw struct 6120 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct 6121 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct 6122 * 6123 **/ 6124 enum 6125 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw, 6126 struct i40e_aqc_replace_cloud_filters_cmd *filters, 6127 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf) 6128 { 6129 struct i40e_aq_desc desc; 6130 struct i40e_aqc_replace_cloud_filters_cmd *cmd = 6131 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw; 6132 enum i40e_status_code status = I40E_SUCCESS; 6133 int i = 0; 6134 6135 /* X722 doesn't support this command */ 6136 if (hw->mac.type == I40E_MAC_X722) 6137 return I40E_ERR_DEVICE_NOT_SUPPORTED; 6138 6139 /* need FW version greater than 6.00 */ 6140 if (hw->aq.fw_maj_ver < 6) 6141 return I40E_NOT_SUPPORTED; 6142 6143 i40e_fill_default_direct_cmd_desc(&desc, 6144 i40e_aqc_opc_replace_cloud_filters); 6145 6146 desc.datalen = CPU_TO_LE16(32); 6147 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 6148 cmd->old_filter_type = filters->old_filter_type; 6149 cmd->new_filter_type = filters->new_filter_type; 6150 cmd->valid_flags = filters->valid_flags; 6151 cmd->tr_bit = filters->tr_bit; 6152 cmd->tr_bit2 = filters->tr_bit2; 6153 6154 status = i40e_asq_send_command(hw, &desc, cmd_buf, 6155 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL); 6156 6157 /* for get cloud filters command */ 6158 for (i = 0; i < 32; i += 4) { 6159 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i]; 6160 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1]; 6161 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2]; 6162 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3]; 6163 } 6164 6165 return status; 6166 } 6167 6168 6169 /** 6170 * i40e_aq_alternate_write 6171 * @hw: pointer to the hardware structure 6172 * @reg_addr0: address of first dword to be read 6173 * @reg_val0: value to be written under 'reg_addr0' 6174 * @reg_addr1: address of second dword to be read 6175 * @reg_val1: value to be written under 'reg_addr1' 6176 * 6177 * Write one or two dwords to alternate structure. Fields are indicated 6178 * by 'reg_addr0' and 'reg_addr1' register numbers. 6179 * 6180 **/ 6181 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 6182 u32 reg_addr0, u32 reg_val0, 6183 u32 reg_addr1, u32 reg_val1) 6184 { 6185 struct i40e_aq_desc desc; 6186 struct i40e_aqc_alternate_write *cmd_resp = 6187 (struct i40e_aqc_alternate_write *)&desc.params.raw; 6188 enum i40e_status_code status; 6189 6190 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 6191 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 6192 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 6193 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 6194 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 6195 6196 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6197 6198 return status; 6199 } 6200 6201 /** 6202 * i40e_aq_alternate_write_indirect 6203 * @hw: pointer to the hardware structure 6204 * @addr: address of a first register to be modified 6205 * @dw_count: number of alternate structure fields to write 6206 * @buffer: pointer to the command buffer 6207 * 6208 * Write 'dw_count' dwords from 'buffer' to alternate structure 6209 * starting at 'addr'. 6210 * 6211 **/ 6212 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 6213 u32 addr, u32 dw_count, void *buffer) 6214 { 6215 struct i40e_aq_desc desc; 6216 struct i40e_aqc_alternate_ind_write *cmd_resp = 6217 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 6218 enum i40e_status_code status; 6219 6220 if (buffer == NULL) 6221 return I40E_ERR_PARAM; 6222 6223 /* Indirect command */ 6224 i40e_fill_default_direct_cmd_desc(&desc, 6225 i40e_aqc_opc_alternate_write_indirect); 6226 6227 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 6228 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 6229 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 6230 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6231 6232 cmd_resp->address = CPU_TO_LE32(addr); 6233 cmd_resp->length = CPU_TO_LE32(dw_count); 6234 6235 status = i40e_asq_send_command(hw, &desc, buffer, 6236 I40E_LO_DWORD(4*dw_count), NULL); 6237 6238 return status; 6239 } 6240 6241 /** 6242 * i40e_aq_alternate_read 6243 * @hw: pointer to the hardware structure 6244 * @reg_addr0: address of first dword to be read 6245 * @reg_val0: pointer for data read from 'reg_addr0' 6246 * @reg_addr1: address of second dword to be read 6247 * @reg_val1: pointer for data read from 'reg_addr1' 6248 * 6249 * Read one or two dwords from alternate structure. Fields are indicated 6250 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 6251 * is not passed then only register at 'reg_addr0' is read. 6252 * 6253 **/ 6254 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 6255 u32 reg_addr0, u32 *reg_val0, 6256 u32 reg_addr1, u32 *reg_val1) 6257 { 6258 struct i40e_aq_desc desc; 6259 struct i40e_aqc_alternate_write *cmd_resp = 6260 (struct i40e_aqc_alternate_write *)&desc.params.raw; 6261 enum i40e_status_code status; 6262 6263 if (reg_val0 == NULL) 6264 return I40E_ERR_PARAM; 6265 6266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 6267 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 6268 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 6269 6270 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6271 6272 if (status == I40E_SUCCESS) { 6273 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 6274 6275 if (reg_val1 != NULL) 6276 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 6277 } 6278 6279 return status; 6280 } 6281 6282 /** 6283 * i40e_aq_alternate_read_indirect 6284 * @hw: pointer to the hardware structure 6285 * @addr: address of the alternate structure field 6286 * @dw_count: number of alternate structure fields to read 6287 * @buffer: pointer to the command buffer 6288 * 6289 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 6290 * place them in 'buffer'. The buffer should be allocated by caller. 6291 * 6292 **/ 6293 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 6294 u32 addr, u32 dw_count, void *buffer) 6295 { 6296 struct i40e_aq_desc desc; 6297 struct i40e_aqc_alternate_ind_write *cmd_resp = 6298 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 6299 enum i40e_status_code status; 6300 6301 if (buffer == NULL) 6302 return I40E_ERR_PARAM; 6303 6304 /* Indirect command */ 6305 i40e_fill_default_direct_cmd_desc(&desc, 6306 i40e_aqc_opc_alternate_read_indirect); 6307 6308 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 6309 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 6310 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 6311 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6312 6313 cmd_resp->address = CPU_TO_LE32(addr); 6314 cmd_resp->length = CPU_TO_LE32(dw_count); 6315 6316 status = i40e_asq_send_command(hw, &desc, buffer, 6317 I40E_LO_DWORD(4*dw_count), NULL); 6318 6319 return status; 6320 } 6321 6322 /** 6323 * i40e_aq_alternate_clear 6324 * @hw: pointer to the HW structure. 6325 * 6326 * Clear the alternate structures of the port from which the function 6327 * is called. 6328 * 6329 **/ 6330 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 6331 { 6332 struct i40e_aq_desc desc; 6333 enum i40e_status_code status; 6334 6335 i40e_fill_default_direct_cmd_desc(&desc, 6336 i40e_aqc_opc_alternate_clear_port); 6337 6338 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6339 6340 return status; 6341 } 6342 6343 /** 6344 * i40e_aq_alternate_write_done 6345 * @hw: pointer to the HW structure. 6346 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 6347 * @reset_needed: indicates the SW should trigger GLOBAL reset 6348 * 6349 * Indicates to the FW that alternate structures have been changed. 6350 * 6351 **/ 6352 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 6353 u8 bios_mode, bool *reset_needed) 6354 { 6355 struct i40e_aq_desc desc; 6356 struct i40e_aqc_alternate_write_done *cmd = 6357 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 6358 enum i40e_status_code status; 6359 6360 if (reset_needed == NULL) 6361 return I40E_ERR_PARAM; 6362 6363 i40e_fill_default_direct_cmd_desc(&desc, 6364 i40e_aqc_opc_alternate_write_done); 6365 6366 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 6367 6368 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6369 if (!status && reset_needed) 6370 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 6371 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 6372 6373 return status; 6374 } 6375 6376 /** 6377 * i40e_aq_set_oem_mode 6378 * @hw: pointer to the HW structure. 6379 * @oem_mode: the OEM mode to be used 6380 * 6381 * Sets the device to a specific operating mode. Currently the only supported 6382 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 6383 * 6384 **/ 6385 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 6386 u8 oem_mode) 6387 { 6388 struct i40e_aq_desc desc; 6389 struct i40e_aqc_alternate_write_done *cmd = 6390 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 6391 enum i40e_status_code status; 6392 6393 i40e_fill_default_direct_cmd_desc(&desc, 6394 i40e_aqc_opc_alternate_set_mode); 6395 6396 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 6397 6398 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6399 6400 return status; 6401 } 6402 6403 /** 6404 * i40e_aq_resume_port_tx 6405 * @hw: pointer to the hardware structure 6406 * @cmd_details: pointer to command details structure or NULL 6407 * 6408 * Resume port's Tx traffic 6409 **/ 6410 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 6411 struct i40e_asq_cmd_details *cmd_details) 6412 { 6413 struct i40e_aq_desc desc; 6414 enum i40e_status_code status; 6415 6416 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 6417 6418 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6419 6420 return status; 6421 } 6422 6423 /** 6424 * i40e_set_pci_config_data - store PCI bus info 6425 * @hw: pointer to hardware structure 6426 * @link_status: the link status word from PCI config space 6427 * 6428 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 6429 **/ 6430 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 6431 { 6432 hw->bus.type = i40e_bus_type_pci_express; 6433 6434 switch (link_status & I40E_PCI_LINK_WIDTH) { 6435 case I40E_PCI_LINK_WIDTH_1: 6436 hw->bus.width = i40e_bus_width_pcie_x1; 6437 break; 6438 case I40E_PCI_LINK_WIDTH_2: 6439 hw->bus.width = i40e_bus_width_pcie_x2; 6440 break; 6441 case I40E_PCI_LINK_WIDTH_4: 6442 hw->bus.width = i40e_bus_width_pcie_x4; 6443 break; 6444 case I40E_PCI_LINK_WIDTH_8: 6445 hw->bus.width = i40e_bus_width_pcie_x8; 6446 break; 6447 default: 6448 hw->bus.width = i40e_bus_width_unknown; 6449 break; 6450 } 6451 6452 switch (link_status & I40E_PCI_LINK_SPEED) { 6453 case I40E_PCI_LINK_SPEED_2500: 6454 hw->bus.speed = i40e_bus_speed_2500; 6455 break; 6456 case I40E_PCI_LINK_SPEED_5000: 6457 hw->bus.speed = i40e_bus_speed_5000; 6458 break; 6459 case I40E_PCI_LINK_SPEED_8000: 6460 hw->bus.speed = i40e_bus_speed_8000; 6461 break; 6462 default: 6463 hw->bus.speed = i40e_bus_speed_unknown; 6464 break; 6465 } 6466 } 6467 6468 /** 6469 * i40e_aq_debug_dump 6470 * @hw: pointer to the hardware structure 6471 * @cluster_id: specific cluster to dump 6472 * @table_id: table id within cluster 6473 * @start_index: index of line in the block to read 6474 * @buff_size: dump buffer size 6475 * @buff: dump buffer 6476 * @ret_buff_size: actual buffer size returned 6477 * @ret_next_table: next block to read 6478 * @ret_next_index: next index to read 6479 * @cmd_details: pointer to command details structure or NULL 6480 * 6481 * Dump internal FW/HW data for debug purposes. 6482 * 6483 **/ 6484 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 6485 u8 table_id, u32 start_index, u16 buff_size, 6486 void *buff, u16 *ret_buff_size, 6487 u8 *ret_next_table, u32 *ret_next_index, 6488 struct i40e_asq_cmd_details *cmd_details) 6489 { 6490 struct i40e_aq_desc desc; 6491 struct i40e_aqc_debug_dump_internals *cmd = 6492 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6493 struct i40e_aqc_debug_dump_internals *resp = 6494 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6495 enum i40e_status_code status; 6496 6497 if (buff_size == 0 || !buff) 6498 return I40E_ERR_PARAM; 6499 6500 i40e_fill_default_direct_cmd_desc(&desc, 6501 i40e_aqc_opc_debug_dump_internals); 6502 /* Indirect Command */ 6503 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6504 if (buff_size > I40E_AQ_LARGE_BUF) 6505 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6506 6507 cmd->cluster_id = cluster_id; 6508 cmd->table_id = table_id; 6509 cmd->idx = CPU_TO_LE32(start_index); 6510 6511 desc.datalen = CPU_TO_LE16(buff_size); 6512 6513 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 6514 if (!status) { 6515 if (ret_buff_size != NULL) 6516 *ret_buff_size = LE16_TO_CPU(desc.datalen); 6517 if (ret_next_table != NULL) 6518 *ret_next_table = resp->table_id; 6519 if (ret_next_index != NULL) 6520 *ret_next_index = LE32_TO_CPU(resp->idx); 6521 } 6522 6523 return status; 6524 } 6525 6526 6527 /** 6528 * i40e_enable_eee 6529 * @hw: pointer to the hardware structure 6530 * @enable: state of Energy Efficient Ethernet mode to be set 6531 * 6532 * Enables or disables Energy Efficient Ethernet (EEE) mode 6533 * accordingly to @enable parameter. 6534 **/ 6535 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable) 6536 { 6537 struct i40e_aq_get_phy_abilities_resp abilities; 6538 struct i40e_aq_set_phy_config config; 6539 enum i40e_status_code status; 6540 __le16 eee_capability; 6541 6542 /* Get initial PHY capabilities */ 6543 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, 6544 NULL); 6545 if (status) 6546 goto err; 6547 6548 /* Check whether NIC configuration is compatible with Energy Efficient 6549 * Ethernet (EEE) mode. 6550 */ 6551 if (abilities.eee_capability == 0) { 6552 status = I40E_ERR_CONFIG; 6553 goto err; 6554 } 6555 6556 /* Cache initial EEE capability */ 6557 eee_capability = abilities.eee_capability; 6558 6559 /* Get current configuration */ 6560 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 6561 NULL); 6562 if (status) 6563 goto err; 6564 6565 /* Cache current configuration */ 6566 config.phy_type = abilities.phy_type; 6567 config.phy_type_ext = abilities.phy_type_ext; 6568 config.link_speed = abilities.link_speed; 6569 config.abilities = abilities.abilities | 6570 I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 6571 config.eeer = abilities.eeer_val; 6572 config.low_power_ctrl = abilities.d3_lpan; 6573 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 6574 I40E_AQ_PHY_FEC_CONFIG_MASK; 6575 6576 /* Set desired EEE state */ 6577 if (enable) { 6578 config.eee_capability = eee_capability; 6579 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK; 6580 } else { 6581 config.eee_capability = 0; 6582 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK; 6583 } 6584 6585 /* Save modified config */ 6586 status = i40e_aq_set_phy_config(hw, &config, NULL); 6587 err: 6588 return status; 6589 } 6590 6591 /** 6592 * i40e_read_bw_from_alt_ram 6593 * @hw: pointer to the hardware structure 6594 * @max_bw: pointer for max_bw read 6595 * @min_bw: pointer for min_bw read 6596 * @min_valid: pointer for bool that is true if min_bw is a valid value 6597 * @max_valid: pointer for bool that is true if max_bw is a valid value 6598 * 6599 * Read bw from the alternate ram for the given pf 6600 **/ 6601 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 6602 u32 *max_bw, u32 *min_bw, 6603 bool *min_valid, bool *max_valid) 6604 { 6605 enum i40e_status_code status; 6606 u32 max_bw_addr, min_bw_addr; 6607 6608 /* Calculate the address of the min/max bw registers */ 6609 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6610 I40E_ALT_STRUCT_MAX_BW_OFFSET + 6611 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6612 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6613 I40E_ALT_STRUCT_MIN_BW_OFFSET + 6614 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6615 6616 /* Read the bandwidths from alt ram */ 6617 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 6618 min_bw_addr, min_bw); 6619 6620 if (*min_bw & I40E_ALT_BW_VALID_MASK) 6621 *min_valid = true; 6622 else 6623 *min_valid = false; 6624 6625 if (*max_bw & I40E_ALT_BW_VALID_MASK) 6626 *max_valid = true; 6627 else 6628 *max_valid = false; 6629 6630 return status; 6631 } 6632 6633 /** 6634 * i40e_aq_configure_partition_bw 6635 * @hw: pointer to the hardware structure 6636 * @bw_data: Buffer holding valid pfs and bw limits 6637 * @cmd_details: pointer to command details 6638 * 6639 * Configure partitions guaranteed/max bw 6640 **/ 6641 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 6642 struct i40e_aqc_configure_partition_bw_data *bw_data, 6643 struct i40e_asq_cmd_details *cmd_details) 6644 { 6645 enum i40e_status_code status; 6646 struct i40e_aq_desc desc; 6647 u16 bwd_size = sizeof(*bw_data); 6648 6649 i40e_fill_default_direct_cmd_desc(&desc, 6650 i40e_aqc_opc_configure_partition_bw); 6651 6652 /* Indirect command */ 6653 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6654 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6655 6656 desc.datalen = CPU_TO_LE16(bwd_size); 6657 6658 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6659 6660 return status; 6661 } 6662 6663 /** 6664 * i40e_read_phy_register_clause22 6665 * @hw: pointer to the HW structure 6666 * @reg: register address in the page 6667 * @phy_addr: PHY address on MDIO interface 6668 * @value: PHY register value 6669 * 6670 * Reads specified PHY register value 6671 **/ 6672 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6673 u16 reg, u8 phy_addr, u16 *value) 6674 { 6675 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6676 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6677 u32 command = 0; 6678 u16 retry = 1000; 6679 6680 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6681 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6682 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6683 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6684 (I40E_GLGEN_MSCA_MDICMD_MASK); 6685 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6686 do { 6687 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6688 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6689 status = I40E_SUCCESS; 6690 break; 6691 } 6692 i40e_usec_delay(10); 6693 retry--; 6694 } while (retry); 6695 6696 if (status) { 6697 i40e_debug(hw, I40E_DEBUG_PHY, 6698 "PHY: Can't write command to external PHY.\n"); 6699 } else { 6700 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6701 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6702 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6703 } 6704 6705 return status; 6706 } 6707 6708 /** 6709 * i40e_write_phy_register_clause22 6710 * @hw: pointer to the HW structure 6711 * @reg: register address in the page 6712 * @phy_addr: PHY address on MDIO interface 6713 * @value: PHY register value 6714 * 6715 * Writes specified PHY register value 6716 **/ 6717 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6718 u16 reg, u8 phy_addr, u16 value) 6719 { 6720 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6721 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6722 u32 command = 0; 6723 u16 retry = 1000; 6724 6725 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6726 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6727 6728 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6729 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6730 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6731 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6732 (I40E_GLGEN_MSCA_MDICMD_MASK); 6733 6734 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6735 do { 6736 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6737 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6738 status = I40E_SUCCESS; 6739 break; 6740 } 6741 i40e_usec_delay(10); 6742 retry--; 6743 } while (retry); 6744 6745 return status; 6746 } 6747 6748 /** 6749 * i40e_read_phy_register_clause45 6750 * @hw: pointer to the HW structure 6751 * @page: registers page number 6752 * @reg: register address in the page 6753 * @phy_addr: PHY address on MDIO interface 6754 * @value: PHY register value 6755 * 6756 * Reads specified PHY register value 6757 **/ 6758 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6759 u8 page, u16 reg, u8 phy_addr, u16 *value) 6760 { 6761 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6762 u32 command = 0; 6763 u16 retry = 1000; 6764 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6765 6766 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6767 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6768 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6769 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6770 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6771 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6772 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6773 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6774 do { 6775 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6776 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6777 status = I40E_SUCCESS; 6778 break; 6779 } 6780 i40e_usec_delay(10); 6781 retry--; 6782 } while (retry); 6783 6784 if (status) { 6785 i40e_debug(hw, I40E_DEBUG_PHY, 6786 "PHY: Can't write command to external PHY.\n"); 6787 goto phy_read_end; 6788 } 6789 6790 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6791 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6792 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6793 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6794 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6795 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6796 status = I40E_ERR_TIMEOUT; 6797 retry = 1000; 6798 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6799 do { 6800 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6801 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6802 status = I40E_SUCCESS; 6803 break; 6804 } 6805 i40e_usec_delay(10); 6806 retry--; 6807 } while (retry); 6808 6809 if (!status) { 6810 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6811 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6812 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6813 } else { 6814 i40e_debug(hw, I40E_DEBUG_PHY, 6815 "PHY: Can't read register value from external PHY.\n"); 6816 } 6817 6818 phy_read_end: 6819 return status; 6820 } 6821 6822 /** 6823 * i40e_write_phy_register_clause45 6824 * @hw: pointer to the HW structure 6825 * @page: registers page number 6826 * @reg: register address in the page 6827 * @phy_addr: PHY address on MDIO interface 6828 * @value: PHY register value 6829 * 6830 * Writes value to specified PHY register 6831 **/ 6832 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6833 u8 page, u16 reg, u8 phy_addr, u16 value) 6834 { 6835 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6836 u32 command = 0; 6837 u16 retry = 1000; 6838 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6839 6840 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6841 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6842 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6843 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6844 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6845 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6846 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6847 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6848 do { 6849 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6850 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6851 status = I40E_SUCCESS; 6852 break; 6853 } 6854 i40e_usec_delay(10); 6855 retry--; 6856 } while (retry); 6857 if (status) { 6858 i40e_debug(hw, I40E_DEBUG_PHY, 6859 "PHY: Can't write command to external PHY.\n"); 6860 goto phy_write_end; 6861 } 6862 6863 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6864 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6865 6866 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6867 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6868 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6869 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6870 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6871 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6872 status = I40E_ERR_TIMEOUT; 6873 retry = 1000; 6874 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6875 do { 6876 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6877 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6878 status = I40E_SUCCESS; 6879 break; 6880 } 6881 i40e_usec_delay(10); 6882 retry--; 6883 } while (retry); 6884 6885 phy_write_end: 6886 return status; 6887 } 6888 6889 /** 6890 * i40e_write_phy_register 6891 * @hw: pointer to the HW structure 6892 * @page: registers page number 6893 * @reg: register address in the page 6894 * @phy_addr: PHY address on MDIO interface 6895 * @value: PHY register value 6896 * 6897 * Writes value to specified PHY register 6898 **/ 6899 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6900 u8 page, u16 reg, u8 phy_addr, u16 value) 6901 { 6902 enum i40e_status_code status; 6903 6904 switch (hw->device_id) { 6905 case I40E_DEV_ID_1G_BASE_T_X722: 6906 status = i40e_write_phy_register_clause22(hw, 6907 reg, phy_addr, value); 6908 break; 6909 case I40E_DEV_ID_10G_BASE_T: 6910 case I40E_DEV_ID_10G_BASE_T4: 6911 case I40E_DEV_ID_10G_BASE_T_BC: 6912 case I40E_DEV_ID_5G_BASE_T_BC: 6913 case I40E_DEV_ID_10G_BASE_T_X722: 6914 case I40E_DEV_ID_25G_B: 6915 case I40E_DEV_ID_25G_SFP28: 6916 status = i40e_write_phy_register_clause45(hw, 6917 page, reg, phy_addr, value); 6918 break; 6919 default: 6920 status = I40E_ERR_UNKNOWN_PHY; 6921 break; 6922 } 6923 6924 return status; 6925 } 6926 6927 /** 6928 * i40e_read_phy_register 6929 * @hw: pointer to the HW structure 6930 * @page: registers page number 6931 * @reg: register address in the page 6932 * @phy_addr: PHY address on MDIO interface 6933 * @value: PHY register value 6934 * 6935 * Reads specified PHY register value 6936 **/ 6937 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6938 u8 page, u16 reg, u8 phy_addr, u16 *value) 6939 { 6940 enum i40e_status_code status; 6941 6942 switch (hw->device_id) { 6943 case I40E_DEV_ID_1G_BASE_T_X722: 6944 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6945 value); 6946 break; 6947 case I40E_DEV_ID_10G_BASE_T: 6948 case I40E_DEV_ID_10G_BASE_T4: 6949 case I40E_DEV_ID_5G_BASE_T_BC: 6950 case I40E_DEV_ID_10G_BASE_T_X722: 6951 case I40E_DEV_ID_25G_B: 6952 case I40E_DEV_ID_25G_SFP28: 6953 status = i40e_read_phy_register_clause45(hw, page, reg, 6954 phy_addr, value); 6955 break; 6956 default: 6957 status = I40E_ERR_UNKNOWN_PHY; 6958 break; 6959 } 6960 6961 return status; 6962 } 6963 6964 /** 6965 * i40e_get_phy_address 6966 * @hw: pointer to the HW structure 6967 * @dev_num: PHY port num that address we want 6968 * 6969 * Gets PHY address for current port 6970 **/ 6971 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6972 { 6973 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6974 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6975 6976 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6977 } 6978 6979 /** 6980 * i40e_blink_phy_link_led 6981 * @hw: pointer to the HW structure 6982 * @time: time how long led will blinks in secs 6983 * @interval: gap between LED on and off in msecs 6984 * 6985 * Blinks PHY link LED 6986 **/ 6987 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6988 u32 time, u32 interval) 6989 { 6990 enum i40e_status_code status = I40E_SUCCESS; 6991 u32 i; 6992 u16 led_ctl = 0; 6993 u16 gpio_led_port; 6994 u16 led_reg; 6995 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6996 u8 phy_addr = 0; 6997 u8 port_num; 6998 6999 i = rd32(hw, I40E_PFGEN_PORTNUM); 7000 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 7001 phy_addr = i40e_get_phy_address(hw, port_num); 7002 7003 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 7004 led_addr++) { 7005 status = i40e_read_phy_register_clause45(hw, 7006 I40E_PHY_COM_REG_PAGE, 7007 led_addr, phy_addr, 7008 &led_reg); 7009 if (status) 7010 goto phy_blinking_end; 7011 led_ctl = led_reg; 7012 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 7013 led_reg = 0; 7014 status = i40e_write_phy_register_clause45(hw, 7015 I40E_PHY_COM_REG_PAGE, 7016 led_addr, phy_addr, 7017 led_reg); 7018 if (status) 7019 goto phy_blinking_end; 7020 break; 7021 } 7022 } 7023 7024 if (time > 0 && interval > 0) { 7025 for (i = 0; i < time * 1000; i += interval) { 7026 status = i40e_read_phy_register_clause45(hw, 7027 I40E_PHY_COM_REG_PAGE, 7028 led_addr, phy_addr, &led_reg); 7029 if (status) 7030 goto restore_config; 7031 if (led_reg & I40E_PHY_LED_MANUAL_ON) 7032 led_reg = 0; 7033 else 7034 led_reg = I40E_PHY_LED_MANUAL_ON; 7035 status = i40e_write_phy_register_clause45(hw, 7036 I40E_PHY_COM_REG_PAGE, 7037 led_addr, phy_addr, led_reg); 7038 if (status) 7039 goto restore_config; 7040 i40e_msec_delay(interval); 7041 } 7042 } 7043 7044 restore_config: 7045 status = i40e_write_phy_register_clause45(hw, 7046 I40E_PHY_COM_REG_PAGE, 7047 led_addr, phy_addr, led_ctl); 7048 7049 phy_blinking_end: 7050 return status; 7051 } 7052 7053 /** 7054 * i40e_led_get_reg - read LED register 7055 * @hw: pointer to the HW structure 7056 * @led_addr: LED register address 7057 * @reg_val: read register value 7058 **/ 7059 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 7060 u32 *reg_val) 7061 { 7062 enum i40e_status_code status; 7063 u8 phy_addr = 0; 7064 7065 *reg_val = 0; 7066 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 7067 status = i40e_aq_get_phy_register(hw, 7068 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 7069 I40E_PHY_COM_REG_PAGE, true, 7070 I40E_PHY_LED_PROV_REG_1, 7071 reg_val, NULL); 7072 } else { 7073 phy_addr = i40e_get_phy_address(hw, hw->port); 7074 status = i40e_read_phy_register_clause45(hw, 7075 I40E_PHY_COM_REG_PAGE, 7076 led_addr, phy_addr, 7077 (u16 *)reg_val); 7078 } 7079 return status; 7080 } 7081 7082 /** 7083 * i40e_led_set_reg - write LED register 7084 * @hw: pointer to the HW structure 7085 * @led_addr: LED register address 7086 * @reg_val: register value to write 7087 **/ 7088 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 7089 u32 reg_val) 7090 { 7091 enum i40e_status_code status; 7092 u8 phy_addr = 0; 7093 7094 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 7095 status = i40e_aq_set_phy_register(hw, 7096 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 7097 I40E_PHY_COM_REG_PAGE, true, 7098 I40E_PHY_LED_PROV_REG_1, 7099 reg_val, NULL); 7100 } else { 7101 phy_addr = i40e_get_phy_address(hw, hw->port); 7102 status = i40e_write_phy_register_clause45(hw, 7103 I40E_PHY_COM_REG_PAGE, 7104 led_addr, phy_addr, 7105 (u16)reg_val); 7106 } 7107 7108 return status; 7109 } 7110 7111 /** 7112 * i40e_led_get_phy - return current on/off mode 7113 * @hw: pointer to the hw struct 7114 * @led_addr: address of led register to use 7115 * @val: original value of register to use 7116 * 7117 **/ 7118 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 7119 u16 *val) 7120 { 7121 enum i40e_status_code status = I40E_SUCCESS; 7122 u16 gpio_led_port; 7123 u32 reg_val_aq; 7124 u16 temp_addr; 7125 u8 phy_addr = 0; 7126 u16 reg_val; 7127 7128 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 7129 status = i40e_aq_get_phy_register(hw, 7130 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 7131 I40E_PHY_COM_REG_PAGE, true, 7132 I40E_PHY_LED_PROV_REG_1, 7133 ®_val_aq, NULL); 7134 if (status == I40E_SUCCESS) 7135 *val = (u16)reg_val_aq; 7136 return status; 7137 } 7138 temp_addr = I40E_PHY_LED_PROV_REG_1; 7139 phy_addr = i40e_get_phy_address(hw, hw->port); 7140 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 7141 temp_addr++) { 7142 status = i40e_read_phy_register_clause45(hw, 7143 I40E_PHY_COM_REG_PAGE, 7144 temp_addr, phy_addr, 7145 ®_val); 7146 if (status) 7147 return status; 7148 *val = reg_val; 7149 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 7150 *led_addr = temp_addr; 7151 break; 7152 } 7153 } 7154 return status; 7155 } 7156 7157 /** 7158 * i40e_led_set_phy 7159 * @hw: pointer to the HW structure 7160 * @on: true or false 7161 * @led_addr: address of led register to use 7162 * @mode: original val plus bit for set or ignore 7163 * 7164 * Set led's on or off when controlled by the PHY 7165 * 7166 **/ 7167 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 7168 u16 led_addr, u32 mode) 7169 { 7170 enum i40e_status_code status = I40E_SUCCESS; 7171 u32 led_ctl = 0; 7172 u32 led_reg = 0; 7173 7174 status = i40e_led_get_reg(hw, led_addr, &led_reg); 7175 if (status) 7176 return status; 7177 led_ctl = led_reg; 7178 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 7179 led_reg = 0; 7180 status = i40e_led_set_reg(hw, led_addr, led_reg); 7181 if (status) 7182 return status; 7183 } 7184 status = i40e_led_get_reg(hw, led_addr, &led_reg); 7185 if (status) 7186 goto restore_config; 7187 if (on) 7188 led_reg = I40E_PHY_LED_MANUAL_ON; 7189 else 7190 led_reg = 0; 7191 status = i40e_led_set_reg(hw, led_addr, led_reg); 7192 if (status) 7193 goto restore_config; 7194 if (mode & I40E_PHY_LED_MODE_ORIG) { 7195 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 7196 status = i40e_led_set_reg(hw, led_addr, led_ctl); 7197 } 7198 return status; 7199 7200 restore_config: 7201 status = i40e_led_set_reg(hw, led_addr, led_ctl); 7202 return status; 7203 } 7204 #endif /* PF_DRIVER */ 7205 /** 7206 * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register 7207 * @hw: pointer to the hw struct 7208 * @stat: pointer to structure with status of rx and tx lpi 7209 * 7210 * Read LPI state directly from external PHY register or from MAC 7211 * register, depending on device ID and current link speed. 7212 */ 7213 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw, 7214 struct i40e_hw_port_stats *stat) 7215 { 7216 enum i40e_status_code ret = I40E_SUCCESS; 7217 bool eee_mrvl_phy; 7218 bool eee_bcm_phy; 7219 u32 val; 7220 7221 stat->rx_lpi_status = 0; 7222 stat->tx_lpi_status = 0; 7223 7224 eee_bcm_phy = 7225 (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC || 7226 hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) && 7227 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB || 7228 hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB); 7229 eee_mrvl_phy = 7230 hw->device_id == I40E_DEV_ID_1G_BASE_T_X722; 7231 7232 if (eee_bcm_phy || eee_mrvl_phy) { 7233 /* read Clause 45 PCS Status 1 register */ 7234 ret = i40e_aq_get_phy_register(hw, 7235 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 7236 I40E_BCM_PHY_PCS_STATUS1_PAGE, 7237 true, 7238 I40E_BCM_PHY_PCS_STATUS1_REG, 7239 &val, NULL); 7240 7241 if (ret != I40E_SUCCESS) 7242 return ret; 7243 7244 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI); 7245 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI); 7246 7247 return ret; 7248 } 7249 7250 val = rd32(hw, I40E_PRTPM_EEE_STAT); 7251 stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> 7252 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; 7253 stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> 7254 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; 7255 7256 return ret; 7257 } 7258 7259 /** 7260 * i40e_get_lpi_counters - read LPI counters from EEE statistics 7261 * @hw: pointer to the hw struct 7262 * @tx_counter: pointer to memory for TX LPI counter 7263 * @rx_counter: pointer to memory for RX LPI counter 7264 * @is_clear: returns true if counters are clear after read 7265 * 7266 * Read Low Power Idle (LPI) mode counters from Energy Efficient 7267 * Ethernet (EEE) statistics. 7268 **/ 7269 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw, 7270 u32 *tx_counter, u32 *rx_counter, 7271 bool *is_clear) 7272 { 7273 /* only X710-T*L requires special handling of counters 7274 * for other devices we just read the MAC registers 7275 */ 7276 if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC || 7277 hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) && 7278 hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) { 7279 enum i40e_status_code retval; 7280 u32 cmd_status = 0; 7281 7282 *is_clear = false; 7283 retval = i40e_aq_run_phy_activity(hw, 7284 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND, 7285 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT, 7286 &cmd_status, tx_counter, rx_counter, NULL); 7287 7288 if (!retval && cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC) 7289 retval = I40E_ERR_ADMIN_QUEUE_ERROR; 7290 7291 return retval; 7292 } 7293 7294 *is_clear = true; 7295 *tx_counter = rd32(hw, I40E_PRTPM_TLPIC); 7296 *rx_counter = rd32(hw, I40E_PRTPM_RLPIC); 7297 7298 return I40E_SUCCESS; 7299 } 7300 7301 /** 7302 * i40e_get_lpi_duration - read LPI time duration from EEE statistics 7303 * @hw: pointer to the hw struct 7304 * @stat: pointer to structure with status of rx and tx lpi 7305 * @tx_duration: pointer to memory for TX LPI time duration 7306 * @rx_duration: pointer to memory for RX LPI time duration 7307 * 7308 * Read Low Power Idle (LPI) mode time duration from Energy Efficient 7309 * Ethernet (EEE) statistics. 7310 */ 7311 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw, 7312 struct i40e_hw_port_stats *stat, 7313 u64 *tx_duration, u64 *rx_duration) 7314 { 7315 u32 tx_time_dur, rx_time_dur; 7316 enum i40e_status_code retval; 7317 u32 cmd_status; 7318 7319 if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC && 7320 hw->device_id != I40E_DEV_ID_5G_BASE_T_BC) 7321 return I40E_ERR_NOT_IMPLEMENTED; 7322 7323 retval = i40e_aq_run_phy_activity 7324 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND, 7325 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR, 7326 &cmd_status, &tx_time_dur, &rx_time_dur, NULL); 7327 7328 if (retval) 7329 return retval; 7330 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) != 7331 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC) 7332 return I40E_ERR_ADMIN_QUEUE_ERROR; 7333 7334 if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB && 7335 !tx_time_dur && !rx_time_dur && 7336 stat->tx_lpi_status && stat->rx_lpi_status) { 7337 retval = i40e_aq_run_phy_activity 7338 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND, 7339 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR, 7340 &cmd_status, 7341 &tx_time_dur, &rx_time_dur, NULL); 7342 7343 if (retval) 7344 return retval; 7345 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) != 7346 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC) 7347 return I40E_ERR_ADMIN_QUEUE_ERROR; 7348 tx_time_dur = 0; 7349 rx_time_dur = 0; 7350 } 7351 7352 *tx_duration = tx_time_dur; 7353 *rx_duration = rx_time_dur; 7354 7355 return retval; 7356 } 7357 7358 /** 7359 * i40e_lpi_stat_update - update LPI counters with values relative to offset 7360 * @hw: pointer to the hw struct 7361 * @offset_loaded: flag indicating need of writing current value to offset 7362 * @tx_offset: pointer to offset of TX LPI counter 7363 * @tx_stat: pointer to value of TX LPI counter 7364 * @rx_offset: pointer to offset of RX LPI counter 7365 * @rx_stat: pointer to value of RX LPI counter 7366 * 7367 * Update Low Power Idle (LPI) mode counters while having regard to passed 7368 * offsets. 7369 **/ 7370 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw, 7371 bool offset_loaded, u64 *tx_offset, 7372 u64 *tx_stat, u64 *rx_offset, 7373 u64 *rx_stat) 7374 { 7375 enum i40e_status_code retval; 7376 u32 tx_counter, rx_counter; 7377 bool is_clear; 7378 7379 retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear); 7380 if (retval) 7381 goto err; 7382 7383 if (is_clear) { 7384 *tx_stat += tx_counter; 7385 *rx_stat += rx_counter; 7386 } else { 7387 if (!offset_loaded) { 7388 *tx_offset = tx_counter; 7389 *rx_offset = rx_counter; 7390 } 7391 7392 *tx_stat = (tx_counter >= *tx_offset) ? 7393 (u32)(tx_counter - *tx_offset) : 7394 (u32)((tx_counter + BIT_ULL(32)) - *tx_offset); 7395 *rx_stat = (rx_counter >= *rx_offset) ? 7396 (u32)(rx_counter - *rx_offset) : 7397 (u32)((rx_counter + BIT_ULL(32)) - *rx_offset); 7398 } 7399 err: 7400 return retval; 7401 } 7402 7403 /** 7404 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 7405 * @hw: pointer to the hw struct 7406 * @reg_addr: register address 7407 * @reg_val: ptr to register value 7408 * @cmd_details: pointer to command details structure or NULL 7409 * 7410 * Use the firmware to read the Rx control register, 7411 * especially useful if the Rx unit is under heavy pressure 7412 **/ 7413 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 7414 u32 reg_addr, u32 *reg_val, 7415 struct i40e_asq_cmd_details *cmd_details) 7416 { 7417 struct i40e_aq_desc desc; 7418 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 7419 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 7420 enum i40e_status_code status; 7421 7422 if (reg_val == NULL) 7423 return I40E_ERR_PARAM; 7424 7425 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 7426 7427 cmd_resp->address = CPU_TO_LE32(reg_addr); 7428 7429 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7430 7431 if (status == I40E_SUCCESS) 7432 *reg_val = LE32_TO_CPU(cmd_resp->value); 7433 7434 return status; 7435 } 7436 7437 /** 7438 * i40e_read_rx_ctl - read from an Rx control register 7439 * @hw: pointer to the hw struct 7440 * @reg_addr: register address 7441 **/ 7442 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 7443 { 7444 enum i40e_status_code status = I40E_SUCCESS; 7445 bool use_register; 7446 int retry = 5; 7447 u32 val = 0; 7448 7449 use_register = (((hw->aq.api_maj_ver == 1) && 7450 (hw->aq.api_min_ver < 5)) || 7451 (hw->mac.type == I40E_MAC_X722)); 7452 if (!use_register) { 7453 do_retry: 7454 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 7455 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 7456 i40e_msec_delay(1); 7457 retry--; 7458 goto do_retry; 7459 } 7460 } 7461 7462 /* if the AQ access failed, try the old-fashioned way */ 7463 if (status || use_register) 7464 val = rd32(hw, reg_addr); 7465 7466 return val; 7467 } 7468 7469 /** 7470 * i40e_aq_rx_ctl_write_register 7471 * @hw: pointer to the hw struct 7472 * @reg_addr: register address 7473 * @reg_val: register value 7474 * @cmd_details: pointer to command details structure or NULL 7475 * 7476 * Use the firmware to write to an Rx control register, 7477 * especially useful if the Rx unit is under heavy pressure 7478 **/ 7479 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 7480 u32 reg_addr, u32 reg_val, 7481 struct i40e_asq_cmd_details *cmd_details) 7482 { 7483 struct i40e_aq_desc desc; 7484 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 7485 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 7486 enum i40e_status_code status; 7487 7488 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 7489 7490 cmd->address = CPU_TO_LE32(reg_addr); 7491 cmd->value = CPU_TO_LE32(reg_val); 7492 7493 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7494 7495 return status; 7496 } 7497 7498 /** 7499 * i40e_write_rx_ctl - write to an Rx control register 7500 * @hw: pointer to the hw struct 7501 * @reg_addr: register address 7502 * @reg_val: register value 7503 **/ 7504 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 7505 { 7506 enum i40e_status_code status = I40E_SUCCESS; 7507 bool use_register; 7508 int retry = 5; 7509 7510 use_register = (((hw->aq.api_maj_ver == 1) && 7511 (hw->aq.api_min_ver < 5)) || 7512 (hw->mac.type == I40E_MAC_X722)); 7513 if (!use_register) { 7514 do_retry: 7515 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 7516 reg_val, NULL); 7517 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 7518 i40e_msec_delay(1); 7519 retry--; 7520 goto do_retry; 7521 } 7522 } 7523 7524 /* if the AQ access failed, try the old-fashioned way */ 7525 if (status || use_register) 7526 wr32(hw, reg_addr, reg_val); 7527 } 7528 7529 /** 7530 * i40e_mdio_if_number_selection - MDIO I/F number selection 7531 * @hw: pointer to the hw struct 7532 * @set_mdio: use MDIO I/F number specified by mdio_num 7533 * @mdio_num: MDIO I/F number 7534 * @cmd: pointer to PHY Register command structure 7535 **/ 7536 static void 7537 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num, 7538 struct i40e_aqc_phy_register_access *cmd) 7539 { 7540 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) { 7541 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED) 7542 cmd->cmd_flags |= 7543 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 7544 ((mdio_num << 7545 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) & 7546 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK); 7547 else 7548 i40e_debug(hw, I40E_DEBUG_PHY, 7549 "MDIO I/F number selection not supported by current FW version.\n"); 7550 } 7551 } 7552 7553 /** 7554 * i40e_aq_set_phy_register_ext 7555 * @hw: pointer to the hw struct 7556 * @phy_select: select which phy should be accessed 7557 * @dev_addr: PHY device address 7558 * @page_change: enable auto page change 7559 * @set_mdio: use MDIO I/F number specified by mdio_num 7560 * @mdio_num: MDIO I/F number 7561 * @reg_addr: PHY register address 7562 * @reg_val: new register value 7563 * @cmd_details: pointer to command details structure or NULL 7564 * 7565 * Write the external PHY register. 7566 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 7567 * may use simple wrapper i40e_aq_set_phy_register. 7568 **/ 7569 enum i40e_status_code 7570 i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 7571 u8 phy_select, u8 dev_addr, bool page_change, 7572 bool set_mdio, u8 mdio_num, 7573 u32 reg_addr, u32 reg_val, 7574 struct i40e_asq_cmd_details *cmd_details) 7575 { 7576 struct i40e_aq_desc desc; 7577 struct i40e_aqc_phy_register_access *cmd = 7578 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 7579 enum i40e_status_code status; 7580 7581 i40e_fill_default_direct_cmd_desc(&desc, 7582 i40e_aqc_opc_set_phy_register); 7583 7584 cmd->phy_interface = phy_select; 7585 cmd->dev_addres = dev_addr; 7586 cmd->reg_address = CPU_TO_LE32(reg_addr); 7587 cmd->reg_value = CPU_TO_LE32(reg_val); 7588 7589 if (!page_change) 7590 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 7591 7592 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 7593 7594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7595 7596 return status; 7597 } 7598 7599 /** 7600 * i40e_aq_get_phy_register_ext 7601 * @hw: pointer to the hw struct 7602 * @phy_select: select which phy should be accessed 7603 * @dev_addr: PHY device address 7604 * @page_change: enable auto page change 7605 * @set_mdio: use MDIO I/F number specified by mdio_num 7606 * @mdio_num: MDIO I/F number 7607 * @reg_addr: PHY register address 7608 * @reg_val: read register value 7609 * @cmd_details: pointer to command details structure or NULL 7610 * 7611 * Read the external PHY register. 7612 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 7613 * may use simple wrapper i40e_aq_get_phy_register. 7614 **/ 7615 enum i40e_status_code 7616 i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 7617 u8 phy_select, u8 dev_addr, bool page_change, 7618 bool set_mdio, u8 mdio_num, 7619 u32 reg_addr, u32 *reg_val, 7620 struct i40e_asq_cmd_details *cmd_details) 7621 { 7622 struct i40e_aq_desc desc; 7623 struct i40e_aqc_phy_register_access *cmd = 7624 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 7625 enum i40e_status_code status; 7626 7627 i40e_fill_default_direct_cmd_desc(&desc, 7628 i40e_aqc_opc_get_phy_register); 7629 7630 cmd->phy_interface = phy_select; 7631 cmd->dev_addres = dev_addr; 7632 cmd->reg_address = CPU_TO_LE32(reg_addr); 7633 7634 if (!page_change) 7635 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 7636 7637 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 7638 7639 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7640 if (!status) 7641 *reg_val = LE32_TO_CPU(cmd->reg_value); 7642 7643 return status; 7644 } 7645 7646 /** 7647 * i40e_aq_run_phy_activity 7648 * @hw: pointer to the hw struct 7649 * @activity_id: ID of DNL activity to run 7650 * @dnl_opcode: opcode passed to DNL script 7651 * @cmd_status: pointer to memory to write return value of DNL script 7652 * @data0: pointer to memory for first 4 bytes of data returned by DNL script 7653 * @data1: pointer to memory for last 4 bytes of data returned by DNL script 7654 * @cmd_details: pointer to command details structure or NULL 7655 * 7656 * Run DNL admin command. 7657 **/ 7658 enum i40e_status_code 7659 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode, 7660 u32 *cmd_status, u32 *data0, u32 *data1, 7661 struct i40e_asq_cmd_details *cmd_details) 7662 { 7663 struct i40e_aqc_run_phy_activity *cmd; 7664 enum i40e_status_code retval; 7665 struct i40e_aq_desc desc; 7666 7667 cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw; 7668 7669 if (!cmd_status || !data0 || !data1) { 7670 retval = I40E_ERR_PARAM; 7671 goto err; 7672 } 7673 7674 i40e_fill_default_direct_cmd_desc(&desc, 7675 i40e_aqc_opc_run_phy_activity); 7676 7677 cmd->activity_id = CPU_TO_LE16(activity_id); 7678 cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode); 7679 7680 retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7681 if (retval) 7682 goto err; 7683 7684 *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status); 7685 *data0 = LE32_TO_CPU(cmd->params.resp.data0); 7686 *data1 = LE32_TO_CPU(cmd->params.resp.data1); 7687 err: 7688 return retval; 7689 } 7690 7691 #ifdef VF_DRIVER 7692 7693 /** 7694 * i40e_aq_send_msg_to_pf 7695 * @hw: pointer to the hardware structure 7696 * @v_opcode: opcodes for VF-PF communication 7697 * @v_retval: return error code 7698 * @msg: pointer to the msg buffer 7699 * @msglen: msg length 7700 * @cmd_details: pointer to command details 7701 * 7702 * Send message to PF driver using admin queue. By default, this message 7703 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 7704 * completion before returning. 7705 **/ 7706 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 7707 enum virtchnl_ops v_opcode, 7708 enum i40e_status_code v_retval, 7709 u8 *msg, u16 msglen, 7710 struct i40e_asq_cmd_details *cmd_details) 7711 { 7712 struct i40e_aq_desc desc; 7713 struct i40e_asq_cmd_details details; 7714 enum i40e_status_code status; 7715 7716 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 7717 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 7718 desc.cookie_high = CPU_TO_LE32(v_opcode); 7719 desc.cookie_low = CPU_TO_LE32(v_retval); 7720 if (msglen) { 7721 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 7722 | I40E_AQ_FLAG_RD)); 7723 if (msglen > I40E_AQ_LARGE_BUF) 7724 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7725 desc.datalen = CPU_TO_LE16(msglen); 7726 } 7727 if (!cmd_details) { 7728 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 7729 details.async = true; 7730 cmd_details = &details; 7731 } 7732 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 7733 msglen, cmd_details); 7734 return status; 7735 } 7736 7737 /** 7738 * i40e_vf_parse_hw_config 7739 * @hw: pointer to the hardware structure 7740 * @msg: pointer to the virtual channel VF resource structure 7741 * 7742 * Given a VF resource message from the PF, populate the hw struct 7743 * with appropriate information. 7744 **/ 7745 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 7746 struct virtchnl_vf_resource *msg) 7747 { 7748 struct virtchnl_vsi_resource *vsi_res; 7749 int i; 7750 7751 vsi_res = &msg->vsi_res[0]; 7752 7753 hw->dev_caps.num_vsis = msg->num_vsis; 7754 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 7755 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 7756 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 7757 hw->dev_caps.dcb = msg->vf_cap_flags & 7758 VIRTCHNL_VF_OFFLOAD_L2; 7759 hw->dev_caps.iwarp = (msg->vf_cap_flags & 7760 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 7761 for (i = 0; i < msg->num_vsis; i++) { 7762 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) { 7763 i40e_memcpy(hw->mac.perm_addr, 7764 vsi_res->default_mac_addr, 7765 ETH_ALEN, 7766 I40E_NONDMA_TO_NONDMA); 7767 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 7768 ETH_ALEN, 7769 I40E_NONDMA_TO_NONDMA); 7770 } 7771 vsi_res++; 7772 } 7773 } 7774 7775 /** 7776 * i40e_vf_reset 7777 * @hw: pointer to the hardware structure 7778 * 7779 * Send a VF_RESET message to the PF. Does not wait for response from PF 7780 * as none will be forthcoming. Immediately after calling this function, 7781 * the admin queue should be shut down and (optionally) reinitialized. 7782 **/ 7783 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 7784 { 7785 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, 7786 I40E_SUCCESS, NULL, 0, NULL); 7787 } 7788 #endif /* VF_DRIVER */ 7789 7790 /** 7791 * i40e_aq_set_arp_proxy_config 7792 * @hw: pointer to the HW structure 7793 * @proxy_config: pointer to proxy config command table struct 7794 * @cmd_details: pointer to command details 7795 * 7796 * Set ARP offload parameters from pre-populated 7797 * i40e_aqc_arp_proxy_data struct 7798 **/ 7799 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 7800 struct i40e_aqc_arp_proxy_data *proxy_config, 7801 struct i40e_asq_cmd_details *cmd_details) 7802 { 7803 struct i40e_aq_desc desc; 7804 enum i40e_status_code status; 7805 7806 if (!proxy_config) 7807 return I40E_ERR_PARAM; 7808 7809 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 7810 7811 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7812 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7813 desc.params.external.addr_high = 7814 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config)); 7815 desc.params.external.addr_low = 7816 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config)); 7817 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data)); 7818 7819 status = i40e_asq_send_command(hw, &desc, proxy_config, 7820 sizeof(struct i40e_aqc_arp_proxy_data), 7821 cmd_details); 7822 7823 return status; 7824 } 7825 7826 /** 7827 * i40e_aq_set_ns_proxy_table_entry 7828 * @hw: pointer to the HW structure 7829 * @ns_proxy_table_entry: pointer to NS table entry command struct 7830 * @cmd_details: pointer to command details 7831 * 7832 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 7833 * from pre-populated i40e_aqc_ns_proxy_data struct 7834 **/ 7835 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 7836 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 7837 struct i40e_asq_cmd_details *cmd_details) 7838 { 7839 struct i40e_aq_desc desc; 7840 enum i40e_status_code status; 7841 7842 if (!ns_proxy_table_entry) 7843 return I40E_ERR_PARAM; 7844 7845 i40e_fill_default_direct_cmd_desc(&desc, 7846 i40e_aqc_opc_set_ns_proxy_table_entry); 7847 7848 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7849 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7850 desc.params.external.addr_high = 7851 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry)); 7852 desc.params.external.addr_low = 7853 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry)); 7854 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data)); 7855 7856 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 7857 sizeof(struct i40e_aqc_ns_proxy_data), 7858 cmd_details); 7859 7860 return status; 7861 } 7862 7863 /** 7864 * i40e_aq_set_clear_wol_filter 7865 * @hw: pointer to the hw struct 7866 * @filter_index: index of filter to modify (0-7) 7867 * @filter: buffer containing filter to be set 7868 * @set_filter: true to set filter, false to clear filter 7869 * @no_wol_tco: if true, pass through packets cannot cause wake-up 7870 * if false, pass through packets may cause wake-up 7871 * @filter_valid: true if filter action is valid 7872 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid 7873 * @cmd_details: pointer to command details structure or NULL 7874 * 7875 * Set or clear WoL filter for port attached to the PF 7876 **/ 7877 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 7878 u8 filter_index, 7879 struct i40e_aqc_set_wol_filter_data *filter, 7880 bool set_filter, bool no_wol_tco, 7881 bool filter_valid, bool no_wol_tco_valid, 7882 struct i40e_asq_cmd_details *cmd_details) 7883 { 7884 struct i40e_aq_desc desc; 7885 struct i40e_aqc_set_wol_filter *cmd = 7886 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 7887 enum i40e_status_code status; 7888 u16 cmd_flags = 0; 7889 u16 valid_flags = 0; 7890 u16 buff_len = 0; 7891 7892 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 7893 7894 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 7895 return I40E_ERR_PARAM; 7896 cmd->filter_index = CPU_TO_LE16(filter_index); 7897 7898 if (set_filter) { 7899 if (!filter) 7900 return I40E_ERR_PARAM; 7901 7902 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 7903 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR; 7904 } 7905 7906 if (no_wol_tco) 7907 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 7908 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 7909 7910 if (filter_valid) 7911 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 7912 if (no_wol_tco_valid) 7913 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 7914 cmd->valid_flags = CPU_TO_LE16(valid_flags); 7915 7916 buff_len = sizeof(*filter); 7917 desc.datalen = CPU_TO_LE16(buff_len); 7918 7919 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7920 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7921 7922 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter)); 7923 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter)); 7924 7925 status = i40e_asq_send_command(hw, &desc, filter, 7926 buff_len, cmd_details); 7927 7928 return status; 7929 } 7930 7931 /** 7932 * i40e_aq_get_wake_event_reason 7933 * @hw: pointer to the hw struct 7934 * @wake_reason: return value, index of matching filter 7935 * @cmd_details: pointer to command details structure or NULL 7936 * 7937 * Get information for the reason of a Wake Up event 7938 **/ 7939 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 7940 u16 *wake_reason, 7941 struct i40e_asq_cmd_details *cmd_details) 7942 { 7943 struct i40e_aq_desc desc; 7944 struct i40e_aqc_get_wake_reason_completion *resp = 7945 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 7946 enum i40e_status_code status; 7947 7948 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 7949 7950 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7951 7952 if (status == I40E_SUCCESS) 7953 *wake_reason = LE16_TO_CPU(resp->wake_reason); 7954 7955 return status; 7956 } 7957 7958 /** 7959 * i40e_aq_clear_all_wol_filters 7960 * @hw: pointer to the hw struct 7961 * @cmd_details: pointer to command details structure or NULL 7962 * 7963 * Get information for the reason of a Wake Up event 7964 **/ 7965 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw, 7966 struct i40e_asq_cmd_details *cmd_details) 7967 { 7968 struct i40e_aq_desc desc; 7969 enum i40e_status_code status; 7970 7971 i40e_fill_default_direct_cmd_desc(&desc, 7972 i40e_aqc_opc_clear_all_wol_filters); 7973 7974 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7975 7976 return status; 7977 } 7978 7979 /** 7980 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 7981 * @hw: pointer to the hw struct 7982 * @buff: command buffer (size in bytes = buff_size) 7983 * @buff_size: buffer size in bytes 7984 * @track_id: package tracking id 7985 * @error_offset: returns error offset 7986 * @error_info: returns error information 7987 * @cmd_details: pointer to command details structure or NULL 7988 **/ 7989 enum 7990 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 7991 u16 buff_size, u32 track_id, 7992 u32 *error_offset, u32 *error_info, 7993 struct i40e_asq_cmd_details *cmd_details) 7994 { 7995 struct i40e_aq_desc desc; 7996 struct i40e_aqc_write_personalization_profile *cmd = 7997 (struct i40e_aqc_write_personalization_profile *) 7998 &desc.params.raw; 7999 struct i40e_aqc_write_ddp_resp *resp; 8000 enum i40e_status_code status; 8001 8002 i40e_fill_default_direct_cmd_desc(&desc, 8003 i40e_aqc_opc_write_personalization_profile); 8004 8005 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 8006 if (buff_size > I40E_AQ_LARGE_BUF) 8007 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 8008 8009 desc.datalen = CPU_TO_LE16(buff_size); 8010 8011 cmd->profile_track_id = CPU_TO_LE32(track_id); 8012 8013 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 8014 if (!status) { 8015 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 8016 if (error_offset) 8017 *error_offset = LE32_TO_CPU(resp->error_offset); 8018 if (error_info) 8019 *error_info = LE32_TO_CPU(resp->error_info); 8020 } 8021 8022 return status; 8023 } 8024 8025 /** 8026 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 8027 * @hw: pointer to the hw struct 8028 * @buff: command buffer (size in bytes = buff_size) 8029 * @buff_size: buffer size in bytes 8030 * @flags: AdminQ command flags 8031 * @cmd_details: pointer to command details structure or NULL 8032 **/ 8033 enum 8034 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 8035 u16 buff_size, u8 flags, 8036 struct i40e_asq_cmd_details *cmd_details) 8037 { 8038 struct i40e_aq_desc desc; 8039 struct i40e_aqc_get_applied_profiles *cmd = 8040 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 8041 enum i40e_status_code status; 8042 8043 i40e_fill_default_direct_cmd_desc(&desc, 8044 i40e_aqc_opc_get_personalization_profile_list); 8045 8046 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 8047 if (buff_size > I40E_AQ_LARGE_BUF) 8048 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 8049 desc.datalen = CPU_TO_LE16(buff_size); 8050 8051 cmd->flags = flags; 8052 8053 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 8054 8055 return status; 8056 } 8057 8058 /** 8059 * i40e_find_segment_in_package 8060 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 8061 * @pkg_hdr: pointer to the package header to be searched 8062 * 8063 * This function searches a package file for a particular segment type. On 8064 * success it returns a pointer to the segment header, otherwise it will 8065 * return NULL. 8066 **/ 8067 struct i40e_generic_seg_header * 8068 i40e_find_segment_in_package(u32 segment_type, 8069 struct i40e_package_header *pkg_hdr) 8070 { 8071 struct i40e_generic_seg_header *segment; 8072 u32 i; 8073 8074 /* Search all package segments for the requested segment type */ 8075 for (i = 0; i < pkg_hdr->segment_count; i++) { 8076 segment = 8077 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 8078 pkg_hdr->segment_offset[i]); 8079 8080 if (segment->type == segment_type) 8081 return segment; 8082 } 8083 8084 return NULL; 8085 } 8086 8087 /* Get section table in profile */ 8088 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 8089 do { \ 8090 struct i40e_profile_segment *p = (profile); \ 8091 u32 count; \ 8092 u32 *nvm; \ 8093 count = p->device_table_count; \ 8094 nvm = (u32 *)&p->device_table[count]; \ 8095 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 8096 } while (0) 8097 8098 /* Get section header in profile */ 8099 #define I40E_SECTION_HEADER(profile, offset) \ 8100 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 8101 8102 /** 8103 * i40e_find_section_in_profile 8104 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE) 8105 * @profile: pointer to the i40e segment header to be searched 8106 * 8107 * This function searches i40e segment for a particular section type. On 8108 * success it returns a pointer to the section header, otherwise it will 8109 * return NULL. 8110 **/ 8111 struct i40e_profile_section_header * 8112 i40e_find_section_in_profile(u32 section_type, 8113 struct i40e_profile_segment *profile) 8114 { 8115 struct i40e_profile_section_header *sec; 8116 struct i40e_section_table *sec_tbl; 8117 u32 sec_off; 8118 u32 i; 8119 8120 if (profile->header.type != SEGMENT_TYPE_I40E) 8121 return NULL; 8122 8123 I40E_SECTION_TABLE(profile, sec_tbl); 8124 8125 for (i = 0; i < sec_tbl->section_count; i++) { 8126 sec_off = sec_tbl->section_offset[i]; 8127 sec = I40E_SECTION_HEADER(profile, sec_off); 8128 if (sec->section.type == section_type) 8129 return sec; 8130 } 8131 8132 return NULL; 8133 } 8134 8135 /** 8136 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 8137 * @hw: pointer to the hw struct 8138 * @aq: command buffer containing all data to execute AQ 8139 **/ 8140 STATIC enum 8141 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw, 8142 struct i40e_profile_aq_section *aq) 8143 { 8144 enum i40e_status_code status; 8145 struct i40e_aq_desc desc; 8146 u8 *msg = NULL; 8147 u16 msglen; 8148 8149 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 8150 desc.flags |= CPU_TO_LE16(aq->flags); 8151 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw), 8152 I40E_NONDMA_TO_NONDMA); 8153 8154 msglen = aq->datalen; 8155 if (msglen) { 8156 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 8157 I40E_AQ_FLAG_RD)); 8158 if (msglen > I40E_AQ_LARGE_BUF) 8159 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 8160 desc.datalen = CPU_TO_LE16(msglen); 8161 msg = &aq->data[0]; 8162 } 8163 8164 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 8165 8166 if (status != I40E_SUCCESS) { 8167 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8168 "unable to exec DDP AQ opcode %u, error %d\n", 8169 aq->opcode, status); 8170 return status; 8171 } 8172 8173 /* copy returned desc to aq_buf */ 8174 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw), 8175 I40E_NONDMA_TO_NONDMA); 8176 8177 return I40E_SUCCESS; 8178 } 8179 8180 /** 8181 * i40e_validate_profile 8182 * @hw: pointer to the hardware structure 8183 * @profile: pointer to the profile segment of the package to be validated 8184 * @track_id: package tracking id 8185 * @rollback: flag if the profile is for rollback. 8186 * 8187 * Validates supported devices and profile's sections. 8188 */ 8189 STATIC enum i40e_status_code 8190 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 8191 u32 track_id, bool rollback) 8192 { 8193 struct i40e_profile_section_header *sec = NULL; 8194 enum i40e_status_code status = I40E_SUCCESS; 8195 struct i40e_section_table *sec_tbl; 8196 u32 vendor_dev_id; 8197 u32 dev_cnt; 8198 u32 sec_off; 8199 u32 i; 8200 8201 if (track_id == I40E_DDP_TRACKID_INVALID) { 8202 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 8203 return I40E_NOT_SUPPORTED; 8204 } 8205 8206 dev_cnt = profile->device_table_count; 8207 for (i = 0; i < dev_cnt; i++) { 8208 vendor_dev_id = profile->device_table[i].vendor_dev_id; 8209 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID && 8210 hw->device_id == (vendor_dev_id & 0xFFFF)) 8211 break; 8212 } 8213 if (dev_cnt && (i == dev_cnt)) { 8214 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8215 "Device doesn't support DDP\n"); 8216 return I40E_ERR_DEVICE_NOT_SUPPORTED; 8217 } 8218 8219 I40E_SECTION_TABLE(profile, sec_tbl); 8220 8221 /* Validate sections types */ 8222 for (i = 0; i < sec_tbl->section_count; i++) { 8223 sec_off = sec_tbl->section_offset[i]; 8224 sec = I40E_SECTION_HEADER(profile, sec_off); 8225 if (rollback) { 8226 if (sec->section.type == SECTION_TYPE_MMIO || 8227 sec->section.type == SECTION_TYPE_AQ || 8228 sec->section.type == SECTION_TYPE_RB_AQ) { 8229 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8230 "Not a roll-back package\n"); 8231 return I40E_NOT_SUPPORTED; 8232 } 8233 } else { 8234 if (sec->section.type == SECTION_TYPE_RB_AQ || 8235 sec->section.type == SECTION_TYPE_RB_MMIO) { 8236 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8237 "Not an original package\n"); 8238 return I40E_NOT_SUPPORTED; 8239 } 8240 } 8241 } 8242 8243 return status; 8244 } 8245 8246 /** 8247 * i40e_write_profile 8248 * @hw: pointer to the hardware structure 8249 * @profile: pointer to the profile segment of the package to be downloaded 8250 * @track_id: package tracking id 8251 * 8252 * Handles the download of a complete package. 8253 */ 8254 enum i40e_status_code 8255 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 8256 u32 track_id) 8257 { 8258 enum i40e_status_code status = I40E_SUCCESS; 8259 struct i40e_section_table *sec_tbl; 8260 struct i40e_profile_section_header *sec = NULL; 8261 struct i40e_profile_aq_section *ddp_aq; 8262 u32 section_size = 0; 8263 u32 offset = 0, info = 0; 8264 u32 sec_off; 8265 u32 i; 8266 8267 status = i40e_validate_profile(hw, profile, track_id, false); 8268 if (status) 8269 return status; 8270 8271 I40E_SECTION_TABLE(profile, sec_tbl); 8272 8273 for (i = 0; i < sec_tbl->section_count; i++) { 8274 sec_off = sec_tbl->section_offset[i]; 8275 sec = I40E_SECTION_HEADER(profile, sec_off); 8276 /* Process generic admin command */ 8277 if (sec->section.type == SECTION_TYPE_AQ) { 8278 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 8279 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 8280 if (status) { 8281 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8282 "Failed to execute aq: section %d, opcode %u\n", 8283 i, ddp_aq->opcode); 8284 break; 8285 } 8286 sec->section.type = SECTION_TYPE_RB_AQ; 8287 } 8288 8289 /* Skip any non-mmio sections */ 8290 if (sec->section.type != SECTION_TYPE_MMIO) 8291 continue; 8292 8293 section_size = sec->section.size + 8294 sizeof(struct i40e_profile_section_header); 8295 8296 /* Write MMIO section */ 8297 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 8298 track_id, &offset, &info, NULL); 8299 if (status) { 8300 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8301 "Failed to write profile: section %d, offset %d, info %d\n", 8302 i, offset, info); 8303 break; 8304 } 8305 } 8306 return status; 8307 } 8308 8309 /** 8310 * i40e_rollback_profile 8311 * @hw: pointer to the hardware structure 8312 * @profile: pointer to the profile segment of the package to be removed 8313 * @track_id: package tracking id 8314 * 8315 * Rolls back previously loaded package. 8316 */ 8317 enum i40e_status_code 8318 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 8319 u32 track_id) 8320 { 8321 struct i40e_profile_section_header *sec = NULL; 8322 enum i40e_status_code status = I40E_SUCCESS; 8323 struct i40e_section_table *sec_tbl; 8324 u32 offset = 0, info = 0; 8325 u32 section_size = 0; 8326 u32 sec_off; 8327 int i; 8328 8329 status = i40e_validate_profile(hw, profile, track_id, true); 8330 if (status) 8331 return status; 8332 8333 I40E_SECTION_TABLE(profile, sec_tbl); 8334 8335 /* For rollback write sections in reverse */ 8336 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 8337 sec_off = sec_tbl->section_offset[i]; 8338 sec = I40E_SECTION_HEADER(profile, sec_off); 8339 8340 /* Skip any non-rollback sections */ 8341 if (sec->section.type != SECTION_TYPE_RB_MMIO) 8342 continue; 8343 8344 section_size = sec->section.size + 8345 sizeof(struct i40e_profile_section_header); 8346 8347 /* Write roll-back MMIO section */ 8348 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 8349 track_id, &offset, &info, NULL); 8350 if (status) { 8351 i40e_debug(hw, I40E_DEBUG_PACKAGE, 8352 "Failed to write profile: section %d, offset %d, info %d\n", 8353 i, offset, info); 8354 break; 8355 } 8356 } 8357 return status; 8358 } 8359 8360 /** 8361 * i40e_add_pinfo_to_list 8362 * @hw: pointer to the hardware structure 8363 * @profile: pointer to the profile segment of the package 8364 * @profile_info_sec: buffer for information section 8365 * @track_id: package tracking id 8366 * 8367 * Register a profile to the list of loaded profiles. 8368 */ 8369 enum i40e_status_code 8370 i40e_add_pinfo_to_list(struct i40e_hw *hw, 8371 struct i40e_profile_segment *profile, 8372 u8 *profile_info_sec, u32 track_id) 8373 { 8374 enum i40e_status_code status = I40E_SUCCESS; 8375 struct i40e_profile_section_header *sec = NULL; 8376 struct i40e_profile_info *pinfo; 8377 u32 offset = 0, info = 0; 8378 8379 sec = (struct i40e_profile_section_header *)profile_info_sec; 8380 sec->tbl_size = 1; 8381 sec->data_end = sizeof(struct i40e_profile_section_header) + 8382 sizeof(struct i40e_profile_info); 8383 sec->section.type = SECTION_TYPE_INFO; 8384 sec->section.offset = sizeof(struct i40e_profile_section_header); 8385 sec->section.size = sizeof(struct i40e_profile_info); 8386 pinfo = (struct i40e_profile_info *)(profile_info_sec + 8387 sec->section.offset); 8388 pinfo->track_id = track_id; 8389 pinfo->version = profile->version; 8390 pinfo->op = I40E_DDP_ADD_TRACKID; 8391 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE, 8392 I40E_NONDMA_TO_NONDMA); 8393 8394 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 8395 track_id, &offset, &info, NULL); 8396 return status; 8397 } 8398