1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <linux/pci_regs.h> 6 #include <rte_alarm.h> 7 #include <ethdev_pci.h> 8 #include <rte_io.h> 9 #include <rte_pci.h> 10 #include <rte_vfio.h> 11 12 #include "hns3_ethdev.h" 13 #include "hns3_logs.h" 14 #include "hns3_rxtx.h" 15 #include "hns3_regs.h" 16 #include "hns3_intr.h" 17 #include "hns3_dcb.h" 18 #include "hns3_mp.h" 19 20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */ 21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */ 22 23 #define HNS3VF_RESET_WAIT_MS 20 24 #define HNS3VF_RESET_WAIT_CNT 2000 25 26 /* Reset related Registers */ 27 #define HNS3_GLOBAL_RESET_BIT 0 28 #define HNS3_CORE_RESET_BIT 1 29 #define HNS3_IMP_RESET_BIT 2 30 #define HNS3_FUN_RST_ING_B 0 31 32 enum hns3vf_evt_cause { 33 HNS3VF_VECTOR0_EVENT_RST, 34 HNS3VF_VECTOR0_EVENT_MBX, 35 HNS3VF_VECTOR0_EVENT_OTHER, 36 }; 37 38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw, 39 uint64_t *levels); 40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev); 42 43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 44 struct rte_ether_addr *mac_addr); 45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 46 struct rte_ether_addr *mac_addr); 47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, 48 __rte_unused int wait_to_complete); 49 50 /* set PCI bus mastering */ 51 static int 52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) 53 { 54 uint16_t reg; 55 int ret; 56 57 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); 58 if (ret < 0) { 59 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 60 PCI_COMMAND); 61 return ret; 62 } 63 64 if (op) 65 /* set the master bit */ 66 reg |= PCI_COMMAND_MASTER; 67 else 68 reg &= ~(PCI_COMMAND_MASTER); 69 70 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); 71 } 72 73 /** 74 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list 75 * @cap: the capability 76 * 77 * Return the address of the given capability within the PCI capability list. 78 */ 79 static int 80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) 81 { 82 #define MAX_PCIE_CAPABILITY 48 83 uint16_t status; 84 uint8_t pos; 85 uint8_t id; 86 int ttl; 87 int ret; 88 89 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); 90 if (ret < 0) { 91 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS); 92 return 0; 93 } 94 95 if (!(status & PCI_STATUS_CAP_LIST)) 96 return 0; 97 98 ttl = MAX_PCIE_CAPABILITY; 99 ret = rte_pci_read_config(device, &pos, sizeof(pos), 100 PCI_CAPABILITY_LIST); 101 if (ret < 0) { 102 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 103 PCI_CAPABILITY_LIST); 104 return 0; 105 } 106 107 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { 108 ret = rte_pci_read_config(device, &id, sizeof(id), 109 (pos + PCI_CAP_LIST_ID)); 110 if (ret < 0) { 111 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 112 (pos + PCI_CAP_LIST_ID)); 113 break; 114 } 115 116 if (id == 0xFF) 117 break; 118 119 if (id == cap) 120 return (int)pos; 121 122 ret = rte_pci_read_config(device, &pos, sizeof(pos), 123 (pos + PCI_CAP_LIST_NEXT)); 124 if (ret < 0) { 125 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 126 (pos + PCI_CAP_LIST_NEXT)); 127 break; 128 } 129 } 130 return 0; 131 } 132 133 static int 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op) 135 { 136 uint16_t control; 137 int pos; 138 int ret; 139 140 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); 141 if (pos) { 142 ret = rte_pci_read_config(device, &control, sizeof(control), 143 (pos + PCI_MSIX_FLAGS)); 144 if (ret < 0) { 145 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 146 (pos + PCI_MSIX_FLAGS)); 147 return -ENXIO; 148 } 149 150 if (op) 151 control |= PCI_MSIX_FLAGS_ENABLE; 152 else 153 control &= ~PCI_MSIX_FLAGS_ENABLE; 154 ret = rte_pci_write_config(device, &control, sizeof(control), 155 (pos + PCI_MSIX_FLAGS)); 156 if (ret < 0) { 157 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x", 158 (pos + PCI_MSIX_FLAGS)); 159 } 160 return 0; 161 } 162 return -ENXIO; 163 } 164 165 static int 166 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 167 { 168 /* mac address was checked by upper level interface */ 169 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 170 int ret; 171 172 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 173 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes, 174 RTE_ETHER_ADDR_LEN, false, NULL, 0); 175 if (ret) { 176 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 177 mac_addr); 178 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 179 mac_str, ret); 180 } 181 return ret; 182 } 183 184 static int 185 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 186 { 187 /* mac address was checked by upper level interface */ 188 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 189 int ret; 190 191 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 192 HNS3_MBX_MAC_VLAN_UC_REMOVE, 193 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, 194 false, NULL, 0); 195 if (ret) { 196 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 197 mac_addr); 198 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 199 mac_str, ret); 200 } 201 return ret; 202 } 203 204 static int 205 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 206 { 207 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 208 struct rte_ether_addr *addr; 209 int ret; 210 int i; 211 212 for (i = 0; i < hw->mc_addrs_num; i++) { 213 addr = &hw->mc_addrs[i]; 214 /* Check if there are duplicate addresses */ 215 if (rte_is_same_ether_addr(addr, mac_addr)) { 216 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 217 addr); 218 hns3_err(hw, "failed to add mc mac addr, same addrs" 219 "(%s) is added by the set_mc_mac_addr_list " 220 "API", mac_str); 221 return -EINVAL; 222 } 223 } 224 225 ret = hns3vf_add_mc_mac_addr(hw, mac_addr); 226 if (ret) { 227 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 228 mac_addr); 229 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 230 mac_str, ret); 231 } 232 return ret; 233 } 234 235 static int 236 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 237 __rte_unused uint32_t idx, 238 __rte_unused uint32_t pool) 239 { 240 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 241 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 242 int ret; 243 244 rte_spinlock_lock(&hw->lock); 245 246 /* 247 * In hns3 network engine adding UC and MC mac address with different 248 * commands with firmware. We need to determine whether the input 249 * address is a UC or a MC address to call different commands. 250 * By the way, it is recommended calling the API function named 251 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 252 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 253 * may affect the specifications of UC mac addresses. 254 */ 255 if (rte_is_multicast_ether_addr(mac_addr)) 256 ret = hns3vf_add_mc_addr_common(hw, mac_addr); 257 else 258 ret = hns3vf_add_uc_mac_addr(hw, mac_addr); 259 260 rte_spinlock_unlock(&hw->lock); 261 if (ret) { 262 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 263 mac_addr); 264 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 265 ret); 266 } 267 268 return ret; 269 } 270 271 static void 272 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 273 { 274 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 275 /* index will be checked by upper level rte interface */ 276 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 277 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 278 int ret; 279 280 rte_spinlock_lock(&hw->lock); 281 282 if (rte_is_multicast_ether_addr(mac_addr)) 283 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr); 284 else 285 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr); 286 287 rte_spinlock_unlock(&hw->lock); 288 if (ret) { 289 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 290 mac_addr); 291 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", 292 mac_str, ret); 293 } 294 } 295 296 static int 297 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev, 298 struct rte_ether_addr *mac_addr) 299 { 300 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2) 301 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 302 struct rte_ether_addr *old_addr; 303 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */ 304 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 305 int ret; 306 307 /* 308 * It has been guaranteed that input parameter named mac_addr is valid 309 * address in the rte layer of DPDK framework. 310 */ 311 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 312 rte_spinlock_lock(&hw->lock); 313 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN); 314 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes, 315 RTE_ETHER_ADDR_LEN); 316 317 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 318 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes, 319 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0); 320 if (ret) { 321 /* 322 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev 323 * driver. When user has configured a MAC address for VF device 324 * by "ip link set ..." command based on the PF device, the hns3 325 * PF kernel ethdev driver does not allow VF driver to request 326 * reconfiguring a different default MAC address, and return 327 * -EPREM to VF driver through mailbox. 328 */ 329 if (ret == -EPERM) { 330 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 331 old_addr); 332 hns3_warn(hw, "Has permanet mac addr(%s) for vf", 333 mac_str); 334 } else { 335 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 336 mac_addr); 337 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", 338 mac_str, ret); 339 } 340 } 341 342 rte_ether_addr_copy(mac_addr, 343 (struct rte_ether_addr *)hw->mac.mac_addr); 344 rte_spinlock_unlock(&hw->lock); 345 346 return ret; 347 } 348 349 static int 350 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del) 351 { 352 struct hns3_hw *hw = &hns->hw; 353 struct rte_ether_addr *addr; 354 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 355 int err = 0; 356 int ret; 357 int i; 358 359 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) { 360 addr = &hw->data->mac_addrs[i]; 361 if (rte_is_zero_ether_addr(addr)) 362 continue; 363 if (rte_is_multicast_ether_addr(addr)) 364 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) : 365 hns3vf_add_mc_mac_addr(hw, addr); 366 else 367 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) : 368 hns3vf_add_uc_mac_addr(hw, addr); 369 370 if (ret) { 371 err = ret; 372 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 373 addr); 374 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 375 "ret = %d.", del ? "remove" : "restore", 376 mac_str, i, ret); 377 } 378 } 379 return err; 380 } 381 382 static int 383 hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 384 struct rte_ether_addr *mac_addr) 385 { 386 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 387 int ret; 388 389 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 390 HNS3_MBX_MAC_VLAN_MC_ADD, 391 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 392 NULL, 0); 393 if (ret) { 394 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 395 mac_addr); 396 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d", 397 mac_str, ret); 398 } 399 400 return ret; 401 } 402 403 static int 404 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 405 struct rte_ether_addr *mac_addr) 406 { 407 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 408 int ret; 409 410 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 411 HNS3_MBX_MAC_VLAN_MC_REMOVE, 412 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 413 NULL, 0); 414 if (ret) { 415 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 416 mac_addr); 417 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d", 418 mac_str, ret); 419 } 420 421 return ret; 422 } 423 424 static int 425 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw, 426 struct rte_ether_addr *mc_addr_set, 427 uint32_t nb_mc_addr) 428 { 429 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 430 struct rte_ether_addr *addr; 431 uint32_t i; 432 uint32_t j; 433 434 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 435 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 436 "invalid. valid range: 0~%d", 437 nb_mc_addr, HNS3_MC_MACADDR_NUM); 438 return -EINVAL; 439 } 440 441 /* Check if input mac addresses are valid */ 442 for (i = 0; i < nb_mc_addr; i++) { 443 addr = &mc_addr_set[i]; 444 if (!rte_is_multicast_ether_addr(addr)) { 445 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 446 addr); 447 hns3_err(hw, 448 "failed to set mc mac addr, addr(%s) invalid.", 449 mac_str); 450 return -EINVAL; 451 } 452 453 /* Check if there are duplicate addresses */ 454 for (j = i + 1; j < nb_mc_addr; j++) { 455 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 456 hns3_ether_format_addr(mac_str, 457 RTE_ETHER_ADDR_FMT_SIZE, 458 addr); 459 hns3_err(hw, "failed to set mc mac addr, " 460 "addrs invalid. two same addrs(%s).", 461 mac_str); 462 return -EINVAL; 463 } 464 } 465 466 /* 467 * Check if there are duplicate addresses between mac_addrs 468 * and mc_addr_set 469 */ 470 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) { 471 if (rte_is_same_ether_addr(addr, 472 &hw->data->mac_addrs[j])) { 473 hns3_ether_format_addr(mac_str, 474 RTE_ETHER_ADDR_FMT_SIZE, 475 addr); 476 hns3_err(hw, "failed to set mc mac addr, " 477 "addrs invalid. addrs(%s) has already " 478 "configured in mac_addr add API", 479 mac_str); 480 return -EINVAL; 481 } 482 } 483 } 484 485 return 0; 486 } 487 488 static int 489 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev, 490 struct rte_ether_addr *mc_addr_set, 491 uint32_t nb_mc_addr) 492 { 493 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 494 struct rte_ether_addr *addr; 495 int cur_addr_num; 496 int set_addr_num; 497 int num; 498 int ret; 499 int i; 500 501 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 502 if (ret) 503 return ret; 504 505 rte_spinlock_lock(&hw->lock); 506 cur_addr_num = hw->mc_addrs_num; 507 for (i = 0; i < cur_addr_num; i++) { 508 num = cur_addr_num - i - 1; 509 addr = &hw->mc_addrs[num]; 510 ret = hns3vf_remove_mc_mac_addr(hw, addr); 511 if (ret) { 512 rte_spinlock_unlock(&hw->lock); 513 return ret; 514 } 515 516 hw->mc_addrs_num--; 517 } 518 519 set_addr_num = (int)nb_mc_addr; 520 for (i = 0; i < set_addr_num; i++) { 521 addr = &mc_addr_set[i]; 522 ret = hns3vf_add_mc_mac_addr(hw, addr); 523 if (ret) { 524 rte_spinlock_unlock(&hw->lock); 525 return ret; 526 } 527 528 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]); 529 hw->mc_addrs_num++; 530 } 531 rte_spinlock_unlock(&hw->lock); 532 533 return 0; 534 } 535 536 static int 537 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 538 { 539 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 540 struct hns3_hw *hw = &hns->hw; 541 struct rte_ether_addr *addr; 542 int err = 0; 543 int ret; 544 int i; 545 546 for (i = 0; i < hw->mc_addrs_num; i++) { 547 addr = &hw->mc_addrs[i]; 548 if (!rte_is_multicast_ether_addr(addr)) 549 continue; 550 if (del) 551 ret = hns3vf_remove_mc_mac_addr(hw, addr); 552 else 553 ret = hns3vf_add_mc_mac_addr(hw, addr); 554 if (ret) { 555 err = ret; 556 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 557 addr); 558 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d", 559 del ? "Remove" : "Restore", mac_str, ret); 560 } 561 } 562 return err; 563 } 564 565 static int 566 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc, 567 bool en_uc_pmc, bool en_mc_pmc) 568 { 569 struct hns3_mbx_vf_to_pf_cmd *req; 570 struct hns3_cmd_desc desc; 571 int ret; 572 573 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data; 574 575 /* 576 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver, 577 * so there are some features for promiscuous/allmulticast mode in hns3 578 * VF PMD driver as below: 579 * 1. The promiscuous/allmulticast mode can be configured successfully 580 * only based on the trusted VF device. If based on the non trusted 581 * VF device, configuring promiscuous/allmulticast mode will fail. 582 * The hns3 VF device can be confiruged as trusted device by hns3 PF 583 * kernel ethdev driver on the host by the following command: 584 * "ip link set <eth num> vf <vf id> turst on" 585 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD 586 * driver can receive the ingress and outgoing traffic. In the words, 587 * all the ingress packets, all the packets sent from the PF and 588 * other VFs on the same physical port. 589 * 3. Note: Because of the hardware constraints, By default vlan filter 590 * is enabled and couldn't be turned off based on VF device, so vlan 591 * filter is still effective even in promiscuous mode. If upper 592 * applications don't call rte_eth_dev_vlan_filter API function to 593 * set vlan based on VF device, hns3 VF PMD driver will can't receive 594 * the packets with vlan tag in promiscuoue mode. 595 */ 596 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false); 597 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE; 598 req->msg[1] = en_bc_pmc ? 1 : 0; 599 req->msg[2] = en_uc_pmc ? 1 : 0; 600 req->msg[3] = en_mc_pmc ? 1 : 0; 601 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0; 602 603 ret = hns3_cmd_send(hw, &desc, 1); 604 if (ret) 605 hns3_err(hw, "Set promisc mode fail, ret = %d", ret); 606 607 return ret; 608 } 609 610 static int 611 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev) 612 { 613 struct hns3_adapter *hns = dev->data->dev_private; 614 struct hns3_hw *hw = &hns->hw; 615 int ret; 616 617 ret = hns3vf_set_promisc_mode(hw, true, true, true); 618 if (ret) 619 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d", 620 ret); 621 return ret; 622 } 623 624 static int 625 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev) 626 { 627 bool allmulti = dev->data->all_multicast ? true : false; 628 struct hns3_adapter *hns = dev->data->dev_private; 629 struct hns3_hw *hw = &hns->hw; 630 int ret; 631 632 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti); 633 if (ret) 634 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d", 635 ret); 636 return ret; 637 } 638 639 static int 640 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev) 641 { 642 struct hns3_adapter *hns = dev->data->dev_private; 643 struct hns3_hw *hw = &hns->hw; 644 int ret; 645 646 if (dev->data->promiscuous) 647 return 0; 648 649 ret = hns3vf_set_promisc_mode(hw, true, false, true); 650 if (ret) 651 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d", 652 ret); 653 return ret; 654 } 655 656 static int 657 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev) 658 { 659 struct hns3_adapter *hns = dev->data->dev_private; 660 struct hns3_hw *hw = &hns->hw; 661 int ret; 662 663 if (dev->data->promiscuous) 664 return 0; 665 666 ret = hns3vf_set_promisc_mode(hw, true, false, false); 667 if (ret) 668 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d", 669 ret); 670 return ret; 671 } 672 673 static int 674 hns3vf_restore_promisc(struct hns3_adapter *hns) 675 { 676 struct hns3_hw *hw = &hns->hw; 677 bool allmulti = hw->data->all_multicast ? true : false; 678 679 if (hw->data->promiscuous) 680 return hns3vf_set_promisc_mode(hw, true, true, true); 681 682 return hns3vf_set_promisc_mode(hw, true, false, allmulti); 683 } 684 685 static int 686 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, 687 bool mmap, enum hns3_ring_type queue_type, 688 uint16_t queue_id) 689 { 690 struct hns3_vf_bind_vector_msg bind_msg; 691 const char *op_str; 692 uint16_t code; 693 int ret; 694 695 memset(&bind_msg, 0, sizeof(bind_msg)); 696 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR : 697 HNS3_MBX_UNMAP_RING_TO_VECTOR; 698 bind_msg.vector_id = vector_id; 699 700 if (queue_type == HNS3_RING_TYPE_RX) 701 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX; 702 else 703 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX; 704 705 bind_msg.param[0].ring_type = queue_type; 706 bind_msg.ring_num = 1; 707 bind_msg.param[0].tqp_index = queue_id; 708 op_str = mmap ? "Map" : "Unmap"; 709 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg, 710 sizeof(bind_msg), false, NULL, 0); 711 if (ret) 712 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.", 713 op_str, queue_id, bind_msg.vector_id, ret); 714 715 return ret; 716 } 717 718 static int 719 hns3vf_init_ring_with_vector(struct hns3_hw *hw) 720 { 721 uint16_t vec; 722 int ret; 723 int i; 724 725 /* 726 * In hns3 network engine, vector 0 is always the misc interrupt of this 727 * function, vector 1~N can be used respectively for the queues of the 728 * function. Tx and Rx queues with the same number share the interrupt 729 * vector. In the initialization clearing the all hardware mapping 730 * relationship configurations between queues and interrupt vectors is 731 * needed, so some error caused by the residual configurations, such as 732 * the unexpected Tx interrupt, can be avoid. 733 */ 734 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 735 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 736 vec = vec - 1; /* the last interrupt is reserved */ 737 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 738 for (i = 0; i < hw->intr_tqps_num; i++) { 739 /* 740 * Set gap limiter/rate limiter/quanity limiter algorithm 741 * configuration for interrupt coalesce of queue's interrupt. 742 */ 743 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 744 HNS3_TQP_INTR_GL_DEFAULT); 745 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 746 HNS3_TQP_INTR_GL_DEFAULT); 747 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 748 /* 749 * QL(quantity limiter) is not used currently, just set 0 to 750 * close it. 751 */ 752 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 753 754 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 755 HNS3_RING_TYPE_TX, i); 756 if (ret) { 757 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with " 758 "vector: %u, ret=%d", i, vec, ret); 759 return ret; 760 } 761 762 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 763 HNS3_RING_TYPE_RX, i); 764 if (ret) { 765 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with " 766 "vector: %u, ret=%d", i, vec, ret); 767 return ret; 768 } 769 } 770 771 return 0; 772 } 773 774 static int 775 hns3vf_dev_configure(struct rte_eth_dev *dev) 776 { 777 struct hns3_adapter *hns = dev->data->dev_private; 778 struct hns3_hw *hw = &hns->hw; 779 struct rte_eth_conf *conf = &dev->data->dev_conf; 780 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 781 uint16_t nb_rx_q = dev->data->nb_rx_queues; 782 uint16_t nb_tx_q = dev->data->nb_tx_queues; 783 struct rte_eth_rss_conf rss_conf; 784 uint32_t max_rx_pkt_len; 785 uint16_t mtu; 786 bool gro_en; 787 int ret; 788 789 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 790 791 /* 792 * Some versions of hardware network engine does not support 793 * individually enable/disable/reset the Tx or Rx queue. These devices 794 * must enable/disable/reset Tx and Rx queues at the same time. When the 795 * numbers of Tx queues allocated by upper applications are not equal to 796 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 797 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 798 * work as usual. But these fake queues are imperceptible, and can not 799 * be used by upper applications. 800 */ 801 if (!hns3_dev_indep_txrx_supported(hw)) { 802 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 803 if (ret) { 804 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", 805 ret); 806 return ret; 807 } 808 } 809 810 hw->adapter_state = HNS3_NIC_CONFIGURING; 811 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 812 hns3_err(hw, "setting link speed/duplex not supported"); 813 ret = -EINVAL; 814 goto cfg_err; 815 } 816 817 /* When RSS is not configured, redirect the packet queue 0 */ 818 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 819 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 820 hw->rss_dis_flag = false; 821 rss_conf = conf->rx_adv_conf.rss_conf; 822 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 823 if (ret) 824 goto cfg_err; 825 } 826 827 /* 828 * If jumbo frames are enabled, MTU needs to be refreshed 829 * according to the maximum RX packet length. 830 */ 831 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 832 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len; 833 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN || 834 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) { 835 hns3_err(hw, "maximum Rx packet length must be greater " 836 "than %u and less than %u when jumbo frame enabled.", 837 (uint16_t)HNS3_DEFAULT_FRAME_LEN, 838 (uint16_t)HNS3_MAX_FRAME_LEN); 839 ret = -EINVAL; 840 goto cfg_err; 841 } 842 843 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len); 844 ret = hns3vf_dev_mtu_set(dev, mtu); 845 if (ret) 846 goto cfg_err; 847 dev->data->mtu = mtu; 848 } 849 850 ret = hns3vf_dev_configure_vlan(dev); 851 if (ret) 852 goto cfg_err; 853 854 /* config hardware GRO */ 855 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 856 ret = hns3_config_gro(hw, gro_en); 857 if (ret) 858 goto cfg_err; 859 860 hns3_init_rx_ptype_tble(dev); 861 862 hw->adapter_state = HNS3_NIC_CONFIGURED; 863 return 0; 864 865 cfg_err: 866 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 867 hw->adapter_state = HNS3_NIC_INITIALIZED; 868 869 return ret; 870 } 871 872 static int 873 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu) 874 { 875 int ret; 876 877 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu, 878 sizeof(mtu), true, NULL, 0); 879 if (ret) 880 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret); 881 882 return ret; 883 } 884 885 static int 886 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 887 { 888 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 889 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 890 int ret; 891 892 /* 893 * The hns3 PF/VF devices on the same port share the hardware MTU 894 * configuration. Currently, we send mailbox to inform hns3 PF kernel 895 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD 896 * driver, there is no need to stop the port for hns3 VF device, and the 897 * MTU value issued by hns3 VF PMD driver must be less than or equal to 898 * PF's MTU. 899 */ 900 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 901 hns3_err(hw, "Failed to set mtu during resetting"); 902 return -EIO; 903 } 904 905 /* 906 * when Rx of scattered packets is off, we have some possibility of 907 * using vector Rx process function or simple Rx functions in hns3 PMD 908 * driver. If the input MTU is increased and the maximum length of 909 * received packets is greater than the length of a buffer for Rx 910 * packet, the hardware network engine needs to use multiple BDs and 911 * buffers to store these packets. This will cause problems when still 912 * using vector Rx process function or simple Rx function to receiving 913 * packets. So, when Rx of scattered packets is off and device is 914 * started, it is not permitted to increase MTU so that the maximum 915 * length of Rx packets is greater than Rx buffer length. 916 */ 917 if (dev->data->dev_started && !dev->data->scattered_rx && 918 frame_size > hw->rx_buf_len) { 919 hns3_err(hw, "failed to set mtu because current is " 920 "not scattered rx mode"); 921 return -EOPNOTSUPP; 922 } 923 924 rte_spinlock_lock(&hw->lock); 925 ret = hns3vf_config_mtu(hw, mtu); 926 if (ret) { 927 rte_spinlock_unlock(&hw->lock); 928 return ret; 929 } 930 if (mtu > RTE_ETHER_MTU) 931 dev->data->dev_conf.rxmode.offloads |= 932 DEV_RX_OFFLOAD_JUMBO_FRAME; 933 else 934 dev->data->dev_conf.rxmode.offloads &= 935 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 936 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 937 rte_spinlock_unlock(&hw->lock); 938 939 return 0; 940 } 941 942 static int 943 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 944 { 945 struct hns3_adapter *hns = eth_dev->data->dev_private; 946 struct hns3_hw *hw = &hns->hw; 947 uint16_t q_num = hw->tqps_num; 948 949 /* 950 * In interrupt mode, 'max_rx_queues' is set based on the number of 951 * MSI-X interrupt resources of the hardware. 952 */ 953 if (hw->data->dev_conf.intr_conf.rxq == 1) 954 q_num = hw->intr_tqps_num; 955 956 info->max_rx_queues = q_num; 957 info->max_tx_queues = hw->tqps_num; 958 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 959 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 960 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; 961 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 962 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 963 964 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 965 DEV_RX_OFFLOAD_UDP_CKSUM | 966 DEV_RX_OFFLOAD_TCP_CKSUM | 967 DEV_RX_OFFLOAD_SCTP_CKSUM | 968 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 969 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 970 DEV_RX_OFFLOAD_SCATTER | 971 DEV_RX_OFFLOAD_VLAN_STRIP | 972 DEV_RX_OFFLOAD_VLAN_FILTER | 973 DEV_RX_OFFLOAD_JUMBO_FRAME | 974 DEV_RX_OFFLOAD_RSS_HASH | 975 DEV_RX_OFFLOAD_TCP_LRO); 976 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 977 DEV_TX_OFFLOAD_IPV4_CKSUM | 978 DEV_TX_OFFLOAD_TCP_CKSUM | 979 DEV_TX_OFFLOAD_UDP_CKSUM | 980 DEV_TX_OFFLOAD_SCTP_CKSUM | 981 DEV_TX_OFFLOAD_MULTI_SEGS | 982 DEV_TX_OFFLOAD_TCP_TSO | 983 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 984 DEV_TX_OFFLOAD_GRE_TNL_TSO | 985 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 986 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 987 hns3_txvlan_cap_get(hw)); 988 989 if (hns3_dev_outer_udp_cksum_supported(hw)) 990 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 991 992 if (hns3_dev_indep_txrx_supported(hw)) 993 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 994 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 995 996 info->rx_desc_lim = (struct rte_eth_desc_lim) { 997 .nb_max = HNS3_MAX_RING_DESC, 998 .nb_min = HNS3_MIN_RING_DESC, 999 .nb_align = HNS3_ALIGN_RING_DESC, 1000 }; 1001 1002 info->tx_desc_lim = (struct rte_eth_desc_lim) { 1003 .nb_max = HNS3_MAX_RING_DESC, 1004 .nb_min = HNS3_MIN_RING_DESC, 1005 .nb_align = HNS3_ALIGN_RING_DESC, 1006 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 1007 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 1008 }; 1009 1010 info->default_rxconf = (struct rte_eth_rxconf) { 1011 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 1012 /* 1013 * If there are no available Rx buffer descriptors, incoming 1014 * packets are always dropped by hardware based on hns3 network 1015 * engine. 1016 */ 1017 .rx_drop_en = 1, 1018 .offloads = 0, 1019 }; 1020 info->default_txconf = (struct rte_eth_txconf) { 1021 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 1022 .offloads = 0, 1023 }; 1024 1025 info->vmdq_queue_num = 0; 1026 1027 info->reta_size = hw->rss_ind_tbl_size; 1028 info->hash_key_size = HNS3_RSS_KEY_SIZE; 1029 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 1030 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1031 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1032 1033 return 0; 1034 } 1035 1036 static void 1037 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr) 1038 { 1039 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 1040 } 1041 1042 static void 1043 hns3vf_disable_irq0(struct hns3_hw *hw) 1044 { 1045 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 1046 } 1047 1048 static void 1049 hns3vf_enable_irq0(struct hns3_hw *hw) 1050 { 1051 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 1052 } 1053 1054 static enum hns3vf_evt_cause 1055 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 1056 { 1057 struct hns3_hw *hw = &hns->hw; 1058 enum hns3vf_evt_cause ret; 1059 uint32_t cmdq_stat_reg; 1060 uint32_t rst_ing_reg; 1061 uint32_t val; 1062 1063 /* Fetch the events from their corresponding regs */ 1064 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG); 1065 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1066 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING); 1067 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg); 1068 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 1069 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 1070 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 1071 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT); 1072 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B); 1073 if (clearval) { 1074 hw->reset.stats.global_cnt++; 1075 hns3_warn(hw, "Global reset detected, clear reset status"); 1076 } else { 1077 hns3_schedule_delayed_reset(hns); 1078 hns3_warn(hw, "Global reset detected, don't clear reset status"); 1079 } 1080 1081 ret = HNS3VF_VECTOR0_EVENT_RST; 1082 goto out; 1083 } 1084 1085 /* Check for vector0 mailbox(=CMDQ RX) event source */ 1086 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1087 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 1088 ret = HNS3VF_VECTOR0_EVENT_MBX; 1089 goto out; 1090 } 1091 1092 val = 0; 1093 ret = HNS3VF_VECTOR0_EVENT_OTHER; 1094 out: 1095 if (clearval) 1096 *clearval = val; 1097 return ret; 1098 } 1099 1100 static void 1101 hns3vf_interrupt_handler(void *param) 1102 { 1103 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1104 struct hns3_adapter *hns = dev->data->dev_private; 1105 struct hns3_hw *hw = &hns->hw; 1106 enum hns3vf_evt_cause event_cause; 1107 uint32_t clearval; 1108 1109 /* Disable interrupt */ 1110 hns3vf_disable_irq0(hw); 1111 1112 /* Read out interrupt causes */ 1113 event_cause = hns3vf_check_event_cause(hns, &clearval); 1114 1115 switch (event_cause) { 1116 case HNS3VF_VECTOR0_EVENT_RST: 1117 hns3_schedule_reset(hns); 1118 break; 1119 case HNS3VF_VECTOR0_EVENT_MBX: 1120 hns3_dev_handle_mbx_msg(hw); 1121 break; 1122 default: 1123 break; 1124 } 1125 1126 /* Clear interrupt causes */ 1127 hns3vf_clear_event_cause(hw, clearval); 1128 1129 /* Enable interrupt */ 1130 hns3vf_enable_irq0(hw); 1131 } 1132 1133 static void 1134 hns3vf_set_default_dev_specifications(struct hns3_hw *hw) 1135 { 1136 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 1137 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 1138 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 1139 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 1140 } 1141 1142 static void 1143 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 1144 { 1145 struct hns3_dev_specs_0_cmd *req0; 1146 1147 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 1148 1149 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 1150 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 1151 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 1152 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 1153 } 1154 1155 static int 1156 hns3vf_check_dev_specifications(struct hns3_hw *hw) 1157 { 1158 if (hw->rss_ind_tbl_size == 0 || 1159 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 1160 hns3_warn(hw, "the size of hash lookup table configured (%u)" 1161 " exceeds the maximum(%u)", hw->rss_ind_tbl_size, 1162 HNS3_RSS_IND_TBL_SIZE_MAX); 1163 return -EINVAL; 1164 } 1165 1166 return 0; 1167 } 1168 1169 static int 1170 hns3vf_query_dev_specifications(struct hns3_hw *hw) 1171 { 1172 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 1173 int ret; 1174 int i; 1175 1176 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1177 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 1178 true); 1179 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1180 } 1181 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 1182 1183 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 1184 if (ret) 1185 return ret; 1186 1187 hns3vf_parse_dev_specifications(hw, desc); 1188 1189 return hns3vf_check_dev_specifications(hw); 1190 } 1191 1192 void 1193 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported) 1194 { 1195 uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED : 1196 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED; 1197 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN; 1198 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw); 1199 1200 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN) 1201 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0, 1202 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); 1203 } 1204 1205 static void 1206 hns3vf_get_push_lsc_cap(struct hns3_hw *hw) 1207 { 1208 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500 1209 1210 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1211 int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS; 1212 uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED; 1213 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN; 1214 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw); 1215 1216 __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN, 1217 __ATOMIC_RELEASE); 1218 1219 (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false, 1220 NULL, 0); 1221 1222 while (remain_ms > 0) { 1223 rte_delay_ms(HNS3_POLL_RESPONE_MS); 1224 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) != 1225 HNS3_PF_PUSH_LSC_CAP_UNKNOWN) 1226 break; 1227 remain_ms--; 1228 } 1229 1230 /* 1231 * When exit above loop, the pf_push_lsc_cap could be one of the three 1232 * state: unknown (means pf not ack), not_supported, supported. 1233 * Here config it as 'not_supported' when it's 'unknown' state. 1234 */ 1235 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0, 1236 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); 1237 1238 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) == 1239 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) { 1240 hns3_info(hw, "detect PF support push link status change!"); 1241 } else { 1242 /* 1243 * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver 1244 * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared 1245 * the RTE_ETH_DEV_INTR_LSC capability. 1246 */ 1247 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 1248 } 1249 } 1250 1251 static int 1252 hns3vf_get_capability(struct hns3_hw *hw) 1253 { 1254 struct rte_pci_device *pci_dev; 1255 struct rte_eth_dev *eth_dev; 1256 uint8_t revision; 1257 int ret; 1258 1259 eth_dev = &rte_eth_devices[hw->data->port_id]; 1260 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1261 1262 /* Get PCI revision id */ 1263 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 1264 HNS3_PCI_REVISION_ID); 1265 if (ret != HNS3_PCI_REVISION_ID_LEN) { 1266 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 1267 ret); 1268 return -EIO; 1269 } 1270 hw->revision = revision; 1271 1272 if (revision < PCI_REVISION_ID_HIP09_A) { 1273 hns3vf_set_default_dev_specifications(hw); 1274 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 1275 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 1276 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 1277 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 1278 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 1279 hw->rss_info.ipv6_sctp_offload_supported = false; 1280 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; 1281 return 0; 1282 } 1283 1284 ret = hns3vf_query_dev_specifications(hw); 1285 if (ret) { 1286 PMD_INIT_LOG(ERR, 1287 "failed to query dev specifications, ret = %d", 1288 ret); 1289 return ret; 1290 } 1291 1292 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 1293 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 1294 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 1295 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 1296 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 1297 hw->rss_info.ipv6_sctp_offload_supported = true; 1298 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; 1299 1300 return 0; 1301 } 1302 1303 static int 1304 hns3vf_check_tqp_info(struct hns3_hw *hw) 1305 { 1306 if (hw->tqps_num == 0) { 1307 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF."); 1308 return -EINVAL; 1309 } 1310 1311 if (hw->rss_size_max == 0) { 1312 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF."); 1313 return -EINVAL; 1314 } 1315 1316 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num); 1317 1318 return 0; 1319 } 1320 1321 static int 1322 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw) 1323 { 1324 uint8_t resp_msg; 1325 int ret; 1326 1327 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, 1328 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0, 1329 true, &resp_msg, sizeof(resp_msg)); 1330 if (ret) { 1331 if (ret == -ETIME) { 1332 /* 1333 * Getting current port based VLAN state from PF driver 1334 * will not affect VF driver's basic function. Because 1335 * the VF driver relies on hns3 PF kernel ether driver, 1336 * to avoid introducing compatibility issues with older 1337 * version of PF driver, no failure will be returned 1338 * when the return value is ETIME. This return value has 1339 * the following scenarios: 1340 * 1) Firmware didn't return the results in time 1341 * 2) the result return by firmware is timeout 1342 * 3) the older version of kernel side PF driver does 1343 * not support this mailbox message. 1344 * For scenarios 1 and 2, it is most likely that a 1345 * hardware error has occurred, or a hardware reset has 1346 * occurred. In this case, these errors will be caught 1347 * by other functions. 1348 */ 1349 PMD_INIT_LOG(WARNING, 1350 "failed to get PVID state for timeout, maybe " 1351 "kernel side PF driver doesn't support this " 1352 "mailbox message, or firmware didn't respond."); 1353 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE; 1354 } else { 1355 PMD_INIT_LOG(ERR, "failed to get port based VLAN state," 1356 " ret = %d", ret); 1357 return ret; 1358 } 1359 } 1360 hw->port_base_vlan_cfg.state = resp_msg ? 1361 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 1362 return 0; 1363 } 1364 1365 static int 1366 hns3vf_get_queue_info(struct hns3_hw *hw) 1367 { 1368 #define HNS3VF_TQPS_RSS_INFO_LEN 6 1369 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN]; 1370 int ret; 1371 1372 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true, 1373 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN); 1374 if (ret) { 1375 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret); 1376 return ret; 1377 } 1378 1379 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t)); 1380 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t)); 1381 1382 return hns3vf_check_tqp_info(hw); 1383 } 1384 1385 static int 1386 hns3vf_get_queue_depth(struct hns3_hw *hw) 1387 { 1388 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4 1389 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN]; 1390 int ret; 1391 1392 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true, 1393 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN); 1394 if (ret) { 1395 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d", 1396 ret); 1397 return ret; 1398 } 1399 1400 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t)); 1401 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t)); 1402 1403 return 0; 1404 } 1405 1406 static int 1407 hns3vf_get_tc_info(struct hns3_hw *hw) 1408 { 1409 uint8_t resp_msg; 1410 int ret; 1411 uint32_t i; 1412 1413 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0, 1414 true, &resp_msg, sizeof(resp_msg)); 1415 if (ret) { 1416 hns3_err(hw, "VF request to get TC info from PF failed %d", 1417 ret); 1418 return ret; 1419 } 1420 1421 hw->hw_tc_map = resp_msg; 1422 1423 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 1424 if (hw->hw_tc_map & BIT(i)) 1425 hw->num_tc++; 1426 } 1427 1428 return 0; 1429 } 1430 1431 static int 1432 hns3vf_get_host_mac_addr(struct hns3_hw *hw) 1433 { 1434 uint8_t host_mac[RTE_ETHER_ADDR_LEN]; 1435 int ret; 1436 1437 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0, 1438 true, host_mac, RTE_ETHER_ADDR_LEN); 1439 if (ret) { 1440 hns3_err(hw, "Failed to get mac addr from PF: %d", ret); 1441 return ret; 1442 } 1443 1444 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN); 1445 1446 return 0; 1447 } 1448 1449 static int 1450 hns3vf_get_configuration(struct hns3_hw *hw) 1451 { 1452 int ret; 1453 1454 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE; 1455 hw->rss_dis_flag = false; 1456 1457 /* Get device capability */ 1458 ret = hns3vf_get_capability(hw); 1459 if (ret) { 1460 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 1461 return ret; 1462 } 1463 1464 hns3vf_get_push_lsc_cap(hw); 1465 1466 /* Get queue configuration from PF */ 1467 ret = hns3vf_get_queue_info(hw); 1468 if (ret) 1469 return ret; 1470 1471 /* Get queue depth info from PF */ 1472 ret = hns3vf_get_queue_depth(hw); 1473 if (ret) 1474 return ret; 1475 1476 /* Get user defined VF MAC addr from PF */ 1477 ret = hns3vf_get_host_mac_addr(hw); 1478 if (ret) 1479 return ret; 1480 1481 ret = hns3vf_get_port_base_vlan_filter_state(hw); 1482 if (ret) 1483 return ret; 1484 1485 /* Get tc configuration from PF */ 1486 return hns3vf_get_tc_info(hw); 1487 } 1488 1489 static int 1490 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q, 1491 uint16_t nb_tx_q) 1492 { 1493 struct hns3_hw *hw = &hns->hw; 1494 1495 if (nb_rx_q < hw->num_tc) { 1496 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).", 1497 nb_rx_q, hw->num_tc); 1498 return -EINVAL; 1499 } 1500 1501 if (nb_tx_q < hw->num_tc) { 1502 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).", 1503 nb_tx_q, hw->num_tc); 1504 return -EINVAL; 1505 } 1506 1507 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q); 1508 } 1509 1510 static void 1511 hns3vf_request_link_info(struct hns3_hw *hw) 1512 { 1513 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw); 1514 uint8_t resp_msg; 1515 bool send_req; 1516 int ret; 1517 1518 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 1519 return; 1520 1521 send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED || 1522 vf->req_link_info_cnt > 0; 1523 if (!send_req) 1524 return; 1525 1526 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false, 1527 &resp_msg, sizeof(resp_msg)); 1528 if (ret) { 1529 hns3_err(hw, "failed to fetch link status, ret = %d", ret); 1530 return; 1531 } 1532 1533 if (vf->req_link_info_cnt > 0) 1534 vf->req_link_info_cnt--; 1535 } 1536 1537 void 1538 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1539 uint32_t link_speed, uint8_t link_duplex) 1540 { 1541 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1542 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw); 1543 struct hns3_mac *mac = &hw->mac; 1544 int ret; 1545 1546 /* 1547 * PF kernel driver may push link status when VF driver is in resetting, 1548 * driver will stop polling job in this case, after resetting done 1549 * driver will start polling job again. 1550 * When polling job started, driver will get initial link status by 1551 * sending request to PF kernel driver, then could update link status by 1552 * process PF kernel driver's link status mailbox message. 1553 */ 1554 if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED)) 1555 return; 1556 1557 if (hw->adapter_state != HNS3_NIC_STARTED) 1558 return; 1559 1560 mac->link_status = link_status; 1561 mac->link_speed = link_speed; 1562 mac->link_duplex = link_duplex; 1563 ret = hns3vf_dev_link_update(dev, 0); 1564 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0) 1565 hns3_start_report_lse(dev); 1566 } 1567 1568 static int 1569 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 1570 { 1571 #define HNS3VF_VLAN_MBX_MSG_LEN 5 1572 struct hns3_hw *hw = &hns->hw; 1573 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN]; 1574 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN); 1575 uint8_t is_kill = on ? 0 : 1; 1576 1577 msg_data[0] = is_kill; 1578 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1579 memcpy(&msg_data[3], &proto, sizeof(proto)); 1580 1581 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER, 1582 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL, 1583 0); 1584 } 1585 1586 static int 1587 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1588 { 1589 struct hns3_adapter *hns = dev->data->dev_private; 1590 struct hns3_hw *hw = &hns->hw; 1591 int ret; 1592 1593 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 1594 hns3_err(hw, 1595 "vf set vlan id failed during resetting, vlan_id =%u", 1596 vlan_id); 1597 return -EIO; 1598 } 1599 rte_spinlock_lock(&hw->lock); 1600 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1601 rte_spinlock_unlock(&hw->lock); 1602 if (ret) 1603 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d", 1604 vlan_id, ret); 1605 1606 return ret; 1607 } 1608 1609 static int 1610 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable) 1611 { 1612 uint8_t msg_data; 1613 int ret; 1614 1615 msg_data = enable ? 1 : 0; 1616 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG, 1617 &msg_data, sizeof(msg_data), false, NULL, 0); 1618 if (ret) 1619 hns3_err(hw, "vf enable strip failed, ret =%d", ret); 1620 1621 return ret; 1622 } 1623 1624 static int 1625 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1626 { 1627 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1628 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1629 unsigned int tmp_mask; 1630 int ret = 0; 1631 1632 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 1633 hns3_err(hw, "vf set vlan offload failed during resetting, " 1634 "mask = 0x%x", mask); 1635 return -EIO; 1636 } 1637 1638 tmp_mask = (unsigned int)mask; 1639 /* Vlan stripping setting */ 1640 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 1641 rte_spinlock_lock(&hw->lock); 1642 /* Enable or disable VLAN stripping */ 1643 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1644 ret = hns3vf_en_hw_strip_rxvtag(hw, true); 1645 else 1646 ret = hns3vf_en_hw_strip_rxvtag(hw, false); 1647 rte_spinlock_unlock(&hw->lock); 1648 } 1649 1650 return ret; 1651 } 1652 1653 static int 1654 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on) 1655 { 1656 struct rte_vlan_filter_conf *vfc; 1657 struct hns3_hw *hw = &hns->hw; 1658 uint16_t vlan_id; 1659 uint64_t vbit; 1660 uint64_t ids; 1661 int ret = 0; 1662 uint32_t i; 1663 1664 vfc = &hw->data->vlan_filter_conf; 1665 for (i = 0; i < RTE_DIM(vfc->ids); i++) { 1666 if (vfc->ids[i] == 0) 1667 continue; 1668 ids = vfc->ids[i]; 1669 while (ids) { 1670 /* 1671 * 64 means the num bits of ids, one bit corresponds to 1672 * one vlan id 1673 */ 1674 vlan_id = 64 * i; 1675 /* count trailing zeroes */ 1676 vbit = ~ids & (ids - 1); 1677 /* clear least significant bit set */ 1678 ids ^= (ids ^ (ids - 1)) ^ vbit; 1679 for (; vbit;) { 1680 vbit >>= 1; 1681 vlan_id++; 1682 } 1683 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1684 if (ret) { 1685 hns3_err(hw, 1686 "VF handle vlan table failed, ret =%d, on = %d", 1687 ret, on); 1688 return ret; 1689 } 1690 } 1691 } 1692 1693 return ret; 1694 } 1695 1696 static int 1697 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns) 1698 { 1699 return hns3vf_handle_all_vlan_table(hns, 0); 1700 } 1701 1702 static int 1703 hns3vf_restore_vlan_conf(struct hns3_adapter *hns) 1704 { 1705 struct hns3_hw *hw = &hns->hw; 1706 struct rte_eth_conf *dev_conf; 1707 bool en; 1708 int ret; 1709 1710 dev_conf = &hw->data->dev_conf; 1711 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true 1712 : false; 1713 ret = hns3vf_en_hw_strip_rxvtag(hw, en); 1714 if (ret) 1715 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en, 1716 ret); 1717 return ret; 1718 } 1719 1720 static int 1721 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev) 1722 { 1723 struct hns3_adapter *hns = dev->data->dev_private; 1724 struct rte_eth_dev_data *data = dev->data; 1725 struct hns3_hw *hw = &hns->hw; 1726 int ret; 1727 1728 if (data->dev_conf.txmode.hw_vlan_reject_tagged || 1729 data->dev_conf.txmode.hw_vlan_reject_untagged || 1730 data->dev_conf.txmode.hw_vlan_insert_pvid) { 1731 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged " 1732 "or hw_vlan_insert_pvid is not support!"); 1733 } 1734 1735 /* Apply vlan offload setting */ 1736 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK); 1737 if (ret) 1738 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret); 1739 1740 return ret; 1741 } 1742 1743 static int 1744 hns3vf_set_alive(struct hns3_hw *hw, bool alive) 1745 { 1746 uint8_t msg_data; 1747 1748 msg_data = alive ? 1 : 0; 1749 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data, 1750 sizeof(msg_data), false, NULL, 0); 1751 } 1752 1753 static void 1754 hns3vf_keep_alive_handler(void *param) 1755 { 1756 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1757 struct hns3_adapter *hns = eth_dev->data->dev_private; 1758 struct hns3_hw *hw = &hns->hw; 1759 uint8_t respmsg; 1760 int ret; 1761 1762 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0, 1763 false, &respmsg, sizeof(uint8_t)); 1764 if (ret) 1765 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)", 1766 ret); 1767 1768 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 1769 eth_dev); 1770 } 1771 1772 static void 1773 hns3vf_service_handler(void *param) 1774 { 1775 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1776 struct hns3_adapter *hns = eth_dev->data->dev_private; 1777 struct hns3_hw *hw = &hns->hw; 1778 1779 /* 1780 * The query link status and reset processing are executed in the 1781 * interrupt thread. When the IMP reset occurs, IMP will not respond, 1782 * and the query operation will timeout after 30ms. In the case of 1783 * multiple PF/VFs, each query failure timeout causes the IMP reset 1784 * interrupt to fail to respond within 100ms. 1785 * Before querying the link status, check whether there is a reset 1786 * pending, and if so, abandon the query. 1787 */ 1788 if (!hns3vf_is_reset_pending(hns)) 1789 hns3vf_request_link_info(hw); 1790 else 1791 hns3_warn(hw, "Cancel the query when reset is pending"); 1792 1793 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, 1794 eth_dev); 1795 } 1796 1797 static void 1798 hns3vf_start_poll_job(struct rte_eth_dev *dev) 1799 { 1800 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT 3 1801 1802 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1803 1804 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED) 1805 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT; 1806 1807 __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED); 1808 1809 hns3vf_service_handler(dev); 1810 } 1811 1812 static void 1813 hns3vf_stop_poll_job(struct rte_eth_dev *dev) 1814 { 1815 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1816 1817 rte_eal_alarm_cancel(hns3vf_service_handler, dev); 1818 1819 __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED); 1820 } 1821 1822 static int 1823 hns3_query_vf_resource(struct hns3_hw *hw) 1824 { 1825 struct hns3_vf_res_cmd *req; 1826 struct hns3_cmd_desc desc; 1827 uint16_t num_msi; 1828 int ret; 1829 1830 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true); 1831 ret = hns3_cmd_send(hw, &desc, 1); 1832 if (ret) { 1833 hns3_err(hw, "query vf resource failed, ret = %d", ret); 1834 return ret; 1835 } 1836 1837 req = (struct hns3_vf_res_cmd *)desc.data; 1838 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number), 1839 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S); 1840 if (num_msi < HNS3_MIN_VECTOR_NUM) { 1841 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)", 1842 num_msi, HNS3_MIN_VECTOR_NUM); 1843 return -EINVAL; 1844 } 1845 1846 hw->num_msi = num_msi; 1847 1848 return 0; 1849 } 1850 1851 static int 1852 hns3vf_init_hardware(struct hns3_adapter *hns) 1853 { 1854 struct hns3_hw *hw = &hns->hw; 1855 uint16_t mtu = hw->data->mtu; 1856 int ret; 1857 1858 ret = hns3vf_set_promisc_mode(hw, true, false, false); 1859 if (ret) 1860 return ret; 1861 1862 ret = hns3vf_config_mtu(hw, mtu); 1863 if (ret) 1864 goto err_init_hardware; 1865 1866 ret = hns3vf_vlan_filter_configure(hns, 0, 1); 1867 if (ret) { 1868 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret); 1869 goto err_init_hardware; 1870 } 1871 1872 ret = hns3_config_gro(hw, false); 1873 if (ret) { 1874 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 1875 goto err_init_hardware; 1876 } 1877 1878 /* 1879 * In the initialization clearing the all hardware mapping relationship 1880 * configurations between queues and interrupt vectors is needed, so 1881 * some error caused by the residual configurations, such as the 1882 * unexpected interrupt, can be avoid. 1883 */ 1884 ret = hns3vf_init_ring_with_vector(hw); 1885 if (ret) { 1886 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 1887 goto err_init_hardware; 1888 } 1889 1890 ret = hns3vf_set_alive(hw, true); 1891 if (ret) { 1892 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret); 1893 goto err_init_hardware; 1894 } 1895 1896 return 0; 1897 1898 err_init_hardware: 1899 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1900 return ret; 1901 } 1902 1903 static int 1904 hns3vf_clear_vport_list(struct hns3_hw *hw) 1905 { 1906 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL, 1907 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false, 1908 NULL, 0); 1909 } 1910 1911 static int 1912 hns3vf_init_vf(struct rte_eth_dev *eth_dev) 1913 { 1914 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1915 struct hns3_adapter *hns = eth_dev->data->dev_private; 1916 struct hns3_hw *hw = &hns->hw; 1917 int ret; 1918 1919 PMD_INIT_FUNC_TRACE(); 1920 1921 /* Get hardware io base address from pcie BAR2 IO space */ 1922 hw->io_base = pci_dev->mem_resource[2].addr; 1923 1924 /* Firmware command queue initialize */ 1925 ret = hns3_cmd_init_queue(hw); 1926 if (ret) { 1927 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 1928 goto err_cmd_init_queue; 1929 } 1930 1931 /* Firmware command initialize */ 1932 ret = hns3_cmd_init(hw); 1933 if (ret) { 1934 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 1935 goto err_cmd_init; 1936 } 1937 1938 /* Get VF resource */ 1939 ret = hns3_query_vf_resource(hw); 1940 if (ret) 1941 goto err_cmd_init; 1942 1943 rte_spinlock_init(&hw->mbx_resp.lock); 1944 1945 hns3vf_clear_event_cause(hw, 0); 1946 1947 ret = rte_intr_callback_register(&pci_dev->intr_handle, 1948 hns3vf_interrupt_handler, eth_dev); 1949 if (ret) { 1950 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 1951 goto err_intr_callback_register; 1952 } 1953 1954 /* Enable interrupt */ 1955 rte_intr_enable(&pci_dev->intr_handle); 1956 hns3vf_enable_irq0(hw); 1957 1958 /* Get configuration from PF */ 1959 ret = hns3vf_get_configuration(hw); 1960 if (ret) { 1961 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 1962 goto err_get_config; 1963 } 1964 1965 ret = hns3_tqp_stats_init(hw); 1966 if (ret) 1967 goto err_get_config; 1968 1969 /* Hardware statistics of imissed registers cleared. */ 1970 ret = hns3_update_imissed_stats(hw, true); 1971 if (ret) { 1972 hns3_err(hw, "clear imissed stats failed, ret = %d", ret); 1973 goto err_set_tc_queue; 1974 } 1975 1976 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); 1977 if (ret) { 1978 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); 1979 goto err_set_tc_queue; 1980 } 1981 1982 ret = hns3vf_clear_vport_list(hw); 1983 if (ret) { 1984 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret); 1985 goto err_set_tc_queue; 1986 } 1987 1988 ret = hns3vf_init_hardware(hns); 1989 if (ret) 1990 goto err_set_tc_queue; 1991 1992 hns3_rss_set_default_args(hw); 1993 1994 return 0; 1995 1996 err_set_tc_queue: 1997 hns3_tqp_stats_uninit(hw); 1998 1999 err_get_config: 2000 hns3vf_disable_irq0(hw); 2001 rte_intr_disable(&pci_dev->intr_handle); 2002 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 2003 eth_dev); 2004 err_intr_callback_register: 2005 err_cmd_init: 2006 hns3_cmd_uninit(hw); 2007 hns3_cmd_destroy_queue(hw); 2008 err_cmd_init_queue: 2009 hw->io_base = NULL; 2010 2011 return ret; 2012 } 2013 2014 static void 2015 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev) 2016 { 2017 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2018 struct hns3_adapter *hns = eth_dev->data->dev_private; 2019 struct hns3_hw *hw = &hns->hw; 2020 2021 PMD_INIT_FUNC_TRACE(); 2022 2023 hns3_rss_uninit(hns); 2024 (void)hns3_config_gro(hw, false); 2025 (void)hns3vf_set_alive(hw, false); 2026 (void)hns3vf_set_promisc_mode(hw, false, false, false); 2027 hns3_tqp_stats_uninit(hw); 2028 hns3vf_disable_irq0(hw); 2029 rte_intr_disable(&pci_dev->intr_handle); 2030 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 2031 eth_dev); 2032 hns3_cmd_uninit(hw); 2033 hns3_cmd_destroy_queue(hw); 2034 hw->io_base = NULL; 2035 } 2036 2037 static int 2038 hns3vf_do_stop(struct hns3_adapter *hns) 2039 { 2040 struct hns3_hw *hw = &hns->hw; 2041 int ret; 2042 2043 hw->mac.link_status = ETH_LINK_DOWN; 2044 2045 /* 2046 * The "hns3vf_do_stop" function will also be called by .stop_service to 2047 * prepare reset. At the time of global or IMP reset, the command cannot 2048 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 2049 * accessed during the reset process. So the mbuf can not be released 2050 * during reset and is required to be released after the reset is 2051 * completed. 2052 */ 2053 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 2054 hns3_dev_release_mbufs(hns); 2055 2056 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 2057 hns3vf_configure_mac_addr(hns, true); 2058 ret = hns3_reset_all_tqps(hns); 2059 if (ret) { 2060 hns3_err(hw, "failed to reset all queues ret = %d", 2061 ret); 2062 return ret; 2063 } 2064 } 2065 return 0; 2066 } 2067 2068 static void 2069 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev) 2070 { 2071 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2072 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2073 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2074 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 2075 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 2076 uint16_t q_id; 2077 2078 if (dev->data->dev_conf.intr_conf.rxq == 0) 2079 return; 2080 2081 /* unmap the ring with vector */ 2082 if (rte_intr_allow_others(intr_handle)) { 2083 vec = RTE_INTR_VEC_RXTX_OFFSET; 2084 base = RTE_INTR_VEC_RXTX_OFFSET; 2085 } 2086 if (rte_intr_dp_is_en(intr_handle)) { 2087 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2088 (void)hns3vf_bind_ring_with_vector(hw, vec, false, 2089 HNS3_RING_TYPE_RX, 2090 q_id); 2091 if (vec < base + intr_handle->nb_efd - 1) 2092 vec++; 2093 } 2094 } 2095 /* Clean datapath event and queue/vec mapping */ 2096 rte_intr_efd_disable(intr_handle); 2097 if (intr_handle->intr_vec) { 2098 rte_free(intr_handle->intr_vec); 2099 intr_handle->intr_vec = NULL; 2100 } 2101 } 2102 2103 static int 2104 hns3vf_dev_stop(struct rte_eth_dev *dev) 2105 { 2106 struct hns3_adapter *hns = dev->data->dev_private; 2107 struct hns3_hw *hw = &hns->hw; 2108 2109 PMD_INIT_FUNC_TRACE(); 2110 dev->data->dev_started = 0; 2111 2112 hw->adapter_state = HNS3_NIC_STOPPING; 2113 hns3_set_rxtx_function(dev); 2114 rte_wmb(); 2115 /* Disable datapath on secondary process. */ 2116 hns3_mp_req_stop_rxtx(dev); 2117 /* Prevent crashes when queues are still in use. */ 2118 rte_delay_ms(hw->tqps_num); 2119 2120 rte_spinlock_lock(&hw->lock); 2121 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 2122 hns3_stop_tqps(hw); 2123 hns3vf_do_stop(hns); 2124 hns3vf_unmap_rx_interrupt(dev); 2125 hw->adapter_state = HNS3_NIC_CONFIGURED; 2126 } 2127 hns3_rx_scattered_reset(dev); 2128 hns3vf_stop_poll_job(dev); 2129 hns3_stop_report_lse(dev); 2130 rte_spinlock_unlock(&hw->lock); 2131 2132 return 0; 2133 } 2134 2135 static int 2136 hns3vf_dev_close(struct rte_eth_dev *eth_dev) 2137 { 2138 struct hns3_adapter *hns = eth_dev->data->dev_private; 2139 struct hns3_hw *hw = &hns->hw; 2140 int ret = 0; 2141 2142 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2143 rte_free(eth_dev->process_private); 2144 eth_dev->process_private = NULL; 2145 return 0; 2146 } 2147 2148 if (hw->adapter_state == HNS3_NIC_STARTED) 2149 ret = hns3vf_dev_stop(eth_dev); 2150 2151 hw->adapter_state = HNS3_NIC_CLOSING; 2152 hns3_reset_abort(hns); 2153 hw->adapter_state = HNS3_NIC_CLOSED; 2154 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev); 2155 hns3vf_configure_all_mc_mac_addr(hns, true); 2156 hns3vf_remove_all_vlan_table(hns); 2157 hns3vf_uninit_vf(eth_dev); 2158 hns3_free_all_queues(eth_dev); 2159 rte_free(hw->reset.wait_data); 2160 rte_free(eth_dev->process_private); 2161 eth_dev->process_private = NULL; 2162 hns3_mp_uninit_primary(); 2163 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 2164 2165 return ret; 2166 } 2167 2168 static int 2169 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2170 size_t fw_size) 2171 { 2172 struct hns3_adapter *hns = eth_dev->data->dev_private; 2173 struct hns3_hw *hw = &hns->hw; 2174 uint32_t version = hw->fw_version; 2175 int ret; 2176 2177 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2178 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2179 HNS3_FW_VERSION_BYTE3_S), 2180 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2181 HNS3_FW_VERSION_BYTE2_S), 2182 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2183 HNS3_FW_VERSION_BYTE1_S), 2184 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2185 HNS3_FW_VERSION_BYTE0_S)); 2186 ret += 1; /* add the size of '\0' */ 2187 if (fw_size < (uint32_t)ret) 2188 return ret; 2189 else 2190 return 0; 2191 } 2192 2193 static int 2194 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, 2195 __rte_unused int wait_to_complete) 2196 { 2197 struct hns3_adapter *hns = eth_dev->data->dev_private; 2198 struct hns3_hw *hw = &hns->hw; 2199 struct hns3_mac *mac = &hw->mac; 2200 struct rte_eth_link new_link; 2201 2202 memset(&new_link, 0, sizeof(new_link)); 2203 switch (mac->link_speed) { 2204 case ETH_SPEED_NUM_10M: 2205 case ETH_SPEED_NUM_100M: 2206 case ETH_SPEED_NUM_1G: 2207 case ETH_SPEED_NUM_10G: 2208 case ETH_SPEED_NUM_25G: 2209 case ETH_SPEED_NUM_40G: 2210 case ETH_SPEED_NUM_50G: 2211 case ETH_SPEED_NUM_100G: 2212 case ETH_SPEED_NUM_200G: 2213 new_link.link_speed = mac->link_speed; 2214 break; 2215 default: 2216 if (mac->link_status) 2217 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN; 2218 else 2219 new_link.link_speed = ETH_SPEED_NUM_NONE; 2220 break; 2221 } 2222 2223 new_link.link_duplex = mac->link_duplex; 2224 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2225 new_link.link_autoneg = 2226 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2227 2228 return rte_eth_linkstatus_set(eth_dev, &new_link); 2229 } 2230 2231 static int 2232 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue) 2233 { 2234 struct hns3_hw *hw = &hns->hw; 2235 uint16_t nb_rx_q = hw->data->nb_rx_queues; 2236 uint16_t nb_tx_q = hw->data->nb_tx_queues; 2237 int ret; 2238 2239 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q); 2240 if (ret) 2241 return ret; 2242 2243 hns3_enable_rxd_adv_layout(hw); 2244 2245 ret = hns3_init_queues(hns, reset_queue); 2246 if (ret) 2247 hns3_err(hw, "failed to init queues, ret = %d.", ret); 2248 2249 return ret; 2250 } 2251 2252 static int 2253 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) 2254 { 2255 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2256 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2257 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2258 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 2259 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 2260 uint32_t intr_vector; 2261 uint16_t q_id; 2262 int ret; 2263 2264 /* 2265 * hns3 needs a separate interrupt to be used as event interrupt which 2266 * could not be shared with task queue pair, so KERNEL drivers need 2267 * support multiple interrupt vectors. 2268 */ 2269 if (dev->data->dev_conf.intr_conf.rxq == 0 || 2270 !rte_intr_cap_multiple(intr_handle)) 2271 return 0; 2272 2273 rte_intr_disable(intr_handle); 2274 intr_vector = hw->used_rx_queues; 2275 /* It creates event fd for each intr vector when MSIX is used */ 2276 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2277 return -EINVAL; 2278 2279 if (intr_handle->intr_vec == NULL) { 2280 intr_handle->intr_vec = 2281 rte_zmalloc("intr_vec", 2282 hw->used_rx_queues * sizeof(int), 0); 2283 if (intr_handle->intr_vec == NULL) { 2284 hns3_err(hw, "Failed to allocate %u rx_queues" 2285 " intr_vec", hw->used_rx_queues); 2286 ret = -ENOMEM; 2287 goto vf_alloc_intr_vec_error; 2288 } 2289 } 2290 2291 if (rte_intr_allow_others(intr_handle)) { 2292 vec = RTE_INTR_VEC_RXTX_OFFSET; 2293 base = RTE_INTR_VEC_RXTX_OFFSET; 2294 } 2295 2296 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2297 ret = hns3vf_bind_ring_with_vector(hw, vec, true, 2298 HNS3_RING_TYPE_RX, q_id); 2299 if (ret) 2300 goto vf_bind_vector_error; 2301 intr_handle->intr_vec[q_id] = vec; 2302 /* 2303 * If there are not enough efds (e.g. not enough interrupt), 2304 * remaining queues will be bond to the last interrupt. 2305 */ 2306 if (vec < base + intr_handle->nb_efd - 1) 2307 vec++; 2308 } 2309 rte_intr_enable(intr_handle); 2310 return 0; 2311 2312 vf_bind_vector_error: 2313 free(intr_handle->intr_vec); 2314 intr_handle->intr_vec = NULL; 2315 vf_alloc_intr_vec_error: 2316 rte_intr_efd_disable(intr_handle); 2317 return ret; 2318 } 2319 2320 static int 2321 hns3vf_restore_rx_interrupt(struct hns3_hw *hw) 2322 { 2323 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 2324 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2325 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2326 uint16_t q_id; 2327 int ret; 2328 2329 if (dev->data->dev_conf.intr_conf.rxq == 0) 2330 return 0; 2331 2332 if (rte_intr_dp_is_en(intr_handle)) { 2333 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2334 ret = hns3vf_bind_ring_with_vector(hw, 2335 intr_handle->intr_vec[q_id], true, 2336 HNS3_RING_TYPE_RX, q_id); 2337 if (ret) 2338 return ret; 2339 } 2340 } 2341 2342 return 0; 2343 } 2344 2345 static void 2346 hns3vf_restore_filter(struct rte_eth_dev *dev) 2347 { 2348 hns3_restore_rss_filter(dev); 2349 } 2350 2351 static int 2352 hns3vf_dev_start(struct rte_eth_dev *dev) 2353 { 2354 struct hns3_adapter *hns = dev->data->dev_private; 2355 struct hns3_hw *hw = &hns->hw; 2356 int ret; 2357 2358 PMD_INIT_FUNC_TRACE(); 2359 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 2360 return -EBUSY; 2361 2362 rte_spinlock_lock(&hw->lock); 2363 hw->adapter_state = HNS3_NIC_STARTING; 2364 ret = hns3vf_do_start(hns, true); 2365 if (ret) { 2366 hw->adapter_state = HNS3_NIC_CONFIGURED; 2367 rte_spinlock_unlock(&hw->lock); 2368 return ret; 2369 } 2370 ret = hns3vf_map_rx_interrupt(dev); 2371 if (ret) 2372 goto map_rx_inter_err; 2373 2374 /* 2375 * There are three register used to control the status of a TQP 2376 * (contains a pair of Tx queue and Rx queue) in the new version network 2377 * engine. One is used to control the enabling of Tx queue, the other is 2378 * used to control the enabling of Rx queue, and the last is the master 2379 * switch used to control the enabling of the tqp. The Tx register and 2380 * TQP register must be enabled at the same time to enable a Tx queue. 2381 * The same applies to the Rx queue. For the older network enginem, this 2382 * function only refresh the enabled flag, and it is used to update the 2383 * status of queue in the dpdk framework. 2384 */ 2385 ret = hns3_start_all_txqs(dev); 2386 if (ret) 2387 goto map_rx_inter_err; 2388 2389 ret = hns3_start_all_rxqs(dev); 2390 if (ret) 2391 goto start_all_rxqs_fail; 2392 2393 hw->adapter_state = HNS3_NIC_STARTED; 2394 rte_spinlock_unlock(&hw->lock); 2395 2396 hns3_rx_scattered_calc(dev); 2397 hns3_set_rxtx_function(dev); 2398 hns3_mp_req_start_rxtx(dev); 2399 2400 hns3vf_restore_filter(dev); 2401 2402 /* Enable interrupt of all rx queues before enabling queues */ 2403 hns3_dev_all_rx_queue_intr_enable(hw, true); 2404 hns3_start_tqps(hw); 2405 2406 if (dev->data->dev_conf.intr_conf.lsc != 0) 2407 hns3vf_dev_link_update(dev, 0); 2408 hns3vf_start_poll_job(dev); 2409 2410 return ret; 2411 2412 start_all_rxqs_fail: 2413 hns3_stop_all_txqs(dev); 2414 map_rx_inter_err: 2415 (void)hns3vf_do_stop(hns); 2416 hw->adapter_state = HNS3_NIC_CONFIGURED; 2417 rte_spinlock_unlock(&hw->lock); 2418 2419 return ret; 2420 } 2421 2422 static bool 2423 is_vf_reset_done(struct hns3_hw *hw) 2424 { 2425 #define HNS3_FUN_RST_ING_BITS \ 2426 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \ 2427 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \ 2428 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \ 2429 BIT(HNS3_VECTOR0_FUNCRESET_INT_B)) 2430 2431 uint32_t val; 2432 2433 if (hw->reset.level == HNS3_VF_RESET) { 2434 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 2435 if (val & HNS3_VF_RST_ING_BIT) 2436 return false; 2437 } else { 2438 val = hns3_read_dev(hw, HNS3_FUN_RST_ING); 2439 if (val & HNS3_FUN_RST_ING_BITS) 2440 return false; 2441 } 2442 return true; 2443 } 2444 2445 bool 2446 hns3vf_is_reset_pending(struct hns3_adapter *hns) 2447 { 2448 struct hns3_hw *hw = &hns->hw; 2449 enum hns3_reset_level reset; 2450 2451 /* 2452 * According to the protocol of PCIe, FLR to a PF device resets the PF 2453 * state as well as the SR-IOV extended capability including VF Enable 2454 * which means that VFs no longer exist. 2455 * 2456 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device 2457 * is in FLR stage, the register state of VF device is not reliable, 2458 * so register states detection can not be carried out. In this case, 2459 * we just ignore the register states and return false to indicate that 2460 * there are no other reset states that need to be processed by driver. 2461 */ 2462 if (hw->reset.level == HNS3_VF_FULL_RESET) 2463 return false; 2464 2465 /* Check the registers to confirm whether there is reset pending */ 2466 hns3vf_check_event_cause(hns, NULL); 2467 reset = hns3vf_get_reset_level(hw, &hw->reset.pending); 2468 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 2469 hns3_warn(hw, "High level reset %d is pending", reset); 2470 return true; 2471 } 2472 return false; 2473 } 2474 2475 static int 2476 hns3vf_wait_hardware_ready(struct hns3_adapter *hns) 2477 { 2478 struct hns3_hw *hw = &hns->hw; 2479 struct hns3_wait_data *wait_data = hw->reset.wait_data; 2480 struct timeval tv; 2481 2482 if (wait_data->result == HNS3_WAIT_SUCCESS) { 2483 /* 2484 * After vf reset is ready, the PF may not have completed 2485 * the reset processing. The vf sending mbox to PF may fail 2486 * during the pf reset, so it is better to add extra delay. 2487 */ 2488 if (hw->reset.level == HNS3_VF_FUNC_RESET || 2489 hw->reset.level == HNS3_FLR_RESET) 2490 return 0; 2491 /* Reset retry process, no need to add extra delay. */ 2492 if (hw->reset.attempts) 2493 return 0; 2494 if (wait_data->check_completion == NULL) 2495 return 0; 2496 2497 wait_data->check_completion = NULL; 2498 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC; 2499 wait_data->count = 1; 2500 wait_data->result = HNS3_WAIT_REQUEST; 2501 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, 2502 wait_data); 2503 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); 2504 return -EAGAIN; 2505 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 2506 gettimeofday(&tv, NULL); 2507 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 2508 tv.tv_sec, tv.tv_usec); 2509 return -ETIME; 2510 } else if (wait_data->result == HNS3_WAIT_REQUEST) 2511 return -EAGAIN; 2512 2513 wait_data->hns = hns; 2514 wait_data->check_completion = is_vf_reset_done; 2515 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT * 2516 HNS3VF_RESET_WAIT_MS + get_timeofday_ms(); 2517 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC; 2518 wait_data->count = HNS3VF_RESET_WAIT_CNT; 2519 wait_data->result = HNS3_WAIT_REQUEST; 2520 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 2521 return -EAGAIN; 2522 } 2523 2524 static int 2525 hns3vf_prepare_reset(struct hns3_adapter *hns) 2526 { 2527 struct hns3_hw *hw = &hns->hw; 2528 int ret; 2529 2530 if (hw->reset.level == HNS3_VF_FUNC_RESET) { 2531 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL, 2532 0, true, NULL, 0); 2533 if (ret) 2534 return ret; 2535 } 2536 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 2537 2538 return 0; 2539 } 2540 2541 static int 2542 hns3vf_stop_service(struct hns3_adapter *hns) 2543 { 2544 struct hns3_hw *hw = &hns->hw; 2545 struct rte_eth_dev *eth_dev; 2546 2547 eth_dev = &rte_eth_devices[hw->data->port_id]; 2548 if (hw->adapter_state == HNS3_NIC_STARTED) { 2549 /* 2550 * Make sure call update link status before hns3vf_stop_poll_job 2551 * because update link status depend on polling job exist. 2552 */ 2553 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed, 2554 hw->mac.link_duplex); 2555 hns3vf_stop_poll_job(eth_dev); 2556 } 2557 hw->mac.link_status = ETH_LINK_DOWN; 2558 2559 hns3_set_rxtx_function(eth_dev); 2560 rte_wmb(); 2561 /* Disable datapath on secondary process. */ 2562 hns3_mp_req_stop_rxtx(eth_dev); 2563 rte_delay_ms(hw->tqps_num); 2564 2565 rte_spinlock_lock(&hw->lock); 2566 if (hw->adapter_state == HNS3_NIC_STARTED || 2567 hw->adapter_state == HNS3_NIC_STOPPING) { 2568 hns3_enable_all_queues(hw, false); 2569 hns3vf_do_stop(hns); 2570 hw->reset.mbuf_deferred_free = true; 2571 } else 2572 hw->reset.mbuf_deferred_free = false; 2573 2574 /* 2575 * It is cumbersome for hardware to pick-and-choose entries for deletion 2576 * from table space. Hence, for function reset software intervention is 2577 * required to delete the entries. 2578 */ 2579 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 2580 hns3vf_configure_all_mc_mac_addr(hns, true); 2581 rte_spinlock_unlock(&hw->lock); 2582 2583 return 0; 2584 } 2585 2586 static int 2587 hns3vf_start_service(struct hns3_adapter *hns) 2588 { 2589 struct hns3_hw *hw = &hns->hw; 2590 struct rte_eth_dev *eth_dev; 2591 2592 eth_dev = &rte_eth_devices[hw->data->port_id]; 2593 hns3_set_rxtx_function(eth_dev); 2594 hns3_mp_req_start_rxtx(eth_dev); 2595 if (hw->adapter_state == HNS3_NIC_STARTED) { 2596 hns3vf_start_poll_job(eth_dev); 2597 2598 /* Enable interrupt of all rx queues before enabling queues */ 2599 hns3_dev_all_rx_queue_intr_enable(hw, true); 2600 /* 2601 * Enable state of each rxq and txq will be recovered after 2602 * reset, so we need to restore them before enable all tqps; 2603 */ 2604 hns3_restore_tqp_enable_state(hw); 2605 /* 2606 * When finished the initialization, enable queues to receive 2607 * and transmit packets. 2608 */ 2609 hns3_enable_all_queues(hw, true); 2610 } 2611 2612 return 0; 2613 } 2614 2615 static int 2616 hns3vf_check_default_mac_change(struct hns3_hw *hw) 2617 { 2618 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2619 struct rte_ether_addr *hw_mac; 2620 int ret; 2621 2622 /* 2623 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2624 * on the host by "ip link set ..." command. If the hns3 PF kernel 2625 * ethdev driver sets the MAC address for VF device after the 2626 * initialization of the related VF device, the PF driver will notify 2627 * VF driver to reset VF device to make the new MAC address effective 2628 * immediately. The hns3 VF PMD driver should check whether the MAC 2629 * address has been changed by the PF kernel ethdev driver, if changed 2630 * VF driver should configure hardware using the new MAC address in the 2631 * recovering hardware configuration stage of the reset process. 2632 */ 2633 ret = hns3vf_get_host_mac_addr(hw); 2634 if (ret) 2635 return ret; 2636 2637 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr; 2638 ret = rte_is_zero_ether_addr(hw_mac); 2639 if (ret) { 2640 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac); 2641 } else { 2642 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac); 2643 if (!ret) { 2644 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]); 2645 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2646 &hw->data->mac_addrs[0]); 2647 hns3_warn(hw, "Default MAC address has been changed to:" 2648 " %s by the host PF kernel ethdev driver", 2649 mac_str); 2650 } 2651 } 2652 2653 return 0; 2654 } 2655 2656 static int 2657 hns3vf_restore_conf(struct hns3_adapter *hns) 2658 { 2659 struct hns3_hw *hw = &hns->hw; 2660 int ret; 2661 2662 ret = hns3vf_check_default_mac_change(hw); 2663 if (ret) 2664 return ret; 2665 2666 ret = hns3vf_configure_mac_addr(hns, false); 2667 if (ret) 2668 return ret; 2669 2670 ret = hns3vf_configure_all_mc_mac_addr(hns, false); 2671 if (ret) 2672 goto err_mc_mac; 2673 2674 ret = hns3vf_restore_promisc(hns); 2675 if (ret) 2676 goto err_vlan_table; 2677 2678 ret = hns3vf_restore_vlan_conf(hns); 2679 if (ret) 2680 goto err_vlan_table; 2681 2682 ret = hns3vf_get_port_base_vlan_filter_state(hw); 2683 if (ret) 2684 goto err_vlan_table; 2685 2686 ret = hns3vf_restore_rx_interrupt(hw); 2687 if (ret) 2688 goto err_vlan_table; 2689 2690 ret = hns3_restore_gro_conf(hw); 2691 if (ret) 2692 goto err_vlan_table; 2693 2694 if (hw->adapter_state == HNS3_NIC_STARTED) { 2695 ret = hns3vf_do_start(hns, false); 2696 if (ret) 2697 goto err_vlan_table; 2698 hns3_info(hw, "hns3vf dev restart successful!"); 2699 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 2700 hw->adapter_state = HNS3_NIC_CONFIGURED; 2701 return 0; 2702 2703 err_vlan_table: 2704 hns3vf_configure_all_mc_mac_addr(hns, true); 2705 err_mc_mac: 2706 hns3vf_configure_mac_addr(hns, true); 2707 return ret; 2708 } 2709 2710 static enum hns3_reset_level 2711 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels) 2712 { 2713 enum hns3_reset_level reset_level; 2714 2715 /* return the highest priority reset level amongst all */ 2716 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels)) 2717 reset_level = HNS3_VF_RESET; 2718 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels)) 2719 reset_level = HNS3_VF_FULL_RESET; 2720 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels)) 2721 reset_level = HNS3_VF_PF_FUNC_RESET; 2722 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels)) 2723 reset_level = HNS3_VF_FUNC_RESET; 2724 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 2725 reset_level = HNS3_FLR_RESET; 2726 else 2727 reset_level = HNS3_NONE_RESET; 2728 2729 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 2730 return HNS3_NONE_RESET; 2731 2732 return reset_level; 2733 } 2734 2735 static void 2736 hns3vf_reset_service(void *param) 2737 { 2738 struct hns3_adapter *hns = (struct hns3_adapter *)param; 2739 struct hns3_hw *hw = &hns->hw; 2740 enum hns3_reset_level reset_level; 2741 struct timeval tv_delta; 2742 struct timeval tv_start; 2743 struct timeval tv; 2744 uint64_t msec; 2745 2746 /* 2747 * The interrupt is not triggered within the delay time. 2748 * The interrupt may have been lost. It is necessary to handle 2749 * the interrupt to recover from the error. 2750 */ 2751 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2752 SCHEDULE_DEFERRED) { 2753 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 2754 __ATOMIC_RELAXED); 2755 hns3_err(hw, "Handling interrupts in delayed tasks"); 2756 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 2757 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2758 if (reset_level == HNS3_NONE_RESET) { 2759 hns3_err(hw, "No reset level is set, try global reset"); 2760 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 2761 } 2762 } 2763 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 2764 2765 /* 2766 * Hardware reset has been notified, we now have to poll & check if 2767 * hardware has actually completed the reset sequence. 2768 */ 2769 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2770 if (reset_level != HNS3_NONE_RESET) { 2771 gettimeofday(&tv_start, NULL); 2772 hns3_reset_process(hns, reset_level); 2773 gettimeofday(&tv, NULL); 2774 timersub(&tv, &tv_start, &tv_delta); 2775 msec = tv_delta.tv_sec * MSEC_PER_SEC + 2776 tv_delta.tv_usec / USEC_PER_MSEC; 2777 if (msec > HNS3_RESET_PROCESS_MS) 2778 hns3_err(hw, "%d handle long time delta %" PRIx64 2779 " ms time=%ld.%.6ld", 2780 hw->reset.level, msec, tv.tv_sec, tv.tv_usec); 2781 } 2782 } 2783 2784 static int 2785 hns3vf_reinit_dev(struct hns3_adapter *hns) 2786 { 2787 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id]; 2788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2789 struct hns3_hw *hw = &hns->hw; 2790 int ret; 2791 2792 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2793 rte_intr_disable(&pci_dev->intr_handle); 2794 ret = hns3vf_set_bus_master(pci_dev, true); 2795 if (ret < 0) { 2796 hns3_err(hw, "failed to set pci bus, ret = %d", ret); 2797 return ret; 2798 } 2799 } 2800 2801 /* Firmware command initialize */ 2802 ret = hns3_cmd_init(hw); 2803 if (ret) { 2804 hns3_err(hw, "Failed to init cmd: %d", ret); 2805 return ret; 2806 } 2807 2808 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2809 /* 2810 * UIO enables msix by writing the pcie configuration space 2811 * vfio_pci enables msix in rte_intr_enable. 2812 */ 2813 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO || 2814 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) { 2815 if (hns3vf_enable_msix(pci_dev, true)) 2816 hns3_err(hw, "Failed to enable msix"); 2817 } 2818 2819 rte_intr_enable(&pci_dev->intr_handle); 2820 } 2821 2822 ret = hns3_reset_all_tqps(hns); 2823 if (ret) { 2824 hns3_err(hw, "Failed to reset all queues: %d", ret); 2825 return ret; 2826 } 2827 2828 ret = hns3vf_init_hardware(hns); 2829 if (ret) { 2830 hns3_err(hw, "Failed to init hardware: %d", ret); 2831 return ret; 2832 } 2833 2834 return 0; 2835 } 2836 2837 static const struct eth_dev_ops hns3vf_eth_dev_ops = { 2838 .dev_configure = hns3vf_dev_configure, 2839 .dev_start = hns3vf_dev_start, 2840 .dev_stop = hns3vf_dev_stop, 2841 .dev_close = hns3vf_dev_close, 2842 .mtu_set = hns3vf_dev_mtu_set, 2843 .promiscuous_enable = hns3vf_dev_promiscuous_enable, 2844 .promiscuous_disable = hns3vf_dev_promiscuous_disable, 2845 .allmulticast_enable = hns3vf_dev_allmulticast_enable, 2846 .allmulticast_disable = hns3vf_dev_allmulticast_disable, 2847 .stats_get = hns3_stats_get, 2848 .stats_reset = hns3_stats_reset, 2849 .xstats_get = hns3_dev_xstats_get, 2850 .xstats_get_names = hns3_dev_xstats_get_names, 2851 .xstats_reset = hns3_dev_xstats_reset, 2852 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 2853 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 2854 .dev_infos_get = hns3vf_dev_infos_get, 2855 .fw_version_get = hns3vf_fw_version_get, 2856 .rx_queue_setup = hns3_rx_queue_setup, 2857 .tx_queue_setup = hns3_tx_queue_setup, 2858 .rx_queue_release = hns3_dev_rx_queue_release, 2859 .tx_queue_release = hns3_dev_tx_queue_release, 2860 .rx_queue_start = hns3_dev_rx_queue_start, 2861 .rx_queue_stop = hns3_dev_rx_queue_stop, 2862 .tx_queue_start = hns3_dev_tx_queue_start, 2863 .tx_queue_stop = hns3_dev_tx_queue_stop, 2864 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 2865 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 2866 .rxq_info_get = hns3_rxq_info_get, 2867 .txq_info_get = hns3_txq_info_get, 2868 .rx_burst_mode_get = hns3_rx_burst_mode_get, 2869 .tx_burst_mode_get = hns3_tx_burst_mode_get, 2870 .mac_addr_add = hns3vf_add_mac_addr, 2871 .mac_addr_remove = hns3vf_remove_mac_addr, 2872 .mac_addr_set = hns3vf_set_default_mac_addr, 2873 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list, 2874 .link_update = hns3vf_dev_link_update, 2875 .rss_hash_update = hns3_dev_rss_hash_update, 2876 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 2877 .reta_update = hns3_dev_rss_reta_update, 2878 .reta_query = hns3_dev_rss_reta_query, 2879 .flow_ops_get = hns3_dev_flow_ops_get, 2880 .vlan_filter_set = hns3vf_vlan_filter_set, 2881 .vlan_offload_set = hns3vf_vlan_offload_set, 2882 .get_reg = hns3_get_regs, 2883 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 2884 .tx_done_cleanup = hns3_tx_done_cleanup, 2885 }; 2886 2887 static const struct hns3_reset_ops hns3vf_reset_ops = { 2888 .reset_service = hns3vf_reset_service, 2889 .stop_service = hns3vf_stop_service, 2890 .prepare_reset = hns3vf_prepare_reset, 2891 .wait_hardware_ready = hns3vf_wait_hardware_ready, 2892 .reinit_dev = hns3vf_reinit_dev, 2893 .restore_conf = hns3vf_restore_conf, 2894 .start_service = hns3vf_start_service, 2895 }; 2896 2897 static int 2898 hns3vf_dev_init(struct rte_eth_dev *eth_dev) 2899 { 2900 struct hns3_adapter *hns = eth_dev->data->dev_private; 2901 struct hns3_hw *hw = &hns->hw; 2902 int ret; 2903 2904 PMD_INIT_FUNC_TRACE(); 2905 2906 eth_dev->process_private = (struct hns3_process_private *) 2907 rte_zmalloc_socket("hns3_filter_list", 2908 sizeof(struct hns3_process_private), 2909 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 2910 if (eth_dev->process_private == NULL) { 2911 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 2912 return -ENOMEM; 2913 } 2914 2915 /* initialize flow filter lists */ 2916 hns3_filterlist_init(eth_dev); 2917 2918 hns3_set_rxtx_function(eth_dev); 2919 eth_dev->dev_ops = &hns3vf_eth_dev_ops; 2920 eth_dev->rx_queue_count = hns3_rx_queue_count; 2921 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2922 ret = hns3_mp_init_secondary(); 2923 if (ret) { 2924 PMD_INIT_LOG(ERR, "Failed to init for secondary " 2925 "process, ret = %d", ret); 2926 goto err_mp_init_secondary; 2927 } 2928 2929 hw->secondary_cnt++; 2930 return 0; 2931 } 2932 2933 ret = hns3_mp_init_primary(); 2934 if (ret) { 2935 PMD_INIT_LOG(ERR, 2936 "Failed to init for primary process, ret = %d", 2937 ret); 2938 goto err_mp_init_primary; 2939 } 2940 2941 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 2942 hns->is_vf = true; 2943 hw->data = eth_dev->data; 2944 hns3_parse_devargs(eth_dev); 2945 2946 ret = hns3_reset_init(hw); 2947 if (ret) 2948 goto err_init_reset; 2949 hw->reset.ops = &hns3vf_reset_ops; 2950 2951 ret = hns3vf_init_vf(eth_dev); 2952 if (ret) { 2953 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret); 2954 goto err_init_vf; 2955 } 2956 2957 /* Allocate memory for storing MAC addresses */ 2958 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac", 2959 sizeof(struct rte_ether_addr) * 2960 HNS3_VF_UC_MACADDR_NUM, 0); 2961 if (eth_dev->data->mac_addrs == NULL) { 2962 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 2963 "to store MAC addresses", 2964 sizeof(struct rte_ether_addr) * 2965 HNS3_VF_UC_MACADDR_NUM); 2966 ret = -ENOMEM; 2967 goto err_rte_zmalloc; 2968 } 2969 2970 /* 2971 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2972 * on the host by "ip link set ..." command. To avoid some incorrect 2973 * scenes, for example, hns3 VF PMD driver fails to receive and send 2974 * packets after user configure the MAC address by using the 2975 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC 2976 * address strategy as the hns3 kernel ethdev driver in the 2977 * initialization. If user configure a MAC address by the ip command 2978 * for VF device, then hns3 VF PMD driver will start with it, otherwise 2979 * start with a random MAC address in the initialization. 2980 */ 2981 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr)) 2982 rte_eth_random_addr(hw->mac.mac_addr); 2983 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 2984 ð_dev->data->mac_addrs[0]); 2985 2986 hw->adapter_state = HNS3_NIC_INITIALIZED; 2987 2988 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2989 SCHEDULE_PENDING) { 2990 hns3_err(hw, "Reschedule reset service after dev_init"); 2991 hns3_schedule_reset(hns); 2992 } else { 2993 /* IMP will wait ready flag before reset */ 2994 hns3_notify_reset_ready(hw, false); 2995 } 2996 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 2997 eth_dev); 2998 return 0; 2999 3000 err_rte_zmalloc: 3001 hns3vf_uninit_vf(eth_dev); 3002 3003 err_init_vf: 3004 rte_free(hw->reset.wait_data); 3005 3006 err_init_reset: 3007 hns3_mp_uninit_primary(); 3008 3009 err_mp_init_primary: 3010 err_mp_init_secondary: 3011 eth_dev->dev_ops = NULL; 3012 eth_dev->rx_pkt_burst = NULL; 3013 eth_dev->rx_descriptor_status = NULL; 3014 eth_dev->tx_pkt_burst = NULL; 3015 eth_dev->tx_pkt_prepare = NULL; 3016 eth_dev->tx_descriptor_status = NULL; 3017 rte_free(eth_dev->process_private); 3018 eth_dev->process_private = NULL; 3019 3020 return ret; 3021 } 3022 3023 static int 3024 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev) 3025 { 3026 struct hns3_adapter *hns = eth_dev->data->dev_private; 3027 struct hns3_hw *hw = &hns->hw; 3028 3029 PMD_INIT_FUNC_TRACE(); 3030 3031 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 3032 rte_free(eth_dev->process_private); 3033 eth_dev->process_private = NULL; 3034 return 0; 3035 } 3036 3037 if (hw->adapter_state < HNS3_NIC_CLOSING) 3038 hns3vf_dev_close(eth_dev); 3039 3040 hw->adapter_state = HNS3_NIC_REMOVED; 3041 return 0; 3042 } 3043 3044 static int 3045 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3046 struct rte_pci_device *pci_dev) 3047 { 3048 return rte_eth_dev_pci_generic_probe(pci_dev, 3049 sizeof(struct hns3_adapter), 3050 hns3vf_dev_init); 3051 } 3052 3053 static int 3054 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev) 3055 { 3056 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit); 3057 } 3058 3059 static const struct rte_pci_id pci_id_hns3vf_map[] = { 3060 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) }, 3061 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) }, 3062 { .vendor_id = 0, }, /* sentinel */ 3063 }; 3064 3065 static struct rte_pci_driver rte_hns3vf_pmd = { 3066 .id_table = pci_id_hns3vf_map, 3067 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3068 .probe = eth_hns3vf_pci_probe, 3069 .remove = eth_hns3vf_pci_remove, 3070 }; 3071 3072 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); 3073 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); 3074 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); 3075 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf, 3076 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 3077 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); 3078