1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <linux/pci_regs.h> 6 #include <rte_alarm.h> 7 #include <rte_ethdev_pci.h> 8 #include <rte_io.h> 9 #include <rte_pci.h> 10 #include <rte_vfio.h> 11 12 #include "hns3_ethdev.h" 13 #include "hns3_logs.h" 14 #include "hns3_rxtx.h" 15 #include "hns3_regs.h" 16 #include "hns3_intr.h" 17 #include "hns3_dcb.h" 18 #include "hns3_mp.h" 19 20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */ 21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */ 22 23 #define HNS3VF_RESET_WAIT_MS 20 24 #define HNS3VF_RESET_WAIT_CNT 2000 25 26 /* Reset related Registers */ 27 #define HNS3_GLOBAL_RESET_BIT 0 28 #define HNS3_CORE_RESET_BIT 1 29 #define HNS3_IMP_RESET_BIT 2 30 #define HNS3_FUN_RST_ING_B 0 31 32 enum hns3vf_evt_cause { 33 HNS3VF_VECTOR0_EVENT_RST, 34 HNS3VF_VECTOR0_EVENT_MBX, 35 HNS3VF_VECTOR0_EVENT_OTHER, 36 }; 37 38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw, 39 uint64_t *levels); 40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev); 42 43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 44 struct rte_ether_addr *mac_addr); 45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 46 struct rte_ether_addr *mac_addr); 47 /* set PCI bus mastering */ 48 static int 49 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) 50 { 51 uint16_t reg; 52 int ret; 53 54 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); 55 if (ret < 0) { 56 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 57 PCI_COMMAND); 58 return ret; 59 } 60 61 if (op) 62 /* set the master bit */ 63 reg |= PCI_COMMAND_MASTER; 64 else 65 reg &= ~(PCI_COMMAND_MASTER); 66 67 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); 68 } 69 70 /** 71 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list 72 * @cap: the capability 73 * 74 * Return the address of the given capability within the PCI capability list. 75 */ 76 static int 77 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) 78 { 79 #define MAX_PCIE_CAPABILITY 48 80 uint16_t status; 81 uint8_t pos; 82 uint8_t id; 83 int ttl; 84 int ret; 85 86 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); 87 if (ret < 0) { 88 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS); 89 return 0; 90 } 91 92 if (!(status & PCI_STATUS_CAP_LIST)) 93 return 0; 94 95 ttl = MAX_PCIE_CAPABILITY; 96 ret = rte_pci_read_config(device, &pos, sizeof(pos), 97 PCI_CAPABILITY_LIST); 98 if (ret < 0) { 99 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 100 PCI_CAPABILITY_LIST); 101 return 0; 102 } 103 104 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { 105 ret = rte_pci_read_config(device, &id, sizeof(id), 106 (pos + PCI_CAP_LIST_ID)); 107 if (ret < 0) { 108 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 109 (pos + PCI_CAP_LIST_ID)); 110 break; 111 } 112 113 if (id == 0xFF) 114 break; 115 116 if (id == cap) 117 return (int)pos; 118 119 ret = rte_pci_read_config(device, &pos, sizeof(pos), 120 (pos + PCI_CAP_LIST_NEXT)); 121 if (ret < 0) { 122 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 123 (pos + PCI_CAP_LIST_NEXT)); 124 break; 125 } 126 } 127 return 0; 128 } 129 130 static int 131 hns3vf_enable_msix(const struct rte_pci_device *device, bool op) 132 { 133 uint16_t control; 134 int pos; 135 int ret; 136 137 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); 138 if (pos) { 139 ret = rte_pci_read_config(device, &control, sizeof(control), 140 (pos + PCI_MSIX_FLAGS)); 141 if (ret < 0) { 142 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 143 (pos + PCI_MSIX_FLAGS)); 144 return -ENXIO; 145 } 146 147 if (op) 148 control |= PCI_MSIX_FLAGS_ENABLE; 149 else 150 control &= ~PCI_MSIX_FLAGS_ENABLE; 151 ret = rte_pci_write_config(device, &control, sizeof(control), 152 (pos + PCI_MSIX_FLAGS)); 153 if (ret < 0) { 154 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x", 155 (pos + PCI_MSIX_FLAGS)); 156 } 157 return 0; 158 } 159 return -ENXIO; 160 } 161 162 static int 163 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 164 { 165 /* mac address was checked by upper level interface */ 166 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 167 int ret; 168 169 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 170 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes, 171 RTE_ETHER_ADDR_LEN, false, NULL, 0); 172 if (ret) { 173 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 174 mac_addr); 175 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 176 mac_str, ret); 177 } 178 return ret; 179 } 180 181 static int 182 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 183 { 184 /* mac address was checked by upper level interface */ 185 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 186 int ret; 187 188 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 189 HNS3_MBX_MAC_VLAN_UC_REMOVE, 190 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, 191 false, NULL, 0); 192 if (ret) { 193 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 194 mac_addr); 195 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 196 mac_str, ret); 197 } 198 return ret; 199 } 200 201 static int 202 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 203 { 204 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 205 struct rte_ether_addr *addr; 206 int ret; 207 int i; 208 209 for (i = 0; i < hw->mc_addrs_num; i++) { 210 addr = &hw->mc_addrs[i]; 211 /* Check if there are duplicate addresses */ 212 if (rte_is_same_ether_addr(addr, mac_addr)) { 213 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 214 addr); 215 hns3_err(hw, "failed to add mc mac addr, same addrs" 216 "(%s) is added by the set_mc_mac_addr_list " 217 "API", mac_str); 218 return -EINVAL; 219 } 220 } 221 222 ret = hns3vf_add_mc_mac_addr(hw, mac_addr); 223 if (ret) { 224 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 225 mac_addr); 226 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 227 mac_str, ret); 228 } 229 return ret; 230 } 231 232 static int 233 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 234 __rte_unused uint32_t idx, 235 __rte_unused uint32_t pool) 236 { 237 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 238 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 239 int ret; 240 241 rte_spinlock_lock(&hw->lock); 242 243 /* 244 * In hns3 network engine adding UC and MC mac address with different 245 * commands with firmware. We need to determine whether the input 246 * address is a UC or a MC address to call different commands. 247 * By the way, it is recommended calling the API function named 248 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 249 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 250 * may affect the specifications of UC mac addresses. 251 */ 252 if (rte_is_multicast_ether_addr(mac_addr)) 253 ret = hns3vf_add_mc_addr_common(hw, mac_addr); 254 else 255 ret = hns3vf_add_uc_mac_addr(hw, mac_addr); 256 257 rte_spinlock_unlock(&hw->lock); 258 if (ret) { 259 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 260 mac_addr); 261 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 262 ret); 263 } 264 265 return ret; 266 } 267 268 static void 269 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 270 { 271 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 272 /* index will be checked by upper level rte interface */ 273 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 274 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 275 int ret; 276 277 rte_spinlock_lock(&hw->lock); 278 279 if (rte_is_multicast_ether_addr(mac_addr)) 280 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr); 281 else 282 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr); 283 284 rte_spinlock_unlock(&hw->lock); 285 if (ret) { 286 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 287 mac_addr); 288 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", 289 mac_str, ret); 290 } 291 } 292 293 static int 294 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev, 295 struct rte_ether_addr *mac_addr) 296 { 297 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2) 298 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 299 struct rte_ether_addr *old_addr; 300 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */ 301 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 302 int ret; 303 304 /* 305 * It has been guaranteed that input parameter named mac_addr is valid 306 * address in the rte layer of DPDK framework. 307 */ 308 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 309 rte_spinlock_lock(&hw->lock); 310 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN); 311 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes, 312 RTE_ETHER_ADDR_LEN); 313 314 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 315 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes, 316 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0); 317 if (ret) { 318 /* 319 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev 320 * driver. When user has configured a MAC address for VF device 321 * by "ip link set ..." command based on the PF device, the hns3 322 * PF kernel ethdev driver does not allow VF driver to request 323 * reconfiguring a different default MAC address, and return 324 * -EPREM to VF driver through mailbox. 325 */ 326 if (ret == -EPERM) { 327 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 328 old_addr); 329 hns3_warn(hw, "Has permanet mac addr(%s) for vf", 330 mac_str); 331 } else { 332 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 333 mac_addr); 334 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", 335 mac_str, ret); 336 } 337 } 338 339 rte_ether_addr_copy(mac_addr, 340 (struct rte_ether_addr *)hw->mac.mac_addr); 341 rte_spinlock_unlock(&hw->lock); 342 343 return ret; 344 } 345 346 static int 347 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del) 348 { 349 struct hns3_hw *hw = &hns->hw; 350 struct rte_ether_addr *addr; 351 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 352 int err = 0; 353 int ret; 354 int i; 355 356 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) { 357 addr = &hw->data->mac_addrs[i]; 358 if (rte_is_zero_ether_addr(addr)) 359 continue; 360 if (rte_is_multicast_ether_addr(addr)) 361 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) : 362 hns3vf_add_mc_mac_addr(hw, addr); 363 else 364 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) : 365 hns3vf_add_uc_mac_addr(hw, addr); 366 367 if (ret) { 368 err = ret; 369 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 370 addr); 371 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 372 "ret = %d.", del ? "remove" : "restore", 373 mac_str, i, ret); 374 } 375 } 376 return err; 377 } 378 379 static int 380 hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 381 struct rte_ether_addr *mac_addr) 382 { 383 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 384 int ret; 385 386 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 387 HNS3_MBX_MAC_VLAN_MC_ADD, 388 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 389 NULL, 0); 390 if (ret) { 391 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 392 mac_addr); 393 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d", 394 mac_str, ret); 395 } 396 397 return ret; 398 } 399 400 static int 401 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 402 struct rte_ether_addr *mac_addr) 403 { 404 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 405 int ret; 406 407 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 408 HNS3_MBX_MAC_VLAN_MC_REMOVE, 409 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 410 NULL, 0); 411 if (ret) { 412 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 413 mac_addr); 414 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d", 415 mac_str, ret); 416 } 417 418 return ret; 419 } 420 421 static int 422 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw, 423 struct rte_ether_addr *mc_addr_set, 424 uint32_t nb_mc_addr) 425 { 426 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 427 struct rte_ether_addr *addr; 428 uint32_t i; 429 uint32_t j; 430 431 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 432 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 433 "invalid. valid range: 0~%d", 434 nb_mc_addr, HNS3_MC_MACADDR_NUM); 435 return -EINVAL; 436 } 437 438 /* Check if input mac addresses are valid */ 439 for (i = 0; i < nb_mc_addr; i++) { 440 addr = &mc_addr_set[i]; 441 if (!rte_is_multicast_ether_addr(addr)) { 442 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 443 addr); 444 hns3_err(hw, 445 "failed to set mc mac addr, addr(%s) invalid.", 446 mac_str); 447 return -EINVAL; 448 } 449 450 /* Check if there are duplicate addresses */ 451 for (j = i + 1; j < nb_mc_addr; j++) { 452 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 453 hns3_ether_format_addr(mac_str, 454 RTE_ETHER_ADDR_FMT_SIZE, 455 addr); 456 hns3_err(hw, "failed to set mc mac addr, " 457 "addrs invalid. two same addrs(%s).", 458 mac_str); 459 return -EINVAL; 460 } 461 } 462 463 /* 464 * Check if there are duplicate addresses between mac_addrs 465 * and mc_addr_set 466 */ 467 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) { 468 if (rte_is_same_ether_addr(addr, 469 &hw->data->mac_addrs[j])) { 470 hns3_ether_format_addr(mac_str, 471 RTE_ETHER_ADDR_FMT_SIZE, 472 addr); 473 hns3_err(hw, "failed to set mc mac addr, " 474 "addrs invalid. addrs(%s) has already " 475 "configured in mac_addr add API", 476 mac_str); 477 return -EINVAL; 478 } 479 } 480 } 481 482 return 0; 483 } 484 485 static int 486 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev, 487 struct rte_ether_addr *mc_addr_set, 488 uint32_t nb_mc_addr) 489 { 490 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 491 struct rte_ether_addr *addr; 492 int cur_addr_num; 493 int set_addr_num; 494 int num; 495 int ret; 496 int i; 497 498 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 499 if (ret) 500 return ret; 501 502 rte_spinlock_lock(&hw->lock); 503 cur_addr_num = hw->mc_addrs_num; 504 for (i = 0; i < cur_addr_num; i++) { 505 num = cur_addr_num - i - 1; 506 addr = &hw->mc_addrs[num]; 507 ret = hns3vf_remove_mc_mac_addr(hw, addr); 508 if (ret) { 509 rte_spinlock_unlock(&hw->lock); 510 return ret; 511 } 512 513 hw->mc_addrs_num--; 514 } 515 516 set_addr_num = (int)nb_mc_addr; 517 for (i = 0; i < set_addr_num; i++) { 518 addr = &mc_addr_set[i]; 519 ret = hns3vf_add_mc_mac_addr(hw, addr); 520 if (ret) { 521 rte_spinlock_unlock(&hw->lock); 522 return ret; 523 } 524 525 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]); 526 hw->mc_addrs_num++; 527 } 528 rte_spinlock_unlock(&hw->lock); 529 530 return 0; 531 } 532 533 static int 534 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 535 { 536 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 537 struct hns3_hw *hw = &hns->hw; 538 struct rte_ether_addr *addr; 539 int err = 0; 540 int ret; 541 int i; 542 543 for (i = 0; i < hw->mc_addrs_num; i++) { 544 addr = &hw->mc_addrs[i]; 545 if (!rte_is_multicast_ether_addr(addr)) 546 continue; 547 if (del) 548 ret = hns3vf_remove_mc_mac_addr(hw, addr); 549 else 550 ret = hns3vf_add_mc_mac_addr(hw, addr); 551 if (ret) { 552 err = ret; 553 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 554 addr); 555 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d", 556 del ? "Remove" : "Restore", mac_str, ret); 557 } 558 } 559 return err; 560 } 561 562 static int 563 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc, 564 bool en_uc_pmc, bool en_mc_pmc) 565 { 566 struct hns3_mbx_vf_to_pf_cmd *req; 567 struct hns3_cmd_desc desc; 568 int ret; 569 570 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data; 571 572 /* 573 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver, 574 * so there are some features for promiscuous/allmulticast mode in hns3 575 * VF PMD driver as below: 576 * 1. The promiscuous/allmulticast mode can be configured successfully 577 * only based on the trusted VF device. If based on the non trusted 578 * VF device, configuring promiscuous/allmulticast mode will fail. 579 * The hns3 VF device can be confiruged as trusted device by hns3 PF 580 * kernel ethdev driver on the host by the following command: 581 * "ip link set <eth num> vf <vf id> turst on" 582 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD 583 * driver can receive the ingress and outgoing traffic. In the words, 584 * all the ingress packets, all the packets sent from the PF and 585 * other VFs on the same physical port. 586 * 3. Note: Because of the hardware constraints, By default vlan filter 587 * is enabled and couldn't be turned off based on VF device, so vlan 588 * filter is still effective even in promiscuous mode. If upper 589 * applications don't call rte_eth_dev_vlan_filter API function to 590 * set vlan based on VF device, hns3 VF PMD driver will can't receive 591 * the packets with vlan tag in promiscuoue mode. 592 */ 593 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false); 594 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE; 595 req->msg[1] = en_bc_pmc ? 1 : 0; 596 req->msg[2] = en_uc_pmc ? 1 : 0; 597 req->msg[3] = en_mc_pmc ? 1 : 0; 598 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0; 599 600 ret = hns3_cmd_send(hw, &desc, 1); 601 if (ret) 602 hns3_err(hw, "Set promisc mode fail, ret = %d", ret); 603 604 return ret; 605 } 606 607 static int 608 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev) 609 { 610 struct hns3_adapter *hns = dev->data->dev_private; 611 struct hns3_hw *hw = &hns->hw; 612 int ret; 613 614 ret = hns3vf_set_promisc_mode(hw, true, true, true); 615 if (ret) 616 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d", 617 ret); 618 return ret; 619 } 620 621 static int 622 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev) 623 { 624 bool allmulti = dev->data->all_multicast ? true : false; 625 struct hns3_adapter *hns = dev->data->dev_private; 626 struct hns3_hw *hw = &hns->hw; 627 int ret; 628 629 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti); 630 if (ret) 631 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d", 632 ret); 633 return ret; 634 } 635 636 static int 637 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev) 638 { 639 struct hns3_adapter *hns = dev->data->dev_private; 640 struct hns3_hw *hw = &hns->hw; 641 int ret; 642 643 if (dev->data->promiscuous) 644 return 0; 645 646 ret = hns3vf_set_promisc_mode(hw, true, false, true); 647 if (ret) 648 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d", 649 ret); 650 return ret; 651 } 652 653 static int 654 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev) 655 { 656 struct hns3_adapter *hns = dev->data->dev_private; 657 struct hns3_hw *hw = &hns->hw; 658 int ret; 659 660 if (dev->data->promiscuous) 661 return 0; 662 663 ret = hns3vf_set_promisc_mode(hw, true, false, false); 664 if (ret) 665 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d", 666 ret); 667 return ret; 668 } 669 670 static int 671 hns3vf_restore_promisc(struct hns3_adapter *hns) 672 { 673 struct hns3_hw *hw = &hns->hw; 674 bool allmulti = hw->data->all_multicast ? true : false; 675 676 if (hw->data->promiscuous) 677 return hns3vf_set_promisc_mode(hw, true, true, true); 678 679 return hns3vf_set_promisc_mode(hw, true, false, allmulti); 680 } 681 682 static int 683 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, 684 bool mmap, enum hns3_ring_type queue_type, 685 uint16_t queue_id) 686 { 687 struct hns3_vf_bind_vector_msg bind_msg; 688 const char *op_str; 689 uint16_t code; 690 int ret; 691 692 memset(&bind_msg, 0, sizeof(bind_msg)); 693 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR : 694 HNS3_MBX_UNMAP_RING_TO_VECTOR; 695 bind_msg.vector_id = vector_id; 696 697 if (queue_type == HNS3_RING_TYPE_RX) 698 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX; 699 else 700 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX; 701 702 bind_msg.param[0].ring_type = queue_type; 703 bind_msg.ring_num = 1; 704 bind_msg.param[0].tqp_index = queue_id; 705 op_str = mmap ? "Map" : "Unmap"; 706 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg, 707 sizeof(bind_msg), false, NULL, 0); 708 if (ret) 709 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.", 710 op_str, queue_id, bind_msg.vector_id, ret); 711 712 return ret; 713 } 714 715 static int 716 hns3vf_init_ring_with_vector(struct hns3_hw *hw) 717 { 718 uint16_t vec; 719 int ret; 720 int i; 721 722 /* 723 * In hns3 network engine, vector 0 is always the misc interrupt of this 724 * function, vector 1~N can be used respectively for the queues of the 725 * function. Tx and Rx queues with the same number share the interrupt 726 * vector. In the initialization clearing the all hardware mapping 727 * relationship configurations between queues and interrupt vectors is 728 * needed, so some error caused by the residual configurations, such as 729 * the unexpected Tx interrupt, can be avoid. 730 */ 731 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 732 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 733 vec = vec - 1; /* the last interrupt is reserved */ 734 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 735 for (i = 0; i < hw->intr_tqps_num; i++) { 736 /* 737 * Set gap limiter/rate limiter/quanity limiter algorithm 738 * configuration for interrupt coalesce of queue's interrupt. 739 */ 740 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 741 HNS3_TQP_INTR_GL_DEFAULT); 742 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 743 HNS3_TQP_INTR_GL_DEFAULT); 744 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 745 /* 746 * QL(quantity limiter) is not used currently, just set 0 to 747 * close it. 748 */ 749 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 750 751 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 752 HNS3_RING_TYPE_TX, i); 753 if (ret) { 754 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with " 755 "vector: %u, ret=%d", i, vec, ret); 756 return ret; 757 } 758 759 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 760 HNS3_RING_TYPE_RX, i); 761 if (ret) { 762 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with " 763 "vector: %u, ret=%d", i, vec, ret); 764 return ret; 765 } 766 } 767 768 return 0; 769 } 770 771 static int 772 hns3vf_dev_configure(struct rte_eth_dev *dev) 773 { 774 struct hns3_adapter *hns = dev->data->dev_private; 775 struct hns3_hw *hw = &hns->hw; 776 struct hns3_rss_conf *rss_cfg = &hw->rss_info; 777 struct rte_eth_conf *conf = &dev->data->dev_conf; 778 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 779 uint16_t nb_rx_q = dev->data->nb_rx_queues; 780 uint16_t nb_tx_q = dev->data->nb_tx_queues; 781 struct rte_eth_rss_conf rss_conf; 782 uint16_t mtu; 783 bool gro_en; 784 int ret; 785 786 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 787 788 /* 789 * Some versions of hardware network engine does not support 790 * individually enable/disable/reset the Tx or Rx queue. These devices 791 * must enable/disable/reset Tx and Rx queues at the same time. When the 792 * numbers of Tx queues allocated by upper applications are not equal to 793 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 794 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 795 * work as usual. But these fake queues are imperceptible, and can not 796 * be used by upper applications. 797 */ 798 if (!hns3_dev_indep_txrx_supported(hw)) { 799 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 800 if (ret) { 801 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", 802 ret); 803 return ret; 804 } 805 } 806 807 hw->adapter_state = HNS3_NIC_CONFIGURING; 808 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 809 hns3_err(hw, "setting link speed/duplex not supported"); 810 ret = -EINVAL; 811 goto cfg_err; 812 } 813 814 /* When RSS is not configured, redirect the packet queue 0 */ 815 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 816 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 817 hw->rss_dis_flag = false; 818 rss_conf = conf->rx_adv_conf.rss_conf; 819 if (rss_conf.rss_key == NULL) { 820 rss_conf.rss_key = rss_cfg->key; 821 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE; 822 } 823 824 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 825 if (ret) 826 goto cfg_err; 827 } 828 829 /* 830 * If jumbo frames are enabled, MTU needs to be refreshed 831 * according to the maximum RX packet length. 832 */ 833 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 834 /* 835 * Security of max_rx_pkt_len is guaranteed in dpdk frame. 836 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it 837 * can safely assign to "uint16_t" type variable. 838 */ 839 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len); 840 ret = hns3vf_dev_mtu_set(dev, mtu); 841 if (ret) 842 goto cfg_err; 843 dev->data->mtu = mtu; 844 } 845 846 ret = hns3vf_dev_configure_vlan(dev); 847 if (ret) 848 goto cfg_err; 849 850 /* config hardware GRO */ 851 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 852 ret = hns3_config_gro(hw, gro_en); 853 if (ret) 854 goto cfg_err; 855 856 hns->rx_simple_allowed = true; 857 hns->rx_vec_allowed = true; 858 hns->tx_simple_allowed = true; 859 hns->tx_vec_allowed = true; 860 861 hns3_init_rx_ptype_tble(dev); 862 863 hw->adapter_state = HNS3_NIC_CONFIGURED; 864 return 0; 865 866 cfg_err: 867 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 868 hw->adapter_state = HNS3_NIC_INITIALIZED; 869 870 return ret; 871 } 872 873 static int 874 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu) 875 { 876 int ret; 877 878 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu, 879 sizeof(mtu), true, NULL, 0); 880 if (ret) 881 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret); 882 883 return ret; 884 } 885 886 static int 887 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 888 { 889 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 890 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 891 int ret; 892 893 /* 894 * The hns3 PF/VF devices on the same port share the hardware MTU 895 * configuration. Currently, we send mailbox to inform hns3 PF kernel 896 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD 897 * driver, there is no need to stop the port for hns3 VF device, and the 898 * MTU value issued by hns3 VF PMD driver must be less than or equal to 899 * PF's MTU. 900 */ 901 if (rte_atomic16_read(&hw->reset.resetting)) { 902 hns3_err(hw, "Failed to set mtu during resetting"); 903 return -EIO; 904 } 905 906 /* 907 * when Rx of scattered packets is off, we have some possibility of 908 * using vector Rx process function or simple Rx functions in hns3 PMD 909 * driver. If the input MTU is increased and the maximum length of 910 * received packets is greater than the length of a buffer for Rx 911 * packet, the hardware network engine needs to use multiple BDs and 912 * buffers to store these packets. This will cause problems when still 913 * using vector Rx process function or simple Rx function to receiving 914 * packets. So, when Rx of scattered packets is off and device is 915 * started, it is not permitted to increase MTU so that the maximum 916 * length of Rx packets is greater than Rx buffer length. 917 */ 918 if (dev->data->dev_started && !dev->data->scattered_rx && 919 frame_size > hw->rx_buf_len) { 920 hns3_err(hw, "failed to set mtu because current is " 921 "not scattered rx mode"); 922 return -EOPNOTSUPP; 923 } 924 925 rte_spinlock_lock(&hw->lock); 926 ret = hns3vf_config_mtu(hw, mtu); 927 if (ret) { 928 rte_spinlock_unlock(&hw->lock); 929 return ret; 930 } 931 if (frame_size > RTE_ETHER_MAX_LEN) 932 dev->data->dev_conf.rxmode.offloads |= 933 DEV_RX_OFFLOAD_JUMBO_FRAME; 934 else 935 dev->data->dev_conf.rxmode.offloads &= 936 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 937 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 938 rte_spinlock_unlock(&hw->lock); 939 940 return 0; 941 } 942 943 static int 944 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 945 { 946 struct hns3_adapter *hns = eth_dev->data->dev_private; 947 struct hns3_hw *hw = &hns->hw; 948 uint16_t q_num = hw->tqps_num; 949 950 /* 951 * In interrupt mode, 'max_rx_queues' is set based on the number of 952 * MSI-X interrupt resources of the hardware. 953 */ 954 if (hw->data->dev_conf.intr_conf.rxq == 1) 955 q_num = hw->intr_tqps_num; 956 957 info->max_rx_queues = q_num; 958 info->max_tx_queues = hw->tqps_num; 959 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 960 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 961 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; 962 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 963 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 964 965 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 966 DEV_RX_OFFLOAD_UDP_CKSUM | 967 DEV_RX_OFFLOAD_TCP_CKSUM | 968 DEV_RX_OFFLOAD_SCTP_CKSUM | 969 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 970 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 971 DEV_RX_OFFLOAD_SCATTER | 972 DEV_RX_OFFLOAD_VLAN_STRIP | 973 DEV_RX_OFFLOAD_VLAN_FILTER | 974 DEV_RX_OFFLOAD_JUMBO_FRAME | 975 DEV_RX_OFFLOAD_RSS_HASH | 976 DEV_RX_OFFLOAD_TCP_LRO); 977 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 978 DEV_TX_OFFLOAD_IPV4_CKSUM | 979 DEV_TX_OFFLOAD_TCP_CKSUM | 980 DEV_TX_OFFLOAD_UDP_CKSUM | 981 DEV_TX_OFFLOAD_SCTP_CKSUM | 982 DEV_TX_OFFLOAD_MULTI_SEGS | 983 DEV_TX_OFFLOAD_TCP_TSO | 984 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 985 DEV_TX_OFFLOAD_GRE_TNL_TSO | 986 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 987 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 988 hns3_txvlan_cap_get(hw)); 989 990 if (hns3_dev_indep_txrx_supported(hw)) 991 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 992 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 993 994 info->rx_desc_lim = (struct rte_eth_desc_lim) { 995 .nb_max = HNS3_MAX_RING_DESC, 996 .nb_min = HNS3_MIN_RING_DESC, 997 .nb_align = HNS3_ALIGN_RING_DESC, 998 }; 999 1000 info->tx_desc_lim = (struct rte_eth_desc_lim) { 1001 .nb_max = HNS3_MAX_RING_DESC, 1002 .nb_min = HNS3_MIN_RING_DESC, 1003 .nb_align = HNS3_ALIGN_RING_DESC, 1004 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 1005 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 1006 }; 1007 1008 info->default_rxconf = (struct rte_eth_rxconf) { 1009 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 1010 /* 1011 * If there are no available Rx buffer descriptors, incoming 1012 * packets are always dropped by hardware based on hns3 network 1013 * engine. 1014 */ 1015 .rx_drop_en = 1, 1016 .offloads = 0, 1017 }; 1018 info->default_txconf = (struct rte_eth_txconf) { 1019 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 1020 .offloads = 0, 1021 }; 1022 1023 info->vmdq_queue_num = 0; 1024 1025 info->reta_size = HNS3_RSS_IND_TBL_SIZE; 1026 info->hash_key_size = HNS3_RSS_KEY_SIZE; 1027 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 1028 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1029 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1030 1031 return 0; 1032 } 1033 1034 static void 1035 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr) 1036 { 1037 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 1038 } 1039 1040 static void 1041 hns3vf_disable_irq0(struct hns3_hw *hw) 1042 { 1043 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 1044 } 1045 1046 static void 1047 hns3vf_enable_irq0(struct hns3_hw *hw) 1048 { 1049 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 1050 } 1051 1052 static enum hns3vf_evt_cause 1053 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 1054 { 1055 struct hns3_hw *hw = &hns->hw; 1056 enum hns3vf_evt_cause ret; 1057 uint32_t cmdq_stat_reg; 1058 uint32_t rst_ing_reg; 1059 uint32_t val; 1060 1061 /* Fetch the events from their corresponding regs */ 1062 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG); 1063 1064 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1065 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING); 1066 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg); 1067 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 1068 rte_atomic16_set(&hw->reset.disable_cmd, 1); 1069 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 1070 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT); 1071 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B); 1072 if (clearval) { 1073 hw->reset.stats.global_cnt++; 1074 hns3_warn(hw, "Global reset detected, clear reset status"); 1075 } else { 1076 hns3_schedule_delayed_reset(hns); 1077 hns3_warn(hw, "Global reset detected, don't clear reset status"); 1078 } 1079 1080 ret = HNS3VF_VECTOR0_EVENT_RST; 1081 goto out; 1082 } 1083 1084 /* Check for vector0 mailbox(=CMDQ RX) event source */ 1085 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1086 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 1087 ret = HNS3VF_VECTOR0_EVENT_MBX; 1088 goto out; 1089 } 1090 1091 val = 0; 1092 ret = HNS3VF_VECTOR0_EVENT_OTHER; 1093 out: 1094 if (clearval) 1095 *clearval = val; 1096 return ret; 1097 } 1098 1099 static void 1100 hns3vf_interrupt_handler(void *param) 1101 { 1102 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1103 struct hns3_adapter *hns = dev->data->dev_private; 1104 struct hns3_hw *hw = &hns->hw; 1105 enum hns3vf_evt_cause event_cause; 1106 uint32_t clearval; 1107 1108 if (hw->irq_thread_id == 0) 1109 hw->irq_thread_id = pthread_self(); 1110 1111 /* Disable interrupt */ 1112 hns3vf_disable_irq0(hw); 1113 1114 /* Read out interrupt causes */ 1115 event_cause = hns3vf_check_event_cause(hns, &clearval); 1116 1117 switch (event_cause) { 1118 case HNS3VF_VECTOR0_EVENT_RST: 1119 hns3_schedule_reset(hns); 1120 break; 1121 case HNS3VF_VECTOR0_EVENT_MBX: 1122 hns3_dev_handle_mbx_msg(hw); 1123 break; 1124 default: 1125 break; 1126 } 1127 1128 /* Clear interrupt causes */ 1129 hns3vf_clear_event_cause(hw, clearval); 1130 1131 /* Enable interrupt */ 1132 hns3vf_enable_irq0(hw); 1133 } 1134 1135 static void 1136 hns3vf_set_default_dev_specifications(struct hns3_hw *hw) 1137 { 1138 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 1139 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 1140 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 1141 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 1142 } 1143 1144 static void 1145 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 1146 { 1147 struct hns3_dev_specs_0_cmd *req0; 1148 1149 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 1150 1151 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 1152 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 1153 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 1154 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 1155 } 1156 1157 static int 1158 hns3vf_query_dev_specifications(struct hns3_hw *hw) 1159 { 1160 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 1161 int ret; 1162 int i; 1163 1164 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1165 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 1166 true); 1167 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1168 } 1169 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 1170 1171 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 1172 if (ret) 1173 return ret; 1174 1175 hns3vf_parse_dev_specifications(hw, desc); 1176 1177 return 0; 1178 } 1179 1180 static int 1181 hns3vf_get_capability(struct hns3_hw *hw) 1182 { 1183 struct rte_pci_device *pci_dev; 1184 struct rte_eth_dev *eth_dev; 1185 uint8_t revision; 1186 int ret; 1187 1188 eth_dev = &rte_eth_devices[hw->data->port_id]; 1189 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1190 1191 /* Get PCI revision id */ 1192 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 1193 HNS3_PCI_REVISION_ID); 1194 if (ret != HNS3_PCI_REVISION_ID_LEN) { 1195 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 1196 ret); 1197 return -EIO; 1198 } 1199 hw->revision = revision; 1200 1201 if (revision < PCI_REVISION_ID_HIP09_A) { 1202 hns3vf_set_default_dev_specifications(hw); 1203 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 1204 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 1205 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 1206 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 1207 hw->rss_info.ipv6_sctp_offload_supported = false; 1208 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; 1209 return 0; 1210 } 1211 1212 ret = hns3vf_query_dev_specifications(hw); 1213 if (ret) { 1214 PMD_INIT_LOG(ERR, 1215 "failed to query dev specifications, ret = %d", 1216 ret); 1217 return ret; 1218 } 1219 1220 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 1221 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 1222 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 1223 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 1224 hw->rss_info.ipv6_sctp_offload_supported = true; 1225 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; 1226 1227 return 0; 1228 } 1229 1230 static int 1231 hns3vf_check_tqp_info(struct hns3_hw *hw) 1232 { 1233 if (hw->tqps_num == 0) { 1234 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF."); 1235 return -EINVAL; 1236 } 1237 1238 if (hw->rss_size_max == 0) { 1239 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF."); 1240 return -EINVAL; 1241 } 1242 1243 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num); 1244 1245 return 0; 1246 } 1247 1248 static int 1249 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw) 1250 { 1251 uint8_t resp_msg; 1252 int ret; 1253 1254 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, 1255 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0, 1256 true, &resp_msg, sizeof(resp_msg)); 1257 if (ret) { 1258 if (ret == -ETIME) { 1259 /* 1260 * Getting current port based VLAN state from PF driver 1261 * will not affect VF driver's basic function. Because 1262 * the VF driver relies on hns3 PF kernel ether driver, 1263 * to avoid introducing compatibility issues with older 1264 * version of PF driver, no failure will be returned 1265 * when the return value is ETIME. This return value has 1266 * the following scenarios: 1267 * 1) Firmware didn't return the results in time 1268 * 2) the result return by firmware is timeout 1269 * 3) the older version of kernel side PF driver does 1270 * not support this mailbox message. 1271 * For scenarios 1 and 2, it is most likely that a 1272 * hardware error has occurred, or a hardware reset has 1273 * occurred. In this case, these errors will be caught 1274 * by other functions. 1275 */ 1276 PMD_INIT_LOG(WARNING, 1277 "failed to get PVID state for timeout, maybe " 1278 "kernel side PF driver doesn't support this " 1279 "mailbox message, or firmware didn't respond."); 1280 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE; 1281 } else { 1282 PMD_INIT_LOG(ERR, "failed to get port based VLAN state," 1283 " ret = %d", ret); 1284 return ret; 1285 } 1286 } 1287 hw->port_base_vlan_cfg.state = resp_msg ? 1288 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 1289 return 0; 1290 } 1291 1292 static int 1293 hns3vf_get_queue_info(struct hns3_hw *hw) 1294 { 1295 #define HNS3VF_TQPS_RSS_INFO_LEN 6 1296 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN]; 1297 int ret; 1298 1299 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true, 1300 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN); 1301 if (ret) { 1302 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret); 1303 return ret; 1304 } 1305 1306 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t)); 1307 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t)); 1308 1309 return hns3vf_check_tqp_info(hw); 1310 } 1311 1312 static int 1313 hns3vf_get_queue_depth(struct hns3_hw *hw) 1314 { 1315 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4 1316 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN]; 1317 int ret; 1318 1319 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true, 1320 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN); 1321 if (ret) { 1322 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d", 1323 ret); 1324 return ret; 1325 } 1326 1327 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t)); 1328 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t)); 1329 1330 return 0; 1331 } 1332 1333 static int 1334 hns3vf_get_tc_info(struct hns3_hw *hw) 1335 { 1336 uint8_t resp_msg; 1337 int ret; 1338 uint32_t i; 1339 1340 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0, 1341 true, &resp_msg, sizeof(resp_msg)); 1342 if (ret) { 1343 hns3_err(hw, "VF request to get TC info from PF failed %d", 1344 ret); 1345 return ret; 1346 } 1347 1348 hw->hw_tc_map = resp_msg; 1349 1350 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 1351 if (hw->hw_tc_map & BIT(i)) 1352 hw->num_tc++; 1353 } 1354 1355 return 0; 1356 } 1357 1358 static int 1359 hns3vf_get_host_mac_addr(struct hns3_hw *hw) 1360 { 1361 uint8_t host_mac[RTE_ETHER_ADDR_LEN]; 1362 int ret; 1363 1364 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0, 1365 true, host_mac, RTE_ETHER_ADDR_LEN); 1366 if (ret) { 1367 hns3_err(hw, "Failed to get mac addr from PF: %d", ret); 1368 return ret; 1369 } 1370 1371 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN); 1372 1373 return 0; 1374 } 1375 1376 static int 1377 hns3vf_get_configuration(struct hns3_hw *hw) 1378 { 1379 int ret; 1380 1381 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE; 1382 hw->rss_dis_flag = false; 1383 1384 /* Get device capability */ 1385 ret = hns3vf_get_capability(hw); 1386 if (ret) { 1387 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 1388 return ret; 1389 } 1390 1391 /* Get queue configuration from PF */ 1392 ret = hns3vf_get_queue_info(hw); 1393 if (ret) 1394 return ret; 1395 1396 /* Get queue depth info from PF */ 1397 ret = hns3vf_get_queue_depth(hw); 1398 if (ret) 1399 return ret; 1400 1401 /* Get user defined VF MAC addr from PF */ 1402 ret = hns3vf_get_host_mac_addr(hw); 1403 if (ret) 1404 return ret; 1405 1406 ret = hns3vf_get_port_base_vlan_filter_state(hw); 1407 if (ret) 1408 return ret; 1409 1410 /* Get tc configuration from PF */ 1411 return hns3vf_get_tc_info(hw); 1412 } 1413 1414 static int 1415 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q, 1416 uint16_t nb_tx_q) 1417 { 1418 struct hns3_hw *hw = &hns->hw; 1419 1420 if (nb_rx_q < hw->num_tc) { 1421 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).", 1422 nb_rx_q, hw->num_tc); 1423 return -EINVAL; 1424 } 1425 1426 if (nb_tx_q < hw->num_tc) { 1427 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).", 1428 nb_tx_q, hw->num_tc); 1429 return -EINVAL; 1430 } 1431 1432 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q); 1433 } 1434 1435 static void 1436 hns3vf_request_link_info(struct hns3_hw *hw) 1437 { 1438 uint8_t resp_msg; 1439 int ret; 1440 1441 if (rte_atomic16_read(&hw->reset.resetting)) 1442 return; 1443 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false, 1444 &resp_msg, sizeof(resp_msg)); 1445 if (ret) 1446 hns3_err(hw, "Failed to fetch link status from PF: %d", ret); 1447 } 1448 1449 static int 1450 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 1451 { 1452 #define HNS3VF_VLAN_MBX_MSG_LEN 5 1453 struct hns3_hw *hw = &hns->hw; 1454 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN]; 1455 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN); 1456 uint8_t is_kill = on ? 0 : 1; 1457 1458 msg_data[0] = is_kill; 1459 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1460 memcpy(&msg_data[3], &proto, sizeof(proto)); 1461 1462 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER, 1463 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL, 1464 0); 1465 } 1466 1467 static int 1468 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1469 { 1470 struct hns3_adapter *hns = dev->data->dev_private; 1471 struct hns3_hw *hw = &hns->hw; 1472 int ret; 1473 1474 if (rte_atomic16_read(&hw->reset.resetting)) { 1475 hns3_err(hw, 1476 "vf set vlan id failed during resetting, vlan_id =%u", 1477 vlan_id); 1478 return -EIO; 1479 } 1480 rte_spinlock_lock(&hw->lock); 1481 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1482 rte_spinlock_unlock(&hw->lock); 1483 if (ret) 1484 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d", 1485 vlan_id, ret); 1486 1487 return ret; 1488 } 1489 1490 static int 1491 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable) 1492 { 1493 uint8_t msg_data; 1494 int ret; 1495 1496 msg_data = enable ? 1 : 0; 1497 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG, 1498 &msg_data, sizeof(msg_data), false, NULL, 0); 1499 if (ret) 1500 hns3_err(hw, "vf enable strip failed, ret =%d", ret); 1501 1502 return ret; 1503 } 1504 1505 static int 1506 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1507 { 1508 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1509 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1510 unsigned int tmp_mask; 1511 int ret = 0; 1512 1513 if (rte_atomic16_read(&hw->reset.resetting)) { 1514 hns3_err(hw, "vf set vlan offload failed during resetting, " 1515 "mask = 0x%x", mask); 1516 return -EIO; 1517 } 1518 1519 tmp_mask = (unsigned int)mask; 1520 /* Vlan stripping setting */ 1521 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 1522 rte_spinlock_lock(&hw->lock); 1523 /* Enable or disable VLAN stripping */ 1524 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1525 ret = hns3vf_en_hw_strip_rxvtag(hw, true); 1526 else 1527 ret = hns3vf_en_hw_strip_rxvtag(hw, false); 1528 rte_spinlock_unlock(&hw->lock); 1529 } 1530 1531 return ret; 1532 } 1533 1534 static int 1535 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on) 1536 { 1537 struct rte_vlan_filter_conf *vfc; 1538 struct hns3_hw *hw = &hns->hw; 1539 uint16_t vlan_id; 1540 uint64_t vbit; 1541 uint64_t ids; 1542 int ret = 0; 1543 uint32_t i; 1544 1545 vfc = &hw->data->vlan_filter_conf; 1546 for (i = 0; i < RTE_DIM(vfc->ids); i++) { 1547 if (vfc->ids[i] == 0) 1548 continue; 1549 ids = vfc->ids[i]; 1550 while (ids) { 1551 /* 1552 * 64 means the num bits of ids, one bit corresponds to 1553 * one vlan id 1554 */ 1555 vlan_id = 64 * i; 1556 /* count trailing zeroes */ 1557 vbit = ~ids & (ids - 1); 1558 /* clear least significant bit set */ 1559 ids ^= (ids ^ (ids - 1)) ^ vbit; 1560 for (; vbit;) { 1561 vbit >>= 1; 1562 vlan_id++; 1563 } 1564 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1565 if (ret) { 1566 hns3_err(hw, 1567 "VF handle vlan table failed, ret =%d, on = %d", 1568 ret, on); 1569 return ret; 1570 } 1571 } 1572 } 1573 1574 return ret; 1575 } 1576 1577 static int 1578 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns) 1579 { 1580 return hns3vf_handle_all_vlan_table(hns, 0); 1581 } 1582 1583 static int 1584 hns3vf_restore_vlan_conf(struct hns3_adapter *hns) 1585 { 1586 struct hns3_hw *hw = &hns->hw; 1587 struct rte_eth_conf *dev_conf; 1588 bool en; 1589 int ret; 1590 1591 dev_conf = &hw->data->dev_conf; 1592 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true 1593 : false; 1594 ret = hns3vf_en_hw_strip_rxvtag(hw, en); 1595 if (ret) 1596 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en, 1597 ret); 1598 return ret; 1599 } 1600 1601 static int 1602 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev) 1603 { 1604 struct hns3_adapter *hns = dev->data->dev_private; 1605 struct rte_eth_dev_data *data = dev->data; 1606 struct hns3_hw *hw = &hns->hw; 1607 int ret; 1608 1609 if (data->dev_conf.txmode.hw_vlan_reject_tagged || 1610 data->dev_conf.txmode.hw_vlan_reject_untagged || 1611 data->dev_conf.txmode.hw_vlan_insert_pvid) { 1612 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged " 1613 "or hw_vlan_insert_pvid is not support!"); 1614 } 1615 1616 /* Apply vlan offload setting */ 1617 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK); 1618 if (ret) 1619 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret); 1620 1621 return ret; 1622 } 1623 1624 static int 1625 hns3vf_set_alive(struct hns3_hw *hw, bool alive) 1626 { 1627 uint8_t msg_data; 1628 1629 msg_data = alive ? 1 : 0; 1630 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data, 1631 sizeof(msg_data), false, NULL, 0); 1632 } 1633 1634 static void 1635 hns3vf_keep_alive_handler(void *param) 1636 { 1637 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1638 struct hns3_adapter *hns = eth_dev->data->dev_private; 1639 struct hns3_hw *hw = &hns->hw; 1640 uint8_t respmsg; 1641 int ret; 1642 1643 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0, 1644 false, &respmsg, sizeof(uint8_t)); 1645 if (ret) 1646 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)", 1647 ret); 1648 1649 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 1650 eth_dev); 1651 } 1652 1653 static void 1654 hns3vf_service_handler(void *param) 1655 { 1656 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1657 struct hns3_adapter *hns = eth_dev->data->dev_private; 1658 struct hns3_hw *hw = &hns->hw; 1659 1660 /* 1661 * The query link status and reset processing are executed in the 1662 * interrupt thread.When the IMP reset occurs, IMP will not respond, 1663 * and the query operation will time out after 30ms. In the case of 1664 * multiple PF/VFs, each query failure timeout causes the IMP reset 1665 * interrupt to fail to respond within 100ms. 1666 * Before querying the link status, check whether there is a reset 1667 * pending, and if so, abandon the query. 1668 */ 1669 if (!hns3vf_is_reset_pending(hns)) 1670 hns3vf_request_link_info(hw); 1671 else 1672 hns3_warn(hw, "Cancel the query when reset is pending"); 1673 1674 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, 1675 eth_dev); 1676 } 1677 1678 static int 1679 hns3_query_vf_resource(struct hns3_hw *hw) 1680 { 1681 struct hns3_vf_res_cmd *req; 1682 struct hns3_cmd_desc desc; 1683 uint16_t num_msi; 1684 int ret; 1685 1686 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true); 1687 ret = hns3_cmd_send(hw, &desc, 1); 1688 if (ret) { 1689 hns3_err(hw, "query vf resource failed, ret = %d", ret); 1690 return ret; 1691 } 1692 1693 req = (struct hns3_vf_res_cmd *)desc.data; 1694 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number), 1695 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S); 1696 if (num_msi < HNS3_MIN_VECTOR_NUM) { 1697 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)", 1698 num_msi, HNS3_MIN_VECTOR_NUM); 1699 return -EINVAL; 1700 } 1701 1702 hw->num_msi = num_msi; 1703 1704 return 0; 1705 } 1706 1707 static int 1708 hns3vf_init_hardware(struct hns3_adapter *hns) 1709 { 1710 struct hns3_hw *hw = &hns->hw; 1711 uint16_t mtu = hw->data->mtu; 1712 int ret; 1713 1714 ret = hns3vf_set_promisc_mode(hw, true, false, false); 1715 if (ret) 1716 return ret; 1717 1718 ret = hns3vf_config_mtu(hw, mtu); 1719 if (ret) 1720 goto err_init_hardware; 1721 1722 ret = hns3vf_vlan_filter_configure(hns, 0, 1); 1723 if (ret) { 1724 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret); 1725 goto err_init_hardware; 1726 } 1727 1728 ret = hns3_config_gro(hw, false); 1729 if (ret) { 1730 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 1731 goto err_init_hardware; 1732 } 1733 1734 /* 1735 * In the initialization clearing the all hardware mapping relationship 1736 * configurations between queues and interrupt vectors is needed, so 1737 * some error caused by the residual configurations, such as the 1738 * unexpected interrupt, can be avoid. 1739 */ 1740 ret = hns3vf_init_ring_with_vector(hw); 1741 if (ret) { 1742 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 1743 goto err_init_hardware; 1744 } 1745 1746 ret = hns3vf_set_alive(hw, true); 1747 if (ret) { 1748 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret); 1749 goto err_init_hardware; 1750 } 1751 1752 hns3vf_request_link_info(hw); 1753 return 0; 1754 1755 err_init_hardware: 1756 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1757 return ret; 1758 } 1759 1760 static int 1761 hns3vf_clear_vport_list(struct hns3_hw *hw) 1762 { 1763 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL, 1764 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false, 1765 NULL, 0); 1766 } 1767 1768 static int 1769 hns3vf_init_vf(struct rte_eth_dev *eth_dev) 1770 { 1771 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1772 struct hns3_adapter *hns = eth_dev->data->dev_private; 1773 struct hns3_hw *hw = &hns->hw; 1774 int ret; 1775 1776 PMD_INIT_FUNC_TRACE(); 1777 1778 /* Get hardware io base address from pcie BAR2 IO space */ 1779 hw->io_base = pci_dev->mem_resource[2].addr; 1780 1781 /* Firmware command queue initialize */ 1782 ret = hns3_cmd_init_queue(hw); 1783 if (ret) { 1784 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 1785 goto err_cmd_init_queue; 1786 } 1787 1788 /* Firmware command initialize */ 1789 ret = hns3_cmd_init(hw); 1790 if (ret) { 1791 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 1792 goto err_cmd_init; 1793 } 1794 1795 /* Get VF resource */ 1796 ret = hns3_query_vf_resource(hw); 1797 if (ret) 1798 goto err_cmd_init; 1799 1800 rte_spinlock_init(&hw->mbx_resp.lock); 1801 1802 hns3vf_clear_event_cause(hw, 0); 1803 1804 ret = rte_intr_callback_register(&pci_dev->intr_handle, 1805 hns3vf_interrupt_handler, eth_dev); 1806 if (ret) { 1807 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 1808 goto err_intr_callback_register; 1809 } 1810 1811 /* Enable interrupt */ 1812 rte_intr_enable(&pci_dev->intr_handle); 1813 hns3vf_enable_irq0(hw); 1814 1815 /* Get configuration from PF */ 1816 ret = hns3vf_get_configuration(hw); 1817 if (ret) { 1818 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 1819 goto err_get_config; 1820 } 1821 1822 ret = hns3_tqp_stats_init(hw); 1823 if (ret) 1824 goto err_get_config; 1825 1826 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); 1827 if (ret) { 1828 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); 1829 goto err_set_tc_queue; 1830 } 1831 1832 ret = hns3vf_clear_vport_list(hw); 1833 if (ret) { 1834 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret); 1835 goto err_set_tc_queue; 1836 } 1837 1838 ret = hns3vf_init_hardware(hns); 1839 if (ret) 1840 goto err_set_tc_queue; 1841 1842 hns3_set_default_rss_args(hw); 1843 1844 return 0; 1845 1846 err_set_tc_queue: 1847 hns3_tqp_stats_uninit(hw); 1848 1849 err_get_config: 1850 hns3vf_disable_irq0(hw); 1851 rte_intr_disable(&pci_dev->intr_handle); 1852 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 1853 eth_dev); 1854 err_intr_callback_register: 1855 err_cmd_init: 1856 hns3_cmd_uninit(hw); 1857 hns3_cmd_destroy_queue(hw); 1858 err_cmd_init_queue: 1859 hw->io_base = NULL; 1860 1861 return ret; 1862 } 1863 1864 static void 1865 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev) 1866 { 1867 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1868 struct hns3_adapter *hns = eth_dev->data->dev_private; 1869 struct hns3_hw *hw = &hns->hw; 1870 1871 PMD_INIT_FUNC_TRACE(); 1872 1873 hns3_rss_uninit(hns); 1874 (void)hns3_config_gro(hw, false); 1875 (void)hns3vf_set_alive(hw, false); 1876 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1877 hns3_tqp_stats_uninit(hw); 1878 hns3vf_disable_irq0(hw); 1879 rte_intr_disable(&pci_dev->intr_handle); 1880 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 1881 eth_dev); 1882 hns3_cmd_uninit(hw); 1883 hns3_cmd_destroy_queue(hw); 1884 hw->io_base = NULL; 1885 } 1886 1887 static int 1888 hns3vf_do_stop(struct hns3_adapter *hns) 1889 { 1890 struct hns3_hw *hw = &hns->hw; 1891 int ret; 1892 1893 hw->mac.link_status = ETH_LINK_DOWN; 1894 1895 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) { 1896 hns3vf_configure_mac_addr(hns, true); 1897 ret = hns3_reset_all_tqps(hns); 1898 if (ret) { 1899 hns3_err(hw, "failed to reset all queues ret = %d", 1900 ret); 1901 return ret; 1902 } 1903 } 1904 return 0; 1905 } 1906 1907 static void 1908 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev) 1909 { 1910 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1911 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1912 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1913 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 1914 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 1915 uint16_t q_id; 1916 1917 if (dev->data->dev_conf.intr_conf.rxq == 0) 1918 return; 1919 1920 /* unmap the ring with vector */ 1921 if (rte_intr_allow_others(intr_handle)) { 1922 vec = RTE_INTR_VEC_RXTX_OFFSET; 1923 base = RTE_INTR_VEC_RXTX_OFFSET; 1924 } 1925 if (rte_intr_dp_is_en(intr_handle)) { 1926 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 1927 (void)hns3vf_bind_ring_with_vector(hw, vec, false, 1928 HNS3_RING_TYPE_RX, 1929 q_id); 1930 if (vec < base + intr_handle->nb_efd - 1) 1931 vec++; 1932 } 1933 } 1934 /* Clean datapath event and queue/vec mapping */ 1935 rte_intr_efd_disable(intr_handle); 1936 if (intr_handle->intr_vec) { 1937 rte_free(intr_handle->intr_vec); 1938 intr_handle->intr_vec = NULL; 1939 } 1940 } 1941 1942 static int 1943 hns3vf_dev_stop(struct rte_eth_dev *dev) 1944 { 1945 struct hns3_adapter *hns = dev->data->dev_private; 1946 struct hns3_hw *hw = &hns->hw; 1947 1948 PMD_INIT_FUNC_TRACE(); 1949 dev->data->dev_started = 0; 1950 1951 hw->adapter_state = HNS3_NIC_STOPPING; 1952 hns3_set_rxtx_function(dev); 1953 rte_wmb(); 1954 /* Disable datapath on secondary process. */ 1955 hns3_mp_req_stop_rxtx(dev); 1956 /* Prevent crashes when queues are still in use. */ 1957 rte_delay_ms(hw->tqps_num); 1958 1959 rte_spinlock_lock(&hw->lock); 1960 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 1961 hns3_stop_tqps(hw); 1962 hns3vf_do_stop(hns); 1963 hns3vf_unmap_rx_interrupt(dev); 1964 hns3_dev_release_mbufs(hns); 1965 hw->adapter_state = HNS3_NIC_CONFIGURED; 1966 } 1967 hns3_rx_scattered_reset(dev); 1968 rte_eal_alarm_cancel(hns3vf_service_handler, dev); 1969 rte_spinlock_unlock(&hw->lock); 1970 1971 return 0; 1972 } 1973 1974 static int 1975 hns3vf_dev_close(struct rte_eth_dev *eth_dev) 1976 { 1977 struct hns3_adapter *hns = eth_dev->data->dev_private; 1978 struct hns3_hw *hw = &hns->hw; 1979 int ret = 0; 1980 1981 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1982 return 0; 1983 1984 if (hw->adapter_state == HNS3_NIC_STARTED) 1985 ret = hns3vf_dev_stop(eth_dev); 1986 1987 hw->adapter_state = HNS3_NIC_CLOSING; 1988 hns3_reset_abort(hns); 1989 hw->adapter_state = HNS3_NIC_CLOSED; 1990 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev); 1991 hns3vf_configure_all_mc_mac_addr(hns, true); 1992 hns3vf_remove_all_vlan_table(hns); 1993 hns3vf_uninit_vf(eth_dev); 1994 hns3_free_all_queues(eth_dev); 1995 rte_free(hw->reset.wait_data); 1996 rte_free(eth_dev->process_private); 1997 eth_dev->process_private = NULL; 1998 hns3_mp_uninit_primary(); 1999 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 2000 2001 return ret; 2002 } 2003 2004 static int 2005 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2006 size_t fw_size) 2007 { 2008 struct hns3_adapter *hns = eth_dev->data->dev_private; 2009 struct hns3_hw *hw = &hns->hw; 2010 uint32_t version = hw->fw_version; 2011 int ret; 2012 2013 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2014 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2015 HNS3_FW_VERSION_BYTE3_S), 2016 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2017 HNS3_FW_VERSION_BYTE2_S), 2018 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2019 HNS3_FW_VERSION_BYTE1_S), 2020 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2021 HNS3_FW_VERSION_BYTE0_S)); 2022 ret += 1; /* add the size of '\0' */ 2023 if (fw_size < (uint32_t)ret) 2024 return ret; 2025 else 2026 return 0; 2027 } 2028 2029 static int 2030 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, 2031 __rte_unused int wait_to_complete) 2032 { 2033 struct hns3_adapter *hns = eth_dev->data->dev_private; 2034 struct hns3_hw *hw = &hns->hw; 2035 struct hns3_mac *mac = &hw->mac; 2036 struct rte_eth_link new_link; 2037 2038 memset(&new_link, 0, sizeof(new_link)); 2039 switch (mac->link_speed) { 2040 case ETH_SPEED_NUM_10M: 2041 case ETH_SPEED_NUM_100M: 2042 case ETH_SPEED_NUM_1G: 2043 case ETH_SPEED_NUM_10G: 2044 case ETH_SPEED_NUM_25G: 2045 case ETH_SPEED_NUM_40G: 2046 case ETH_SPEED_NUM_50G: 2047 case ETH_SPEED_NUM_100G: 2048 case ETH_SPEED_NUM_200G: 2049 new_link.link_speed = mac->link_speed; 2050 break; 2051 default: 2052 new_link.link_speed = ETH_SPEED_NUM_100M; 2053 break; 2054 } 2055 2056 new_link.link_duplex = mac->link_duplex; 2057 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2058 new_link.link_autoneg = 2059 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2060 2061 return rte_eth_linkstatus_set(eth_dev, &new_link); 2062 } 2063 2064 static int 2065 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue) 2066 { 2067 struct hns3_hw *hw = &hns->hw; 2068 uint16_t nb_rx_q = hw->data->nb_rx_queues; 2069 uint16_t nb_tx_q = hw->data->nb_tx_queues; 2070 int ret; 2071 2072 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q); 2073 if (ret) 2074 return ret; 2075 2076 ret = hns3_init_queues(hns, reset_queue); 2077 if (ret) 2078 hns3_err(hw, "failed to init queues, ret = %d.", ret); 2079 2080 return ret; 2081 } 2082 2083 static int 2084 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) 2085 { 2086 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2087 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2088 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2089 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 2090 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 2091 uint32_t intr_vector; 2092 uint16_t q_id; 2093 int ret; 2094 2095 if (dev->data->dev_conf.intr_conf.rxq == 0) 2096 return 0; 2097 2098 /* disable uio/vfio intr/eventfd mapping */ 2099 rte_intr_disable(intr_handle); 2100 2101 /* check and configure queue intr-vector mapping */ 2102 if (rte_intr_cap_multiple(intr_handle) || 2103 !RTE_ETH_DEV_SRIOV(dev).active) { 2104 intr_vector = hw->used_rx_queues; 2105 /* It creates event fd for each intr vector when MSIX is used */ 2106 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2107 return -EINVAL; 2108 } 2109 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2110 intr_handle->intr_vec = 2111 rte_zmalloc("intr_vec", 2112 hw->used_rx_queues * sizeof(int), 0); 2113 if (intr_handle->intr_vec == NULL) { 2114 hns3_err(hw, "Failed to allocate %u rx_queues" 2115 " intr_vec", hw->used_rx_queues); 2116 ret = -ENOMEM; 2117 goto vf_alloc_intr_vec_error; 2118 } 2119 } 2120 2121 if (rte_intr_allow_others(intr_handle)) { 2122 vec = RTE_INTR_VEC_RXTX_OFFSET; 2123 base = RTE_INTR_VEC_RXTX_OFFSET; 2124 } 2125 if (rte_intr_dp_is_en(intr_handle)) { 2126 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2127 ret = hns3vf_bind_ring_with_vector(hw, vec, true, 2128 HNS3_RING_TYPE_RX, 2129 q_id); 2130 if (ret) 2131 goto vf_bind_vector_error; 2132 intr_handle->intr_vec[q_id] = vec; 2133 if (vec < base + intr_handle->nb_efd - 1) 2134 vec++; 2135 } 2136 } 2137 rte_intr_enable(intr_handle); 2138 return 0; 2139 2140 vf_bind_vector_error: 2141 rte_intr_efd_disable(intr_handle); 2142 if (intr_handle->intr_vec) { 2143 free(intr_handle->intr_vec); 2144 intr_handle->intr_vec = NULL; 2145 } 2146 return ret; 2147 vf_alloc_intr_vec_error: 2148 rte_intr_efd_disable(intr_handle); 2149 return ret; 2150 } 2151 2152 static int 2153 hns3vf_restore_rx_interrupt(struct hns3_hw *hw) 2154 { 2155 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 2156 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2157 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2158 uint16_t q_id; 2159 int ret; 2160 2161 if (dev->data->dev_conf.intr_conf.rxq == 0) 2162 return 0; 2163 2164 if (rte_intr_dp_is_en(intr_handle)) { 2165 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2166 ret = hns3vf_bind_ring_with_vector(hw, 2167 intr_handle->intr_vec[q_id], true, 2168 HNS3_RING_TYPE_RX, q_id); 2169 if (ret) 2170 return ret; 2171 } 2172 } 2173 2174 return 0; 2175 } 2176 2177 static void 2178 hns3vf_restore_filter(struct rte_eth_dev *dev) 2179 { 2180 hns3_restore_rss_filter(dev); 2181 } 2182 2183 static int 2184 hns3vf_dev_start(struct rte_eth_dev *dev) 2185 { 2186 struct hns3_adapter *hns = dev->data->dev_private; 2187 struct hns3_hw *hw = &hns->hw; 2188 int ret; 2189 2190 PMD_INIT_FUNC_TRACE(); 2191 if (rte_atomic16_read(&hw->reset.resetting)) 2192 return -EBUSY; 2193 2194 rte_spinlock_lock(&hw->lock); 2195 hw->adapter_state = HNS3_NIC_STARTING; 2196 ret = hns3vf_do_start(hns, true); 2197 if (ret) { 2198 hw->adapter_state = HNS3_NIC_CONFIGURED; 2199 rte_spinlock_unlock(&hw->lock); 2200 return ret; 2201 } 2202 ret = hns3vf_map_rx_interrupt(dev); 2203 if (ret) { 2204 hw->adapter_state = HNS3_NIC_CONFIGURED; 2205 rte_spinlock_unlock(&hw->lock); 2206 return ret; 2207 } 2208 2209 /* 2210 * There are three register used to control the status of a TQP 2211 * (contains a pair of Tx queue and Rx queue) in the new version network 2212 * engine. One is used to control the enabling of Tx queue, the other is 2213 * used to control the enabling of Rx queue, and the last is the master 2214 * switch used to control the enabling of the tqp. The Tx register and 2215 * TQP register must be enabled at the same time to enable a Tx queue. 2216 * The same applies to the Rx queue. For the older network enginem, this 2217 * function only refresh the enabled flag, and it is used to update the 2218 * status of queue in the dpdk framework. 2219 */ 2220 ret = hns3_start_all_txqs(dev); 2221 if (ret) { 2222 hw->adapter_state = HNS3_NIC_CONFIGURED; 2223 rte_spinlock_unlock(&hw->lock); 2224 return ret; 2225 } 2226 2227 ret = hns3_start_all_rxqs(dev); 2228 if (ret) { 2229 hns3_stop_all_txqs(dev); 2230 hw->adapter_state = HNS3_NIC_CONFIGURED; 2231 rte_spinlock_unlock(&hw->lock); 2232 return ret; 2233 } 2234 2235 hw->adapter_state = HNS3_NIC_STARTED; 2236 rte_spinlock_unlock(&hw->lock); 2237 2238 hns3_rx_scattered_calc(dev); 2239 hns3_set_rxtx_function(dev); 2240 hns3_mp_req_start_rxtx(dev); 2241 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev); 2242 2243 hns3vf_restore_filter(dev); 2244 2245 /* Enable interrupt of all rx queues before enabling queues */ 2246 hns3_dev_all_rx_queue_intr_enable(hw, true); 2247 2248 /* 2249 * After finished the initialization, start all tqps to receive/transmit 2250 * packets and refresh all queue status. 2251 */ 2252 hns3_start_tqps(hw); 2253 2254 return ret; 2255 } 2256 2257 static bool 2258 is_vf_reset_done(struct hns3_hw *hw) 2259 { 2260 #define HNS3_FUN_RST_ING_BITS \ 2261 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \ 2262 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \ 2263 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \ 2264 BIT(HNS3_VECTOR0_FUNCRESET_INT_B)) 2265 2266 uint32_t val; 2267 2268 if (hw->reset.level == HNS3_VF_RESET) { 2269 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 2270 if (val & HNS3_VF_RST_ING_BIT) 2271 return false; 2272 } else { 2273 val = hns3_read_dev(hw, HNS3_FUN_RST_ING); 2274 if (val & HNS3_FUN_RST_ING_BITS) 2275 return false; 2276 } 2277 return true; 2278 } 2279 2280 bool 2281 hns3vf_is_reset_pending(struct hns3_adapter *hns) 2282 { 2283 struct hns3_hw *hw = &hns->hw; 2284 enum hns3_reset_level reset; 2285 2286 /* 2287 * According to the protocol of PCIe, FLR to a PF device resets the PF 2288 * state as well as the SR-IOV extended capability including VF Enable 2289 * which means that VFs no longer exist. 2290 * 2291 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device 2292 * is in FLR stage, the register state of VF device is not reliable, 2293 * so register states detection can not be carried out. In this case, 2294 * we just ignore the register states and return false to indicate that 2295 * there are no other reset states that need to be processed by driver. 2296 */ 2297 if (hw->reset.level == HNS3_VF_FULL_RESET) 2298 return false; 2299 2300 /* Check the registers to confirm whether there is reset pending */ 2301 hns3vf_check_event_cause(hns, NULL); 2302 reset = hns3vf_get_reset_level(hw, &hw->reset.pending); 2303 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 2304 hns3_warn(hw, "High level reset %d is pending", reset); 2305 return true; 2306 } 2307 return false; 2308 } 2309 2310 static int 2311 hns3vf_wait_hardware_ready(struct hns3_adapter *hns) 2312 { 2313 struct hns3_hw *hw = &hns->hw; 2314 struct hns3_wait_data *wait_data = hw->reset.wait_data; 2315 struct timeval tv; 2316 2317 if (wait_data->result == HNS3_WAIT_SUCCESS) { 2318 /* 2319 * After vf reset is ready, the PF may not have completed 2320 * the reset processing. The vf sending mbox to PF may fail 2321 * during the pf reset, so it is better to add extra delay. 2322 */ 2323 if (hw->reset.level == HNS3_VF_FUNC_RESET || 2324 hw->reset.level == HNS3_FLR_RESET) 2325 return 0; 2326 /* Reset retry process, no need to add extra delay. */ 2327 if (hw->reset.attempts) 2328 return 0; 2329 if (wait_data->check_completion == NULL) 2330 return 0; 2331 2332 wait_data->check_completion = NULL; 2333 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC; 2334 wait_data->count = 1; 2335 wait_data->result = HNS3_WAIT_REQUEST; 2336 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, 2337 wait_data); 2338 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); 2339 return -EAGAIN; 2340 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 2341 gettimeofday(&tv, NULL); 2342 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 2343 tv.tv_sec, tv.tv_usec); 2344 return -ETIME; 2345 } else if (wait_data->result == HNS3_WAIT_REQUEST) 2346 return -EAGAIN; 2347 2348 wait_data->hns = hns; 2349 wait_data->check_completion = is_vf_reset_done; 2350 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT * 2351 HNS3VF_RESET_WAIT_MS + get_timeofday_ms(); 2352 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC; 2353 wait_data->count = HNS3VF_RESET_WAIT_CNT; 2354 wait_data->result = HNS3_WAIT_REQUEST; 2355 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 2356 return -EAGAIN; 2357 } 2358 2359 static int 2360 hns3vf_prepare_reset(struct hns3_adapter *hns) 2361 { 2362 struct hns3_hw *hw = &hns->hw; 2363 int ret = 0; 2364 2365 if (hw->reset.level == HNS3_VF_FUNC_RESET) { 2366 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL, 2367 0, true, NULL, 0); 2368 } 2369 rte_atomic16_set(&hw->reset.disable_cmd, 1); 2370 2371 return ret; 2372 } 2373 2374 static int 2375 hns3vf_stop_service(struct hns3_adapter *hns) 2376 { 2377 struct hns3_hw *hw = &hns->hw; 2378 struct rte_eth_dev *eth_dev; 2379 2380 eth_dev = &rte_eth_devices[hw->data->port_id]; 2381 if (hw->adapter_state == HNS3_NIC_STARTED) 2382 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev); 2383 hw->mac.link_status = ETH_LINK_DOWN; 2384 2385 hns3_set_rxtx_function(eth_dev); 2386 rte_wmb(); 2387 /* Disable datapath on secondary process. */ 2388 hns3_mp_req_stop_rxtx(eth_dev); 2389 rte_delay_ms(hw->tqps_num); 2390 2391 rte_spinlock_lock(&hw->lock); 2392 if (hw->adapter_state == HNS3_NIC_STARTED || 2393 hw->adapter_state == HNS3_NIC_STOPPING) { 2394 hns3_enable_all_queues(hw, false); 2395 hns3vf_do_stop(hns); 2396 hw->reset.mbuf_deferred_free = true; 2397 } else 2398 hw->reset.mbuf_deferred_free = false; 2399 2400 /* 2401 * It is cumbersome for hardware to pick-and-choose entries for deletion 2402 * from table space. Hence, for function reset software intervention is 2403 * required to delete the entries. 2404 */ 2405 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) 2406 hns3vf_configure_all_mc_mac_addr(hns, true); 2407 rte_spinlock_unlock(&hw->lock); 2408 2409 return 0; 2410 } 2411 2412 static int 2413 hns3vf_start_service(struct hns3_adapter *hns) 2414 { 2415 struct hns3_hw *hw = &hns->hw; 2416 struct rte_eth_dev *eth_dev; 2417 2418 eth_dev = &rte_eth_devices[hw->data->port_id]; 2419 hns3_set_rxtx_function(eth_dev); 2420 hns3_mp_req_start_rxtx(eth_dev); 2421 if (hw->adapter_state == HNS3_NIC_STARTED) { 2422 hns3vf_service_handler(eth_dev); 2423 2424 /* Enable interrupt of all rx queues before enabling queues */ 2425 hns3_dev_all_rx_queue_intr_enable(hw, true); 2426 /* 2427 * Enable state of each rxq and txq will be recovered after 2428 * reset, so we need to restore them before enable all tqps; 2429 */ 2430 hns3_restore_tqp_enable_state(hw); 2431 /* 2432 * When finished the initialization, enable queues to receive 2433 * and transmit packets. 2434 */ 2435 hns3_enable_all_queues(hw, true); 2436 } 2437 2438 return 0; 2439 } 2440 2441 static int 2442 hns3vf_check_default_mac_change(struct hns3_hw *hw) 2443 { 2444 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2445 struct rte_ether_addr *hw_mac; 2446 int ret; 2447 2448 /* 2449 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2450 * on the host by "ip link set ..." command. If the hns3 PF kernel 2451 * ethdev driver sets the MAC address for VF device after the 2452 * initialization of the related VF device, the PF driver will notify 2453 * VF driver to reset VF device to make the new MAC address effective 2454 * immediately. The hns3 VF PMD driver should check whether the MAC 2455 * address has been changed by the PF kernel ethdev driver, if changed 2456 * VF driver should configure hardware using the new MAC address in the 2457 * recovering hardware configuration stage of the reset process. 2458 */ 2459 ret = hns3vf_get_host_mac_addr(hw); 2460 if (ret) 2461 return ret; 2462 2463 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr; 2464 ret = rte_is_zero_ether_addr(hw_mac); 2465 if (ret) { 2466 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac); 2467 } else { 2468 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac); 2469 if (!ret) { 2470 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]); 2471 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2472 &hw->data->mac_addrs[0]); 2473 hns3_warn(hw, "Default MAC address has been changed to:" 2474 " %s by the host PF kernel ethdev driver", 2475 mac_str); 2476 } 2477 } 2478 2479 return 0; 2480 } 2481 2482 static int 2483 hns3vf_restore_conf(struct hns3_adapter *hns) 2484 { 2485 struct hns3_hw *hw = &hns->hw; 2486 int ret; 2487 2488 ret = hns3vf_check_default_mac_change(hw); 2489 if (ret) 2490 return ret; 2491 2492 ret = hns3vf_configure_mac_addr(hns, false); 2493 if (ret) 2494 return ret; 2495 2496 ret = hns3vf_configure_all_mc_mac_addr(hns, false); 2497 if (ret) 2498 goto err_mc_mac; 2499 2500 ret = hns3vf_restore_promisc(hns); 2501 if (ret) 2502 goto err_vlan_table; 2503 2504 ret = hns3vf_restore_vlan_conf(hns); 2505 if (ret) 2506 goto err_vlan_table; 2507 2508 ret = hns3vf_get_port_base_vlan_filter_state(hw); 2509 if (ret) 2510 goto err_vlan_table; 2511 2512 ret = hns3vf_restore_rx_interrupt(hw); 2513 if (ret) 2514 goto err_vlan_table; 2515 2516 ret = hns3_restore_gro_conf(hw); 2517 if (ret) 2518 goto err_vlan_table; 2519 2520 if (hw->adapter_state == HNS3_NIC_STARTED) { 2521 ret = hns3vf_do_start(hns, false); 2522 if (ret) 2523 goto err_vlan_table; 2524 hns3_info(hw, "hns3vf dev restart successful!"); 2525 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 2526 hw->adapter_state = HNS3_NIC_CONFIGURED; 2527 return 0; 2528 2529 err_vlan_table: 2530 hns3vf_configure_all_mc_mac_addr(hns, true); 2531 err_mc_mac: 2532 hns3vf_configure_mac_addr(hns, true); 2533 return ret; 2534 } 2535 2536 static enum hns3_reset_level 2537 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels) 2538 { 2539 enum hns3_reset_level reset_level; 2540 2541 /* return the highest priority reset level amongst all */ 2542 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels)) 2543 reset_level = HNS3_VF_RESET; 2544 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels)) 2545 reset_level = HNS3_VF_FULL_RESET; 2546 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels)) 2547 reset_level = HNS3_VF_PF_FUNC_RESET; 2548 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels)) 2549 reset_level = HNS3_VF_FUNC_RESET; 2550 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 2551 reset_level = HNS3_FLR_RESET; 2552 else 2553 reset_level = HNS3_NONE_RESET; 2554 2555 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 2556 return HNS3_NONE_RESET; 2557 2558 return reset_level; 2559 } 2560 2561 static void 2562 hns3vf_reset_service(void *param) 2563 { 2564 struct hns3_adapter *hns = (struct hns3_adapter *)param; 2565 struct hns3_hw *hw = &hns->hw; 2566 enum hns3_reset_level reset_level; 2567 struct timeval tv_delta; 2568 struct timeval tv_start; 2569 struct timeval tv; 2570 uint64_t msec; 2571 2572 /* 2573 * The interrupt is not triggered within the delay time. 2574 * The interrupt may have been lost. It is necessary to handle 2575 * the interrupt to recover from the error. 2576 */ 2577 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) { 2578 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); 2579 hns3_err(hw, "Handling interrupts in delayed tasks"); 2580 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 2581 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2582 if (reset_level == HNS3_NONE_RESET) { 2583 hns3_err(hw, "No reset level is set, try global reset"); 2584 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 2585 } 2586 } 2587 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); 2588 2589 /* 2590 * Hardware reset has been notified, we now have to poll & check if 2591 * hardware has actually completed the reset sequence. 2592 */ 2593 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2594 if (reset_level != HNS3_NONE_RESET) { 2595 gettimeofday(&tv_start, NULL); 2596 hns3_reset_process(hns, reset_level); 2597 gettimeofday(&tv, NULL); 2598 timersub(&tv, &tv_start, &tv_delta); 2599 msec = tv_delta.tv_sec * MSEC_PER_SEC + 2600 tv_delta.tv_usec / USEC_PER_MSEC; 2601 if (msec > HNS3_RESET_PROCESS_MS) 2602 hns3_err(hw, "%d handle long time delta %" PRIx64 2603 " ms time=%ld.%.6ld", 2604 hw->reset.level, msec, tv.tv_sec, tv.tv_usec); 2605 } 2606 } 2607 2608 static int 2609 hns3vf_reinit_dev(struct hns3_adapter *hns) 2610 { 2611 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id]; 2612 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2613 struct hns3_hw *hw = &hns->hw; 2614 int ret; 2615 2616 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2617 rte_intr_disable(&pci_dev->intr_handle); 2618 ret = hns3vf_set_bus_master(pci_dev, true); 2619 if (ret < 0) { 2620 hns3_err(hw, "failed to set pci bus, ret = %d", ret); 2621 return ret; 2622 } 2623 } 2624 2625 /* Firmware command initialize */ 2626 ret = hns3_cmd_init(hw); 2627 if (ret) { 2628 hns3_err(hw, "Failed to init cmd: %d", ret); 2629 return ret; 2630 } 2631 2632 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2633 /* 2634 * UIO enables msix by writing the pcie configuration space 2635 * vfio_pci enables msix in rte_intr_enable. 2636 */ 2637 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO || 2638 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) { 2639 if (hns3vf_enable_msix(pci_dev, true)) 2640 hns3_err(hw, "Failed to enable msix"); 2641 } 2642 2643 rte_intr_enable(&pci_dev->intr_handle); 2644 } 2645 2646 ret = hns3_reset_all_tqps(hns); 2647 if (ret) { 2648 hns3_err(hw, "Failed to reset all queues: %d", ret); 2649 return ret; 2650 } 2651 2652 ret = hns3vf_init_hardware(hns); 2653 if (ret) { 2654 hns3_err(hw, "Failed to init hardware: %d", ret); 2655 return ret; 2656 } 2657 2658 return 0; 2659 } 2660 2661 static const struct eth_dev_ops hns3vf_eth_dev_ops = { 2662 .dev_configure = hns3vf_dev_configure, 2663 .dev_start = hns3vf_dev_start, 2664 .dev_stop = hns3vf_dev_stop, 2665 .dev_close = hns3vf_dev_close, 2666 .mtu_set = hns3vf_dev_mtu_set, 2667 .promiscuous_enable = hns3vf_dev_promiscuous_enable, 2668 .promiscuous_disable = hns3vf_dev_promiscuous_disable, 2669 .allmulticast_enable = hns3vf_dev_allmulticast_enable, 2670 .allmulticast_disable = hns3vf_dev_allmulticast_disable, 2671 .stats_get = hns3_stats_get, 2672 .stats_reset = hns3_stats_reset, 2673 .xstats_get = hns3_dev_xstats_get, 2674 .xstats_get_names = hns3_dev_xstats_get_names, 2675 .xstats_reset = hns3_dev_xstats_reset, 2676 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 2677 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 2678 .dev_infos_get = hns3vf_dev_infos_get, 2679 .fw_version_get = hns3vf_fw_version_get, 2680 .rx_queue_setup = hns3_rx_queue_setup, 2681 .tx_queue_setup = hns3_tx_queue_setup, 2682 .rx_queue_release = hns3_dev_rx_queue_release, 2683 .tx_queue_release = hns3_dev_tx_queue_release, 2684 .rx_queue_start = hns3_dev_rx_queue_start, 2685 .rx_queue_stop = hns3_dev_rx_queue_stop, 2686 .tx_queue_start = hns3_dev_tx_queue_start, 2687 .tx_queue_stop = hns3_dev_tx_queue_stop, 2688 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 2689 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 2690 .rxq_info_get = hns3_rxq_info_get, 2691 .txq_info_get = hns3_txq_info_get, 2692 .rx_burst_mode_get = hns3_rx_burst_mode_get, 2693 .tx_burst_mode_get = hns3_tx_burst_mode_get, 2694 .mac_addr_add = hns3vf_add_mac_addr, 2695 .mac_addr_remove = hns3vf_remove_mac_addr, 2696 .mac_addr_set = hns3vf_set_default_mac_addr, 2697 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list, 2698 .link_update = hns3vf_dev_link_update, 2699 .rss_hash_update = hns3_dev_rss_hash_update, 2700 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 2701 .reta_update = hns3_dev_rss_reta_update, 2702 .reta_query = hns3_dev_rss_reta_query, 2703 .filter_ctrl = hns3_dev_filter_ctrl, 2704 .vlan_filter_set = hns3vf_vlan_filter_set, 2705 .vlan_offload_set = hns3vf_vlan_offload_set, 2706 .get_reg = hns3_get_regs, 2707 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 2708 }; 2709 2710 static const struct hns3_reset_ops hns3vf_reset_ops = { 2711 .reset_service = hns3vf_reset_service, 2712 .stop_service = hns3vf_stop_service, 2713 .prepare_reset = hns3vf_prepare_reset, 2714 .wait_hardware_ready = hns3vf_wait_hardware_ready, 2715 .reinit_dev = hns3vf_reinit_dev, 2716 .restore_conf = hns3vf_restore_conf, 2717 .start_service = hns3vf_start_service, 2718 }; 2719 2720 static int 2721 hns3vf_dev_init(struct rte_eth_dev *eth_dev) 2722 { 2723 struct hns3_adapter *hns = eth_dev->data->dev_private; 2724 struct hns3_hw *hw = &hns->hw; 2725 int ret; 2726 2727 PMD_INIT_FUNC_TRACE(); 2728 2729 eth_dev->process_private = (struct hns3_process_private *) 2730 rte_zmalloc_socket("hns3_filter_list", 2731 sizeof(struct hns3_process_private), 2732 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 2733 if (eth_dev->process_private == NULL) { 2734 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 2735 return -ENOMEM; 2736 } 2737 2738 /* initialize flow filter lists */ 2739 hns3_filterlist_init(eth_dev); 2740 2741 hns3_set_rxtx_function(eth_dev); 2742 eth_dev->dev_ops = &hns3vf_eth_dev_ops; 2743 eth_dev->rx_queue_count = hns3_rx_queue_count; 2744 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2745 ret = hns3_mp_init_secondary(); 2746 if (ret) { 2747 PMD_INIT_LOG(ERR, "Failed to init for secondary " 2748 "process, ret = %d", ret); 2749 goto err_mp_init_secondary; 2750 } 2751 2752 hw->secondary_cnt++; 2753 return 0; 2754 } 2755 2756 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2757 2758 ret = hns3_mp_init_primary(); 2759 if (ret) { 2760 PMD_INIT_LOG(ERR, 2761 "Failed to init for primary process, ret = %d", 2762 ret); 2763 goto err_mp_init_primary; 2764 } 2765 2766 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 2767 hns->is_vf = true; 2768 hw->data = eth_dev->data; 2769 2770 ret = hns3_reset_init(hw); 2771 if (ret) 2772 goto err_init_reset; 2773 hw->reset.ops = &hns3vf_reset_ops; 2774 2775 ret = hns3vf_init_vf(eth_dev); 2776 if (ret) { 2777 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret); 2778 goto err_init_vf; 2779 } 2780 2781 /* Allocate memory for storing MAC addresses */ 2782 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac", 2783 sizeof(struct rte_ether_addr) * 2784 HNS3_VF_UC_MACADDR_NUM, 0); 2785 if (eth_dev->data->mac_addrs == NULL) { 2786 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 2787 "to store MAC addresses", 2788 sizeof(struct rte_ether_addr) * 2789 HNS3_VF_UC_MACADDR_NUM); 2790 ret = -ENOMEM; 2791 goto err_rte_zmalloc; 2792 } 2793 2794 /* 2795 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2796 * on the host by "ip link set ..." command. To avoid some incorrect 2797 * scenes, for example, hns3 VF PMD driver fails to receive and send 2798 * packets after user configure the MAC address by using the 2799 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC 2800 * address strategy as the hns3 kernel ethdev driver in the 2801 * initialization. If user configure a MAC address by the ip command 2802 * for VF device, then hns3 VF PMD driver will start with it, otherwise 2803 * start with a random MAC address in the initialization. 2804 */ 2805 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr)) 2806 rte_eth_random_addr(hw->mac.mac_addr); 2807 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 2808 ð_dev->data->mac_addrs[0]); 2809 2810 hw->adapter_state = HNS3_NIC_INITIALIZED; 2811 2812 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) { 2813 hns3_err(hw, "Reschedule reset service after dev_init"); 2814 hns3_schedule_reset(hns); 2815 } else { 2816 /* IMP will wait ready flag before reset */ 2817 hns3_notify_reset_ready(hw, false); 2818 } 2819 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 2820 eth_dev); 2821 return 0; 2822 2823 err_rte_zmalloc: 2824 hns3vf_uninit_vf(eth_dev); 2825 2826 err_init_vf: 2827 rte_free(hw->reset.wait_data); 2828 2829 err_init_reset: 2830 hns3_mp_uninit_primary(); 2831 2832 err_mp_init_primary: 2833 err_mp_init_secondary: 2834 eth_dev->dev_ops = NULL; 2835 eth_dev->rx_pkt_burst = NULL; 2836 eth_dev->tx_pkt_burst = NULL; 2837 eth_dev->tx_pkt_prepare = NULL; 2838 rte_free(eth_dev->process_private); 2839 eth_dev->process_private = NULL; 2840 2841 return ret; 2842 } 2843 2844 static int 2845 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev) 2846 { 2847 struct hns3_adapter *hns = eth_dev->data->dev_private; 2848 struct hns3_hw *hw = &hns->hw; 2849 2850 PMD_INIT_FUNC_TRACE(); 2851 2852 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2853 return -EPERM; 2854 2855 if (hw->adapter_state < HNS3_NIC_CLOSING) 2856 hns3vf_dev_close(eth_dev); 2857 2858 hw->adapter_state = HNS3_NIC_REMOVED; 2859 return 0; 2860 } 2861 2862 static int 2863 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2864 struct rte_pci_device *pci_dev) 2865 { 2866 return rte_eth_dev_pci_generic_probe(pci_dev, 2867 sizeof(struct hns3_adapter), 2868 hns3vf_dev_init); 2869 } 2870 2871 static int 2872 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev) 2873 { 2874 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit); 2875 } 2876 2877 static const struct rte_pci_id pci_id_hns3vf_map[] = { 2878 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) }, 2879 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) }, 2880 { .vendor_id = 0, }, /* sentinel */ 2881 }; 2882 2883 static struct rte_pci_driver rte_hns3vf_pmd = { 2884 .id_table = pci_id_hns3vf_map, 2885 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2886 .probe = eth_hns3vf_pci_probe, 2887 .remove = eth_hns3vf_pci_remove, 2888 }; 2889 2890 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); 2891 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); 2892 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); 2893