1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <errno.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <string.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <arpa/inet.h> 12 #include <linux/pci_regs.h> 13 14 #include <rte_alarm.h> 15 #include <rte_atomic.h> 16 #include <rte_bus_pci.h> 17 #include <rte_byteorder.h> 18 #include <rte_common.h> 19 #include <rte_cycles.h> 20 #include <rte_dev.h> 21 #include <rte_eal.h> 22 #include <rte_ether.h> 23 #include <rte_ethdev_driver.h> 24 #include <rte_ethdev_pci.h> 25 #include <rte_interrupts.h> 26 #include <rte_io.h> 27 #include <rte_log.h> 28 #include <rte_pci.h> 29 #include <rte_vfio.h> 30 31 #include "hns3_ethdev.h" 32 #include "hns3_logs.h" 33 #include "hns3_rxtx.h" 34 #include "hns3_regs.h" 35 #include "hns3_intr.h" 36 #include "hns3_dcb.h" 37 #include "hns3_mp.h" 38 39 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */ 40 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */ 41 42 #define HNS3VF_RESET_WAIT_MS 20 43 #define HNS3VF_RESET_WAIT_CNT 2000 44 45 /* Reset related Registers */ 46 #define HNS3_GLOBAL_RESET_BIT 0 47 #define HNS3_CORE_RESET_BIT 1 48 #define HNS3_IMP_RESET_BIT 2 49 #define HNS3_FUN_RST_ING_B 0 50 51 enum hns3vf_evt_cause { 52 HNS3VF_VECTOR0_EVENT_RST, 53 HNS3VF_VECTOR0_EVENT_MBX, 54 HNS3VF_VECTOR0_EVENT_OTHER, 55 }; 56 57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw, 58 uint64_t *levels); 59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev); 61 62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 63 struct rte_ether_addr *mac_addr); 64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 65 struct rte_ether_addr *mac_addr); 66 /* set PCI bus mastering */ 67 static void 68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) 69 { 70 uint16_t reg; 71 72 rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); 73 74 if (op) 75 /* set the master bit */ 76 reg |= PCI_COMMAND_MASTER; 77 else 78 reg &= ~(PCI_COMMAND_MASTER); 79 80 rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); 81 } 82 83 /** 84 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list 85 * @cap: the capability 86 * 87 * Return the address of the given capability within the PCI capability list. 88 */ 89 static int 90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) 91 { 92 #define MAX_PCIE_CAPABILITY 48 93 uint16_t status; 94 uint8_t pos; 95 uint8_t id; 96 int ttl; 97 98 rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); 99 if (!(status & PCI_STATUS_CAP_LIST)) 100 return 0; 101 102 ttl = MAX_PCIE_CAPABILITY; 103 rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST); 104 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { 105 rte_pci_read_config(device, &id, sizeof(id), 106 (pos + PCI_CAP_LIST_ID)); 107 108 if (id == 0xFF) 109 break; 110 111 if (id == cap) 112 return (int)pos; 113 114 rte_pci_read_config(device, &pos, sizeof(pos), 115 (pos + PCI_CAP_LIST_NEXT)); 116 } 117 return 0; 118 } 119 120 static int 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op) 122 { 123 uint16_t control; 124 int pos; 125 126 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); 127 if (pos) { 128 rte_pci_read_config(device, &control, sizeof(control), 129 (pos + PCI_MSIX_FLAGS)); 130 if (op) 131 control |= PCI_MSIX_FLAGS_ENABLE; 132 else 133 control &= ~PCI_MSIX_FLAGS_ENABLE; 134 rte_pci_write_config(device, &control, sizeof(control), 135 (pos + PCI_MSIX_FLAGS)); 136 return 0; 137 } 138 return -ENXIO; 139 } 140 141 static int 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 143 { 144 /* mac address was checked by upper level interface */ 145 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 146 int ret; 147 148 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 149 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes, 150 RTE_ETHER_ADDR_LEN, false, NULL, 0); 151 if (ret) { 152 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 153 mac_addr); 154 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 155 mac_str, ret); 156 } 157 return ret; 158 } 159 160 static int 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 162 { 163 /* mac address was checked by upper level interface */ 164 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 165 int ret; 166 167 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 168 HNS3_MBX_MAC_VLAN_UC_REMOVE, 169 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, 170 false, NULL, 0); 171 if (ret) { 172 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 173 mac_addr); 174 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 175 mac_str, ret); 176 } 177 return ret; 178 } 179 180 static int 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 182 { 183 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 184 struct rte_ether_addr *addr; 185 int ret; 186 int i; 187 188 for (i = 0; i < hw->mc_addrs_num; i++) { 189 addr = &hw->mc_addrs[i]; 190 /* Check if there are duplicate addresses */ 191 if (rte_is_same_ether_addr(addr, mac_addr)) { 192 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 193 addr); 194 hns3_err(hw, "failed to add mc mac addr, same addrs" 195 "(%s) is added by the set_mc_mac_addr_list " 196 "API", mac_str); 197 return -EINVAL; 198 } 199 } 200 201 ret = hns3vf_add_mc_mac_addr(hw, mac_addr); 202 if (ret) { 203 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 204 mac_addr); 205 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 206 mac_str, ret); 207 } 208 return ret; 209 } 210 211 static int 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 213 __rte_unused uint32_t idx, 214 __rte_unused uint32_t pool) 215 { 216 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 217 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 218 int ret; 219 220 rte_spinlock_lock(&hw->lock); 221 222 /* 223 * In hns3 network engine adding UC and MC mac address with different 224 * commands with firmware. We need to determine whether the input 225 * address is a UC or a MC address to call different commands. 226 * By the way, it is recommended calling the API function named 227 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 228 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 229 * may affect the specifications of UC mac addresses. 230 */ 231 if (rte_is_multicast_ether_addr(mac_addr)) 232 ret = hns3vf_add_mc_addr_common(hw, mac_addr); 233 else 234 ret = hns3vf_add_uc_mac_addr(hw, mac_addr); 235 236 rte_spinlock_unlock(&hw->lock); 237 if (ret) { 238 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 239 mac_addr); 240 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 241 ret); 242 } 243 244 return ret; 245 } 246 247 static void 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 249 { 250 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 251 /* index will be checked by upper level rte interface */ 252 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 253 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 254 int ret; 255 256 rte_spinlock_lock(&hw->lock); 257 258 if (rte_is_multicast_ether_addr(mac_addr)) 259 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr); 260 else 261 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr); 262 263 rte_spinlock_unlock(&hw->lock); 264 if (ret) { 265 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 266 mac_addr); 267 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", 268 mac_str, ret); 269 } 270 } 271 272 static int 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev, 274 struct rte_ether_addr *mac_addr) 275 { 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2) 277 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 278 struct rte_ether_addr *old_addr; 279 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */ 280 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 281 int ret; 282 283 /* 284 * It has been guaranteed that input parameter named mac_addr is valid 285 * address in the rte layer of DPDK framework. 286 */ 287 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 288 rte_spinlock_lock(&hw->lock); 289 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN); 290 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes, 291 RTE_ETHER_ADDR_LEN); 292 293 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 294 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes, 295 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0); 296 if (ret) { 297 /* 298 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev 299 * driver. When user has configured a MAC address for VF device 300 * by "ip link set ..." command based on the PF device, the hns3 301 * PF kernel ethdev driver does not allow VF driver to request 302 * reconfiguring a different default MAC address, and return 303 * -EPREM to VF driver through mailbox. 304 */ 305 if (ret == -EPERM) { 306 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 307 old_addr); 308 hns3_warn(hw, "Has permanet mac addr(%s) for vf", 309 mac_str); 310 } else { 311 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 312 mac_addr); 313 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", 314 mac_str, ret); 315 } 316 } 317 318 rte_ether_addr_copy(mac_addr, 319 (struct rte_ether_addr *)hw->mac.mac_addr); 320 rte_spinlock_unlock(&hw->lock); 321 322 return ret; 323 } 324 325 static int 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del) 327 { 328 struct hns3_hw *hw = &hns->hw; 329 struct rte_ether_addr *addr; 330 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 331 int err = 0; 332 int ret; 333 int i; 334 335 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) { 336 addr = &hw->data->mac_addrs[i]; 337 if (rte_is_zero_ether_addr(addr)) 338 continue; 339 if (rte_is_multicast_ether_addr(addr)) 340 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) : 341 hns3vf_add_mc_mac_addr(hw, addr); 342 else 343 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) : 344 hns3vf_add_uc_mac_addr(hw, addr); 345 346 if (ret) { 347 err = ret; 348 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 349 addr); 350 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 351 "ret = %d.", del ? "remove" : "restore", 352 mac_str, i, ret); 353 } 354 } 355 return err; 356 } 357 358 static int 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 360 struct rte_ether_addr *mac_addr) 361 { 362 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 363 int ret; 364 365 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 366 HNS3_MBX_MAC_VLAN_MC_ADD, 367 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 368 NULL, 0); 369 if (ret) { 370 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 371 mac_addr); 372 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d", 373 mac_str, ret); 374 } 375 376 return ret; 377 } 378 379 static int 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 381 struct rte_ether_addr *mac_addr) 382 { 383 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 384 int ret; 385 386 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 387 HNS3_MBX_MAC_VLAN_MC_REMOVE, 388 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 389 NULL, 0); 390 if (ret) { 391 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 392 mac_addr); 393 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d", 394 mac_str, ret); 395 } 396 397 return ret; 398 } 399 400 static int 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw, 402 struct rte_ether_addr *mc_addr_set, 403 uint32_t nb_mc_addr) 404 { 405 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 406 struct rte_ether_addr *addr; 407 uint32_t i; 408 uint32_t j; 409 410 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 411 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) " 412 "invalid. valid range: 0~%d", 413 nb_mc_addr, HNS3_MC_MACADDR_NUM); 414 return -EINVAL; 415 } 416 417 /* Check if input mac addresses are valid */ 418 for (i = 0; i < nb_mc_addr; i++) { 419 addr = &mc_addr_set[i]; 420 if (!rte_is_multicast_ether_addr(addr)) { 421 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 422 addr); 423 hns3_err(hw, 424 "failed to set mc mac addr, addr(%s) invalid.", 425 mac_str); 426 return -EINVAL; 427 } 428 429 /* Check if there are duplicate addresses */ 430 for (j = i + 1; j < nb_mc_addr; j++) { 431 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 432 rte_ether_format_addr(mac_str, 433 RTE_ETHER_ADDR_FMT_SIZE, 434 addr); 435 hns3_err(hw, "failed to set mc mac addr, " 436 "addrs invalid. two same addrs(%s).", 437 mac_str); 438 return -EINVAL; 439 } 440 } 441 442 /* 443 * Check if there are duplicate addresses between mac_addrs 444 * and mc_addr_set 445 */ 446 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) { 447 if (rte_is_same_ether_addr(addr, 448 &hw->data->mac_addrs[j])) { 449 rte_ether_format_addr(mac_str, 450 RTE_ETHER_ADDR_FMT_SIZE, 451 addr); 452 hns3_err(hw, "failed to set mc mac addr, " 453 "addrs invalid. addrs(%s) has already " 454 "configured in mac_addr add API", 455 mac_str); 456 return -EINVAL; 457 } 458 } 459 } 460 461 return 0; 462 } 463 464 static int 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev, 466 struct rte_ether_addr *mc_addr_set, 467 uint32_t nb_mc_addr) 468 { 469 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 470 struct rte_ether_addr *addr; 471 int cur_addr_num; 472 int set_addr_num; 473 int num; 474 int ret; 475 int i; 476 477 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 478 if (ret) 479 return ret; 480 481 rte_spinlock_lock(&hw->lock); 482 cur_addr_num = hw->mc_addrs_num; 483 for (i = 0; i < cur_addr_num; i++) { 484 num = cur_addr_num - i - 1; 485 addr = &hw->mc_addrs[num]; 486 ret = hns3vf_remove_mc_mac_addr(hw, addr); 487 if (ret) { 488 rte_spinlock_unlock(&hw->lock); 489 return ret; 490 } 491 492 hw->mc_addrs_num--; 493 } 494 495 set_addr_num = (int)nb_mc_addr; 496 for (i = 0; i < set_addr_num; i++) { 497 addr = &mc_addr_set[i]; 498 ret = hns3vf_add_mc_mac_addr(hw, addr); 499 if (ret) { 500 rte_spinlock_unlock(&hw->lock); 501 return ret; 502 } 503 504 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]); 505 hw->mc_addrs_num++; 506 } 507 rte_spinlock_unlock(&hw->lock); 508 509 return 0; 510 } 511 512 static int 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 514 { 515 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 516 struct hns3_hw *hw = &hns->hw; 517 struct rte_ether_addr *addr; 518 int err = 0; 519 int ret; 520 int i; 521 522 for (i = 0; i < hw->mc_addrs_num; i++) { 523 addr = &hw->mc_addrs[i]; 524 if (!rte_is_multicast_ether_addr(addr)) 525 continue; 526 if (del) 527 ret = hns3vf_remove_mc_mac_addr(hw, addr); 528 else 529 ret = hns3vf_add_mc_mac_addr(hw, addr); 530 if (ret) { 531 err = ret; 532 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 533 addr); 534 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d", 535 del ? "Remove" : "Restore", mac_str, ret); 536 } 537 } 538 return err; 539 } 540 541 static int 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc, 543 bool en_uc_pmc, bool en_mc_pmc) 544 { 545 struct hns3_mbx_vf_to_pf_cmd *req; 546 struct hns3_cmd_desc desc; 547 int ret; 548 549 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data; 550 551 /* 552 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver, 553 * so there are some features for promiscuous/allmulticast mode in hns3 554 * VF PMD driver as below: 555 * 1. The promiscuous/allmulticast mode can be configured successfully 556 * only based on the trusted VF device. If based on the non trusted 557 * VF device, configuring promiscuous/allmulticast mode will fail. 558 * The hns3 VF device can be confiruged as trusted device by hns3 PF 559 * kernel ethdev driver on the host by the following command: 560 * "ip link set <eth num> vf <vf id> turst on" 561 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD 562 * driver can receive the ingress and outgoing traffic. In the words, 563 * all the ingress packets, all the packets sent from the PF and 564 * other VFs on the same physical port. 565 * 3. Note: Because of the hardware constraints, By default vlan filter 566 * is enabled and couldn't be turned off based on VF device, so vlan 567 * filter is still effective even in promiscuous mode. If upper 568 * applications don't call rte_eth_dev_vlan_filter API function to 569 * set vlan based on VF device, hns3 VF PMD driver will can't receive 570 * the packets with vlan tag in promiscuoue mode. 571 */ 572 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false); 573 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE; 574 req->msg[1] = en_bc_pmc ? 1 : 0; 575 req->msg[2] = en_uc_pmc ? 1 : 0; 576 req->msg[3] = en_mc_pmc ? 1 : 0; 577 578 ret = hns3_cmd_send(hw, &desc, 1); 579 if (ret) 580 hns3_err(hw, "Set promisc mode fail, ret = %d", ret); 581 582 return ret; 583 } 584 585 static int 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev) 587 { 588 struct hns3_adapter *hns = dev->data->dev_private; 589 struct hns3_hw *hw = &hns->hw; 590 int ret; 591 592 ret = hns3vf_set_promisc_mode(hw, true, true, true); 593 if (ret) 594 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d", 595 ret); 596 return ret; 597 } 598 599 static int 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev) 601 { 602 bool allmulti = dev->data->all_multicast ? true : false; 603 struct hns3_adapter *hns = dev->data->dev_private; 604 struct hns3_hw *hw = &hns->hw; 605 int ret; 606 607 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti); 608 if (ret) 609 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d", 610 ret); 611 return ret; 612 } 613 614 static int 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev) 616 { 617 struct hns3_adapter *hns = dev->data->dev_private; 618 struct hns3_hw *hw = &hns->hw; 619 int ret; 620 621 if (dev->data->promiscuous) 622 return 0; 623 624 ret = hns3vf_set_promisc_mode(hw, true, false, true); 625 if (ret) 626 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d", 627 ret); 628 return ret; 629 } 630 631 static int 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev) 633 { 634 struct hns3_adapter *hns = dev->data->dev_private; 635 struct hns3_hw *hw = &hns->hw; 636 int ret; 637 638 if (dev->data->promiscuous) 639 return 0; 640 641 ret = hns3vf_set_promisc_mode(hw, true, false, false); 642 if (ret) 643 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d", 644 ret); 645 return ret; 646 } 647 648 static int 649 hns3vf_restore_promisc(struct hns3_adapter *hns) 650 { 651 struct hns3_hw *hw = &hns->hw; 652 bool allmulti = hw->data->all_multicast ? true : false; 653 654 if (hw->data->promiscuous) 655 return hns3vf_set_promisc_mode(hw, true, true, true); 656 657 return hns3vf_set_promisc_mode(hw, true, false, allmulti); 658 } 659 660 static int 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, 662 bool mmap, enum hns3_ring_type queue_type, 663 uint16_t queue_id) 664 { 665 struct hns3_vf_bind_vector_msg bind_msg; 666 const char *op_str; 667 uint16_t code; 668 int ret; 669 670 memset(&bind_msg, 0, sizeof(bind_msg)); 671 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR : 672 HNS3_MBX_UNMAP_RING_TO_VECTOR; 673 bind_msg.vector_id = vector_id; 674 675 if (queue_type == HNS3_RING_TYPE_RX) 676 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX; 677 else 678 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX; 679 680 bind_msg.param[0].ring_type = queue_type; 681 bind_msg.ring_num = 1; 682 bind_msg.param[0].tqp_index = queue_id; 683 op_str = mmap ? "Map" : "Unmap"; 684 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg, 685 sizeof(bind_msg), false, NULL, 0); 686 if (ret) 687 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.", 688 op_str, queue_id, bind_msg.vector_id, ret); 689 690 return ret; 691 } 692 693 static int 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw) 695 { 696 uint8_t vec; 697 int ret; 698 int i; 699 700 /* 701 * In hns3 network engine, vector 0 is always the misc interrupt of this 702 * function, vector 1~N can be used respectively for the queues of the 703 * function. Tx and Rx queues with the same number share the interrupt 704 * vector. In the initialization clearing the all hardware mapping 705 * relationship configurations between queues and interrupt vectors is 706 * needed, so some error caused by the residual configurations, such as 707 * the unexpected Tx interrupt, can be avoid. Because of the hardware 708 * constraints in hns3 hardware engine, we have to implement clearing 709 * the mapping relationship configurations by binding all queues to the 710 * last interrupt vector and reserving the last interrupt vector. This 711 * method results in a decrease of the maximum queues when upper 712 * applications call the rte_eth_dev_configure API function to enable 713 * Rx interrupt. 714 */ 715 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 716 /* vec - 1: the last interrupt is reserved */ 717 hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1; 718 for (i = 0; i < hw->intr_tqps_num; i++) { 719 /* 720 * Set gap limiter and rate limiter configuration of queue's 721 * interrupt. 722 */ 723 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 724 HNS3_TQP_INTR_GL_DEFAULT); 725 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 726 HNS3_TQP_INTR_GL_DEFAULT); 727 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 728 729 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 730 HNS3_RING_TYPE_TX, i); 731 if (ret) { 732 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with " 733 "vector: %d, ret=%d", i, vec, ret); 734 return ret; 735 } 736 737 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 738 HNS3_RING_TYPE_RX, i); 739 if (ret) { 740 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with " 741 "vector: %d, ret=%d", i, vec, ret); 742 return ret; 743 } 744 } 745 746 return 0; 747 } 748 749 static int 750 hns3vf_dev_configure(struct rte_eth_dev *dev) 751 { 752 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 753 struct hns3_rss_conf *rss_cfg = &hw->rss_info; 754 struct rte_eth_conf *conf = &dev->data->dev_conf; 755 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 756 uint16_t nb_rx_q = dev->data->nb_rx_queues; 757 uint16_t nb_tx_q = dev->data->nb_tx_queues; 758 struct rte_eth_rss_conf rss_conf; 759 uint16_t mtu; 760 bool gro_en; 761 int ret; 762 763 /* 764 * Hardware does not support individually enable/disable/reset the Tx or 765 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx 766 * and Rx queues at the same time. When the numbers of Tx queues 767 * allocated by upper applications are not equal to the numbers of Rx 768 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers 769 * of Tx/Rx queues. otherwise, network engine can not work as usual. But 770 * these fake queues are imperceptible, and can not be used by upper 771 * applications. 772 */ 773 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 774 if (ret) { 775 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret); 776 return ret; 777 } 778 779 hw->adapter_state = HNS3_NIC_CONFIGURING; 780 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 781 hns3_err(hw, "setting link speed/duplex not supported"); 782 ret = -EINVAL; 783 goto cfg_err; 784 } 785 786 /* When RSS is not configured, redirect the packet queue 0 */ 787 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 788 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 789 rss_conf = conf->rx_adv_conf.rss_conf; 790 if (rss_conf.rss_key == NULL) { 791 rss_conf.rss_key = rss_cfg->key; 792 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE; 793 } 794 795 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 796 if (ret) 797 goto cfg_err; 798 } 799 800 /* 801 * If jumbo frames are enabled, MTU needs to be refreshed 802 * according to the maximum RX packet length. 803 */ 804 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 805 /* 806 * Security of max_rx_pkt_len is guaranteed in dpdk frame. 807 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it 808 * can safely assign to "uint16_t" type variable. 809 */ 810 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len); 811 ret = hns3vf_dev_mtu_set(dev, mtu); 812 if (ret) 813 goto cfg_err; 814 dev->data->mtu = mtu; 815 } 816 817 ret = hns3vf_dev_configure_vlan(dev); 818 if (ret) 819 goto cfg_err; 820 821 /* config hardware GRO */ 822 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 823 ret = hns3_config_gro(hw, gro_en); 824 if (ret) 825 goto cfg_err; 826 827 hw->adapter_state = HNS3_NIC_CONFIGURED; 828 return 0; 829 830 cfg_err: 831 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 832 hw->adapter_state = HNS3_NIC_INITIALIZED; 833 834 return ret; 835 } 836 837 static int 838 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu) 839 { 840 int ret; 841 842 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu, 843 sizeof(mtu), true, NULL, 0); 844 if (ret) 845 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret); 846 847 return ret; 848 } 849 850 static int 851 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 852 { 853 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 854 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 855 int ret; 856 857 /* 858 * The hns3 PF/VF devices on the same port share the hardware MTU 859 * configuration. Currently, we send mailbox to inform hns3 PF kernel 860 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD 861 * driver, there is no need to stop the port for hns3 VF device, and the 862 * MTU value issued by hns3 VF PMD driver must be less than or equal to 863 * PF's MTU. 864 */ 865 if (rte_atomic16_read(&hw->reset.resetting)) { 866 hns3_err(hw, "Failed to set mtu during resetting"); 867 return -EIO; 868 } 869 870 rte_spinlock_lock(&hw->lock); 871 ret = hns3vf_config_mtu(hw, mtu); 872 if (ret) { 873 rte_spinlock_unlock(&hw->lock); 874 return ret; 875 } 876 if (frame_size > RTE_ETHER_MAX_LEN) 877 dev->data->dev_conf.rxmode.offloads |= 878 DEV_RX_OFFLOAD_JUMBO_FRAME; 879 else 880 dev->data->dev_conf.rxmode.offloads &= 881 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 882 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 883 rte_spinlock_unlock(&hw->lock); 884 885 return 0; 886 } 887 888 static int 889 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 890 { 891 struct hns3_adapter *hns = eth_dev->data->dev_private; 892 struct hns3_hw *hw = &hns->hw; 893 uint16_t q_num = hw->tqps_num; 894 895 /* 896 * In interrupt mode, 'max_rx_queues' is set based on the number of 897 * MSI-X interrupt resources of the hardware. 898 */ 899 if (hw->data->dev_conf.intr_conf.rxq == 1) 900 q_num = hw->intr_tqps_num; 901 902 info->max_rx_queues = q_num; 903 info->max_tx_queues = hw->tqps_num; 904 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 905 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 906 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; 907 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 908 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 909 910 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 911 DEV_RX_OFFLOAD_UDP_CKSUM | 912 DEV_RX_OFFLOAD_TCP_CKSUM | 913 DEV_RX_OFFLOAD_SCTP_CKSUM | 914 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 915 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 916 DEV_RX_OFFLOAD_SCATTER | 917 DEV_RX_OFFLOAD_VLAN_STRIP | 918 DEV_RX_OFFLOAD_VLAN_FILTER | 919 DEV_RX_OFFLOAD_JUMBO_FRAME | 920 DEV_RX_OFFLOAD_RSS_HASH | 921 DEV_RX_OFFLOAD_TCP_LRO); 922 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 923 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 924 DEV_TX_OFFLOAD_IPV4_CKSUM | 925 DEV_TX_OFFLOAD_TCP_CKSUM | 926 DEV_TX_OFFLOAD_UDP_CKSUM | 927 DEV_TX_OFFLOAD_SCTP_CKSUM | 928 DEV_TX_OFFLOAD_MULTI_SEGS | 929 DEV_TX_OFFLOAD_TCP_TSO | 930 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 931 DEV_TX_OFFLOAD_GRE_TNL_TSO | 932 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 933 info->tx_queue_offload_capa | 934 hns3_txvlan_cap_get(hw)); 935 936 info->rx_desc_lim = (struct rte_eth_desc_lim) { 937 .nb_max = HNS3_MAX_RING_DESC, 938 .nb_min = HNS3_MIN_RING_DESC, 939 .nb_align = HNS3_ALIGN_RING_DESC, 940 }; 941 942 info->tx_desc_lim = (struct rte_eth_desc_lim) { 943 .nb_max = HNS3_MAX_RING_DESC, 944 .nb_min = HNS3_MIN_RING_DESC, 945 .nb_align = HNS3_ALIGN_RING_DESC, 946 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 947 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT, 948 }; 949 950 info->vmdq_queue_num = 0; 951 952 info->reta_size = HNS3_RSS_IND_TBL_SIZE; 953 info->hash_key_size = HNS3_RSS_KEY_SIZE; 954 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 955 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 956 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 957 958 return 0; 959 } 960 961 static void 962 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr) 963 { 964 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 965 } 966 967 static void 968 hns3vf_disable_irq0(struct hns3_hw *hw) 969 { 970 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 971 } 972 973 static void 974 hns3vf_enable_irq0(struct hns3_hw *hw) 975 { 976 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 977 } 978 979 static enum hns3vf_evt_cause 980 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 981 { 982 struct hns3_hw *hw = &hns->hw; 983 enum hns3vf_evt_cause ret; 984 uint32_t cmdq_stat_reg; 985 uint32_t rst_ing_reg; 986 uint32_t val; 987 988 /* Fetch the events from their corresponding regs */ 989 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG); 990 991 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 992 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING); 993 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg); 994 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 995 rte_atomic16_set(&hw->reset.disable_cmd, 1); 996 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 997 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT); 998 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B); 999 if (clearval) { 1000 hw->reset.stats.global_cnt++; 1001 hns3_warn(hw, "Global reset detected, clear reset status"); 1002 } else { 1003 hns3_schedule_delayed_reset(hns); 1004 hns3_warn(hw, "Global reset detected, don't clear reset status"); 1005 } 1006 1007 ret = HNS3VF_VECTOR0_EVENT_RST; 1008 goto out; 1009 } 1010 1011 /* Check for vector0 mailbox(=CMDQ RX) event source */ 1012 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1013 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 1014 ret = HNS3VF_VECTOR0_EVENT_MBX; 1015 goto out; 1016 } 1017 1018 val = 0; 1019 ret = HNS3VF_VECTOR0_EVENT_OTHER; 1020 out: 1021 if (clearval) 1022 *clearval = val; 1023 return ret; 1024 } 1025 1026 static void 1027 hns3vf_interrupt_handler(void *param) 1028 { 1029 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1030 struct hns3_adapter *hns = dev->data->dev_private; 1031 struct hns3_hw *hw = &hns->hw; 1032 enum hns3vf_evt_cause event_cause; 1033 uint32_t clearval; 1034 1035 if (hw->irq_thread_id == 0) 1036 hw->irq_thread_id = pthread_self(); 1037 1038 /* Disable interrupt */ 1039 hns3vf_disable_irq0(hw); 1040 1041 /* Read out interrupt causes */ 1042 event_cause = hns3vf_check_event_cause(hns, &clearval); 1043 1044 switch (event_cause) { 1045 case HNS3VF_VECTOR0_EVENT_RST: 1046 hns3_schedule_reset(hns); 1047 break; 1048 case HNS3VF_VECTOR0_EVENT_MBX: 1049 hns3_dev_handle_mbx_msg(hw); 1050 break; 1051 default: 1052 break; 1053 } 1054 1055 /* Clear interrupt causes */ 1056 hns3vf_clear_event_cause(hw, clearval); 1057 1058 /* Enable interrupt */ 1059 hns3vf_enable_irq0(hw); 1060 } 1061 1062 static int 1063 hns3vf_get_capability(struct hns3_hw *hw) 1064 { 1065 struct rte_pci_device *pci_dev; 1066 struct rte_eth_dev *eth_dev; 1067 uint8_t revision; 1068 int ret; 1069 1070 eth_dev = &rte_eth_devices[hw->data->port_id]; 1071 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1072 1073 /* Get PCI revision id */ 1074 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 1075 HNS3_PCI_REVISION_ID); 1076 if (ret != HNS3_PCI_REVISION_ID_LEN) { 1077 PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret); 1078 return -EIO; 1079 } 1080 hw->revision = revision; 1081 1082 return 0; 1083 } 1084 1085 static int 1086 hns3vf_check_tqp_info(struct hns3_hw *hw) 1087 { 1088 uint16_t tqps_num; 1089 1090 tqps_num = hw->tqps_num; 1091 if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) { 1092 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid " 1093 "range: 1~%d", 1094 tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 1095 return -EINVAL; 1096 } 1097 1098 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num); 1099 1100 return 0; 1101 } 1102 static int 1103 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw) 1104 { 1105 uint8_t resp_msg; 1106 int ret; 1107 1108 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, 1109 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0, 1110 true, &resp_msg, sizeof(resp_msg)); 1111 if (ret) { 1112 if (ret == -ETIME) { 1113 /* 1114 * Getting current port based VLAN state from PF driver 1115 * will not affect VF driver's basic function. Because 1116 * the VF driver relies on hns3 PF kernel ether driver, 1117 * to avoid introducing compatibility issues with older 1118 * version of PF driver, no failure will be returned 1119 * when the return value is ETIME. This return value has 1120 * the following scenarios: 1121 * 1) Firmware didn't return the results in time 1122 * 2) the result return by firmware is timeout 1123 * 3) the older version of kernel side PF driver does 1124 * not support this mailbox message. 1125 * For scenarios 1 and 2, it is most likely that a 1126 * hardware error has occurred, or a hardware reset has 1127 * occurred. In this case, these errors will be caught 1128 * by other functions. 1129 */ 1130 PMD_INIT_LOG(WARNING, 1131 "failed to get PVID state for timeout, maybe " 1132 "kernel side PF driver doesn't support this " 1133 "mailbox message, or firmware didn't respond."); 1134 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE; 1135 } else { 1136 PMD_INIT_LOG(ERR, "failed to get port based VLAN state," 1137 " ret = %d", ret); 1138 return ret; 1139 } 1140 } 1141 hw->port_base_vlan_cfg.state = resp_msg ? 1142 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 1143 return 0; 1144 } 1145 1146 static int 1147 hns3vf_get_queue_info(struct hns3_hw *hw) 1148 { 1149 #define HNS3VF_TQPS_RSS_INFO_LEN 6 1150 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN]; 1151 int ret; 1152 1153 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true, 1154 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN); 1155 if (ret) { 1156 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret); 1157 return ret; 1158 } 1159 1160 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t)); 1161 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t)); 1162 1163 return hns3vf_check_tqp_info(hw); 1164 } 1165 1166 static int 1167 hns3vf_get_queue_depth(struct hns3_hw *hw) 1168 { 1169 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4 1170 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN]; 1171 int ret; 1172 1173 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true, 1174 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN); 1175 if (ret) { 1176 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d", 1177 ret); 1178 return ret; 1179 } 1180 1181 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t)); 1182 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t)); 1183 1184 return 0; 1185 } 1186 1187 static int 1188 hns3vf_get_tc_info(struct hns3_hw *hw) 1189 { 1190 uint8_t resp_msg; 1191 int ret; 1192 1193 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0, 1194 true, &resp_msg, sizeof(resp_msg)); 1195 if (ret) { 1196 hns3_err(hw, "VF request to get TC info from PF failed %d", 1197 ret); 1198 return ret; 1199 } 1200 1201 hw->hw_tc_map = resp_msg; 1202 1203 return 0; 1204 } 1205 1206 static int 1207 hns3vf_get_host_mac_addr(struct hns3_hw *hw) 1208 { 1209 uint8_t host_mac[RTE_ETHER_ADDR_LEN]; 1210 int ret; 1211 1212 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0, 1213 true, host_mac, RTE_ETHER_ADDR_LEN); 1214 if (ret) { 1215 hns3_err(hw, "Failed to get mac addr from PF: %d", ret); 1216 return ret; 1217 } 1218 1219 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN); 1220 1221 return 0; 1222 } 1223 1224 static int 1225 hns3vf_get_configuration(struct hns3_hw *hw) 1226 { 1227 int ret; 1228 1229 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE; 1230 hw->rss_dis_flag = false; 1231 1232 /* Get device capability */ 1233 ret = hns3vf_get_capability(hw); 1234 if (ret) { 1235 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 1236 return ret; 1237 } 1238 1239 /* Get queue configuration from PF */ 1240 ret = hns3vf_get_queue_info(hw); 1241 if (ret) 1242 return ret; 1243 1244 /* Get queue depth info from PF */ 1245 ret = hns3vf_get_queue_depth(hw); 1246 if (ret) 1247 return ret; 1248 1249 /* Get user defined VF MAC addr from PF */ 1250 ret = hns3vf_get_host_mac_addr(hw); 1251 if (ret) 1252 return ret; 1253 1254 ret = hns3vf_get_port_base_vlan_filter_state(hw); 1255 if (ret) 1256 return ret; 1257 1258 /* Get tc configuration from PF */ 1259 return hns3vf_get_tc_info(hw); 1260 } 1261 1262 static int 1263 hns3vf_set_tc_info(struct hns3_adapter *hns) 1264 { 1265 struct hns3_hw *hw = &hns->hw; 1266 uint16_t nb_rx_q = hw->data->nb_rx_queues; 1267 uint16_t nb_tx_q = hw->data->nb_tx_queues; 1268 uint8_t i; 1269 1270 hw->num_tc = 0; 1271 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 1272 if (hw->hw_tc_map & BIT(i)) 1273 hw->num_tc++; 1274 1275 if (nb_rx_q < hw->num_tc) { 1276 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).", 1277 nb_rx_q, hw->num_tc); 1278 return -EINVAL; 1279 } 1280 1281 if (nb_tx_q < hw->num_tc) { 1282 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).", 1283 nb_tx_q, hw->num_tc); 1284 return -EINVAL; 1285 } 1286 1287 hns3_set_rss_size(hw, nb_rx_q); 1288 hns3_tc_queue_mapping_cfg(hw, nb_tx_q); 1289 1290 return 0; 1291 } 1292 1293 static void 1294 hns3vf_request_link_info(struct hns3_hw *hw) 1295 { 1296 uint8_t resp_msg; 1297 int ret; 1298 1299 if (rte_atomic16_read(&hw->reset.resetting)) 1300 return; 1301 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false, 1302 &resp_msg, sizeof(resp_msg)); 1303 if (ret) 1304 hns3_err(hw, "Failed to fetch link status from PF: %d", ret); 1305 } 1306 1307 static int 1308 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 1309 { 1310 #define HNS3VF_VLAN_MBX_MSG_LEN 5 1311 struct hns3_hw *hw = &hns->hw; 1312 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN]; 1313 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN); 1314 uint8_t is_kill = on ? 0 : 1; 1315 1316 msg_data[0] = is_kill; 1317 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1318 memcpy(&msg_data[3], &proto, sizeof(proto)); 1319 1320 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER, 1321 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL, 1322 0); 1323 } 1324 1325 static int 1326 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1327 { 1328 struct hns3_adapter *hns = dev->data->dev_private; 1329 struct hns3_hw *hw = &hns->hw; 1330 int ret; 1331 1332 if (rte_atomic16_read(&hw->reset.resetting)) { 1333 hns3_err(hw, 1334 "vf set vlan id failed during resetting, vlan_id =%u", 1335 vlan_id); 1336 return -EIO; 1337 } 1338 rte_spinlock_lock(&hw->lock); 1339 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1340 rte_spinlock_unlock(&hw->lock); 1341 if (ret) 1342 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d", 1343 vlan_id, ret); 1344 1345 return ret; 1346 } 1347 1348 static int 1349 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable) 1350 { 1351 uint8_t msg_data; 1352 int ret; 1353 1354 msg_data = enable ? 1 : 0; 1355 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG, 1356 &msg_data, sizeof(msg_data), false, NULL, 0); 1357 if (ret) 1358 hns3_err(hw, "vf enable strip failed, ret =%d", ret); 1359 1360 return ret; 1361 } 1362 1363 static int 1364 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1365 { 1366 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1367 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1368 unsigned int tmp_mask; 1369 int ret = 0; 1370 1371 if (rte_atomic16_read(&hw->reset.resetting)) { 1372 hns3_err(hw, "vf set vlan offload failed during resetting, " 1373 "mask = 0x%x", mask); 1374 return -EIO; 1375 } 1376 1377 tmp_mask = (unsigned int)mask; 1378 /* Vlan stripping setting */ 1379 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 1380 rte_spinlock_lock(&hw->lock); 1381 /* Enable or disable VLAN stripping */ 1382 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1383 ret = hns3vf_en_hw_strip_rxvtag(hw, true); 1384 else 1385 ret = hns3vf_en_hw_strip_rxvtag(hw, false); 1386 rte_spinlock_unlock(&hw->lock); 1387 } 1388 1389 return ret; 1390 } 1391 1392 static int 1393 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on) 1394 { 1395 struct rte_vlan_filter_conf *vfc; 1396 struct hns3_hw *hw = &hns->hw; 1397 uint16_t vlan_id; 1398 uint64_t vbit; 1399 uint64_t ids; 1400 int ret = 0; 1401 uint32_t i; 1402 1403 vfc = &hw->data->vlan_filter_conf; 1404 for (i = 0; i < RTE_DIM(vfc->ids); i++) { 1405 if (vfc->ids[i] == 0) 1406 continue; 1407 ids = vfc->ids[i]; 1408 while (ids) { 1409 /* 1410 * 64 means the num bits of ids, one bit corresponds to 1411 * one vlan id 1412 */ 1413 vlan_id = 64 * i; 1414 /* count trailing zeroes */ 1415 vbit = ~ids & (ids - 1); 1416 /* clear least significant bit set */ 1417 ids ^= (ids ^ (ids - 1)) ^ vbit; 1418 for (; vbit;) { 1419 vbit >>= 1; 1420 vlan_id++; 1421 } 1422 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1423 if (ret) { 1424 hns3_err(hw, 1425 "VF handle vlan table failed, ret =%d, on = %d", 1426 ret, on); 1427 return ret; 1428 } 1429 } 1430 } 1431 1432 return ret; 1433 } 1434 1435 static int 1436 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns) 1437 { 1438 return hns3vf_handle_all_vlan_table(hns, 0); 1439 } 1440 1441 static int 1442 hns3vf_restore_vlan_conf(struct hns3_adapter *hns) 1443 { 1444 struct hns3_hw *hw = &hns->hw; 1445 struct rte_eth_conf *dev_conf; 1446 bool en; 1447 int ret; 1448 1449 dev_conf = &hw->data->dev_conf; 1450 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true 1451 : false; 1452 ret = hns3vf_en_hw_strip_rxvtag(hw, en); 1453 if (ret) 1454 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en, 1455 ret); 1456 return ret; 1457 } 1458 1459 static int 1460 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev) 1461 { 1462 struct hns3_adapter *hns = dev->data->dev_private; 1463 struct rte_eth_dev_data *data = dev->data; 1464 struct hns3_hw *hw = &hns->hw; 1465 int ret; 1466 1467 if (data->dev_conf.txmode.hw_vlan_reject_tagged || 1468 data->dev_conf.txmode.hw_vlan_reject_untagged || 1469 data->dev_conf.txmode.hw_vlan_insert_pvid) { 1470 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged " 1471 "or hw_vlan_insert_pvid is not support!"); 1472 } 1473 1474 /* Apply vlan offload setting */ 1475 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK); 1476 if (ret) 1477 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret); 1478 1479 return ret; 1480 } 1481 1482 static int 1483 hns3vf_set_alive(struct hns3_hw *hw, bool alive) 1484 { 1485 uint8_t msg_data; 1486 1487 msg_data = alive ? 1 : 0; 1488 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data, 1489 sizeof(msg_data), false, NULL, 0); 1490 } 1491 1492 static void 1493 hns3vf_keep_alive_handler(void *param) 1494 { 1495 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1496 struct hns3_adapter *hns = eth_dev->data->dev_private; 1497 struct hns3_hw *hw = &hns->hw; 1498 uint8_t respmsg; 1499 int ret; 1500 1501 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0, 1502 false, &respmsg, sizeof(uint8_t)); 1503 if (ret) 1504 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)", 1505 ret); 1506 1507 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 1508 eth_dev); 1509 } 1510 1511 static void 1512 hns3vf_service_handler(void *param) 1513 { 1514 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1515 struct hns3_adapter *hns = eth_dev->data->dev_private; 1516 struct hns3_hw *hw = &hns->hw; 1517 1518 /* 1519 * The query link status and reset processing are executed in the 1520 * interrupt thread.When the IMP reset occurs, IMP will not respond, 1521 * and the query operation will time out after 30ms. In the case of 1522 * multiple PF/VFs, each query failure timeout causes the IMP reset 1523 * interrupt to fail to respond within 100ms. 1524 * Before querying the link status, check whether there is a reset 1525 * pending, and if so, abandon the query. 1526 */ 1527 if (!hns3vf_is_reset_pending(hns)) 1528 hns3vf_request_link_info(hw); 1529 else 1530 hns3_warn(hw, "Cancel the query when reset is pending"); 1531 1532 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, 1533 eth_dev); 1534 } 1535 1536 static int 1537 hns3_query_vf_resource(struct hns3_hw *hw) 1538 { 1539 struct hns3_vf_res_cmd *req; 1540 struct hns3_cmd_desc desc; 1541 uint16_t num_msi; 1542 int ret; 1543 1544 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true); 1545 ret = hns3_cmd_send(hw, &desc, 1); 1546 if (ret) { 1547 hns3_err(hw, "query vf resource failed, ret = %d", ret); 1548 return ret; 1549 } 1550 1551 req = (struct hns3_vf_res_cmd *)desc.data; 1552 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number), 1553 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S); 1554 if (num_msi < HNS3_MIN_VECTOR_NUM) { 1555 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)", 1556 num_msi, HNS3_MIN_VECTOR_NUM); 1557 return -EINVAL; 1558 } 1559 1560 hw->num_msi = num_msi; 1561 1562 return 0; 1563 } 1564 1565 static int 1566 hns3vf_init_hardware(struct hns3_adapter *hns) 1567 { 1568 struct hns3_hw *hw = &hns->hw; 1569 uint16_t mtu = hw->data->mtu; 1570 int ret; 1571 1572 ret = hns3vf_set_promisc_mode(hw, true, false, false); 1573 if (ret) 1574 return ret; 1575 1576 ret = hns3vf_config_mtu(hw, mtu); 1577 if (ret) 1578 goto err_init_hardware; 1579 1580 ret = hns3vf_vlan_filter_configure(hns, 0, 1); 1581 if (ret) { 1582 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret); 1583 goto err_init_hardware; 1584 } 1585 1586 ret = hns3_config_gro(hw, false); 1587 if (ret) { 1588 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 1589 goto err_init_hardware; 1590 } 1591 1592 /* 1593 * In the initialization clearing the all hardware mapping relationship 1594 * configurations between queues and interrupt vectors is needed, so 1595 * some error caused by the residual configurations, such as the 1596 * unexpected interrupt, can be avoid. 1597 */ 1598 ret = hns3vf_init_ring_with_vector(hw); 1599 if (ret) { 1600 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 1601 goto err_init_hardware; 1602 } 1603 1604 ret = hns3vf_set_alive(hw, true); 1605 if (ret) { 1606 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret); 1607 goto err_init_hardware; 1608 } 1609 1610 hns3vf_request_link_info(hw); 1611 return 0; 1612 1613 err_init_hardware: 1614 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1615 return ret; 1616 } 1617 1618 static int 1619 hns3vf_clear_vport_list(struct hns3_hw *hw) 1620 { 1621 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL, 1622 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false, 1623 NULL, 0); 1624 } 1625 1626 static int 1627 hns3vf_init_vf(struct rte_eth_dev *eth_dev) 1628 { 1629 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1630 struct hns3_adapter *hns = eth_dev->data->dev_private; 1631 struct hns3_hw *hw = &hns->hw; 1632 int ret; 1633 1634 PMD_INIT_FUNC_TRACE(); 1635 1636 /* Get hardware io base address from pcie BAR2 IO space */ 1637 hw->io_base = pci_dev->mem_resource[2].addr; 1638 1639 /* Firmware command queue initialize */ 1640 ret = hns3_cmd_init_queue(hw); 1641 if (ret) { 1642 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 1643 goto err_cmd_init_queue; 1644 } 1645 1646 /* Firmware command initialize */ 1647 ret = hns3_cmd_init(hw); 1648 if (ret) { 1649 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 1650 goto err_cmd_init; 1651 } 1652 1653 /* Get VF resource */ 1654 ret = hns3_query_vf_resource(hw); 1655 if (ret) 1656 goto err_cmd_init; 1657 1658 rte_spinlock_init(&hw->mbx_resp.lock); 1659 1660 hns3vf_clear_event_cause(hw, 0); 1661 1662 ret = rte_intr_callback_register(&pci_dev->intr_handle, 1663 hns3vf_interrupt_handler, eth_dev); 1664 if (ret) { 1665 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 1666 goto err_intr_callback_register; 1667 } 1668 1669 /* Enable interrupt */ 1670 rte_intr_enable(&pci_dev->intr_handle); 1671 hns3vf_enable_irq0(hw); 1672 1673 /* Get configuration from PF */ 1674 ret = hns3vf_get_configuration(hw); 1675 if (ret) { 1676 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 1677 goto err_get_config; 1678 } 1679 1680 /* 1681 * The hns3 PF ethdev driver in kernel support setting VF MAC address 1682 * on the host by "ip link set ..." command. To avoid some incorrect 1683 * scenes, for example, hns3 VF PMD driver fails to receive and send 1684 * packets after user configure the MAC address by using the 1685 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC 1686 * address strategy as the hns3 kernel ethdev driver in the 1687 * initialization. If user configure a MAC address by the ip command 1688 * for VF device, then hns3 VF PMD driver will start with it, otherwise 1689 * start with a random MAC address in the initialization. 1690 */ 1691 ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr); 1692 if (ret) 1693 rte_eth_random_addr(hw->mac.mac_addr); 1694 1695 ret = hns3vf_clear_vport_list(hw); 1696 if (ret) { 1697 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret); 1698 goto err_get_config; 1699 } 1700 1701 ret = hns3vf_init_hardware(hns); 1702 if (ret) 1703 goto err_get_config; 1704 1705 hns3_set_default_rss_args(hw); 1706 1707 return 0; 1708 1709 err_get_config: 1710 hns3vf_disable_irq0(hw); 1711 rte_intr_disable(&pci_dev->intr_handle); 1712 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 1713 eth_dev); 1714 err_intr_callback_register: 1715 err_cmd_init: 1716 hns3_cmd_uninit(hw); 1717 hns3_cmd_destroy_queue(hw); 1718 err_cmd_init_queue: 1719 hw->io_base = NULL; 1720 1721 return ret; 1722 } 1723 1724 static void 1725 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev) 1726 { 1727 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1728 struct hns3_adapter *hns = eth_dev->data->dev_private; 1729 struct hns3_hw *hw = &hns->hw; 1730 1731 PMD_INIT_FUNC_TRACE(); 1732 1733 hns3_rss_uninit(hns); 1734 (void)hns3_config_gro(hw, false); 1735 (void)hns3vf_set_alive(hw, false); 1736 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1737 hns3vf_disable_irq0(hw); 1738 rte_intr_disable(&pci_dev->intr_handle); 1739 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 1740 eth_dev); 1741 hns3_cmd_uninit(hw); 1742 hns3_cmd_destroy_queue(hw); 1743 hw->io_base = NULL; 1744 } 1745 1746 static int 1747 hns3vf_do_stop(struct hns3_adapter *hns) 1748 { 1749 struct hns3_hw *hw = &hns->hw; 1750 bool reset_queue; 1751 1752 hw->mac.link_status = ETH_LINK_DOWN; 1753 1754 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) { 1755 hns3vf_configure_mac_addr(hns, true); 1756 reset_queue = true; 1757 } else 1758 reset_queue = false; 1759 return hns3_stop_queues(hns, reset_queue); 1760 } 1761 1762 static void 1763 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev) 1764 { 1765 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1766 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1767 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1768 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 1769 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 1770 uint16_t q_id; 1771 1772 if (dev->data->dev_conf.intr_conf.rxq == 0) 1773 return; 1774 1775 /* unmap the ring with vector */ 1776 if (rte_intr_allow_others(intr_handle)) { 1777 vec = RTE_INTR_VEC_RXTX_OFFSET; 1778 base = RTE_INTR_VEC_RXTX_OFFSET; 1779 } 1780 if (rte_intr_dp_is_en(intr_handle)) { 1781 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 1782 (void)hns3vf_bind_ring_with_vector(hw, vec, false, 1783 HNS3_RING_TYPE_RX, 1784 q_id); 1785 if (vec < base + intr_handle->nb_efd - 1) 1786 vec++; 1787 } 1788 } 1789 /* Clean datapath event and queue/vec mapping */ 1790 rte_intr_efd_disable(intr_handle); 1791 if (intr_handle->intr_vec) { 1792 rte_free(intr_handle->intr_vec); 1793 intr_handle->intr_vec = NULL; 1794 } 1795 } 1796 1797 static void 1798 hns3vf_dev_stop(struct rte_eth_dev *dev) 1799 { 1800 struct hns3_adapter *hns = dev->data->dev_private; 1801 struct hns3_hw *hw = &hns->hw; 1802 1803 PMD_INIT_FUNC_TRACE(); 1804 1805 hw->adapter_state = HNS3_NIC_STOPPING; 1806 hns3_set_rxtx_function(dev); 1807 rte_wmb(); 1808 /* Disable datapath on secondary process. */ 1809 hns3_mp_req_stop_rxtx(dev); 1810 /* Prevent crashes when queues are still in use. */ 1811 rte_delay_ms(hw->tqps_num); 1812 1813 rte_spinlock_lock(&hw->lock); 1814 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 1815 hns3vf_do_stop(hns); 1816 hns3vf_unmap_rx_interrupt(dev); 1817 hns3_dev_release_mbufs(hns); 1818 hw->adapter_state = HNS3_NIC_CONFIGURED; 1819 } 1820 rte_eal_alarm_cancel(hns3vf_service_handler, dev); 1821 rte_spinlock_unlock(&hw->lock); 1822 } 1823 1824 static void 1825 hns3vf_dev_close(struct rte_eth_dev *eth_dev) 1826 { 1827 struct hns3_adapter *hns = eth_dev->data->dev_private; 1828 struct hns3_hw *hw = &hns->hw; 1829 1830 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1831 return; 1832 1833 if (hw->adapter_state == HNS3_NIC_STARTED) 1834 hns3vf_dev_stop(eth_dev); 1835 1836 hw->adapter_state = HNS3_NIC_CLOSING; 1837 hns3_reset_abort(hns); 1838 hw->adapter_state = HNS3_NIC_CLOSED; 1839 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev); 1840 hns3vf_configure_all_mc_mac_addr(hns, true); 1841 hns3vf_remove_all_vlan_table(hns); 1842 hns3vf_uninit_vf(eth_dev); 1843 hns3_free_all_queues(eth_dev); 1844 rte_free(hw->reset.wait_data); 1845 rte_free(eth_dev->process_private); 1846 eth_dev->process_private = NULL; 1847 hns3_mp_uninit_primary(); 1848 hns3_warn(hw, "Close port %d finished", hw->data->port_id); 1849 } 1850 1851 static int 1852 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 1853 size_t fw_size) 1854 { 1855 struct hns3_adapter *hns = eth_dev->data->dev_private; 1856 struct hns3_hw *hw = &hns->hw; 1857 uint32_t version = hw->fw_version; 1858 int ret; 1859 1860 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 1861 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 1862 HNS3_FW_VERSION_BYTE3_S), 1863 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 1864 HNS3_FW_VERSION_BYTE2_S), 1865 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 1866 HNS3_FW_VERSION_BYTE1_S), 1867 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 1868 HNS3_FW_VERSION_BYTE0_S)); 1869 ret += 1; /* add the size of '\0' */ 1870 if (fw_size < (uint32_t)ret) 1871 return ret; 1872 else 1873 return 0; 1874 } 1875 1876 static int 1877 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, 1878 __rte_unused int wait_to_complete) 1879 { 1880 struct hns3_adapter *hns = eth_dev->data->dev_private; 1881 struct hns3_hw *hw = &hns->hw; 1882 struct hns3_mac *mac = &hw->mac; 1883 struct rte_eth_link new_link; 1884 1885 memset(&new_link, 0, sizeof(new_link)); 1886 switch (mac->link_speed) { 1887 case ETH_SPEED_NUM_10M: 1888 case ETH_SPEED_NUM_100M: 1889 case ETH_SPEED_NUM_1G: 1890 case ETH_SPEED_NUM_10G: 1891 case ETH_SPEED_NUM_25G: 1892 case ETH_SPEED_NUM_40G: 1893 case ETH_SPEED_NUM_50G: 1894 case ETH_SPEED_NUM_100G: 1895 case ETH_SPEED_NUM_200G: 1896 new_link.link_speed = mac->link_speed; 1897 break; 1898 default: 1899 new_link.link_speed = ETH_SPEED_NUM_100M; 1900 break; 1901 } 1902 1903 new_link.link_duplex = mac->link_duplex; 1904 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 1905 new_link.link_autoneg = 1906 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 1907 1908 return rte_eth_linkstatus_set(eth_dev, &new_link); 1909 } 1910 1911 static int 1912 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue) 1913 { 1914 struct hns3_hw *hw = &hns->hw; 1915 int ret; 1916 1917 ret = hns3vf_set_tc_info(hns); 1918 if (ret) 1919 return ret; 1920 1921 ret = hns3_start_queues(hns, reset_queue); 1922 if (ret) 1923 hns3_err(hw, "Failed to start queues: %d", ret); 1924 1925 return ret; 1926 } 1927 1928 static int 1929 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) 1930 { 1931 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1932 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1933 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1934 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 1935 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 1936 uint32_t intr_vector; 1937 uint16_t q_id; 1938 int ret; 1939 1940 if (dev->data->dev_conf.intr_conf.rxq == 0) 1941 return 0; 1942 1943 /* disable uio/vfio intr/eventfd mapping */ 1944 rte_intr_disable(intr_handle); 1945 1946 /* check and configure queue intr-vector mapping */ 1947 if (rte_intr_cap_multiple(intr_handle) || 1948 !RTE_ETH_DEV_SRIOV(dev).active) { 1949 intr_vector = hw->used_rx_queues; 1950 /* It creates event fd for each intr vector when MSIX is used */ 1951 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1952 return -EINVAL; 1953 } 1954 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1955 intr_handle->intr_vec = 1956 rte_zmalloc("intr_vec", 1957 hw->used_rx_queues * sizeof(int), 0); 1958 if (intr_handle->intr_vec == NULL) { 1959 hns3_err(hw, "Failed to allocate %d rx_queues" 1960 " intr_vec", hw->used_rx_queues); 1961 ret = -ENOMEM; 1962 goto vf_alloc_intr_vec_error; 1963 } 1964 } 1965 1966 if (rte_intr_allow_others(intr_handle)) { 1967 vec = RTE_INTR_VEC_RXTX_OFFSET; 1968 base = RTE_INTR_VEC_RXTX_OFFSET; 1969 } 1970 if (rte_intr_dp_is_en(intr_handle)) { 1971 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 1972 ret = hns3vf_bind_ring_with_vector(hw, vec, true, 1973 HNS3_RING_TYPE_RX, 1974 q_id); 1975 if (ret) 1976 goto vf_bind_vector_error; 1977 intr_handle->intr_vec[q_id] = vec; 1978 if (vec < base + intr_handle->nb_efd - 1) 1979 vec++; 1980 } 1981 } 1982 rte_intr_enable(intr_handle); 1983 return 0; 1984 1985 vf_bind_vector_error: 1986 rte_intr_efd_disable(intr_handle); 1987 if (intr_handle->intr_vec) { 1988 free(intr_handle->intr_vec); 1989 intr_handle->intr_vec = NULL; 1990 } 1991 return ret; 1992 vf_alloc_intr_vec_error: 1993 rte_intr_efd_disable(intr_handle); 1994 return ret; 1995 } 1996 1997 static int 1998 hns3vf_restore_rx_interrupt(struct hns3_hw *hw) 1999 { 2000 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 2001 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2002 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2003 uint16_t q_id; 2004 int ret; 2005 2006 if (dev->data->dev_conf.intr_conf.rxq == 0) 2007 return 0; 2008 2009 if (rte_intr_dp_is_en(intr_handle)) { 2010 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2011 ret = hns3vf_bind_ring_with_vector(hw, 2012 intr_handle->intr_vec[q_id], true, 2013 HNS3_RING_TYPE_RX, q_id); 2014 if (ret) 2015 return ret; 2016 } 2017 } 2018 2019 return 0; 2020 } 2021 2022 static void 2023 hns3vf_restore_filter(struct rte_eth_dev *dev) 2024 { 2025 hns3_restore_rss_filter(dev); 2026 } 2027 2028 static int 2029 hns3vf_dev_start(struct rte_eth_dev *dev) 2030 { 2031 struct hns3_adapter *hns = dev->data->dev_private; 2032 struct hns3_hw *hw = &hns->hw; 2033 int ret; 2034 2035 PMD_INIT_FUNC_TRACE(); 2036 if (rte_atomic16_read(&hw->reset.resetting)) 2037 return -EBUSY; 2038 2039 rte_spinlock_lock(&hw->lock); 2040 hw->adapter_state = HNS3_NIC_STARTING; 2041 ret = hns3vf_do_start(hns, true); 2042 if (ret) { 2043 hw->adapter_state = HNS3_NIC_CONFIGURED; 2044 rte_spinlock_unlock(&hw->lock); 2045 return ret; 2046 } 2047 ret = hns3vf_map_rx_interrupt(dev); 2048 if (ret) { 2049 hw->adapter_state = HNS3_NIC_CONFIGURED; 2050 rte_spinlock_unlock(&hw->lock); 2051 return ret; 2052 } 2053 hw->adapter_state = HNS3_NIC_STARTED; 2054 rte_spinlock_unlock(&hw->lock); 2055 2056 hns3_set_rxtx_function(dev); 2057 hns3_mp_req_start_rxtx(dev); 2058 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev); 2059 2060 hns3vf_restore_filter(dev); 2061 2062 /* Enable interrupt of all rx queues before enabling queues */ 2063 hns3_dev_all_rx_queue_intr_enable(hw, true); 2064 /* 2065 * When finished the initialization, enable queues to receive/transmit 2066 * packets. 2067 */ 2068 hns3_enable_all_queues(hw, true); 2069 2070 return ret; 2071 } 2072 2073 static bool 2074 is_vf_reset_done(struct hns3_hw *hw) 2075 { 2076 #define HNS3_FUN_RST_ING_BITS \ 2077 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \ 2078 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \ 2079 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \ 2080 BIT(HNS3_VECTOR0_FUNCRESET_INT_B)) 2081 2082 uint32_t val; 2083 2084 if (hw->reset.level == HNS3_VF_RESET) { 2085 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 2086 if (val & HNS3_VF_RST_ING_BIT) 2087 return false; 2088 } else { 2089 val = hns3_read_dev(hw, HNS3_FUN_RST_ING); 2090 if (val & HNS3_FUN_RST_ING_BITS) 2091 return false; 2092 } 2093 return true; 2094 } 2095 2096 bool 2097 hns3vf_is_reset_pending(struct hns3_adapter *hns) 2098 { 2099 struct hns3_hw *hw = &hns->hw; 2100 enum hns3_reset_level reset; 2101 2102 hns3vf_check_event_cause(hns, NULL); 2103 reset = hns3vf_get_reset_level(hw, &hw->reset.pending); 2104 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 2105 hns3_warn(hw, "High level reset %d is pending", reset); 2106 return true; 2107 } 2108 return false; 2109 } 2110 2111 static int 2112 hns3vf_wait_hardware_ready(struct hns3_adapter *hns) 2113 { 2114 struct hns3_hw *hw = &hns->hw; 2115 struct hns3_wait_data *wait_data = hw->reset.wait_data; 2116 struct timeval tv; 2117 2118 if (wait_data->result == HNS3_WAIT_SUCCESS) { 2119 /* 2120 * After vf reset is ready, the PF may not have completed 2121 * the reset processing. The vf sending mbox to PF may fail 2122 * during the pf reset, so it is better to add extra delay. 2123 */ 2124 if (hw->reset.level == HNS3_VF_FUNC_RESET || 2125 hw->reset.level == HNS3_FLR_RESET) 2126 return 0; 2127 /* Reset retry process, no need to add extra delay. */ 2128 if (hw->reset.attempts) 2129 return 0; 2130 if (wait_data->check_completion == NULL) 2131 return 0; 2132 2133 wait_data->check_completion = NULL; 2134 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC; 2135 wait_data->count = 1; 2136 wait_data->result = HNS3_WAIT_REQUEST; 2137 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, 2138 wait_data); 2139 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); 2140 return -EAGAIN; 2141 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 2142 gettimeofday(&tv, NULL); 2143 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 2144 tv.tv_sec, tv.tv_usec); 2145 return -ETIME; 2146 } else if (wait_data->result == HNS3_WAIT_REQUEST) 2147 return -EAGAIN; 2148 2149 wait_data->hns = hns; 2150 wait_data->check_completion = is_vf_reset_done; 2151 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT * 2152 HNS3VF_RESET_WAIT_MS + get_timeofday_ms(); 2153 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC; 2154 wait_data->count = HNS3VF_RESET_WAIT_CNT; 2155 wait_data->result = HNS3_WAIT_REQUEST; 2156 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 2157 return -EAGAIN; 2158 } 2159 2160 static int 2161 hns3vf_prepare_reset(struct hns3_adapter *hns) 2162 { 2163 struct hns3_hw *hw = &hns->hw; 2164 int ret = 0; 2165 2166 if (hw->reset.level == HNS3_VF_FUNC_RESET) { 2167 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL, 2168 0, true, NULL, 0); 2169 } 2170 rte_atomic16_set(&hw->reset.disable_cmd, 1); 2171 2172 return ret; 2173 } 2174 2175 static int 2176 hns3vf_stop_service(struct hns3_adapter *hns) 2177 { 2178 struct hns3_hw *hw = &hns->hw; 2179 struct rte_eth_dev *eth_dev; 2180 2181 eth_dev = &rte_eth_devices[hw->data->port_id]; 2182 if (hw->adapter_state == HNS3_NIC_STARTED) 2183 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev); 2184 hw->mac.link_status = ETH_LINK_DOWN; 2185 2186 hns3_set_rxtx_function(eth_dev); 2187 rte_wmb(); 2188 /* Disable datapath on secondary process. */ 2189 hns3_mp_req_stop_rxtx(eth_dev); 2190 rte_delay_ms(hw->tqps_num); 2191 2192 rte_spinlock_lock(&hw->lock); 2193 if (hw->adapter_state == HNS3_NIC_STARTED || 2194 hw->adapter_state == HNS3_NIC_STOPPING) { 2195 hns3vf_do_stop(hns); 2196 hw->reset.mbuf_deferred_free = true; 2197 } else 2198 hw->reset.mbuf_deferred_free = false; 2199 2200 /* 2201 * It is cumbersome for hardware to pick-and-choose entries for deletion 2202 * from table space. Hence, for function reset software intervention is 2203 * required to delete the entries. 2204 */ 2205 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) 2206 hns3vf_configure_all_mc_mac_addr(hns, true); 2207 rte_spinlock_unlock(&hw->lock); 2208 2209 return 0; 2210 } 2211 2212 static int 2213 hns3vf_start_service(struct hns3_adapter *hns) 2214 { 2215 struct hns3_hw *hw = &hns->hw; 2216 struct rte_eth_dev *eth_dev; 2217 2218 eth_dev = &rte_eth_devices[hw->data->port_id]; 2219 hns3_set_rxtx_function(eth_dev); 2220 hns3_mp_req_start_rxtx(eth_dev); 2221 if (hw->adapter_state == HNS3_NIC_STARTED) { 2222 hns3vf_service_handler(eth_dev); 2223 2224 /* Enable interrupt of all rx queues before enabling queues */ 2225 hns3_dev_all_rx_queue_intr_enable(hw, true); 2226 /* 2227 * When finished the initialization, enable queues to receive 2228 * and transmit packets. 2229 */ 2230 hns3_enable_all_queues(hw, true); 2231 } 2232 2233 return 0; 2234 } 2235 2236 static int 2237 hns3vf_check_default_mac_change(struct hns3_hw *hw) 2238 { 2239 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2240 struct rte_ether_addr *hw_mac; 2241 int ret; 2242 2243 /* 2244 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2245 * on the host by "ip link set ..." command. If the hns3 PF kernel 2246 * ethdev driver sets the MAC address for VF device after the 2247 * initialization of the related VF device, the PF driver will notify 2248 * VF driver to reset VF device to make the new MAC address effective 2249 * immediately. The hns3 VF PMD driver should check whether the MAC 2250 * address has been changed by the PF kernel ethdev driver, if changed 2251 * VF driver should configure hardware using the new MAC address in the 2252 * recovering hardware configuration stage of the reset process. 2253 */ 2254 ret = hns3vf_get_host_mac_addr(hw); 2255 if (ret) 2256 return ret; 2257 2258 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr; 2259 ret = rte_is_zero_ether_addr(hw_mac); 2260 if (ret) { 2261 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac); 2262 } else { 2263 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac); 2264 if (!ret) { 2265 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]); 2266 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2267 &hw->data->mac_addrs[0]); 2268 hns3_warn(hw, "Default MAC address has been changed to:" 2269 " %s by the host PF kernel ethdev driver", 2270 mac_str); 2271 } 2272 } 2273 2274 return 0; 2275 } 2276 2277 static int 2278 hns3vf_restore_conf(struct hns3_adapter *hns) 2279 { 2280 struct hns3_hw *hw = &hns->hw; 2281 int ret; 2282 2283 ret = hns3vf_check_default_mac_change(hw); 2284 if (ret) 2285 return ret; 2286 2287 ret = hns3vf_configure_mac_addr(hns, false); 2288 if (ret) 2289 return ret; 2290 2291 ret = hns3vf_configure_all_mc_mac_addr(hns, false); 2292 if (ret) 2293 goto err_mc_mac; 2294 2295 ret = hns3vf_restore_promisc(hns); 2296 if (ret) 2297 goto err_vlan_table; 2298 2299 ret = hns3vf_restore_vlan_conf(hns); 2300 if (ret) 2301 goto err_vlan_table; 2302 2303 ret = hns3vf_get_port_base_vlan_filter_state(hw); 2304 if (ret) 2305 goto err_vlan_table; 2306 2307 ret = hns3vf_restore_rx_interrupt(hw); 2308 if (ret) 2309 goto err_vlan_table; 2310 2311 ret = hns3_restore_gro_conf(hw); 2312 if (ret) 2313 goto err_vlan_table; 2314 2315 if (hw->adapter_state == HNS3_NIC_STARTED) { 2316 ret = hns3vf_do_start(hns, false); 2317 if (ret) 2318 goto err_vlan_table; 2319 hns3_info(hw, "hns3vf dev restart successful!"); 2320 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 2321 hw->adapter_state = HNS3_NIC_CONFIGURED; 2322 return 0; 2323 2324 err_vlan_table: 2325 hns3vf_configure_all_mc_mac_addr(hns, true); 2326 err_mc_mac: 2327 hns3vf_configure_mac_addr(hns, true); 2328 return ret; 2329 } 2330 2331 static enum hns3_reset_level 2332 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels) 2333 { 2334 enum hns3_reset_level reset_level; 2335 2336 /* return the highest priority reset level amongst all */ 2337 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels)) 2338 reset_level = HNS3_VF_RESET; 2339 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels)) 2340 reset_level = HNS3_VF_FULL_RESET; 2341 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels)) 2342 reset_level = HNS3_VF_PF_FUNC_RESET; 2343 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels)) 2344 reset_level = HNS3_VF_FUNC_RESET; 2345 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 2346 reset_level = HNS3_FLR_RESET; 2347 else 2348 reset_level = HNS3_NONE_RESET; 2349 2350 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 2351 return HNS3_NONE_RESET; 2352 2353 return reset_level; 2354 } 2355 2356 static void 2357 hns3vf_reset_service(void *param) 2358 { 2359 struct hns3_adapter *hns = (struct hns3_adapter *)param; 2360 struct hns3_hw *hw = &hns->hw; 2361 enum hns3_reset_level reset_level; 2362 struct timeval tv_delta; 2363 struct timeval tv_start; 2364 struct timeval tv; 2365 uint64_t msec; 2366 2367 /* 2368 * The interrupt is not triggered within the delay time. 2369 * The interrupt may have been lost. It is necessary to handle 2370 * the interrupt to recover from the error. 2371 */ 2372 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) { 2373 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); 2374 hns3_err(hw, "Handling interrupts in delayed tasks"); 2375 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 2376 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2377 if (reset_level == HNS3_NONE_RESET) { 2378 hns3_err(hw, "No reset level is set, try global reset"); 2379 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 2380 } 2381 } 2382 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); 2383 2384 /* 2385 * Hardware reset has been notified, we now have to poll & check if 2386 * hardware has actually completed the reset sequence. 2387 */ 2388 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2389 if (reset_level != HNS3_NONE_RESET) { 2390 gettimeofday(&tv_start, NULL); 2391 hns3_reset_process(hns, reset_level); 2392 gettimeofday(&tv, NULL); 2393 timersub(&tv, &tv_start, &tv_delta); 2394 msec = tv_delta.tv_sec * MSEC_PER_SEC + 2395 tv_delta.tv_usec / USEC_PER_MSEC; 2396 if (msec > HNS3_RESET_PROCESS_MS) 2397 hns3_err(hw, "%d handle long time delta %" PRIx64 2398 " ms time=%ld.%.6ld", 2399 hw->reset.level, msec, tv.tv_sec, tv.tv_usec); 2400 } 2401 } 2402 2403 static int 2404 hns3vf_reinit_dev(struct hns3_adapter *hns) 2405 { 2406 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id]; 2407 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2408 struct hns3_hw *hw = &hns->hw; 2409 int ret; 2410 2411 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2412 rte_intr_disable(&pci_dev->intr_handle); 2413 hns3vf_set_bus_master(pci_dev, true); 2414 } 2415 2416 /* Firmware command initialize */ 2417 ret = hns3_cmd_init(hw); 2418 if (ret) { 2419 hns3_err(hw, "Failed to init cmd: %d", ret); 2420 return ret; 2421 } 2422 2423 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2424 /* 2425 * UIO enables msix by writing the pcie configuration space 2426 * vfio_pci enables msix in rte_intr_enable. 2427 */ 2428 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO || 2429 pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) { 2430 if (hns3vf_enable_msix(pci_dev, true)) 2431 hns3_err(hw, "Failed to enable msix"); 2432 } 2433 2434 rte_intr_enable(&pci_dev->intr_handle); 2435 } 2436 2437 ret = hns3_reset_all_queues(hns); 2438 if (ret) { 2439 hns3_err(hw, "Failed to reset all queues: %d", ret); 2440 return ret; 2441 } 2442 2443 ret = hns3vf_init_hardware(hns); 2444 if (ret) { 2445 hns3_err(hw, "Failed to init hardware: %d", ret); 2446 return ret; 2447 } 2448 2449 return 0; 2450 } 2451 2452 static const struct eth_dev_ops hns3vf_eth_dev_ops = { 2453 .dev_start = hns3vf_dev_start, 2454 .dev_stop = hns3vf_dev_stop, 2455 .dev_close = hns3vf_dev_close, 2456 .mtu_set = hns3vf_dev_mtu_set, 2457 .promiscuous_enable = hns3vf_dev_promiscuous_enable, 2458 .promiscuous_disable = hns3vf_dev_promiscuous_disable, 2459 .allmulticast_enable = hns3vf_dev_allmulticast_enable, 2460 .allmulticast_disable = hns3vf_dev_allmulticast_disable, 2461 .stats_get = hns3_stats_get, 2462 .stats_reset = hns3_stats_reset, 2463 .xstats_get = hns3_dev_xstats_get, 2464 .xstats_get_names = hns3_dev_xstats_get_names, 2465 .xstats_reset = hns3_dev_xstats_reset, 2466 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 2467 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 2468 .dev_infos_get = hns3vf_dev_infos_get, 2469 .fw_version_get = hns3vf_fw_version_get, 2470 .rx_queue_setup = hns3_rx_queue_setup, 2471 .tx_queue_setup = hns3_tx_queue_setup, 2472 .rx_queue_release = hns3_dev_rx_queue_release, 2473 .tx_queue_release = hns3_dev_tx_queue_release, 2474 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 2475 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 2476 .dev_configure = hns3vf_dev_configure, 2477 .mac_addr_add = hns3vf_add_mac_addr, 2478 .mac_addr_remove = hns3vf_remove_mac_addr, 2479 .mac_addr_set = hns3vf_set_default_mac_addr, 2480 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list, 2481 .link_update = hns3vf_dev_link_update, 2482 .rss_hash_update = hns3_dev_rss_hash_update, 2483 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 2484 .reta_update = hns3_dev_rss_reta_update, 2485 .reta_query = hns3_dev_rss_reta_query, 2486 .filter_ctrl = hns3_dev_filter_ctrl, 2487 .vlan_filter_set = hns3vf_vlan_filter_set, 2488 .vlan_offload_set = hns3vf_vlan_offload_set, 2489 .get_reg = hns3_get_regs, 2490 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 2491 }; 2492 2493 static const struct hns3_reset_ops hns3vf_reset_ops = { 2494 .reset_service = hns3vf_reset_service, 2495 .stop_service = hns3vf_stop_service, 2496 .prepare_reset = hns3vf_prepare_reset, 2497 .wait_hardware_ready = hns3vf_wait_hardware_ready, 2498 .reinit_dev = hns3vf_reinit_dev, 2499 .restore_conf = hns3vf_restore_conf, 2500 .start_service = hns3vf_start_service, 2501 }; 2502 2503 static int 2504 hns3vf_dev_init(struct rte_eth_dev *eth_dev) 2505 { 2506 struct hns3_adapter *hns = eth_dev->data->dev_private; 2507 struct hns3_hw *hw = &hns->hw; 2508 int ret; 2509 2510 PMD_INIT_FUNC_TRACE(); 2511 2512 eth_dev->process_private = (struct hns3_process_private *) 2513 rte_zmalloc_socket("hns3_filter_list", 2514 sizeof(struct hns3_process_private), 2515 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 2516 if (eth_dev->process_private == NULL) { 2517 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 2518 return -ENOMEM; 2519 } 2520 2521 /* initialize flow filter lists */ 2522 hns3_filterlist_init(eth_dev); 2523 2524 hns3_set_rxtx_function(eth_dev); 2525 eth_dev->dev_ops = &hns3vf_eth_dev_ops; 2526 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2527 ret = hns3_mp_init_secondary(); 2528 if (ret) { 2529 PMD_INIT_LOG(ERR, "Failed to init for secondary " 2530 "process, ret = %d", ret); 2531 goto err_mp_init_secondary; 2532 } 2533 2534 hw->secondary_cnt++; 2535 return 0; 2536 } 2537 2538 ret = hns3_mp_init_primary(); 2539 if (ret) { 2540 PMD_INIT_LOG(ERR, 2541 "Failed to init for primary process, ret = %d", 2542 ret); 2543 goto err_mp_init_primary; 2544 } 2545 2546 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 2547 hns->is_vf = true; 2548 hw->data = eth_dev->data; 2549 2550 ret = hns3_reset_init(hw); 2551 if (ret) 2552 goto err_init_reset; 2553 hw->reset.ops = &hns3vf_reset_ops; 2554 2555 ret = hns3vf_init_vf(eth_dev); 2556 if (ret) { 2557 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret); 2558 goto err_init_vf; 2559 } 2560 2561 /* Allocate memory for storing MAC addresses */ 2562 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac", 2563 sizeof(struct rte_ether_addr) * 2564 HNS3_VF_UC_MACADDR_NUM, 0); 2565 if (eth_dev->data->mac_addrs == NULL) { 2566 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 2567 "to store MAC addresses", 2568 sizeof(struct rte_ether_addr) * 2569 HNS3_VF_UC_MACADDR_NUM); 2570 ret = -ENOMEM; 2571 goto err_rte_zmalloc; 2572 } 2573 2574 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 2575 ð_dev->data->mac_addrs[0]); 2576 hw->adapter_state = HNS3_NIC_INITIALIZED; 2577 /* 2578 * Pass the information to the rte_eth_dev_close() that it should also 2579 * release the private port resources. 2580 */ 2581 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 2582 2583 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) { 2584 hns3_err(hw, "Reschedule reset service after dev_init"); 2585 hns3_schedule_reset(hns); 2586 } else { 2587 /* IMP will wait ready flag before reset */ 2588 hns3_notify_reset_ready(hw, false); 2589 } 2590 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 2591 eth_dev); 2592 return 0; 2593 2594 err_rte_zmalloc: 2595 hns3vf_uninit_vf(eth_dev); 2596 2597 err_init_vf: 2598 rte_free(hw->reset.wait_data); 2599 2600 err_init_reset: 2601 hns3_mp_uninit_primary(); 2602 2603 err_mp_init_primary: 2604 err_mp_init_secondary: 2605 eth_dev->dev_ops = NULL; 2606 eth_dev->rx_pkt_burst = NULL; 2607 eth_dev->tx_pkt_burst = NULL; 2608 eth_dev->tx_pkt_prepare = NULL; 2609 rte_free(eth_dev->process_private); 2610 eth_dev->process_private = NULL; 2611 2612 return ret; 2613 } 2614 2615 static int 2616 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev) 2617 { 2618 struct hns3_adapter *hns = eth_dev->data->dev_private; 2619 struct hns3_hw *hw = &hns->hw; 2620 2621 PMD_INIT_FUNC_TRACE(); 2622 2623 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2624 return -EPERM; 2625 2626 eth_dev->dev_ops = NULL; 2627 eth_dev->rx_pkt_burst = NULL; 2628 eth_dev->tx_pkt_burst = NULL; 2629 eth_dev->tx_pkt_prepare = NULL; 2630 2631 if (hw->adapter_state < HNS3_NIC_CLOSING) 2632 hns3vf_dev_close(eth_dev); 2633 2634 hw->adapter_state = HNS3_NIC_REMOVED; 2635 return 0; 2636 } 2637 2638 static int 2639 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2640 struct rte_pci_device *pci_dev) 2641 { 2642 return rte_eth_dev_pci_generic_probe(pci_dev, 2643 sizeof(struct hns3_adapter), 2644 hns3vf_dev_init); 2645 } 2646 2647 static int 2648 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev) 2649 { 2650 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit); 2651 } 2652 2653 static const struct rte_pci_id pci_id_hns3vf_map[] = { 2654 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) }, 2655 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) }, 2656 { .vendor_id = 0, /* sentinel */ }, 2657 }; 2658 2659 static struct rte_pci_driver rte_hns3vf_pmd = { 2660 .id_table = pci_id_hns3vf_map, 2661 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2662 .probe = eth_hns3vf_pci_probe, 2663 .remove = eth_hns3vf_pci_remove, 2664 }; 2665 2666 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); 2667 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); 2668 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); 2669