1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <linux/pci_regs.h> 6 #include <rte_alarm.h> 7 #include <ethdev_pci.h> 8 #include <rte_io.h> 9 #include <rte_pci.h> 10 #include <rte_vfio.h> 11 12 #include "hns3_ethdev.h" 13 #include "hns3_logs.h" 14 #include "hns3_rxtx.h" 15 #include "hns3_regs.h" 16 #include "hns3_intr.h" 17 #include "hns3_dcb.h" 18 #include "hns3_mp.h" 19 20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */ 21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */ 22 23 #define HNS3VF_RESET_WAIT_MS 20 24 #define HNS3VF_RESET_WAIT_CNT 2000 25 26 /* Reset related Registers */ 27 #define HNS3_GLOBAL_RESET_BIT 0 28 #define HNS3_CORE_RESET_BIT 1 29 #define HNS3_IMP_RESET_BIT 2 30 #define HNS3_FUN_RST_ING_B 0 31 32 enum hns3vf_evt_cause { 33 HNS3VF_VECTOR0_EVENT_RST, 34 HNS3VF_VECTOR0_EVENT_MBX, 35 HNS3VF_VECTOR0_EVENT_OTHER, 36 }; 37 38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw, 39 uint64_t *levels); 40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev); 42 43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 44 struct rte_ether_addr *mac_addr); 45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 46 struct rte_ether_addr *mac_addr); 47 /* set PCI bus mastering */ 48 static int 49 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) 50 { 51 uint16_t reg; 52 int ret; 53 54 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); 55 if (ret < 0) { 56 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 57 PCI_COMMAND); 58 return ret; 59 } 60 61 if (op) 62 /* set the master bit */ 63 reg |= PCI_COMMAND_MASTER; 64 else 65 reg &= ~(PCI_COMMAND_MASTER); 66 67 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); 68 } 69 70 /** 71 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list 72 * @cap: the capability 73 * 74 * Return the address of the given capability within the PCI capability list. 75 */ 76 static int 77 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) 78 { 79 #define MAX_PCIE_CAPABILITY 48 80 uint16_t status; 81 uint8_t pos; 82 uint8_t id; 83 int ttl; 84 int ret; 85 86 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); 87 if (ret < 0) { 88 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS); 89 return 0; 90 } 91 92 if (!(status & PCI_STATUS_CAP_LIST)) 93 return 0; 94 95 ttl = MAX_PCIE_CAPABILITY; 96 ret = rte_pci_read_config(device, &pos, sizeof(pos), 97 PCI_CAPABILITY_LIST); 98 if (ret < 0) { 99 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 100 PCI_CAPABILITY_LIST); 101 return 0; 102 } 103 104 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { 105 ret = rte_pci_read_config(device, &id, sizeof(id), 106 (pos + PCI_CAP_LIST_ID)); 107 if (ret < 0) { 108 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 109 (pos + PCI_CAP_LIST_ID)); 110 break; 111 } 112 113 if (id == 0xFF) 114 break; 115 116 if (id == cap) 117 return (int)pos; 118 119 ret = rte_pci_read_config(device, &pos, sizeof(pos), 120 (pos + PCI_CAP_LIST_NEXT)); 121 if (ret < 0) { 122 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 123 (pos + PCI_CAP_LIST_NEXT)); 124 break; 125 } 126 } 127 return 0; 128 } 129 130 static int 131 hns3vf_enable_msix(const struct rte_pci_device *device, bool op) 132 { 133 uint16_t control; 134 int pos; 135 int ret; 136 137 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); 138 if (pos) { 139 ret = rte_pci_read_config(device, &control, sizeof(control), 140 (pos + PCI_MSIX_FLAGS)); 141 if (ret < 0) { 142 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 143 (pos + PCI_MSIX_FLAGS)); 144 return -ENXIO; 145 } 146 147 if (op) 148 control |= PCI_MSIX_FLAGS_ENABLE; 149 else 150 control &= ~PCI_MSIX_FLAGS_ENABLE; 151 ret = rte_pci_write_config(device, &control, sizeof(control), 152 (pos + PCI_MSIX_FLAGS)); 153 if (ret < 0) { 154 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x", 155 (pos + PCI_MSIX_FLAGS)); 156 } 157 return 0; 158 } 159 return -ENXIO; 160 } 161 162 static int 163 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 164 { 165 /* mac address was checked by upper level interface */ 166 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 167 int ret; 168 169 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 170 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes, 171 RTE_ETHER_ADDR_LEN, false, NULL, 0); 172 if (ret) { 173 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 174 mac_addr); 175 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 176 mac_str, ret); 177 } 178 return ret; 179 } 180 181 static int 182 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 183 { 184 /* mac address was checked by upper level interface */ 185 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 186 int ret; 187 188 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 189 HNS3_MBX_MAC_VLAN_UC_REMOVE, 190 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, 191 false, NULL, 0); 192 if (ret) { 193 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 194 mac_addr); 195 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 196 mac_str, ret); 197 } 198 return ret; 199 } 200 201 static int 202 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 203 { 204 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 205 struct rte_ether_addr *addr; 206 int ret; 207 int i; 208 209 for (i = 0; i < hw->mc_addrs_num; i++) { 210 addr = &hw->mc_addrs[i]; 211 /* Check if there are duplicate addresses */ 212 if (rte_is_same_ether_addr(addr, mac_addr)) { 213 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 214 addr); 215 hns3_err(hw, "failed to add mc mac addr, same addrs" 216 "(%s) is added by the set_mc_mac_addr_list " 217 "API", mac_str); 218 return -EINVAL; 219 } 220 } 221 222 ret = hns3vf_add_mc_mac_addr(hw, mac_addr); 223 if (ret) { 224 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 225 mac_addr); 226 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 227 mac_str, ret); 228 } 229 return ret; 230 } 231 232 static int 233 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 234 __rte_unused uint32_t idx, 235 __rte_unused uint32_t pool) 236 { 237 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 238 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 239 int ret; 240 241 rte_spinlock_lock(&hw->lock); 242 243 /* 244 * In hns3 network engine adding UC and MC mac address with different 245 * commands with firmware. We need to determine whether the input 246 * address is a UC or a MC address to call different commands. 247 * By the way, it is recommended calling the API function named 248 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 249 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 250 * may affect the specifications of UC mac addresses. 251 */ 252 if (rte_is_multicast_ether_addr(mac_addr)) 253 ret = hns3vf_add_mc_addr_common(hw, mac_addr); 254 else 255 ret = hns3vf_add_uc_mac_addr(hw, mac_addr); 256 257 rte_spinlock_unlock(&hw->lock); 258 if (ret) { 259 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 260 mac_addr); 261 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 262 ret); 263 } 264 265 return ret; 266 } 267 268 static void 269 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 270 { 271 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 272 /* index will be checked by upper level rte interface */ 273 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 274 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 275 int ret; 276 277 rte_spinlock_lock(&hw->lock); 278 279 if (rte_is_multicast_ether_addr(mac_addr)) 280 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr); 281 else 282 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr); 283 284 rte_spinlock_unlock(&hw->lock); 285 if (ret) { 286 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 287 mac_addr); 288 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", 289 mac_str, ret); 290 } 291 } 292 293 static int 294 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev, 295 struct rte_ether_addr *mac_addr) 296 { 297 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2) 298 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 299 struct rte_ether_addr *old_addr; 300 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */ 301 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 302 int ret; 303 304 /* 305 * It has been guaranteed that input parameter named mac_addr is valid 306 * address in the rte layer of DPDK framework. 307 */ 308 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 309 rte_spinlock_lock(&hw->lock); 310 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN); 311 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes, 312 RTE_ETHER_ADDR_LEN); 313 314 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 315 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes, 316 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0); 317 if (ret) { 318 /* 319 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev 320 * driver. When user has configured a MAC address for VF device 321 * by "ip link set ..." command based on the PF device, the hns3 322 * PF kernel ethdev driver does not allow VF driver to request 323 * reconfiguring a different default MAC address, and return 324 * -EPREM to VF driver through mailbox. 325 */ 326 if (ret == -EPERM) { 327 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 328 old_addr); 329 hns3_warn(hw, "Has permanet mac addr(%s) for vf", 330 mac_str); 331 } else { 332 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 333 mac_addr); 334 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", 335 mac_str, ret); 336 } 337 } 338 339 rte_ether_addr_copy(mac_addr, 340 (struct rte_ether_addr *)hw->mac.mac_addr); 341 rte_spinlock_unlock(&hw->lock); 342 343 return ret; 344 } 345 346 static int 347 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del) 348 { 349 struct hns3_hw *hw = &hns->hw; 350 struct rte_ether_addr *addr; 351 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 352 int err = 0; 353 int ret; 354 int i; 355 356 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) { 357 addr = &hw->data->mac_addrs[i]; 358 if (rte_is_zero_ether_addr(addr)) 359 continue; 360 if (rte_is_multicast_ether_addr(addr)) 361 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) : 362 hns3vf_add_mc_mac_addr(hw, addr); 363 else 364 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) : 365 hns3vf_add_uc_mac_addr(hw, addr); 366 367 if (ret) { 368 err = ret; 369 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 370 addr); 371 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 372 "ret = %d.", del ? "remove" : "restore", 373 mac_str, i, ret); 374 } 375 } 376 return err; 377 } 378 379 static int 380 hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 381 struct rte_ether_addr *mac_addr) 382 { 383 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 384 int ret; 385 386 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 387 HNS3_MBX_MAC_VLAN_MC_ADD, 388 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 389 NULL, 0); 390 if (ret) { 391 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 392 mac_addr); 393 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d", 394 mac_str, ret); 395 } 396 397 return ret; 398 } 399 400 static int 401 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 402 struct rte_ether_addr *mac_addr) 403 { 404 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 405 int ret; 406 407 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 408 HNS3_MBX_MAC_VLAN_MC_REMOVE, 409 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 410 NULL, 0); 411 if (ret) { 412 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 413 mac_addr); 414 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d", 415 mac_str, ret); 416 } 417 418 return ret; 419 } 420 421 static int 422 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw, 423 struct rte_ether_addr *mc_addr_set, 424 uint32_t nb_mc_addr) 425 { 426 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 427 struct rte_ether_addr *addr; 428 uint32_t i; 429 uint32_t j; 430 431 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 432 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 433 "invalid. valid range: 0~%d", 434 nb_mc_addr, HNS3_MC_MACADDR_NUM); 435 return -EINVAL; 436 } 437 438 /* Check if input mac addresses are valid */ 439 for (i = 0; i < nb_mc_addr; i++) { 440 addr = &mc_addr_set[i]; 441 if (!rte_is_multicast_ether_addr(addr)) { 442 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 443 addr); 444 hns3_err(hw, 445 "failed to set mc mac addr, addr(%s) invalid.", 446 mac_str); 447 return -EINVAL; 448 } 449 450 /* Check if there are duplicate addresses */ 451 for (j = i + 1; j < nb_mc_addr; j++) { 452 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 453 hns3_ether_format_addr(mac_str, 454 RTE_ETHER_ADDR_FMT_SIZE, 455 addr); 456 hns3_err(hw, "failed to set mc mac addr, " 457 "addrs invalid. two same addrs(%s).", 458 mac_str); 459 return -EINVAL; 460 } 461 } 462 463 /* 464 * Check if there are duplicate addresses between mac_addrs 465 * and mc_addr_set 466 */ 467 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) { 468 if (rte_is_same_ether_addr(addr, 469 &hw->data->mac_addrs[j])) { 470 hns3_ether_format_addr(mac_str, 471 RTE_ETHER_ADDR_FMT_SIZE, 472 addr); 473 hns3_err(hw, "failed to set mc mac addr, " 474 "addrs invalid. addrs(%s) has already " 475 "configured in mac_addr add API", 476 mac_str); 477 return -EINVAL; 478 } 479 } 480 } 481 482 return 0; 483 } 484 485 static int 486 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev, 487 struct rte_ether_addr *mc_addr_set, 488 uint32_t nb_mc_addr) 489 { 490 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 491 struct rte_ether_addr *addr; 492 int cur_addr_num; 493 int set_addr_num; 494 int num; 495 int ret; 496 int i; 497 498 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 499 if (ret) 500 return ret; 501 502 rte_spinlock_lock(&hw->lock); 503 cur_addr_num = hw->mc_addrs_num; 504 for (i = 0; i < cur_addr_num; i++) { 505 num = cur_addr_num - i - 1; 506 addr = &hw->mc_addrs[num]; 507 ret = hns3vf_remove_mc_mac_addr(hw, addr); 508 if (ret) { 509 rte_spinlock_unlock(&hw->lock); 510 return ret; 511 } 512 513 hw->mc_addrs_num--; 514 } 515 516 set_addr_num = (int)nb_mc_addr; 517 for (i = 0; i < set_addr_num; i++) { 518 addr = &mc_addr_set[i]; 519 ret = hns3vf_add_mc_mac_addr(hw, addr); 520 if (ret) { 521 rte_spinlock_unlock(&hw->lock); 522 return ret; 523 } 524 525 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]); 526 hw->mc_addrs_num++; 527 } 528 rte_spinlock_unlock(&hw->lock); 529 530 return 0; 531 } 532 533 static int 534 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 535 { 536 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 537 struct hns3_hw *hw = &hns->hw; 538 struct rte_ether_addr *addr; 539 int err = 0; 540 int ret; 541 int i; 542 543 for (i = 0; i < hw->mc_addrs_num; i++) { 544 addr = &hw->mc_addrs[i]; 545 if (!rte_is_multicast_ether_addr(addr)) 546 continue; 547 if (del) 548 ret = hns3vf_remove_mc_mac_addr(hw, addr); 549 else 550 ret = hns3vf_add_mc_mac_addr(hw, addr); 551 if (ret) { 552 err = ret; 553 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 554 addr); 555 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d", 556 del ? "Remove" : "Restore", mac_str, ret); 557 } 558 } 559 return err; 560 } 561 562 static int 563 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc, 564 bool en_uc_pmc, bool en_mc_pmc) 565 { 566 struct hns3_mbx_vf_to_pf_cmd *req; 567 struct hns3_cmd_desc desc; 568 int ret; 569 570 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data; 571 572 /* 573 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver, 574 * so there are some features for promiscuous/allmulticast mode in hns3 575 * VF PMD driver as below: 576 * 1. The promiscuous/allmulticast mode can be configured successfully 577 * only based on the trusted VF device. If based on the non trusted 578 * VF device, configuring promiscuous/allmulticast mode will fail. 579 * The hns3 VF device can be confiruged as trusted device by hns3 PF 580 * kernel ethdev driver on the host by the following command: 581 * "ip link set <eth num> vf <vf id> turst on" 582 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD 583 * driver can receive the ingress and outgoing traffic. In the words, 584 * all the ingress packets, all the packets sent from the PF and 585 * other VFs on the same physical port. 586 * 3. Note: Because of the hardware constraints, By default vlan filter 587 * is enabled and couldn't be turned off based on VF device, so vlan 588 * filter is still effective even in promiscuous mode. If upper 589 * applications don't call rte_eth_dev_vlan_filter API function to 590 * set vlan based on VF device, hns3 VF PMD driver will can't receive 591 * the packets with vlan tag in promiscuoue mode. 592 */ 593 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false); 594 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE; 595 req->msg[1] = en_bc_pmc ? 1 : 0; 596 req->msg[2] = en_uc_pmc ? 1 : 0; 597 req->msg[3] = en_mc_pmc ? 1 : 0; 598 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0; 599 600 ret = hns3_cmd_send(hw, &desc, 1); 601 if (ret) 602 hns3_err(hw, "Set promisc mode fail, ret = %d", ret); 603 604 return ret; 605 } 606 607 static int 608 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev) 609 { 610 struct hns3_adapter *hns = dev->data->dev_private; 611 struct hns3_hw *hw = &hns->hw; 612 int ret; 613 614 ret = hns3vf_set_promisc_mode(hw, true, true, true); 615 if (ret) 616 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d", 617 ret); 618 return ret; 619 } 620 621 static int 622 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev) 623 { 624 bool allmulti = dev->data->all_multicast ? true : false; 625 struct hns3_adapter *hns = dev->data->dev_private; 626 struct hns3_hw *hw = &hns->hw; 627 int ret; 628 629 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti); 630 if (ret) 631 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d", 632 ret); 633 return ret; 634 } 635 636 static int 637 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev) 638 { 639 struct hns3_adapter *hns = dev->data->dev_private; 640 struct hns3_hw *hw = &hns->hw; 641 int ret; 642 643 if (dev->data->promiscuous) 644 return 0; 645 646 ret = hns3vf_set_promisc_mode(hw, true, false, true); 647 if (ret) 648 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d", 649 ret); 650 return ret; 651 } 652 653 static int 654 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev) 655 { 656 struct hns3_adapter *hns = dev->data->dev_private; 657 struct hns3_hw *hw = &hns->hw; 658 int ret; 659 660 if (dev->data->promiscuous) 661 return 0; 662 663 ret = hns3vf_set_promisc_mode(hw, true, false, false); 664 if (ret) 665 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d", 666 ret); 667 return ret; 668 } 669 670 static int 671 hns3vf_restore_promisc(struct hns3_adapter *hns) 672 { 673 struct hns3_hw *hw = &hns->hw; 674 bool allmulti = hw->data->all_multicast ? true : false; 675 676 if (hw->data->promiscuous) 677 return hns3vf_set_promisc_mode(hw, true, true, true); 678 679 return hns3vf_set_promisc_mode(hw, true, false, allmulti); 680 } 681 682 static int 683 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, 684 bool mmap, enum hns3_ring_type queue_type, 685 uint16_t queue_id) 686 { 687 struct hns3_vf_bind_vector_msg bind_msg; 688 const char *op_str; 689 uint16_t code; 690 int ret; 691 692 memset(&bind_msg, 0, sizeof(bind_msg)); 693 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR : 694 HNS3_MBX_UNMAP_RING_TO_VECTOR; 695 bind_msg.vector_id = vector_id; 696 697 if (queue_type == HNS3_RING_TYPE_RX) 698 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX; 699 else 700 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX; 701 702 bind_msg.param[0].ring_type = queue_type; 703 bind_msg.ring_num = 1; 704 bind_msg.param[0].tqp_index = queue_id; 705 op_str = mmap ? "Map" : "Unmap"; 706 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg, 707 sizeof(bind_msg), false, NULL, 0); 708 if (ret) 709 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.", 710 op_str, queue_id, bind_msg.vector_id, ret); 711 712 return ret; 713 } 714 715 static int 716 hns3vf_init_ring_with_vector(struct hns3_hw *hw) 717 { 718 uint16_t vec; 719 int ret; 720 int i; 721 722 /* 723 * In hns3 network engine, vector 0 is always the misc interrupt of this 724 * function, vector 1~N can be used respectively for the queues of the 725 * function. Tx and Rx queues with the same number share the interrupt 726 * vector. In the initialization clearing the all hardware mapping 727 * relationship configurations between queues and interrupt vectors is 728 * needed, so some error caused by the residual configurations, such as 729 * the unexpected Tx interrupt, can be avoid. 730 */ 731 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 732 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 733 vec = vec - 1; /* the last interrupt is reserved */ 734 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 735 for (i = 0; i < hw->intr_tqps_num; i++) { 736 /* 737 * Set gap limiter/rate limiter/quanity limiter algorithm 738 * configuration for interrupt coalesce of queue's interrupt. 739 */ 740 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 741 HNS3_TQP_INTR_GL_DEFAULT); 742 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 743 HNS3_TQP_INTR_GL_DEFAULT); 744 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 745 /* 746 * QL(quantity limiter) is not used currently, just set 0 to 747 * close it. 748 */ 749 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 750 751 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 752 HNS3_RING_TYPE_TX, i); 753 if (ret) { 754 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with " 755 "vector: %u, ret=%d", i, vec, ret); 756 return ret; 757 } 758 759 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 760 HNS3_RING_TYPE_RX, i); 761 if (ret) { 762 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with " 763 "vector: %u, ret=%d", i, vec, ret); 764 return ret; 765 } 766 } 767 768 return 0; 769 } 770 771 static int 772 hns3vf_dev_configure(struct rte_eth_dev *dev) 773 { 774 struct hns3_adapter *hns = dev->data->dev_private; 775 struct hns3_hw *hw = &hns->hw; 776 struct rte_eth_conf *conf = &dev->data->dev_conf; 777 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 778 uint16_t nb_rx_q = dev->data->nb_rx_queues; 779 uint16_t nb_tx_q = dev->data->nb_tx_queues; 780 struct rte_eth_rss_conf rss_conf; 781 uint32_t max_rx_pkt_len; 782 uint16_t mtu; 783 bool gro_en; 784 int ret; 785 786 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 787 788 /* 789 * Some versions of hardware network engine does not support 790 * individually enable/disable/reset the Tx or Rx queue. These devices 791 * must enable/disable/reset Tx and Rx queues at the same time. When the 792 * numbers of Tx queues allocated by upper applications are not equal to 793 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 794 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 795 * work as usual. But these fake queues are imperceptible, and can not 796 * be used by upper applications. 797 */ 798 if (!hns3_dev_indep_txrx_supported(hw)) { 799 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 800 if (ret) { 801 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", 802 ret); 803 return ret; 804 } 805 } 806 807 hw->adapter_state = HNS3_NIC_CONFIGURING; 808 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 809 hns3_err(hw, "setting link speed/duplex not supported"); 810 ret = -EINVAL; 811 goto cfg_err; 812 } 813 814 /* When RSS is not configured, redirect the packet queue 0 */ 815 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 816 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 817 hw->rss_dis_flag = false; 818 rss_conf = conf->rx_adv_conf.rss_conf; 819 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 820 if (ret) 821 goto cfg_err; 822 } 823 824 /* 825 * If jumbo frames are enabled, MTU needs to be refreshed 826 * according to the maximum RX packet length. 827 */ 828 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 829 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len; 830 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN || 831 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) { 832 hns3_err(hw, "maximum Rx packet length must be greater " 833 "than %u and less than %u when jumbo frame enabled.", 834 (uint16_t)HNS3_DEFAULT_FRAME_LEN, 835 (uint16_t)HNS3_MAX_FRAME_LEN); 836 ret = -EINVAL; 837 goto cfg_err; 838 } 839 840 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len); 841 ret = hns3vf_dev_mtu_set(dev, mtu); 842 if (ret) 843 goto cfg_err; 844 dev->data->mtu = mtu; 845 } 846 847 ret = hns3vf_dev_configure_vlan(dev); 848 if (ret) 849 goto cfg_err; 850 851 /* config hardware GRO */ 852 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 853 ret = hns3_config_gro(hw, gro_en); 854 if (ret) 855 goto cfg_err; 856 857 hns->rx_simple_allowed = true; 858 hns->rx_vec_allowed = true; 859 hns->tx_simple_allowed = true; 860 hns->tx_vec_allowed = true; 861 862 hns3_init_rx_ptype_tble(dev); 863 864 hw->adapter_state = HNS3_NIC_CONFIGURED; 865 return 0; 866 867 cfg_err: 868 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 869 hw->adapter_state = HNS3_NIC_INITIALIZED; 870 871 return ret; 872 } 873 874 static int 875 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu) 876 { 877 int ret; 878 879 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu, 880 sizeof(mtu), true, NULL, 0); 881 if (ret) 882 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret); 883 884 return ret; 885 } 886 887 static int 888 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 889 { 890 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 891 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 892 int ret; 893 894 /* 895 * The hns3 PF/VF devices on the same port share the hardware MTU 896 * configuration. Currently, we send mailbox to inform hns3 PF kernel 897 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD 898 * driver, there is no need to stop the port for hns3 VF device, and the 899 * MTU value issued by hns3 VF PMD driver must be less than or equal to 900 * PF's MTU. 901 */ 902 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 903 hns3_err(hw, "Failed to set mtu during resetting"); 904 return -EIO; 905 } 906 907 /* 908 * when Rx of scattered packets is off, we have some possibility of 909 * using vector Rx process function or simple Rx functions in hns3 PMD 910 * driver. If the input MTU is increased and the maximum length of 911 * received packets is greater than the length of a buffer for Rx 912 * packet, the hardware network engine needs to use multiple BDs and 913 * buffers to store these packets. This will cause problems when still 914 * using vector Rx process function or simple Rx function to receiving 915 * packets. So, when Rx of scattered packets is off and device is 916 * started, it is not permitted to increase MTU so that the maximum 917 * length of Rx packets is greater than Rx buffer length. 918 */ 919 if (dev->data->dev_started && !dev->data->scattered_rx && 920 frame_size > hw->rx_buf_len) { 921 hns3_err(hw, "failed to set mtu because current is " 922 "not scattered rx mode"); 923 return -EOPNOTSUPP; 924 } 925 926 rte_spinlock_lock(&hw->lock); 927 ret = hns3vf_config_mtu(hw, mtu); 928 if (ret) { 929 rte_spinlock_unlock(&hw->lock); 930 return ret; 931 } 932 if (mtu > RTE_ETHER_MTU) 933 dev->data->dev_conf.rxmode.offloads |= 934 DEV_RX_OFFLOAD_JUMBO_FRAME; 935 else 936 dev->data->dev_conf.rxmode.offloads &= 937 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 938 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 939 rte_spinlock_unlock(&hw->lock); 940 941 return 0; 942 } 943 944 static int 945 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 946 { 947 struct hns3_adapter *hns = eth_dev->data->dev_private; 948 struct hns3_hw *hw = &hns->hw; 949 uint16_t q_num = hw->tqps_num; 950 951 /* 952 * In interrupt mode, 'max_rx_queues' is set based on the number of 953 * MSI-X interrupt resources of the hardware. 954 */ 955 if (hw->data->dev_conf.intr_conf.rxq == 1) 956 q_num = hw->intr_tqps_num; 957 958 info->max_rx_queues = q_num; 959 info->max_tx_queues = hw->tqps_num; 960 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 961 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 962 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; 963 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 964 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 965 966 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 967 DEV_RX_OFFLOAD_UDP_CKSUM | 968 DEV_RX_OFFLOAD_TCP_CKSUM | 969 DEV_RX_OFFLOAD_SCTP_CKSUM | 970 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 971 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 972 DEV_RX_OFFLOAD_SCATTER | 973 DEV_RX_OFFLOAD_VLAN_STRIP | 974 DEV_RX_OFFLOAD_VLAN_FILTER | 975 DEV_RX_OFFLOAD_JUMBO_FRAME | 976 DEV_RX_OFFLOAD_RSS_HASH | 977 DEV_RX_OFFLOAD_TCP_LRO); 978 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 979 DEV_TX_OFFLOAD_IPV4_CKSUM | 980 DEV_TX_OFFLOAD_TCP_CKSUM | 981 DEV_TX_OFFLOAD_UDP_CKSUM | 982 DEV_TX_OFFLOAD_SCTP_CKSUM | 983 DEV_TX_OFFLOAD_MULTI_SEGS | 984 DEV_TX_OFFLOAD_TCP_TSO | 985 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 986 DEV_TX_OFFLOAD_GRE_TNL_TSO | 987 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 988 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 989 hns3_txvlan_cap_get(hw)); 990 991 if (hns3_dev_indep_txrx_supported(hw)) 992 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 993 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 994 995 info->rx_desc_lim = (struct rte_eth_desc_lim) { 996 .nb_max = HNS3_MAX_RING_DESC, 997 .nb_min = HNS3_MIN_RING_DESC, 998 .nb_align = HNS3_ALIGN_RING_DESC, 999 }; 1000 1001 info->tx_desc_lim = (struct rte_eth_desc_lim) { 1002 .nb_max = HNS3_MAX_RING_DESC, 1003 .nb_min = HNS3_MIN_RING_DESC, 1004 .nb_align = HNS3_ALIGN_RING_DESC, 1005 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 1006 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 1007 }; 1008 1009 info->default_rxconf = (struct rte_eth_rxconf) { 1010 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 1011 /* 1012 * If there are no available Rx buffer descriptors, incoming 1013 * packets are always dropped by hardware based on hns3 network 1014 * engine. 1015 */ 1016 .rx_drop_en = 1, 1017 .offloads = 0, 1018 }; 1019 info->default_txconf = (struct rte_eth_txconf) { 1020 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 1021 .offloads = 0, 1022 }; 1023 1024 info->vmdq_queue_num = 0; 1025 1026 info->reta_size = hw->rss_ind_tbl_size; 1027 info->hash_key_size = HNS3_RSS_KEY_SIZE; 1028 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 1029 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1030 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1031 1032 return 0; 1033 } 1034 1035 static void 1036 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr) 1037 { 1038 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 1039 } 1040 1041 static void 1042 hns3vf_disable_irq0(struct hns3_hw *hw) 1043 { 1044 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 1045 } 1046 1047 static void 1048 hns3vf_enable_irq0(struct hns3_hw *hw) 1049 { 1050 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 1051 } 1052 1053 static enum hns3vf_evt_cause 1054 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 1055 { 1056 struct hns3_hw *hw = &hns->hw; 1057 enum hns3vf_evt_cause ret; 1058 uint32_t cmdq_stat_reg; 1059 uint32_t rst_ing_reg; 1060 uint32_t val; 1061 1062 /* Fetch the events from their corresponding regs */ 1063 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG); 1064 1065 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1066 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING); 1067 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg); 1068 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 1069 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 1070 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 1071 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT); 1072 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B); 1073 if (clearval) { 1074 hw->reset.stats.global_cnt++; 1075 hns3_warn(hw, "Global reset detected, clear reset status"); 1076 } else { 1077 hns3_schedule_delayed_reset(hns); 1078 hns3_warn(hw, "Global reset detected, don't clear reset status"); 1079 } 1080 1081 ret = HNS3VF_VECTOR0_EVENT_RST; 1082 goto out; 1083 } 1084 1085 /* Check for vector0 mailbox(=CMDQ RX) event source */ 1086 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1087 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 1088 ret = HNS3VF_VECTOR0_EVENT_MBX; 1089 goto out; 1090 } 1091 1092 val = 0; 1093 ret = HNS3VF_VECTOR0_EVENT_OTHER; 1094 out: 1095 if (clearval) 1096 *clearval = val; 1097 return ret; 1098 } 1099 1100 static void 1101 hns3vf_interrupt_handler(void *param) 1102 { 1103 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1104 struct hns3_adapter *hns = dev->data->dev_private; 1105 struct hns3_hw *hw = &hns->hw; 1106 enum hns3vf_evt_cause event_cause; 1107 uint32_t clearval; 1108 1109 if (hw->irq_thread_id == 0) 1110 hw->irq_thread_id = pthread_self(); 1111 1112 /* Disable interrupt */ 1113 hns3vf_disable_irq0(hw); 1114 1115 /* Read out interrupt causes */ 1116 event_cause = hns3vf_check_event_cause(hns, &clearval); 1117 1118 switch (event_cause) { 1119 case HNS3VF_VECTOR0_EVENT_RST: 1120 hns3_schedule_reset(hns); 1121 break; 1122 case HNS3VF_VECTOR0_EVENT_MBX: 1123 hns3_dev_handle_mbx_msg(hw); 1124 break; 1125 default: 1126 break; 1127 } 1128 1129 /* Clear interrupt causes */ 1130 hns3vf_clear_event_cause(hw, clearval); 1131 1132 /* Enable interrupt */ 1133 hns3vf_enable_irq0(hw); 1134 } 1135 1136 static void 1137 hns3vf_set_default_dev_specifications(struct hns3_hw *hw) 1138 { 1139 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 1140 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 1141 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 1142 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 1143 } 1144 1145 static void 1146 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 1147 { 1148 struct hns3_dev_specs_0_cmd *req0; 1149 1150 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 1151 1152 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 1153 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 1154 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 1155 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 1156 } 1157 1158 static int 1159 hns3vf_check_dev_specifications(struct hns3_hw *hw) 1160 { 1161 if (hw->rss_ind_tbl_size == 0 || 1162 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 1163 hns3_warn(hw, "the size of hash lookup table configured (%u)" 1164 " exceeds the maximum(%u)", hw->rss_ind_tbl_size, 1165 HNS3_RSS_IND_TBL_SIZE_MAX); 1166 return -EINVAL; 1167 } 1168 1169 return 0; 1170 } 1171 1172 static int 1173 hns3vf_query_dev_specifications(struct hns3_hw *hw) 1174 { 1175 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 1176 int ret; 1177 int i; 1178 1179 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1180 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 1181 true); 1182 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1183 } 1184 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 1185 1186 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 1187 if (ret) 1188 return ret; 1189 1190 hns3vf_parse_dev_specifications(hw, desc); 1191 1192 return hns3vf_check_dev_specifications(hw); 1193 } 1194 1195 static int 1196 hns3vf_get_capability(struct hns3_hw *hw) 1197 { 1198 struct rte_pci_device *pci_dev; 1199 struct rte_eth_dev *eth_dev; 1200 uint8_t revision; 1201 int ret; 1202 1203 eth_dev = &rte_eth_devices[hw->data->port_id]; 1204 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1205 1206 /* Get PCI revision id */ 1207 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 1208 HNS3_PCI_REVISION_ID); 1209 if (ret != HNS3_PCI_REVISION_ID_LEN) { 1210 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 1211 ret); 1212 return -EIO; 1213 } 1214 hw->revision = revision; 1215 1216 if (revision < PCI_REVISION_ID_HIP09_A) { 1217 hns3vf_set_default_dev_specifications(hw); 1218 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 1219 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 1220 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 1221 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 1222 hw->rss_info.ipv6_sctp_offload_supported = false; 1223 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; 1224 return 0; 1225 } 1226 1227 ret = hns3vf_query_dev_specifications(hw); 1228 if (ret) { 1229 PMD_INIT_LOG(ERR, 1230 "failed to query dev specifications, ret = %d", 1231 ret); 1232 return ret; 1233 } 1234 1235 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 1236 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 1237 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 1238 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 1239 hw->rss_info.ipv6_sctp_offload_supported = true; 1240 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; 1241 1242 return 0; 1243 } 1244 1245 static int 1246 hns3vf_check_tqp_info(struct hns3_hw *hw) 1247 { 1248 if (hw->tqps_num == 0) { 1249 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF."); 1250 return -EINVAL; 1251 } 1252 1253 if (hw->rss_size_max == 0) { 1254 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF."); 1255 return -EINVAL; 1256 } 1257 1258 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num); 1259 1260 return 0; 1261 } 1262 1263 static int 1264 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw) 1265 { 1266 uint8_t resp_msg; 1267 int ret; 1268 1269 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, 1270 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0, 1271 true, &resp_msg, sizeof(resp_msg)); 1272 if (ret) { 1273 if (ret == -ETIME) { 1274 /* 1275 * Getting current port based VLAN state from PF driver 1276 * will not affect VF driver's basic function. Because 1277 * the VF driver relies on hns3 PF kernel ether driver, 1278 * to avoid introducing compatibility issues with older 1279 * version of PF driver, no failure will be returned 1280 * when the return value is ETIME. This return value has 1281 * the following scenarios: 1282 * 1) Firmware didn't return the results in time 1283 * 2) the result return by firmware is timeout 1284 * 3) the older version of kernel side PF driver does 1285 * not support this mailbox message. 1286 * For scenarios 1 and 2, it is most likely that a 1287 * hardware error has occurred, or a hardware reset has 1288 * occurred. In this case, these errors will be caught 1289 * by other functions. 1290 */ 1291 PMD_INIT_LOG(WARNING, 1292 "failed to get PVID state for timeout, maybe " 1293 "kernel side PF driver doesn't support this " 1294 "mailbox message, or firmware didn't respond."); 1295 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE; 1296 } else { 1297 PMD_INIT_LOG(ERR, "failed to get port based VLAN state," 1298 " ret = %d", ret); 1299 return ret; 1300 } 1301 } 1302 hw->port_base_vlan_cfg.state = resp_msg ? 1303 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 1304 return 0; 1305 } 1306 1307 static int 1308 hns3vf_get_queue_info(struct hns3_hw *hw) 1309 { 1310 #define HNS3VF_TQPS_RSS_INFO_LEN 6 1311 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN]; 1312 int ret; 1313 1314 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true, 1315 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN); 1316 if (ret) { 1317 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret); 1318 return ret; 1319 } 1320 1321 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t)); 1322 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t)); 1323 1324 return hns3vf_check_tqp_info(hw); 1325 } 1326 1327 static int 1328 hns3vf_get_queue_depth(struct hns3_hw *hw) 1329 { 1330 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4 1331 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN]; 1332 int ret; 1333 1334 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true, 1335 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN); 1336 if (ret) { 1337 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d", 1338 ret); 1339 return ret; 1340 } 1341 1342 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t)); 1343 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t)); 1344 1345 return 0; 1346 } 1347 1348 static int 1349 hns3vf_get_tc_info(struct hns3_hw *hw) 1350 { 1351 uint8_t resp_msg; 1352 int ret; 1353 uint32_t i; 1354 1355 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0, 1356 true, &resp_msg, sizeof(resp_msg)); 1357 if (ret) { 1358 hns3_err(hw, "VF request to get TC info from PF failed %d", 1359 ret); 1360 return ret; 1361 } 1362 1363 hw->hw_tc_map = resp_msg; 1364 1365 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 1366 if (hw->hw_tc_map & BIT(i)) 1367 hw->num_tc++; 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int 1374 hns3vf_get_host_mac_addr(struct hns3_hw *hw) 1375 { 1376 uint8_t host_mac[RTE_ETHER_ADDR_LEN]; 1377 int ret; 1378 1379 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0, 1380 true, host_mac, RTE_ETHER_ADDR_LEN); 1381 if (ret) { 1382 hns3_err(hw, "Failed to get mac addr from PF: %d", ret); 1383 return ret; 1384 } 1385 1386 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN); 1387 1388 return 0; 1389 } 1390 1391 static int 1392 hns3vf_get_configuration(struct hns3_hw *hw) 1393 { 1394 int ret; 1395 1396 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE; 1397 hw->rss_dis_flag = false; 1398 1399 /* Get device capability */ 1400 ret = hns3vf_get_capability(hw); 1401 if (ret) { 1402 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 1403 return ret; 1404 } 1405 1406 /* Get queue configuration from PF */ 1407 ret = hns3vf_get_queue_info(hw); 1408 if (ret) 1409 return ret; 1410 1411 /* Get queue depth info from PF */ 1412 ret = hns3vf_get_queue_depth(hw); 1413 if (ret) 1414 return ret; 1415 1416 /* Get user defined VF MAC addr from PF */ 1417 ret = hns3vf_get_host_mac_addr(hw); 1418 if (ret) 1419 return ret; 1420 1421 ret = hns3vf_get_port_base_vlan_filter_state(hw); 1422 if (ret) 1423 return ret; 1424 1425 /* Get tc configuration from PF */ 1426 return hns3vf_get_tc_info(hw); 1427 } 1428 1429 static int 1430 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q, 1431 uint16_t nb_tx_q) 1432 { 1433 struct hns3_hw *hw = &hns->hw; 1434 1435 if (nb_rx_q < hw->num_tc) { 1436 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).", 1437 nb_rx_q, hw->num_tc); 1438 return -EINVAL; 1439 } 1440 1441 if (nb_tx_q < hw->num_tc) { 1442 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).", 1443 nb_tx_q, hw->num_tc); 1444 return -EINVAL; 1445 } 1446 1447 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q); 1448 } 1449 1450 static void 1451 hns3vf_request_link_info(struct hns3_hw *hw) 1452 { 1453 uint8_t resp_msg; 1454 int ret; 1455 1456 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 1457 return; 1458 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false, 1459 &resp_msg, sizeof(resp_msg)); 1460 if (ret) 1461 hns3_err(hw, "Failed to fetch link status from PF: %d", ret); 1462 } 1463 1464 void 1465 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1466 uint32_t link_speed, uint8_t link_duplex) 1467 { 1468 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1469 struct hns3_mac *mac = &hw->mac; 1470 bool report_lse; 1471 bool changed; 1472 1473 changed = mac->link_status != link_status || 1474 mac->link_speed != link_speed || 1475 mac->link_duplex != link_duplex; 1476 if (!changed) 1477 return; 1478 1479 /* 1480 * VF's link status/speed/duplex were updated by polling from PF driver, 1481 * because the link status/speed/duplex may be changed in the polling 1482 * interval, so driver will report lse (lsc event) once any of the above 1483 * thress variables changed. 1484 * But if the PF's link status is down and driver saved link status is 1485 * also down, there are no need to report lse. 1486 */ 1487 report_lse = true; 1488 if (link_status == ETH_LINK_DOWN && link_status == mac->link_status) 1489 report_lse = false; 1490 1491 mac->link_status = link_status; 1492 mac->link_speed = link_speed; 1493 mac->link_duplex = link_duplex; 1494 1495 if (report_lse) 1496 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1497 } 1498 1499 static int 1500 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 1501 { 1502 #define HNS3VF_VLAN_MBX_MSG_LEN 5 1503 struct hns3_hw *hw = &hns->hw; 1504 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN]; 1505 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN); 1506 uint8_t is_kill = on ? 0 : 1; 1507 1508 msg_data[0] = is_kill; 1509 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1510 memcpy(&msg_data[3], &proto, sizeof(proto)); 1511 1512 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER, 1513 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL, 1514 0); 1515 } 1516 1517 static int 1518 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1519 { 1520 struct hns3_adapter *hns = dev->data->dev_private; 1521 struct hns3_hw *hw = &hns->hw; 1522 int ret; 1523 1524 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 1525 hns3_err(hw, 1526 "vf set vlan id failed during resetting, vlan_id =%u", 1527 vlan_id); 1528 return -EIO; 1529 } 1530 rte_spinlock_lock(&hw->lock); 1531 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1532 rte_spinlock_unlock(&hw->lock); 1533 if (ret) 1534 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d", 1535 vlan_id, ret); 1536 1537 return ret; 1538 } 1539 1540 static int 1541 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable) 1542 { 1543 uint8_t msg_data; 1544 int ret; 1545 1546 msg_data = enable ? 1 : 0; 1547 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG, 1548 &msg_data, sizeof(msg_data), false, NULL, 0); 1549 if (ret) 1550 hns3_err(hw, "vf enable strip failed, ret =%d", ret); 1551 1552 return ret; 1553 } 1554 1555 static int 1556 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1557 { 1558 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1559 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1560 unsigned int tmp_mask; 1561 int ret = 0; 1562 1563 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 1564 hns3_err(hw, "vf set vlan offload failed during resetting, " 1565 "mask = 0x%x", mask); 1566 return -EIO; 1567 } 1568 1569 tmp_mask = (unsigned int)mask; 1570 /* Vlan stripping setting */ 1571 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 1572 rte_spinlock_lock(&hw->lock); 1573 /* Enable or disable VLAN stripping */ 1574 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1575 ret = hns3vf_en_hw_strip_rxvtag(hw, true); 1576 else 1577 ret = hns3vf_en_hw_strip_rxvtag(hw, false); 1578 rte_spinlock_unlock(&hw->lock); 1579 } 1580 1581 return ret; 1582 } 1583 1584 static int 1585 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on) 1586 { 1587 struct rte_vlan_filter_conf *vfc; 1588 struct hns3_hw *hw = &hns->hw; 1589 uint16_t vlan_id; 1590 uint64_t vbit; 1591 uint64_t ids; 1592 int ret = 0; 1593 uint32_t i; 1594 1595 vfc = &hw->data->vlan_filter_conf; 1596 for (i = 0; i < RTE_DIM(vfc->ids); i++) { 1597 if (vfc->ids[i] == 0) 1598 continue; 1599 ids = vfc->ids[i]; 1600 while (ids) { 1601 /* 1602 * 64 means the num bits of ids, one bit corresponds to 1603 * one vlan id 1604 */ 1605 vlan_id = 64 * i; 1606 /* count trailing zeroes */ 1607 vbit = ~ids & (ids - 1); 1608 /* clear least significant bit set */ 1609 ids ^= (ids ^ (ids - 1)) ^ vbit; 1610 for (; vbit;) { 1611 vbit >>= 1; 1612 vlan_id++; 1613 } 1614 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1615 if (ret) { 1616 hns3_err(hw, 1617 "VF handle vlan table failed, ret =%d, on = %d", 1618 ret, on); 1619 return ret; 1620 } 1621 } 1622 } 1623 1624 return ret; 1625 } 1626 1627 static int 1628 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns) 1629 { 1630 return hns3vf_handle_all_vlan_table(hns, 0); 1631 } 1632 1633 static int 1634 hns3vf_restore_vlan_conf(struct hns3_adapter *hns) 1635 { 1636 struct hns3_hw *hw = &hns->hw; 1637 struct rte_eth_conf *dev_conf; 1638 bool en; 1639 int ret; 1640 1641 dev_conf = &hw->data->dev_conf; 1642 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true 1643 : false; 1644 ret = hns3vf_en_hw_strip_rxvtag(hw, en); 1645 if (ret) 1646 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en, 1647 ret); 1648 return ret; 1649 } 1650 1651 static int 1652 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev) 1653 { 1654 struct hns3_adapter *hns = dev->data->dev_private; 1655 struct rte_eth_dev_data *data = dev->data; 1656 struct hns3_hw *hw = &hns->hw; 1657 int ret; 1658 1659 if (data->dev_conf.txmode.hw_vlan_reject_tagged || 1660 data->dev_conf.txmode.hw_vlan_reject_untagged || 1661 data->dev_conf.txmode.hw_vlan_insert_pvid) { 1662 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged " 1663 "or hw_vlan_insert_pvid is not support!"); 1664 } 1665 1666 /* Apply vlan offload setting */ 1667 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK); 1668 if (ret) 1669 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret); 1670 1671 return ret; 1672 } 1673 1674 static int 1675 hns3vf_set_alive(struct hns3_hw *hw, bool alive) 1676 { 1677 uint8_t msg_data; 1678 1679 msg_data = alive ? 1 : 0; 1680 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data, 1681 sizeof(msg_data), false, NULL, 0); 1682 } 1683 1684 static void 1685 hns3vf_keep_alive_handler(void *param) 1686 { 1687 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1688 struct hns3_adapter *hns = eth_dev->data->dev_private; 1689 struct hns3_hw *hw = &hns->hw; 1690 uint8_t respmsg; 1691 int ret; 1692 1693 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0, 1694 false, &respmsg, sizeof(uint8_t)); 1695 if (ret) 1696 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)", 1697 ret); 1698 1699 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 1700 eth_dev); 1701 } 1702 1703 static void 1704 hns3vf_service_handler(void *param) 1705 { 1706 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1707 struct hns3_adapter *hns = eth_dev->data->dev_private; 1708 struct hns3_hw *hw = &hns->hw; 1709 1710 /* 1711 * The query link status and reset processing are executed in the 1712 * interrupt thread.When the IMP reset occurs, IMP will not respond, 1713 * and the query operation will time out after 30ms. In the case of 1714 * multiple PF/VFs, each query failure timeout causes the IMP reset 1715 * interrupt to fail to respond within 100ms. 1716 * Before querying the link status, check whether there is a reset 1717 * pending, and if so, abandon the query. 1718 */ 1719 if (!hns3vf_is_reset_pending(hns)) 1720 hns3vf_request_link_info(hw); 1721 else 1722 hns3_warn(hw, "Cancel the query when reset is pending"); 1723 1724 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, 1725 eth_dev); 1726 } 1727 1728 static int 1729 hns3_query_vf_resource(struct hns3_hw *hw) 1730 { 1731 struct hns3_vf_res_cmd *req; 1732 struct hns3_cmd_desc desc; 1733 uint16_t num_msi; 1734 int ret; 1735 1736 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true); 1737 ret = hns3_cmd_send(hw, &desc, 1); 1738 if (ret) { 1739 hns3_err(hw, "query vf resource failed, ret = %d", ret); 1740 return ret; 1741 } 1742 1743 req = (struct hns3_vf_res_cmd *)desc.data; 1744 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number), 1745 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S); 1746 if (num_msi < HNS3_MIN_VECTOR_NUM) { 1747 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)", 1748 num_msi, HNS3_MIN_VECTOR_NUM); 1749 return -EINVAL; 1750 } 1751 1752 hw->num_msi = num_msi; 1753 1754 return 0; 1755 } 1756 1757 static int 1758 hns3vf_init_hardware(struct hns3_adapter *hns) 1759 { 1760 struct hns3_hw *hw = &hns->hw; 1761 uint16_t mtu = hw->data->mtu; 1762 int ret; 1763 1764 ret = hns3vf_set_promisc_mode(hw, true, false, false); 1765 if (ret) 1766 return ret; 1767 1768 ret = hns3vf_config_mtu(hw, mtu); 1769 if (ret) 1770 goto err_init_hardware; 1771 1772 ret = hns3vf_vlan_filter_configure(hns, 0, 1); 1773 if (ret) { 1774 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret); 1775 goto err_init_hardware; 1776 } 1777 1778 ret = hns3_config_gro(hw, false); 1779 if (ret) { 1780 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 1781 goto err_init_hardware; 1782 } 1783 1784 /* 1785 * In the initialization clearing the all hardware mapping relationship 1786 * configurations between queues and interrupt vectors is needed, so 1787 * some error caused by the residual configurations, such as the 1788 * unexpected interrupt, can be avoid. 1789 */ 1790 ret = hns3vf_init_ring_with_vector(hw); 1791 if (ret) { 1792 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 1793 goto err_init_hardware; 1794 } 1795 1796 ret = hns3vf_set_alive(hw, true); 1797 if (ret) { 1798 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret); 1799 goto err_init_hardware; 1800 } 1801 1802 return 0; 1803 1804 err_init_hardware: 1805 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1806 return ret; 1807 } 1808 1809 static int 1810 hns3vf_clear_vport_list(struct hns3_hw *hw) 1811 { 1812 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL, 1813 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false, 1814 NULL, 0); 1815 } 1816 1817 static int 1818 hns3vf_init_vf(struct rte_eth_dev *eth_dev) 1819 { 1820 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1821 struct hns3_adapter *hns = eth_dev->data->dev_private; 1822 struct hns3_hw *hw = &hns->hw; 1823 int ret; 1824 1825 PMD_INIT_FUNC_TRACE(); 1826 1827 /* Get hardware io base address from pcie BAR2 IO space */ 1828 hw->io_base = pci_dev->mem_resource[2].addr; 1829 1830 /* Firmware command queue initialize */ 1831 ret = hns3_cmd_init_queue(hw); 1832 if (ret) { 1833 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 1834 goto err_cmd_init_queue; 1835 } 1836 1837 /* Firmware command initialize */ 1838 ret = hns3_cmd_init(hw); 1839 if (ret) { 1840 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 1841 goto err_cmd_init; 1842 } 1843 1844 /* Get VF resource */ 1845 ret = hns3_query_vf_resource(hw); 1846 if (ret) 1847 goto err_cmd_init; 1848 1849 rte_spinlock_init(&hw->mbx_resp.lock); 1850 1851 hns3vf_clear_event_cause(hw, 0); 1852 1853 ret = rte_intr_callback_register(&pci_dev->intr_handle, 1854 hns3vf_interrupt_handler, eth_dev); 1855 if (ret) { 1856 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 1857 goto err_intr_callback_register; 1858 } 1859 1860 /* Enable interrupt */ 1861 rte_intr_enable(&pci_dev->intr_handle); 1862 hns3vf_enable_irq0(hw); 1863 1864 /* Get configuration from PF */ 1865 ret = hns3vf_get_configuration(hw); 1866 if (ret) { 1867 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 1868 goto err_get_config; 1869 } 1870 1871 ret = hns3_tqp_stats_init(hw); 1872 if (ret) 1873 goto err_get_config; 1874 1875 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); 1876 if (ret) { 1877 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); 1878 goto err_set_tc_queue; 1879 } 1880 1881 ret = hns3vf_clear_vport_list(hw); 1882 if (ret) { 1883 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret); 1884 goto err_set_tc_queue; 1885 } 1886 1887 ret = hns3vf_init_hardware(hns); 1888 if (ret) 1889 goto err_set_tc_queue; 1890 1891 hns3_rss_set_default_args(hw); 1892 1893 return 0; 1894 1895 err_set_tc_queue: 1896 hns3_tqp_stats_uninit(hw); 1897 1898 err_get_config: 1899 hns3vf_disable_irq0(hw); 1900 rte_intr_disable(&pci_dev->intr_handle); 1901 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 1902 eth_dev); 1903 err_intr_callback_register: 1904 err_cmd_init: 1905 hns3_cmd_uninit(hw); 1906 hns3_cmd_destroy_queue(hw); 1907 err_cmd_init_queue: 1908 hw->io_base = NULL; 1909 1910 return ret; 1911 } 1912 1913 static void 1914 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev) 1915 { 1916 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1917 struct hns3_adapter *hns = eth_dev->data->dev_private; 1918 struct hns3_hw *hw = &hns->hw; 1919 1920 PMD_INIT_FUNC_TRACE(); 1921 1922 hns3_rss_uninit(hns); 1923 (void)hns3_config_gro(hw, false); 1924 (void)hns3vf_set_alive(hw, false); 1925 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1926 hns3_tqp_stats_uninit(hw); 1927 hns3vf_disable_irq0(hw); 1928 rte_intr_disable(&pci_dev->intr_handle); 1929 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 1930 eth_dev); 1931 hns3_cmd_uninit(hw); 1932 hns3_cmd_destroy_queue(hw); 1933 hw->io_base = NULL; 1934 } 1935 1936 static int 1937 hns3vf_do_stop(struct hns3_adapter *hns) 1938 { 1939 struct hns3_hw *hw = &hns->hw; 1940 int ret; 1941 1942 hw->mac.link_status = ETH_LINK_DOWN; 1943 1944 /* 1945 * The "hns3vf_do_stop" function will also be called by .stop_service to 1946 * prepare reset. At the time of global or IMP reset, the command cannot 1947 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 1948 * accessed during the reset process. So the mbuf can not be released 1949 * during reset and is required to be released after the reset is 1950 * completed. 1951 */ 1952 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 1953 hns3_dev_release_mbufs(hns); 1954 1955 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 1956 hns3vf_configure_mac_addr(hns, true); 1957 ret = hns3_reset_all_tqps(hns); 1958 if (ret) { 1959 hns3_err(hw, "failed to reset all queues ret = %d", 1960 ret); 1961 return ret; 1962 } 1963 } 1964 return 0; 1965 } 1966 1967 static void 1968 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev) 1969 { 1970 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1971 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1972 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1973 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 1974 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 1975 uint16_t q_id; 1976 1977 if (dev->data->dev_conf.intr_conf.rxq == 0) 1978 return; 1979 1980 /* unmap the ring with vector */ 1981 if (rte_intr_allow_others(intr_handle)) { 1982 vec = RTE_INTR_VEC_RXTX_OFFSET; 1983 base = RTE_INTR_VEC_RXTX_OFFSET; 1984 } 1985 if (rte_intr_dp_is_en(intr_handle)) { 1986 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 1987 (void)hns3vf_bind_ring_with_vector(hw, vec, false, 1988 HNS3_RING_TYPE_RX, 1989 q_id); 1990 if (vec < base + intr_handle->nb_efd - 1) 1991 vec++; 1992 } 1993 } 1994 /* Clean datapath event and queue/vec mapping */ 1995 rte_intr_efd_disable(intr_handle); 1996 if (intr_handle->intr_vec) { 1997 rte_free(intr_handle->intr_vec); 1998 intr_handle->intr_vec = NULL; 1999 } 2000 } 2001 2002 static int 2003 hns3vf_dev_stop(struct rte_eth_dev *dev) 2004 { 2005 struct hns3_adapter *hns = dev->data->dev_private; 2006 struct hns3_hw *hw = &hns->hw; 2007 2008 PMD_INIT_FUNC_TRACE(); 2009 dev->data->dev_started = 0; 2010 2011 hw->adapter_state = HNS3_NIC_STOPPING; 2012 hns3_set_rxtx_function(dev); 2013 rte_wmb(); 2014 /* Disable datapath on secondary process. */ 2015 hns3_mp_req_stop_rxtx(dev); 2016 /* Prevent crashes when queues are still in use. */ 2017 rte_delay_ms(hw->tqps_num); 2018 2019 rte_spinlock_lock(&hw->lock); 2020 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 2021 hns3_stop_tqps(hw); 2022 hns3vf_do_stop(hns); 2023 hns3vf_unmap_rx_interrupt(dev); 2024 hw->adapter_state = HNS3_NIC_CONFIGURED; 2025 } 2026 hns3_rx_scattered_reset(dev); 2027 rte_eal_alarm_cancel(hns3vf_service_handler, dev); 2028 rte_spinlock_unlock(&hw->lock); 2029 2030 return 0; 2031 } 2032 2033 static int 2034 hns3vf_dev_close(struct rte_eth_dev *eth_dev) 2035 { 2036 struct hns3_adapter *hns = eth_dev->data->dev_private; 2037 struct hns3_hw *hw = &hns->hw; 2038 int ret = 0; 2039 2040 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2041 rte_free(eth_dev->process_private); 2042 eth_dev->process_private = NULL; 2043 return 0; 2044 } 2045 2046 if (hw->adapter_state == HNS3_NIC_STARTED) 2047 ret = hns3vf_dev_stop(eth_dev); 2048 2049 hw->adapter_state = HNS3_NIC_CLOSING; 2050 hns3_reset_abort(hns); 2051 hw->adapter_state = HNS3_NIC_CLOSED; 2052 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev); 2053 hns3vf_configure_all_mc_mac_addr(hns, true); 2054 hns3vf_remove_all_vlan_table(hns); 2055 hns3vf_uninit_vf(eth_dev); 2056 hns3_free_all_queues(eth_dev); 2057 rte_free(hw->reset.wait_data); 2058 rte_free(eth_dev->process_private); 2059 eth_dev->process_private = NULL; 2060 hns3_mp_uninit_primary(); 2061 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 2062 2063 return ret; 2064 } 2065 2066 static int 2067 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2068 size_t fw_size) 2069 { 2070 struct hns3_adapter *hns = eth_dev->data->dev_private; 2071 struct hns3_hw *hw = &hns->hw; 2072 uint32_t version = hw->fw_version; 2073 int ret; 2074 2075 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2076 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2077 HNS3_FW_VERSION_BYTE3_S), 2078 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2079 HNS3_FW_VERSION_BYTE2_S), 2080 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2081 HNS3_FW_VERSION_BYTE1_S), 2082 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2083 HNS3_FW_VERSION_BYTE0_S)); 2084 ret += 1; /* add the size of '\0' */ 2085 if (fw_size < (uint32_t)ret) 2086 return ret; 2087 else 2088 return 0; 2089 } 2090 2091 static int 2092 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, 2093 __rte_unused int wait_to_complete) 2094 { 2095 struct hns3_adapter *hns = eth_dev->data->dev_private; 2096 struct hns3_hw *hw = &hns->hw; 2097 struct hns3_mac *mac = &hw->mac; 2098 struct rte_eth_link new_link; 2099 2100 memset(&new_link, 0, sizeof(new_link)); 2101 switch (mac->link_speed) { 2102 case ETH_SPEED_NUM_10M: 2103 case ETH_SPEED_NUM_100M: 2104 case ETH_SPEED_NUM_1G: 2105 case ETH_SPEED_NUM_10G: 2106 case ETH_SPEED_NUM_25G: 2107 case ETH_SPEED_NUM_40G: 2108 case ETH_SPEED_NUM_50G: 2109 case ETH_SPEED_NUM_100G: 2110 case ETH_SPEED_NUM_200G: 2111 new_link.link_speed = mac->link_speed; 2112 break; 2113 default: 2114 new_link.link_speed = ETH_SPEED_NUM_100M; 2115 break; 2116 } 2117 2118 new_link.link_duplex = mac->link_duplex; 2119 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2120 new_link.link_autoneg = 2121 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2122 2123 return rte_eth_linkstatus_set(eth_dev, &new_link); 2124 } 2125 2126 static int 2127 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue) 2128 { 2129 struct hns3_hw *hw = &hns->hw; 2130 uint16_t nb_rx_q = hw->data->nb_rx_queues; 2131 uint16_t nb_tx_q = hw->data->nb_tx_queues; 2132 int ret; 2133 2134 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q); 2135 if (ret) 2136 return ret; 2137 2138 hns3_enable_rxd_adv_layout(hw); 2139 2140 ret = hns3_init_queues(hns, reset_queue); 2141 if (ret) 2142 hns3_err(hw, "failed to init queues, ret = %d.", ret); 2143 2144 return ret; 2145 } 2146 2147 static int 2148 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) 2149 { 2150 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2151 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2152 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2153 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 2154 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 2155 uint32_t intr_vector; 2156 uint16_t q_id; 2157 int ret; 2158 2159 /* 2160 * hns3 needs a separate interrupt to be used as event interrupt which 2161 * could not be shared with task queue pair, so KERNEL drivers need 2162 * support multiple interrupt vectors. 2163 */ 2164 if (dev->data->dev_conf.intr_conf.rxq == 0 || 2165 !rte_intr_cap_multiple(intr_handle)) 2166 return 0; 2167 2168 rte_intr_disable(intr_handle); 2169 intr_vector = hw->used_rx_queues; 2170 /* It creates event fd for each intr vector when MSIX is used */ 2171 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2172 return -EINVAL; 2173 2174 if (intr_handle->intr_vec == NULL) { 2175 intr_handle->intr_vec = 2176 rte_zmalloc("intr_vec", 2177 hw->used_rx_queues * sizeof(int), 0); 2178 if (intr_handle->intr_vec == NULL) { 2179 hns3_err(hw, "Failed to allocate %u rx_queues" 2180 " intr_vec", hw->used_rx_queues); 2181 ret = -ENOMEM; 2182 goto vf_alloc_intr_vec_error; 2183 } 2184 } 2185 2186 if (rte_intr_allow_others(intr_handle)) { 2187 vec = RTE_INTR_VEC_RXTX_OFFSET; 2188 base = RTE_INTR_VEC_RXTX_OFFSET; 2189 } 2190 2191 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2192 ret = hns3vf_bind_ring_with_vector(hw, vec, true, 2193 HNS3_RING_TYPE_RX, q_id); 2194 if (ret) 2195 goto vf_bind_vector_error; 2196 intr_handle->intr_vec[q_id] = vec; 2197 /* 2198 * If there are not enough efds (e.g. not enough interrupt), 2199 * remaining queues will be bond to the last interrupt. 2200 */ 2201 if (vec < base + intr_handle->nb_efd - 1) 2202 vec++; 2203 } 2204 rte_intr_enable(intr_handle); 2205 return 0; 2206 2207 vf_bind_vector_error: 2208 free(intr_handle->intr_vec); 2209 intr_handle->intr_vec = NULL; 2210 vf_alloc_intr_vec_error: 2211 rte_intr_efd_disable(intr_handle); 2212 return ret; 2213 } 2214 2215 static int 2216 hns3vf_restore_rx_interrupt(struct hns3_hw *hw) 2217 { 2218 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 2219 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2220 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2221 uint16_t q_id; 2222 int ret; 2223 2224 if (dev->data->dev_conf.intr_conf.rxq == 0) 2225 return 0; 2226 2227 if (rte_intr_dp_is_en(intr_handle)) { 2228 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2229 ret = hns3vf_bind_ring_with_vector(hw, 2230 intr_handle->intr_vec[q_id], true, 2231 HNS3_RING_TYPE_RX, q_id); 2232 if (ret) 2233 return ret; 2234 } 2235 } 2236 2237 return 0; 2238 } 2239 2240 static void 2241 hns3vf_restore_filter(struct rte_eth_dev *dev) 2242 { 2243 hns3_restore_rss_filter(dev); 2244 } 2245 2246 static int 2247 hns3vf_dev_start(struct rte_eth_dev *dev) 2248 { 2249 struct hns3_adapter *hns = dev->data->dev_private; 2250 struct hns3_hw *hw = &hns->hw; 2251 int ret; 2252 2253 PMD_INIT_FUNC_TRACE(); 2254 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 2255 return -EBUSY; 2256 2257 rte_spinlock_lock(&hw->lock); 2258 hw->adapter_state = HNS3_NIC_STARTING; 2259 ret = hns3vf_do_start(hns, true); 2260 if (ret) { 2261 hw->adapter_state = HNS3_NIC_CONFIGURED; 2262 rte_spinlock_unlock(&hw->lock); 2263 return ret; 2264 } 2265 ret = hns3vf_map_rx_interrupt(dev); 2266 if (ret) 2267 goto map_rx_inter_err; 2268 2269 /* 2270 * There are three register used to control the status of a TQP 2271 * (contains a pair of Tx queue and Rx queue) in the new version network 2272 * engine. One is used to control the enabling of Tx queue, the other is 2273 * used to control the enabling of Rx queue, and the last is the master 2274 * switch used to control the enabling of the tqp. The Tx register and 2275 * TQP register must be enabled at the same time to enable a Tx queue. 2276 * The same applies to the Rx queue. For the older network enginem, this 2277 * function only refresh the enabled flag, and it is used to update the 2278 * status of queue in the dpdk framework. 2279 */ 2280 ret = hns3_start_all_txqs(dev); 2281 if (ret) 2282 goto map_rx_inter_err; 2283 2284 ret = hns3_start_all_rxqs(dev); 2285 if (ret) 2286 goto start_all_rxqs_fail; 2287 2288 hw->adapter_state = HNS3_NIC_STARTED; 2289 rte_spinlock_unlock(&hw->lock); 2290 2291 hns3_rx_scattered_calc(dev); 2292 hns3_set_rxtx_function(dev); 2293 hns3_mp_req_start_rxtx(dev); 2294 hns3vf_service_handler(dev); 2295 2296 hns3vf_restore_filter(dev); 2297 2298 /* Enable interrupt of all rx queues before enabling queues */ 2299 hns3_dev_all_rx_queue_intr_enable(hw, true); 2300 2301 /* 2302 * After finished the initialization, start all tqps to receive/transmit 2303 * packets and refresh all queue status. 2304 */ 2305 hns3_start_tqps(hw); 2306 2307 return ret; 2308 2309 start_all_rxqs_fail: 2310 hns3_stop_all_txqs(dev); 2311 map_rx_inter_err: 2312 (void)hns3vf_do_stop(hns); 2313 hw->adapter_state = HNS3_NIC_CONFIGURED; 2314 rte_spinlock_unlock(&hw->lock); 2315 2316 return ret; 2317 } 2318 2319 static bool 2320 is_vf_reset_done(struct hns3_hw *hw) 2321 { 2322 #define HNS3_FUN_RST_ING_BITS \ 2323 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \ 2324 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \ 2325 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \ 2326 BIT(HNS3_VECTOR0_FUNCRESET_INT_B)) 2327 2328 uint32_t val; 2329 2330 if (hw->reset.level == HNS3_VF_RESET) { 2331 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 2332 if (val & HNS3_VF_RST_ING_BIT) 2333 return false; 2334 } else { 2335 val = hns3_read_dev(hw, HNS3_FUN_RST_ING); 2336 if (val & HNS3_FUN_RST_ING_BITS) 2337 return false; 2338 } 2339 return true; 2340 } 2341 2342 bool 2343 hns3vf_is_reset_pending(struct hns3_adapter *hns) 2344 { 2345 struct hns3_hw *hw = &hns->hw; 2346 enum hns3_reset_level reset; 2347 2348 /* 2349 * According to the protocol of PCIe, FLR to a PF device resets the PF 2350 * state as well as the SR-IOV extended capability including VF Enable 2351 * which means that VFs no longer exist. 2352 * 2353 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device 2354 * is in FLR stage, the register state of VF device is not reliable, 2355 * so register states detection can not be carried out. In this case, 2356 * we just ignore the register states and return false to indicate that 2357 * there are no other reset states that need to be processed by driver. 2358 */ 2359 if (hw->reset.level == HNS3_VF_FULL_RESET) 2360 return false; 2361 2362 /* Check the registers to confirm whether there is reset pending */ 2363 hns3vf_check_event_cause(hns, NULL); 2364 reset = hns3vf_get_reset_level(hw, &hw->reset.pending); 2365 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 2366 hns3_warn(hw, "High level reset %d is pending", reset); 2367 return true; 2368 } 2369 return false; 2370 } 2371 2372 static int 2373 hns3vf_wait_hardware_ready(struct hns3_adapter *hns) 2374 { 2375 struct hns3_hw *hw = &hns->hw; 2376 struct hns3_wait_data *wait_data = hw->reset.wait_data; 2377 struct timeval tv; 2378 2379 if (wait_data->result == HNS3_WAIT_SUCCESS) { 2380 /* 2381 * After vf reset is ready, the PF may not have completed 2382 * the reset processing. The vf sending mbox to PF may fail 2383 * during the pf reset, so it is better to add extra delay. 2384 */ 2385 if (hw->reset.level == HNS3_VF_FUNC_RESET || 2386 hw->reset.level == HNS3_FLR_RESET) 2387 return 0; 2388 /* Reset retry process, no need to add extra delay. */ 2389 if (hw->reset.attempts) 2390 return 0; 2391 if (wait_data->check_completion == NULL) 2392 return 0; 2393 2394 wait_data->check_completion = NULL; 2395 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC; 2396 wait_data->count = 1; 2397 wait_data->result = HNS3_WAIT_REQUEST; 2398 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, 2399 wait_data); 2400 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); 2401 return -EAGAIN; 2402 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 2403 gettimeofday(&tv, NULL); 2404 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 2405 tv.tv_sec, tv.tv_usec); 2406 return -ETIME; 2407 } else if (wait_data->result == HNS3_WAIT_REQUEST) 2408 return -EAGAIN; 2409 2410 wait_data->hns = hns; 2411 wait_data->check_completion = is_vf_reset_done; 2412 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT * 2413 HNS3VF_RESET_WAIT_MS + get_timeofday_ms(); 2414 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC; 2415 wait_data->count = HNS3VF_RESET_WAIT_CNT; 2416 wait_data->result = HNS3_WAIT_REQUEST; 2417 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 2418 return -EAGAIN; 2419 } 2420 2421 static int 2422 hns3vf_prepare_reset(struct hns3_adapter *hns) 2423 { 2424 struct hns3_hw *hw = &hns->hw; 2425 int ret; 2426 2427 if (hw->reset.level == HNS3_VF_FUNC_RESET) { 2428 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL, 2429 0, true, NULL, 0); 2430 if (ret) 2431 return ret; 2432 } 2433 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 2434 2435 return 0; 2436 } 2437 2438 static int 2439 hns3vf_stop_service(struct hns3_adapter *hns) 2440 { 2441 struct hns3_hw *hw = &hns->hw; 2442 struct rte_eth_dev *eth_dev; 2443 2444 eth_dev = &rte_eth_devices[hw->data->port_id]; 2445 if (hw->adapter_state == HNS3_NIC_STARTED) { 2446 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev); 2447 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed, 2448 hw->mac.link_duplex); 2449 } 2450 hw->mac.link_status = ETH_LINK_DOWN; 2451 2452 hns3_set_rxtx_function(eth_dev); 2453 rte_wmb(); 2454 /* Disable datapath on secondary process. */ 2455 hns3_mp_req_stop_rxtx(eth_dev); 2456 rte_delay_ms(hw->tqps_num); 2457 2458 rte_spinlock_lock(&hw->lock); 2459 if (hw->adapter_state == HNS3_NIC_STARTED || 2460 hw->adapter_state == HNS3_NIC_STOPPING) { 2461 hns3_enable_all_queues(hw, false); 2462 hns3vf_do_stop(hns); 2463 hw->reset.mbuf_deferred_free = true; 2464 } else 2465 hw->reset.mbuf_deferred_free = false; 2466 2467 /* 2468 * It is cumbersome for hardware to pick-and-choose entries for deletion 2469 * from table space. Hence, for function reset software intervention is 2470 * required to delete the entries. 2471 */ 2472 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 2473 hns3vf_configure_all_mc_mac_addr(hns, true); 2474 rte_spinlock_unlock(&hw->lock); 2475 2476 return 0; 2477 } 2478 2479 static int 2480 hns3vf_start_service(struct hns3_adapter *hns) 2481 { 2482 struct hns3_hw *hw = &hns->hw; 2483 struct rte_eth_dev *eth_dev; 2484 2485 eth_dev = &rte_eth_devices[hw->data->port_id]; 2486 hns3_set_rxtx_function(eth_dev); 2487 hns3_mp_req_start_rxtx(eth_dev); 2488 if (hw->adapter_state == HNS3_NIC_STARTED) { 2489 hns3vf_service_handler(eth_dev); 2490 2491 /* Enable interrupt of all rx queues before enabling queues */ 2492 hns3_dev_all_rx_queue_intr_enable(hw, true); 2493 /* 2494 * Enable state of each rxq and txq will be recovered after 2495 * reset, so we need to restore them before enable all tqps; 2496 */ 2497 hns3_restore_tqp_enable_state(hw); 2498 /* 2499 * When finished the initialization, enable queues to receive 2500 * and transmit packets. 2501 */ 2502 hns3_enable_all_queues(hw, true); 2503 } 2504 2505 return 0; 2506 } 2507 2508 static int 2509 hns3vf_check_default_mac_change(struct hns3_hw *hw) 2510 { 2511 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2512 struct rte_ether_addr *hw_mac; 2513 int ret; 2514 2515 /* 2516 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2517 * on the host by "ip link set ..." command. If the hns3 PF kernel 2518 * ethdev driver sets the MAC address for VF device after the 2519 * initialization of the related VF device, the PF driver will notify 2520 * VF driver to reset VF device to make the new MAC address effective 2521 * immediately. The hns3 VF PMD driver should check whether the MAC 2522 * address has been changed by the PF kernel ethdev driver, if changed 2523 * VF driver should configure hardware using the new MAC address in the 2524 * recovering hardware configuration stage of the reset process. 2525 */ 2526 ret = hns3vf_get_host_mac_addr(hw); 2527 if (ret) 2528 return ret; 2529 2530 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr; 2531 ret = rte_is_zero_ether_addr(hw_mac); 2532 if (ret) { 2533 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac); 2534 } else { 2535 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac); 2536 if (!ret) { 2537 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]); 2538 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2539 &hw->data->mac_addrs[0]); 2540 hns3_warn(hw, "Default MAC address has been changed to:" 2541 " %s by the host PF kernel ethdev driver", 2542 mac_str); 2543 } 2544 } 2545 2546 return 0; 2547 } 2548 2549 static int 2550 hns3vf_restore_conf(struct hns3_adapter *hns) 2551 { 2552 struct hns3_hw *hw = &hns->hw; 2553 int ret; 2554 2555 ret = hns3vf_check_default_mac_change(hw); 2556 if (ret) 2557 return ret; 2558 2559 ret = hns3vf_configure_mac_addr(hns, false); 2560 if (ret) 2561 return ret; 2562 2563 ret = hns3vf_configure_all_mc_mac_addr(hns, false); 2564 if (ret) 2565 goto err_mc_mac; 2566 2567 ret = hns3vf_restore_promisc(hns); 2568 if (ret) 2569 goto err_vlan_table; 2570 2571 ret = hns3vf_restore_vlan_conf(hns); 2572 if (ret) 2573 goto err_vlan_table; 2574 2575 ret = hns3vf_get_port_base_vlan_filter_state(hw); 2576 if (ret) 2577 goto err_vlan_table; 2578 2579 ret = hns3vf_restore_rx_interrupt(hw); 2580 if (ret) 2581 goto err_vlan_table; 2582 2583 ret = hns3_restore_gro_conf(hw); 2584 if (ret) 2585 goto err_vlan_table; 2586 2587 if (hw->adapter_state == HNS3_NIC_STARTED) { 2588 ret = hns3vf_do_start(hns, false); 2589 if (ret) 2590 goto err_vlan_table; 2591 hns3_info(hw, "hns3vf dev restart successful!"); 2592 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 2593 hw->adapter_state = HNS3_NIC_CONFIGURED; 2594 return 0; 2595 2596 err_vlan_table: 2597 hns3vf_configure_all_mc_mac_addr(hns, true); 2598 err_mc_mac: 2599 hns3vf_configure_mac_addr(hns, true); 2600 return ret; 2601 } 2602 2603 static enum hns3_reset_level 2604 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels) 2605 { 2606 enum hns3_reset_level reset_level; 2607 2608 /* return the highest priority reset level amongst all */ 2609 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels)) 2610 reset_level = HNS3_VF_RESET; 2611 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels)) 2612 reset_level = HNS3_VF_FULL_RESET; 2613 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels)) 2614 reset_level = HNS3_VF_PF_FUNC_RESET; 2615 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels)) 2616 reset_level = HNS3_VF_FUNC_RESET; 2617 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 2618 reset_level = HNS3_FLR_RESET; 2619 else 2620 reset_level = HNS3_NONE_RESET; 2621 2622 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 2623 return HNS3_NONE_RESET; 2624 2625 return reset_level; 2626 } 2627 2628 static void 2629 hns3vf_reset_service(void *param) 2630 { 2631 struct hns3_adapter *hns = (struct hns3_adapter *)param; 2632 struct hns3_hw *hw = &hns->hw; 2633 enum hns3_reset_level reset_level; 2634 struct timeval tv_delta; 2635 struct timeval tv_start; 2636 struct timeval tv; 2637 uint64_t msec; 2638 2639 /* 2640 * The interrupt is not triggered within the delay time. 2641 * The interrupt may have been lost. It is necessary to handle 2642 * the interrupt to recover from the error. 2643 */ 2644 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2645 SCHEDULE_DEFERRED) { 2646 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 2647 __ATOMIC_RELAXED); 2648 hns3_err(hw, "Handling interrupts in delayed tasks"); 2649 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 2650 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2651 if (reset_level == HNS3_NONE_RESET) { 2652 hns3_err(hw, "No reset level is set, try global reset"); 2653 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 2654 } 2655 } 2656 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 2657 2658 /* 2659 * Hardware reset has been notified, we now have to poll & check if 2660 * hardware has actually completed the reset sequence. 2661 */ 2662 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2663 if (reset_level != HNS3_NONE_RESET) { 2664 gettimeofday(&tv_start, NULL); 2665 hns3_reset_process(hns, reset_level); 2666 gettimeofday(&tv, NULL); 2667 timersub(&tv, &tv_start, &tv_delta); 2668 msec = tv_delta.tv_sec * MSEC_PER_SEC + 2669 tv_delta.tv_usec / USEC_PER_MSEC; 2670 if (msec > HNS3_RESET_PROCESS_MS) 2671 hns3_err(hw, "%d handle long time delta %" PRIx64 2672 " ms time=%ld.%.6ld", 2673 hw->reset.level, msec, tv.tv_sec, tv.tv_usec); 2674 } 2675 } 2676 2677 static int 2678 hns3vf_reinit_dev(struct hns3_adapter *hns) 2679 { 2680 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id]; 2681 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2682 struct hns3_hw *hw = &hns->hw; 2683 int ret; 2684 2685 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2686 rte_intr_disable(&pci_dev->intr_handle); 2687 ret = hns3vf_set_bus_master(pci_dev, true); 2688 if (ret < 0) { 2689 hns3_err(hw, "failed to set pci bus, ret = %d", ret); 2690 return ret; 2691 } 2692 } 2693 2694 /* Firmware command initialize */ 2695 ret = hns3_cmd_init(hw); 2696 if (ret) { 2697 hns3_err(hw, "Failed to init cmd: %d", ret); 2698 return ret; 2699 } 2700 2701 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2702 /* 2703 * UIO enables msix by writing the pcie configuration space 2704 * vfio_pci enables msix in rte_intr_enable. 2705 */ 2706 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO || 2707 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) { 2708 if (hns3vf_enable_msix(pci_dev, true)) 2709 hns3_err(hw, "Failed to enable msix"); 2710 } 2711 2712 rte_intr_enable(&pci_dev->intr_handle); 2713 } 2714 2715 ret = hns3_reset_all_tqps(hns); 2716 if (ret) { 2717 hns3_err(hw, "Failed to reset all queues: %d", ret); 2718 return ret; 2719 } 2720 2721 ret = hns3vf_init_hardware(hns); 2722 if (ret) { 2723 hns3_err(hw, "Failed to init hardware: %d", ret); 2724 return ret; 2725 } 2726 2727 return 0; 2728 } 2729 2730 static const struct eth_dev_ops hns3vf_eth_dev_ops = { 2731 .dev_configure = hns3vf_dev_configure, 2732 .dev_start = hns3vf_dev_start, 2733 .dev_stop = hns3vf_dev_stop, 2734 .dev_close = hns3vf_dev_close, 2735 .mtu_set = hns3vf_dev_mtu_set, 2736 .promiscuous_enable = hns3vf_dev_promiscuous_enable, 2737 .promiscuous_disable = hns3vf_dev_promiscuous_disable, 2738 .allmulticast_enable = hns3vf_dev_allmulticast_enable, 2739 .allmulticast_disable = hns3vf_dev_allmulticast_disable, 2740 .stats_get = hns3_stats_get, 2741 .stats_reset = hns3_stats_reset, 2742 .xstats_get = hns3_dev_xstats_get, 2743 .xstats_get_names = hns3_dev_xstats_get_names, 2744 .xstats_reset = hns3_dev_xstats_reset, 2745 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 2746 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 2747 .dev_infos_get = hns3vf_dev_infos_get, 2748 .fw_version_get = hns3vf_fw_version_get, 2749 .rx_queue_setup = hns3_rx_queue_setup, 2750 .tx_queue_setup = hns3_tx_queue_setup, 2751 .rx_queue_release = hns3_dev_rx_queue_release, 2752 .tx_queue_release = hns3_dev_tx_queue_release, 2753 .rx_queue_start = hns3_dev_rx_queue_start, 2754 .rx_queue_stop = hns3_dev_rx_queue_stop, 2755 .tx_queue_start = hns3_dev_tx_queue_start, 2756 .tx_queue_stop = hns3_dev_tx_queue_stop, 2757 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 2758 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 2759 .rxq_info_get = hns3_rxq_info_get, 2760 .txq_info_get = hns3_txq_info_get, 2761 .rx_burst_mode_get = hns3_rx_burst_mode_get, 2762 .tx_burst_mode_get = hns3_tx_burst_mode_get, 2763 .mac_addr_add = hns3vf_add_mac_addr, 2764 .mac_addr_remove = hns3vf_remove_mac_addr, 2765 .mac_addr_set = hns3vf_set_default_mac_addr, 2766 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list, 2767 .link_update = hns3vf_dev_link_update, 2768 .rss_hash_update = hns3_dev_rss_hash_update, 2769 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 2770 .reta_update = hns3_dev_rss_reta_update, 2771 .reta_query = hns3_dev_rss_reta_query, 2772 .filter_ctrl = hns3_dev_filter_ctrl, 2773 .vlan_filter_set = hns3vf_vlan_filter_set, 2774 .vlan_offload_set = hns3vf_vlan_offload_set, 2775 .get_reg = hns3_get_regs, 2776 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 2777 .tx_done_cleanup = hns3_tx_done_cleanup, 2778 }; 2779 2780 static const struct hns3_reset_ops hns3vf_reset_ops = { 2781 .reset_service = hns3vf_reset_service, 2782 .stop_service = hns3vf_stop_service, 2783 .prepare_reset = hns3vf_prepare_reset, 2784 .wait_hardware_ready = hns3vf_wait_hardware_ready, 2785 .reinit_dev = hns3vf_reinit_dev, 2786 .restore_conf = hns3vf_restore_conf, 2787 .start_service = hns3vf_start_service, 2788 }; 2789 2790 static int 2791 hns3vf_dev_init(struct rte_eth_dev *eth_dev) 2792 { 2793 struct hns3_adapter *hns = eth_dev->data->dev_private; 2794 struct hns3_hw *hw = &hns->hw; 2795 int ret; 2796 2797 PMD_INIT_FUNC_TRACE(); 2798 2799 eth_dev->process_private = (struct hns3_process_private *) 2800 rte_zmalloc_socket("hns3_filter_list", 2801 sizeof(struct hns3_process_private), 2802 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 2803 if (eth_dev->process_private == NULL) { 2804 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 2805 return -ENOMEM; 2806 } 2807 2808 /* initialize flow filter lists */ 2809 hns3_filterlist_init(eth_dev); 2810 2811 hns3_set_rxtx_function(eth_dev); 2812 eth_dev->dev_ops = &hns3vf_eth_dev_ops; 2813 eth_dev->rx_queue_count = hns3_rx_queue_count; 2814 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2815 ret = hns3_mp_init_secondary(); 2816 if (ret) { 2817 PMD_INIT_LOG(ERR, "Failed to init for secondary " 2818 "process, ret = %d", ret); 2819 goto err_mp_init_secondary; 2820 } 2821 2822 hw->secondary_cnt++; 2823 return 0; 2824 } 2825 2826 ret = hns3_mp_init_primary(); 2827 if (ret) { 2828 PMD_INIT_LOG(ERR, 2829 "Failed to init for primary process, ret = %d", 2830 ret); 2831 goto err_mp_init_primary; 2832 } 2833 2834 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 2835 hns->is_vf = true; 2836 hw->data = eth_dev->data; 2837 2838 ret = hns3_reset_init(hw); 2839 if (ret) 2840 goto err_init_reset; 2841 hw->reset.ops = &hns3vf_reset_ops; 2842 2843 ret = hns3vf_init_vf(eth_dev); 2844 if (ret) { 2845 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret); 2846 goto err_init_vf; 2847 } 2848 2849 /* Allocate memory for storing MAC addresses */ 2850 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac", 2851 sizeof(struct rte_ether_addr) * 2852 HNS3_VF_UC_MACADDR_NUM, 0); 2853 if (eth_dev->data->mac_addrs == NULL) { 2854 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 2855 "to store MAC addresses", 2856 sizeof(struct rte_ether_addr) * 2857 HNS3_VF_UC_MACADDR_NUM); 2858 ret = -ENOMEM; 2859 goto err_rte_zmalloc; 2860 } 2861 2862 /* 2863 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2864 * on the host by "ip link set ..." command. To avoid some incorrect 2865 * scenes, for example, hns3 VF PMD driver fails to receive and send 2866 * packets after user configure the MAC address by using the 2867 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC 2868 * address strategy as the hns3 kernel ethdev driver in the 2869 * initialization. If user configure a MAC address by the ip command 2870 * for VF device, then hns3 VF PMD driver will start with it, otherwise 2871 * start with a random MAC address in the initialization. 2872 */ 2873 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr)) 2874 rte_eth_random_addr(hw->mac.mac_addr); 2875 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 2876 ð_dev->data->mac_addrs[0]); 2877 2878 hw->adapter_state = HNS3_NIC_INITIALIZED; 2879 2880 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2881 SCHEDULE_PENDING) { 2882 hns3_err(hw, "Reschedule reset service after dev_init"); 2883 hns3_schedule_reset(hns); 2884 } else { 2885 /* IMP will wait ready flag before reset */ 2886 hns3_notify_reset_ready(hw, false); 2887 } 2888 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 2889 eth_dev); 2890 return 0; 2891 2892 err_rte_zmalloc: 2893 hns3vf_uninit_vf(eth_dev); 2894 2895 err_init_vf: 2896 rte_free(hw->reset.wait_data); 2897 2898 err_init_reset: 2899 hns3_mp_uninit_primary(); 2900 2901 err_mp_init_primary: 2902 err_mp_init_secondary: 2903 eth_dev->dev_ops = NULL; 2904 eth_dev->rx_pkt_burst = NULL; 2905 eth_dev->tx_pkt_burst = NULL; 2906 eth_dev->tx_pkt_prepare = NULL; 2907 rte_free(eth_dev->process_private); 2908 eth_dev->process_private = NULL; 2909 2910 return ret; 2911 } 2912 2913 static int 2914 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev) 2915 { 2916 struct hns3_adapter *hns = eth_dev->data->dev_private; 2917 struct hns3_hw *hw = &hns->hw; 2918 2919 PMD_INIT_FUNC_TRACE(); 2920 2921 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2922 rte_free(eth_dev->process_private); 2923 eth_dev->process_private = NULL; 2924 return 0; 2925 } 2926 2927 if (hw->adapter_state < HNS3_NIC_CLOSING) 2928 hns3vf_dev_close(eth_dev); 2929 2930 hw->adapter_state = HNS3_NIC_REMOVED; 2931 return 0; 2932 } 2933 2934 static int 2935 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2936 struct rte_pci_device *pci_dev) 2937 { 2938 return rte_eth_dev_pci_generic_probe(pci_dev, 2939 sizeof(struct hns3_adapter), 2940 hns3vf_dev_init); 2941 } 2942 2943 static int 2944 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev) 2945 { 2946 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit); 2947 } 2948 2949 static const struct rte_pci_id pci_id_hns3vf_map[] = { 2950 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) }, 2951 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) }, 2952 { .vendor_id = 0, }, /* sentinel */ 2953 }; 2954 2955 static struct rte_pci_driver rte_hns3vf_pmd = { 2956 .id_table = pci_id_hns3vf_map, 2957 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2958 .probe = eth_hns3vf_pci_probe, 2959 .remove = eth_hns3vf_pci_remove, 2960 }; 2961 2962 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); 2963 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); 2964 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); 2965