1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <linux/pci_regs.h> 6 #include <rte_alarm.h> 7 #include <ethdev_pci.h> 8 #include <rte_io.h> 9 #include <rte_pci.h> 10 #include <rte_vfio.h> 11 12 #include "hns3_ethdev.h" 13 #include "hns3_logs.h" 14 #include "hns3_rxtx.h" 15 #include "hns3_regs.h" 16 #include "hns3_intr.h" 17 #include "hns3_dcb.h" 18 #include "hns3_mp.h" 19 20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */ 21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */ 22 23 #define HNS3VF_RESET_WAIT_MS 20 24 #define HNS3VF_RESET_WAIT_CNT 2000 25 26 /* Reset related Registers */ 27 #define HNS3_GLOBAL_RESET_BIT 0 28 #define HNS3_CORE_RESET_BIT 1 29 #define HNS3_IMP_RESET_BIT 2 30 #define HNS3_FUN_RST_ING_B 0 31 32 enum hns3vf_evt_cause { 33 HNS3VF_VECTOR0_EVENT_RST, 34 HNS3VF_VECTOR0_EVENT_MBX, 35 HNS3VF_VECTOR0_EVENT_OTHER, 36 }; 37 38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw, 39 uint64_t *levels); 40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev); 42 43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 44 struct rte_ether_addr *mac_addr); 45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 46 struct rte_ether_addr *mac_addr); 47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, 48 __rte_unused int wait_to_complete); 49 50 /* set PCI bus mastering */ 51 static int 52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) 53 { 54 uint16_t reg; 55 int ret; 56 57 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); 58 if (ret < 0) { 59 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 60 PCI_COMMAND); 61 return ret; 62 } 63 64 if (op) 65 /* set the master bit */ 66 reg |= PCI_COMMAND_MASTER; 67 else 68 reg &= ~(PCI_COMMAND_MASTER); 69 70 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); 71 } 72 73 /** 74 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list 75 * @cap: the capability 76 * 77 * Return the address of the given capability within the PCI capability list. 78 */ 79 static int 80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) 81 { 82 #define MAX_PCIE_CAPABILITY 48 83 uint16_t status; 84 uint8_t pos; 85 uint8_t id; 86 int ttl; 87 int ret; 88 89 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); 90 if (ret < 0) { 91 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS); 92 return 0; 93 } 94 95 if (!(status & PCI_STATUS_CAP_LIST)) 96 return 0; 97 98 ttl = MAX_PCIE_CAPABILITY; 99 ret = rte_pci_read_config(device, &pos, sizeof(pos), 100 PCI_CAPABILITY_LIST); 101 if (ret < 0) { 102 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 103 PCI_CAPABILITY_LIST); 104 return 0; 105 } 106 107 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { 108 ret = rte_pci_read_config(device, &id, sizeof(id), 109 (pos + PCI_CAP_LIST_ID)); 110 if (ret < 0) { 111 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 112 (pos + PCI_CAP_LIST_ID)); 113 break; 114 } 115 116 if (id == 0xFF) 117 break; 118 119 if (id == cap) 120 return (int)pos; 121 122 ret = rte_pci_read_config(device, &pos, sizeof(pos), 123 (pos + PCI_CAP_LIST_NEXT)); 124 if (ret < 0) { 125 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 126 (pos + PCI_CAP_LIST_NEXT)); 127 break; 128 } 129 } 130 return 0; 131 } 132 133 static int 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op) 135 { 136 uint16_t control; 137 int pos; 138 int ret; 139 140 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); 141 if (pos) { 142 ret = rte_pci_read_config(device, &control, sizeof(control), 143 (pos + PCI_MSIX_FLAGS)); 144 if (ret < 0) { 145 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 146 (pos + PCI_MSIX_FLAGS)); 147 return -ENXIO; 148 } 149 150 if (op) 151 control |= PCI_MSIX_FLAGS_ENABLE; 152 else 153 control &= ~PCI_MSIX_FLAGS_ENABLE; 154 ret = rte_pci_write_config(device, &control, sizeof(control), 155 (pos + PCI_MSIX_FLAGS)); 156 if (ret < 0) { 157 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x", 158 (pos + PCI_MSIX_FLAGS)); 159 } 160 return 0; 161 } 162 return -ENXIO; 163 } 164 165 static int 166 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 167 { 168 /* mac address was checked by upper level interface */ 169 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 170 int ret; 171 172 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 173 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes, 174 RTE_ETHER_ADDR_LEN, false, NULL, 0); 175 if (ret) { 176 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 177 mac_addr); 178 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 179 mac_str, ret); 180 } 181 return ret; 182 } 183 184 static int 185 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 186 { 187 /* mac address was checked by upper level interface */ 188 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 189 int ret; 190 191 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 192 HNS3_MBX_MAC_VLAN_UC_REMOVE, 193 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, 194 false, NULL, 0); 195 if (ret) { 196 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 197 mac_addr); 198 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 199 mac_str, ret); 200 } 201 return ret; 202 } 203 204 static int 205 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 206 { 207 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 208 struct rte_ether_addr *addr; 209 int ret; 210 int i; 211 212 for (i = 0; i < hw->mc_addrs_num; i++) { 213 addr = &hw->mc_addrs[i]; 214 /* Check if there are duplicate addresses */ 215 if (rte_is_same_ether_addr(addr, mac_addr)) { 216 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 217 addr); 218 hns3_err(hw, "failed to add mc mac addr, same addrs" 219 "(%s) is added by the set_mc_mac_addr_list " 220 "API", mac_str); 221 return -EINVAL; 222 } 223 } 224 225 ret = hns3vf_add_mc_mac_addr(hw, mac_addr); 226 if (ret) { 227 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 228 mac_addr); 229 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 230 mac_str, ret); 231 } 232 return ret; 233 } 234 235 static int 236 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 237 __rte_unused uint32_t idx, 238 __rte_unused uint32_t pool) 239 { 240 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 241 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 242 int ret; 243 244 rte_spinlock_lock(&hw->lock); 245 246 /* 247 * In hns3 network engine adding UC and MC mac address with different 248 * commands with firmware. We need to determine whether the input 249 * address is a UC or a MC address to call different commands. 250 * By the way, it is recommended calling the API function named 251 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 252 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 253 * may affect the specifications of UC mac addresses. 254 */ 255 if (rte_is_multicast_ether_addr(mac_addr)) 256 ret = hns3vf_add_mc_addr_common(hw, mac_addr); 257 else 258 ret = hns3vf_add_uc_mac_addr(hw, mac_addr); 259 260 rte_spinlock_unlock(&hw->lock); 261 if (ret) { 262 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 263 mac_addr); 264 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 265 ret); 266 } 267 268 return ret; 269 } 270 271 static void 272 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 273 { 274 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 275 /* index will be checked by upper level rte interface */ 276 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 277 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 278 int ret; 279 280 rte_spinlock_lock(&hw->lock); 281 282 if (rte_is_multicast_ether_addr(mac_addr)) 283 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr); 284 else 285 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr); 286 287 rte_spinlock_unlock(&hw->lock); 288 if (ret) { 289 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 290 mac_addr); 291 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", 292 mac_str, ret); 293 } 294 } 295 296 static int 297 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev, 298 struct rte_ether_addr *mac_addr) 299 { 300 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2) 301 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 302 struct rte_ether_addr *old_addr; 303 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */ 304 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 305 int ret; 306 307 /* 308 * It has been guaranteed that input parameter named mac_addr is valid 309 * address in the rte layer of DPDK framework. 310 */ 311 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 312 rte_spinlock_lock(&hw->lock); 313 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN); 314 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes, 315 RTE_ETHER_ADDR_LEN); 316 317 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 318 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes, 319 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0); 320 if (ret) { 321 /* 322 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev 323 * driver. When user has configured a MAC address for VF device 324 * by "ip link set ..." command based on the PF device, the hns3 325 * PF kernel ethdev driver does not allow VF driver to request 326 * reconfiguring a different default MAC address, and return 327 * -EPREM to VF driver through mailbox. 328 */ 329 if (ret == -EPERM) { 330 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 331 old_addr); 332 hns3_warn(hw, "Has permanet mac addr(%s) for vf", 333 mac_str); 334 } else { 335 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 336 mac_addr); 337 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", 338 mac_str, ret); 339 } 340 } 341 342 rte_ether_addr_copy(mac_addr, 343 (struct rte_ether_addr *)hw->mac.mac_addr); 344 rte_spinlock_unlock(&hw->lock); 345 346 return ret; 347 } 348 349 static int 350 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del) 351 { 352 struct hns3_hw *hw = &hns->hw; 353 struct rte_ether_addr *addr; 354 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 355 int err = 0; 356 int ret; 357 int i; 358 359 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) { 360 addr = &hw->data->mac_addrs[i]; 361 if (rte_is_zero_ether_addr(addr)) 362 continue; 363 if (rte_is_multicast_ether_addr(addr)) 364 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) : 365 hns3vf_add_mc_mac_addr(hw, addr); 366 else 367 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) : 368 hns3vf_add_uc_mac_addr(hw, addr); 369 370 if (ret) { 371 err = ret; 372 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 373 addr); 374 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 375 "ret = %d.", del ? "remove" : "restore", 376 mac_str, i, ret); 377 } 378 } 379 return err; 380 } 381 382 static int 383 hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 384 struct rte_ether_addr *mac_addr) 385 { 386 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 387 int ret; 388 389 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 390 HNS3_MBX_MAC_VLAN_MC_ADD, 391 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 392 NULL, 0); 393 if (ret) { 394 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 395 mac_addr); 396 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d", 397 mac_str, ret); 398 } 399 400 return ret; 401 } 402 403 static int 404 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 405 struct rte_ether_addr *mac_addr) 406 { 407 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 408 int ret; 409 410 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 411 HNS3_MBX_MAC_VLAN_MC_REMOVE, 412 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 413 NULL, 0); 414 if (ret) { 415 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 416 mac_addr); 417 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d", 418 mac_str, ret); 419 } 420 421 return ret; 422 } 423 424 static int 425 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw, 426 struct rte_ether_addr *mc_addr_set, 427 uint32_t nb_mc_addr) 428 { 429 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 430 struct rte_ether_addr *addr; 431 uint32_t i; 432 uint32_t j; 433 434 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 435 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 436 "invalid. valid range: 0~%d", 437 nb_mc_addr, HNS3_MC_MACADDR_NUM); 438 return -EINVAL; 439 } 440 441 /* Check if input mac addresses are valid */ 442 for (i = 0; i < nb_mc_addr; i++) { 443 addr = &mc_addr_set[i]; 444 if (!rte_is_multicast_ether_addr(addr)) { 445 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 446 addr); 447 hns3_err(hw, 448 "failed to set mc mac addr, addr(%s) invalid.", 449 mac_str); 450 return -EINVAL; 451 } 452 453 /* Check if there are duplicate addresses */ 454 for (j = i + 1; j < nb_mc_addr; j++) { 455 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 456 hns3_ether_format_addr(mac_str, 457 RTE_ETHER_ADDR_FMT_SIZE, 458 addr); 459 hns3_err(hw, "failed to set mc mac addr, " 460 "addrs invalid. two same addrs(%s).", 461 mac_str); 462 return -EINVAL; 463 } 464 } 465 466 /* 467 * Check if there are duplicate addresses between mac_addrs 468 * and mc_addr_set 469 */ 470 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) { 471 if (rte_is_same_ether_addr(addr, 472 &hw->data->mac_addrs[j])) { 473 hns3_ether_format_addr(mac_str, 474 RTE_ETHER_ADDR_FMT_SIZE, 475 addr); 476 hns3_err(hw, "failed to set mc mac addr, " 477 "addrs invalid. addrs(%s) has already " 478 "configured in mac_addr add API", 479 mac_str); 480 return -EINVAL; 481 } 482 } 483 } 484 485 return 0; 486 } 487 488 static int 489 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev, 490 struct rte_ether_addr *mc_addr_set, 491 uint32_t nb_mc_addr) 492 { 493 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 494 struct rte_ether_addr *addr; 495 int cur_addr_num; 496 int set_addr_num; 497 int num; 498 int ret; 499 int i; 500 501 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 502 if (ret) 503 return ret; 504 505 rte_spinlock_lock(&hw->lock); 506 cur_addr_num = hw->mc_addrs_num; 507 for (i = 0; i < cur_addr_num; i++) { 508 num = cur_addr_num - i - 1; 509 addr = &hw->mc_addrs[num]; 510 ret = hns3vf_remove_mc_mac_addr(hw, addr); 511 if (ret) { 512 rte_spinlock_unlock(&hw->lock); 513 return ret; 514 } 515 516 hw->mc_addrs_num--; 517 } 518 519 set_addr_num = (int)nb_mc_addr; 520 for (i = 0; i < set_addr_num; i++) { 521 addr = &mc_addr_set[i]; 522 ret = hns3vf_add_mc_mac_addr(hw, addr); 523 if (ret) { 524 rte_spinlock_unlock(&hw->lock); 525 return ret; 526 } 527 528 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]); 529 hw->mc_addrs_num++; 530 } 531 rte_spinlock_unlock(&hw->lock); 532 533 return 0; 534 } 535 536 static int 537 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 538 { 539 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 540 struct hns3_hw *hw = &hns->hw; 541 struct rte_ether_addr *addr; 542 int err = 0; 543 int ret; 544 int i; 545 546 for (i = 0; i < hw->mc_addrs_num; i++) { 547 addr = &hw->mc_addrs[i]; 548 if (!rte_is_multicast_ether_addr(addr)) 549 continue; 550 if (del) 551 ret = hns3vf_remove_mc_mac_addr(hw, addr); 552 else 553 ret = hns3vf_add_mc_mac_addr(hw, addr); 554 if (ret) { 555 err = ret; 556 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 557 addr); 558 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d", 559 del ? "Remove" : "Restore", mac_str, ret); 560 } 561 } 562 return err; 563 } 564 565 static int 566 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc, 567 bool en_uc_pmc, bool en_mc_pmc) 568 { 569 struct hns3_mbx_vf_to_pf_cmd *req; 570 struct hns3_cmd_desc desc; 571 int ret; 572 573 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data; 574 575 /* 576 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver, 577 * so there are some features for promiscuous/allmulticast mode in hns3 578 * VF PMD driver as below: 579 * 1. The promiscuous/allmulticast mode can be configured successfully 580 * only based on the trusted VF device. If based on the non trusted 581 * VF device, configuring promiscuous/allmulticast mode will fail. 582 * The hns3 VF device can be confiruged as trusted device by hns3 PF 583 * kernel ethdev driver on the host by the following command: 584 * "ip link set <eth num> vf <vf id> turst on" 585 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD 586 * driver can receive the ingress and outgoing traffic. In the words, 587 * all the ingress packets, all the packets sent from the PF and 588 * other VFs on the same physical port. 589 * 3. Note: Because of the hardware constraints, By default vlan filter 590 * is enabled and couldn't be turned off based on VF device, so vlan 591 * filter is still effective even in promiscuous mode. If upper 592 * applications don't call rte_eth_dev_vlan_filter API function to 593 * set vlan based on VF device, hns3 VF PMD driver will can't receive 594 * the packets with vlan tag in promiscuoue mode. 595 */ 596 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false); 597 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE; 598 req->msg[1] = en_bc_pmc ? 1 : 0; 599 req->msg[2] = en_uc_pmc ? 1 : 0; 600 req->msg[3] = en_mc_pmc ? 1 : 0; 601 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0; 602 603 ret = hns3_cmd_send(hw, &desc, 1); 604 if (ret) 605 hns3_err(hw, "Set promisc mode fail, ret = %d", ret); 606 607 return ret; 608 } 609 610 static int 611 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev) 612 { 613 struct hns3_adapter *hns = dev->data->dev_private; 614 struct hns3_hw *hw = &hns->hw; 615 int ret; 616 617 ret = hns3vf_set_promisc_mode(hw, true, true, true); 618 if (ret) 619 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d", 620 ret); 621 return ret; 622 } 623 624 static int 625 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev) 626 { 627 bool allmulti = dev->data->all_multicast ? true : false; 628 struct hns3_adapter *hns = dev->data->dev_private; 629 struct hns3_hw *hw = &hns->hw; 630 int ret; 631 632 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti); 633 if (ret) 634 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d", 635 ret); 636 return ret; 637 } 638 639 static int 640 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev) 641 { 642 struct hns3_adapter *hns = dev->data->dev_private; 643 struct hns3_hw *hw = &hns->hw; 644 int ret; 645 646 if (dev->data->promiscuous) 647 return 0; 648 649 ret = hns3vf_set_promisc_mode(hw, true, false, true); 650 if (ret) 651 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d", 652 ret); 653 return ret; 654 } 655 656 static int 657 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev) 658 { 659 struct hns3_adapter *hns = dev->data->dev_private; 660 struct hns3_hw *hw = &hns->hw; 661 int ret; 662 663 if (dev->data->promiscuous) 664 return 0; 665 666 ret = hns3vf_set_promisc_mode(hw, true, false, false); 667 if (ret) 668 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d", 669 ret); 670 return ret; 671 } 672 673 static int 674 hns3vf_restore_promisc(struct hns3_adapter *hns) 675 { 676 struct hns3_hw *hw = &hns->hw; 677 bool allmulti = hw->data->all_multicast ? true : false; 678 679 if (hw->data->promiscuous) 680 return hns3vf_set_promisc_mode(hw, true, true, true); 681 682 return hns3vf_set_promisc_mode(hw, true, false, allmulti); 683 } 684 685 static int 686 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, 687 bool mmap, enum hns3_ring_type queue_type, 688 uint16_t queue_id) 689 { 690 struct hns3_vf_bind_vector_msg bind_msg; 691 const char *op_str; 692 uint16_t code; 693 int ret; 694 695 memset(&bind_msg, 0, sizeof(bind_msg)); 696 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR : 697 HNS3_MBX_UNMAP_RING_TO_VECTOR; 698 bind_msg.vector_id = vector_id; 699 700 if (queue_type == HNS3_RING_TYPE_RX) 701 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX; 702 else 703 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX; 704 705 bind_msg.param[0].ring_type = queue_type; 706 bind_msg.ring_num = 1; 707 bind_msg.param[0].tqp_index = queue_id; 708 op_str = mmap ? "Map" : "Unmap"; 709 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg, 710 sizeof(bind_msg), false, NULL, 0); 711 if (ret) 712 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.", 713 op_str, queue_id, bind_msg.vector_id, ret); 714 715 return ret; 716 } 717 718 static int 719 hns3vf_init_ring_with_vector(struct hns3_hw *hw) 720 { 721 uint16_t vec; 722 int ret; 723 int i; 724 725 /* 726 * In hns3 network engine, vector 0 is always the misc interrupt of this 727 * function, vector 1~N can be used respectively for the queues of the 728 * function. Tx and Rx queues with the same number share the interrupt 729 * vector. In the initialization clearing the all hardware mapping 730 * relationship configurations between queues and interrupt vectors is 731 * needed, so some error caused by the residual configurations, such as 732 * the unexpected Tx interrupt, can be avoid. 733 */ 734 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 735 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 736 vec = vec - 1; /* the last interrupt is reserved */ 737 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 738 for (i = 0; i < hw->intr_tqps_num; i++) { 739 /* 740 * Set gap limiter/rate limiter/quanity limiter algorithm 741 * configuration for interrupt coalesce of queue's interrupt. 742 */ 743 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 744 HNS3_TQP_INTR_GL_DEFAULT); 745 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 746 HNS3_TQP_INTR_GL_DEFAULT); 747 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 748 /* 749 * QL(quantity limiter) is not used currently, just set 0 to 750 * close it. 751 */ 752 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 753 754 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 755 HNS3_RING_TYPE_TX, i); 756 if (ret) { 757 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with " 758 "vector: %u, ret=%d", i, vec, ret); 759 return ret; 760 } 761 762 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 763 HNS3_RING_TYPE_RX, i); 764 if (ret) { 765 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with " 766 "vector: %u, ret=%d", i, vec, ret); 767 return ret; 768 } 769 } 770 771 return 0; 772 } 773 774 static int 775 hns3vf_dev_configure(struct rte_eth_dev *dev) 776 { 777 struct hns3_adapter *hns = dev->data->dev_private; 778 struct hns3_hw *hw = &hns->hw; 779 struct rte_eth_conf *conf = &dev->data->dev_conf; 780 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 781 uint16_t nb_rx_q = dev->data->nb_rx_queues; 782 uint16_t nb_tx_q = dev->data->nb_tx_queues; 783 struct rte_eth_rss_conf rss_conf; 784 uint32_t max_rx_pkt_len; 785 uint16_t mtu; 786 bool gro_en; 787 int ret; 788 789 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 790 791 /* 792 * Some versions of hardware network engine does not support 793 * individually enable/disable/reset the Tx or Rx queue. These devices 794 * must enable/disable/reset Tx and Rx queues at the same time. When the 795 * numbers of Tx queues allocated by upper applications are not equal to 796 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 797 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 798 * work as usual. But these fake queues are imperceptible, and can not 799 * be used by upper applications. 800 */ 801 if (!hns3_dev_indep_txrx_supported(hw)) { 802 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 803 if (ret) { 804 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", 805 ret); 806 return ret; 807 } 808 } 809 810 hw->adapter_state = HNS3_NIC_CONFIGURING; 811 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 812 hns3_err(hw, "setting link speed/duplex not supported"); 813 ret = -EINVAL; 814 goto cfg_err; 815 } 816 817 /* When RSS is not configured, redirect the packet queue 0 */ 818 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 819 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 820 hw->rss_dis_flag = false; 821 rss_conf = conf->rx_adv_conf.rss_conf; 822 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 823 if (ret) 824 goto cfg_err; 825 } 826 827 /* 828 * If jumbo frames are enabled, MTU needs to be refreshed 829 * according to the maximum RX packet length. 830 */ 831 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 832 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len; 833 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN || 834 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) { 835 hns3_err(hw, "maximum Rx packet length must be greater " 836 "than %u and less than %u when jumbo frame enabled.", 837 (uint16_t)HNS3_DEFAULT_FRAME_LEN, 838 (uint16_t)HNS3_MAX_FRAME_LEN); 839 ret = -EINVAL; 840 goto cfg_err; 841 } 842 843 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len); 844 ret = hns3vf_dev_mtu_set(dev, mtu); 845 if (ret) 846 goto cfg_err; 847 dev->data->mtu = mtu; 848 } 849 850 ret = hns3vf_dev_configure_vlan(dev); 851 if (ret) 852 goto cfg_err; 853 854 /* config hardware GRO */ 855 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 856 ret = hns3_config_gro(hw, gro_en); 857 if (ret) 858 goto cfg_err; 859 860 hns3_init_rx_ptype_tble(dev); 861 862 hw->adapter_state = HNS3_NIC_CONFIGURED; 863 return 0; 864 865 cfg_err: 866 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 867 hw->adapter_state = HNS3_NIC_INITIALIZED; 868 869 return ret; 870 } 871 872 static int 873 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu) 874 { 875 int ret; 876 877 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu, 878 sizeof(mtu), true, NULL, 0); 879 if (ret) 880 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret); 881 882 return ret; 883 } 884 885 static int 886 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 887 { 888 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 889 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 890 int ret; 891 892 /* 893 * The hns3 PF/VF devices on the same port share the hardware MTU 894 * configuration. Currently, we send mailbox to inform hns3 PF kernel 895 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD 896 * driver, there is no need to stop the port for hns3 VF device, and the 897 * MTU value issued by hns3 VF PMD driver must be less than or equal to 898 * PF's MTU. 899 */ 900 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 901 hns3_err(hw, "Failed to set mtu during resetting"); 902 return -EIO; 903 } 904 905 /* 906 * when Rx of scattered packets is off, we have some possibility of 907 * using vector Rx process function or simple Rx functions in hns3 PMD 908 * driver. If the input MTU is increased and the maximum length of 909 * received packets is greater than the length of a buffer for Rx 910 * packet, the hardware network engine needs to use multiple BDs and 911 * buffers to store these packets. This will cause problems when still 912 * using vector Rx process function or simple Rx function to receiving 913 * packets. So, when Rx of scattered packets is off and device is 914 * started, it is not permitted to increase MTU so that the maximum 915 * length of Rx packets is greater than Rx buffer length. 916 */ 917 if (dev->data->dev_started && !dev->data->scattered_rx && 918 frame_size > hw->rx_buf_len) { 919 hns3_err(hw, "failed to set mtu because current is " 920 "not scattered rx mode"); 921 return -EOPNOTSUPP; 922 } 923 924 rte_spinlock_lock(&hw->lock); 925 ret = hns3vf_config_mtu(hw, mtu); 926 if (ret) { 927 rte_spinlock_unlock(&hw->lock); 928 return ret; 929 } 930 if (mtu > RTE_ETHER_MTU) 931 dev->data->dev_conf.rxmode.offloads |= 932 DEV_RX_OFFLOAD_JUMBO_FRAME; 933 else 934 dev->data->dev_conf.rxmode.offloads &= 935 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 936 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 937 rte_spinlock_unlock(&hw->lock); 938 939 return 0; 940 } 941 942 static int 943 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 944 { 945 struct hns3_adapter *hns = eth_dev->data->dev_private; 946 struct hns3_hw *hw = &hns->hw; 947 uint16_t q_num = hw->tqps_num; 948 949 /* 950 * In interrupt mode, 'max_rx_queues' is set based on the number of 951 * MSI-X interrupt resources of the hardware. 952 */ 953 if (hw->data->dev_conf.intr_conf.rxq == 1) 954 q_num = hw->intr_tqps_num; 955 956 info->max_rx_queues = q_num; 957 info->max_tx_queues = hw->tqps_num; 958 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 959 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 960 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; 961 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 962 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 963 964 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 965 DEV_RX_OFFLOAD_UDP_CKSUM | 966 DEV_RX_OFFLOAD_TCP_CKSUM | 967 DEV_RX_OFFLOAD_SCTP_CKSUM | 968 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 969 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 970 DEV_RX_OFFLOAD_SCATTER | 971 DEV_RX_OFFLOAD_VLAN_STRIP | 972 DEV_RX_OFFLOAD_VLAN_FILTER | 973 DEV_RX_OFFLOAD_JUMBO_FRAME | 974 DEV_RX_OFFLOAD_RSS_HASH | 975 DEV_RX_OFFLOAD_TCP_LRO); 976 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 977 DEV_TX_OFFLOAD_IPV4_CKSUM | 978 DEV_TX_OFFLOAD_TCP_CKSUM | 979 DEV_TX_OFFLOAD_UDP_CKSUM | 980 DEV_TX_OFFLOAD_SCTP_CKSUM | 981 DEV_TX_OFFLOAD_MULTI_SEGS | 982 DEV_TX_OFFLOAD_TCP_TSO | 983 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 984 DEV_TX_OFFLOAD_GRE_TNL_TSO | 985 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 986 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 987 hns3_txvlan_cap_get(hw)); 988 989 if (hns3_dev_outer_udp_cksum_supported(hw)) 990 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 991 992 if (hns3_dev_indep_txrx_supported(hw)) 993 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 994 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 995 996 info->rx_desc_lim = (struct rte_eth_desc_lim) { 997 .nb_max = HNS3_MAX_RING_DESC, 998 .nb_min = HNS3_MIN_RING_DESC, 999 .nb_align = HNS3_ALIGN_RING_DESC, 1000 }; 1001 1002 info->tx_desc_lim = (struct rte_eth_desc_lim) { 1003 .nb_max = HNS3_MAX_RING_DESC, 1004 .nb_min = HNS3_MIN_RING_DESC, 1005 .nb_align = HNS3_ALIGN_RING_DESC, 1006 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 1007 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 1008 }; 1009 1010 info->default_rxconf = (struct rte_eth_rxconf) { 1011 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 1012 /* 1013 * If there are no available Rx buffer descriptors, incoming 1014 * packets are always dropped by hardware based on hns3 network 1015 * engine. 1016 */ 1017 .rx_drop_en = 1, 1018 .offloads = 0, 1019 }; 1020 info->default_txconf = (struct rte_eth_txconf) { 1021 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 1022 .offloads = 0, 1023 }; 1024 1025 info->reta_size = hw->rss_ind_tbl_size; 1026 info->hash_key_size = HNS3_RSS_KEY_SIZE; 1027 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 1028 1029 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 1030 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 1031 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 1032 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 1033 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1034 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1035 1036 return 0; 1037 } 1038 1039 static void 1040 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr) 1041 { 1042 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 1043 } 1044 1045 static void 1046 hns3vf_disable_irq0(struct hns3_hw *hw) 1047 { 1048 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 1049 } 1050 1051 static void 1052 hns3vf_enable_irq0(struct hns3_hw *hw) 1053 { 1054 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 1055 } 1056 1057 static enum hns3vf_evt_cause 1058 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 1059 { 1060 struct hns3_hw *hw = &hns->hw; 1061 enum hns3vf_evt_cause ret; 1062 uint32_t cmdq_stat_reg; 1063 uint32_t rst_ing_reg; 1064 uint32_t val; 1065 1066 /* Fetch the events from their corresponding regs */ 1067 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG); 1068 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1069 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING); 1070 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg); 1071 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 1072 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 1073 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 1074 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT); 1075 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B); 1076 if (clearval) { 1077 hw->reset.stats.global_cnt++; 1078 hns3_warn(hw, "Global reset detected, clear reset status"); 1079 } else { 1080 hns3_schedule_delayed_reset(hns); 1081 hns3_warn(hw, "Global reset detected, don't clear reset status"); 1082 } 1083 1084 ret = HNS3VF_VECTOR0_EVENT_RST; 1085 goto out; 1086 } 1087 1088 /* Check for vector0 mailbox(=CMDQ RX) event source */ 1089 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1090 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 1091 ret = HNS3VF_VECTOR0_EVENT_MBX; 1092 goto out; 1093 } 1094 1095 val = 0; 1096 ret = HNS3VF_VECTOR0_EVENT_OTHER; 1097 out: 1098 if (clearval) 1099 *clearval = val; 1100 return ret; 1101 } 1102 1103 static void 1104 hns3vf_interrupt_handler(void *param) 1105 { 1106 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1107 struct hns3_adapter *hns = dev->data->dev_private; 1108 struct hns3_hw *hw = &hns->hw; 1109 enum hns3vf_evt_cause event_cause; 1110 uint32_t clearval; 1111 1112 /* Disable interrupt */ 1113 hns3vf_disable_irq0(hw); 1114 1115 /* Read out interrupt causes */ 1116 event_cause = hns3vf_check_event_cause(hns, &clearval); 1117 1118 switch (event_cause) { 1119 case HNS3VF_VECTOR0_EVENT_RST: 1120 hns3_schedule_reset(hns); 1121 break; 1122 case HNS3VF_VECTOR0_EVENT_MBX: 1123 hns3_dev_handle_mbx_msg(hw); 1124 break; 1125 default: 1126 break; 1127 } 1128 1129 /* Clear interrupt causes */ 1130 hns3vf_clear_event_cause(hw, clearval); 1131 1132 /* Enable interrupt */ 1133 hns3vf_enable_irq0(hw); 1134 } 1135 1136 static void 1137 hns3vf_set_default_dev_specifications(struct hns3_hw *hw) 1138 { 1139 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 1140 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 1141 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 1142 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 1143 } 1144 1145 static void 1146 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 1147 { 1148 struct hns3_dev_specs_0_cmd *req0; 1149 1150 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 1151 1152 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 1153 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 1154 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 1155 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 1156 } 1157 1158 static int 1159 hns3vf_check_dev_specifications(struct hns3_hw *hw) 1160 { 1161 if (hw->rss_ind_tbl_size == 0 || 1162 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 1163 hns3_warn(hw, "the size of hash lookup table configured (%u)" 1164 " exceeds the maximum(%u)", hw->rss_ind_tbl_size, 1165 HNS3_RSS_IND_TBL_SIZE_MAX); 1166 return -EINVAL; 1167 } 1168 1169 return 0; 1170 } 1171 1172 static int 1173 hns3vf_query_dev_specifications(struct hns3_hw *hw) 1174 { 1175 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 1176 int ret; 1177 int i; 1178 1179 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1180 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 1181 true); 1182 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1183 } 1184 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 1185 1186 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 1187 if (ret) 1188 return ret; 1189 1190 hns3vf_parse_dev_specifications(hw, desc); 1191 1192 return hns3vf_check_dev_specifications(hw); 1193 } 1194 1195 void 1196 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported) 1197 { 1198 uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED : 1199 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED; 1200 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN; 1201 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw); 1202 1203 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN) 1204 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0, 1205 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); 1206 } 1207 1208 static void 1209 hns3vf_get_push_lsc_cap(struct hns3_hw *hw) 1210 { 1211 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500 1212 1213 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1214 int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS; 1215 uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED; 1216 uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN; 1217 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw); 1218 1219 __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN, 1220 __ATOMIC_RELEASE); 1221 1222 (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false, 1223 NULL, 0); 1224 1225 while (remain_ms > 0) { 1226 rte_delay_ms(HNS3_POLL_RESPONE_MS); 1227 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) != 1228 HNS3_PF_PUSH_LSC_CAP_UNKNOWN) 1229 break; 1230 remain_ms--; 1231 } 1232 1233 /* 1234 * When exit above loop, the pf_push_lsc_cap could be one of the three 1235 * state: unknown (means pf not ack), not_supported, supported. 1236 * Here config it as 'not_supported' when it's 'unknown' state. 1237 */ 1238 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0, 1239 __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); 1240 1241 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) == 1242 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) { 1243 hns3_info(hw, "detect PF support push link status change!"); 1244 } else { 1245 /* 1246 * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver 1247 * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared 1248 * the RTE_ETH_DEV_INTR_LSC capability. 1249 */ 1250 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 1251 } 1252 } 1253 1254 static int 1255 hns3vf_get_capability(struct hns3_hw *hw) 1256 { 1257 struct rte_pci_device *pci_dev; 1258 struct rte_eth_dev *eth_dev; 1259 uint8_t revision; 1260 int ret; 1261 1262 eth_dev = &rte_eth_devices[hw->data->port_id]; 1263 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1264 1265 /* Get PCI revision id */ 1266 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 1267 HNS3_PCI_REVISION_ID); 1268 if (ret != HNS3_PCI_REVISION_ID_LEN) { 1269 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 1270 ret); 1271 return -EIO; 1272 } 1273 hw->revision = revision; 1274 1275 if (revision < PCI_REVISION_ID_HIP09_A) { 1276 hns3vf_set_default_dev_specifications(hw); 1277 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 1278 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 1279 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 1280 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 1281 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 1282 hw->rss_info.ipv6_sctp_offload_supported = false; 1283 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; 1284 return 0; 1285 } 1286 1287 ret = hns3vf_query_dev_specifications(hw); 1288 if (ret) { 1289 PMD_INIT_LOG(ERR, 1290 "failed to query dev specifications, ret = %d", 1291 ret); 1292 return ret; 1293 } 1294 1295 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 1296 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 1297 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 1298 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 1299 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 1300 hw->rss_info.ipv6_sctp_offload_supported = true; 1301 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; 1302 1303 return 0; 1304 } 1305 1306 static int 1307 hns3vf_check_tqp_info(struct hns3_hw *hw) 1308 { 1309 if (hw->tqps_num == 0) { 1310 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF."); 1311 return -EINVAL; 1312 } 1313 1314 if (hw->rss_size_max == 0) { 1315 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF."); 1316 return -EINVAL; 1317 } 1318 1319 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num); 1320 1321 return 0; 1322 } 1323 1324 static int 1325 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw) 1326 { 1327 uint8_t resp_msg; 1328 int ret; 1329 1330 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, 1331 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0, 1332 true, &resp_msg, sizeof(resp_msg)); 1333 if (ret) { 1334 if (ret == -ETIME) { 1335 /* 1336 * Getting current port based VLAN state from PF driver 1337 * will not affect VF driver's basic function. Because 1338 * the VF driver relies on hns3 PF kernel ether driver, 1339 * to avoid introducing compatibility issues with older 1340 * version of PF driver, no failure will be returned 1341 * when the return value is ETIME. This return value has 1342 * the following scenarios: 1343 * 1) Firmware didn't return the results in time 1344 * 2) the result return by firmware is timeout 1345 * 3) the older version of kernel side PF driver does 1346 * not support this mailbox message. 1347 * For scenarios 1 and 2, it is most likely that a 1348 * hardware error has occurred, or a hardware reset has 1349 * occurred. In this case, these errors will be caught 1350 * by other functions. 1351 */ 1352 PMD_INIT_LOG(WARNING, 1353 "failed to get PVID state for timeout, maybe " 1354 "kernel side PF driver doesn't support this " 1355 "mailbox message, or firmware didn't respond."); 1356 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE; 1357 } else { 1358 PMD_INIT_LOG(ERR, "failed to get port based VLAN state," 1359 " ret = %d", ret); 1360 return ret; 1361 } 1362 } 1363 hw->port_base_vlan_cfg.state = resp_msg ? 1364 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 1365 return 0; 1366 } 1367 1368 static int 1369 hns3vf_get_queue_info(struct hns3_hw *hw) 1370 { 1371 #define HNS3VF_TQPS_RSS_INFO_LEN 6 1372 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN]; 1373 int ret; 1374 1375 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true, 1376 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN); 1377 if (ret) { 1378 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret); 1379 return ret; 1380 } 1381 1382 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t)); 1383 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t)); 1384 1385 return hns3vf_check_tqp_info(hw); 1386 } 1387 1388 static int 1389 hns3vf_get_queue_depth(struct hns3_hw *hw) 1390 { 1391 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4 1392 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN]; 1393 int ret; 1394 1395 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true, 1396 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN); 1397 if (ret) { 1398 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d", 1399 ret); 1400 return ret; 1401 } 1402 1403 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t)); 1404 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t)); 1405 1406 return 0; 1407 } 1408 1409 static int 1410 hns3vf_get_tc_info(struct hns3_hw *hw) 1411 { 1412 uint8_t resp_msg; 1413 int ret; 1414 uint32_t i; 1415 1416 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0, 1417 true, &resp_msg, sizeof(resp_msg)); 1418 if (ret) { 1419 hns3_err(hw, "VF request to get TC info from PF failed %d", 1420 ret); 1421 return ret; 1422 } 1423 1424 hw->hw_tc_map = resp_msg; 1425 1426 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 1427 if (hw->hw_tc_map & BIT(i)) 1428 hw->num_tc++; 1429 } 1430 1431 return 0; 1432 } 1433 1434 static int 1435 hns3vf_get_host_mac_addr(struct hns3_hw *hw) 1436 { 1437 uint8_t host_mac[RTE_ETHER_ADDR_LEN]; 1438 int ret; 1439 1440 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0, 1441 true, host_mac, RTE_ETHER_ADDR_LEN); 1442 if (ret) { 1443 hns3_err(hw, "Failed to get mac addr from PF: %d", ret); 1444 return ret; 1445 } 1446 1447 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN); 1448 1449 return 0; 1450 } 1451 1452 static int 1453 hns3vf_get_configuration(struct hns3_hw *hw) 1454 { 1455 int ret; 1456 1457 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE; 1458 hw->rss_dis_flag = false; 1459 1460 /* Get device capability */ 1461 ret = hns3vf_get_capability(hw); 1462 if (ret) { 1463 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 1464 return ret; 1465 } 1466 1467 hns3vf_get_push_lsc_cap(hw); 1468 1469 /* Get queue configuration from PF */ 1470 ret = hns3vf_get_queue_info(hw); 1471 if (ret) 1472 return ret; 1473 1474 /* Get queue depth info from PF */ 1475 ret = hns3vf_get_queue_depth(hw); 1476 if (ret) 1477 return ret; 1478 1479 /* Get user defined VF MAC addr from PF */ 1480 ret = hns3vf_get_host_mac_addr(hw); 1481 if (ret) 1482 return ret; 1483 1484 ret = hns3vf_get_port_base_vlan_filter_state(hw); 1485 if (ret) 1486 return ret; 1487 1488 /* Get tc configuration from PF */ 1489 return hns3vf_get_tc_info(hw); 1490 } 1491 1492 static int 1493 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q, 1494 uint16_t nb_tx_q) 1495 { 1496 struct hns3_hw *hw = &hns->hw; 1497 1498 if (nb_rx_q < hw->num_tc) { 1499 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).", 1500 nb_rx_q, hw->num_tc); 1501 return -EINVAL; 1502 } 1503 1504 if (nb_tx_q < hw->num_tc) { 1505 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).", 1506 nb_tx_q, hw->num_tc); 1507 return -EINVAL; 1508 } 1509 1510 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q); 1511 } 1512 1513 static void 1514 hns3vf_request_link_info(struct hns3_hw *hw) 1515 { 1516 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw); 1517 bool send_req; 1518 int ret; 1519 1520 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 1521 return; 1522 1523 send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED || 1524 vf->req_link_info_cnt > 0; 1525 if (!send_req) 1526 return; 1527 1528 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false, 1529 NULL, 0); 1530 if (ret) { 1531 hns3_err(hw, "failed to fetch link status, ret = %d", ret); 1532 return; 1533 } 1534 1535 if (vf->req_link_info_cnt > 0) 1536 vf->req_link_info_cnt--; 1537 } 1538 1539 void 1540 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1541 uint32_t link_speed, uint8_t link_duplex) 1542 { 1543 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1544 struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw); 1545 struct hns3_mac *mac = &hw->mac; 1546 int ret; 1547 1548 /* 1549 * PF kernel driver may push link status when VF driver is in resetting, 1550 * driver will stop polling job in this case, after resetting done 1551 * driver will start polling job again. 1552 * When polling job started, driver will get initial link status by 1553 * sending request to PF kernel driver, then could update link status by 1554 * process PF kernel driver's link status mailbox message. 1555 */ 1556 if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED)) 1557 return; 1558 1559 if (hw->adapter_state != HNS3_NIC_STARTED) 1560 return; 1561 1562 mac->link_status = link_status; 1563 mac->link_speed = link_speed; 1564 mac->link_duplex = link_duplex; 1565 ret = hns3vf_dev_link_update(dev, 0); 1566 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0) 1567 hns3_start_report_lse(dev); 1568 } 1569 1570 static int 1571 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 1572 { 1573 #define HNS3VF_VLAN_MBX_MSG_LEN 5 1574 struct hns3_hw *hw = &hns->hw; 1575 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN]; 1576 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN); 1577 uint8_t is_kill = on ? 0 : 1; 1578 1579 msg_data[0] = is_kill; 1580 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1581 memcpy(&msg_data[3], &proto, sizeof(proto)); 1582 1583 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER, 1584 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL, 1585 0); 1586 } 1587 1588 static int 1589 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1590 { 1591 struct hns3_adapter *hns = dev->data->dev_private; 1592 struct hns3_hw *hw = &hns->hw; 1593 int ret; 1594 1595 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 1596 hns3_err(hw, 1597 "vf set vlan id failed during resetting, vlan_id =%u", 1598 vlan_id); 1599 return -EIO; 1600 } 1601 rte_spinlock_lock(&hw->lock); 1602 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1603 rte_spinlock_unlock(&hw->lock); 1604 if (ret) 1605 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d", 1606 vlan_id, ret); 1607 1608 return ret; 1609 } 1610 1611 static int 1612 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable) 1613 { 1614 uint8_t msg_data; 1615 int ret; 1616 1617 msg_data = enable ? 1 : 0; 1618 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG, 1619 &msg_data, sizeof(msg_data), false, NULL, 0); 1620 if (ret) 1621 hns3_err(hw, "vf enable strip failed, ret =%d", ret); 1622 1623 return ret; 1624 } 1625 1626 static int 1627 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1628 { 1629 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1630 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1631 unsigned int tmp_mask; 1632 int ret = 0; 1633 1634 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 1635 hns3_err(hw, "vf set vlan offload failed during resetting, " 1636 "mask = 0x%x", mask); 1637 return -EIO; 1638 } 1639 1640 tmp_mask = (unsigned int)mask; 1641 /* Vlan stripping setting */ 1642 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 1643 rte_spinlock_lock(&hw->lock); 1644 /* Enable or disable VLAN stripping */ 1645 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1646 ret = hns3vf_en_hw_strip_rxvtag(hw, true); 1647 else 1648 ret = hns3vf_en_hw_strip_rxvtag(hw, false); 1649 rte_spinlock_unlock(&hw->lock); 1650 } 1651 1652 return ret; 1653 } 1654 1655 static int 1656 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on) 1657 { 1658 struct rte_vlan_filter_conf *vfc; 1659 struct hns3_hw *hw = &hns->hw; 1660 uint16_t vlan_id; 1661 uint64_t vbit; 1662 uint64_t ids; 1663 int ret = 0; 1664 uint32_t i; 1665 1666 vfc = &hw->data->vlan_filter_conf; 1667 for (i = 0; i < RTE_DIM(vfc->ids); i++) { 1668 if (vfc->ids[i] == 0) 1669 continue; 1670 ids = vfc->ids[i]; 1671 while (ids) { 1672 /* 1673 * 64 means the num bits of ids, one bit corresponds to 1674 * one vlan id 1675 */ 1676 vlan_id = 64 * i; 1677 /* count trailing zeroes */ 1678 vbit = ~ids & (ids - 1); 1679 /* clear least significant bit set */ 1680 ids ^= (ids ^ (ids - 1)) ^ vbit; 1681 for (; vbit;) { 1682 vbit >>= 1; 1683 vlan_id++; 1684 } 1685 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1686 if (ret) { 1687 hns3_err(hw, 1688 "VF handle vlan table failed, ret =%d, on = %d", 1689 ret, on); 1690 return ret; 1691 } 1692 } 1693 } 1694 1695 return ret; 1696 } 1697 1698 static int 1699 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns) 1700 { 1701 return hns3vf_handle_all_vlan_table(hns, 0); 1702 } 1703 1704 static int 1705 hns3vf_restore_vlan_conf(struct hns3_adapter *hns) 1706 { 1707 struct hns3_hw *hw = &hns->hw; 1708 struct rte_eth_conf *dev_conf; 1709 bool en; 1710 int ret; 1711 1712 dev_conf = &hw->data->dev_conf; 1713 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true 1714 : false; 1715 ret = hns3vf_en_hw_strip_rxvtag(hw, en); 1716 if (ret) 1717 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en, 1718 ret); 1719 return ret; 1720 } 1721 1722 static int 1723 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev) 1724 { 1725 struct hns3_adapter *hns = dev->data->dev_private; 1726 struct rte_eth_dev_data *data = dev->data; 1727 struct hns3_hw *hw = &hns->hw; 1728 int ret; 1729 1730 if (data->dev_conf.txmode.hw_vlan_reject_tagged || 1731 data->dev_conf.txmode.hw_vlan_reject_untagged || 1732 data->dev_conf.txmode.hw_vlan_insert_pvid) { 1733 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged " 1734 "or hw_vlan_insert_pvid is not support!"); 1735 } 1736 1737 /* Apply vlan offload setting */ 1738 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK); 1739 if (ret) 1740 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret); 1741 1742 return ret; 1743 } 1744 1745 static int 1746 hns3vf_set_alive(struct hns3_hw *hw, bool alive) 1747 { 1748 uint8_t msg_data; 1749 1750 msg_data = alive ? 1 : 0; 1751 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data, 1752 sizeof(msg_data), false, NULL, 0); 1753 } 1754 1755 static void 1756 hns3vf_keep_alive_handler(void *param) 1757 { 1758 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1759 struct hns3_adapter *hns = eth_dev->data->dev_private; 1760 struct hns3_hw *hw = &hns->hw; 1761 int ret; 1762 1763 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0, 1764 false, NULL, 0); 1765 if (ret) 1766 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)", 1767 ret); 1768 1769 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 1770 eth_dev); 1771 } 1772 1773 static void 1774 hns3vf_service_handler(void *param) 1775 { 1776 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1777 struct hns3_adapter *hns = eth_dev->data->dev_private; 1778 struct hns3_hw *hw = &hns->hw; 1779 1780 /* 1781 * The query link status and reset processing are executed in the 1782 * interrupt thread. When the IMP reset occurs, IMP will not respond, 1783 * and the query operation will timeout after 30ms. In the case of 1784 * multiple PF/VFs, each query failure timeout causes the IMP reset 1785 * interrupt to fail to respond within 100ms. 1786 * Before querying the link status, check whether there is a reset 1787 * pending, and if so, abandon the query. 1788 */ 1789 if (!hns3vf_is_reset_pending(hns)) 1790 hns3vf_request_link_info(hw); 1791 else 1792 hns3_warn(hw, "Cancel the query when reset is pending"); 1793 1794 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, 1795 eth_dev); 1796 } 1797 1798 static void 1799 hns3vf_start_poll_job(struct rte_eth_dev *dev) 1800 { 1801 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT 3 1802 1803 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1804 1805 if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED) 1806 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT; 1807 1808 __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED); 1809 1810 hns3vf_service_handler(dev); 1811 } 1812 1813 static void 1814 hns3vf_stop_poll_job(struct rte_eth_dev *dev) 1815 { 1816 struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1817 1818 rte_eal_alarm_cancel(hns3vf_service_handler, dev); 1819 1820 __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED); 1821 } 1822 1823 static int 1824 hns3_query_vf_resource(struct hns3_hw *hw) 1825 { 1826 struct hns3_vf_res_cmd *req; 1827 struct hns3_cmd_desc desc; 1828 uint16_t num_msi; 1829 int ret; 1830 1831 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true); 1832 ret = hns3_cmd_send(hw, &desc, 1); 1833 if (ret) { 1834 hns3_err(hw, "query vf resource failed, ret = %d", ret); 1835 return ret; 1836 } 1837 1838 req = (struct hns3_vf_res_cmd *)desc.data; 1839 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number), 1840 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S); 1841 if (num_msi < HNS3_MIN_VECTOR_NUM) { 1842 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)", 1843 num_msi, HNS3_MIN_VECTOR_NUM); 1844 return -EINVAL; 1845 } 1846 1847 hw->num_msi = num_msi; 1848 1849 return 0; 1850 } 1851 1852 static int 1853 hns3vf_init_hardware(struct hns3_adapter *hns) 1854 { 1855 struct hns3_hw *hw = &hns->hw; 1856 uint16_t mtu = hw->data->mtu; 1857 int ret; 1858 1859 ret = hns3vf_set_promisc_mode(hw, true, false, false); 1860 if (ret) 1861 return ret; 1862 1863 ret = hns3vf_config_mtu(hw, mtu); 1864 if (ret) 1865 goto err_init_hardware; 1866 1867 ret = hns3vf_vlan_filter_configure(hns, 0, 1); 1868 if (ret) { 1869 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret); 1870 goto err_init_hardware; 1871 } 1872 1873 ret = hns3_config_gro(hw, false); 1874 if (ret) { 1875 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 1876 goto err_init_hardware; 1877 } 1878 1879 /* 1880 * In the initialization clearing the all hardware mapping relationship 1881 * configurations between queues and interrupt vectors is needed, so 1882 * some error caused by the residual configurations, such as the 1883 * unexpected interrupt, can be avoid. 1884 */ 1885 ret = hns3vf_init_ring_with_vector(hw); 1886 if (ret) { 1887 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 1888 goto err_init_hardware; 1889 } 1890 1891 ret = hns3vf_set_alive(hw, true); 1892 if (ret) { 1893 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret); 1894 goto err_init_hardware; 1895 } 1896 1897 return 0; 1898 1899 err_init_hardware: 1900 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1901 return ret; 1902 } 1903 1904 static int 1905 hns3vf_clear_vport_list(struct hns3_hw *hw) 1906 { 1907 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL, 1908 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false, 1909 NULL, 0); 1910 } 1911 1912 static int 1913 hns3vf_init_vf(struct rte_eth_dev *eth_dev) 1914 { 1915 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1916 struct hns3_adapter *hns = eth_dev->data->dev_private; 1917 struct hns3_hw *hw = &hns->hw; 1918 int ret; 1919 1920 PMD_INIT_FUNC_TRACE(); 1921 1922 /* Get hardware io base address from pcie BAR2 IO space */ 1923 hw->io_base = pci_dev->mem_resource[2].addr; 1924 1925 /* Firmware command queue initialize */ 1926 ret = hns3_cmd_init_queue(hw); 1927 if (ret) { 1928 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 1929 goto err_cmd_init_queue; 1930 } 1931 1932 /* Firmware command initialize */ 1933 ret = hns3_cmd_init(hw); 1934 if (ret) { 1935 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 1936 goto err_cmd_init; 1937 } 1938 1939 /* Get VF resource */ 1940 ret = hns3_query_vf_resource(hw); 1941 if (ret) 1942 goto err_cmd_init; 1943 1944 rte_spinlock_init(&hw->mbx_resp.lock); 1945 1946 hns3vf_clear_event_cause(hw, 0); 1947 1948 ret = rte_intr_callback_register(&pci_dev->intr_handle, 1949 hns3vf_interrupt_handler, eth_dev); 1950 if (ret) { 1951 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 1952 goto err_intr_callback_register; 1953 } 1954 1955 /* Enable interrupt */ 1956 rte_intr_enable(&pci_dev->intr_handle); 1957 hns3vf_enable_irq0(hw); 1958 1959 /* Get configuration from PF */ 1960 ret = hns3vf_get_configuration(hw); 1961 if (ret) { 1962 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 1963 goto err_get_config; 1964 } 1965 1966 ret = hns3_tqp_stats_init(hw); 1967 if (ret) 1968 goto err_get_config; 1969 1970 /* Hardware statistics of imissed registers cleared. */ 1971 ret = hns3_update_imissed_stats(hw, true); 1972 if (ret) { 1973 hns3_err(hw, "clear imissed stats failed, ret = %d", ret); 1974 goto err_set_tc_queue; 1975 } 1976 1977 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); 1978 if (ret) { 1979 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); 1980 goto err_set_tc_queue; 1981 } 1982 1983 ret = hns3vf_clear_vport_list(hw); 1984 if (ret) { 1985 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret); 1986 goto err_set_tc_queue; 1987 } 1988 1989 ret = hns3vf_init_hardware(hns); 1990 if (ret) 1991 goto err_set_tc_queue; 1992 1993 hns3_rss_set_default_args(hw); 1994 1995 return 0; 1996 1997 err_set_tc_queue: 1998 hns3_tqp_stats_uninit(hw); 1999 2000 err_get_config: 2001 hns3vf_disable_irq0(hw); 2002 rte_intr_disable(&pci_dev->intr_handle); 2003 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 2004 eth_dev); 2005 err_intr_callback_register: 2006 err_cmd_init: 2007 hns3_cmd_uninit(hw); 2008 hns3_cmd_destroy_queue(hw); 2009 err_cmd_init_queue: 2010 hw->io_base = NULL; 2011 2012 return ret; 2013 } 2014 2015 static void 2016 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev) 2017 { 2018 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2019 struct hns3_adapter *hns = eth_dev->data->dev_private; 2020 struct hns3_hw *hw = &hns->hw; 2021 2022 PMD_INIT_FUNC_TRACE(); 2023 2024 hns3_rss_uninit(hns); 2025 (void)hns3_config_gro(hw, false); 2026 (void)hns3vf_set_alive(hw, false); 2027 (void)hns3vf_set_promisc_mode(hw, false, false, false); 2028 hns3_tqp_stats_uninit(hw); 2029 hns3vf_disable_irq0(hw); 2030 rte_intr_disable(&pci_dev->intr_handle); 2031 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 2032 eth_dev); 2033 hns3_cmd_uninit(hw); 2034 hns3_cmd_destroy_queue(hw); 2035 hw->io_base = NULL; 2036 } 2037 2038 static int 2039 hns3vf_do_stop(struct hns3_adapter *hns) 2040 { 2041 struct hns3_hw *hw = &hns->hw; 2042 int ret; 2043 2044 hw->mac.link_status = ETH_LINK_DOWN; 2045 2046 /* 2047 * The "hns3vf_do_stop" function will also be called by .stop_service to 2048 * prepare reset. At the time of global or IMP reset, the command cannot 2049 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 2050 * accessed during the reset process. So the mbuf can not be released 2051 * during reset and is required to be released after the reset is 2052 * completed. 2053 */ 2054 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 2055 hns3_dev_release_mbufs(hns); 2056 2057 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 2058 hns3vf_configure_mac_addr(hns, true); 2059 ret = hns3_reset_all_tqps(hns); 2060 if (ret) { 2061 hns3_err(hw, "failed to reset all queues ret = %d", 2062 ret); 2063 return ret; 2064 } 2065 } 2066 return 0; 2067 } 2068 2069 static void 2070 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev) 2071 { 2072 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2073 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2074 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2075 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 2076 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 2077 uint16_t q_id; 2078 2079 if (dev->data->dev_conf.intr_conf.rxq == 0) 2080 return; 2081 2082 /* unmap the ring with vector */ 2083 if (rte_intr_allow_others(intr_handle)) { 2084 vec = RTE_INTR_VEC_RXTX_OFFSET; 2085 base = RTE_INTR_VEC_RXTX_OFFSET; 2086 } 2087 if (rte_intr_dp_is_en(intr_handle)) { 2088 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2089 (void)hns3vf_bind_ring_with_vector(hw, vec, false, 2090 HNS3_RING_TYPE_RX, 2091 q_id); 2092 if (vec < base + intr_handle->nb_efd - 1) 2093 vec++; 2094 } 2095 } 2096 /* Clean datapath event and queue/vec mapping */ 2097 rte_intr_efd_disable(intr_handle); 2098 if (intr_handle->intr_vec) { 2099 rte_free(intr_handle->intr_vec); 2100 intr_handle->intr_vec = NULL; 2101 } 2102 } 2103 2104 static int 2105 hns3vf_dev_stop(struct rte_eth_dev *dev) 2106 { 2107 struct hns3_adapter *hns = dev->data->dev_private; 2108 struct hns3_hw *hw = &hns->hw; 2109 2110 PMD_INIT_FUNC_TRACE(); 2111 dev->data->dev_started = 0; 2112 2113 hw->adapter_state = HNS3_NIC_STOPPING; 2114 hns3_set_rxtx_function(dev); 2115 rte_wmb(); 2116 /* Disable datapath on secondary process. */ 2117 hns3_mp_req_stop_rxtx(dev); 2118 /* Prevent crashes when queues are still in use. */ 2119 rte_delay_ms(hw->tqps_num); 2120 2121 rte_spinlock_lock(&hw->lock); 2122 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 2123 hns3_stop_tqps(hw); 2124 hns3vf_do_stop(hns); 2125 hns3vf_unmap_rx_interrupt(dev); 2126 hw->adapter_state = HNS3_NIC_CONFIGURED; 2127 } 2128 hns3_rx_scattered_reset(dev); 2129 hns3vf_stop_poll_job(dev); 2130 hns3_stop_report_lse(dev); 2131 rte_spinlock_unlock(&hw->lock); 2132 2133 return 0; 2134 } 2135 2136 static int 2137 hns3vf_dev_close(struct rte_eth_dev *eth_dev) 2138 { 2139 struct hns3_adapter *hns = eth_dev->data->dev_private; 2140 struct hns3_hw *hw = &hns->hw; 2141 int ret = 0; 2142 2143 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2144 rte_free(eth_dev->process_private); 2145 eth_dev->process_private = NULL; 2146 return 0; 2147 } 2148 2149 if (hw->adapter_state == HNS3_NIC_STARTED) 2150 ret = hns3vf_dev_stop(eth_dev); 2151 2152 hw->adapter_state = HNS3_NIC_CLOSING; 2153 hns3_reset_abort(hns); 2154 hw->adapter_state = HNS3_NIC_CLOSED; 2155 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev); 2156 hns3vf_configure_all_mc_mac_addr(hns, true); 2157 hns3vf_remove_all_vlan_table(hns); 2158 hns3vf_uninit_vf(eth_dev); 2159 hns3_free_all_queues(eth_dev); 2160 rte_free(hw->reset.wait_data); 2161 rte_free(eth_dev->process_private); 2162 eth_dev->process_private = NULL; 2163 hns3_mp_uninit_primary(); 2164 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 2165 2166 return ret; 2167 } 2168 2169 static int 2170 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2171 size_t fw_size) 2172 { 2173 struct hns3_adapter *hns = eth_dev->data->dev_private; 2174 struct hns3_hw *hw = &hns->hw; 2175 uint32_t version = hw->fw_version; 2176 int ret; 2177 2178 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2179 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2180 HNS3_FW_VERSION_BYTE3_S), 2181 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2182 HNS3_FW_VERSION_BYTE2_S), 2183 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2184 HNS3_FW_VERSION_BYTE1_S), 2185 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2186 HNS3_FW_VERSION_BYTE0_S)); 2187 if (ret < 0) 2188 return -EINVAL; 2189 2190 ret += 1; /* add the size of '\0' */ 2191 if (fw_size < (size_t)ret) 2192 return ret; 2193 else 2194 return 0; 2195 } 2196 2197 static int 2198 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, 2199 __rte_unused int wait_to_complete) 2200 { 2201 struct hns3_adapter *hns = eth_dev->data->dev_private; 2202 struct hns3_hw *hw = &hns->hw; 2203 struct hns3_mac *mac = &hw->mac; 2204 struct rte_eth_link new_link; 2205 2206 memset(&new_link, 0, sizeof(new_link)); 2207 switch (mac->link_speed) { 2208 case ETH_SPEED_NUM_10M: 2209 case ETH_SPEED_NUM_100M: 2210 case ETH_SPEED_NUM_1G: 2211 case ETH_SPEED_NUM_10G: 2212 case ETH_SPEED_NUM_25G: 2213 case ETH_SPEED_NUM_40G: 2214 case ETH_SPEED_NUM_50G: 2215 case ETH_SPEED_NUM_100G: 2216 case ETH_SPEED_NUM_200G: 2217 new_link.link_speed = mac->link_speed; 2218 break; 2219 default: 2220 if (mac->link_status) 2221 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN; 2222 else 2223 new_link.link_speed = ETH_SPEED_NUM_NONE; 2224 break; 2225 } 2226 2227 new_link.link_duplex = mac->link_duplex; 2228 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2229 new_link.link_autoneg = 2230 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2231 2232 return rte_eth_linkstatus_set(eth_dev, &new_link); 2233 } 2234 2235 static int 2236 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue) 2237 { 2238 struct hns3_hw *hw = &hns->hw; 2239 uint16_t nb_rx_q = hw->data->nb_rx_queues; 2240 uint16_t nb_tx_q = hw->data->nb_tx_queues; 2241 int ret; 2242 2243 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q); 2244 if (ret) 2245 return ret; 2246 2247 hns3_enable_rxd_adv_layout(hw); 2248 2249 ret = hns3_init_queues(hns, reset_queue); 2250 if (ret) 2251 hns3_err(hw, "failed to init queues, ret = %d.", ret); 2252 2253 return ret; 2254 } 2255 2256 static int 2257 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) 2258 { 2259 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2260 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2261 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2262 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 2263 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 2264 uint32_t intr_vector; 2265 uint16_t q_id; 2266 int ret; 2267 2268 /* 2269 * hns3 needs a separate interrupt to be used as event interrupt which 2270 * could not be shared with task queue pair, so KERNEL drivers need 2271 * support multiple interrupt vectors. 2272 */ 2273 if (dev->data->dev_conf.intr_conf.rxq == 0 || 2274 !rte_intr_cap_multiple(intr_handle)) 2275 return 0; 2276 2277 rte_intr_disable(intr_handle); 2278 intr_vector = hw->used_rx_queues; 2279 /* It creates event fd for each intr vector when MSIX is used */ 2280 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2281 return -EINVAL; 2282 2283 if (intr_handle->intr_vec == NULL) { 2284 intr_handle->intr_vec = 2285 rte_zmalloc("intr_vec", 2286 hw->used_rx_queues * sizeof(int), 0); 2287 if (intr_handle->intr_vec == NULL) { 2288 hns3_err(hw, "Failed to allocate %u rx_queues" 2289 " intr_vec", hw->used_rx_queues); 2290 ret = -ENOMEM; 2291 goto vf_alloc_intr_vec_error; 2292 } 2293 } 2294 2295 if (rte_intr_allow_others(intr_handle)) { 2296 vec = RTE_INTR_VEC_RXTX_OFFSET; 2297 base = RTE_INTR_VEC_RXTX_OFFSET; 2298 } 2299 2300 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2301 ret = hns3vf_bind_ring_with_vector(hw, vec, true, 2302 HNS3_RING_TYPE_RX, q_id); 2303 if (ret) 2304 goto vf_bind_vector_error; 2305 intr_handle->intr_vec[q_id] = vec; 2306 /* 2307 * If there are not enough efds (e.g. not enough interrupt), 2308 * remaining queues will be bond to the last interrupt. 2309 */ 2310 if (vec < base + intr_handle->nb_efd - 1) 2311 vec++; 2312 } 2313 rte_intr_enable(intr_handle); 2314 return 0; 2315 2316 vf_bind_vector_error: 2317 free(intr_handle->intr_vec); 2318 intr_handle->intr_vec = NULL; 2319 vf_alloc_intr_vec_error: 2320 rte_intr_efd_disable(intr_handle); 2321 return ret; 2322 } 2323 2324 static int 2325 hns3vf_restore_rx_interrupt(struct hns3_hw *hw) 2326 { 2327 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 2328 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2329 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2330 uint16_t q_id; 2331 int ret; 2332 2333 if (dev->data->dev_conf.intr_conf.rxq == 0) 2334 return 0; 2335 2336 if (rte_intr_dp_is_en(intr_handle)) { 2337 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2338 ret = hns3vf_bind_ring_with_vector(hw, 2339 intr_handle->intr_vec[q_id], true, 2340 HNS3_RING_TYPE_RX, q_id); 2341 if (ret) 2342 return ret; 2343 } 2344 } 2345 2346 return 0; 2347 } 2348 2349 static void 2350 hns3vf_restore_filter(struct rte_eth_dev *dev) 2351 { 2352 hns3_restore_rss_filter(dev); 2353 } 2354 2355 static int 2356 hns3vf_dev_start(struct rte_eth_dev *dev) 2357 { 2358 struct hns3_adapter *hns = dev->data->dev_private; 2359 struct hns3_hw *hw = &hns->hw; 2360 int ret; 2361 2362 PMD_INIT_FUNC_TRACE(); 2363 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 2364 return -EBUSY; 2365 2366 rte_spinlock_lock(&hw->lock); 2367 hw->adapter_state = HNS3_NIC_STARTING; 2368 ret = hns3vf_do_start(hns, true); 2369 if (ret) { 2370 hw->adapter_state = HNS3_NIC_CONFIGURED; 2371 rte_spinlock_unlock(&hw->lock); 2372 return ret; 2373 } 2374 ret = hns3vf_map_rx_interrupt(dev); 2375 if (ret) 2376 goto map_rx_inter_err; 2377 2378 /* 2379 * There are three register used to control the status of a TQP 2380 * (contains a pair of Tx queue and Rx queue) in the new version network 2381 * engine. One is used to control the enabling of Tx queue, the other is 2382 * used to control the enabling of Rx queue, and the last is the master 2383 * switch used to control the enabling of the tqp. The Tx register and 2384 * TQP register must be enabled at the same time to enable a Tx queue. 2385 * The same applies to the Rx queue. For the older network enginem, this 2386 * function only refresh the enabled flag, and it is used to update the 2387 * status of queue in the dpdk framework. 2388 */ 2389 ret = hns3_start_all_txqs(dev); 2390 if (ret) 2391 goto map_rx_inter_err; 2392 2393 ret = hns3_start_all_rxqs(dev); 2394 if (ret) 2395 goto start_all_rxqs_fail; 2396 2397 hw->adapter_state = HNS3_NIC_STARTED; 2398 rte_spinlock_unlock(&hw->lock); 2399 2400 hns3_rx_scattered_calc(dev); 2401 hns3_set_rxtx_function(dev); 2402 hns3_mp_req_start_rxtx(dev); 2403 2404 hns3vf_restore_filter(dev); 2405 2406 /* Enable interrupt of all rx queues before enabling queues */ 2407 hns3_dev_all_rx_queue_intr_enable(hw, true); 2408 hns3_start_tqps(hw); 2409 2410 if (dev->data->dev_conf.intr_conf.lsc != 0) 2411 hns3vf_dev_link_update(dev, 0); 2412 hns3vf_start_poll_job(dev); 2413 2414 return ret; 2415 2416 start_all_rxqs_fail: 2417 hns3_stop_all_txqs(dev); 2418 map_rx_inter_err: 2419 (void)hns3vf_do_stop(hns); 2420 hw->adapter_state = HNS3_NIC_CONFIGURED; 2421 rte_spinlock_unlock(&hw->lock); 2422 2423 return ret; 2424 } 2425 2426 static bool 2427 is_vf_reset_done(struct hns3_hw *hw) 2428 { 2429 #define HNS3_FUN_RST_ING_BITS \ 2430 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \ 2431 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \ 2432 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \ 2433 BIT(HNS3_VECTOR0_FUNCRESET_INT_B)) 2434 2435 uint32_t val; 2436 2437 if (hw->reset.level == HNS3_VF_RESET) { 2438 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 2439 if (val & HNS3_VF_RST_ING_BIT) 2440 return false; 2441 } else { 2442 val = hns3_read_dev(hw, HNS3_FUN_RST_ING); 2443 if (val & HNS3_FUN_RST_ING_BITS) 2444 return false; 2445 } 2446 return true; 2447 } 2448 2449 bool 2450 hns3vf_is_reset_pending(struct hns3_adapter *hns) 2451 { 2452 struct hns3_hw *hw = &hns->hw; 2453 enum hns3_reset_level reset; 2454 2455 /* 2456 * According to the protocol of PCIe, FLR to a PF device resets the PF 2457 * state as well as the SR-IOV extended capability including VF Enable 2458 * which means that VFs no longer exist. 2459 * 2460 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device 2461 * is in FLR stage, the register state of VF device is not reliable, 2462 * so register states detection can not be carried out. In this case, 2463 * we just ignore the register states and return false to indicate that 2464 * there are no other reset states that need to be processed by driver. 2465 */ 2466 if (hw->reset.level == HNS3_VF_FULL_RESET) 2467 return false; 2468 2469 /* Check the registers to confirm whether there is reset pending */ 2470 hns3vf_check_event_cause(hns, NULL); 2471 reset = hns3vf_get_reset_level(hw, &hw->reset.pending); 2472 if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET && 2473 hw->reset.level < reset) { 2474 hns3_warn(hw, "High level reset %d is pending", reset); 2475 return true; 2476 } 2477 return false; 2478 } 2479 2480 static int 2481 hns3vf_wait_hardware_ready(struct hns3_adapter *hns) 2482 { 2483 struct hns3_hw *hw = &hns->hw; 2484 struct hns3_wait_data *wait_data = hw->reset.wait_data; 2485 struct timeval tv; 2486 2487 if (wait_data->result == HNS3_WAIT_SUCCESS) { 2488 /* 2489 * After vf reset is ready, the PF may not have completed 2490 * the reset processing. The vf sending mbox to PF may fail 2491 * during the pf reset, so it is better to add extra delay. 2492 */ 2493 if (hw->reset.level == HNS3_VF_FUNC_RESET || 2494 hw->reset.level == HNS3_FLR_RESET) 2495 return 0; 2496 /* Reset retry process, no need to add extra delay. */ 2497 if (hw->reset.attempts) 2498 return 0; 2499 if (wait_data->check_completion == NULL) 2500 return 0; 2501 2502 wait_data->check_completion = NULL; 2503 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC; 2504 wait_data->count = 1; 2505 wait_data->result = HNS3_WAIT_REQUEST; 2506 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, 2507 wait_data); 2508 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); 2509 return -EAGAIN; 2510 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 2511 hns3_clock_gettime(&tv); 2512 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 2513 tv.tv_sec, tv.tv_usec); 2514 return -ETIME; 2515 } else if (wait_data->result == HNS3_WAIT_REQUEST) 2516 return -EAGAIN; 2517 2518 wait_data->hns = hns; 2519 wait_data->check_completion = is_vf_reset_done; 2520 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT * 2521 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms(); 2522 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC; 2523 wait_data->count = HNS3VF_RESET_WAIT_CNT; 2524 wait_data->result = HNS3_WAIT_REQUEST; 2525 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 2526 return -EAGAIN; 2527 } 2528 2529 static int 2530 hns3vf_prepare_reset(struct hns3_adapter *hns) 2531 { 2532 struct hns3_hw *hw = &hns->hw; 2533 int ret; 2534 2535 if (hw->reset.level == HNS3_VF_FUNC_RESET) { 2536 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL, 2537 0, true, NULL, 0); 2538 if (ret) 2539 return ret; 2540 } 2541 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 2542 2543 return 0; 2544 } 2545 2546 static int 2547 hns3vf_stop_service(struct hns3_adapter *hns) 2548 { 2549 struct hns3_hw *hw = &hns->hw; 2550 struct rte_eth_dev *eth_dev; 2551 2552 eth_dev = &rte_eth_devices[hw->data->port_id]; 2553 if (hw->adapter_state == HNS3_NIC_STARTED) { 2554 /* 2555 * Make sure call update link status before hns3vf_stop_poll_job 2556 * because update link status depend on polling job exist. 2557 */ 2558 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed, 2559 hw->mac.link_duplex); 2560 hns3vf_stop_poll_job(eth_dev); 2561 } 2562 hw->mac.link_status = ETH_LINK_DOWN; 2563 2564 hns3_set_rxtx_function(eth_dev); 2565 rte_wmb(); 2566 /* Disable datapath on secondary process. */ 2567 hns3_mp_req_stop_rxtx(eth_dev); 2568 rte_delay_ms(hw->tqps_num); 2569 2570 rte_spinlock_lock(&hw->lock); 2571 if (hw->adapter_state == HNS3_NIC_STARTED || 2572 hw->adapter_state == HNS3_NIC_STOPPING) { 2573 hns3_enable_all_queues(hw, false); 2574 hns3vf_do_stop(hns); 2575 hw->reset.mbuf_deferred_free = true; 2576 } else 2577 hw->reset.mbuf_deferred_free = false; 2578 2579 /* 2580 * It is cumbersome for hardware to pick-and-choose entries for deletion 2581 * from table space. Hence, for function reset software intervention is 2582 * required to delete the entries. 2583 */ 2584 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 2585 hns3vf_configure_all_mc_mac_addr(hns, true); 2586 rte_spinlock_unlock(&hw->lock); 2587 2588 return 0; 2589 } 2590 2591 static int 2592 hns3vf_start_service(struct hns3_adapter *hns) 2593 { 2594 struct hns3_hw *hw = &hns->hw; 2595 struct rte_eth_dev *eth_dev; 2596 2597 eth_dev = &rte_eth_devices[hw->data->port_id]; 2598 hns3_set_rxtx_function(eth_dev); 2599 hns3_mp_req_start_rxtx(eth_dev); 2600 if (hw->adapter_state == HNS3_NIC_STARTED) { 2601 hns3vf_start_poll_job(eth_dev); 2602 2603 /* Enable interrupt of all rx queues before enabling queues */ 2604 hns3_dev_all_rx_queue_intr_enable(hw, true); 2605 /* 2606 * Enable state of each rxq and txq will be recovered after 2607 * reset, so we need to restore them before enable all tqps; 2608 */ 2609 hns3_restore_tqp_enable_state(hw); 2610 /* 2611 * When finished the initialization, enable queues to receive 2612 * and transmit packets. 2613 */ 2614 hns3_enable_all_queues(hw, true); 2615 } 2616 2617 return 0; 2618 } 2619 2620 static int 2621 hns3vf_check_default_mac_change(struct hns3_hw *hw) 2622 { 2623 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2624 struct rte_ether_addr *hw_mac; 2625 int ret; 2626 2627 /* 2628 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2629 * on the host by "ip link set ..." command. If the hns3 PF kernel 2630 * ethdev driver sets the MAC address for VF device after the 2631 * initialization of the related VF device, the PF driver will notify 2632 * VF driver to reset VF device to make the new MAC address effective 2633 * immediately. The hns3 VF PMD driver should check whether the MAC 2634 * address has been changed by the PF kernel ethdev driver, if changed 2635 * VF driver should configure hardware using the new MAC address in the 2636 * recovering hardware configuration stage of the reset process. 2637 */ 2638 ret = hns3vf_get_host_mac_addr(hw); 2639 if (ret) 2640 return ret; 2641 2642 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr; 2643 ret = rte_is_zero_ether_addr(hw_mac); 2644 if (ret) { 2645 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac); 2646 } else { 2647 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac); 2648 if (!ret) { 2649 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]); 2650 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2651 &hw->data->mac_addrs[0]); 2652 hns3_warn(hw, "Default MAC address has been changed to:" 2653 " %s by the host PF kernel ethdev driver", 2654 mac_str); 2655 } 2656 } 2657 2658 return 0; 2659 } 2660 2661 static int 2662 hns3vf_restore_conf(struct hns3_adapter *hns) 2663 { 2664 struct hns3_hw *hw = &hns->hw; 2665 int ret; 2666 2667 ret = hns3vf_check_default_mac_change(hw); 2668 if (ret) 2669 return ret; 2670 2671 ret = hns3vf_configure_mac_addr(hns, false); 2672 if (ret) 2673 return ret; 2674 2675 ret = hns3vf_configure_all_mc_mac_addr(hns, false); 2676 if (ret) 2677 goto err_mc_mac; 2678 2679 ret = hns3vf_restore_promisc(hns); 2680 if (ret) 2681 goto err_vlan_table; 2682 2683 ret = hns3vf_restore_vlan_conf(hns); 2684 if (ret) 2685 goto err_vlan_table; 2686 2687 ret = hns3vf_get_port_base_vlan_filter_state(hw); 2688 if (ret) 2689 goto err_vlan_table; 2690 2691 ret = hns3vf_restore_rx_interrupt(hw); 2692 if (ret) 2693 goto err_vlan_table; 2694 2695 ret = hns3_restore_gro_conf(hw); 2696 if (ret) 2697 goto err_vlan_table; 2698 2699 if (hw->adapter_state == HNS3_NIC_STARTED) { 2700 ret = hns3vf_do_start(hns, false); 2701 if (ret) 2702 goto err_vlan_table; 2703 hns3_info(hw, "hns3vf dev restart successful!"); 2704 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 2705 hw->adapter_state = HNS3_NIC_CONFIGURED; 2706 return 0; 2707 2708 err_vlan_table: 2709 hns3vf_configure_all_mc_mac_addr(hns, true); 2710 err_mc_mac: 2711 hns3vf_configure_mac_addr(hns, true); 2712 return ret; 2713 } 2714 2715 static enum hns3_reset_level 2716 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels) 2717 { 2718 enum hns3_reset_level reset_level; 2719 2720 /* return the highest priority reset level amongst all */ 2721 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels)) 2722 reset_level = HNS3_VF_RESET; 2723 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels)) 2724 reset_level = HNS3_VF_FULL_RESET; 2725 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels)) 2726 reset_level = HNS3_VF_PF_FUNC_RESET; 2727 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels)) 2728 reset_level = HNS3_VF_FUNC_RESET; 2729 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 2730 reset_level = HNS3_FLR_RESET; 2731 else 2732 reset_level = HNS3_NONE_RESET; 2733 2734 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 2735 return HNS3_NONE_RESET; 2736 2737 return reset_level; 2738 } 2739 2740 static void 2741 hns3vf_reset_service(void *param) 2742 { 2743 struct hns3_adapter *hns = (struct hns3_adapter *)param; 2744 struct hns3_hw *hw = &hns->hw; 2745 enum hns3_reset_level reset_level; 2746 struct timeval tv_delta; 2747 struct timeval tv_start; 2748 struct timeval tv; 2749 uint64_t msec; 2750 2751 /* 2752 * The interrupt is not triggered within the delay time. 2753 * The interrupt may have been lost. It is necessary to handle 2754 * the interrupt to recover from the error. 2755 */ 2756 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2757 SCHEDULE_DEFERRED) { 2758 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 2759 __ATOMIC_RELAXED); 2760 hns3_err(hw, "Handling interrupts in delayed tasks"); 2761 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 2762 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2763 if (reset_level == HNS3_NONE_RESET) { 2764 hns3_err(hw, "No reset level is set, try global reset"); 2765 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 2766 } 2767 } 2768 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 2769 2770 /* 2771 * Hardware reset has been notified, we now have to poll & check if 2772 * hardware has actually completed the reset sequence. 2773 */ 2774 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2775 if (reset_level != HNS3_NONE_RESET) { 2776 hns3_clock_gettime(&tv_start); 2777 hns3_reset_process(hns, reset_level); 2778 hns3_clock_gettime(&tv); 2779 timersub(&tv, &tv_start, &tv_delta); 2780 msec = hns3_clock_calctime_ms(&tv_delta); 2781 if (msec > HNS3_RESET_PROCESS_MS) 2782 hns3_err(hw, "%d handle long time delta %" PRIu64 2783 " ms time=%ld.%.6ld", 2784 hw->reset.level, msec, tv.tv_sec, tv.tv_usec); 2785 } 2786 } 2787 2788 static int 2789 hns3vf_reinit_dev(struct hns3_adapter *hns) 2790 { 2791 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id]; 2792 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2793 struct hns3_hw *hw = &hns->hw; 2794 int ret; 2795 2796 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2797 rte_intr_disable(&pci_dev->intr_handle); 2798 ret = hns3vf_set_bus_master(pci_dev, true); 2799 if (ret < 0) { 2800 hns3_err(hw, "failed to set pci bus, ret = %d", ret); 2801 return ret; 2802 } 2803 } 2804 2805 /* Firmware command initialize */ 2806 ret = hns3_cmd_init(hw); 2807 if (ret) { 2808 hns3_err(hw, "Failed to init cmd: %d", ret); 2809 return ret; 2810 } 2811 2812 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2813 /* 2814 * UIO enables msix by writing the pcie configuration space 2815 * vfio_pci enables msix in rte_intr_enable. 2816 */ 2817 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO || 2818 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) { 2819 if (hns3vf_enable_msix(pci_dev, true)) 2820 hns3_err(hw, "Failed to enable msix"); 2821 } 2822 2823 rte_intr_enable(&pci_dev->intr_handle); 2824 } 2825 2826 ret = hns3_reset_all_tqps(hns); 2827 if (ret) { 2828 hns3_err(hw, "Failed to reset all queues: %d", ret); 2829 return ret; 2830 } 2831 2832 ret = hns3vf_init_hardware(hns); 2833 if (ret) { 2834 hns3_err(hw, "Failed to init hardware: %d", ret); 2835 return ret; 2836 } 2837 2838 return 0; 2839 } 2840 2841 static const struct eth_dev_ops hns3vf_eth_dev_ops = { 2842 .dev_configure = hns3vf_dev_configure, 2843 .dev_start = hns3vf_dev_start, 2844 .dev_stop = hns3vf_dev_stop, 2845 .dev_close = hns3vf_dev_close, 2846 .mtu_set = hns3vf_dev_mtu_set, 2847 .promiscuous_enable = hns3vf_dev_promiscuous_enable, 2848 .promiscuous_disable = hns3vf_dev_promiscuous_disable, 2849 .allmulticast_enable = hns3vf_dev_allmulticast_enable, 2850 .allmulticast_disable = hns3vf_dev_allmulticast_disable, 2851 .stats_get = hns3_stats_get, 2852 .stats_reset = hns3_stats_reset, 2853 .xstats_get = hns3_dev_xstats_get, 2854 .xstats_get_names = hns3_dev_xstats_get_names, 2855 .xstats_reset = hns3_dev_xstats_reset, 2856 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 2857 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 2858 .dev_infos_get = hns3vf_dev_infos_get, 2859 .fw_version_get = hns3vf_fw_version_get, 2860 .rx_queue_setup = hns3_rx_queue_setup, 2861 .tx_queue_setup = hns3_tx_queue_setup, 2862 .rx_queue_release = hns3_dev_rx_queue_release, 2863 .tx_queue_release = hns3_dev_tx_queue_release, 2864 .rx_queue_start = hns3_dev_rx_queue_start, 2865 .rx_queue_stop = hns3_dev_rx_queue_stop, 2866 .tx_queue_start = hns3_dev_tx_queue_start, 2867 .tx_queue_stop = hns3_dev_tx_queue_stop, 2868 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 2869 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 2870 .rxq_info_get = hns3_rxq_info_get, 2871 .txq_info_get = hns3_txq_info_get, 2872 .rx_burst_mode_get = hns3_rx_burst_mode_get, 2873 .tx_burst_mode_get = hns3_tx_burst_mode_get, 2874 .mac_addr_add = hns3vf_add_mac_addr, 2875 .mac_addr_remove = hns3vf_remove_mac_addr, 2876 .mac_addr_set = hns3vf_set_default_mac_addr, 2877 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list, 2878 .link_update = hns3vf_dev_link_update, 2879 .rss_hash_update = hns3_dev_rss_hash_update, 2880 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 2881 .reta_update = hns3_dev_rss_reta_update, 2882 .reta_query = hns3_dev_rss_reta_query, 2883 .flow_ops_get = hns3_dev_flow_ops_get, 2884 .vlan_filter_set = hns3vf_vlan_filter_set, 2885 .vlan_offload_set = hns3vf_vlan_offload_set, 2886 .get_reg = hns3_get_regs, 2887 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 2888 .tx_done_cleanup = hns3_tx_done_cleanup, 2889 }; 2890 2891 static const struct hns3_reset_ops hns3vf_reset_ops = { 2892 .reset_service = hns3vf_reset_service, 2893 .stop_service = hns3vf_stop_service, 2894 .prepare_reset = hns3vf_prepare_reset, 2895 .wait_hardware_ready = hns3vf_wait_hardware_ready, 2896 .reinit_dev = hns3vf_reinit_dev, 2897 .restore_conf = hns3vf_restore_conf, 2898 .start_service = hns3vf_start_service, 2899 }; 2900 2901 static int 2902 hns3vf_dev_init(struct rte_eth_dev *eth_dev) 2903 { 2904 struct hns3_adapter *hns = eth_dev->data->dev_private; 2905 struct hns3_hw *hw = &hns->hw; 2906 int ret; 2907 2908 PMD_INIT_FUNC_TRACE(); 2909 2910 eth_dev->process_private = (struct hns3_process_private *) 2911 rte_zmalloc_socket("hns3_filter_list", 2912 sizeof(struct hns3_process_private), 2913 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 2914 if (eth_dev->process_private == NULL) { 2915 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 2916 return -ENOMEM; 2917 } 2918 2919 hns3_flow_init(eth_dev); 2920 2921 hns3_set_rxtx_function(eth_dev); 2922 eth_dev->dev_ops = &hns3vf_eth_dev_ops; 2923 eth_dev->rx_queue_count = hns3_rx_queue_count; 2924 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2925 ret = hns3_mp_init_secondary(); 2926 if (ret) { 2927 PMD_INIT_LOG(ERR, "Failed to init for secondary " 2928 "process, ret = %d", ret); 2929 goto err_mp_init_secondary; 2930 } 2931 2932 hw->secondary_cnt++; 2933 return 0; 2934 } 2935 2936 ret = hns3_mp_init_primary(); 2937 if (ret) { 2938 PMD_INIT_LOG(ERR, 2939 "Failed to init for primary process, ret = %d", 2940 ret); 2941 goto err_mp_init_primary; 2942 } 2943 2944 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 2945 hns->is_vf = true; 2946 hw->data = eth_dev->data; 2947 hns3_parse_devargs(eth_dev); 2948 2949 ret = hns3_reset_init(hw); 2950 if (ret) 2951 goto err_init_reset; 2952 hw->reset.ops = &hns3vf_reset_ops; 2953 2954 ret = hns3vf_init_vf(eth_dev); 2955 if (ret) { 2956 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret); 2957 goto err_init_vf; 2958 } 2959 2960 /* Allocate memory for storing MAC addresses */ 2961 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac", 2962 sizeof(struct rte_ether_addr) * 2963 HNS3_VF_UC_MACADDR_NUM, 0); 2964 if (eth_dev->data->mac_addrs == NULL) { 2965 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 2966 "to store MAC addresses", 2967 sizeof(struct rte_ether_addr) * 2968 HNS3_VF_UC_MACADDR_NUM); 2969 ret = -ENOMEM; 2970 goto err_rte_zmalloc; 2971 } 2972 2973 /* 2974 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2975 * on the host by "ip link set ..." command. To avoid some incorrect 2976 * scenes, for example, hns3 VF PMD driver fails to receive and send 2977 * packets after user configure the MAC address by using the 2978 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC 2979 * address strategy as the hns3 kernel ethdev driver in the 2980 * initialization. If user configure a MAC address by the ip command 2981 * for VF device, then hns3 VF PMD driver will start with it, otherwise 2982 * start with a random MAC address in the initialization. 2983 */ 2984 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr)) 2985 rte_eth_random_addr(hw->mac.mac_addr); 2986 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 2987 ð_dev->data->mac_addrs[0]); 2988 2989 hw->adapter_state = HNS3_NIC_INITIALIZED; 2990 2991 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2992 SCHEDULE_PENDING) { 2993 hns3_err(hw, "Reschedule reset service after dev_init"); 2994 hns3_schedule_reset(hns); 2995 } else { 2996 /* IMP will wait ready flag before reset */ 2997 hns3_notify_reset_ready(hw, false); 2998 } 2999 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 3000 eth_dev); 3001 return 0; 3002 3003 err_rte_zmalloc: 3004 hns3vf_uninit_vf(eth_dev); 3005 3006 err_init_vf: 3007 rte_free(hw->reset.wait_data); 3008 3009 err_init_reset: 3010 hns3_mp_uninit_primary(); 3011 3012 err_mp_init_primary: 3013 err_mp_init_secondary: 3014 eth_dev->dev_ops = NULL; 3015 eth_dev->rx_pkt_burst = NULL; 3016 eth_dev->rx_descriptor_status = NULL; 3017 eth_dev->tx_pkt_burst = NULL; 3018 eth_dev->tx_pkt_prepare = NULL; 3019 eth_dev->tx_descriptor_status = NULL; 3020 rte_free(eth_dev->process_private); 3021 eth_dev->process_private = NULL; 3022 3023 return ret; 3024 } 3025 3026 static int 3027 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev) 3028 { 3029 struct hns3_adapter *hns = eth_dev->data->dev_private; 3030 struct hns3_hw *hw = &hns->hw; 3031 3032 PMD_INIT_FUNC_TRACE(); 3033 3034 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 3035 rte_free(eth_dev->process_private); 3036 eth_dev->process_private = NULL; 3037 return 0; 3038 } 3039 3040 if (hw->adapter_state < HNS3_NIC_CLOSING) 3041 hns3vf_dev_close(eth_dev); 3042 3043 hw->adapter_state = HNS3_NIC_REMOVED; 3044 return 0; 3045 } 3046 3047 static int 3048 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3049 struct rte_pci_device *pci_dev) 3050 { 3051 return rte_eth_dev_pci_generic_probe(pci_dev, 3052 sizeof(struct hns3_adapter), 3053 hns3vf_dev_init); 3054 } 3055 3056 static int 3057 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev) 3058 { 3059 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit); 3060 } 3061 3062 static const struct rte_pci_id pci_id_hns3vf_map[] = { 3063 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) }, 3064 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) }, 3065 { .vendor_id = 0, }, /* sentinel */ 3066 }; 3067 3068 static struct rte_pci_driver rte_hns3vf_pmd = { 3069 .id_table = pci_id_hns3vf_map, 3070 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3071 .probe = eth_hns3vf_pci_probe, 3072 .remove = eth_hns3vf_pci_remove, 3073 }; 3074 3075 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); 3076 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); 3077 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); 3078 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf, 3079 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 3080 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " 3081 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "); 3082