1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <linux/pci_regs.h> 6 #include <rte_alarm.h> 7 #include <ethdev_pci.h> 8 #include <rte_io.h> 9 #include <rte_pci.h> 10 #include <rte_vfio.h> 11 12 #include "hns3_ethdev.h" 13 #include "hns3_logs.h" 14 #include "hns3_rxtx.h" 15 #include "hns3_regs.h" 16 #include "hns3_intr.h" 17 #include "hns3_dcb.h" 18 #include "hns3_mp.h" 19 20 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */ 21 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */ 22 23 #define HNS3VF_RESET_WAIT_MS 20 24 #define HNS3VF_RESET_WAIT_CNT 2000 25 26 /* Reset related Registers */ 27 #define HNS3_GLOBAL_RESET_BIT 0 28 #define HNS3_CORE_RESET_BIT 1 29 #define HNS3_IMP_RESET_BIT 2 30 #define HNS3_FUN_RST_ING_B 0 31 32 enum hns3vf_evt_cause { 33 HNS3VF_VECTOR0_EVENT_RST, 34 HNS3VF_VECTOR0_EVENT_MBX, 35 HNS3VF_VECTOR0_EVENT_OTHER, 36 }; 37 38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw, 39 uint64_t *levels); 40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev); 42 43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 44 struct rte_ether_addr *mac_addr); 45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 46 struct rte_ether_addr *mac_addr); 47 /* set PCI bus mastering */ 48 static int 49 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) 50 { 51 uint16_t reg; 52 int ret; 53 54 ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); 55 if (ret < 0) { 56 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 57 PCI_COMMAND); 58 return ret; 59 } 60 61 if (op) 62 /* set the master bit */ 63 reg |= PCI_COMMAND_MASTER; 64 else 65 reg &= ~(PCI_COMMAND_MASTER); 66 67 return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); 68 } 69 70 /** 71 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list 72 * @cap: the capability 73 * 74 * Return the address of the given capability within the PCI capability list. 75 */ 76 static int 77 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) 78 { 79 #define MAX_PCIE_CAPABILITY 48 80 uint16_t status; 81 uint8_t pos; 82 uint8_t id; 83 int ttl; 84 int ret; 85 86 ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); 87 if (ret < 0) { 88 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS); 89 return 0; 90 } 91 92 if (!(status & PCI_STATUS_CAP_LIST)) 93 return 0; 94 95 ttl = MAX_PCIE_CAPABILITY; 96 ret = rte_pci_read_config(device, &pos, sizeof(pos), 97 PCI_CAPABILITY_LIST); 98 if (ret < 0) { 99 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 100 PCI_CAPABILITY_LIST); 101 return 0; 102 } 103 104 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { 105 ret = rte_pci_read_config(device, &id, sizeof(id), 106 (pos + PCI_CAP_LIST_ID)); 107 if (ret < 0) { 108 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 109 (pos + PCI_CAP_LIST_ID)); 110 break; 111 } 112 113 if (id == 0xFF) 114 break; 115 116 if (id == cap) 117 return (int)pos; 118 119 ret = rte_pci_read_config(device, &pos, sizeof(pos), 120 (pos + PCI_CAP_LIST_NEXT)); 121 if (ret < 0) { 122 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 123 (pos + PCI_CAP_LIST_NEXT)); 124 break; 125 } 126 } 127 return 0; 128 } 129 130 static int 131 hns3vf_enable_msix(const struct rte_pci_device *device, bool op) 132 { 133 uint16_t control; 134 int pos; 135 int ret; 136 137 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); 138 if (pos) { 139 ret = rte_pci_read_config(device, &control, sizeof(control), 140 (pos + PCI_MSIX_FLAGS)); 141 if (ret < 0) { 142 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", 143 (pos + PCI_MSIX_FLAGS)); 144 return -ENXIO; 145 } 146 147 if (op) 148 control |= PCI_MSIX_FLAGS_ENABLE; 149 else 150 control &= ~PCI_MSIX_FLAGS_ENABLE; 151 ret = rte_pci_write_config(device, &control, sizeof(control), 152 (pos + PCI_MSIX_FLAGS)); 153 if (ret < 0) { 154 PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x", 155 (pos + PCI_MSIX_FLAGS)); 156 } 157 return 0; 158 } 159 return -ENXIO; 160 } 161 162 static int 163 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 164 { 165 /* mac address was checked by upper level interface */ 166 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 167 int ret; 168 169 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 170 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes, 171 RTE_ETHER_ADDR_LEN, false, NULL, 0); 172 if (ret) { 173 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 174 mac_addr); 175 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 176 mac_str, ret); 177 } 178 return ret; 179 } 180 181 static int 182 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 183 { 184 /* mac address was checked by upper level interface */ 185 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 186 int ret; 187 188 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 189 HNS3_MBX_MAC_VLAN_UC_REMOVE, 190 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, 191 false, NULL, 0); 192 if (ret) { 193 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 194 mac_addr); 195 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d", 196 mac_str, ret); 197 } 198 return ret; 199 } 200 201 static int 202 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 203 { 204 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 205 struct rte_ether_addr *addr; 206 int ret; 207 int i; 208 209 for (i = 0; i < hw->mc_addrs_num; i++) { 210 addr = &hw->mc_addrs[i]; 211 /* Check if there are duplicate addresses */ 212 if (rte_is_same_ether_addr(addr, mac_addr)) { 213 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 214 addr); 215 hns3_err(hw, "failed to add mc mac addr, same addrs" 216 "(%s) is added by the set_mc_mac_addr_list " 217 "API", mac_str); 218 return -EINVAL; 219 } 220 } 221 222 ret = hns3vf_add_mc_mac_addr(hw, mac_addr); 223 if (ret) { 224 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 225 mac_addr); 226 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 227 mac_str, ret); 228 } 229 return ret; 230 } 231 232 static int 233 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 234 __rte_unused uint32_t idx, 235 __rte_unused uint32_t pool) 236 { 237 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 238 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 239 int ret; 240 241 rte_spinlock_lock(&hw->lock); 242 243 /* 244 * In hns3 network engine adding UC and MC mac address with different 245 * commands with firmware. We need to determine whether the input 246 * address is a UC or a MC address to call different commands. 247 * By the way, it is recommended calling the API function named 248 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 249 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 250 * may affect the specifications of UC mac addresses. 251 */ 252 if (rte_is_multicast_ether_addr(mac_addr)) 253 ret = hns3vf_add_mc_addr_common(hw, mac_addr); 254 else 255 ret = hns3vf_add_uc_mac_addr(hw, mac_addr); 256 257 rte_spinlock_unlock(&hw->lock); 258 if (ret) { 259 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 260 mac_addr); 261 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 262 ret); 263 } 264 265 return ret; 266 } 267 268 static void 269 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 270 { 271 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 272 /* index will be checked by upper level rte interface */ 273 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 274 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 275 int ret; 276 277 rte_spinlock_lock(&hw->lock); 278 279 if (rte_is_multicast_ether_addr(mac_addr)) 280 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr); 281 else 282 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr); 283 284 rte_spinlock_unlock(&hw->lock); 285 if (ret) { 286 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 287 mac_addr); 288 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", 289 mac_str, ret); 290 } 291 } 292 293 static int 294 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev, 295 struct rte_ether_addr *mac_addr) 296 { 297 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2) 298 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 299 struct rte_ether_addr *old_addr; 300 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */ 301 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 302 int ret; 303 304 /* 305 * It has been guaranteed that input parameter named mac_addr is valid 306 * address in the rte layer of DPDK framework. 307 */ 308 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 309 rte_spinlock_lock(&hw->lock); 310 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN); 311 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes, 312 RTE_ETHER_ADDR_LEN); 313 314 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, 315 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes, 316 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0); 317 if (ret) { 318 /* 319 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev 320 * driver. When user has configured a MAC address for VF device 321 * by "ip link set ..." command based on the PF device, the hns3 322 * PF kernel ethdev driver does not allow VF driver to request 323 * reconfiguring a different default MAC address, and return 324 * -EPREM to VF driver through mailbox. 325 */ 326 if (ret == -EPERM) { 327 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 328 old_addr); 329 hns3_warn(hw, "Has permanet mac addr(%s) for vf", 330 mac_str); 331 } else { 332 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 333 mac_addr); 334 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", 335 mac_str, ret); 336 } 337 } 338 339 rte_ether_addr_copy(mac_addr, 340 (struct rte_ether_addr *)hw->mac.mac_addr); 341 rte_spinlock_unlock(&hw->lock); 342 343 return ret; 344 } 345 346 static int 347 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del) 348 { 349 struct hns3_hw *hw = &hns->hw; 350 struct rte_ether_addr *addr; 351 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 352 int err = 0; 353 int ret; 354 int i; 355 356 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) { 357 addr = &hw->data->mac_addrs[i]; 358 if (rte_is_zero_ether_addr(addr)) 359 continue; 360 if (rte_is_multicast_ether_addr(addr)) 361 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) : 362 hns3vf_add_mc_mac_addr(hw, addr); 363 else 364 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) : 365 hns3vf_add_uc_mac_addr(hw, addr); 366 367 if (ret) { 368 err = ret; 369 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 370 addr); 371 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 372 "ret = %d.", del ? "remove" : "restore", 373 mac_str, i, ret); 374 } 375 } 376 return err; 377 } 378 379 static int 380 hns3vf_add_mc_mac_addr(struct hns3_hw *hw, 381 struct rte_ether_addr *mac_addr) 382 { 383 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 384 int ret; 385 386 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 387 HNS3_MBX_MAC_VLAN_MC_ADD, 388 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 389 NULL, 0); 390 if (ret) { 391 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 392 mac_addr); 393 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d", 394 mac_str, ret); 395 } 396 397 return ret; 398 } 399 400 static int 401 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, 402 struct rte_ether_addr *mac_addr) 403 { 404 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 405 int ret; 406 407 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST, 408 HNS3_MBX_MAC_VLAN_MC_REMOVE, 409 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false, 410 NULL, 0); 411 if (ret) { 412 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 413 mac_addr); 414 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d", 415 mac_str, ret); 416 } 417 418 return ret; 419 } 420 421 static int 422 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw, 423 struct rte_ether_addr *mc_addr_set, 424 uint32_t nb_mc_addr) 425 { 426 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 427 struct rte_ether_addr *addr; 428 uint32_t i; 429 uint32_t j; 430 431 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 432 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 433 "invalid. valid range: 0~%d", 434 nb_mc_addr, HNS3_MC_MACADDR_NUM); 435 return -EINVAL; 436 } 437 438 /* Check if input mac addresses are valid */ 439 for (i = 0; i < nb_mc_addr; i++) { 440 addr = &mc_addr_set[i]; 441 if (!rte_is_multicast_ether_addr(addr)) { 442 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 443 addr); 444 hns3_err(hw, 445 "failed to set mc mac addr, addr(%s) invalid.", 446 mac_str); 447 return -EINVAL; 448 } 449 450 /* Check if there are duplicate addresses */ 451 for (j = i + 1; j < nb_mc_addr; j++) { 452 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 453 hns3_ether_format_addr(mac_str, 454 RTE_ETHER_ADDR_FMT_SIZE, 455 addr); 456 hns3_err(hw, "failed to set mc mac addr, " 457 "addrs invalid. two same addrs(%s).", 458 mac_str); 459 return -EINVAL; 460 } 461 } 462 463 /* 464 * Check if there are duplicate addresses between mac_addrs 465 * and mc_addr_set 466 */ 467 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) { 468 if (rte_is_same_ether_addr(addr, 469 &hw->data->mac_addrs[j])) { 470 hns3_ether_format_addr(mac_str, 471 RTE_ETHER_ADDR_FMT_SIZE, 472 addr); 473 hns3_err(hw, "failed to set mc mac addr, " 474 "addrs invalid. addrs(%s) has already " 475 "configured in mac_addr add API", 476 mac_str); 477 return -EINVAL; 478 } 479 } 480 } 481 482 return 0; 483 } 484 485 static int 486 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev, 487 struct rte_ether_addr *mc_addr_set, 488 uint32_t nb_mc_addr) 489 { 490 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 491 struct rte_ether_addr *addr; 492 int cur_addr_num; 493 int set_addr_num; 494 int num; 495 int ret; 496 int i; 497 498 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 499 if (ret) 500 return ret; 501 502 rte_spinlock_lock(&hw->lock); 503 cur_addr_num = hw->mc_addrs_num; 504 for (i = 0; i < cur_addr_num; i++) { 505 num = cur_addr_num - i - 1; 506 addr = &hw->mc_addrs[num]; 507 ret = hns3vf_remove_mc_mac_addr(hw, addr); 508 if (ret) { 509 rte_spinlock_unlock(&hw->lock); 510 return ret; 511 } 512 513 hw->mc_addrs_num--; 514 } 515 516 set_addr_num = (int)nb_mc_addr; 517 for (i = 0; i < set_addr_num; i++) { 518 addr = &mc_addr_set[i]; 519 ret = hns3vf_add_mc_mac_addr(hw, addr); 520 if (ret) { 521 rte_spinlock_unlock(&hw->lock); 522 return ret; 523 } 524 525 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]); 526 hw->mc_addrs_num++; 527 } 528 rte_spinlock_unlock(&hw->lock); 529 530 return 0; 531 } 532 533 static int 534 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 535 { 536 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 537 struct hns3_hw *hw = &hns->hw; 538 struct rte_ether_addr *addr; 539 int err = 0; 540 int ret; 541 int i; 542 543 for (i = 0; i < hw->mc_addrs_num; i++) { 544 addr = &hw->mc_addrs[i]; 545 if (!rte_is_multicast_ether_addr(addr)) 546 continue; 547 if (del) 548 ret = hns3vf_remove_mc_mac_addr(hw, addr); 549 else 550 ret = hns3vf_add_mc_mac_addr(hw, addr); 551 if (ret) { 552 err = ret; 553 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 554 addr); 555 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d", 556 del ? "Remove" : "Restore", mac_str, ret); 557 } 558 } 559 return err; 560 } 561 562 static int 563 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc, 564 bool en_uc_pmc, bool en_mc_pmc) 565 { 566 struct hns3_mbx_vf_to_pf_cmd *req; 567 struct hns3_cmd_desc desc; 568 int ret; 569 570 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data; 571 572 /* 573 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver, 574 * so there are some features for promiscuous/allmulticast mode in hns3 575 * VF PMD driver as below: 576 * 1. The promiscuous/allmulticast mode can be configured successfully 577 * only based on the trusted VF device. If based on the non trusted 578 * VF device, configuring promiscuous/allmulticast mode will fail. 579 * The hns3 VF device can be confiruged as trusted device by hns3 PF 580 * kernel ethdev driver on the host by the following command: 581 * "ip link set <eth num> vf <vf id> turst on" 582 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD 583 * driver can receive the ingress and outgoing traffic. In the words, 584 * all the ingress packets, all the packets sent from the PF and 585 * other VFs on the same physical port. 586 * 3. Note: Because of the hardware constraints, By default vlan filter 587 * is enabled and couldn't be turned off based on VF device, so vlan 588 * filter is still effective even in promiscuous mode. If upper 589 * applications don't call rte_eth_dev_vlan_filter API function to 590 * set vlan based on VF device, hns3 VF PMD driver will can't receive 591 * the packets with vlan tag in promiscuoue mode. 592 */ 593 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false); 594 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE; 595 req->msg[1] = en_bc_pmc ? 1 : 0; 596 req->msg[2] = en_uc_pmc ? 1 : 0; 597 req->msg[3] = en_mc_pmc ? 1 : 0; 598 req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0; 599 600 ret = hns3_cmd_send(hw, &desc, 1); 601 if (ret) 602 hns3_err(hw, "Set promisc mode fail, ret = %d", ret); 603 604 return ret; 605 } 606 607 static int 608 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev) 609 { 610 struct hns3_adapter *hns = dev->data->dev_private; 611 struct hns3_hw *hw = &hns->hw; 612 int ret; 613 614 ret = hns3vf_set_promisc_mode(hw, true, true, true); 615 if (ret) 616 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d", 617 ret); 618 return ret; 619 } 620 621 static int 622 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev) 623 { 624 bool allmulti = dev->data->all_multicast ? true : false; 625 struct hns3_adapter *hns = dev->data->dev_private; 626 struct hns3_hw *hw = &hns->hw; 627 int ret; 628 629 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti); 630 if (ret) 631 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d", 632 ret); 633 return ret; 634 } 635 636 static int 637 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev) 638 { 639 struct hns3_adapter *hns = dev->data->dev_private; 640 struct hns3_hw *hw = &hns->hw; 641 int ret; 642 643 if (dev->data->promiscuous) 644 return 0; 645 646 ret = hns3vf_set_promisc_mode(hw, true, false, true); 647 if (ret) 648 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d", 649 ret); 650 return ret; 651 } 652 653 static int 654 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev) 655 { 656 struct hns3_adapter *hns = dev->data->dev_private; 657 struct hns3_hw *hw = &hns->hw; 658 int ret; 659 660 if (dev->data->promiscuous) 661 return 0; 662 663 ret = hns3vf_set_promisc_mode(hw, true, false, false); 664 if (ret) 665 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d", 666 ret); 667 return ret; 668 } 669 670 static int 671 hns3vf_restore_promisc(struct hns3_adapter *hns) 672 { 673 struct hns3_hw *hw = &hns->hw; 674 bool allmulti = hw->data->all_multicast ? true : false; 675 676 if (hw->data->promiscuous) 677 return hns3vf_set_promisc_mode(hw, true, true, true); 678 679 return hns3vf_set_promisc_mode(hw, true, false, allmulti); 680 } 681 682 static int 683 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, 684 bool mmap, enum hns3_ring_type queue_type, 685 uint16_t queue_id) 686 { 687 struct hns3_vf_bind_vector_msg bind_msg; 688 const char *op_str; 689 uint16_t code; 690 int ret; 691 692 memset(&bind_msg, 0, sizeof(bind_msg)); 693 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR : 694 HNS3_MBX_UNMAP_RING_TO_VECTOR; 695 bind_msg.vector_id = vector_id; 696 697 if (queue_type == HNS3_RING_TYPE_RX) 698 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX; 699 else 700 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX; 701 702 bind_msg.param[0].ring_type = queue_type; 703 bind_msg.ring_num = 1; 704 bind_msg.param[0].tqp_index = queue_id; 705 op_str = mmap ? "Map" : "Unmap"; 706 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg, 707 sizeof(bind_msg), false, NULL, 0); 708 if (ret) 709 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.", 710 op_str, queue_id, bind_msg.vector_id, ret); 711 712 return ret; 713 } 714 715 static int 716 hns3vf_init_ring_with_vector(struct hns3_hw *hw) 717 { 718 uint16_t vec; 719 int ret; 720 int i; 721 722 /* 723 * In hns3 network engine, vector 0 is always the misc interrupt of this 724 * function, vector 1~N can be used respectively for the queues of the 725 * function. Tx and Rx queues with the same number share the interrupt 726 * vector. In the initialization clearing the all hardware mapping 727 * relationship configurations between queues and interrupt vectors is 728 * needed, so some error caused by the residual configurations, such as 729 * the unexpected Tx interrupt, can be avoid. 730 */ 731 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 732 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 733 vec = vec - 1; /* the last interrupt is reserved */ 734 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 735 for (i = 0; i < hw->intr_tqps_num; i++) { 736 /* 737 * Set gap limiter/rate limiter/quanity limiter algorithm 738 * configuration for interrupt coalesce of queue's interrupt. 739 */ 740 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 741 HNS3_TQP_INTR_GL_DEFAULT); 742 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 743 HNS3_TQP_INTR_GL_DEFAULT); 744 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 745 /* 746 * QL(quantity limiter) is not used currently, just set 0 to 747 * close it. 748 */ 749 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 750 751 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 752 HNS3_RING_TYPE_TX, i); 753 if (ret) { 754 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with " 755 "vector: %u, ret=%d", i, vec, ret); 756 return ret; 757 } 758 759 ret = hns3vf_bind_ring_with_vector(hw, vec, false, 760 HNS3_RING_TYPE_RX, i); 761 if (ret) { 762 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with " 763 "vector: %u, ret=%d", i, vec, ret); 764 return ret; 765 } 766 } 767 768 return 0; 769 } 770 771 static int 772 hns3vf_dev_configure(struct rte_eth_dev *dev) 773 { 774 struct hns3_adapter *hns = dev->data->dev_private; 775 struct hns3_hw *hw = &hns->hw; 776 struct rte_eth_conf *conf = &dev->data->dev_conf; 777 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 778 uint16_t nb_rx_q = dev->data->nb_rx_queues; 779 uint16_t nb_tx_q = dev->data->nb_tx_queues; 780 struct rte_eth_rss_conf rss_conf; 781 uint32_t max_rx_pkt_len; 782 uint16_t mtu; 783 bool gro_en; 784 int ret; 785 786 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 787 788 /* 789 * Some versions of hardware network engine does not support 790 * individually enable/disable/reset the Tx or Rx queue. These devices 791 * must enable/disable/reset Tx and Rx queues at the same time. When the 792 * numbers of Tx queues allocated by upper applications are not equal to 793 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 794 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 795 * work as usual. But these fake queues are imperceptible, and can not 796 * be used by upper applications. 797 */ 798 if (!hns3_dev_indep_txrx_supported(hw)) { 799 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 800 if (ret) { 801 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", 802 ret); 803 return ret; 804 } 805 } 806 807 hw->adapter_state = HNS3_NIC_CONFIGURING; 808 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 809 hns3_err(hw, "setting link speed/duplex not supported"); 810 ret = -EINVAL; 811 goto cfg_err; 812 } 813 814 /* When RSS is not configured, redirect the packet queue 0 */ 815 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 816 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 817 hw->rss_dis_flag = false; 818 rss_conf = conf->rx_adv_conf.rss_conf; 819 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 820 if (ret) 821 goto cfg_err; 822 } 823 824 /* 825 * If jumbo frames are enabled, MTU needs to be refreshed 826 * according to the maximum RX packet length. 827 */ 828 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 829 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len; 830 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN || 831 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) { 832 hns3_err(hw, "maximum Rx packet length must be greater " 833 "than %u and less than %u when jumbo frame enabled.", 834 (uint16_t)HNS3_DEFAULT_FRAME_LEN, 835 (uint16_t)HNS3_MAX_FRAME_LEN); 836 ret = -EINVAL; 837 goto cfg_err; 838 } 839 840 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len); 841 ret = hns3vf_dev_mtu_set(dev, mtu); 842 if (ret) 843 goto cfg_err; 844 dev->data->mtu = mtu; 845 } 846 847 ret = hns3vf_dev_configure_vlan(dev); 848 if (ret) 849 goto cfg_err; 850 851 /* config hardware GRO */ 852 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 853 ret = hns3_config_gro(hw, gro_en); 854 if (ret) 855 goto cfg_err; 856 857 hns->rx_simple_allowed = true; 858 hns->rx_vec_allowed = true; 859 hns->tx_simple_allowed = true; 860 hns->tx_vec_allowed = true; 861 862 hns3_init_rx_ptype_tble(dev); 863 864 hw->adapter_state = HNS3_NIC_CONFIGURED; 865 return 0; 866 867 cfg_err: 868 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 869 hw->adapter_state = HNS3_NIC_INITIALIZED; 870 871 return ret; 872 } 873 874 static int 875 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu) 876 { 877 int ret; 878 879 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu, 880 sizeof(mtu), true, NULL, 0); 881 if (ret) 882 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret); 883 884 return ret; 885 } 886 887 static int 888 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 889 { 890 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 891 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 892 int ret; 893 894 /* 895 * The hns3 PF/VF devices on the same port share the hardware MTU 896 * configuration. Currently, we send mailbox to inform hns3 PF kernel 897 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD 898 * driver, there is no need to stop the port for hns3 VF device, and the 899 * MTU value issued by hns3 VF PMD driver must be less than or equal to 900 * PF's MTU. 901 */ 902 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 903 hns3_err(hw, "Failed to set mtu during resetting"); 904 return -EIO; 905 } 906 907 /* 908 * when Rx of scattered packets is off, we have some possibility of 909 * using vector Rx process function or simple Rx functions in hns3 PMD 910 * driver. If the input MTU is increased and the maximum length of 911 * received packets is greater than the length of a buffer for Rx 912 * packet, the hardware network engine needs to use multiple BDs and 913 * buffers to store these packets. This will cause problems when still 914 * using vector Rx process function or simple Rx function to receiving 915 * packets. So, when Rx of scattered packets is off and device is 916 * started, it is not permitted to increase MTU so that the maximum 917 * length of Rx packets is greater than Rx buffer length. 918 */ 919 if (dev->data->dev_started && !dev->data->scattered_rx && 920 frame_size > hw->rx_buf_len) { 921 hns3_err(hw, "failed to set mtu because current is " 922 "not scattered rx mode"); 923 return -EOPNOTSUPP; 924 } 925 926 rte_spinlock_lock(&hw->lock); 927 ret = hns3vf_config_mtu(hw, mtu); 928 if (ret) { 929 rte_spinlock_unlock(&hw->lock); 930 return ret; 931 } 932 if (mtu > RTE_ETHER_MTU) 933 dev->data->dev_conf.rxmode.offloads |= 934 DEV_RX_OFFLOAD_JUMBO_FRAME; 935 else 936 dev->data->dev_conf.rxmode.offloads &= 937 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 938 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 939 rte_spinlock_unlock(&hw->lock); 940 941 return 0; 942 } 943 944 static int 945 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 946 { 947 struct hns3_adapter *hns = eth_dev->data->dev_private; 948 struct hns3_hw *hw = &hns->hw; 949 uint16_t q_num = hw->tqps_num; 950 951 /* 952 * In interrupt mode, 'max_rx_queues' is set based on the number of 953 * MSI-X interrupt resources of the hardware. 954 */ 955 if (hw->data->dev_conf.intr_conf.rxq == 1) 956 q_num = hw->intr_tqps_num; 957 958 info->max_rx_queues = q_num; 959 info->max_tx_queues = hw->tqps_num; 960 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 961 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 962 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; 963 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 964 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 965 966 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 967 DEV_RX_OFFLOAD_UDP_CKSUM | 968 DEV_RX_OFFLOAD_TCP_CKSUM | 969 DEV_RX_OFFLOAD_SCTP_CKSUM | 970 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 971 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 972 DEV_RX_OFFLOAD_SCATTER | 973 DEV_RX_OFFLOAD_VLAN_STRIP | 974 DEV_RX_OFFLOAD_VLAN_FILTER | 975 DEV_RX_OFFLOAD_JUMBO_FRAME | 976 DEV_RX_OFFLOAD_RSS_HASH | 977 DEV_RX_OFFLOAD_TCP_LRO); 978 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 979 DEV_TX_OFFLOAD_IPV4_CKSUM | 980 DEV_TX_OFFLOAD_TCP_CKSUM | 981 DEV_TX_OFFLOAD_UDP_CKSUM | 982 DEV_TX_OFFLOAD_SCTP_CKSUM | 983 DEV_TX_OFFLOAD_MULTI_SEGS | 984 DEV_TX_OFFLOAD_TCP_TSO | 985 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 986 DEV_TX_OFFLOAD_GRE_TNL_TSO | 987 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 988 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 989 hns3_txvlan_cap_get(hw)); 990 991 if (hns3_dev_outer_udp_cksum_supported(hw)) 992 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 993 994 if (hns3_dev_indep_txrx_supported(hw)) 995 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 996 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 997 998 info->rx_desc_lim = (struct rte_eth_desc_lim) { 999 .nb_max = HNS3_MAX_RING_DESC, 1000 .nb_min = HNS3_MIN_RING_DESC, 1001 .nb_align = HNS3_ALIGN_RING_DESC, 1002 }; 1003 1004 info->tx_desc_lim = (struct rte_eth_desc_lim) { 1005 .nb_max = HNS3_MAX_RING_DESC, 1006 .nb_min = HNS3_MIN_RING_DESC, 1007 .nb_align = HNS3_ALIGN_RING_DESC, 1008 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 1009 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 1010 }; 1011 1012 info->default_rxconf = (struct rte_eth_rxconf) { 1013 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 1014 /* 1015 * If there are no available Rx buffer descriptors, incoming 1016 * packets are always dropped by hardware based on hns3 network 1017 * engine. 1018 */ 1019 .rx_drop_en = 1, 1020 .offloads = 0, 1021 }; 1022 info->default_txconf = (struct rte_eth_txconf) { 1023 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 1024 .offloads = 0, 1025 }; 1026 1027 info->vmdq_queue_num = 0; 1028 1029 info->reta_size = hw->rss_ind_tbl_size; 1030 info->hash_key_size = HNS3_RSS_KEY_SIZE; 1031 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 1032 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1033 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 1034 1035 return 0; 1036 } 1037 1038 static void 1039 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr) 1040 { 1041 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 1042 } 1043 1044 static void 1045 hns3vf_disable_irq0(struct hns3_hw *hw) 1046 { 1047 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 1048 } 1049 1050 static void 1051 hns3vf_enable_irq0(struct hns3_hw *hw) 1052 { 1053 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 1054 } 1055 1056 static enum hns3vf_evt_cause 1057 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 1058 { 1059 struct hns3_hw *hw = &hns->hw; 1060 enum hns3vf_evt_cause ret; 1061 uint32_t cmdq_stat_reg; 1062 uint32_t rst_ing_reg; 1063 uint32_t val; 1064 1065 /* Fetch the events from their corresponding regs */ 1066 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG); 1067 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1068 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING); 1069 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg); 1070 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 1071 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 1072 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 1073 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT); 1074 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B); 1075 if (clearval) { 1076 hw->reset.stats.global_cnt++; 1077 hns3_warn(hw, "Global reset detected, clear reset status"); 1078 } else { 1079 hns3_schedule_delayed_reset(hns); 1080 hns3_warn(hw, "Global reset detected, don't clear reset status"); 1081 } 1082 1083 ret = HNS3VF_VECTOR0_EVENT_RST; 1084 goto out; 1085 } 1086 1087 /* Check for vector0 mailbox(=CMDQ RX) event source */ 1088 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1089 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 1090 ret = HNS3VF_VECTOR0_EVENT_MBX; 1091 goto out; 1092 } 1093 1094 val = 0; 1095 ret = HNS3VF_VECTOR0_EVENT_OTHER; 1096 out: 1097 if (clearval) 1098 *clearval = val; 1099 return ret; 1100 } 1101 1102 static void 1103 hns3vf_interrupt_handler(void *param) 1104 { 1105 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1106 struct hns3_adapter *hns = dev->data->dev_private; 1107 struct hns3_hw *hw = &hns->hw; 1108 enum hns3vf_evt_cause event_cause; 1109 uint32_t clearval; 1110 1111 /* Disable interrupt */ 1112 hns3vf_disable_irq0(hw); 1113 1114 /* Read out interrupt causes */ 1115 event_cause = hns3vf_check_event_cause(hns, &clearval); 1116 1117 switch (event_cause) { 1118 case HNS3VF_VECTOR0_EVENT_RST: 1119 hns3_schedule_reset(hns); 1120 break; 1121 case HNS3VF_VECTOR0_EVENT_MBX: 1122 hns3_dev_handle_mbx_msg(hw); 1123 break; 1124 default: 1125 break; 1126 } 1127 1128 /* Clear interrupt causes */ 1129 hns3vf_clear_event_cause(hw, clearval); 1130 1131 /* Enable interrupt */ 1132 hns3vf_enable_irq0(hw); 1133 } 1134 1135 static void 1136 hns3vf_set_default_dev_specifications(struct hns3_hw *hw) 1137 { 1138 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 1139 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 1140 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 1141 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 1142 } 1143 1144 static void 1145 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 1146 { 1147 struct hns3_dev_specs_0_cmd *req0; 1148 1149 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 1150 1151 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 1152 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 1153 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 1154 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 1155 } 1156 1157 static int 1158 hns3vf_check_dev_specifications(struct hns3_hw *hw) 1159 { 1160 if (hw->rss_ind_tbl_size == 0 || 1161 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 1162 hns3_warn(hw, "the size of hash lookup table configured (%u)" 1163 " exceeds the maximum(%u)", hw->rss_ind_tbl_size, 1164 HNS3_RSS_IND_TBL_SIZE_MAX); 1165 return -EINVAL; 1166 } 1167 1168 return 0; 1169 } 1170 1171 static int 1172 hns3vf_query_dev_specifications(struct hns3_hw *hw) 1173 { 1174 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 1175 int ret; 1176 int i; 1177 1178 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1179 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 1180 true); 1181 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1182 } 1183 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 1184 1185 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 1186 if (ret) 1187 return ret; 1188 1189 hns3vf_parse_dev_specifications(hw, desc); 1190 1191 return hns3vf_check_dev_specifications(hw); 1192 } 1193 1194 static int 1195 hns3vf_get_capability(struct hns3_hw *hw) 1196 { 1197 struct rte_pci_device *pci_dev; 1198 struct rte_eth_dev *eth_dev; 1199 uint8_t revision; 1200 int ret; 1201 1202 eth_dev = &rte_eth_devices[hw->data->port_id]; 1203 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1204 1205 /* Get PCI revision id */ 1206 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 1207 HNS3_PCI_REVISION_ID); 1208 if (ret != HNS3_PCI_REVISION_ID_LEN) { 1209 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 1210 ret); 1211 return -EIO; 1212 } 1213 hw->revision = revision; 1214 1215 if (revision < PCI_REVISION_ID_HIP09_A) { 1216 hns3vf_set_default_dev_specifications(hw); 1217 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 1218 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 1219 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 1220 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 1221 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 1222 hw->rss_info.ipv6_sctp_offload_supported = false; 1223 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; 1224 return 0; 1225 } 1226 1227 ret = hns3vf_query_dev_specifications(hw); 1228 if (ret) { 1229 PMD_INIT_LOG(ERR, 1230 "failed to query dev specifications, ret = %d", 1231 ret); 1232 return ret; 1233 } 1234 1235 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 1236 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 1237 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 1238 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 1239 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 1240 hw->rss_info.ipv6_sctp_offload_supported = true; 1241 hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; 1242 1243 return 0; 1244 } 1245 1246 static int 1247 hns3vf_check_tqp_info(struct hns3_hw *hw) 1248 { 1249 if (hw->tqps_num == 0) { 1250 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF."); 1251 return -EINVAL; 1252 } 1253 1254 if (hw->rss_size_max == 0) { 1255 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF."); 1256 return -EINVAL; 1257 } 1258 1259 hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num); 1260 1261 return 0; 1262 } 1263 1264 static int 1265 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw) 1266 { 1267 uint8_t resp_msg; 1268 int ret; 1269 1270 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, 1271 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0, 1272 true, &resp_msg, sizeof(resp_msg)); 1273 if (ret) { 1274 if (ret == -ETIME) { 1275 /* 1276 * Getting current port based VLAN state from PF driver 1277 * will not affect VF driver's basic function. Because 1278 * the VF driver relies on hns3 PF kernel ether driver, 1279 * to avoid introducing compatibility issues with older 1280 * version of PF driver, no failure will be returned 1281 * when the return value is ETIME. This return value has 1282 * the following scenarios: 1283 * 1) Firmware didn't return the results in time 1284 * 2) the result return by firmware is timeout 1285 * 3) the older version of kernel side PF driver does 1286 * not support this mailbox message. 1287 * For scenarios 1 and 2, it is most likely that a 1288 * hardware error has occurred, or a hardware reset has 1289 * occurred. In this case, these errors will be caught 1290 * by other functions. 1291 */ 1292 PMD_INIT_LOG(WARNING, 1293 "failed to get PVID state for timeout, maybe " 1294 "kernel side PF driver doesn't support this " 1295 "mailbox message, or firmware didn't respond."); 1296 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE; 1297 } else { 1298 PMD_INIT_LOG(ERR, "failed to get port based VLAN state," 1299 " ret = %d", ret); 1300 return ret; 1301 } 1302 } 1303 hw->port_base_vlan_cfg.state = resp_msg ? 1304 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 1305 return 0; 1306 } 1307 1308 static int 1309 hns3vf_get_queue_info(struct hns3_hw *hw) 1310 { 1311 #define HNS3VF_TQPS_RSS_INFO_LEN 6 1312 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN]; 1313 int ret; 1314 1315 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true, 1316 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN); 1317 if (ret) { 1318 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret); 1319 return ret; 1320 } 1321 1322 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t)); 1323 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t)); 1324 1325 return hns3vf_check_tqp_info(hw); 1326 } 1327 1328 static int 1329 hns3vf_get_queue_depth(struct hns3_hw *hw) 1330 { 1331 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4 1332 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN]; 1333 int ret; 1334 1335 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true, 1336 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN); 1337 if (ret) { 1338 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d", 1339 ret); 1340 return ret; 1341 } 1342 1343 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t)); 1344 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t)); 1345 1346 return 0; 1347 } 1348 1349 static int 1350 hns3vf_get_tc_info(struct hns3_hw *hw) 1351 { 1352 uint8_t resp_msg; 1353 int ret; 1354 uint32_t i; 1355 1356 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0, 1357 true, &resp_msg, sizeof(resp_msg)); 1358 if (ret) { 1359 hns3_err(hw, "VF request to get TC info from PF failed %d", 1360 ret); 1361 return ret; 1362 } 1363 1364 hw->hw_tc_map = resp_msg; 1365 1366 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 1367 if (hw->hw_tc_map & BIT(i)) 1368 hw->num_tc++; 1369 } 1370 1371 return 0; 1372 } 1373 1374 static int 1375 hns3vf_get_host_mac_addr(struct hns3_hw *hw) 1376 { 1377 uint8_t host_mac[RTE_ETHER_ADDR_LEN]; 1378 int ret; 1379 1380 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0, 1381 true, host_mac, RTE_ETHER_ADDR_LEN); 1382 if (ret) { 1383 hns3_err(hw, "Failed to get mac addr from PF: %d", ret); 1384 return ret; 1385 } 1386 1387 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN); 1388 1389 return 0; 1390 } 1391 1392 static int 1393 hns3vf_get_configuration(struct hns3_hw *hw) 1394 { 1395 int ret; 1396 1397 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE; 1398 hw->rss_dis_flag = false; 1399 1400 /* Get device capability */ 1401 ret = hns3vf_get_capability(hw); 1402 if (ret) { 1403 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 1404 return ret; 1405 } 1406 1407 /* Get queue configuration from PF */ 1408 ret = hns3vf_get_queue_info(hw); 1409 if (ret) 1410 return ret; 1411 1412 /* Get queue depth info from PF */ 1413 ret = hns3vf_get_queue_depth(hw); 1414 if (ret) 1415 return ret; 1416 1417 /* Get user defined VF MAC addr from PF */ 1418 ret = hns3vf_get_host_mac_addr(hw); 1419 if (ret) 1420 return ret; 1421 1422 ret = hns3vf_get_port_base_vlan_filter_state(hw); 1423 if (ret) 1424 return ret; 1425 1426 /* Get tc configuration from PF */ 1427 return hns3vf_get_tc_info(hw); 1428 } 1429 1430 static int 1431 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q, 1432 uint16_t nb_tx_q) 1433 { 1434 struct hns3_hw *hw = &hns->hw; 1435 1436 if (nb_rx_q < hw->num_tc) { 1437 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).", 1438 nb_rx_q, hw->num_tc); 1439 return -EINVAL; 1440 } 1441 1442 if (nb_tx_q < hw->num_tc) { 1443 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).", 1444 nb_tx_q, hw->num_tc); 1445 return -EINVAL; 1446 } 1447 1448 return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q); 1449 } 1450 1451 static void 1452 hns3vf_request_link_info(struct hns3_hw *hw) 1453 { 1454 uint8_t resp_msg; 1455 int ret; 1456 1457 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 1458 return; 1459 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false, 1460 &resp_msg, sizeof(resp_msg)); 1461 if (ret) 1462 hns3_err(hw, "Failed to fetch link status from PF: %d", ret); 1463 } 1464 1465 void 1466 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1467 uint32_t link_speed, uint8_t link_duplex) 1468 { 1469 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 1470 struct hns3_mac *mac = &hw->mac; 1471 bool report_lse; 1472 bool changed; 1473 1474 changed = mac->link_status != link_status || 1475 mac->link_speed != link_speed || 1476 mac->link_duplex != link_duplex; 1477 if (!changed) 1478 return; 1479 1480 /* 1481 * VF's link status/speed/duplex were updated by polling from PF driver, 1482 * because the link status/speed/duplex may be changed in the polling 1483 * interval, so driver will report lse (lsc event) once any of the above 1484 * thress variables changed. 1485 * But if the PF's link status is down and driver saved link status is 1486 * also down, there are no need to report lse. 1487 */ 1488 report_lse = true; 1489 if (link_status == ETH_LINK_DOWN && link_status == mac->link_status) 1490 report_lse = false; 1491 1492 mac->link_status = link_status; 1493 mac->link_speed = link_speed; 1494 mac->link_duplex = link_duplex; 1495 1496 if (report_lse) 1497 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1498 } 1499 1500 static int 1501 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 1502 { 1503 #define HNS3VF_VLAN_MBX_MSG_LEN 5 1504 struct hns3_hw *hw = &hns->hw; 1505 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN]; 1506 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN); 1507 uint8_t is_kill = on ? 0 : 1; 1508 1509 msg_data[0] = is_kill; 1510 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1511 memcpy(&msg_data[3], &proto, sizeof(proto)); 1512 1513 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER, 1514 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL, 1515 0); 1516 } 1517 1518 static int 1519 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1520 { 1521 struct hns3_adapter *hns = dev->data->dev_private; 1522 struct hns3_hw *hw = &hns->hw; 1523 int ret; 1524 1525 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 1526 hns3_err(hw, 1527 "vf set vlan id failed during resetting, vlan_id =%u", 1528 vlan_id); 1529 return -EIO; 1530 } 1531 rte_spinlock_lock(&hw->lock); 1532 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1533 rte_spinlock_unlock(&hw->lock); 1534 if (ret) 1535 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d", 1536 vlan_id, ret); 1537 1538 return ret; 1539 } 1540 1541 static int 1542 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable) 1543 { 1544 uint8_t msg_data; 1545 int ret; 1546 1547 msg_data = enable ? 1 : 0; 1548 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG, 1549 &msg_data, sizeof(msg_data), false, NULL, 0); 1550 if (ret) 1551 hns3_err(hw, "vf enable strip failed, ret =%d", ret); 1552 1553 return ret; 1554 } 1555 1556 static int 1557 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1558 { 1559 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1560 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1561 unsigned int tmp_mask; 1562 int ret = 0; 1563 1564 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) { 1565 hns3_err(hw, "vf set vlan offload failed during resetting, " 1566 "mask = 0x%x", mask); 1567 return -EIO; 1568 } 1569 1570 tmp_mask = (unsigned int)mask; 1571 /* Vlan stripping setting */ 1572 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 1573 rte_spinlock_lock(&hw->lock); 1574 /* Enable or disable VLAN stripping */ 1575 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1576 ret = hns3vf_en_hw_strip_rxvtag(hw, true); 1577 else 1578 ret = hns3vf_en_hw_strip_rxvtag(hw, false); 1579 rte_spinlock_unlock(&hw->lock); 1580 } 1581 1582 return ret; 1583 } 1584 1585 static int 1586 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on) 1587 { 1588 struct rte_vlan_filter_conf *vfc; 1589 struct hns3_hw *hw = &hns->hw; 1590 uint16_t vlan_id; 1591 uint64_t vbit; 1592 uint64_t ids; 1593 int ret = 0; 1594 uint32_t i; 1595 1596 vfc = &hw->data->vlan_filter_conf; 1597 for (i = 0; i < RTE_DIM(vfc->ids); i++) { 1598 if (vfc->ids[i] == 0) 1599 continue; 1600 ids = vfc->ids[i]; 1601 while (ids) { 1602 /* 1603 * 64 means the num bits of ids, one bit corresponds to 1604 * one vlan id 1605 */ 1606 vlan_id = 64 * i; 1607 /* count trailing zeroes */ 1608 vbit = ~ids & (ids - 1); 1609 /* clear least significant bit set */ 1610 ids ^= (ids ^ (ids - 1)) ^ vbit; 1611 for (; vbit;) { 1612 vbit >>= 1; 1613 vlan_id++; 1614 } 1615 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on); 1616 if (ret) { 1617 hns3_err(hw, 1618 "VF handle vlan table failed, ret =%d, on = %d", 1619 ret, on); 1620 return ret; 1621 } 1622 } 1623 } 1624 1625 return ret; 1626 } 1627 1628 static int 1629 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns) 1630 { 1631 return hns3vf_handle_all_vlan_table(hns, 0); 1632 } 1633 1634 static int 1635 hns3vf_restore_vlan_conf(struct hns3_adapter *hns) 1636 { 1637 struct hns3_hw *hw = &hns->hw; 1638 struct rte_eth_conf *dev_conf; 1639 bool en; 1640 int ret; 1641 1642 dev_conf = &hw->data->dev_conf; 1643 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true 1644 : false; 1645 ret = hns3vf_en_hw_strip_rxvtag(hw, en); 1646 if (ret) 1647 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en, 1648 ret); 1649 return ret; 1650 } 1651 1652 static int 1653 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev) 1654 { 1655 struct hns3_adapter *hns = dev->data->dev_private; 1656 struct rte_eth_dev_data *data = dev->data; 1657 struct hns3_hw *hw = &hns->hw; 1658 int ret; 1659 1660 if (data->dev_conf.txmode.hw_vlan_reject_tagged || 1661 data->dev_conf.txmode.hw_vlan_reject_untagged || 1662 data->dev_conf.txmode.hw_vlan_insert_pvid) { 1663 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged " 1664 "or hw_vlan_insert_pvid is not support!"); 1665 } 1666 1667 /* Apply vlan offload setting */ 1668 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK); 1669 if (ret) 1670 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret); 1671 1672 return ret; 1673 } 1674 1675 static int 1676 hns3vf_set_alive(struct hns3_hw *hw, bool alive) 1677 { 1678 uint8_t msg_data; 1679 1680 msg_data = alive ? 1 : 0; 1681 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data, 1682 sizeof(msg_data), false, NULL, 0); 1683 } 1684 1685 static void 1686 hns3vf_keep_alive_handler(void *param) 1687 { 1688 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1689 struct hns3_adapter *hns = eth_dev->data->dev_private; 1690 struct hns3_hw *hw = &hns->hw; 1691 uint8_t respmsg; 1692 int ret; 1693 1694 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0, 1695 false, &respmsg, sizeof(uint8_t)); 1696 if (ret) 1697 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)", 1698 ret); 1699 1700 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 1701 eth_dev); 1702 } 1703 1704 static void 1705 hns3vf_service_handler(void *param) 1706 { 1707 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1708 struct hns3_adapter *hns = eth_dev->data->dev_private; 1709 struct hns3_hw *hw = &hns->hw; 1710 1711 /* 1712 * The query link status and reset processing are executed in the 1713 * interrupt thread.When the IMP reset occurs, IMP will not respond, 1714 * and the query operation will time out after 30ms. In the case of 1715 * multiple PF/VFs, each query failure timeout causes the IMP reset 1716 * interrupt to fail to respond within 100ms. 1717 * Before querying the link status, check whether there is a reset 1718 * pending, and if so, abandon the query. 1719 */ 1720 if (!hns3vf_is_reset_pending(hns)) 1721 hns3vf_request_link_info(hw); 1722 else 1723 hns3_warn(hw, "Cancel the query when reset is pending"); 1724 1725 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, 1726 eth_dev); 1727 } 1728 1729 static int 1730 hns3_query_vf_resource(struct hns3_hw *hw) 1731 { 1732 struct hns3_vf_res_cmd *req; 1733 struct hns3_cmd_desc desc; 1734 uint16_t num_msi; 1735 int ret; 1736 1737 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true); 1738 ret = hns3_cmd_send(hw, &desc, 1); 1739 if (ret) { 1740 hns3_err(hw, "query vf resource failed, ret = %d", ret); 1741 return ret; 1742 } 1743 1744 req = (struct hns3_vf_res_cmd *)desc.data; 1745 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number), 1746 HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S); 1747 if (num_msi < HNS3_MIN_VECTOR_NUM) { 1748 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)", 1749 num_msi, HNS3_MIN_VECTOR_NUM); 1750 return -EINVAL; 1751 } 1752 1753 hw->num_msi = num_msi; 1754 1755 return 0; 1756 } 1757 1758 static int 1759 hns3vf_init_hardware(struct hns3_adapter *hns) 1760 { 1761 struct hns3_hw *hw = &hns->hw; 1762 uint16_t mtu = hw->data->mtu; 1763 int ret; 1764 1765 ret = hns3vf_set_promisc_mode(hw, true, false, false); 1766 if (ret) 1767 return ret; 1768 1769 ret = hns3vf_config_mtu(hw, mtu); 1770 if (ret) 1771 goto err_init_hardware; 1772 1773 ret = hns3vf_vlan_filter_configure(hns, 0, 1); 1774 if (ret) { 1775 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret); 1776 goto err_init_hardware; 1777 } 1778 1779 ret = hns3_config_gro(hw, false); 1780 if (ret) { 1781 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 1782 goto err_init_hardware; 1783 } 1784 1785 /* 1786 * In the initialization clearing the all hardware mapping relationship 1787 * configurations between queues and interrupt vectors is needed, so 1788 * some error caused by the residual configurations, such as the 1789 * unexpected interrupt, can be avoid. 1790 */ 1791 ret = hns3vf_init_ring_with_vector(hw); 1792 if (ret) { 1793 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 1794 goto err_init_hardware; 1795 } 1796 1797 ret = hns3vf_set_alive(hw, true); 1798 if (ret) { 1799 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret); 1800 goto err_init_hardware; 1801 } 1802 1803 return 0; 1804 1805 err_init_hardware: 1806 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1807 return ret; 1808 } 1809 1810 static int 1811 hns3vf_clear_vport_list(struct hns3_hw *hw) 1812 { 1813 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL, 1814 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false, 1815 NULL, 0); 1816 } 1817 1818 static int 1819 hns3vf_init_vf(struct rte_eth_dev *eth_dev) 1820 { 1821 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1822 struct hns3_adapter *hns = eth_dev->data->dev_private; 1823 struct hns3_hw *hw = &hns->hw; 1824 int ret; 1825 1826 PMD_INIT_FUNC_TRACE(); 1827 1828 /* Get hardware io base address from pcie BAR2 IO space */ 1829 hw->io_base = pci_dev->mem_resource[2].addr; 1830 1831 /* Firmware command queue initialize */ 1832 ret = hns3_cmd_init_queue(hw); 1833 if (ret) { 1834 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 1835 goto err_cmd_init_queue; 1836 } 1837 1838 /* Firmware command initialize */ 1839 ret = hns3_cmd_init(hw); 1840 if (ret) { 1841 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 1842 goto err_cmd_init; 1843 } 1844 1845 /* Get VF resource */ 1846 ret = hns3_query_vf_resource(hw); 1847 if (ret) 1848 goto err_cmd_init; 1849 1850 rte_spinlock_init(&hw->mbx_resp.lock); 1851 1852 hns3vf_clear_event_cause(hw, 0); 1853 1854 ret = rte_intr_callback_register(&pci_dev->intr_handle, 1855 hns3vf_interrupt_handler, eth_dev); 1856 if (ret) { 1857 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 1858 goto err_intr_callback_register; 1859 } 1860 1861 /* Enable interrupt */ 1862 rte_intr_enable(&pci_dev->intr_handle); 1863 hns3vf_enable_irq0(hw); 1864 1865 /* Get configuration from PF */ 1866 ret = hns3vf_get_configuration(hw); 1867 if (ret) { 1868 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 1869 goto err_get_config; 1870 } 1871 1872 ret = hns3_tqp_stats_init(hw); 1873 if (ret) 1874 goto err_get_config; 1875 1876 /* Hardware statistics of imissed registers cleared. */ 1877 ret = hns3_update_imissed_stats(hw, true); 1878 if (ret) { 1879 hns3_err(hw, "clear imissed stats failed, ret = %d", ret); 1880 goto err_set_tc_queue; 1881 } 1882 1883 ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); 1884 if (ret) { 1885 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); 1886 goto err_set_tc_queue; 1887 } 1888 1889 ret = hns3vf_clear_vport_list(hw); 1890 if (ret) { 1891 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret); 1892 goto err_set_tc_queue; 1893 } 1894 1895 ret = hns3vf_init_hardware(hns); 1896 if (ret) 1897 goto err_set_tc_queue; 1898 1899 hns3_rss_set_default_args(hw); 1900 1901 return 0; 1902 1903 err_set_tc_queue: 1904 hns3_tqp_stats_uninit(hw); 1905 1906 err_get_config: 1907 hns3vf_disable_irq0(hw); 1908 rte_intr_disable(&pci_dev->intr_handle); 1909 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 1910 eth_dev); 1911 err_intr_callback_register: 1912 err_cmd_init: 1913 hns3_cmd_uninit(hw); 1914 hns3_cmd_destroy_queue(hw); 1915 err_cmd_init_queue: 1916 hw->io_base = NULL; 1917 1918 return ret; 1919 } 1920 1921 static void 1922 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev) 1923 { 1924 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1925 struct hns3_adapter *hns = eth_dev->data->dev_private; 1926 struct hns3_hw *hw = &hns->hw; 1927 1928 PMD_INIT_FUNC_TRACE(); 1929 1930 hns3_rss_uninit(hns); 1931 (void)hns3_config_gro(hw, false); 1932 (void)hns3vf_set_alive(hw, false); 1933 (void)hns3vf_set_promisc_mode(hw, false, false, false); 1934 hns3_tqp_stats_uninit(hw); 1935 hns3vf_disable_irq0(hw); 1936 rte_intr_disable(&pci_dev->intr_handle); 1937 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, 1938 eth_dev); 1939 hns3_cmd_uninit(hw); 1940 hns3_cmd_destroy_queue(hw); 1941 hw->io_base = NULL; 1942 } 1943 1944 static int 1945 hns3vf_do_stop(struct hns3_adapter *hns) 1946 { 1947 struct hns3_hw *hw = &hns->hw; 1948 int ret; 1949 1950 hw->mac.link_status = ETH_LINK_DOWN; 1951 1952 /* 1953 * The "hns3vf_do_stop" function will also be called by .stop_service to 1954 * prepare reset. At the time of global or IMP reset, the command cannot 1955 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 1956 * accessed during the reset process. So the mbuf can not be released 1957 * during reset and is required to be released after the reset is 1958 * completed. 1959 */ 1960 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 1961 hns3_dev_release_mbufs(hns); 1962 1963 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 1964 hns3vf_configure_mac_addr(hns, true); 1965 ret = hns3_reset_all_tqps(hns); 1966 if (ret) { 1967 hns3_err(hw, "failed to reset all queues ret = %d", 1968 ret); 1969 return ret; 1970 } 1971 } 1972 return 0; 1973 } 1974 1975 static void 1976 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev) 1977 { 1978 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1979 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1980 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1981 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 1982 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 1983 uint16_t q_id; 1984 1985 if (dev->data->dev_conf.intr_conf.rxq == 0) 1986 return; 1987 1988 /* unmap the ring with vector */ 1989 if (rte_intr_allow_others(intr_handle)) { 1990 vec = RTE_INTR_VEC_RXTX_OFFSET; 1991 base = RTE_INTR_VEC_RXTX_OFFSET; 1992 } 1993 if (rte_intr_dp_is_en(intr_handle)) { 1994 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 1995 (void)hns3vf_bind_ring_with_vector(hw, vec, false, 1996 HNS3_RING_TYPE_RX, 1997 q_id); 1998 if (vec < base + intr_handle->nb_efd - 1) 1999 vec++; 2000 } 2001 } 2002 /* Clean datapath event and queue/vec mapping */ 2003 rte_intr_efd_disable(intr_handle); 2004 if (intr_handle->intr_vec) { 2005 rte_free(intr_handle->intr_vec); 2006 intr_handle->intr_vec = NULL; 2007 } 2008 } 2009 2010 static int 2011 hns3vf_dev_stop(struct rte_eth_dev *dev) 2012 { 2013 struct hns3_adapter *hns = dev->data->dev_private; 2014 struct hns3_hw *hw = &hns->hw; 2015 2016 PMD_INIT_FUNC_TRACE(); 2017 dev->data->dev_started = 0; 2018 2019 hw->adapter_state = HNS3_NIC_STOPPING; 2020 hns3_set_rxtx_function(dev); 2021 rte_wmb(); 2022 /* Disable datapath on secondary process. */ 2023 hns3_mp_req_stop_rxtx(dev); 2024 /* Prevent crashes when queues are still in use. */ 2025 rte_delay_ms(hw->tqps_num); 2026 2027 rte_spinlock_lock(&hw->lock); 2028 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 2029 hns3_stop_tqps(hw); 2030 hns3vf_do_stop(hns); 2031 hns3vf_unmap_rx_interrupt(dev); 2032 hw->adapter_state = HNS3_NIC_CONFIGURED; 2033 } 2034 hns3_rx_scattered_reset(dev); 2035 rte_eal_alarm_cancel(hns3vf_service_handler, dev); 2036 rte_spinlock_unlock(&hw->lock); 2037 2038 return 0; 2039 } 2040 2041 static int 2042 hns3vf_dev_close(struct rte_eth_dev *eth_dev) 2043 { 2044 struct hns3_adapter *hns = eth_dev->data->dev_private; 2045 struct hns3_hw *hw = &hns->hw; 2046 int ret = 0; 2047 2048 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2049 rte_free(eth_dev->process_private); 2050 eth_dev->process_private = NULL; 2051 return 0; 2052 } 2053 2054 if (hw->adapter_state == HNS3_NIC_STARTED) 2055 ret = hns3vf_dev_stop(eth_dev); 2056 2057 hw->adapter_state = HNS3_NIC_CLOSING; 2058 hns3_reset_abort(hns); 2059 hw->adapter_state = HNS3_NIC_CLOSED; 2060 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev); 2061 hns3vf_configure_all_mc_mac_addr(hns, true); 2062 hns3vf_remove_all_vlan_table(hns); 2063 hns3vf_uninit_vf(eth_dev); 2064 hns3_free_all_queues(eth_dev); 2065 rte_free(hw->reset.wait_data); 2066 rte_free(eth_dev->process_private); 2067 eth_dev->process_private = NULL; 2068 hns3_mp_uninit_primary(); 2069 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 2070 2071 return ret; 2072 } 2073 2074 static int 2075 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2076 size_t fw_size) 2077 { 2078 struct hns3_adapter *hns = eth_dev->data->dev_private; 2079 struct hns3_hw *hw = &hns->hw; 2080 uint32_t version = hw->fw_version; 2081 int ret; 2082 2083 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2084 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2085 HNS3_FW_VERSION_BYTE3_S), 2086 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2087 HNS3_FW_VERSION_BYTE2_S), 2088 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2089 HNS3_FW_VERSION_BYTE1_S), 2090 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2091 HNS3_FW_VERSION_BYTE0_S)); 2092 ret += 1; /* add the size of '\0' */ 2093 if (fw_size < (uint32_t)ret) 2094 return ret; 2095 else 2096 return 0; 2097 } 2098 2099 static int 2100 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, 2101 __rte_unused int wait_to_complete) 2102 { 2103 struct hns3_adapter *hns = eth_dev->data->dev_private; 2104 struct hns3_hw *hw = &hns->hw; 2105 struct hns3_mac *mac = &hw->mac; 2106 struct rte_eth_link new_link; 2107 2108 memset(&new_link, 0, sizeof(new_link)); 2109 switch (mac->link_speed) { 2110 case ETH_SPEED_NUM_10M: 2111 case ETH_SPEED_NUM_100M: 2112 case ETH_SPEED_NUM_1G: 2113 case ETH_SPEED_NUM_10G: 2114 case ETH_SPEED_NUM_25G: 2115 case ETH_SPEED_NUM_40G: 2116 case ETH_SPEED_NUM_50G: 2117 case ETH_SPEED_NUM_100G: 2118 case ETH_SPEED_NUM_200G: 2119 new_link.link_speed = mac->link_speed; 2120 break; 2121 default: 2122 if (mac->link_status) 2123 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN; 2124 else 2125 new_link.link_speed = ETH_SPEED_NUM_NONE; 2126 break; 2127 } 2128 2129 new_link.link_duplex = mac->link_duplex; 2130 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2131 new_link.link_autoneg = 2132 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2133 2134 return rte_eth_linkstatus_set(eth_dev, &new_link); 2135 } 2136 2137 static int 2138 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue) 2139 { 2140 struct hns3_hw *hw = &hns->hw; 2141 uint16_t nb_rx_q = hw->data->nb_rx_queues; 2142 uint16_t nb_tx_q = hw->data->nb_tx_queues; 2143 int ret; 2144 2145 ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q); 2146 if (ret) 2147 return ret; 2148 2149 hns3_enable_rxd_adv_layout(hw); 2150 2151 ret = hns3_init_queues(hns, reset_queue); 2152 if (ret) 2153 hns3_err(hw, "failed to init queues, ret = %d.", ret); 2154 2155 return ret; 2156 } 2157 2158 static int 2159 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) 2160 { 2161 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2162 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2163 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2164 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 2165 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 2166 uint32_t intr_vector; 2167 uint16_t q_id; 2168 int ret; 2169 2170 /* 2171 * hns3 needs a separate interrupt to be used as event interrupt which 2172 * could not be shared with task queue pair, so KERNEL drivers need 2173 * support multiple interrupt vectors. 2174 */ 2175 if (dev->data->dev_conf.intr_conf.rxq == 0 || 2176 !rte_intr_cap_multiple(intr_handle)) 2177 return 0; 2178 2179 rte_intr_disable(intr_handle); 2180 intr_vector = hw->used_rx_queues; 2181 /* It creates event fd for each intr vector when MSIX is used */ 2182 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2183 return -EINVAL; 2184 2185 if (intr_handle->intr_vec == NULL) { 2186 intr_handle->intr_vec = 2187 rte_zmalloc("intr_vec", 2188 hw->used_rx_queues * sizeof(int), 0); 2189 if (intr_handle->intr_vec == NULL) { 2190 hns3_err(hw, "Failed to allocate %u rx_queues" 2191 " intr_vec", hw->used_rx_queues); 2192 ret = -ENOMEM; 2193 goto vf_alloc_intr_vec_error; 2194 } 2195 } 2196 2197 if (rte_intr_allow_others(intr_handle)) { 2198 vec = RTE_INTR_VEC_RXTX_OFFSET; 2199 base = RTE_INTR_VEC_RXTX_OFFSET; 2200 } 2201 2202 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2203 ret = hns3vf_bind_ring_with_vector(hw, vec, true, 2204 HNS3_RING_TYPE_RX, q_id); 2205 if (ret) 2206 goto vf_bind_vector_error; 2207 intr_handle->intr_vec[q_id] = vec; 2208 /* 2209 * If there are not enough efds (e.g. not enough interrupt), 2210 * remaining queues will be bond to the last interrupt. 2211 */ 2212 if (vec < base + intr_handle->nb_efd - 1) 2213 vec++; 2214 } 2215 rte_intr_enable(intr_handle); 2216 return 0; 2217 2218 vf_bind_vector_error: 2219 free(intr_handle->intr_vec); 2220 intr_handle->intr_vec = NULL; 2221 vf_alloc_intr_vec_error: 2222 rte_intr_efd_disable(intr_handle); 2223 return ret; 2224 } 2225 2226 static int 2227 hns3vf_restore_rx_interrupt(struct hns3_hw *hw) 2228 { 2229 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 2230 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2231 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2232 uint16_t q_id; 2233 int ret; 2234 2235 if (dev->data->dev_conf.intr_conf.rxq == 0) 2236 return 0; 2237 2238 if (rte_intr_dp_is_en(intr_handle)) { 2239 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 2240 ret = hns3vf_bind_ring_with_vector(hw, 2241 intr_handle->intr_vec[q_id], true, 2242 HNS3_RING_TYPE_RX, q_id); 2243 if (ret) 2244 return ret; 2245 } 2246 } 2247 2248 return 0; 2249 } 2250 2251 static void 2252 hns3vf_restore_filter(struct rte_eth_dev *dev) 2253 { 2254 hns3_restore_rss_filter(dev); 2255 } 2256 2257 static int 2258 hns3vf_dev_start(struct rte_eth_dev *dev) 2259 { 2260 struct hns3_adapter *hns = dev->data->dev_private; 2261 struct hns3_hw *hw = &hns->hw; 2262 int ret; 2263 2264 PMD_INIT_FUNC_TRACE(); 2265 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 2266 return -EBUSY; 2267 2268 rte_spinlock_lock(&hw->lock); 2269 hw->adapter_state = HNS3_NIC_STARTING; 2270 ret = hns3vf_do_start(hns, true); 2271 if (ret) { 2272 hw->adapter_state = HNS3_NIC_CONFIGURED; 2273 rte_spinlock_unlock(&hw->lock); 2274 return ret; 2275 } 2276 ret = hns3vf_map_rx_interrupt(dev); 2277 if (ret) 2278 goto map_rx_inter_err; 2279 2280 /* 2281 * There are three register used to control the status of a TQP 2282 * (contains a pair of Tx queue and Rx queue) in the new version network 2283 * engine. One is used to control the enabling of Tx queue, the other is 2284 * used to control the enabling of Rx queue, and the last is the master 2285 * switch used to control the enabling of the tqp. The Tx register and 2286 * TQP register must be enabled at the same time to enable a Tx queue. 2287 * The same applies to the Rx queue. For the older network enginem, this 2288 * function only refresh the enabled flag, and it is used to update the 2289 * status of queue in the dpdk framework. 2290 */ 2291 ret = hns3_start_all_txqs(dev); 2292 if (ret) 2293 goto map_rx_inter_err; 2294 2295 ret = hns3_start_all_rxqs(dev); 2296 if (ret) 2297 goto start_all_rxqs_fail; 2298 2299 hw->adapter_state = HNS3_NIC_STARTED; 2300 rte_spinlock_unlock(&hw->lock); 2301 2302 hns3_rx_scattered_calc(dev); 2303 hns3_set_rxtx_function(dev); 2304 hns3_mp_req_start_rxtx(dev); 2305 hns3vf_service_handler(dev); 2306 2307 hns3vf_restore_filter(dev); 2308 2309 /* Enable interrupt of all rx queues before enabling queues */ 2310 hns3_dev_all_rx_queue_intr_enable(hw, true); 2311 2312 /* 2313 * After finished the initialization, start all tqps to receive/transmit 2314 * packets and refresh all queue status. 2315 */ 2316 hns3_start_tqps(hw); 2317 2318 return ret; 2319 2320 start_all_rxqs_fail: 2321 hns3_stop_all_txqs(dev); 2322 map_rx_inter_err: 2323 (void)hns3vf_do_stop(hns); 2324 hw->adapter_state = HNS3_NIC_CONFIGURED; 2325 rte_spinlock_unlock(&hw->lock); 2326 2327 return ret; 2328 } 2329 2330 static bool 2331 is_vf_reset_done(struct hns3_hw *hw) 2332 { 2333 #define HNS3_FUN_RST_ING_BITS \ 2334 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \ 2335 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \ 2336 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \ 2337 BIT(HNS3_VECTOR0_FUNCRESET_INT_B)) 2338 2339 uint32_t val; 2340 2341 if (hw->reset.level == HNS3_VF_RESET) { 2342 val = hns3_read_dev(hw, HNS3_VF_RST_ING); 2343 if (val & HNS3_VF_RST_ING_BIT) 2344 return false; 2345 } else { 2346 val = hns3_read_dev(hw, HNS3_FUN_RST_ING); 2347 if (val & HNS3_FUN_RST_ING_BITS) 2348 return false; 2349 } 2350 return true; 2351 } 2352 2353 bool 2354 hns3vf_is_reset_pending(struct hns3_adapter *hns) 2355 { 2356 struct hns3_hw *hw = &hns->hw; 2357 enum hns3_reset_level reset; 2358 2359 /* 2360 * According to the protocol of PCIe, FLR to a PF device resets the PF 2361 * state as well as the SR-IOV extended capability including VF Enable 2362 * which means that VFs no longer exist. 2363 * 2364 * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device 2365 * is in FLR stage, the register state of VF device is not reliable, 2366 * so register states detection can not be carried out. In this case, 2367 * we just ignore the register states and return false to indicate that 2368 * there are no other reset states that need to be processed by driver. 2369 */ 2370 if (hw->reset.level == HNS3_VF_FULL_RESET) 2371 return false; 2372 2373 /* Check the registers to confirm whether there is reset pending */ 2374 hns3vf_check_event_cause(hns, NULL); 2375 reset = hns3vf_get_reset_level(hw, &hw->reset.pending); 2376 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 2377 hns3_warn(hw, "High level reset %d is pending", reset); 2378 return true; 2379 } 2380 return false; 2381 } 2382 2383 static int 2384 hns3vf_wait_hardware_ready(struct hns3_adapter *hns) 2385 { 2386 struct hns3_hw *hw = &hns->hw; 2387 struct hns3_wait_data *wait_data = hw->reset.wait_data; 2388 struct timeval tv; 2389 2390 if (wait_data->result == HNS3_WAIT_SUCCESS) { 2391 /* 2392 * After vf reset is ready, the PF may not have completed 2393 * the reset processing. The vf sending mbox to PF may fail 2394 * during the pf reset, so it is better to add extra delay. 2395 */ 2396 if (hw->reset.level == HNS3_VF_FUNC_RESET || 2397 hw->reset.level == HNS3_FLR_RESET) 2398 return 0; 2399 /* Reset retry process, no need to add extra delay. */ 2400 if (hw->reset.attempts) 2401 return 0; 2402 if (wait_data->check_completion == NULL) 2403 return 0; 2404 2405 wait_data->check_completion = NULL; 2406 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC; 2407 wait_data->count = 1; 2408 wait_data->result = HNS3_WAIT_REQUEST; 2409 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, 2410 wait_data); 2411 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); 2412 return -EAGAIN; 2413 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 2414 gettimeofday(&tv, NULL); 2415 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 2416 tv.tv_sec, tv.tv_usec); 2417 return -ETIME; 2418 } else if (wait_data->result == HNS3_WAIT_REQUEST) 2419 return -EAGAIN; 2420 2421 wait_data->hns = hns; 2422 wait_data->check_completion = is_vf_reset_done; 2423 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT * 2424 HNS3VF_RESET_WAIT_MS + get_timeofday_ms(); 2425 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC; 2426 wait_data->count = HNS3VF_RESET_WAIT_CNT; 2427 wait_data->result = HNS3_WAIT_REQUEST; 2428 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 2429 return -EAGAIN; 2430 } 2431 2432 static int 2433 hns3vf_prepare_reset(struct hns3_adapter *hns) 2434 { 2435 struct hns3_hw *hw = &hns->hw; 2436 int ret; 2437 2438 if (hw->reset.level == HNS3_VF_FUNC_RESET) { 2439 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL, 2440 0, true, NULL, 0); 2441 if (ret) 2442 return ret; 2443 } 2444 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 2445 2446 return 0; 2447 } 2448 2449 static int 2450 hns3vf_stop_service(struct hns3_adapter *hns) 2451 { 2452 struct hns3_hw *hw = &hns->hw; 2453 struct rte_eth_dev *eth_dev; 2454 2455 eth_dev = &rte_eth_devices[hw->data->port_id]; 2456 if (hw->adapter_state == HNS3_NIC_STARTED) { 2457 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev); 2458 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed, 2459 hw->mac.link_duplex); 2460 } 2461 hw->mac.link_status = ETH_LINK_DOWN; 2462 2463 hns3_set_rxtx_function(eth_dev); 2464 rte_wmb(); 2465 /* Disable datapath on secondary process. */ 2466 hns3_mp_req_stop_rxtx(eth_dev); 2467 rte_delay_ms(hw->tqps_num); 2468 2469 rte_spinlock_lock(&hw->lock); 2470 if (hw->adapter_state == HNS3_NIC_STARTED || 2471 hw->adapter_state == HNS3_NIC_STOPPING) { 2472 hns3_enable_all_queues(hw, false); 2473 hns3vf_do_stop(hns); 2474 hw->reset.mbuf_deferred_free = true; 2475 } else 2476 hw->reset.mbuf_deferred_free = false; 2477 2478 /* 2479 * It is cumbersome for hardware to pick-and-choose entries for deletion 2480 * from table space. Hence, for function reset software intervention is 2481 * required to delete the entries. 2482 */ 2483 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 2484 hns3vf_configure_all_mc_mac_addr(hns, true); 2485 rte_spinlock_unlock(&hw->lock); 2486 2487 return 0; 2488 } 2489 2490 static int 2491 hns3vf_start_service(struct hns3_adapter *hns) 2492 { 2493 struct hns3_hw *hw = &hns->hw; 2494 struct rte_eth_dev *eth_dev; 2495 2496 eth_dev = &rte_eth_devices[hw->data->port_id]; 2497 hns3_set_rxtx_function(eth_dev); 2498 hns3_mp_req_start_rxtx(eth_dev); 2499 if (hw->adapter_state == HNS3_NIC_STARTED) { 2500 hns3vf_service_handler(eth_dev); 2501 2502 /* Enable interrupt of all rx queues before enabling queues */ 2503 hns3_dev_all_rx_queue_intr_enable(hw, true); 2504 /* 2505 * Enable state of each rxq and txq will be recovered after 2506 * reset, so we need to restore them before enable all tqps; 2507 */ 2508 hns3_restore_tqp_enable_state(hw); 2509 /* 2510 * When finished the initialization, enable queues to receive 2511 * and transmit packets. 2512 */ 2513 hns3_enable_all_queues(hw, true); 2514 } 2515 2516 return 0; 2517 } 2518 2519 static int 2520 hns3vf_check_default_mac_change(struct hns3_hw *hw) 2521 { 2522 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2523 struct rte_ether_addr *hw_mac; 2524 int ret; 2525 2526 /* 2527 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2528 * on the host by "ip link set ..." command. If the hns3 PF kernel 2529 * ethdev driver sets the MAC address for VF device after the 2530 * initialization of the related VF device, the PF driver will notify 2531 * VF driver to reset VF device to make the new MAC address effective 2532 * immediately. The hns3 VF PMD driver should check whether the MAC 2533 * address has been changed by the PF kernel ethdev driver, if changed 2534 * VF driver should configure hardware using the new MAC address in the 2535 * recovering hardware configuration stage of the reset process. 2536 */ 2537 ret = hns3vf_get_host_mac_addr(hw); 2538 if (ret) 2539 return ret; 2540 2541 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr; 2542 ret = rte_is_zero_ether_addr(hw_mac); 2543 if (ret) { 2544 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac); 2545 } else { 2546 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac); 2547 if (!ret) { 2548 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]); 2549 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2550 &hw->data->mac_addrs[0]); 2551 hns3_warn(hw, "Default MAC address has been changed to:" 2552 " %s by the host PF kernel ethdev driver", 2553 mac_str); 2554 } 2555 } 2556 2557 return 0; 2558 } 2559 2560 static int 2561 hns3vf_restore_conf(struct hns3_adapter *hns) 2562 { 2563 struct hns3_hw *hw = &hns->hw; 2564 int ret; 2565 2566 ret = hns3vf_check_default_mac_change(hw); 2567 if (ret) 2568 return ret; 2569 2570 ret = hns3vf_configure_mac_addr(hns, false); 2571 if (ret) 2572 return ret; 2573 2574 ret = hns3vf_configure_all_mc_mac_addr(hns, false); 2575 if (ret) 2576 goto err_mc_mac; 2577 2578 ret = hns3vf_restore_promisc(hns); 2579 if (ret) 2580 goto err_vlan_table; 2581 2582 ret = hns3vf_restore_vlan_conf(hns); 2583 if (ret) 2584 goto err_vlan_table; 2585 2586 ret = hns3vf_get_port_base_vlan_filter_state(hw); 2587 if (ret) 2588 goto err_vlan_table; 2589 2590 ret = hns3vf_restore_rx_interrupt(hw); 2591 if (ret) 2592 goto err_vlan_table; 2593 2594 ret = hns3_restore_gro_conf(hw); 2595 if (ret) 2596 goto err_vlan_table; 2597 2598 if (hw->adapter_state == HNS3_NIC_STARTED) { 2599 ret = hns3vf_do_start(hns, false); 2600 if (ret) 2601 goto err_vlan_table; 2602 hns3_info(hw, "hns3vf dev restart successful!"); 2603 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 2604 hw->adapter_state = HNS3_NIC_CONFIGURED; 2605 return 0; 2606 2607 err_vlan_table: 2608 hns3vf_configure_all_mc_mac_addr(hns, true); 2609 err_mc_mac: 2610 hns3vf_configure_mac_addr(hns, true); 2611 return ret; 2612 } 2613 2614 static enum hns3_reset_level 2615 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels) 2616 { 2617 enum hns3_reset_level reset_level; 2618 2619 /* return the highest priority reset level amongst all */ 2620 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels)) 2621 reset_level = HNS3_VF_RESET; 2622 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels)) 2623 reset_level = HNS3_VF_FULL_RESET; 2624 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels)) 2625 reset_level = HNS3_VF_PF_FUNC_RESET; 2626 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels)) 2627 reset_level = HNS3_VF_FUNC_RESET; 2628 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 2629 reset_level = HNS3_FLR_RESET; 2630 else 2631 reset_level = HNS3_NONE_RESET; 2632 2633 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 2634 return HNS3_NONE_RESET; 2635 2636 return reset_level; 2637 } 2638 2639 static void 2640 hns3vf_reset_service(void *param) 2641 { 2642 struct hns3_adapter *hns = (struct hns3_adapter *)param; 2643 struct hns3_hw *hw = &hns->hw; 2644 enum hns3_reset_level reset_level; 2645 struct timeval tv_delta; 2646 struct timeval tv_start; 2647 struct timeval tv; 2648 uint64_t msec; 2649 2650 /* 2651 * The interrupt is not triggered within the delay time. 2652 * The interrupt may have been lost. It is necessary to handle 2653 * the interrupt to recover from the error. 2654 */ 2655 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2656 SCHEDULE_DEFERRED) { 2657 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 2658 __ATOMIC_RELAXED); 2659 hns3_err(hw, "Handling interrupts in delayed tasks"); 2660 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 2661 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2662 if (reset_level == HNS3_NONE_RESET) { 2663 hns3_err(hw, "No reset level is set, try global reset"); 2664 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); 2665 } 2666 } 2667 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 2668 2669 /* 2670 * Hardware reset has been notified, we now have to poll & check if 2671 * hardware has actually completed the reset sequence. 2672 */ 2673 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); 2674 if (reset_level != HNS3_NONE_RESET) { 2675 gettimeofday(&tv_start, NULL); 2676 hns3_reset_process(hns, reset_level); 2677 gettimeofday(&tv, NULL); 2678 timersub(&tv, &tv_start, &tv_delta); 2679 msec = tv_delta.tv_sec * MSEC_PER_SEC + 2680 tv_delta.tv_usec / USEC_PER_MSEC; 2681 if (msec > HNS3_RESET_PROCESS_MS) 2682 hns3_err(hw, "%d handle long time delta %" PRIx64 2683 " ms time=%ld.%.6ld", 2684 hw->reset.level, msec, tv.tv_sec, tv.tv_usec); 2685 } 2686 } 2687 2688 static int 2689 hns3vf_reinit_dev(struct hns3_adapter *hns) 2690 { 2691 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id]; 2692 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2693 struct hns3_hw *hw = &hns->hw; 2694 int ret; 2695 2696 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2697 rte_intr_disable(&pci_dev->intr_handle); 2698 ret = hns3vf_set_bus_master(pci_dev, true); 2699 if (ret < 0) { 2700 hns3_err(hw, "failed to set pci bus, ret = %d", ret); 2701 return ret; 2702 } 2703 } 2704 2705 /* Firmware command initialize */ 2706 ret = hns3_cmd_init(hw); 2707 if (ret) { 2708 hns3_err(hw, "Failed to init cmd: %d", ret); 2709 return ret; 2710 } 2711 2712 if (hw->reset.level == HNS3_VF_FULL_RESET) { 2713 /* 2714 * UIO enables msix by writing the pcie configuration space 2715 * vfio_pci enables msix in rte_intr_enable. 2716 */ 2717 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO || 2718 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) { 2719 if (hns3vf_enable_msix(pci_dev, true)) 2720 hns3_err(hw, "Failed to enable msix"); 2721 } 2722 2723 rte_intr_enable(&pci_dev->intr_handle); 2724 } 2725 2726 ret = hns3_reset_all_tqps(hns); 2727 if (ret) { 2728 hns3_err(hw, "Failed to reset all queues: %d", ret); 2729 return ret; 2730 } 2731 2732 ret = hns3vf_init_hardware(hns); 2733 if (ret) { 2734 hns3_err(hw, "Failed to init hardware: %d", ret); 2735 return ret; 2736 } 2737 2738 return 0; 2739 } 2740 2741 static const struct eth_dev_ops hns3vf_eth_dev_ops = { 2742 .dev_configure = hns3vf_dev_configure, 2743 .dev_start = hns3vf_dev_start, 2744 .dev_stop = hns3vf_dev_stop, 2745 .dev_close = hns3vf_dev_close, 2746 .mtu_set = hns3vf_dev_mtu_set, 2747 .promiscuous_enable = hns3vf_dev_promiscuous_enable, 2748 .promiscuous_disable = hns3vf_dev_promiscuous_disable, 2749 .allmulticast_enable = hns3vf_dev_allmulticast_enable, 2750 .allmulticast_disable = hns3vf_dev_allmulticast_disable, 2751 .stats_get = hns3_stats_get, 2752 .stats_reset = hns3_stats_reset, 2753 .xstats_get = hns3_dev_xstats_get, 2754 .xstats_get_names = hns3_dev_xstats_get_names, 2755 .xstats_reset = hns3_dev_xstats_reset, 2756 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 2757 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 2758 .dev_infos_get = hns3vf_dev_infos_get, 2759 .fw_version_get = hns3vf_fw_version_get, 2760 .rx_queue_setup = hns3_rx_queue_setup, 2761 .tx_queue_setup = hns3_tx_queue_setup, 2762 .rx_queue_release = hns3_dev_rx_queue_release, 2763 .tx_queue_release = hns3_dev_tx_queue_release, 2764 .rx_queue_start = hns3_dev_rx_queue_start, 2765 .rx_queue_stop = hns3_dev_rx_queue_stop, 2766 .tx_queue_start = hns3_dev_tx_queue_start, 2767 .tx_queue_stop = hns3_dev_tx_queue_stop, 2768 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 2769 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 2770 .rxq_info_get = hns3_rxq_info_get, 2771 .txq_info_get = hns3_txq_info_get, 2772 .rx_burst_mode_get = hns3_rx_burst_mode_get, 2773 .tx_burst_mode_get = hns3_tx_burst_mode_get, 2774 .mac_addr_add = hns3vf_add_mac_addr, 2775 .mac_addr_remove = hns3vf_remove_mac_addr, 2776 .mac_addr_set = hns3vf_set_default_mac_addr, 2777 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list, 2778 .link_update = hns3vf_dev_link_update, 2779 .rss_hash_update = hns3_dev_rss_hash_update, 2780 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 2781 .reta_update = hns3_dev_rss_reta_update, 2782 .reta_query = hns3_dev_rss_reta_query, 2783 .flow_ops_get = hns3_dev_flow_ops_get, 2784 .vlan_filter_set = hns3vf_vlan_filter_set, 2785 .vlan_offload_set = hns3vf_vlan_offload_set, 2786 .get_reg = hns3_get_regs, 2787 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 2788 .tx_done_cleanup = hns3_tx_done_cleanup, 2789 }; 2790 2791 static const struct hns3_reset_ops hns3vf_reset_ops = { 2792 .reset_service = hns3vf_reset_service, 2793 .stop_service = hns3vf_stop_service, 2794 .prepare_reset = hns3vf_prepare_reset, 2795 .wait_hardware_ready = hns3vf_wait_hardware_ready, 2796 .reinit_dev = hns3vf_reinit_dev, 2797 .restore_conf = hns3vf_restore_conf, 2798 .start_service = hns3vf_start_service, 2799 }; 2800 2801 static int 2802 hns3vf_dev_init(struct rte_eth_dev *eth_dev) 2803 { 2804 struct hns3_adapter *hns = eth_dev->data->dev_private; 2805 struct hns3_hw *hw = &hns->hw; 2806 int ret; 2807 2808 PMD_INIT_FUNC_TRACE(); 2809 2810 eth_dev->process_private = (struct hns3_process_private *) 2811 rte_zmalloc_socket("hns3_filter_list", 2812 sizeof(struct hns3_process_private), 2813 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 2814 if (eth_dev->process_private == NULL) { 2815 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 2816 return -ENOMEM; 2817 } 2818 2819 /* initialize flow filter lists */ 2820 hns3_filterlist_init(eth_dev); 2821 2822 hns3_set_rxtx_function(eth_dev); 2823 eth_dev->dev_ops = &hns3vf_eth_dev_ops; 2824 eth_dev->rx_queue_count = hns3_rx_queue_count; 2825 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2826 ret = hns3_mp_init_secondary(); 2827 if (ret) { 2828 PMD_INIT_LOG(ERR, "Failed to init for secondary " 2829 "process, ret = %d", ret); 2830 goto err_mp_init_secondary; 2831 } 2832 2833 hw->secondary_cnt++; 2834 return 0; 2835 } 2836 2837 ret = hns3_mp_init_primary(); 2838 if (ret) { 2839 PMD_INIT_LOG(ERR, 2840 "Failed to init for primary process, ret = %d", 2841 ret); 2842 goto err_mp_init_primary; 2843 } 2844 2845 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 2846 hns->is_vf = true; 2847 hw->data = eth_dev->data; 2848 hns3_parse_devargs(eth_dev); 2849 2850 ret = hns3_reset_init(hw); 2851 if (ret) 2852 goto err_init_reset; 2853 hw->reset.ops = &hns3vf_reset_ops; 2854 2855 ret = hns3vf_init_vf(eth_dev); 2856 if (ret) { 2857 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret); 2858 goto err_init_vf; 2859 } 2860 2861 /* Allocate memory for storing MAC addresses */ 2862 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac", 2863 sizeof(struct rte_ether_addr) * 2864 HNS3_VF_UC_MACADDR_NUM, 0); 2865 if (eth_dev->data->mac_addrs == NULL) { 2866 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 2867 "to store MAC addresses", 2868 sizeof(struct rte_ether_addr) * 2869 HNS3_VF_UC_MACADDR_NUM); 2870 ret = -ENOMEM; 2871 goto err_rte_zmalloc; 2872 } 2873 2874 /* 2875 * The hns3 PF ethdev driver in kernel support setting VF MAC address 2876 * on the host by "ip link set ..." command. To avoid some incorrect 2877 * scenes, for example, hns3 VF PMD driver fails to receive and send 2878 * packets after user configure the MAC address by using the 2879 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC 2880 * address strategy as the hns3 kernel ethdev driver in the 2881 * initialization. If user configure a MAC address by the ip command 2882 * for VF device, then hns3 VF PMD driver will start with it, otherwise 2883 * start with a random MAC address in the initialization. 2884 */ 2885 if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr)) 2886 rte_eth_random_addr(hw->mac.mac_addr); 2887 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 2888 ð_dev->data->mac_addrs[0]); 2889 2890 hw->adapter_state = HNS3_NIC_INITIALIZED; 2891 2892 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2893 SCHEDULE_PENDING) { 2894 hns3_err(hw, "Reschedule reset service after dev_init"); 2895 hns3_schedule_reset(hns); 2896 } else { 2897 /* IMP will wait ready flag before reset */ 2898 hns3_notify_reset_ready(hw, false); 2899 } 2900 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler, 2901 eth_dev); 2902 return 0; 2903 2904 err_rte_zmalloc: 2905 hns3vf_uninit_vf(eth_dev); 2906 2907 err_init_vf: 2908 rte_free(hw->reset.wait_data); 2909 2910 err_init_reset: 2911 hns3_mp_uninit_primary(); 2912 2913 err_mp_init_primary: 2914 err_mp_init_secondary: 2915 eth_dev->dev_ops = NULL; 2916 eth_dev->rx_pkt_burst = NULL; 2917 eth_dev->rx_descriptor_status = NULL; 2918 eth_dev->tx_pkt_burst = NULL; 2919 eth_dev->tx_pkt_prepare = NULL; 2920 eth_dev->tx_descriptor_status = NULL; 2921 rte_free(eth_dev->process_private); 2922 eth_dev->process_private = NULL; 2923 2924 return ret; 2925 } 2926 2927 static int 2928 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev) 2929 { 2930 struct hns3_adapter *hns = eth_dev->data->dev_private; 2931 struct hns3_hw *hw = &hns->hw; 2932 2933 PMD_INIT_FUNC_TRACE(); 2934 2935 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2936 rte_free(eth_dev->process_private); 2937 eth_dev->process_private = NULL; 2938 return 0; 2939 } 2940 2941 if (hw->adapter_state < HNS3_NIC_CLOSING) 2942 hns3vf_dev_close(eth_dev); 2943 2944 hw->adapter_state = HNS3_NIC_REMOVED; 2945 return 0; 2946 } 2947 2948 static int 2949 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2950 struct rte_pci_device *pci_dev) 2951 { 2952 return rte_eth_dev_pci_generic_probe(pci_dev, 2953 sizeof(struct hns3_adapter), 2954 hns3vf_dev_init); 2955 } 2956 2957 static int 2958 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev) 2959 { 2960 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit); 2961 } 2962 2963 static const struct rte_pci_id pci_id_hns3vf_map[] = { 2964 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) }, 2965 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) }, 2966 { .vendor_id = 0, }, /* sentinel */ 2967 }; 2968 2969 static struct rte_pci_driver rte_hns3vf_pmd = { 2970 .id_table = pci_id_hns3vf_map, 2971 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2972 .probe = eth_hns3vf_pci_probe, 2973 .remove = eth_hns3vf_pci_remove, 2974 }; 2975 2976 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); 2977 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); 2978 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); 2979 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf, 2980 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 2981 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); 2982