1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <ethdev_driver.h> 10 #include <rte_byteorder.h> 11 #include <rte_io.h> 12 #include <rte_spinlock.h> 13 14 #include "hns3_cmd.h" 15 #include "hns3_mbx.h" 16 #include "hns3_rss.h" 17 #include "hns3_fdir.h" 18 #include "hns3_stats.h" 19 #include "hns3_tm.h" 20 21 /* Vendor ID */ 22 #define PCI_VENDOR_ID_HUAWEI 0x19e5 23 24 /* Device IDs */ 25 #define HNS3_DEV_ID_GE 0xA220 26 #define HNS3_DEV_ID_25GE 0xA221 27 #define HNS3_DEV_ID_25GE_RDMA 0xA222 28 #define HNS3_DEV_ID_50GE_RDMA 0xA224 29 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 30 #define HNS3_DEV_ID_200G_RDMA 0xA228 31 #define HNS3_DEV_ID_100G_VF 0xA22E 32 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 33 34 /* PCI Config offsets */ 35 #define HNS3_PCI_REVISION_ID 0x08 36 #define HNS3_PCI_REVISION_ID_LEN 1 37 38 #define PCI_REVISION_ID_HIP08_B 0x21 39 #define PCI_REVISION_ID_HIP09_A 0x30 40 41 #define HNS3_PF_FUNC_ID 0 42 #define HNS3_1ST_VF_FUNC_ID 1 43 44 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 45 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 46 47 #define HNS3_UNLIMIT_PROMISC_MODE 0 48 #define HNS3_LIMIT_PROMISC_MODE 1 49 50 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0 51 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1 52 53 #define HNS3_UC_MACADDR_NUM 128 54 #define HNS3_VF_UC_MACADDR_NUM 48 55 #define HNS3_MC_MACADDR_NUM 128 56 57 #define HNS3_MAX_BD_SIZE 65535 58 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 59 #define HNS3_MAX_TSO_BD_PER_PKT 63 60 #define HNS3_MAX_FRAME_LEN 9728 61 #define HNS3_VLAN_TAG_SIZE 4 62 #define HNS3_DEFAULT_RX_BUF_LEN 2048 63 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 64 #define HNS3_MAX_TSO_HDR_SIZE 512 65 #define HNS3_MAX_TSO_HDR_BD_NUM 3 66 #define HNS3_MAX_LRO_SIZE 64512 67 68 #define HNS3_ETH_OVERHEAD \ 69 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 70 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 71 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 72 #define HNS3_DEFAULT_MTU 1500UL 73 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 74 #define HNS3_HIP08_MIN_TX_PKT_LEN 33 75 #define HNS3_HIP09_MIN_TX_PKT_LEN 9 76 77 #define HNS3_BITS_PER_BYTE 8 78 79 #define HNS3_4_TCS 4 80 #define HNS3_8_TCS 8 81 82 #define HNS3_MAX_PF_NUM 8 83 #define HNS3_UMV_TBL_SIZE 3072 84 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 85 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 86 87 #define HNS3_PF_CFG_BLOCK_SIZE 32 88 #define HNS3_PF_CFG_DESC_NUM \ 89 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 90 91 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 92 93 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 94 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 95 96 #define HNS3_QUIT_RESET_CNT 10 97 #define HNS3_QUIT_RESET_DELAY_MS 100 98 99 #define HNS3_POLL_RESPONE_MS 1 100 101 #define HNS3_MAX_USER_PRIO 8 102 #define HNS3_PG_NUM 4 103 enum hns3_fc_mode { 104 HNS3_FC_NONE, 105 HNS3_FC_RX_PAUSE, 106 HNS3_FC_TX_PAUSE, 107 HNS3_FC_FULL, 108 HNS3_FC_DEFAULT 109 }; 110 111 #define HNS3_SCH_MODE_SP 0 112 #define HNS3_SCH_MODE_DWRR 1 113 struct hns3_pg_info { 114 uint8_t pg_id; 115 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 116 uint8_t tc_bit_map; 117 uint32_t bw_limit; 118 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 119 }; 120 121 struct hns3_tc_info { 122 uint8_t tc_id; 123 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 124 uint8_t pgid; 125 uint32_t bw_limit; 126 uint8_t up_to_tc_map; /* user priority maping on the TC */ 127 }; 128 129 struct hns3_dcb_info { 130 uint8_t num_tc; 131 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 132 uint8_t pg_dwrr[HNS3_PG_NUM]; 133 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 134 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 135 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 136 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 137 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 138 }; 139 140 enum hns3_fc_status { 141 HNS3_FC_STATUS_NONE, 142 HNS3_FC_STATUS_MAC_PAUSE, 143 HNS3_FC_STATUS_PFC, 144 }; 145 146 struct hns3_tc_queue_info { 147 uint16_t tqp_offset; /* TQP offset from base TQP */ 148 uint16_t tqp_count; /* Total TQPs */ 149 uint8_t tc; /* TC index */ 150 bool enable; /* If this TC is enable or not */ 151 }; 152 153 struct hns3_cfg { 154 uint8_t vmdq_vport_num; 155 uint8_t tc_num; 156 uint16_t tqp_desc_num; 157 uint16_t rx_buf_len; 158 uint16_t rss_size_max; 159 uint8_t phy_addr; 160 uint8_t media_type; 161 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 162 uint8_t default_speed; 163 uint32_t numa_node_map; 164 uint8_t speed_ability; 165 uint16_t umv_space; 166 }; 167 168 struct hns3_set_link_speed_cfg { 169 uint32_t speed; 170 uint8_t duplex : 1; 171 uint8_t autoneg : 1; 172 }; 173 174 /* mac media type */ 175 enum hns3_media_type { 176 HNS3_MEDIA_TYPE_UNKNOWN, 177 HNS3_MEDIA_TYPE_FIBER, 178 HNS3_MEDIA_TYPE_COPPER, 179 HNS3_MEDIA_TYPE_BACKPLANE, 180 HNS3_MEDIA_TYPE_NONE, 181 }; 182 183 #define HNS3_DEFAULT_QUERY 0 184 #define HNS3_ACTIVE_QUERY 1 185 186 struct hns3_mac { 187 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 188 bool default_addr_setted; /* whether default addr(mac_addr) is set */ 189 uint8_t media_type; 190 uint8_t phy_addr; 191 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 192 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 193 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 194 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 195 /* 196 * Some firmware versions support only the SFP speed query. In addition 197 * to the SFP speed query, some firmware supports the query of the speed 198 * capability, auto-negotiation capability, and FEC mode, which can be 199 * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD. 200 * This field is used to record the SFP information query mode. 201 * Value range: 202 * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY 203 * 204 * - HNS3_DEFAULT_QUERY 205 * Speed obtained is from SFP. When the queried speed changes, the MAC 206 * speed needs to be reconfigured. 207 * 208 * - HNS3_ACTIVE_QUERY 209 * Speed obtained is from MAC. At this time, it is unnecessary for 210 * driver to reconfigured the MAC speed. In addition, more information, 211 * such as, the speed capability, auto-negotiation capability and FEC 212 * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD. 213 */ 214 uint8_t query_type; 215 uint32_t supported_speed; /* supported speed for current media type */ 216 uint32_t advertising; /* advertised capability in the local part */ 217 uint32_t lp_advertising; /* advertised capability in the link partner */ 218 uint8_t support_autoneg; 219 }; 220 221 struct hns3_fake_queue_data { 222 void **rx_queues; /* Array of pointers to fake RX queues. */ 223 void **tx_queues; /* Array of pointers to fake TX queues. */ 224 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 225 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 226 }; 227 228 #define HNS3_PORT_BASE_VLAN_DISABLE 0 229 #define HNS3_PORT_BASE_VLAN_ENABLE 1 230 struct hns3_port_base_vlan_config { 231 uint16_t state; 232 uint16_t pvid; 233 }; 234 235 /* Primary process maintains driver state in main thread. 236 * 237 * +---------------+ 238 * | UNINITIALIZED |<-----------+ 239 * +---------------+ | 240 * |.eth_dev_init |.eth_dev_uninit 241 * V | 242 * +---------------+------------+ 243 * | INITIALIZED | 244 * +---------------+<-----------<---------------+ 245 * |.dev_configure | | 246 * V |failed | 247 * +---------------+------------+ | 248 * | CONFIGURING | | 249 * +---------------+----+ | 250 * |success | | 251 * | | +---------------+ 252 * | | | CLOSING | 253 * | | +---------------+ 254 * | | ^ 255 * V |.dev_configure | 256 * +---------------+----+ |.dev_close 257 * | CONFIGURED |----------------------------+ 258 * +---------------+<-----------+ 259 * |.dev_start | 260 * V | 261 * +---------------+ | 262 * | STARTING |------------^ 263 * +---------------+ failed | 264 * |success | 265 * | +---------------+ 266 * | | STOPPING | 267 * | +---------------+ 268 * | ^ 269 * V |.dev_stop 270 * +---------------+------------+ 271 * | STARTED | 272 * +---------------+ 273 */ 274 enum hns3_adapter_state { 275 HNS3_NIC_UNINITIALIZED = 0, 276 HNS3_NIC_INITIALIZED, 277 HNS3_NIC_CONFIGURING, 278 HNS3_NIC_CONFIGURED, 279 HNS3_NIC_STARTING, 280 HNS3_NIC_STARTED, 281 HNS3_NIC_STOPPING, 282 HNS3_NIC_CLOSING, 283 HNS3_NIC_CLOSED, 284 HNS3_NIC_REMOVED, 285 HNS3_NIC_NSTATES 286 }; 287 288 /* Reset various stages, execute in order */ 289 enum hns3_reset_stage { 290 /* Stop query services, stop transceiver, disable MAC */ 291 RESET_STAGE_DOWN, 292 /* Clear reset completion flags, disable send command */ 293 RESET_STAGE_PREWAIT, 294 /* Inform IMP to start resetting */ 295 RESET_STAGE_REQ_HW_RESET, 296 /* Waiting for hardware reset to complete */ 297 RESET_STAGE_WAIT, 298 /* Reinitialize hardware */ 299 RESET_STAGE_DEV_INIT, 300 /* Restore user settings and enable MAC */ 301 RESET_STAGE_RESTORE, 302 /* Restart query services, start transceiver */ 303 RESET_STAGE_DONE, 304 /* Not in reset state */ 305 RESET_STAGE_NONE, 306 }; 307 308 enum hns3_reset_level { 309 HNS3_NONE_RESET, 310 HNS3_VF_FUNC_RESET, /* A VF function reset */ 311 /* 312 * All VFs under a PF perform function reset. 313 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 314 * of the reset level and the one defined in kernel driver should be 315 * same. 316 */ 317 HNS3_VF_PF_FUNC_RESET = 2, 318 /* 319 * All VFs under a PF perform FLR reset. 320 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 321 * of the reset level and the one defined in kernel driver should be 322 * same. 323 * 324 * According to the protocol of PCIe, FLR to a PF resets the PF state as 325 * well as the SR-IOV extended capability including VF Enable which 326 * means that VFs no longer exist. 327 * 328 * In PF FLR, the register state of VF is not reliable, VF's driver 329 * should not access the registers of the VF device. 330 */ 331 HNS3_VF_FULL_RESET = 3, 332 HNS3_FLR_RESET, /* A VF perform FLR reset */ 333 /* All VFs under the rootport perform a global or IMP reset */ 334 HNS3_VF_RESET, 335 HNS3_FUNC_RESET, /* A PF function reset */ 336 /* All PFs under the rootport perform a global reset */ 337 HNS3_GLOBAL_RESET, 338 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 339 HNS3_MAX_RESET 340 }; 341 342 enum hns3_wait_result { 343 HNS3_WAIT_UNKNOWN, 344 HNS3_WAIT_REQUEST, 345 HNS3_WAIT_SUCCESS, 346 HNS3_WAIT_TIMEOUT 347 }; 348 349 #define HNS3_RESET_SYNC_US 100000 350 351 struct hns3_reset_stats { 352 uint64_t request_cnt; /* Total request reset times */ 353 uint64_t global_cnt; /* Total GLOBAL reset times */ 354 uint64_t imp_cnt; /* Total IMP reset times */ 355 uint64_t exec_cnt; /* Total reset executive times */ 356 uint64_t success_cnt; /* Total reset successful times */ 357 uint64_t fail_cnt; /* Total reset failed times */ 358 uint64_t merge_cnt; /* Total merged in high reset times */ 359 }; 360 361 typedef bool (*check_completion_func)(struct hns3_hw *hw); 362 363 struct hns3_wait_data { 364 void *hns; 365 uint64_t end_ms; 366 uint64_t interval; 367 int16_t count; 368 enum hns3_wait_result result; 369 check_completion_func check_completion; 370 }; 371 372 struct hns3_reset_ops { 373 void (*reset_service)(void *arg); 374 int (*stop_service)(struct hns3_adapter *hns); 375 int (*prepare_reset)(struct hns3_adapter *hns); 376 int (*wait_hardware_ready)(struct hns3_adapter *hns); 377 int (*reinit_dev)(struct hns3_adapter *hns); 378 int (*restore_conf)(struct hns3_adapter *hns); 379 int (*start_service)(struct hns3_adapter *hns); 380 }; 381 382 enum hns3_schedule { 383 SCHEDULE_NONE, 384 SCHEDULE_PENDING, 385 SCHEDULE_REQUESTED, 386 SCHEDULE_DEFERRED, 387 }; 388 389 struct hns3_reset_data { 390 enum hns3_reset_stage stage; 391 uint16_t schedule; 392 /* Reset flag, covering the entire reset process */ 393 uint16_t resetting; 394 /* Used to disable sending cmds during reset */ 395 uint16_t disable_cmd; 396 /* The reset level being processed */ 397 enum hns3_reset_level level; 398 /* Reset level set, each bit represents a reset level */ 399 uint64_t pending; 400 /* Request reset level set, from interrupt or mailbox */ 401 uint64_t request; 402 int attempts; /* Reset failure retry */ 403 int retries; /* Timeout failure retry in reset_post */ 404 /* 405 * At the time of global or IMP reset, the command cannot be sent to 406 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 407 * reset process, so the mbuf is required to be released after the reset 408 * is completed.The mbuf_deferred_free is used to mark whether mbuf 409 * needs to be released. 410 */ 411 bool mbuf_deferred_free; 412 struct timeval start_time; 413 struct hns3_reset_stats stats; 414 const struct hns3_reset_ops *ops; 415 struct hns3_wait_data *wait_data; 416 }; 417 418 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 419 #define HNS3_INTR_MAPPING_VEC_ALL 1 420 421 #define HNS3_INTR_COALESCE_GL_UINT_2US 0 422 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 423 424 #define HNS3_INTR_QL_NONE 0 425 426 struct hns3_queue_intr { 427 /* 428 * interrupt mapping mode. 429 * value range: 430 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL 431 * 432 * - HNS3_INTR_MAPPING_VEC_RSV_ONE 433 * For some versions of hardware network engine, because of the 434 * hardware constraint, we need implement clearing the mapping 435 * relationship configurations by binding all queues to the last 436 * interrupt vector and reserving the last interrupt vector. This 437 * method results in a decrease of the maximum queues when upper 438 * applications call the rte_eth_dev_configure API function to 439 * enable Rx interrupt. 440 * 441 * - HNS3_INTR_MAPPING_VEC_ALL 442 * PMD driver can map/unmmap all interrupt vectors with queues When 443 * Rx interrupt in enabled. 444 */ 445 uint8_t mapping_mode; 446 /* 447 * The unit of GL(gap limiter) configuration for interrupt coalesce of 448 * queue's interrupt. 449 * value range: 450 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US 451 */ 452 uint8_t gl_unit; 453 /* The max QL(quantity limiter) value */ 454 uint16_t int_ql_max; 455 }; 456 457 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 458 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 459 460 #define HNS3_PKTS_DROP_STATS_MODE1 0 461 #define HNS3_PKTS_DROP_STATS_MODE2 1 462 463 struct hns3_hw { 464 struct rte_eth_dev_data *data; 465 void *io_base; 466 uint8_t revision; /* PCI revision, low byte of class word */ 467 struct hns3_cmq cmq; 468 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 469 struct hns3_mac mac; 470 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 471 struct hns3_tqp_stats tqp_stats; 472 /* Include Mac stats | Rx stats | Tx stats */ 473 struct hns3_mac_stats mac_stats; 474 struct hns3_rx_missed_stats imissed_stats; 475 uint64_t oerror_stats; 476 uint32_t fw_version; 477 478 uint16_t num_msi; 479 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 480 uint16_t tqps_num; /* num task queue pairs of this function */ 481 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 482 uint16_t rss_size_max; /* HW defined max RSS task queue */ 483 uint16_t rx_buf_len; /* hold min hardware rx buf len */ 484 uint16_t num_tx_desc; /* desc num of per tx queue */ 485 uint16_t num_rx_desc; /* desc num of per rx queue */ 486 uint32_t mng_entry_num; /* number of manager table entry */ 487 uint32_t mac_entry_num; /* number of mac-vlan table entry */ 488 489 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 490 int mc_addrs_num; /* Multicast mac addresses number */ 491 492 /* The configuration info of RSS */ 493 struct hns3_rss_conf rss_info; 494 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ 495 uint16_t rss_ind_tbl_size; 496 uint16_t rss_key_size; 497 498 uint8_t num_tc; /* Total number of enabled TCs */ 499 uint8_t hw_tc_map; 500 enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */ 501 struct hns3_dcb_info dcb_info; 502 enum hns3_fc_status current_fc_status; /* current flow control status */ 503 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 504 uint16_t used_rx_queues; 505 uint16_t used_tx_queues; 506 507 /* Config max queue numbers between rx and tx queues from user */ 508 uint16_t cfg_max_queues; 509 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 510 uint16_t alloc_rss_size; /* RX queue number per TC */ 511 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 512 513 uint32_t capability; 514 uint32_t max_tm_rate; 515 /* 516 * The minimum length of the packet supported by hardware in the Tx 517 * direction. 518 */ 519 uint32_t min_tx_pkt_len; 520 521 struct hns3_queue_intr intr; 522 /* 523 * tso mode. 524 * value range: 525 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 526 * 527 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 528 * In this mode, because of the hardware constraint, network driver 529 * software need erase the L4 len value of the TCP pseudo header 530 * and recalculate the TCP pseudo header checksum of packets that 531 * need TSO. 532 * 533 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 534 * In this mode, hardware support recalculate the TCP pseudo header 535 * checksum of packets that need TSO, so network driver software 536 * not need to recalculate it. 537 */ 538 uint8_t tso_mode; 539 /* 540 * vlan mode. 541 * value range: 542 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE 543 * 544 * - HNS3_SW_SHIFT_AND_DISCARD_MODE 545 * For some versions of hardware network engine, because of the 546 * hardware limitation, PMD driver needs to detect the PVID status 547 * to work with haredware to implement PVID-related functions. 548 * For example, driver need discard the stripped PVID tag to ensure 549 * the PVID will not report to mbuf and shift the inserted VLAN tag 550 * to avoid port based VLAN covering it. 551 * 552 * - HNS3_HW_SHIT_AND_DISCARD_MODE 553 * PMD driver does not need to process PVID-related functions in 554 * I/O process, Hardware will adjust the sequence between port based 555 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by 556 * PVID will be invisible to driver. And in this mode, hns3 is able 557 * to send a multi-layer VLAN packets when hw VLAN insert offload 558 * is enabled. 559 */ 560 uint8_t vlan_mode; 561 /* 562 * promisc mode. 563 * value range: 564 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE 565 * 566 * - HNS3_UNLIMIT_PROMISC_MODE 567 * In this mode, TX unicast promisc will be configured when promisc 568 * is set, driver can receive all the ingress and outgoing traffic. 569 * In the words, all the ingress packets, all the packets sent from 570 * the PF and other VFs on the same physical port. 571 * 572 * - HNS3_LIMIT_PROMISC_MODE 573 * In this mode, TX unicast promisc is shutdown when promisc mode 574 * is set. So, driver will only receive all the ingress traffic. 575 * The packets sent from the PF and other VFs on the same physical 576 * port won't be copied to the function which has set promisc mode. 577 */ 578 uint8_t promisc_mode; 579 580 /* 581 * drop_stats_mode mode. 582 * value range: 583 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 584 * 585 * - HNS3_PKTS_DROP_STATS_MODE1 586 * This mode for kunpeng920. In this mode, port level imissed stats 587 * is supported. It only includes RPU drop stats. 588 * 589 * - HNS3_PKTS_DROP_STATS_MODE2 590 * This mode for kunpeng930. In this mode, imissed stats and oerrors 591 * stats is supported. Function level imissed stats is supported. It 592 * includes RPU drop stats in VF, and includes both RPU drop stats 593 * and SSU drop stats in PF. Oerror stats is also supported in PF. 594 */ 595 uint8_t drop_stats_mode; 596 597 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 598 /* 599 * udp checksum mode. 600 * value range: 601 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE 602 * 603 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE 604 * In this mode, HW can not do checksum for special UDP port like 605 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel 606 * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need 607 * do the checksum for these packets to avoid a checksum error. 608 * 609 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE 610 * In this mode, HW does not have the preceding problems and can 611 * directly calculate the checksum of these UDP packets. 612 */ 613 uint8_t udp_cksum_mode; 614 615 struct hns3_port_base_vlan_config port_base_vlan_cfg; 616 /* 617 * PMD setup and configuration is not thread safe. Since it is not 618 * performance sensitive, it is better to guarantee thread-safety 619 * and add device level lock. Adapter control operations which 620 * change its state should acquire the lock. 621 */ 622 rte_spinlock_t lock; 623 enum hns3_adapter_state adapter_state; 624 struct hns3_reset_data reset; 625 }; 626 627 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 628 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 629 630 /* vlan entry information. */ 631 struct hns3_user_vlan_table { 632 LIST_ENTRY(hns3_user_vlan_table) next; 633 bool hd_tbl_status; 634 uint16_t vlan_id; 635 }; 636 637 /* Vlan tag configuration for RX direction */ 638 struct hns3_rx_vtag_cfg { 639 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 640 bool strip_tag1_en; /* Whether strip inner vlan tag */ 641 bool strip_tag2_en; /* Whether strip outer vlan tag */ 642 /* 643 * If strip_tag_en is enabled, this bit decide whether to map the vlan 644 * tag to descriptor. 645 */ 646 bool strip_tag1_discard_en; 647 bool strip_tag2_discard_en; 648 /* 649 * If this bit is enabled, only map inner/outer priority to descriptor 650 * and the vlan tag is always 0. 651 */ 652 bool vlan1_vlan_prionly; 653 bool vlan2_vlan_prionly; 654 }; 655 656 /* Vlan tag configuration for TX direction */ 657 struct hns3_tx_vtag_cfg { 658 bool accept_tag1; /* Whether accept tag1 packet from host */ 659 bool accept_untag1; /* Whether accept untag1 packet from host */ 660 bool accept_tag2; 661 bool accept_untag2; 662 bool insert_tag1_en; /* Whether insert outer vlan tag */ 663 bool insert_tag2_en; /* Whether insert inner vlan tag */ 664 /* 665 * In shift mode, hw will shift the sequence of port based VLAN and 666 * BD VLAN. 667 */ 668 bool tag_shift_mode_en; /* hw shift vlan tag automatically */ 669 uint16_t default_tag1; /* The default outer vlan tag to insert */ 670 uint16_t default_tag2; /* The default inner vlan tag to insert */ 671 }; 672 673 struct hns3_vtag_cfg { 674 struct hns3_rx_vtag_cfg rx_vcfg; 675 struct hns3_tx_vtag_cfg tx_vcfg; 676 }; 677 678 /* Request types for IPC. */ 679 enum hns3_mp_req_type { 680 HNS3_MP_REQ_START_RXTX = 1, 681 HNS3_MP_REQ_STOP_RXTX, 682 HNS3_MP_REQ_MAX 683 }; 684 685 /* Pameters for IPC. */ 686 struct hns3_mp_param { 687 enum hns3_mp_req_type type; 688 int port_id; 689 int result; 690 }; 691 692 /* Request timeout for IPC. */ 693 #define HNS3_MP_REQ_TIMEOUT_SEC 5 694 695 /* Key string for IPC. */ 696 #define HNS3_MP_NAME "net_hns3_mp" 697 698 #define HNS3_L2TBL_NUM 4 699 #define HNS3_L3TBL_NUM 16 700 #define HNS3_L4TBL_NUM 16 701 #define HNS3_OL2TBL_NUM 4 702 #define HNS3_OL3TBL_NUM 16 703 #define HNS3_OL4TBL_NUM 16 704 #define HNS3_PTYPE_NUM 256 705 706 struct hns3_ptype_table { 707 /* 708 * The next fields used to calc packet-type by the 709 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. 710 */ 711 uint32_t l3table[HNS3_L3TBL_NUM]; 712 uint32_t l4table[HNS3_L4TBL_NUM]; 713 uint32_t inner_l3table[HNS3_L3TBL_NUM]; 714 uint32_t inner_l4table[HNS3_L4TBL_NUM]; 715 uint32_t ol3table[HNS3_OL3TBL_NUM]; 716 uint32_t ol4table[HNS3_OL4TBL_NUM]; 717 718 /* 719 * The next field used to calc packet-type by the PTYPE from the Rx 720 * descriptor, it functions only when firmware report the capability of 721 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it. 722 */ 723 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned; 724 }; 725 726 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0 727 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1 728 729 struct hns3_pf { 730 struct hns3_adapter *adapter; 731 bool is_main_pf; 732 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 733 734 /* 735 * tqp_config mode 736 * tqp_config_mode value range: 737 * HNS3_FIXED_MAX_TQP_NUM_MODE, 738 * HNS3_FLEX_MAX_TQP_NUM_MODE 739 * 740 * - HNS3_FIXED_MAX_TQP_NUM_MODE 741 * There is a limitation on the number of pf interrupts available for 742 * on some versions of network engines. In this case, the maximum 743 * queue number of pf can not be greater than the interrupt number, 744 * such as pf of network engine with revision_id 0x21. So the maximum 745 * number of queues must be fixed. 746 * 747 * - HNS3_FLEX_MAX_TQP_NUM_MODE 748 * In this mode, the maximum queue number of pf has not any constraint 749 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 750 * in the config file. Users can modify the macro according to their 751 * own application scenarios, which is more flexible to use. 752 */ 753 uint8_t tqp_config_mode; 754 755 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 756 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 757 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 758 759 uint16_t mps; /* Max packet size */ 760 761 uint8_t tx_sch_mode; 762 uint8_t tc_max; /* max number of tc driver supported */ 763 uint8_t local_max_tc; /* max number of local tc */ 764 uint8_t pfc_max; 765 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 766 uint16_t pause_time; 767 bool support_fc_autoneg; /* support FC autonegotiate */ 768 769 uint16_t wanted_umv_size; 770 uint16_t max_umv_size; 771 uint16_t used_umv_size; 772 773 bool support_sfp_query; 774 uint32_t fec_mode; /* current FEC mode for ethdev */ 775 776 bool ptp_enable; 777 778 /* Stores timestamp of last received packet on dev */ 779 uint64_t rx_timestamp; 780 781 struct hns3_vtag_cfg vtag_config; 782 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 783 784 struct hns3_fdir_info fdir; /* flow director info */ 785 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 786 787 struct hns3_tm_conf tm_conf; 788 }; 789 790 enum { 791 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED, 792 HNS3_PF_PUSH_LSC_CAP_SUPPORTED, 793 HNS3_PF_PUSH_LSC_CAP_UNKNOWN 794 }; 795 796 struct hns3_vf { 797 struct hns3_adapter *adapter; 798 799 /* Whether PF support push link status change to VF */ 800 uint16_t pf_push_lsc_cap; 801 802 /* 803 * If PF support push link status change, VF still need send request to 804 * get link status in some cases (such as reset recover stage), so use 805 * the req_link_info_cnt to control max request count. 806 */ 807 uint16_t req_link_info_cnt; 808 809 uint16_t poll_job_started; /* whether poll job is started */ 810 }; 811 812 struct hns3_adapter { 813 struct hns3_hw hw; 814 815 /* Specific for PF or VF */ 816 bool is_vf; /* false - PF, true - VF */ 817 union { 818 struct hns3_pf pf; 819 struct hns3_vf vf; 820 }; 821 822 uint32_t rx_func_hint; 823 uint32_t tx_func_hint; 824 825 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; 826 }; 827 828 enum { 829 HNS3_IO_FUNC_HINT_NONE = 0, 830 HNS3_IO_FUNC_HINT_VEC, 831 HNS3_IO_FUNC_HINT_SVE, 832 HNS3_IO_FUNC_HINT_SIMPLE, 833 HNS3_IO_FUNC_HINT_COMMON 834 }; 835 836 #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" 837 #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" 838 839 #define HNS3_DEV_SUPPORT_DCB_B 0x0 840 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 841 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 842 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 843 #define HNS3_DEV_SUPPORT_PTP_B 0x4 844 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 845 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 846 #define HNS3_DEV_SUPPORT_STASH_B 0x7 847 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 848 #define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA 849 850 #define hns3_dev_dcb_supported(hw) \ 851 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) 852 853 /* Support copper media type */ 854 #define hns3_dev_copper_supported(hw) \ 855 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) 856 857 /* Support UDP GSO offload */ 858 #define hns3_dev_udp_gso_supported(hw) \ 859 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) 860 861 /* Support the queue region action rule of flow directory */ 862 #define hns3_dev_fd_queue_region_supported(hw) \ 863 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) 864 865 /* Support PTP timestamp offload */ 866 #define hns3_dev_ptp_supported(hw) \ 867 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) 868 869 #define hns3_dev_tx_push_supported(hw) \ 870 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) 871 872 /* Support to Independently enable/disable/reset Tx or Rx queues */ 873 #define hns3_dev_indep_txrx_supported(hw) \ 874 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) 875 876 #define hns3_dev_stash_supported(hw) \ 877 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) 878 879 #define hns3_dev_rxd_adv_layout_supported(hw) \ 880 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) 881 882 #define hns3_dev_outer_udp_cksum_supported(hw) \ 883 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) 884 885 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 886 (&((struct hns3_adapter *)adapter)->hw) 887 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 888 (&((struct hns3_adapter *)adapter)->pf) 889 #define HNS3_DEV_PRIVATE_TO_VF(adapter) \ 890 (&((struct hns3_adapter *)adapter)->vf) 891 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 892 container_of(hw, struct hns3_adapter, hw) 893 894 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) 895 { 896 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 897 return &adapter->pf; 898 } 899 900 static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw) 901 { 902 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 903 return &adapter->vf; 904 } 905 906 #define hns3_set_field(origin, mask, shift, val) \ 907 do { \ 908 (origin) &= (~(mask)); \ 909 (origin) |= ((val) << (shift)) & (mask); \ 910 } while (0) 911 #define hns3_get_field(origin, mask, shift) \ 912 (((origin) & (mask)) >> (shift)) 913 #define hns3_set_bit(origin, shift, val) \ 914 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 915 #define hns3_get_bit(origin, shift) \ 916 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 917 918 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) 919 920 /* 921 * upper_32_bits - return bits 32-63 of a number 922 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 923 * the "right shift count >= width of type" warning when that quantity is 924 * 32-bits. 925 */ 926 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 927 928 /* lower_32_bits - return bits 0-31 of a number */ 929 #define lower_32_bits(n) ((uint32_t)(n)) 930 931 #define BIT(nr) (1UL << (nr)) 932 933 #define BIT_ULL(x) (1ULL << (x)) 934 935 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 936 #define GENMASK(h, l) \ 937 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 938 939 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 940 #define rounddown(x, y) ((x) - ((x) % (y))) 941 942 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 943 944 /* 945 * Because hardware always access register in little-endian mode based on hns3 946 * network engine, so driver should also call rte_cpu_to_le_32 to convert data 947 * in little-endian mode before writing register and call rte_le_to_cpu_32 to 948 * convert data after reading from register. 949 * 950 * Here the driver encapsulates the data conversion operation in the register 951 * read/write operation function as below: 952 * hns3_write_reg 953 * hns3_write_reg_opt 954 * hns3_read_reg 955 * Therefore, when calling these functions, conversion is not required again. 956 */ 957 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 958 { 959 rte_write32(rte_cpu_to_le_32(value), 960 (volatile void *)((char *)base + reg)); 961 } 962 963 /* 964 * The optimized function for writing registers used in the '.rx_pkt_burst' and 965 * '.tx_pkt_burst' ops implementation function. 966 */ 967 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) 968 { 969 rte_io_wmb(); 970 rte_write32_relaxed(rte_cpu_to_le_32(value), addr); 971 } 972 973 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 974 { 975 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); 976 return rte_le_to_cpu_32(read_val); 977 } 978 979 #define hns3_write_dev(a, reg, value) \ 980 hns3_write_reg((a)->io_base, (reg), (value)) 981 982 #define hns3_read_dev(a, reg) \ 983 hns3_read_reg((a)->io_base, (reg)) 984 985 #define ARRAY_SIZE(x) RTE_DIM(x) 986 987 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 988 do { \ 989 act = (actions) + (index); \ 990 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 991 (index)++; \ 992 act = actions + index; \ 993 } \ 994 } while (0) 995 996 #define MSEC_PER_SEC 1000L 997 #define USEC_PER_MSEC 1000L 998 999 static inline uint64_t 1000 get_timeofday_ms(void) 1001 { 1002 struct timeval tv; 1003 1004 (void)gettimeofday(&tv, NULL); 1005 1006 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 1007 } 1008 1009 static inline uint64_t 1010 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 1011 { 1012 uint64_t res; 1013 1014 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 1015 return res; 1016 } 1017 1018 static inline void 1019 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 1020 { 1021 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 1022 } 1023 1024 static inline void 1025 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 1026 { 1027 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 1028 } 1029 1030 static inline int64_t 1031 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 1032 { 1033 uint64_t mask = (1UL << nr); 1034 1035 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 1036 } 1037 1038 int hns3_buffer_alloc(struct hns3_hw *hw); 1039 int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, 1040 const struct rte_flow_ops **ops); 1041 bool hns3_is_reset_pending(struct hns3_adapter *hns); 1042 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 1043 void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); 1044 void hns3_ether_format_addr(char *buf, uint16_t size, 1045 const struct rte_ether_addr *ether_addr); 1046 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, 1047 struct rte_eth_dev_info *info); 1048 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1049 uint32_t link_speed, uint8_t link_duplex); 1050 void hns3_parse_devargs(struct rte_eth_dev *dev); 1051 void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); 1052 int hns3_restore_ptp(struct hns3_adapter *hns); 1053 int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev, 1054 struct rte_eth_conf *conf); 1055 int hns3_ptp_init(struct hns3_hw *hw); 1056 int hns3_timesync_enable(struct rte_eth_dev *dev); 1057 int hns3_timesync_disable(struct rte_eth_dev *dev); 1058 int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1059 struct timespec *timestamp, 1060 uint32_t flags __rte_unused); 1061 int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1062 struct timespec *timestamp); 1063 int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts); 1064 int hns3_timesync_write_time(struct rte_eth_dev *dev, 1065 const struct timespec *ts); 1066 int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 1067 1068 static inline bool 1069 is_reset_pending(struct hns3_adapter *hns) 1070 { 1071 bool ret; 1072 if (hns->is_vf) 1073 ret = hns3vf_is_reset_pending(hns); 1074 else 1075 ret = hns3_is_reset_pending(hns); 1076 return ret; 1077 } 1078 1079 static inline uint64_t 1080 hns3_txvlan_cap_get(struct hns3_hw *hw) 1081 { 1082 if (hw->port_base_vlan_cfg.state) 1083 return DEV_TX_OFFLOAD_VLAN_INSERT; 1084 else 1085 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; 1086 } 1087 1088 #endif /* _HNS3_ETHDEV_H_ */ 1089