1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <rte_ethdev_driver.h> 10 11 #include "hns3_cmd.h" 12 #include "hns3_mbx.h" 13 #include "hns3_rss.h" 14 #include "hns3_fdir.h" 15 #include "hns3_stats.h" 16 17 /* Vendor ID */ 18 #define PCI_VENDOR_ID_HUAWEI 0x19e5 19 20 /* Device IDs */ 21 #define HNS3_DEV_ID_GE 0xA220 22 #define HNS3_DEV_ID_25GE 0xA221 23 #define HNS3_DEV_ID_25GE_RDMA 0xA222 24 #define HNS3_DEV_ID_50GE_RDMA 0xA224 25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 26 #define HNS3_DEV_ID_200G_RDMA 0xA228 27 #define HNS3_DEV_ID_100G_VF 0xA22E 28 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 29 30 /* PCI Config offsets */ 31 #define HNS3_PCI_REVISION_ID 0x08 32 #define HNS3_PCI_REVISION_ID_LEN 1 33 34 #define PCI_REVISION_ID_HIP08_B 0x21 35 #define PCI_REVISION_ID_HIP09_A 0x30 36 37 #define HNS3_PF_FUNC_ID 0 38 #define HNS3_1ST_VF_FUNC_ID 1 39 40 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 41 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 42 43 #define HNS3_UNLIMIT_PROMISC_MODE 0 44 #define HNS3_LIMIT_PROMISC_MODE 1 45 46 #define HNS3_UC_MACADDR_NUM 128 47 #define HNS3_VF_UC_MACADDR_NUM 48 48 #define HNS3_MC_MACADDR_NUM 128 49 50 #define HNS3_MAX_BD_SIZE 65535 51 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 52 #define HNS3_MAX_TSO_BD_PER_PKT 63 53 #define HNS3_MAX_FRAME_LEN 9728 54 #define HNS3_VLAN_TAG_SIZE 4 55 #define HNS3_DEFAULT_RX_BUF_LEN 2048 56 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 57 #define HNS3_MAX_TSO_HDR_SIZE 512 58 #define HNS3_MAX_TSO_HDR_BD_NUM 3 59 #define HNS3_MAX_LRO_SIZE 64512 60 61 #define HNS3_ETH_OVERHEAD \ 62 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 63 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 64 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 65 #define HNS3_DEFAULT_MTU 1500UL 66 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 67 #define HNS3_HIP08_MIN_TX_PKT_LEN 33 68 #define HNS3_HIP09_MIN_TX_PKT_LEN 9 69 70 #define HNS3_BITS_PER_BYTE 8 71 72 #define HNS3_4_TCS 4 73 #define HNS3_8_TCS 8 74 75 #define HNS3_MAX_PF_NUM 8 76 #define HNS3_UMV_TBL_SIZE 3072 77 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 78 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 79 80 #define HNS3_PF_CFG_BLOCK_SIZE 32 81 #define HNS3_PF_CFG_DESC_NUM \ 82 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 83 84 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 85 86 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 87 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 88 89 #define HNS3_QUIT_RESET_CNT 10 90 #define HNS3_QUIT_RESET_DELAY_MS 100 91 92 #define HNS3_POLL_RESPONE_MS 1 93 94 #define HNS3_MAX_USER_PRIO 8 95 #define HNS3_PG_NUM 4 96 enum hns3_fc_mode { 97 HNS3_FC_NONE, 98 HNS3_FC_RX_PAUSE, 99 HNS3_FC_TX_PAUSE, 100 HNS3_FC_FULL, 101 HNS3_FC_DEFAULT 102 }; 103 104 #define HNS3_SCH_MODE_SP 0 105 #define HNS3_SCH_MODE_DWRR 1 106 struct hns3_pg_info { 107 uint8_t pg_id; 108 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 109 uint8_t tc_bit_map; 110 uint32_t bw_limit; 111 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 112 }; 113 114 struct hns3_tc_info { 115 uint8_t tc_id; 116 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 117 uint8_t pgid; 118 uint32_t bw_limit; 119 uint8_t up_to_tc_map; /* user priority maping on the TC */ 120 }; 121 122 struct hns3_dcb_info { 123 uint8_t num_tc; 124 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 125 uint8_t pg_dwrr[HNS3_PG_NUM]; 126 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 127 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 128 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 129 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 130 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 131 }; 132 133 enum hns3_fc_status { 134 HNS3_FC_STATUS_NONE, 135 HNS3_FC_STATUS_MAC_PAUSE, 136 HNS3_FC_STATUS_PFC, 137 }; 138 139 struct hns3_tc_queue_info { 140 uint16_t tqp_offset; /* TQP offset from base TQP */ 141 uint16_t tqp_count; /* Total TQPs */ 142 uint8_t tc; /* TC index */ 143 bool enable; /* If this TC is enable or not */ 144 }; 145 146 struct hns3_cfg { 147 uint8_t vmdq_vport_num; 148 uint8_t tc_num; 149 uint16_t tqp_desc_num; 150 uint16_t rx_buf_len; 151 uint16_t rss_size_max; 152 uint8_t phy_addr; 153 uint8_t media_type; 154 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 155 uint8_t default_speed; 156 uint32_t numa_node_map; 157 uint8_t speed_ability; 158 uint16_t umv_space; 159 }; 160 161 /* mac media type */ 162 enum hns3_media_type { 163 HNS3_MEDIA_TYPE_UNKNOWN, 164 HNS3_MEDIA_TYPE_FIBER, 165 HNS3_MEDIA_TYPE_COPPER, 166 HNS3_MEDIA_TYPE_BACKPLANE, 167 HNS3_MEDIA_TYPE_NONE, 168 }; 169 170 struct hns3_mac { 171 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 172 bool default_addr_setted; /* whether default addr(mac_addr) is set */ 173 uint8_t media_type; 174 uint8_t phy_addr; 175 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 176 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 177 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 178 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 179 }; 180 181 struct hns3_fake_queue_data { 182 void **rx_queues; /* Array of pointers to fake RX queues. */ 183 void **tx_queues; /* Array of pointers to fake TX queues. */ 184 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 185 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 186 }; 187 188 #define HNS3_PORT_BASE_VLAN_DISABLE 0 189 #define HNS3_PORT_BASE_VLAN_ENABLE 1 190 struct hns3_port_base_vlan_config { 191 uint16_t state; 192 uint16_t pvid; 193 }; 194 195 /* Primary process maintains driver state in main thread. 196 * 197 * +---------------+ 198 * | UNINITIALIZED |<-----------+ 199 * +---------------+ | 200 * |.eth_dev_init |.eth_dev_uninit 201 * V | 202 * +---------------+------------+ 203 * | INITIALIZED | 204 * +---------------+<-----------<---------------+ 205 * |.dev_configure | | 206 * V |failed | 207 * +---------------+------------+ | 208 * | CONFIGURING | | 209 * +---------------+----+ | 210 * |success | | 211 * | | +---------------+ 212 * | | | CLOSING | 213 * | | +---------------+ 214 * | | ^ 215 * V |.dev_configure | 216 * +---------------+----+ |.dev_close 217 * | CONFIGURED |----------------------------+ 218 * +---------------+<-----------+ 219 * |.dev_start | 220 * V | 221 * +---------------+ | 222 * | STARTING |------------^ 223 * +---------------+ failed | 224 * |success | 225 * | +---------------+ 226 * | | STOPPING | 227 * | +---------------+ 228 * | ^ 229 * V |.dev_stop 230 * +---------------+------------+ 231 * | STARTED | 232 * +---------------+ 233 */ 234 enum hns3_adapter_state { 235 HNS3_NIC_UNINITIALIZED = 0, 236 HNS3_NIC_INITIALIZED, 237 HNS3_NIC_CONFIGURING, 238 HNS3_NIC_CONFIGURED, 239 HNS3_NIC_STARTING, 240 HNS3_NIC_STARTED, 241 HNS3_NIC_STOPPING, 242 HNS3_NIC_CLOSING, 243 HNS3_NIC_CLOSED, 244 HNS3_NIC_REMOVED, 245 HNS3_NIC_NSTATES 246 }; 247 248 /* Reset various stages, execute in order */ 249 enum hns3_reset_stage { 250 /* Stop query services, stop transceiver, disable MAC */ 251 RESET_STAGE_DOWN, 252 /* Clear reset completion flags, disable send command */ 253 RESET_STAGE_PREWAIT, 254 /* Inform IMP to start resetting */ 255 RESET_STAGE_REQ_HW_RESET, 256 /* Waiting for hardware reset to complete */ 257 RESET_STAGE_WAIT, 258 /* Reinitialize hardware */ 259 RESET_STAGE_DEV_INIT, 260 /* Restore user settings and enable MAC */ 261 RESET_STAGE_RESTORE, 262 /* Restart query services, start transceiver */ 263 RESET_STAGE_DONE, 264 /* Not in reset state */ 265 RESET_STAGE_NONE, 266 }; 267 268 enum hns3_reset_level { 269 HNS3_NONE_RESET, 270 HNS3_VF_FUNC_RESET, /* A VF function reset */ 271 /* 272 * All VFs under a PF perform function reset. 273 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 274 * of the reset level and the one defined in kernel driver should be 275 * same. 276 */ 277 HNS3_VF_PF_FUNC_RESET = 2, 278 /* 279 * All VFs under a PF perform FLR reset. 280 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 281 * of the reset level and the one defined in kernel driver should be 282 * same. 283 * 284 * According to the protocol of PCIe, FLR to a PF resets the PF state as 285 * well as the SR-IOV extended capability including VF Enable which 286 * means that VFs no longer exist. 287 * 288 * In PF FLR, the register state of VF is not reliable, VF's driver 289 * should not access the registers of the VF device. 290 */ 291 HNS3_VF_FULL_RESET = 3, 292 HNS3_FLR_RESET, /* A VF perform FLR reset */ 293 /* All VFs under the rootport perform a global or IMP reset */ 294 HNS3_VF_RESET, 295 HNS3_FUNC_RESET, /* A PF function reset */ 296 /* All PFs under the rootport perform a global reset */ 297 HNS3_GLOBAL_RESET, 298 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 299 HNS3_MAX_RESET 300 }; 301 302 enum hns3_wait_result { 303 HNS3_WAIT_UNKNOWN, 304 HNS3_WAIT_REQUEST, 305 HNS3_WAIT_SUCCESS, 306 HNS3_WAIT_TIMEOUT 307 }; 308 309 #define HNS3_RESET_SYNC_US 100000 310 311 struct hns3_reset_stats { 312 uint64_t request_cnt; /* Total request reset times */ 313 uint64_t global_cnt; /* Total GLOBAL reset times */ 314 uint64_t imp_cnt; /* Total IMP reset times */ 315 uint64_t exec_cnt; /* Total reset executive times */ 316 uint64_t success_cnt; /* Total reset successful times */ 317 uint64_t fail_cnt; /* Total reset failed times */ 318 uint64_t merge_cnt; /* Total merged in high reset times */ 319 }; 320 321 typedef bool (*check_completion_func)(struct hns3_hw *hw); 322 323 struct hns3_wait_data { 324 void *hns; 325 uint64_t end_ms; 326 uint64_t interval; 327 int16_t count; 328 enum hns3_wait_result result; 329 check_completion_func check_completion; 330 }; 331 332 struct hns3_reset_ops { 333 void (*reset_service)(void *arg); 334 int (*stop_service)(struct hns3_adapter *hns); 335 int (*prepare_reset)(struct hns3_adapter *hns); 336 int (*wait_hardware_ready)(struct hns3_adapter *hns); 337 int (*reinit_dev)(struct hns3_adapter *hns); 338 int (*restore_conf)(struct hns3_adapter *hns); 339 int (*start_service)(struct hns3_adapter *hns); 340 }; 341 342 enum hns3_schedule { 343 SCHEDULE_NONE, 344 SCHEDULE_PENDING, 345 SCHEDULE_REQUESTED, 346 SCHEDULE_DEFERRED, 347 }; 348 349 struct hns3_reset_data { 350 enum hns3_reset_stage stage; 351 rte_atomic16_t schedule; 352 /* Reset flag, covering the entire reset process */ 353 rte_atomic16_t resetting; 354 /* Used to disable sending cmds during reset */ 355 rte_atomic16_t disable_cmd; 356 /* The reset level being processed */ 357 enum hns3_reset_level level; 358 /* Reset level set, each bit represents a reset level */ 359 uint64_t pending; 360 /* Request reset level set, from interrupt or mailbox */ 361 uint64_t request; 362 int attempts; /* Reset failure retry */ 363 int retries; /* Timeout failure retry in reset_post */ 364 /* 365 * At the time of global or IMP reset, the command cannot be sent to 366 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 367 * reset process, so the mbuf is required to be released after the reset 368 * is completed.The mbuf_deferred_free is used to mark whether mbuf 369 * needs to be released. 370 */ 371 bool mbuf_deferred_free; 372 struct timeval start_time; 373 struct hns3_reset_stats stats; 374 const struct hns3_reset_ops *ops; 375 struct hns3_wait_data *wait_data; 376 }; 377 378 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 379 #define HNS3_INTR_MAPPING_VEC_ALL 1 380 381 #define HNS3_INTR_COALESCE_GL_UINT_2US 0 382 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 383 384 #define HNS3_INTR_QL_NONE 0 385 386 struct hns3_queue_intr { 387 /* 388 * interrupt mapping mode. 389 * value range: 390 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL 391 * 392 * - HNS3_INTR_MAPPING_VEC_RSV_ONE 393 * For some versions of hardware network engine, because of the 394 * hardware constraint, we need implement clearing the mapping 395 * relationship configurations by binding all queues to the last 396 * interrupt vector and reserving the last interrupt vector. This 397 * method results in a decrease of the maximum queues when upper 398 * applications call the rte_eth_dev_configure API function to 399 * enable Rx interrupt. 400 * 401 * - HNS3_INTR_MAPPING_VEC_ALL 402 * PMD driver can map/unmmap all interrupt vectors with queues When 403 * Rx interrupt in enabled. 404 */ 405 uint8_t mapping_mode; 406 /* 407 * The unit of GL(gap limiter) configuration for interrupt coalesce of 408 * queue's interrupt. 409 * value range: 410 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US 411 */ 412 uint8_t gl_unit; 413 /* The max QL(quantity limiter) value */ 414 uint16_t int_ql_max; 415 }; 416 417 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 418 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 419 420 struct hns3_hw { 421 struct rte_eth_dev_data *data; 422 void *io_base; 423 uint8_t revision; /* PCI revision, low byte of class word */ 424 struct hns3_cmq cmq; 425 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 426 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ 427 pthread_t irq_thread_id; 428 struct hns3_mac mac; 429 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 430 struct hns3_tqp_stats tqp_stats; 431 /* Include Mac stats | Rx stats | Tx stats */ 432 struct hns3_mac_stats mac_stats; 433 uint32_t fw_version; 434 435 uint16_t num_msi; 436 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 437 uint16_t tqps_num; /* num task queue pairs of this function */ 438 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 439 uint16_t rss_size_max; /* HW defined max RSS task queue */ 440 uint16_t rx_buf_len; /* hold min hardware rx buf len */ 441 uint16_t num_tx_desc; /* desc num of per tx queue */ 442 uint16_t num_rx_desc; /* desc num of per rx queue */ 443 uint32_t mng_entry_num; /* number of manager table entry */ 444 uint32_t mac_entry_num; /* number of mac-vlan table entry */ 445 446 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 447 int mc_addrs_num; /* Multicast mac addresses number */ 448 449 /* The configuration info of RSS */ 450 struct hns3_rss_conf rss_info; 451 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ 452 uint16_t rss_ind_tbl_size; 453 uint16_t rss_key_size; 454 455 uint8_t num_tc; /* Total number of enabled TCs */ 456 uint8_t hw_tc_map; 457 enum hns3_fc_mode current_mode; 458 enum hns3_fc_mode requested_mode; 459 struct hns3_dcb_info dcb_info; 460 enum hns3_fc_status current_fc_status; /* current flow control status */ 461 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 462 uint16_t used_rx_queues; 463 uint16_t used_tx_queues; 464 465 /* Config max queue numbers between rx and tx queues from user */ 466 uint16_t cfg_max_queues; 467 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 468 uint16_t alloc_rss_size; /* RX queue number per TC */ 469 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 470 471 uint32_t capability; 472 uint32_t max_tm_rate; 473 /* 474 * The minimum length of the packet supported by hardware in the Tx 475 * direction. 476 */ 477 uint32_t min_tx_pkt_len; 478 479 struct hns3_queue_intr intr; 480 /* 481 * tso mode. 482 * value range: 483 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 484 * 485 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 486 * In this mode, because of the hardware constraint, network driver 487 * software need erase the L4 len value of the TCP pseudo header 488 * and recalculate the TCP pseudo header checksum of packets that 489 * need TSO. 490 * 491 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 492 * In this mode, hardware support recalculate the TCP pseudo header 493 * checksum of packets that need TSO, so network driver software 494 * not need to recalculate it. 495 */ 496 uint8_t tso_mode; 497 /* 498 * vlan mode. 499 * value range: 500 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE 501 * 502 * - HNS3_SW_SHIFT_AND_DISCARD_MODE 503 * For some versions of hardware network engine, because of the 504 * hardware limitation, PMD driver needs to detect the PVID status 505 * to work with haredware to implement PVID-related functions. 506 * For example, driver need discard the stripped PVID tag to ensure 507 * the PVID will not report to mbuf and shift the inserted VLAN tag 508 * to avoid port based VLAN covering it. 509 * 510 * - HNS3_HW_SHIT_AND_DISCARD_MODE 511 * PMD driver does not need to process PVID-related functions in 512 * I/O process, Hardware will adjust the sequence between port based 513 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by 514 * PVID will be invisible to driver. And in this mode, hns3 is able 515 * to send a multi-layer VLAN packets when hw VLAN insert offload 516 * is enabled. 517 */ 518 uint8_t vlan_mode; 519 /* 520 * promisc mode. 521 * value range: 522 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE 523 * 524 * - HNS3_UNLIMIT_PROMISC_MODE 525 * In this mode, TX unicast promisc will be configured when promisc 526 * is set, driver can receive all the ingress and outgoing traffic. 527 * In the words, all the ingress packets, all the packets sent from 528 * the PF and other VFs on the same physical port. 529 * 530 * - HNS3_LIMIT_PROMISC_MODE 531 * In this mode, TX unicast promisc is shutdown when promisc mode 532 * is set. So, driver will only receive all the ingress traffic. 533 * The packets sent from the PF and other VFs on the same physical 534 * port won't be copied to the function which has set promisc mode. 535 */ 536 uint8_t promisc_mode; 537 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 538 539 struct hns3_port_base_vlan_config port_base_vlan_cfg; 540 /* 541 * PMD setup and configuration is not thread safe. Since it is not 542 * performance sensitive, it is better to guarantee thread-safety 543 * and add device level lock. Adapter control operations which 544 * change its state should acquire the lock. 545 */ 546 rte_spinlock_t lock; 547 enum hns3_adapter_state adapter_state; 548 struct hns3_reset_data reset; 549 }; 550 551 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 552 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 553 554 struct hns3_err_msix_intr_stats { 555 uint64_t mac_afifo_tnl_int_cnt; 556 uint64_t ppu_mpf_abn_int_st2_msix_cnt; 557 uint64_t ssu_port_based_pf_int_cnt; 558 uint64_t ppp_pf_abnormal_int_cnt; 559 uint64_t ppu_pf_abnormal_int_msix_cnt; 560 561 uint64_t imp_tcm_ecc_int_cnt; 562 uint64_t cmdq_mem_ecc_int_cnt; 563 uint64_t imp_rd_poison_int_cnt; 564 uint64_t tqp_int_ecc_int_cnt; 565 uint64_t msix_ecc_int_cnt; 566 uint64_t ssu_ecc_multi_bit_int_0_cnt; 567 uint64_t ssu_ecc_multi_bit_int_1_cnt; 568 uint64_t ssu_common_ecc_int_cnt; 569 uint64_t igu_int_cnt; 570 uint64_t ppp_mpf_abnormal_int_st1_cnt; 571 uint64_t ppp_mpf_abnormal_int_st3_cnt; 572 uint64_t ppu_mpf_abnormal_int_st1_cnt; 573 uint64_t ppu_mpf_abn_int_st2_ras_cnt; 574 uint64_t ppu_mpf_abnormal_int_st3_cnt; 575 uint64_t tm_sch_int_cnt; 576 uint64_t qcn_fifo_int_cnt; 577 uint64_t qcn_ecc_int_cnt; 578 uint64_t ncsi_ecc_int_cnt; 579 uint64_t ssu_port_based_err_int_cnt; 580 uint64_t ssu_fifo_overflow_int_cnt; 581 uint64_t ssu_ets_tcg_int_cnt; 582 uint64_t igu_egu_tnl_int_cnt; 583 uint64_t ppu_pf_abnormal_int_ras_cnt; 584 }; 585 586 /* vlan entry information. */ 587 struct hns3_user_vlan_table { 588 LIST_ENTRY(hns3_user_vlan_table) next; 589 bool hd_tbl_status; 590 uint16_t vlan_id; 591 }; 592 593 /* Vlan tag configuration for RX direction */ 594 struct hns3_rx_vtag_cfg { 595 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 596 bool strip_tag1_en; /* Whether strip inner vlan tag */ 597 bool strip_tag2_en; /* Whether strip outer vlan tag */ 598 /* 599 * If strip_tag_en is enabled, this bit decide whether to map the vlan 600 * tag to descriptor. 601 */ 602 bool strip_tag1_discard_en; 603 bool strip_tag2_discard_en; 604 /* 605 * If this bit is enabled, only map inner/outer priority to descriptor 606 * and the vlan tag is always 0. 607 */ 608 bool vlan1_vlan_prionly; 609 bool vlan2_vlan_prionly; 610 }; 611 612 /* Vlan tag configuration for TX direction */ 613 struct hns3_tx_vtag_cfg { 614 bool accept_tag1; /* Whether accept tag1 packet from host */ 615 bool accept_untag1; /* Whether accept untag1 packet from host */ 616 bool accept_tag2; 617 bool accept_untag2; 618 bool insert_tag1_en; /* Whether insert outer vlan tag */ 619 bool insert_tag2_en; /* Whether insert inner vlan tag */ 620 /* 621 * In shift mode, hw will shift the sequence of port based VLAN and 622 * BD VLAN. 623 */ 624 bool tag_shift_mode_en; /* hw shift vlan tag automatically */ 625 uint16_t default_tag1; /* The default outer vlan tag to insert */ 626 uint16_t default_tag2; /* The default inner vlan tag to insert */ 627 }; 628 629 struct hns3_vtag_cfg { 630 struct hns3_rx_vtag_cfg rx_vcfg; 631 struct hns3_tx_vtag_cfg tx_vcfg; 632 }; 633 634 /* Request types for IPC. */ 635 enum hns3_mp_req_type { 636 HNS3_MP_REQ_START_RXTX = 1, 637 HNS3_MP_REQ_STOP_RXTX, 638 HNS3_MP_REQ_MAX 639 }; 640 641 /* Pameters for IPC. */ 642 struct hns3_mp_param { 643 enum hns3_mp_req_type type; 644 int port_id; 645 int result; 646 }; 647 648 /* Request timeout for IPC. */ 649 #define HNS3_MP_REQ_TIMEOUT_SEC 5 650 651 /* Key string for IPC. */ 652 #define HNS3_MP_NAME "net_hns3_mp" 653 654 #define HNS3_L2TBL_NUM 4 655 #define HNS3_L3TBL_NUM 16 656 #define HNS3_L4TBL_NUM 16 657 #define HNS3_OL2TBL_NUM 4 658 #define HNS3_OL3TBL_NUM 16 659 #define HNS3_OL4TBL_NUM 16 660 661 struct hns3_ptype_table { 662 uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM]; 663 uint32_t l4table[HNS3_L4TBL_NUM]; 664 uint32_t inner_l2table[HNS3_L2TBL_NUM]; 665 uint32_t inner_l3table[HNS3_L3TBL_NUM]; 666 uint32_t inner_l4table[HNS3_L4TBL_NUM]; 667 uint32_t ol2table[HNS3_OL2TBL_NUM]; 668 uint32_t ol3table[HNS3_OL3TBL_NUM]; 669 uint32_t ol4table[HNS3_OL4TBL_NUM]; 670 }; 671 672 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0 673 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1 674 675 struct hns3_pf { 676 struct hns3_adapter *adapter; 677 bool is_main_pf; 678 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 679 680 /* 681 * tqp_config mode 682 * tqp_config_mode value range: 683 * HNS3_FIXED_MAX_TQP_NUM_MODE, 684 * HNS3_FLEX_MAX_TQP_NUM_MODE 685 * 686 * - HNS3_FIXED_MAX_TQP_NUM_MODE 687 * There is a limitation on the number of pf interrupts available for 688 * on some versions of network engines. In this case, the maximum 689 * queue number of pf can not be greater than the interrupt number, 690 * such as pf of network engine with revision_id 0x21. So the maximum 691 * number of queues must be fixed. 692 * 693 * - HNS3_FLEX_MAX_TQP_NUM_MODE 694 * In this mode, the maximum queue number of pf has not any constraint 695 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 696 * in the config file. Users can modify the macro according to their 697 * own application scenarios, which is more flexible to use. 698 */ 699 uint8_t tqp_config_mode; 700 701 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 702 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 703 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 704 705 uint16_t mps; /* Max packet size */ 706 707 uint8_t tx_sch_mode; 708 uint8_t tc_max; /* max number of tc driver supported */ 709 uint8_t local_max_tc; /* max number of local tc */ 710 uint8_t pfc_max; 711 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 712 uint16_t pause_time; 713 bool support_fc_autoneg; /* support FC autonegotiate */ 714 715 uint16_t wanted_umv_size; 716 uint16_t max_umv_size; 717 uint16_t used_umv_size; 718 719 /* Statistics information for abnormal interrupt */ 720 struct hns3_err_msix_intr_stats abn_int_stats; 721 722 bool support_sfp_query; 723 uint32_t fec_mode; /* current FEC mode for ethdev */ 724 725 struct hns3_vtag_cfg vtag_config; 726 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 727 728 struct hns3_fdir_info fdir; /* flow director info */ 729 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 730 }; 731 732 struct hns3_vf { 733 struct hns3_adapter *adapter; 734 }; 735 736 struct hns3_adapter { 737 struct hns3_hw hw; 738 739 /* Specific for PF or VF */ 740 bool is_vf; /* false - PF, true - VF */ 741 union { 742 struct hns3_pf pf; 743 struct hns3_vf vf; 744 }; 745 746 struct rte_eth_dev *eth_dev; 747 748 bool rx_simple_allowed; 749 bool rx_vec_allowed; 750 bool tx_simple_allowed; 751 bool tx_vec_allowed; 752 753 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; 754 }; 755 756 #define HNS3_DEV_SUPPORT_DCB_B 0x0 757 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 758 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 759 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 760 #define HNS3_DEV_SUPPORT_PTP_B 0x4 761 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 762 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 763 #define HNS3_DEV_SUPPORT_STASH_B 0x7 764 765 #define hns3_dev_dcb_supported(hw) \ 766 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) 767 768 /* Support copper media type */ 769 #define hns3_dev_copper_supported(hw) \ 770 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) 771 772 /* Support UDP GSO offload */ 773 #define hns3_dev_udp_gso_supported(hw) \ 774 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) 775 776 /* Support the queue region action rule of flow directory */ 777 #define hns3_dev_fd_queue_region_supported(hw) \ 778 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) 779 780 /* Support PTP timestamp offload */ 781 #define hns3_dev_ptp_supported(hw) \ 782 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) 783 784 #define hns3_dev_tx_push_supported(hw) \ 785 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) 786 787 /* Support to Independently enable/disable/reset Tx or Rx queues */ 788 #define hns3_dev_indep_txrx_supported(hw) \ 789 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) 790 791 #define hns3_dev_stash_supported(hw) \ 792 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) 793 794 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 795 (&((struct hns3_adapter *)adapter)->hw) 796 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 797 (&((struct hns3_adapter *)adapter)->pf) 798 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 799 container_of(hw, struct hns3_adapter, hw) 800 801 #define hns3_set_field(origin, mask, shift, val) \ 802 do { \ 803 (origin) &= (~(mask)); \ 804 (origin) |= ((val) << (shift)) & (mask); \ 805 } while (0) 806 #define hns3_get_field(origin, mask, shift) \ 807 (((origin) & (mask)) >> (shift)) 808 #define hns3_set_bit(origin, shift, val) \ 809 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 810 #define hns3_get_bit(origin, shift) \ 811 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 812 813 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) 814 815 /* 816 * upper_32_bits - return bits 32-63 of a number 817 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 818 * the "right shift count >= width of type" warning when that quantity is 819 * 32-bits. 820 */ 821 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 822 823 /* lower_32_bits - return bits 0-31 of a number */ 824 #define lower_32_bits(n) ((uint32_t)(n)) 825 826 #define BIT(nr) (1UL << (nr)) 827 828 #define BIT_ULL(x) (1ULL << (x)) 829 830 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 831 #define GENMASK(h, l) \ 832 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 833 834 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 835 #define rounddown(x, y) ((x) - ((x) % (y))) 836 837 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 838 839 /* 840 * Because hardware always access register in little-endian mode based on hns3 841 * network engine, so driver should also call rte_cpu_to_le_32 to convert data 842 * in little-endian mode before writing register and call rte_le_to_cpu_32 to 843 * convert data after reading from register. 844 * 845 * Here the driver encapsulates the data conversion operation in the register 846 * read/write operation function as below: 847 * hns3_write_reg 848 * hns3_write_reg_opt 849 * hns3_read_reg 850 * Therefore, when calling these functions, conversion is not required again. 851 */ 852 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 853 { 854 rte_write32(rte_cpu_to_le_32(value), 855 (volatile void *)((char *)base + reg)); 856 } 857 858 /* 859 * The optimized function for writing registers used in the '.rx_pkt_burst' and 860 * '.tx_pkt_burst' ops implementation function. 861 */ 862 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) 863 { 864 rte_io_wmb(); 865 rte_write32_relaxed(rte_cpu_to_le_32(value), addr); 866 } 867 868 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 869 { 870 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); 871 return rte_le_to_cpu_32(read_val); 872 } 873 874 #define hns3_write_dev(a, reg, value) \ 875 hns3_write_reg((a)->io_base, (reg), (value)) 876 877 #define hns3_read_dev(a, reg) \ 878 hns3_read_reg((a)->io_base, (reg)) 879 880 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 881 882 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 883 do { \ 884 act = (actions) + (index); \ 885 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 886 (index)++; \ 887 act = actions + index; \ 888 } \ 889 } while (0) 890 891 #define MSEC_PER_SEC 1000L 892 #define USEC_PER_MSEC 1000L 893 894 static inline uint64_t 895 get_timeofday_ms(void) 896 { 897 struct timeval tv; 898 899 (void)gettimeofday(&tv, NULL); 900 901 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 902 } 903 904 static inline uint64_t 905 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 906 { 907 uint64_t res; 908 909 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 910 return res; 911 } 912 913 static inline void 914 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 915 { 916 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 917 } 918 919 static inline void 920 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 921 { 922 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 923 } 924 925 static inline int64_t 926 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 927 { 928 uint64_t mask = (1UL << nr); 929 930 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 931 } 932 933 int hns3_buffer_alloc(struct hns3_hw *hw); 934 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, 935 enum rte_filter_type filter_type, 936 enum rte_filter_op filter_op, void *arg); 937 bool hns3_is_reset_pending(struct hns3_adapter *hns); 938 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 939 void hns3_update_link_status(struct hns3_hw *hw); 940 void hns3_ether_format_addr(char *buf, uint16_t size, 941 const struct rte_ether_addr *ether_addr); 942 943 static inline bool 944 is_reset_pending(struct hns3_adapter *hns) 945 { 946 bool ret; 947 if (hns->is_vf) 948 ret = hns3vf_is_reset_pending(hns); 949 else 950 ret = hns3_is_reset_pending(hns); 951 return ret; 952 } 953 954 static inline uint64_t 955 hns3_txvlan_cap_get(struct hns3_hw *hw) 956 { 957 if (hw->port_base_vlan_cfg.state) 958 return DEV_TX_OFFLOAD_VLAN_INSERT; 959 else 960 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; 961 } 962 963 #endif /* _HNS3_ETHDEV_H_ */ 964