1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <rte_alarm.h> 10 11 #include "hns3_cmd.h" 12 #include "hns3_mbx.h" 13 #include "hns3_rss.h" 14 #include "hns3_fdir.h" 15 #include "hns3_stats.h" 16 17 /* Vendor ID */ 18 #define PCI_VENDOR_ID_HUAWEI 0x19e5 19 20 /* Device IDs */ 21 #define HNS3_DEV_ID_GE 0xA220 22 #define HNS3_DEV_ID_25GE 0xA221 23 #define HNS3_DEV_ID_25GE_RDMA 0xA222 24 #define HNS3_DEV_ID_50GE_RDMA 0xA224 25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 26 #define HNS3_DEV_ID_200G_RDMA 0xA228 27 #define HNS3_DEV_ID_100G_VF 0xA22E 28 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 29 30 /* PCI Config offsets */ 31 #define HNS3_PCI_REVISION_ID 0x08 32 #define HNS3_PCI_REVISION_ID_LEN 1 33 34 #define PCI_REVISION_ID_HIP08_B 0x21 35 #define PCI_REVISION_ID_HIP09_A 0x30 36 37 #define HNS3_PF_FUNC_ID 0 38 #define HNS3_1ST_VF_FUNC_ID 1 39 40 #define HNS3_UC_MACADDR_NUM 128 41 #define HNS3_VF_UC_MACADDR_NUM 48 42 #define HNS3_MC_MACADDR_NUM 128 43 44 #define HNS3_MAX_BD_SIZE 65535 45 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 46 #define HNS3_MAX_TSO_BD_PER_PKT 63 47 #define HNS3_MAX_FRAME_LEN 9728 48 #define HNS3_VLAN_TAG_SIZE 4 49 #define HNS3_DEFAULT_RX_BUF_LEN 2048 50 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 51 #define HNS3_MAX_TSO_HDR_SIZE 512 52 #define HNS3_MAX_TSO_HDR_BD_NUM 3 53 #define HNS3_MAX_LRO_SIZE 64512 54 55 #define HNS3_ETH_OVERHEAD \ 56 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 57 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 58 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 59 #define HNS3_DEFAULT_MTU 1500UL 60 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 61 #define HNS3_MIN_PKT_SIZE 60 62 63 #define HNS3_4_TCS 4 64 #define HNS3_8_TCS 8 65 66 #define HNS3_MAX_PF_NUM 8 67 #define HNS3_UMV_TBL_SIZE 3072 68 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 69 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 70 71 #define HNS3_PF_CFG_BLOCK_SIZE 32 72 #define HNS3_PF_CFG_DESC_NUM \ 73 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 74 75 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 76 77 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 78 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 79 80 #define HNS3_QUIT_RESET_CNT 10 81 #define HNS3_QUIT_RESET_DELAY_MS 100 82 83 #define HNS3_POLL_RESPONE_MS 1 84 85 #define HNS3_MAX_USER_PRIO 8 86 #define HNS3_PG_NUM 4 87 enum hns3_fc_mode { 88 HNS3_FC_NONE, 89 HNS3_FC_RX_PAUSE, 90 HNS3_FC_TX_PAUSE, 91 HNS3_FC_FULL, 92 HNS3_FC_DEFAULT 93 }; 94 95 #define HNS3_SCH_MODE_SP 0 96 #define HNS3_SCH_MODE_DWRR 1 97 struct hns3_pg_info { 98 uint8_t pg_id; 99 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 100 uint8_t tc_bit_map; 101 uint32_t bw_limit; 102 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 103 }; 104 105 struct hns3_tc_info { 106 uint8_t tc_id; 107 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 108 uint8_t pgid; 109 uint32_t bw_limit; 110 uint8_t up_to_tc_map; /* user priority maping on the TC */ 111 }; 112 113 struct hns3_dcb_info { 114 uint8_t num_tc; 115 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 116 uint8_t pg_dwrr[HNS3_PG_NUM]; 117 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 118 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 119 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 120 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 121 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 122 }; 123 124 enum hns3_fc_status { 125 HNS3_FC_STATUS_NONE, 126 HNS3_FC_STATUS_MAC_PAUSE, 127 HNS3_FC_STATUS_PFC, 128 }; 129 130 struct hns3_tc_queue_info { 131 uint8_t tqp_offset; /* TQP offset from base TQP */ 132 uint8_t tqp_count; /* Total TQPs */ 133 uint8_t tc; /* TC index */ 134 bool enable; /* If this TC is enable or not */ 135 }; 136 137 struct hns3_cfg { 138 uint8_t vmdq_vport_num; 139 uint8_t tc_num; 140 uint16_t tqp_desc_num; 141 uint16_t rx_buf_len; 142 uint16_t rss_size_max; 143 uint8_t phy_addr; 144 uint8_t media_type; 145 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 146 uint8_t default_speed; 147 uint32_t numa_node_map; 148 uint8_t speed_ability; 149 uint16_t umv_space; 150 }; 151 152 /* mac media type */ 153 enum hns3_media_type { 154 HNS3_MEDIA_TYPE_UNKNOWN, 155 HNS3_MEDIA_TYPE_FIBER, 156 HNS3_MEDIA_TYPE_COPPER, 157 HNS3_MEDIA_TYPE_BACKPLANE, 158 HNS3_MEDIA_TYPE_NONE, 159 }; 160 161 struct hns3_mac { 162 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 163 bool default_addr_setted; /* whether default addr(mac_addr) is setted */ 164 uint8_t media_type; 165 uint8_t phy_addr; 166 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 167 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 168 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 169 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 170 }; 171 172 struct hns3_fake_queue_data { 173 void **rx_queues; /* Array of pointers to fake RX queues. */ 174 void **tx_queues; /* Array of pointers to fake TX queues. */ 175 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 176 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 177 }; 178 179 #define HNS3_PORT_BASE_VLAN_DISABLE 0 180 #define HNS3_PORT_BASE_VLAN_ENABLE 1 181 struct hns3_port_base_vlan_config { 182 uint16_t state; 183 uint16_t pvid; 184 }; 185 186 /* Primary process maintains driver state in main thread. 187 * 188 * +---------------+ 189 * | UNINITIALIZED |<-----------+ 190 * +---------------+ | 191 * |.eth_dev_init |.eth_dev_uninit 192 * V | 193 * +---------------+------------+ 194 * | INITIALIZED | 195 * +---------------+<-----------<---------------+ 196 * |.dev_configure | | 197 * V |failed | 198 * +---------------+------------+ | 199 * | CONFIGURING | | 200 * +---------------+----+ | 201 * |success | | 202 * | | +---------------+ 203 * | | | CLOSING | 204 * | | +---------------+ 205 * | | ^ 206 * V |.dev_configure | 207 * +---------------+----+ |.dev_close 208 * | CONFIGURED |----------------------------+ 209 * +---------------+<-----------+ 210 * |.dev_start | 211 * V | 212 * +---------------+ | 213 * | STARTING |------------^ 214 * +---------------+ failed | 215 * |success | 216 * | +---------------+ 217 * | | STOPPING | 218 * | +---------------+ 219 * | ^ 220 * V |.dev_stop 221 * +---------------+------------+ 222 * | STARTED | 223 * +---------------+ 224 */ 225 enum hns3_adapter_state { 226 HNS3_NIC_UNINITIALIZED = 0, 227 HNS3_NIC_INITIALIZED, 228 HNS3_NIC_CONFIGURING, 229 HNS3_NIC_CONFIGURED, 230 HNS3_NIC_STARTING, 231 HNS3_NIC_STARTED, 232 HNS3_NIC_STOPPING, 233 HNS3_NIC_CLOSING, 234 HNS3_NIC_CLOSED, 235 HNS3_NIC_REMOVED, 236 HNS3_NIC_NSTATES 237 }; 238 239 /* Reset various stages, execute in order */ 240 enum hns3_reset_stage { 241 /* Stop query services, stop transceiver, disable MAC */ 242 RESET_STAGE_DOWN, 243 /* Clear reset completion flags, disable send command */ 244 RESET_STAGE_PREWAIT, 245 /* Inform IMP to start resetting */ 246 RESET_STAGE_REQ_HW_RESET, 247 /* Waiting for hardware reset to complete */ 248 RESET_STAGE_WAIT, 249 /* Reinitialize hardware */ 250 RESET_STAGE_DEV_INIT, 251 /* Restore user settings and enable MAC */ 252 RESET_STAGE_RESTORE, 253 /* Restart query services, start transceiver */ 254 RESET_STAGE_DONE, 255 /* Not in reset state */ 256 RESET_STAGE_NONE, 257 }; 258 259 enum hns3_reset_level { 260 HNS3_NONE_RESET, 261 HNS3_VF_FUNC_RESET, /* A VF function reset */ 262 /* 263 * All VFs under a PF perform function reset. 264 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 265 * of the reset level and the one defined in kernel driver should be 266 * same. 267 */ 268 HNS3_VF_PF_FUNC_RESET = 2, 269 /* 270 * All VFs under a PF perform FLR reset. 271 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 272 * of the reset level and the one defined in kernel driver should be 273 * same. 274 */ 275 HNS3_VF_FULL_RESET = 3, 276 HNS3_FLR_RESET, /* A VF perform FLR reset */ 277 /* All VFs under the rootport perform a global or IMP reset */ 278 HNS3_VF_RESET, 279 HNS3_FUNC_RESET, /* A PF function reset */ 280 /* All PFs under the rootport perform a global reset */ 281 HNS3_GLOBAL_RESET, 282 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 283 HNS3_MAX_RESET 284 }; 285 286 enum hns3_wait_result { 287 HNS3_WAIT_UNKNOWN, 288 HNS3_WAIT_REQUEST, 289 HNS3_WAIT_SUCCESS, 290 HNS3_WAIT_TIMEOUT 291 }; 292 293 #define HNS3_RESET_SYNC_US 100000 294 295 struct hns3_reset_stats { 296 uint64_t request_cnt; /* Total request reset times */ 297 uint64_t global_cnt; /* Total GLOBAL reset times */ 298 uint64_t imp_cnt; /* Total IMP reset times */ 299 uint64_t exec_cnt; /* Total reset executive times */ 300 uint64_t success_cnt; /* Total reset successful times */ 301 uint64_t fail_cnt; /* Total reset failed times */ 302 uint64_t merge_cnt; /* Total merged in high reset times */ 303 }; 304 305 typedef bool (*check_completion_func)(struct hns3_hw *hw); 306 307 struct hns3_wait_data { 308 void *hns; 309 uint64_t end_ms; 310 uint64_t interval; 311 int16_t count; 312 enum hns3_wait_result result; 313 check_completion_func check_completion; 314 }; 315 316 struct hns3_reset_ops { 317 void (*reset_service)(void *arg); 318 int (*stop_service)(struct hns3_adapter *hns); 319 int (*prepare_reset)(struct hns3_adapter *hns); 320 int (*wait_hardware_ready)(struct hns3_adapter *hns); 321 int (*reinit_dev)(struct hns3_adapter *hns); 322 int (*restore_conf)(struct hns3_adapter *hns); 323 int (*start_service)(struct hns3_adapter *hns); 324 }; 325 326 enum hns3_schedule { 327 SCHEDULE_NONE, 328 SCHEDULE_PENDING, 329 SCHEDULE_REQUESTED, 330 SCHEDULE_DEFERRED, 331 }; 332 333 struct hns3_reset_data { 334 enum hns3_reset_stage stage; 335 rte_atomic16_t schedule; 336 /* Reset flag, covering the entire reset process */ 337 rte_atomic16_t resetting; 338 /* Used to disable sending cmds during reset */ 339 rte_atomic16_t disable_cmd; 340 /* The reset level being processed */ 341 enum hns3_reset_level level; 342 /* Reset level set, each bit represents a reset level */ 343 uint64_t pending; 344 /* Request reset level set, from interrupt or mailbox */ 345 uint64_t request; 346 int attempts; /* Reset failure retry */ 347 int retries; /* Timeout failure retry in reset_post */ 348 /* 349 * At the time of global or IMP reset, the command cannot be sent to 350 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 351 * reset process, so the mbuf is required to be released after the reset 352 * is completed.The mbuf_deferred_free is used to mark whether mbuf 353 * needs to be released. 354 */ 355 bool mbuf_deferred_free; 356 struct timeval start_time; 357 struct hns3_reset_stats stats; 358 const struct hns3_reset_ops *ops; 359 struct hns3_wait_data *wait_data; 360 }; 361 362 struct hns3_hw { 363 struct rte_eth_dev_data *data; 364 void *io_base; 365 uint8_t revision; /* PCI revision, low byte of class word */ 366 struct hns3_cmq cmq; 367 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 368 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ 369 pthread_t irq_thread_id; 370 struct hns3_mac mac; 371 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 372 struct hns3_tqp_stats tqp_stats; 373 /* Include Mac stats | Rx stats | Tx stats */ 374 struct hns3_mac_stats mac_stats; 375 uint32_t fw_version; 376 377 uint16_t num_msi; 378 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 379 uint16_t tqps_num; /* num task queue pairs of this function */ 380 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 381 uint16_t rss_size_max; /* HW defined max RSS task queue */ 382 uint16_t num_tx_desc; /* desc num of per tx queue */ 383 uint16_t num_rx_desc; /* desc num of per rx queue */ 384 385 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 386 int mc_addrs_num; /* Multicast mac addresses number */ 387 388 /* The configuration info of RSS */ 389 struct hns3_rss_conf rss_info; 390 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ 391 392 uint8_t num_tc; /* Total number of enabled TCs */ 393 uint8_t hw_tc_map; 394 enum hns3_fc_mode current_mode; 395 enum hns3_fc_mode requested_mode; 396 struct hns3_dcb_info dcb_info; 397 enum hns3_fc_status current_fc_status; /* current flow control status */ 398 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 399 uint16_t used_rx_queues; 400 uint16_t used_tx_queues; 401 402 /* Config max queue numbers between rx and tx queues from user */ 403 uint16_t cfg_max_queues; 404 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 405 uint16_t alloc_rss_size; /* RX queue number per TC */ 406 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 407 408 uint32_t capability; 409 410 struct hns3_port_base_vlan_config port_base_vlan_cfg; 411 /* 412 * PMD setup and configuration is not thread safe. Since it is not 413 * performance sensitive, it is better to guarantee thread-safety 414 * and add device level lock. Adapter control operations which 415 * change its state should acquire the lock. 416 */ 417 rte_spinlock_t lock; 418 enum hns3_adapter_state adapter_state; 419 struct hns3_reset_data reset; 420 }; 421 422 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 423 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 424 425 struct hns3_err_msix_intr_stats { 426 uint64_t mac_afifo_tnl_intr_cnt; 427 uint64_t ppu_mpf_abnormal_intr_st2_cnt; 428 uint64_t ssu_port_based_pf_intr_cnt; 429 uint64_t ppp_pf_abnormal_intr_cnt; 430 uint64_t ppu_pf_abnormal_intr_cnt; 431 }; 432 433 /* vlan entry information. */ 434 struct hns3_user_vlan_table { 435 LIST_ENTRY(hns3_user_vlan_table) next; 436 bool hd_tbl_status; 437 uint16_t vlan_id; 438 }; 439 440 /* Vlan tag configuration for RX direction */ 441 struct hns3_rx_vtag_cfg { 442 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ 443 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ 444 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ 445 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ 446 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ 447 }; 448 449 /* Vlan tag configuration for TX direction */ 450 struct hns3_tx_vtag_cfg { 451 bool accept_tag1; /* Whether accept tag1 packet from host */ 452 bool accept_untag1; /* Whether accept untag1 packet from host */ 453 bool accept_tag2; 454 bool accept_untag2; 455 bool insert_tag1_en; /* Whether insert inner vlan tag */ 456 bool insert_tag2_en; /* Whether insert outer vlan tag */ 457 uint16_t default_tag1; /* The default inner vlan tag to insert */ 458 uint16_t default_tag2; /* The default outer vlan tag to insert */ 459 }; 460 461 struct hns3_vtag_cfg { 462 struct hns3_rx_vtag_cfg rx_vcfg; 463 struct hns3_tx_vtag_cfg tx_vcfg; 464 }; 465 466 /* Request types for IPC. */ 467 enum hns3_mp_req_type { 468 HNS3_MP_REQ_START_RXTX = 1, 469 HNS3_MP_REQ_STOP_RXTX, 470 HNS3_MP_REQ_MAX 471 }; 472 473 /* Pameters for IPC. */ 474 struct hns3_mp_param { 475 enum hns3_mp_req_type type; 476 int port_id; 477 int result; 478 }; 479 480 /* Request timeout for IPC. */ 481 #define HNS3_MP_REQ_TIMEOUT_SEC 5 482 483 /* Key string for IPC. */ 484 #define HNS3_MP_NAME "net_hns3_mp" 485 486 struct hns3_pf { 487 struct hns3_adapter *adapter; 488 bool is_main_pf; 489 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 490 491 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 492 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 493 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 494 495 uint16_t mps; /* Max packet size */ 496 497 uint8_t tx_sch_mode; 498 uint8_t tc_max; /* max number of tc driver supported */ 499 uint8_t local_max_tc; /* max number of local tc */ 500 uint8_t pfc_max; 501 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 502 uint16_t pause_time; 503 bool support_fc_autoneg; /* support FC autonegotiate */ 504 505 uint16_t wanted_umv_size; 506 uint16_t max_umv_size; 507 uint16_t used_umv_size; 508 509 /* Statistics information for abnormal interrupt */ 510 struct hns3_err_msix_intr_stats abn_int_stats; 511 512 bool support_sfp_query; 513 514 struct hns3_vtag_cfg vtag_config; 515 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 516 517 struct hns3_fdir_info fdir; /* flow director info */ 518 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 519 }; 520 521 struct hns3_vf { 522 struct hns3_adapter *adapter; 523 }; 524 525 struct hns3_adapter { 526 struct hns3_hw hw; 527 528 /* Specific for PF or VF */ 529 bool is_vf; /* false - PF, true - VF */ 530 union { 531 struct hns3_pf pf; 532 struct hns3_vf vf; 533 }; 534 }; 535 536 #define HNS3_DEV_SUPPORT_DCB_B 0x0 537 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 538 539 #define hns3_dev_dcb_supported(hw) \ 540 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) 541 542 #define hns3_dev_copper_supported(hw) \ 543 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) 544 545 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 546 (&((struct hns3_adapter *)adapter)->hw) 547 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \ 548 ((struct hns3_adapter *)adapter) 549 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 550 (&((struct hns3_adapter *)adapter)->pf) 551 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \ 552 (&((struct hns3_adapter *)adapter)->vf) 553 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 554 container_of(hw, struct hns3_adapter, hw) 555 556 #define hns3_set_field(origin, mask, shift, val) \ 557 do { \ 558 (origin) &= (~(mask)); \ 559 (origin) |= ((val) << (shift)) & (mask); \ 560 } while (0) 561 #define hns3_get_field(origin, mask, shift) \ 562 (((origin) & (mask)) >> (shift)) 563 #define hns3_set_bit(origin, shift, val) \ 564 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 565 #define hns3_get_bit(origin, shift) \ 566 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 567 568 /* 569 * upper_32_bits - return bits 32-63 of a number 570 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 571 * the "right shift count >= width of type" warning when that quantity is 572 * 32-bits. 573 */ 574 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 575 576 /* lower_32_bits - return bits 0-31 of a number */ 577 #define lower_32_bits(n) ((uint32_t)(n)) 578 579 #define BIT(nr) (1UL << (nr)) 580 581 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 582 #define GENMASK(h, l) \ 583 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 584 585 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 586 #define rounddown(x, y) ((x) - ((x) % (y))) 587 588 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 589 590 #define max_t(type, x, y) ({ \ 591 type __max1 = (x); \ 592 type __max2 = (y); \ 593 __max1 > __max2 ? __max1 : __max2; }) 594 595 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 596 { 597 rte_write32(value, (volatile void *)((char *)base + reg)); 598 } 599 600 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 601 { 602 return rte_read32((volatile void *)((char *)base + reg)); 603 } 604 605 #define hns3_write_dev(a, reg, value) \ 606 hns3_write_reg((a)->io_base, (reg), (value)) 607 608 #define hns3_read_dev(a, reg) \ 609 hns3_read_reg((a)->io_base, (reg)) 610 611 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 612 613 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 614 do { \ 615 act = (actions) + (index); \ 616 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 617 (index)++; \ 618 act = actions + index; \ 619 } \ 620 } while (0) 621 622 #define MSEC_PER_SEC 1000L 623 #define USEC_PER_MSEC 1000L 624 625 static inline uint64_t 626 get_timeofday_ms(void) 627 { 628 struct timeval tv; 629 630 (void)gettimeofday(&tv, NULL); 631 632 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 633 } 634 635 static inline uint64_t 636 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 637 { 638 uint64_t res; 639 640 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 641 return res; 642 } 643 644 static inline void 645 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 646 { 647 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 648 } 649 650 static inline void 651 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 652 { 653 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 654 } 655 656 static inline int64_t 657 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 658 { 659 uint64_t mask = (1UL << nr); 660 661 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 662 } 663 664 int hns3_buffer_alloc(struct hns3_hw *hw); 665 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, 666 enum rte_filter_type filter_type, 667 enum rte_filter_op filter_op, void *arg); 668 bool hns3_is_reset_pending(struct hns3_adapter *hns); 669 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 670 void hns3_update_link_status(struct hns3_hw *hw); 671 672 static inline bool 673 is_reset_pending(struct hns3_adapter *hns) 674 { 675 bool ret; 676 if (hns->is_vf) 677 ret = hns3vf_is_reset_pending(hns); 678 else 679 ret = hns3_is_reset_pending(hns); 680 return ret; 681 } 682 683 static inline uint64_t 684 hns3_txvlan_cap_get(struct hns3_hw *hw) 685 { 686 if (hw->port_base_vlan_cfg.state) 687 return DEV_TX_OFFLOAD_VLAN_INSERT; 688 else 689 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; 690 } 691 692 #endif /* _HNS3_ETHDEV_H_ */ 693