1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <rte_alarm.h> 10 11 #include "hns3_cmd.h" 12 #include "hns3_mbx.h" 13 #include "hns3_rss.h" 14 #include "hns3_fdir.h" 15 #include "hns3_stats.h" 16 17 /* Vendor ID */ 18 #define PCI_VENDOR_ID_HUAWEI 0x19e5 19 20 /* Device IDs */ 21 #define HNS3_DEV_ID_GE 0xA220 22 #define HNS3_DEV_ID_25GE 0xA221 23 #define HNS3_DEV_ID_25GE_RDMA 0xA222 24 #define HNS3_DEV_ID_50GE_RDMA 0xA224 25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 26 #define HNS3_DEV_ID_100G_VF 0xA22E 27 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 28 29 #define HNS3_UC_MACADDR_NUM 128 30 #define HNS3_VF_UC_MACADDR_NUM 48 31 #define HNS3_MC_MACADDR_NUM 128 32 33 #define HNS3_MAX_BD_SIZE 65535 34 #define HNS3_MAX_TX_BD_PER_PKT 8 35 #define HNS3_MAX_FRAME_LEN 9728 36 #define HNS3_MIN_FRAME_LEN 64 37 #define HNS3_VLAN_TAG_SIZE 4 38 #define HNS3_DEFAULT_RX_BUF_LEN 2048 39 40 #define HNS3_ETH_OVERHEAD \ 41 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 42 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 43 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 44 #define HNS3_DEFAULT_MTU 1500UL 45 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 46 #define HNS3_MIN_PKT_SIZE 60 47 48 #define HNS3_4_TCS 4 49 #define HNS3_8_TCS 8 50 51 #define HNS3_MAX_PF_NUM 8 52 #define HNS3_UMV_TBL_SIZE 3072 53 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 54 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 55 56 #define HNS3_PF_CFG_BLOCK_SIZE 32 57 #define HNS3_PF_CFG_DESC_NUM \ 58 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 59 60 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 61 62 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 63 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 64 65 #define HNS3_QUIT_RESET_CNT 10 66 #define HNS3_QUIT_RESET_DELAY_MS 100 67 68 #define HNS3_POLL_RESPONE_MS 1 69 70 #define HNS3_MAX_USER_PRIO 8 71 #define HNS3_PG_NUM 4 72 enum hns3_fc_mode { 73 HNS3_FC_NONE, 74 HNS3_FC_RX_PAUSE, 75 HNS3_FC_TX_PAUSE, 76 HNS3_FC_FULL, 77 HNS3_FC_DEFAULT 78 }; 79 80 #define HNS3_SCH_MODE_SP 0 81 #define HNS3_SCH_MODE_DWRR 1 82 struct hns3_pg_info { 83 uint8_t pg_id; 84 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 85 uint8_t tc_bit_map; 86 uint32_t bw_limit; 87 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 88 }; 89 90 struct hns3_tc_info { 91 uint8_t tc_id; 92 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 93 uint8_t pgid; 94 uint32_t bw_limit; 95 uint8_t up_to_tc_map; /* user priority maping on the TC */ 96 }; 97 98 struct hns3_dcb_info { 99 uint8_t num_tc; 100 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 101 uint8_t pg_dwrr[HNS3_PG_NUM]; 102 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 103 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 104 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 105 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 106 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 107 }; 108 109 enum hns3_fc_status { 110 HNS3_FC_STATUS_NONE, 111 HNS3_FC_STATUS_MAC_PAUSE, 112 HNS3_FC_STATUS_PFC, 113 }; 114 115 struct hns3_tc_queue_info { 116 uint8_t tqp_offset; /* TQP offset from base TQP */ 117 uint8_t tqp_count; /* Total TQPs */ 118 uint8_t tc; /* TC index */ 119 bool enable; /* If this TC is enable or not */ 120 }; 121 122 struct hns3_cfg { 123 uint8_t vmdq_vport_num; 124 uint8_t tc_num; 125 uint16_t tqp_desc_num; 126 uint16_t rx_buf_len; 127 uint16_t rss_size_max; 128 uint8_t phy_addr; 129 uint8_t media_type; 130 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 131 uint8_t default_speed; 132 uint32_t numa_node_map; 133 uint8_t speed_ability; 134 uint16_t umv_space; 135 }; 136 137 /* mac media type */ 138 enum hns3_media_type { 139 HNS3_MEDIA_TYPE_UNKNOWN, 140 HNS3_MEDIA_TYPE_FIBER, 141 HNS3_MEDIA_TYPE_COPPER, 142 HNS3_MEDIA_TYPE_BACKPLANE, 143 HNS3_MEDIA_TYPE_NONE, 144 }; 145 146 struct hns3_mac { 147 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 148 bool default_addr_setted; /* whether default addr(mac_addr) is setted */ 149 uint8_t media_type; 150 uint8_t phy_addr; 151 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 152 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 153 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 154 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 155 }; 156 157 158 /* Primary process maintains driver state in main thread. 159 * 160 * +---------------+ 161 * | UNINITIALIZED |<-----------+ 162 * +---------------+ | 163 * |.eth_dev_init |.eth_dev_uninit 164 * V | 165 * +---------------+------------+ 166 * | INITIALIZED | 167 * +---------------+<-----------<---------------+ 168 * |.dev_configure | | 169 * V |failed | 170 * +---------------+------------+ | 171 * | CONFIGURING | | 172 * +---------------+----+ | 173 * |success | | 174 * | | +---------------+ 175 * | | | CLOSING | 176 * | | +---------------+ 177 * | | ^ 178 * V |.dev_configure | 179 * +---------------+----+ |.dev_close 180 * | CONFIGURED |----------------------------+ 181 * +---------------+<-----------+ 182 * |.dev_start | 183 * V | 184 * +---------------+ | 185 * | STARTING |------------^ 186 * +---------------+ failed | 187 * |success | 188 * | +---------------+ 189 * | | STOPPING | 190 * | +---------------+ 191 * | ^ 192 * V |.dev_stop 193 * +---------------+------------+ 194 * | STARTED | 195 * +---------------+ 196 */ 197 enum hns3_adapter_state { 198 HNS3_NIC_UNINITIALIZED = 0, 199 HNS3_NIC_INITIALIZED, 200 HNS3_NIC_CONFIGURING, 201 HNS3_NIC_CONFIGURED, 202 HNS3_NIC_STARTING, 203 HNS3_NIC_STARTED, 204 HNS3_NIC_STOPPING, 205 HNS3_NIC_CLOSING, 206 HNS3_NIC_CLOSED, 207 HNS3_NIC_REMOVED, 208 HNS3_NIC_NSTATES 209 }; 210 211 /* Reset various stages, execute in order */ 212 enum hns3_reset_stage { 213 /* Stop query services, stop transceiver, disable MAC */ 214 RESET_STAGE_DOWN, 215 /* Clear reset completion flags, disable send command */ 216 RESET_STAGE_PREWAIT, 217 /* Inform IMP to start resetting */ 218 RESET_STAGE_REQ_HW_RESET, 219 /* Waiting for hardware reset to complete */ 220 RESET_STAGE_WAIT, 221 /* Reinitialize hardware */ 222 RESET_STAGE_DEV_INIT, 223 /* Restore user settings and enable MAC */ 224 RESET_STAGE_RESTORE, 225 /* Restart query services, start transceiver */ 226 RESET_STAGE_DONE, 227 /* Not in reset state */ 228 RESET_STAGE_NONE, 229 }; 230 231 enum hns3_reset_level { 232 HNS3_NONE_RESET, 233 HNS3_VF_FUNC_RESET, /* A VF function reset */ 234 /* 235 * All VFs under a PF perform function reset. 236 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 237 * of the reset level and the one defined in kernel driver should be 238 * same. 239 */ 240 HNS3_VF_PF_FUNC_RESET = 2, 241 /* 242 * All VFs under a PF perform FLR reset. 243 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 244 * of the reset level and the one defined in kernel driver should be 245 * same. 246 */ 247 HNS3_VF_FULL_RESET = 3, 248 HNS3_FLR_RESET, /* A VF perform FLR reset */ 249 /* All VFs under the rootport perform a global or IMP reset */ 250 HNS3_VF_RESET, 251 HNS3_FUNC_RESET, /* A PF function reset */ 252 /* All PFs under the rootport perform a global reset */ 253 HNS3_GLOBAL_RESET, 254 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 255 HNS3_MAX_RESET 256 }; 257 258 enum hns3_wait_result { 259 HNS3_WAIT_UNKNOWN, 260 HNS3_WAIT_REQUEST, 261 HNS3_WAIT_SUCCESS, 262 HNS3_WAIT_TIMEOUT 263 }; 264 265 #define HNS3_RESET_SYNC_US 100000 266 267 struct hns3_reset_stats { 268 uint64_t request_cnt; /* Total request reset times */ 269 uint64_t global_cnt; /* Total GLOBAL reset times */ 270 uint64_t imp_cnt; /* Total IMP reset times */ 271 uint64_t exec_cnt; /* Total reset executive times */ 272 uint64_t success_cnt; /* Total reset successful times */ 273 uint64_t fail_cnt; /* Total reset failed times */ 274 uint64_t merge_cnt; /* Total merged in high reset times */ 275 }; 276 277 typedef bool (*check_completion_func)(struct hns3_hw *hw); 278 279 struct hns3_wait_data { 280 void *hns; 281 uint64_t end_ms; 282 uint64_t interval; 283 int16_t count; 284 enum hns3_wait_result result; 285 check_completion_func check_completion; 286 }; 287 288 struct hns3_reset_ops { 289 void (*reset_service)(void *arg); 290 int (*stop_service)(struct hns3_adapter *hns); 291 int (*prepare_reset)(struct hns3_adapter *hns); 292 int (*wait_hardware_ready)(struct hns3_adapter *hns); 293 int (*reinit_dev)(struct hns3_adapter *hns); 294 int (*restore_conf)(struct hns3_adapter *hns); 295 int (*start_service)(struct hns3_adapter *hns); 296 }; 297 298 enum hns3_schedule { 299 SCHEDULE_NONE, 300 SCHEDULE_PENDING, 301 SCHEDULE_REQUESTED, 302 SCHEDULE_DEFERRED, 303 }; 304 305 struct hns3_reset_data { 306 enum hns3_reset_stage stage; 307 rte_atomic16_t schedule; 308 /* Reset flag, covering the entire reset process */ 309 rte_atomic16_t resetting; 310 /* Used to disable sending cmds during reset */ 311 rte_atomic16_t disable_cmd; 312 /* The reset level being processed */ 313 enum hns3_reset_level level; 314 /* Reset level set, each bit represents a reset level */ 315 uint64_t pending; 316 /* Request reset level set, from interrupt or mailbox */ 317 uint64_t request; 318 int attempts; /* Reset failure retry */ 319 int retries; /* Timeout failure retry in reset_post */ 320 /* 321 * At the time of global or IMP reset, the command cannot be sent to 322 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 323 * reset process, so the mbuf is required to be released after the reset 324 * is completed.The mbuf_deferred_free is used to mark whether mbuf 325 * needs to be released. 326 */ 327 bool mbuf_deferred_free; 328 struct timeval start_time; 329 struct hns3_reset_stats stats; 330 const struct hns3_reset_ops *ops; 331 struct hns3_wait_data *wait_data; 332 }; 333 334 struct hns3_hw { 335 struct rte_eth_dev_data *data; 336 void *io_base; 337 struct hns3_cmq cmq; 338 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 339 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ 340 pthread_t irq_thread_id; 341 struct hns3_mac mac; 342 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 343 struct hns3_tqp_stats tqp_stats; 344 /* Include Mac stats | Rx stats | Tx stats */ 345 struct hns3_mac_stats mac_stats; 346 uint32_t fw_version; 347 348 uint16_t num_msi; 349 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 350 uint16_t tqps_num; /* num task queue pairs of this function */ 351 uint16_t rss_size_max; /* HW defined max RSS task queue */ 352 uint16_t rx_buf_len; 353 uint16_t num_tx_desc; /* desc num of per tx queue */ 354 uint16_t num_rx_desc; /* desc num of per rx queue */ 355 356 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 357 int mc_addrs_num; /* Multicast mac addresses number */ 358 359 /* The configuration info of RSS */ 360 struct hns3_rss_conf rss_info; 361 362 uint8_t num_tc; /* Total number of enabled TCs */ 363 uint8_t hw_tc_map; 364 enum hns3_fc_mode current_mode; 365 enum hns3_fc_mode requested_mode; 366 struct hns3_dcb_info dcb_info; 367 enum hns3_fc_status current_fc_status; /* current flow control status */ 368 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 369 uint16_t alloc_tqps; 370 uint16_t alloc_rss_size; /* Queue number per TC */ 371 372 uint32_t flag; 373 /* 374 * PMD setup and configuration is not thread safe. Since it is not 375 * performance sensitive, it is better to guarantee thread-safety 376 * and add device level lock. Adapter control operations which 377 * change its state should acquire the lock. 378 */ 379 rte_spinlock_t lock; 380 enum hns3_adapter_state adapter_state; 381 struct hns3_reset_data reset; 382 }; 383 384 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 385 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 386 387 struct hns3_err_msix_intr_stats { 388 uint64_t mac_afifo_tnl_intr_cnt; 389 uint64_t ppu_mpf_abnormal_intr_st2_cnt; 390 uint64_t ssu_port_based_pf_intr_cnt; 391 uint64_t ppp_pf_abnormal_intr_cnt; 392 uint64_t ppu_pf_abnormal_intr_cnt; 393 }; 394 395 /* vlan entry information. */ 396 struct hns3_user_vlan_table { 397 LIST_ENTRY(hns3_user_vlan_table) next; 398 bool hd_tbl_status; 399 uint16_t vlan_id; 400 }; 401 402 struct hns3_port_base_vlan_config { 403 uint16_t state; 404 uint16_t pvid; 405 }; 406 407 /* Vlan tag configuration for RX direction */ 408 struct hns3_rx_vtag_cfg { 409 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ 410 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ 411 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ 412 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ 413 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ 414 }; 415 416 /* Vlan tag configuration for TX direction */ 417 struct hns3_tx_vtag_cfg { 418 bool accept_tag1; /* Whether accept tag1 packet from host */ 419 bool accept_untag1; /* Whether accept untag1 packet from host */ 420 bool accept_tag2; 421 bool accept_untag2; 422 bool insert_tag1_en; /* Whether insert inner vlan tag */ 423 bool insert_tag2_en; /* Whether insert outer vlan tag */ 424 uint16_t default_tag1; /* The default inner vlan tag to insert */ 425 uint16_t default_tag2; /* The default outer vlan tag to insert */ 426 }; 427 428 struct hns3_vtag_cfg { 429 struct hns3_rx_vtag_cfg rx_vcfg; 430 struct hns3_tx_vtag_cfg tx_vcfg; 431 }; 432 433 /* Request types for IPC. */ 434 enum hns3_mp_req_type { 435 HNS3_MP_REQ_START_RXTX = 1, 436 HNS3_MP_REQ_STOP_RXTX, 437 HNS3_MP_REQ_MAX 438 }; 439 440 /* Pameters for IPC. */ 441 struct hns3_mp_param { 442 enum hns3_mp_req_type type; 443 int port_id; 444 int result; 445 }; 446 447 /* Request timeout for IPC. */ 448 #define HNS3_MP_REQ_TIMEOUT_SEC 5 449 450 /* Key string for IPC. */ 451 #define HNS3_MP_NAME "net_hns3_mp" 452 453 struct hns3_pf { 454 struct hns3_adapter *adapter; 455 bool is_main_pf; 456 457 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 458 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 459 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 460 461 uint16_t mps; /* Max packet size */ 462 463 uint8_t tx_sch_mode; 464 uint8_t tc_max; /* max number of tc driver supported */ 465 uint8_t local_max_tc; /* max number of local tc */ 466 uint8_t pfc_max; 467 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 468 uint16_t pause_time; 469 bool support_fc_autoneg; /* support FC autonegotiate */ 470 471 uint16_t wanted_umv_size; 472 uint16_t max_umv_size; 473 uint16_t used_umv_size; 474 475 /* Statistics information for abnormal interrupt */ 476 struct hns3_err_msix_intr_stats abn_int_stats; 477 478 bool support_sfp_query; 479 480 struct hns3_vtag_cfg vtag_config; 481 struct hns3_port_base_vlan_config port_base_vlan_cfg; 482 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 483 484 struct hns3_fdir_info fdir; /* flow director info */ 485 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 486 }; 487 488 struct hns3_vf { 489 struct hns3_adapter *adapter; 490 }; 491 492 struct hns3_adapter { 493 struct hns3_hw hw; 494 495 /* Specific for PF or VF */ 496 bool is_vf; /* false - PF, true - VF */ 497 union { 498 struct hns3_pf pf; 499 struct hns3_vf vf; 500 }; 501 }; 502 503 #define HNS3_DEV_SUPPORT_DCB_B 0x0 504 505 #define hns3_dev_dcb_supported(hw) \ 506 hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B) 507 508 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 509 (&((struct hns3_adapter *)adapter)->hw) 510 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \ 511 ((struct hns3_adapter *)adapter) 512 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 513 (&((struct hns3_adapter *)adapter)->pf) 514 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \ 515 (&((struct hns3_adapter *)adapter)->vf) 516 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 517 container_of(hw, struct hns3_adapter, hw) 518 519 #define hns3_set_field(origin, mask, shift, val) \ 520 do { \ 521 (origin) &= (~(mask)); \ 522 (origin) |= ((val) << (shift)) & (mask); \ 523 } while (0) 524 #define hns3_get_field(origin, mask, shift) \ 525 (((origin) & (mask)) >> (shift)) 526 #define hns3_set_bit(origin, shift, val) \ 527 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 528 #define hns3_get_bit(origin, shift) \ 529 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 530 531 /* 532 * upper_32_bits - return bits 32-63 of a number 533 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 534 * the "right shift count >= width of type" warning when that quantity is 535 * 32-bits. 536 */ 537 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 538 539 /* lower_32_bits - return bits 0-31 of a number */ 540 #define lower_32_bits(n) ((uint32_t)(n)) 541 542 #define BIT(nr) (1UL << (nr)) 543 544 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 545 #define GENMASK(h, l) \ 546 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 547 548 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 549 #define rounddown(x, y) ((x) - ((x) % (y))) 550 551 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 552 553 #define max_t(type, x, y) ({ \ 554 type __max1 = (x); \ 555 type __max2 = (y); \ 556 __max1 > __max2 ? __max1 : __max2; }) 557 558 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 559 { 560 rte_write32(value, (volatile void *)((char *)base + reg)); 561 } 562 563 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 564 { 565 return rte_read32((volatile void *)((char *)base + reg)); 566 } 567 568 #define hns3_write_dev(a, reg, value) \ 569 hns3_write_reg((a)->io_base, (reg), (value)) 570 571 #define hns3_read_dev(a, reg) \ 572 hns3_read_reg((a)->io_base, (reg)) 573 574 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 575 576 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 577 do { \ 578 act = (actions) + (index); \ 579 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 580 (index)++; \ 581 act = actions + index; \ 582 } \ 583 } while (0) 584 585 #define MSEC_PER_SEC 1000L 586 #define USEC_PER_MSEC 1000L 587 588 static inline uint64_t 589 get_timeofday_ms(void) 590 { 591 struct timeval tv; 592 593 (void)gettimeofday(&tv, NULL); 594 595 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 596 } 597 598 static inline uint64_t 599 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 600 { 601 uint64_t res; 602 603 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 604 return res; 605 } 606 607 static inline void 608 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 609 { 610 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 611 } 612 613 static inline void 614 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 615 { 616 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 617 } 618 619 static inline int64_t 620 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 621 { 622 uint64_t mask = (1UL << nr); 623 624 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 625 } 626 627 int hns3_buffer_alloc(struct hns3_hw *hw); 628 int hns3_config_gro(struct hns3_hw *hw, bool en); 629 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, 630 enum rte_filter_type filter_type, 631 enum rte_filter_op filter_op, void *arg); 632 bool hns3_is_reset_pending(struct hns3_adapter *hns); 633 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 634 635 static inline bool 636 is_reset_pending(struct hns3_adapter *hns) 637 { 638 bool ret; 639 if (hns->is_vf) 640 ret = hns3vf_is_reset_pending(hns); 641 else 642 ret = hns3_is_reset_pending(hns); 643 return ret; 644 } 645 646 #endif /* _HNS3_ETHDEV_H_ */ 647