1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <rte_alarm.h> 10 11 #include "hns3_cmd.h" 12 #include "hns3_mbx.h" 13 #include "hns3_rss.h" 14 #include "hns3_fdir.h" 15 #include "hns3_stats.h" 16 17 /* Vendor ID */ 18 #define PCI_VENDOR_ID_HUAWEI 0x19e5 19 20 /* Device IDs */ 21 #define HNS3_DEV_ID_GE 0xA220 22 #define HNS3_DEV_ID_25GE 0xA221 23 #define HNS3_DEV_ID_25GE_RDMA 0xA222 24 #define HNS3_DEV_ID_50GE_RDMA 0xA224 25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 26 #define HNS3_DEV_ID_200G_RDMA 0xA228 27 #define HNS3_DEV_ID_100G_VF 0xA22E 28 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 29 30 /* PCI Config offsets */ 31 #define HNS3_PCI_REVISION_ID 0x08 32 #define HNS3_PCI_REVISION_ID_LEN 1 33 34 #define PCI_REVISION_ID_HIP08_B 0x21 35 #define PCI_REVISION_ID_HIP09_A 0x30 36 37 #define HNS3_PF_FUNC_ID 0 38 #define HNS3_1ST_VF_FUNC_ID 1 39 40 #define HNS3_UC_MACADDR_NUM 128 41 #define HNS3_VF_UC_MACADDR_NUM 48 42 #define HNS3_MC_MACADDR_NUM 128 43 44 #define HNS3_MAX_BD_SIZE 65535 45 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 46 #define HNS3_MAX_TSO_BD_PER_PKT 63 47 #define HNS3_MAX_FRAME_LEN 9728 48 #define HNS3_VLAN_TAG_SIZE 4 49 #define HNS3_DEFAULT_RX_BUF_LEN 2048 50 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 51 #define HNS3_MAX_TSO_HDR_SIZE 512 52 #define HNS3_MAX_TSO_HDR_BD_NUM 3 53 #define HNS3_MAX_LRO_SIZE 64512 54 55 #define HNS3_ETH_OVERHEAD \ 56 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 57 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 58 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 59 #define HNS3_DEFAULT_MTU 1500UL 60 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 61 #define HNS3_HIP08_MIN_TX_PKT_LEN 33 62 #define HNS3_HIP09_MIN_TX_PKT_LEN 9 63 64 #define HNS3_4_TCS 4 65 #define HNS3_8_TCS 8 66 67 #define HNS3_MAX_PF_NUM 8 68 #define HNS3_UMV_TBL_SIZE 3072 69 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 70 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 71 72 #define HNS3_PF_CFG_BLOCK_SIZE 32 73 #define HNS3_PF_CFG_DESC_NUM \ 74 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 75 76 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 77 78 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 79 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 80 81 #define HNS3_QUIT_RESET_CNT 10 82 #define HNS3_QUIT_RESET_DELAY_MS 100 83 84 #define HNS3_POLL_RESPONE_MS 1 85 86 #define HNS3_MAX_USER_PRIO 8 87 #define HNS3_PG_NUM 4 88 enum hns3_fc_mode { 89 HNS3_FC_NONE, 90 HNS3_FC_RX_PAUSE, 91 HNS3_FC_TX_PAUSE, 92 HNS3_FC_FULL, 93 HNS3_FC_DEFAULT 94 }; 95 96 #define HNS3_SCH_MODE_SP 0 97 #define HNS3_SCH_MODE_DWRR 1 98 struct hns3_pg_info { 99 uint8_t pg_id; 100 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 101 uint8_t tc_bit_map; 102 uint32_t bw_limit; 103 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 104 }; 105 106 struct hns3_tc_info { 107 uint8_t tc_id; 108 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 109 uint8_t pgid; 110 uint32_t bw_limit; 111 uint8_t up_to_tc_map; /* user priority maping on the TC */ 112 }; 113 114 struct hns3_dcb_info { 115 uint8_t num_tc; 116 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 117 uint8_t pg_dwrr[HNS3_PG_NUM]; 118 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 119 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 120 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 121 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 122 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 123 }; 124 125 enum hns3_fc_status { 126 HNS3_FC_STATUS_NONE, 127 HNS3_FC_STATUS_MAC_PAUSE, 128 HNS3_FC_STATUS_PFC, 129 }; 130 131 struct hns3_tc_queue_info { 132 uint8_t tqp_offset; /* TQP offset from base TQP */ 133 uint8_t tqp_count; /* Total TQPs */ 134 uint8_t tc; /* TC index */ 135 bool enable; /* If this TC is enable or not */ 136 }; 137 138 struct hns3_cfg { 139 uint8_t vmdq_vport_num; 140 uint8_t tc_num; 141 uint16_t tqp_desc_num; 142 uint16_t rx_buf_len; 143 uint16_t rss_size_max; 144 uint8_t phy_addr; 145 uint8_t media_type; 146 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 147 uint8_t default_speed; 148 uint32_t numa_node_map; 149 uint8_t speed_ability; 150 uint16_t umv_space; 151 }; 152 153 /* mac media type */ 154 enum hns3_media_type { 155 HNS3_MEDIA_TYPE_UNKNOWN, 156 HNS3_MEDIA_TYPE_FIBER, 157 HNS3_MEDIA_TYPE_COPPER, 158 HNS3_MEDIA_TYPE_BACKPLANE, 159 HNS3_MEDIA_TYPE_NONE, 160 }; 161 162 struct hns3_mac { 163 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 164 bool default_addr_setted; /* whether default addr(mac_addr) is setted */ 165 uint8_t media_type; 166 uint8_t phy_addr; 167 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 168 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 169 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 170 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 171 }; 172 173 struct hns3_fake_queue_data { 174 void **rx_queues; /* Array of pointers to fake RX queues. */ 175 void **tx_queues; /* Array of pointers to fake TX queues. */ 176 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 177 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 178 }; 179 180 #define HNS3_PORT_BASE_VLAN_DISABLE 0 181 #define HNS3_PORT_BASE_VLAN_ENABLE 1 182 struct hns3_port_base_vlan_config { 183 uint16_t state; 184 uint16_t pvid; 185 }; 186 187 /* Primary process maintains driver state in main thread. 188 * 189 * +---------------+ 190 * | UNINITIALIZED |<-----------+ 191 * +---------------+ | 192 * |.eth_dev_init |.eth_dev_uninit 193 * V | 194 * +---------------+------------+ 195 * | INITIALIZED | 196 * +---------------+<-----------<---------------+ 197 * |.dev_configure | | 198 * V |failed | 199 * +---------------+------------+ | 200 * | CONFIGURING | | 201 * +---------------+----+ | 202 * |success | | 203 * | | +---------------+ 204 * | | | CLOSING | 205 * | | +---------------+ 206 * | | ^ 207 * V |.dev_configure | 208 * +---------------+----+ |.dev_close 209 * | CONFIGURED |----------------------------+ 210 * +---------------+<-----------+ 211 * |.dev_start | 212 * V | 213 * +---------------+ | 214 * | STARTING |------------^ 215 * +---------------+ failed | 216 * |success | 217 * | +---------------+ 218 * | | STOPPING | 219 * | +---------------+ 220 * | ^ 221 * V |.dev_stop 222 * +---------------+------------+ 223 * | STARTED | 224 * +---------------+ 225 */ 226 enum hns3_adapter_state { 227 HNS3_NIC_UNINITIALIZED = 0, 228 HNS3_NIC_INITIALIZED, 229 HNS3_NIC_CONFIGURING, 230 HNS3_NIC_CONFIGURED, 231 HNS3_NIC_STARTING, 232 HNS3_NIC_STARTED, 233 HNS3_NIC_STOPPING, 234 HNS3_NIC_CLOSING, 235 HNS3_NIC_CLOSED, 236 HNS3_NIC_REMOVED, 237 HNS3_NIC_NSTATES 238 }; 239 240 /* Reset various stages, execute in order */ 241 enum hns3_reset_stage { 242 /* Stop query services, stop transceiver, disable MAC */ 243 RESET_STAGE_DOWN, 244 /* Clear reset completion flags, disable send command */ 245 RESET_STAGE_PREWAIT, 246 /* Inform IMP to start resetting */ 247 RESET_STAGE_REQ_HW_RESET, 248 /* Waiting for hardware reset to complete */ 249 RESET_STAGE_WAIT, 250 /* Reinitialize hardware */ 251 RESET_STAGE_DEV_INIT, 252 /* Restore user settings and enable MAC */ 253 RESET_STAGE_RESTORE, 254 /* Restart query services, start transceiver */ 255 RESET_STAGE_DONE, 256 /* Not in reset state */ 257 RESET_STAGE_NONE, 258 }; 259 260 enum hns3_reset_level { 261 HNS3_NONE_RESET, 262 HNS3_VF_FUNC_RESET, /* A VF function reset */ 263 /* 264 * All VFs under a PF perform function reset. 265 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 266 * of the reset level and the one defined in kernel driver should be 267 * same. 268 */ 269 HNS3_VF_PF_FUNC_RESET = 2, 270 /* 271 * All VFs under a PF perform FLR reset. 272 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 273 * of the reset level and the one defined in kernel driver should be 274 * same. 275 */ 276 HNS3_VF_FULL_RESET = 3, 277 HNS3_FLR_RESET, /* A VF perform FLR reset */ 278 /* All VFs under the rootport perform a global or IMP reset */ 279 HNS3_VF_RESET, 280 HNS3_FUNC_RESET, /* A PF function reset */ 281 /* All PFs under the rootport perform a global reset */ 282 HNS3_GLOBAL_RESET, 283 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 284 HNS3_MAX_RESET 285 }; 286 287 enum hns3_wait_result { 288 HNS3_WAIT_UNKNOWN, 289 HNS3_WAIT_REQUEST, 290 HNS3_WAIT_SUCCESS, 291 HNS3_WAIT_TIMEOUT 292 }; 293 294 #define HNS3_RESET_SYNC_US 100000 295 296 struct hns3_reset_stats { 297 uint64_t request_cnt; /* Total request reset times */ 298 uint64_t global_cnt; /* Total GLOBAL reset times */ 299 uint64_t imp_cnt; /* Total IMP reset times */ 300 uint64_t exec_cnt; /* Total reset executive times */ 301 uint64_t success_cnt; /* Total reset successful times */ 302 uint64_t fail_cnt; /* Total reset failed times */ 303 uint64_t merge_cnt; /* Total merged in high reset times */ 304 }; 305 306 typedef bool (*check_completion_func)(struct hns3_hw *hw); 307 308 struct hns3_wait_data { 309 void *hns; 310 uint64_t end_ms; 311 uint64_t interval; 312 int16_t count; 313 enum hns3_wait_result result; 314 check_completion_func check_completion; 315 }; 316 317 struct hns3_reset_ops { 318 void (*reset_service)(void *arg); 319 int (*stop_service)(struct hns3_adapter *hns); 320 int (*prepare_reset)(struct hns3_adapter *hns); 321 int (*wait_hardware_ready)(struct hns3_adapter *hns); 322 int (*reinit_dev)(struct hns3_adapter *hns); 323 int (*restore_conf)(struct hns3_adapter *hns); 324 int (*start_service)(struct hns3_adapter *hns); 325 }; 326 327 enum hns3_schedule { 328 SCHEDULE_NONE, 329 SCHEDULE_PENDING, 330 SCHEDULE_REQUESTED, 331 SCHEDULE_DEFERRED, 332 }; 333 334 struct hns3_reset_data { 335 enum hns3_reset_stage stage; 336 rte_atomic16_t schedule; 337 /* Reset flag, covering the entire reset process */ 338 rte_atomic16_t resetting; 339 /* Used to disable sending cmds during reset */ 340 rte_atomic16_t disable_cmd; 341 /* The reset level being processed */ 342 enum hns3_reset_level level; 343 /* Reset level set, each bit represents a reset level */ 344 uint64_t pending; 345 /* Request reset level set, from interrupt or mailbox */ 346 uint64_t request; 347 int attempts; /* Reset failure retry */ 348 int retries; /* Timeout failure retry in reset_post */ 349 /* 350 * At the time of global or IMP reset, the command cannot be sent to 351 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 352 * reset process, so the mbuf is required to be released after the reset 353 * is completed.The mbuf_deferred_free is used to mark whether mbuf 354 * needs to be released. 355 */ 356 bool mbuf_deferred_free; 357 struct timeval start_time; 358 struct hns3_reset_stats stats; 359 const struct hns3_reset_ops *ops; 360 struct hns3_wait_data *wait_data; 361 }; 362 363 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 364 #define HNS3_INTR_MAPPING_VEC_ALL 1 365 366 #define HNS3_INTR_COALESCE_NON_QL 0 367 #define HNS3_INTR_COALESCE_QL 1 368 369 #define HNS3_INTR_COALESCE_GL_UINT_2US 0 370 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 371 372 struct hns3_queue_intr { 373 /* 374 * interrupt mapping mode. 375 * value range: 376 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL 377 * 378 * - HNS3_INTR_MAPPING_VEC_RSV_ONE 379 * For some versions of hardware network engine, because of the 380 * hardware constraint, we need implement clearing the mapping 381 * relationship configurations by binding all queues to the last 382 * interrupt vector and reserving the last interrupt vector. This 383 * method results in a decrease of the maximum queues when upper 384 * applications call the rte_eth_dev_configure API function to 385 * enable Rx interrupt. 386 * 387 * - HNS3_INTR_MAPPING_VEC_ALL 388 * PMD driver can map/unmmap all interrupt vectors with queues When 389 * Rx interrupt in enabled. 390 */ 391 uint8_t mapping_mode; 392 /* 393 * interrupt coalesce mode. 394 * value range: 395 * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL 396 * 397 * - HNS3_INTR_COALESCE_NON_QL 398 * For some versions of hardware network engine, hardware doesn't 399 * support QL(quanity limiter) algorithm for interrupt coalesce 400 * of queue's interrupt. 401 * 402 * - HNS3_INTR_COALESCE_QL 403 * In this mode, hardware support QL(quanity limiter) algorithm for 404 * interrupt coalesce of queue's interrupt. 405 */ 406 uint8_t coalesce_mode; 407 /* 408 * The unit of GL(gap limiter) configuration for interrupt coalesce of 409 * queue's interrupt. 410 * value range: 411 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US 412 */ 413 uint8_t gl_unit; 414 }; 415 416 struct hns3_hw { 417 struct rte_eth_dev_data *data; 418 void *io_base; 419 uint8_t revision; /* PCI revision, low byte of class word */ 420 struct hns3_cmq cmq; 421 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 422 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ 423 pthread_t irq_thread_id; 424 struct hns3_mac mac; 425 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 426 struct hns3_tqp_stats tqp_stats; 427 /* Include Mac stats | Rx stats | Tx stats */ 428 struct hns3_mac_stats mac_stats; 429 uint32_t fw_version; 430 431 uint16_t num_msi; 432 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 433 uint16_t tqps_num; /* num task queue pairs of this function */ 434 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 435 uint16_t rss_size_max; /* HW defined max RSS task queue */ 436 uint16_t rx_buf_len; /* hold min hardware rx buf len */ 437 uint16_t num_tx_desc; /* desc num of per tx queue */ 438 uint16_t num_rx_desc; /* desc num of per rx queue */ 439 uint32_t mng_entry_num; /* number of manager table entry */ 440 uint32_t mac_entry_num; /* number of mac-vlan table entry */ 441 442 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 443 int mc_addrs_num; /* Multicast mac addresses number */ 444 445 /* The configuration info of RSS */ 446 struct hns3_rss_conf rss_info; 447 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ 448 uint16_t rss_ind_tbl_size; 449 uint16_t rss_key_size; 450 451 uint8_t num_tc; /* Total number of enabled TCs */ 452 uint8_t hw_tc_map; 453 enum hns3_fc_mode current_mode; 454 enum hns3_fc_mode requested_mode; 455 struct hns3_dcb_info dcb_info; 456 enum hns3_fc_status current_fc_status; /* current flow control status */ 457 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 458 uint16_t used_rx_queues; 459 uint16_t used_tx_queues; 460 461 /* Config max queue numbers between rx and tx queues from user */ 462 uint16_t cfg_max_queues; 463 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 464 uint16_t alloc_rss_size; /* RX queue number per TC */ 465 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 466 467 uint32_t capability; 468 uint32_t max_tm_rate; 469 /* 470 * The minimum length of the packet supported by hardware in the Tx 471 * direction. 472 */ 473 uint32_t min_tx_pkt_len; 474 475 struct hns3_queue_intr intr; 476 477 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 478 479 struct hns3_port_base_vlan_config port_base_vlan_cfg; 480 /* 481 * PMD setup and configuration is not thread safe. Since it is not 482 * performance sensitive, it is better to guarantee thread-safety 483 * and add device level lock. Adapter control operations which 484 * change its state should acquire the lock. 485 */ 486 rte_spinlock_t lock; 487 enum hns3_adapter_state adapter_state; 488 struct hns3_reset_data reset; 489 }; 490 491 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 492 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 493 494 struct hns3_err_msix_intr_stats { 495 uint64_t mac_afifo_tnl_int_cnt; 496 uint64_t ppu_mpf_abn_int_st2_msix_cnt; 497 uint64_t ssu_port_based_pf_int_cnt; 498 uint64_t ppp_pf_abnormal_int_cnt; 499 uint64_t ppu_pf_abnormal_int_msix_cnt; 500 501 uint64_t imp_tcm_ecc_int_cnt; 502 uint64_t cmdq_mem_ecc_int_cnt; 503 uint64_t imp_rd_poison_int_cnt; 504 uint64_t tqp_int_ecc_int_cnt; 505 uint64_t msix_ecc_int_cnt; 506 uint64_t ssu_ecc_multi_bit_int_0_cnt; 507 uint64_t ssu_ecc_multi_bit_int_1_cnt; 508 uint64_t ssu_common_ecc_int_cnt; 509 uint64_t igu_int_cnt; 510 uint64_t ppp_mpf_abnormal_int_st1_cnt; 511 uint64_t ppp_mpf_abnormal_int_st3_cnt; 512 uint64_t ppu_mpf_abnormal_int_st1_cnt; 513 uint64_t ppu_mpf_abn_int_st2_ras_cnt; 514 uint64_t ppu_mpf_abnormal_int_st3_cnt; 515 uint64_t tm_sch_int_cnt; 516 uint64_t qcn_fifo_int_cnt; 517 uint64_t qcn_ecc_int_cnt; 518 uint64_t ncsi_ecc_int_cnt; 519 uint64_t ssu_port_based_err_int_cnt; 520 uint64_t ssu_fifo_overflow_int_cnt; 521 uint64_t ssu_ets_tcg_int_cnt; 522 uint64_t igu_egu_tnl_int_cnt; 523 uint64_t ppu_pf_abnormal_int_ras_cnt; 524 }; 525 526 /* vlan entry information. */ 527 struct hns3_user_vlan_table { 528 LIST_ENTRY(hns3_user_vlan_table) next; 529 bool hd_tbl_status; 530 uint16_t vlan_id; 531 }; 532 533 /* Vlan tag configuration for RX direction */ 534 struct hns3_rx_vtag_cfg { 535 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ 536 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ 537 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ 538 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ 539 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ 540 }; 541 542 /* Vlan tag configuration for TX direction */ 543 struct hns3_tx_vtag_cfg { 544 bool accept_tag1; /* Whether accept tag1 packet from host */ 545 bool accept_untag1; /* Whether accept untag1 packet from host */ 546 bool accept_tag2; 547 bool accept_untag2; 548 bool insert_tag1_en; /* Whether insert inner vlan tag */ 549 bool insert_tag2_en; /* Whether insert outer vlan tag */ 550 uint16_t default_tag1; /* The default inner vlan tag to insert */ 551 uint16_t default_tag2; /* The default outer vlan tag to insert */ 552 }; 553 554 struct hns3_vtag_cfg { 555 struct hns3_rx_vtag_cfg rx_vcfg; 556 struct hns3_tx_vtag_cfg tx_vcfg; 557 }; 558 559 /* Request types for IPC. */ 560 enum hns3_mp_req_type { 561 HNS3_MP_REQ_START_RXTX = 1, 562 HNS3_MP_REQ_STOP_RXTX, 563 HNS3_MP_REQ_MAX 564 }; 565 566 /* Pameters for IPC. */ 567 struct hns3_mp_param { 568 enum hns3_mp_req_type type; 569 int port_id; 570 int result; 571 }; 572 573 /* Request timeout for IPC. */ 574 #define HNS3_MP_REQ_TIMEOUT_SEC 5 575 576 /* Key string for IPC. */ 577 #define HNS3_MP_NAME "net_hns3_mp" 578 579 #define HNS3_L2TBL_NUM 4 580 #define HNS3_L3TBL_NUM 16 581 #define HNS3_L4TBL_NUM 16 582 #define HNS3_OL3TBL_NUM 16 583 #define HNS3_OL4TBL_NUM 16 584 585 struct hns3_ptype_table { 586 uint32_t l2table[HNS3_L2TBL_NUM]; 587 uint32_t l3table[HNS3_L3TBL_NUM]; 588 uint32_t l4table[HNS3_L4TBL_NUM]; 589 uint32_t inner_l2table[HNS3_L2TBL_NUM]; 590 uint32_t inner_l3table[HNS3_L3TBL_NUM]; 591 uint32_t inner_l4table[HNS3_L4TBL_NUM]; 592 uint32_t ol3table[HNS3_OL3TBL_NUM]; 593 uint32_t ol4table[HNS3_OL4TBL_NUM]; 594 }; 595 596 struct hns3_pf { 597 struct hns3_adapter *adapter; 598 bool is_main_pf; 599 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 600 601 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 602 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 603 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 604 605 uint16_t mps; /* Max packet size */ 606 607 uint8_t tx_sch_mode; 608 uint8_t tc_max; /* max number of tc driver supported */ 609 uint8_t local_max_tc; /* max number of local tc */ 610 uint8_t pfc_max; 611 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 612 uint16_t pause_time; 613 bool support_fc_autoneg; /* support FC autonegotiate */ 614 615 uint16_t wanted_umv_size; 616 uint16_t max_umv_size; 617 uint16_t used_umv_size; 618 619 /* Statistics information for abnormal interrupt */ 620 struct hns3_err_msix_intr_stats abn_int_stats; 621 622 bool support_sfp_query; 623 624 struct hns3_vtag_cfg vtag_config; 625 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 626 627 struct hns3_fdir_info fdir; /* flow director info */ 628 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 629 }; 630 631 struct hns3_vf { 632 struct hns3_adapter *adapter; 633 }; 634 635 struct hns3_adapter { 636 struct hns3_hw hw; 637 638 /* Specific for PF or VF */ 639 bool is_vf; /* false - PF, true - VF */ 640 union { 641 struct hns3_pf pf; 642 struct hns3_vf vf; 643 }; 644 645 bool rx_simple_allowed; 646 bool rx_vec_allowed; 647 bool tx_simple_allowed; 648 bool tx_vec_allowed; 649 650 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; 651 }; 652 653 #define HNS3_DEV_SUPPORT_DCB_B 0x0 654 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 655 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 656 #define HNS3_DEV_SUPPORT_ADQ_B 0x3 657 #define HNS3_DEV_SUPPORT_PTP_B 0x4 658 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 659 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 660 #define HNS3_DEV_SUPPORT_STASH_B 0x7 661 662 #define hns3_dev_dcb_supported(hw) \ 663 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) 664 665 /* Support copper media type */ 666 #define hns3_dev_copper_supported(hw) \ 667 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) 668 669 /* Support UDP GSO offload */ 670 #define hns3_dev_udp_gso_supported(hw) \ 671 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) 672 673 /* Support Application Device Queue */ 674 #define hns3_dev_adq_supported(hw) \ 675 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B) 676 677 /* Support PTP timestamp offload */ 678 #define hns3_dev_ptp_supported(hw) \ 679 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) 680 681 #define hns3_dev_tx_push_supported(hw) \ 682 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) 683 684 /* Support to Independently enable/disable/reset Tx or Rx queues */ 685 #define hns3_dev_indep_txrx_supported(hw) \ 686 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) 687 688 #define hns3_dev_stash_supported(hw) \ 689 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) 690 691 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 692 (&((struct hns3_adapter *)adapter)->hw) 693 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \ 694 ((struct hns3_adapter *)adapter) 695 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 696 (&((struct hns3_adapter *)adapter)->pf) 697 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \ 698 (&((struct hns3_adapter *)adapter)->vf) 699 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 700 container_of(hw, struct hns3_adapter, hw) 701 702 #define hns3_set_field(origin, mask, shift, val) \ 703 do { \ 704 (origin) &= (~(mask)); \ 705 (origin) |= ((val) << (shift)) & (mask); \ 706 } while (0) 707 #define hns3_get_field(origin, mask, shift) \ 708 (((origin) & (mask)) >> (shift)) 709 #define hns3_set_bit(origin, shift, val) \ 710 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 711 #define hns3_get_bit(origin, shift) \ 712 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 713 714 /* 715 * upper_32_bits - return bits 32-63 of a number 716 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 717 * the "right shift count >= width of type" warning when that quantity is 718 * 32-bits. 719 */ 720 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 721 722 /* lower_32_bits - return bits 0-31 of a number */ 723 #define lower_32_bits(n) ((uint32_t)(n)) 724 725 #define BIT(nr) (1UL << (nr)) 726 727 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 728 #define GENMASK(h, l) \ 729 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 730 731 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 732 #define rounddown(x, y) ((x) - ((x) % (y))) 733 734 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 735 736 /* 737 * Because hardware always access register in little-endian mode based on hns3 738 * network engine, so driver should also call rte_cpu_to_le_32 to convert data 739 * in little-endian mode before writing register and call rte_le_to_cpu_32 to 740 * convert data after reading from register. 741 * 742 * Here the driver encapsulates the data conversion operation in the register 743 * read/write operation function as below: 744 * hns3_write_reg 745 * hns3_write_reg_opt 746 * hns3_read_reg 747 * Therefore, when calling these functions, conversion is not required again. 748 */ 749 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 750 { 751 rte_write32(rte_cpu_to_le_32(value), 752 (volatile void *)((char *)base + reg)); 753 } 754 755 /* 756 * The optimized function for writing registers used in the '.rx_pkt_burst' and 757 * '.tx_pkt_burst' ops implementation function. 758 */ 759 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) 760 { 761 rte_io_wmb(); 762 rte_write32_relaxed(rte_cpu_to_le_32(value), addr); 763 } 764 765 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 766 { 767 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); 768 return rte_le_to_cpu_32(read_val); 769 } 770 771 #define hns3_write_dev(a, reg, value) \ 772 hns3_write_reg((a)->io_base, (reg), (value)) 773 774 #define hns3_read_dev(a, reg) \ 775 hns3_read_reg((a)->io_base, (reg)) 776 777 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 778 779 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 780 do { \ 781 act = (actions) + (index); \ 782 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 783 (index)++; \ 784 act = actions + index; \ 785 } \ 786 } while (0) 787 788 #define MSEC_PER_SEC 1000L 789 #define USEC_PER_MSEC 1000L 790 791 static inline uint64_t 792 get_timeofday_ms(void) 793 { 794 struct timeval tv; 795 796 (void)gettimeofday(&tv, NULL); 797 798 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 799 } 800 801 static inline uint64_t 802 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 803 { 804 uint64_t res; 805 806 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 807 return res; 808 } 809 810 static inline void 811 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 812 { 813 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 814 } 815 816 static inline void 817 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 818 { 819 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 820 } 821 822 static inline int64_t 823 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 824 { 825 uint64_t mask = (1UL << nr); 826 827 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 828 } 829 830 int hns3_buffer_alloc(struct hns3_hw *hw); 831 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, 832 enum rte_filter_type filter_type, 833 enum rte_filter_op filter_op, void *arg); 834 bool hns3_is_reset_pending(struct hns3_adapter *hns); 835 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 836 void hns3_update_link_status(struct hns3_hw *hw); 837 838 static inline bool 839 is_reset_pending(struct hns3_adapter *hns) 840 { 841 bool ret; 842 if (hns->is_vf) 843 ret = hns3vf_is_reset_pending(hns); 844 else 845 ret = hns3_is_reset_pending(hns); 846 return ret; 847 } 848 849 static inline uint64_t 850 hns3_txvlan_cap_get(struct hns3_hw *hw) 851 { 852 if (hw->port_base_vlan_cfg.state) 853 return DEV_TX_OFFLOAD_VLAN_INSERT; 854 else 855 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; 856 } 857 858 #endif /* _HNS3_ETHDEV_H_ */ 859