1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <ethdev_driver.h> 10 #include <rte_byteorder.h> 11 #include <rte_io.h> 12 #include <rte_spinlock.h> 13 14 #include "hns3_cmd.h" 15 #include "hns3_mbx.h" 16 #include "hns3_rss.h" 17 #include "hns3_fdir.h" 18 #include "hns3_stats.h" 19 #include "hns3_tm.h" 20 21 /* Vendor ID */ 22 #define PCI_VENDOR_ID_HUAWEI 0x19e5 23 24 /* Device IDs */ 25 #define HNS3_DEV_ID_GE 0xA220 26 #define HNS3_DEV_ID_25GE 0xA221 27 #define HNS3_DEV_ID_25GE_RDMA 0xA222 28 #define HNS3_DEV_ID_50GE_RDMA 0xA224 29 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 30 #define HNS3_DEV_ID_200G_RDMA 0xA228 31 #define HNS3_DEV_ID_100G_VF 0xA22E 32 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 33 34 /* PCI Config offsets */ 35 #define HNS3_PCI_REVISION_ID 0x08 36 #define HNS3_PCI_REVISION_ID_LEN 1 37 38 #define PCI_REVISION_ID_HIP08_B 0x21 39 #define PCI_REVISION_ID_HIP09_A 0x30 40 41 #define HNS3_PF_FUNC_ID 0 42 #define HNS3_1ST_VF_FUNC_ID 1 43 44 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 45 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 46 47 #define HNS3_UNLIMIT_PROMISC_MODE 0 48 #define HNS3_LIMIT_PROMISC_MODE 1 49 50 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0 51 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1 52 53 #define HNS3_UC_MACADDR_NUM 128 54 #define HNS3_VF_UC_MACADDR_NUM 48 55 #define HNS3_MC_MACADDR_NUM 128 56 57 #define HNS3_MAX_BD_SIZE 65535 58 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 59 #define HNS3_MAX_TSO_BD_PER_PKT 63 60 #define HNS3_MAX_FRAME_LEN 9728 61 #define HNS3_VLAN_TAG_SIZE 4 62 #define HNS3_DEFAULT_RX_BUF_LEN 2048 63 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 64 #define HNS3_MAX_TSO_HDR_SIZE 512 65 #define HNS3_MAX_TSO_HDR_BD_NUM 3 66 #define HNS3_MAX_LRO_SIZE 64512 67 68 #define HNS3_ETH_OVERHEAD \ 69 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 70 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 71 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 72 #define HNS3_DEFAULT_MTU 1500UL 73 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 74 #define HNS3_HIP08_MIN_TX_PKT_LEN 33 75 #define HNS3_HIP09_MIN_TX_PKT_LEN 9 76 77 #define HNS3_BITS_PER_BYTE 8 78 79 #define HNS3_4_TCS 4 80 #define HNS3_8_TCS 8 81 82 #define HNS3_MAX_PF_NUM 8 83 #define HNS3_UMV_TBL_SIZE 3072 84 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 85 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 86 87 #define HNS3_PF_CFG_BLOCK_SIZE 32 88 #define HNS3_PF_CFG_DESC_NUM \ 89 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 90 91 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 92 93 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 94 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 95 96 #define HNS3_QUIT_RESET_CNT 10 97 #define HNS3_QUIT_RESET_DELAY_MS 100 98 99 #define HNS3_POLL_RESPONE_MS 1 100 101 #define HNS3_MAX_USER_PRIO 8 102 #define HNS3_PG_NUM 4 103 enum hns3_fc_mode { 104 HNS3_FC_NONE, 105 HNS3_FC_RX_PAUSE, 106 HNS3_FC_TX_PAUSE, 107 HNS3_FC_FULL, 108 HNS3_FC_DEFAULT 109 }; 110 111 #define HNS3_SCH_MODE_SP 0 112 #define HNS3_SCH_MODE_DWRR 1 113 struct hns3_pg_info { 114 uint8_t pg_id; 115 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 116 uint8_t tc_bit_map; 117 uint32_t bw_limit; 118 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 119 }; 120 121 struct hns3_tc_info { 122 uint8_t tc_id; 123 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 124 uint8_t pgid; 125 uint32_t bw_limit; 126 uint8_t up_to_tc_map; /* user priority maping on the TC */ 127 }; 128 129 struct hns3_dcb_info { 130 uint8_t num_tc; 131 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 132 uint8_t pg_dwrr[HNS3_PG_NUM]; 133 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 134 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 135 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 136 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 137 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 138 }; 139 140 enum hns3_fc_status { 141 HNS3_FC_STATUS_NONE, 142 HNS3_FC_STATUS_MAC_PAUSE, 143 HNS3_FC_STATUS_PFC, 144 }; 145 146 struct hns3_tc_queue_info { 147 uint16_t tqp_offset; /* TQP offset from base TQP */ 148 uint16_t tqp_count; /* Total TQPs */ 149 uint8_t tc; /* TC index */ 150 bool enable; /* If this TC is enable or not */ 151 }; 152 153 struct hns3_cfg { 154 uint8_t vmdq_vport_num; 155 uint8_t tc_num; 156 uint16_t tqp_desc_num; 157 uint16_t rx_buf_len; 158 uint16_t rss_size_max; 159 uint8_t phy_addr; 160 uint8_t media_type; 161 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 162 uint8_t default_speed; 163 uint32_t numa_node_map; 164 uint8_t speed_ability; 165 uint16_t umv_space; 166 }; 167 168 /* mac media type */ 169 enum hns3_media_type { 170 HNS3_MEDIA_TYPE_UNKNOWN, 171 HNS3_MEDIA_TYPE_FIBER, 172 HNS3_MEDIA_TYPE_COPPER, 173 HNS3_MEDIA_TYPE_BACKPLANE, 174 HNS3_MEDIA_TYPE_NONE, 175 }; 176 177 struct hns3_mac { 178 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 179 bool default_addr_setted; /* whether default addr(mac_addr) is set */ 180 uint8_t media_type; 181 uint8_t phy_addr; 182 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 183 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 184 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 185 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 186 uint32_t supported_capa; /* supported capability for current media */ 187 uint32_t advertising; /* advertised capability in the local part */ 188 /* advertised capability in the link partner */ 189 uint32_t lp_advertising; 190 uint8_t support_autoneg; 191 }; 192 193 struct hns3_fake_queue_data { 194 void **rx_queues; /* Array of pointers to fake RX queues. */ 195 void **tx_queues; /* Array of pointers to fake TX queues. */ 196 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 197 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 198 }; 199 200 #define HNS3_PORT_BASE_VLAN_DISABLE 0 201 #define HNS3_PORT_BASE_VLAN_ENABLE 1 202 struct hns3_port_base_vlan_config { 203 uint16_t state; 204 uint16_t pvid; 205 }; 206 207 /* Primary process maintains driver state in main thread. 208 * 209 * +---------------+ 210 * | UNINITIALIZED |<-----------+ 211 * +---------------+ | 212 * |.eth_dev_init |.eth_dev_uninit 213 * V | 214 * +---------------+------------+ 215 * | INITIALIZED | 216 * +---------------+<-----------<---------------+ 217 * |.dev_configure | | 218 * V |failed | 219 * +---------------+------------+ | 220 * | CONFIGURING | | 221 * +---------------+----+ | 222 * |success | | 223 * | | +---------------+ 224 * | | | CLOSING | 225 * | | +---------------+ 226 * | | ^ 227 * V |.dev_configure | 228 * +---------------+----+ |.dev_close 229 * | CONFIGURED |----------------------------+ 230 * +---------------+<-----------+ 231 * |.dev_start | 232 * V | 233 * +---------------+ | 234 * | STARTING |------------^ 235 * +---------------+ failed | 236 * |success | 237 * | +---------------+ 238 * | | STOPPING | 239 * | +---------------+ 240 * | ^ 241 * V |.dev_stop 242 * +---------------+------------+ 243 * | STARTED | 244 * +---------------+ 245 */ 246 enum hns3_adapter_state { 247 HNS3_NIC_UNINITIALIZED = 0, 248 HNS3_NIC_INITIALIZED, 249 HNS3_NIC_CONFIGURING, 250 HNS3_NIC_CONFIGURED, 251 HNS3_NIC_STARTING, 252 HNS3_NIC_STARTED, 253 HNS3_NIC_STOPPING, 254 HNS3_NIC_CLOSING, 255 HNS3_NIC_CLOSED, 256 HNS3_NIC_REMOVED, 257 HNS3_NIC_NSTATES 258 }; 259 260 /* Reset various stages, execute in order */ 261 enum hns3_reset_stage { 262 /* Stop query services, stop transceiver, disable MAC */ 263 RESET_STAGE_DOWN, 264 /* Clear reset completion flags, disable send command */ 265 RESET_STAGE_PREWAIT, 266 /* Inform IMP to start resetting */ 267 RESET_STAGE_REQ_HW_RESET, 268 /* Waiting for hardware reset to complete */ 269 RESET_STAGE_WAIT, 270 /* Reinitialize hardware */ 271 RESET_STAGE_DEV_INIT, 272 /* Restore user settings and enable MAC */ 273 RESET_STAGE_RESTORE, 274 /* Restart query services, start transceiver */ 275 RESET_STAGE_DONE, 276 /* Not in reset state */ 277 RESET_STAGE_NONE, 278 }; 279 280 enum hns3_reset_level { 281 HNS3_NONE_RESET, 282 HNS3_VF_FUNC_RESET, /* A VF function reset */ 283 /* 284 * All VFs under a PF perform function reset. 285 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 286 * of the reset level and the one defined in kernel driver should be 287 * same. 288 */ 289 HNS3_VF_PF_FUNC_RESET = 2, 290 /* 291 * All VFs under a PF perform FLR reset. 292 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 293 * of the reset level and the one defined in kernel driver should be 294 * same. 295 * 296 * According to the protocol of PCIe, FLR to a PF resets the PF state as 297 * well as the SR-IOV extended capability including VF Enable which 298 * means that VFs no longer exist. 299 * 300 * In PF FLR, the register state of VF is not reliable, VF's driver 301 * should not access the registers of the VF device. 302 */ 303 HNS3_VF_FULL_RESET = 3, 304 HNS3_FLR_RESET, /* A VF perform FLR reset */ 305 /* All VFs under the rootport perform a global or IMP reset */ 306 HNS3_VF_RESET, 307 HNS3_FUNC_RESET, /* A PF function reset */ 308 /* All PFs under the rootport perform a global reset */ 309 HNS3_GLOBAL_RESET, 310 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 311 HNS3_MAX_RESET 312 }; 313 314 enum hns3_wait_result { 315 HNS3_WAIT_UNKNOWN, 316 HNS3_WAIT_REQUEST, 317 HNS3_WAIT_SUCCESS, 318 HNS3_WAIT_TIMEOUT 319 }; 320 321 #define HNS3_RESET_SYNC_US 100000 322 323 struct hns3_reset_stats { 324 uint64_t request_cnt; /* Total request reset times */ 325 uint64_t global_cnt; /* Total GLOBAL reset times */ 326 uint64_t imp_cnt; /* Total IMP reset times */ 327 uint64_t exec_cnt; /* Total reset executive times */ 328 uint64_t success_cnt; /* Total reset successful times */ 329 uint64_t fail_cnt; /* Total reset failed times */ 330 uint64_t merge_cnt; /* Total merged in high reset times */ 331 }; 332 333 typedef bool (*check_completion_func)(struct hns3_hw *hw); 334 335 struct hns3_wait_data { 336 void *hns; 337 uint64_t end_ms; 338 uint64_t interval; 339 int16_t count; 340 enum hns3_wait_result result; 341 check_completion_func check_completion; 342 }; 343 344 struct hns3_reset_ops { 345 void (*reset_service)(void *arg); 346 int (*stop_service)(struct hns3_adapter *hns); 347 int (*prepare_reset)(struct hns3_adapter *hns); 348 int (*wait_hardware_ready)(struct hns3_adapter *hns); 349 int (*reinit_dev)(struct hns3_adapter *hns); 350 int (*restore_conf)(struct hns3_adapter *hns); 351 int (*start_service)(struct hns3_adapter *hns); 352 }; 353 354 enum hns3_schedule { 355 SCHEDULE_NONE, 356 SCHEDULE_PENDING, 357 SCHEDULE_REQUESTED, 358 SCHEDULE_DEFERRED, 359 }; 360 361 struct hns3_reset_data { 362 enum hns3_reset_stage stage; 363 uint16_t schedule; 364 /* Reset flag, covering the entire reset process */ 365 uint16_t resetting; 366 /* Used to disable sending cmds during reset */ 367 uint16_t disable_cmd; 368 /* The reset level being processed */ 369 enum hns3_reset_level level; 370 /* Reset level set, each bit represents a reset level */ 371 uint64_t pending; 372 /* Request reset level set, from interrupt or mailbox */ 373 uint64_t request; 374 int attempts; /* Reset failure retry */ 375 int retries; /* Timeout failure retry in reset_post */ 376 /* 377 * At the time of global or IMP reset, the command cannot be sent to 378 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 379 * reset process, so the mbuf is required to be released after the reset 380 * is completed.The mbuf_deferred_free is used to mark whether mbuf 381 * needs to be released. 382 */ 383 bool mbuf_deferred_free; 384 struct timeval start_time; 385 struct hns3_reset_stats stats; 386 const struct hns3_reset_ops *ops; 387 struct hns3_wait_data *wait_data; 388 }; 389 390 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 391 #define HNS3_INTR_MAPPING_VEC_ALL 1 392 393 #define HNS3_INTR_COALESCE_GL_UINT_2US 0 394 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 395 396 #define HNS3_INTR_QL_NONE 0 397 398 struct hns3_queue_intr { 399 /* 400 * interrupt mapping mode. 401 * value range: 402 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL 403 * 404 * - HNS3_INTR_MAPPING_VEC_RSV_ONE 405 * For some versions of hardware network engine, because of the 406 * hardware constraint, we need implement clearing the mapping 407 * relationship configurations by binding all queues to the last 408 * interrupt vector and reserving the last interrupt vector. This 409 * method results in a decrease of the maximum queues when upper 410 * applications call the rte_eth_dev_configure API function to 411 * enable Rx interrupt. 412 * 413 * - HNS3_INTR_MAPPING_VEC_ALL 414 * PMD driver can map/unmmap all interrupt vectors with queues When 415 * Rx interrupt in enabled. 416 */ 417 uint8_t mapping_mode; 418 /* 419 * The unit of GL(gap limiter) configuration for interrupt coalesce of 420 * queue's interrupt. 421 * value range: 422 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US 423 */ 424 uint8_t gl_unit; 425 /* The max QL(quantity limiter) value */ 426 uint16_t int_ql_max; 427 }; 428 429 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 430 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 431 432 #define HNS3_PKTS_DROP_STATS_MODE1 0 433 #define HNS3_PKTS_DROP_STATS_MODE2 1 434 435 struct hns3_hw { 436 struct rte_eth_dev_data *data; 437 void *io_base; 438 uint8_t revision; /* PCI revision, low byte of class word */ 439 struct hns3_cmq cmq; 440 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 441 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ 442 struct hns3_mac mac; 443 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 444 struct hns3_tqp_stats tqp_stats; 445 /* Include Mac stats | Rx stats | Tx stats */ 446 struct hns3_mac_stats mac_stats; 447 struct hns3_rx_missed_stats imissed_stats; 448 uint64_t oerror_stats; 449 uint32_t fw_version; 450 451 uint16_t num_msi; 452 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 453 uint16_t tqps_num; /* num task queue pairs of this function */ 454 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 455 uint16_t rss_size_max; /* HW defined max RSS task queue */ 456 uint16_t rx_buf_len; /* hold min hardware rx buf len */ 457 uint16_t num_tx_desc; /* desc num of per tx queue */ 458 uint16_t num_rx_desc; /* desc num of per rx queue */ 459 uint32_t mng_entry_num; /* number of manager table entry */ 460 uint32_t mac_entry_num; /* number of mac-vlan table entry */ 461 462 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 463 int mc_addrs_num; /* Multicast mac addresses number */ 464 465 /* The configuration info of RSS */ 466 struct hns3_rss_conf rss_info; 467 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ 468 uint16_t rss_ind_tbl_size; 469 uint16_t rss_key_size; 470 471 uint8_t num_tc; /* Total number of enabled TCs */ 472 uint8_t hw_tc_map; 473 enum hns3_fc_mode current_mode; 474 enum hns3_fc_mode requested_mode; 475 struct hns3_dcb_info dcb_info; 476 enum hns3_fc_status current_fc_status; /* current flow control status */ 477 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 478 uint16_t used_rx_queues; 479 uint16_t used_tx_queues; 480 481 /* Config max queue numbers between rx and tx queues from user */ 482 uint16_t cfg_max_queues; 483 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 484 uint16_t alloc_rss_size; /* RX queue number per TC */ 485 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 486 487 uint32_t capability; 488 uint32_t max_tm_rate; 489 /* 490 * The minimum length of the packet supported by hardware in the Tx 491 * direction. 492 */ 493 uint32_t min_tx_pkt_len; 494 495 struct hns3_queue_intr intr; 496 /* 497 * tso mode. 498 * value range: 499 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 500 * 501 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 502 * In this mode, because of the hardware constraint, network driver 503 * software need erase the L4 len value of the TCP pseudo header 504 * and recalculate the TCP pseudo header checksum of packets that 505 * need TSO. 506 * 507 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 508 * In this mode, hardware support recalculate the TCP pseudo header 509 * checksum of packets that need TSO, so network driver software 510 * not need to recalculate it. 511 */ 512 uint8_t tso_mode; 513 /* 514 * vlan mode. 515 * value range: 516 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE 517 * 518 * - HNS3_SW_SHIFT_AND_DISCARD_MODE 519 * For some versions of hardware network engine, because of the 520 * hardware limitation, PMD driver needs to detect the PVID status 521 * to work with haredware to implement PVID-related functions. 522 * For example, driver need discard the stripped PVID tag to ensure 523 * the PVID will not report to mbuf and shift the inserted VLAN tag 524 * to avoid port based VLAN covering it. 525 * 526 * - HNS3_HW_SHIT_AND_DISCARD_MODE 527 * PMD driver does not need to process PVID-related functions in 528 * I/O process, Hardware will adjust the sequence between port based 529 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by 530 * PVID will be invisible to driver. And in this mode, hns3 is able 531 * to send a multi-layer VLAN packets when hw VLAN insert offload 532 * is enabled. 533 */ 534 uint8_t vlan_mode; 535 /* 536 * promisc mode. 537 * value range: 538 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE 539 * 540 * - HNS3_UNLIMIT_PROMISC_MODE 541 * In this mode, TX unicast promisc will be configured when promisc 542 * is set, driver can receive all the ingress and outgoing traffic. 543 * In the words, all the ingress packets, all the packets sent from 544 * the PF and other VFs on the same physical port. 545 * 546 * - HNS3_LIMIT_PROMISC_MODE 547 * In this mode, TX unicast promisc is shutdown when promisc mode 548 * is set. So, driver will only receive all the ingress traffic. 549 * The packets sent from the PF and other VFs on the same physical 550 * port won't be copied to the function which has set promisc mode. 551 */ 552 uint8_t promisc_mode; 553 554 /* 555 * drop_stats_mode mode. 556 * value range: 557 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 558 * 559 * - HNS3_PKTS_DROP_STATS_MODE1 560 * This mode for kunpeng920. In this mode, port level imissed stats 561 * is supported. It only includes RPU drop stats. 562 * 563 * - HNS3_PKTS_DROP_STATS_MODE2 564 * This mode for kunpeng930. In this mode, imissed stats and oerrors 565 * stats is supported. Function level imissed stats is supported. It 566 * includes RPU drop stats in VF, and includes both RPU drop stats 567 * and SSU drop stats in PF. Oerror stats is also supported in PF. 568 */ 569 uint8_t drop_stats_mode; 570 571 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 572 /* 573 * udp checksum mode. 574 * value range: 575 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE 576 * 577 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE 578 * In this mode, HW can not do checksum for special UDP port like 579 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel 580 * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need 581 * do the checksum for these packets to avoid a checksum error. 582 * 583 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE 584 * In this mode, HW does not have the preceding problems and can 585 * directly calculate the checksum of these UDP packets. 586 */ 587 uint8_t udp_cksum_mode; 588 589 struct hns3_port_base_vlan_config port_base_vlan_cfg; 590 /* 591 * PMD setup and configuration is not thread safe. Since it is not 592 * performance sensitive, it is better to guarantee thread-safety 593 * and add device level lock. Adapter control operations which 594 * change its state should acquire the lock. 595 */ 596 rte_spinlock_t lock; 597 enum hns3_adapter_state adapter_state; 598 struct hns3_reset_data reset; 599 }; 600 601 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 602 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 603 604 /* vlan entry information. */ 605 struct hns3_user_vlan_table { 606 LIST_ENTRY(hns3_user_vlan_table) next; 607 bool hd_tbl_status; 608 uint16_t vlan_id; 609 }; 610 611 /* Vlan tag configuration for RX direction */ 612 struct hns3_rx_vtag_cfg { 613 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 614 bool strip_tag1_en; /* Whether strip inner vlan tag */ 615 bool strip_tag2_en; /* Whether strip outer vlan tag */ 616 /* 617 * If strip_tag_en is enabled, this bit decide whether to map the vlan 618 * tag to descriptor. 619 */ 620 bool strip_tag1_discard_en; 621 bool strip_tag2_discard_en; 622 /* 623 * If this bit is enabled, only map inner/outer priority to descriptor 624 * and the vlan tag is always 0. 625 */ 626 bool vlan1_vlan_prionly; 627 bool vlan2_vlan_prionly; 628 }; 629 630 /* Vlan tag configuration for TX direction */ 631 struct hns3_tx_vtag_cfg { 632 bool accept_tag1; /* Whether accept tag1 packet from host */ 633 bool accept_untag1; /* Whether accept untag1 packet from host */ 634 bool accept_tag2; 635 bool accept_untag2; 636 bool insert_tag1_en; /* Whether insert outer vlan tag */ 637 bool insert_tag2_en; /* Whether insert inner vlan tag */ 638 /* 639 * In shift mode, hw will shift the sequence of port based VLAN and 640 * BD VLAN. 641 */ 642 bool tag_shift_mode_en; /* hw shift vlan tag automatically */ 643 uint16_t default_tag1; /* The default outer vlan tag to insert */ 644 uint16_t default_tag2; /* The default inner vlan tag to insert */ 645 }; 646 647 struct hns3_vtag_cfg { 648 struct hns3_rx_vtag_cfg rx_vcfg; 649 struct hns3_tx_vtag_cfg tx_vcfg; 650 }; 651 652 /* Request types for IPC. */ 653 enum hns3_mp_req_type { 654 HNS3_MP_REQ_START_RXTX = 1, 655 HNS3_MP_REQ_STOP_RXTX, 656 HNS3_MP_REQ_MAX 657 }; 658 659 /* Pameters for IPC. */ 660 struct hns3_mp_param { 661 enum hns3_mp_req_type type; 662 int port_id; 663 int result; 664 }; 665 666 /* Request timeout for IPC. */ 667 #define HNS3_MP_REQ_TIMEOUT_SEC 5 668 669 /* Key string for IPC. */ 670 #define HNS3_MP_NAME "net_hns3_mp" 671 672 #define HNS3_L2TBL_NUM 4 673 #define HNS3_L3TBL_NUM 16 674 #define HNS3_L4TBL_NUM 16 675 #define HNS3_OL2TBL_NUM 4 676 #define HNS3_OL3TBL_NUM 16 677 #define HNS3_OL4TBL_NUM 16 678 #define HNS3_PTYPE_NUM 256 679 680 struct hns3_ptype_table { 681 /* 682 * The next fields used to calc packet-type by the 683 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. 684 */ 685 uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM]; 686 uint32_t l4table[HNS3_L4TBL_NUM]; 687 uint32_t inner_l2table[HNS3_L2TBL_NUM]; 688 uint32_t inner_l3table[HNS3_L3TBL_NUM]; 689 uint32_t inner_l4table[HNS3_L4TBL_NUM]; 690 uint32_t ol2table[HNS3_OL2TBL_NUM]; 691 uint32_t ol3table[HNS3_OL3TBL_NUM]; 692 uint32_t ol4table[HNS3_OL4TBL_NUM]; 693 694 /* 695 * The next field used to calc packet-type by the PTYPE from the Rx 696 * descriptor, it functions only when firmware report the capability of 697 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it. 698 */ 699 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned; 700 }; 701 702 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0 703 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1 704 705 struct hns3_pf { 706 struct hns3_adapter *adapter; 707 bool is_main_pf; 708 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 709 710 /* 711 * tqp_config mode 712 * tqp_config_mode value range: 713 * HNS3_FIXED_MAX_TQP_NUM_MODE, 714 * HNS3_FLEX_MAX_TQP_NUM_MODE 715 * 716 * - HNS3_FIXED_MAX_TQP_NUM_MODE 717 * There is a limitation on the number of pf interrupts available for 718 * on some versions of network engines. In this case, the maximum 719 * queue number of pf can not be greater than the interrupt number, 720 * such as pf of network engine with revision_id 0x21. So the maximum 721 * number of queues must be fixed. 722 * 723 * - HNS3_FLEX_MAX_TQP_NUM_MODE 724 * In this mode, the maximum queue number of pf has not any constraint 725 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 726 * in the config file. Users can modify the macro according to their 727 * own application scenarios, which is more flexible to use. 728 */ 729 uint8_t tqp_config_mode; 730 731 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 732 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 733 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 734 735 uint16_t mps; /* Max packet size */ 736 737 uint8_t tx_sch_mode; 738 uint8_t tc_max; /* max number of tc driver supported */ 739 uint8_t local_max_tc; /* max number of local tc */ 740 uint8_t pfc_max; 741 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 742 uint16_t pause_time; 743 bool support_fc_autoneg; /* support FC autonegotiate */ 744 745 uint16_t wanted_umv_size; 746 uint16_t max_umv_size; 747 uint16_t used_umv_size; 748 749 bool support_sfp_query; 750 uint32_t fec_mode; /* current FEC mode for ethdev */ 751 752 bool ptp_enable; 753 754 /* Stores timestamp of last received packet on dev */ 755 uint64_t rx_timestamp; 756 757 struct hns3_vtag_cfg vtag_config; 758 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 759 760 struct hns3_fdir_info fdir; /* flow director info */ 761 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 762 763 struct hns3_tm_conf tm_conf; 764 }; 765 766 struct hns3_vf { 767 struct hns3_adapter *adapter; 768 }; 769 770 struct hns3_adapter { 771 struct hns3_hw hw; 772 773 /* Specific for PF or VF */ 774 bool is_vf; /* false - PF, true - VF */ 775 union { 776 struct hns3_pf pf; 777 struct hns3_vf vf; 778 }; 779 780 bool rx_simple_allowed; 781 bool rx_vec_allowed; 782 bool tx_simple_allowed; 783 bool tx_vec_allowed; 784 785 uint32_t rx_func_hint; 786 uint32_t tx_func_hint; 787 788 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; 789 }; 790 791 enum { 792 HNS3_IO_FUNC_HINT_NONE = 0, 793 HNS3_IO_FUNC_HINT_VEC, 794 HNS3_IO_FUNC_HINT_SVE, 795 HNS3_IO_FUNC_HINT_SIMPLE, 796 HNS3_IO_FUNC_HINT_COMMON 797 }; 798 799 #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" 800 #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" 801 802 #define HNS3_DEV_SUPPORT_DCB_B 0x0 803 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 804 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 805 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 806 #define HNS3_DEV_SUPPORT_PTP_B 0x4 807 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 808 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 809 #define HNS3_DEV_SUPPORT_STASH_B 0x7 810 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 811 #define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA 812 813 #define hns3_dev_dcb_supported(hw) \ 814 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) 815 816 /* Support copper media type */ 817 #define hns3_dev_copper_supported(hw) \ 818 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) 819 820 /* Support UDP GSO offload */ 821 #define hns3_dev_udp_gso_supported(hw) \ 822 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) 823 824 /* Support the queue region action rule of flow directory */ 825 #define hns3_dev_fd_queue_region_supported(hw) \ 826 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) 827 828 /* Support PTP timestamp offload */ 829 #define hns3_dev_ptp_supported(hw) \ 830 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) 831 832 #define hns3_dev_tx_push_supported(hw) \ 833 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) 834 835 /* Support to Independently enable/disable/reset Tx or Rx queues */ 836 #define hns3_dev_indep_txrx_supported(hw) \ 837 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) 838 839 #define hns3_dev_stash_supported(hw) \ 840 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) 841 842 #define hns3_dev_rxd_adv_layout_supported(hw) \ 843 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) 844 845 #define hns3_dev_outer_udp_cksum_supported(hw) \ 846 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) 847 848 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 849 (&((struct hns3_adapter *)adapter)->hw) 850 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 851 (&((struct hns3_adapter *)adapter)->pf) 852 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 853 container_of(hw, struct hns3_adapter, hw) 854 855 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) 856 { 857 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 858 return &adapter->pf; 859 } 860 861 #define hns3_set_field(origin, mask, shift, val) \ 862 do { \ 863 (origin) &= (~(mask)); \ 864 (origin) |= ((val) << (shift)) & (mask); \ 865 } while (0) 866 #define hns3_get_field(origin, mask, shift) \ 867 (((origin) & (mask)) >> (shift)) 868 #define hns3_set_bit(origin, shift, val) \ 869 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 870 #define hns3_get_bit(origin, shift) \ 871 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 872 873 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) 874 875 /* 876 * upper_32_bits - return bits 32-63 of a number 877 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 878 * the "right shift count >= width of type" warning when that quantity is 879 * 32-bits. 880 */ 881 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 882 883 /* lower_32_bits - return bits 0-31 of a number */ 884 #define lower_32_bits(n) ((uint32_t)(n)) 885 886 #define BIT(nr) (1UL << (nr)) 887 888 #define BIT_ULL(x) (1ULL << (x)) 889 890 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 891 #define GENMASK(h, l) \ 892 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 893 894 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 895 #define rounddown(x, y) ((x) - ((x) % (y))) 896 897 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 898 899 /* 900 * Because hardware always access register in little-endian mode based on hns3 901 * network engine, so driver should also call rte_cpu_to_le_32 to convert data 902 * in little-endian mode before writing register and call rte_le_to_cpu_32 to 903 * convert data after reading from register. 904 * 905 * Here the driver encapsulates the data conversion operation in the register 906 * read/write operation function as below: 907 * hns3_write_reg 908 * hns3_write_reg_opt 909 * hns3_read_reg 910 * Therefore, when calling these functions, conversion is not required again. 911 */ 912 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 913 { 914 rte_write32(rte_cpu_to_le_32(value), 915 (volatile void *)((char *)base + reg)); 916 } 917 918 /* 919 * The optimized function for writing registers used in the '.rx_pkt_burst' and 920 * '.tx_pkt_burst' ops implementation function. 921 */ 922 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) 923 { 924 rte_io_wmb(); 925 rte_write32_relaxed(rte_cpu_to_le_32(value), addr); 926 } 927 928 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 929 { 930 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); 931 return rte_le_to_cpu_32(read_val); 932 } 933 934 #define hns3_write_dev(a, reg, value) \ 935 hns3_write_reg((a)->io_base, (reg), (value)) 936 937 #define hns3_read_dev(a, reg) \ 938 hns3_read_reg((a)->io_base, (reg)) 939 940 #define ARRAY_SIZE(x) RTE_DIM(x) 941 942 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 943 do { \ 944 act = (actions) + (index); \ 945 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 946 (index)++; \ 947 act = actions + index; \ 948 } \ 949 } while (0) 950 951 #define MSEC_PER_SEC 1000L 952 #define USEC_PER_MSEC 1000L 953 954 static inline uint64_t 955 get_timeofday_ms(void) 956 { 957 struct timeval tv; 958 959 (void)gettimeofday(&tv, NULL); 960 961 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 962 } 963 964 static inline uint64_t 965 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 966 { 967 uint64_t res; 968 969 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 970 return res; 971 } 972 973 static inline void 974 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 975 { 976 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 977 } 978 979 static inline void 980 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 981 { 982 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 983 } 984 985 static inline int64_t 986 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 987 { 988 uint64_t mask = (1UL << nr); 989 990 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 991 } 992 993 int hns3_buffer_alloc(struct hns3_hw *hw); 994 int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, 995 const struct rte_flow_ops **ops); 996 bool hns3_is_reset_pending(struct hns3_adapter *hns); 997 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 998 void hns3_update_link_status_and_event(struct hns3_hw *hw); 999 void hns3_ether_format_addr(char *buf, uint16_t size, 1000 const struct rte_ether_addr *ether_addr); 1001 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, 1002 struct rte_eth_dev_info *info); 1003 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1004 uint32_t link_speed, uint8_t link_duplex); 1005 void hns3_parse_devargs(struct rte_eth_dev *dev); 1006 int hns3_restore_ptp(struct hns3_adapter *hns); 1007 int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev, 1008 struct rte_eth_conf *conf); 1009 int hns3_ptp_init(struct hns3_hw *hw); 1010 int hns3_timesync_enable(struct rte_eth_dev *dev); 1011 int hns3_timesync_disable(struct rte_eth_dev *dev); 1012 int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1013 struct timespec *timestamp, 1014 uint32_t flags __rte_unused); 1015 int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1016 struct timespec *timestamp); 1017 int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts); 1018 int hns3_timesync_write_time(struct rte_eth_dev *dev, 1019 const struct timespec *ts); 1020 int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 1021 1022 static inline bool 1023 is_reset_pending(struct hns3_adapter *hns) 1024 { 1025 bool ret; 1026 if (hns->is_vf) 1027 ret = hns3vf_is_reset_pending(hns); 1028 else 1029 ret = hns3_is_reset_pending(hns); 1030 return ret; 1031 } 1032 1033 static inline uint64_t 1034 hns3_txvlan_cap_get(struct hns3_hw *hw) 1035 { 1036 if (hw->port_base_vlan_cfg.state) 1037 return DEV_TX_OFFLOAD_VLAN_INSERT; 1038 else 1039 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; 1040 } 1041 1042 #endif /* _HNS3_ETHDEV_H_ */ 1043