1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <rte_alarm.h> 10 11 #include "hns3_cmd.h" 12 #include "hns3_mbx.h" 13 #include "hns3_rss.h" 14 #include "hns3_fdir.h" 15 #include "hns3_stats.h" 16 17 /* Vendor ID */ 18 #define PCI_VENDOR_ID_HUAWEI 0x19e5 19 20 /* Device IDs */ 21 #define HNS3_DEV_ID_GE 0xA220 22 #define HNS3_DEV_ID_25GE 0xA221 23 #define HNS3_DEV_ID_25GE_RDMA 0xA222 24 #define HNS3_DEV_ID_50GE_RDMA 0xA224 25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 26 #define HNS3_DEV_ID_100G_VF 0xA22E 27 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 28 29 #define HNS3_UC_MACADDR_NUM 128 30 #define HNS3_VF_UC_MACADDR_NUM 48 31 #define HNS3_MC_MACADDR_NUM 128 32 33 #define HNS3_MAX_BD_SIZE 65535 34 #define HNS3_MAX_TX_BD_PER_PKT 8 35 #define HNS3_MAX_FRAME_LEN 9728 36 #define HNS3_MIN_FRAME_LEN 64 37 #define HNS3_VLAN_TAG_SIZE 4 38 #define HNS3_DEFAULT_RX_BUF_LEN 2048 39 40 #define HNS3_ETH_OVERHEAD \ 41 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 42 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 43 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 44 #define HNS3_DEFAULT_MTU 1500UL 45 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 46 47 #define HNS3_4_TCS 4 48 #define HNS3_8_TCS 8 49 50 #define HNS3_MAX_PF_NUM 8 51 #define HNS3_UMV_TBL_SIZE 3072 52 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 53 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 54 55 #define HNS3_PF_CFG_BLOCK_SIZE 32 56 #define HNS3_PF_CFG_DESC_NUM \ 57 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 58 59 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 60 61 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 62 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 63 64 #define HNS3_QUIT_RESET_CNT 10 65 #define HNS3_QUIT_RESET_DELAY_MS 100 66 67 #define HNS3_POLL_RESPONE_MS 1 68 69 #define HNS3_MAX_USER_PRIO 8 70 #define HNS3_PG_NUM 4 71 enum hns3_fc_mode { 72 HNS3_FC_NONE, 73 HNS3_FC_RX_PAUSE, 74 HNS3_FC_TX_PAUSE, 75 HNS3_FC_FULL, 76 HNS3_FC_DEFAULT 77 }; 78 79 #define HNS3_SCH_MODE_SP 0 80 #define HNS3_SCH_MODE_DWRR 1 81 struct hns3_pg_info { 82 uint8_t pg_id; 83 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 84 uint8_t tc_bit_map; 85 uint32_t bw_limit; 86 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 87 }; 88 89 struct hns3_tc_info { 90 uint8_t tc_id; 91 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 92 uint8_t pgid; 93 uint32_t bw_limit; 94 uint8_t up_to_tc_map; /* user priority maping on the TC */ 95 }; 96 97 struct hns3_dcb_info { 98 uint8_t num_tc; 99 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 100 uint8_t pg_dwrr[HNS3_PG_NUM]; 101 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 102 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 103 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 104 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 105 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 106 }; 107 108 enum hns3_fc_status { 109 HNS3_FC_STATUS_NONE, 110 HNS3_FC_STATUS_MAC_PAUSE, 111 HNS3_FC_STATUS_PFC, 112 }; 113 114 struct hns3_tc_queue_info { 115 uint8_t tqp_offset; /* TQP offset from base TQP */ 116 uint8_t tqp_count; /* Total TQPs */ 117 uint8_t tc; /* TC index */ 118 bool enable; /* If this TC is enable or not */ 119 }; 120 121 struct hns3_cfg { 122 uint8_t vmdq_vport_num; 123 uint8_t tc_num; 124 uint16_t tqp_desc_num; 125 uint16_t rx_buf_len; 126 uint16_t rss_size_max; 127 uint8_t phy_addr; 128 uint8_t media_type; 129 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 130 uint8_t default_speed; 131 uint32_t numa_node_map; 132 uint8_t speed_ability; 133 uint16_t umv_space; 134 }; 135 136 /* mac media type */ 137 enum hns3_media_type { 138 HNS3_MEDIA_TYPE_UNKNOWN, 139 HNS3_MEDIA_TYPE_FIBER, 140 HNS3_MEDIA_TYPE_COPPER, 141 HNS3_MEDIA_TYPE_BACKPLANE, 142 HNS3_MEDIA_TYPE_NONE, 143 }; 144 145 struct hns3_mac { 146 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 147 bool default_addr_setted; /* whether default addr(mac_addr) is setted */ 148 uint8_t media_type; 149 uint8_t phy_addr; 150 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 151 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 152 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 153 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 154 }; 155 156 157 /* Primary process maintains driver state in main thread. 158 * 159 * +---------------+ 160 * | UNINITIALIZED |<-----------+ 161 * +---------------+ | 162 * |.eth_dev_init |.eth_dev_uninit 163 * V | 164 * +---------------+------------+ 165 * | INITIALIZED | 166 * +---------------+<-----------<---------------+ 167 * |.dev_configure | | 168 * V |failed | 169 * +---------------+------------+ | 170 * | CONFIGURING | | 171 * +---------------+----+ | 172 * |success | | 173 * | | +---------------+ 174 * | | | CLOSING | 175 * | | +---------------+ 176 * | | ^ 177 * V |.dev_configure | 178 * +---------------+----+ |.dev_close 179 * | CONFIGURED |----------------------------+ 180 * +---------------+<-----------+ 181 * |.dev_start | 182 * V | 183 * +---------------+ | 184 * | STARTING |------------^ 185 * +---------------+ failed | 186 * |success | 187 * | +---------------+ 188 * | | STOPPING | 189 * | +---------------+ 190 * | ^ 191 * V |.dev_stop 192 * +---------------+------------+ 193 * | STARTED | 194 * +---------------+ 195 */ 196 enum hns3_adapter_state { 197 HNS3_NIC_UNINITIALIZED = 0, 198 HNS3_NIC_INITIALIZED, 199 HNS3_NIC_CONFIGURING, 200 HNS3_NIC_CONFIGURED, 201 HNS3_NIC_STARTING, 202 HNS3_NIC_STARTED, 203 HNS3_NIC_STOPPING, 204 HNS3_NIC_CLOSING, 205 HNS3_NIC_CLOSED, 206 HNS3_NIC_REMOVED, 207 HNS3_NIC_NSTATES 208 }; 209 210 /* Reset various stages, execute in order */ 211 enum hns3_reset_stage { 212 /* Stop query services, stop transceiver, disable MAC */ 213 RESET_STAGE_DOWN, 214 /* Clear reset completion flags, disable send command */ 215 RESET_STAGE_PREWAIT, 216 /* Inform IMP to start resetting */ 217 RESET_STAGE_REQ_HW_RESET, 218 /* Waiting for hardware reset to complete */ 219 RESET_STAGE_WAIT, 220 /* Reinitialize hardware */ 221 RESET_STAGE_DEV_INIT, 222 /* Restore user settings and enable MAC */ 223 RESET_STAGE_RESTORE, 224 /* Restart query services, start transceiver */ 225 RESET_STAGE_DONE, 226 /* Not in reset state */ 227 RESET_STAGE_NONE, 228 }; 229 230 enum hns3_reset_level { 231 HNS3_NONE_RESET, 232 HNS3_VF_FUNC_RESET, /* A VF function reset */ 233 /* 234 * All VFs under a PF perform function reset. 235 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 236 * of the reset level and the one defined in kernel driver should be 237 * same. 238 */ 239 HNS3_VF_PF_FUNC_RESET = 2, 240 /* 241 * All VFs under a PF perform FLR reset. 242 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 243 * of the reset level and the one defined in kernel driver should be 244 * same. 245 */ 246 HNS3_VF_FULL_RESET = 3, 247 HNS3_FLR_RESET, /* A VF perform FLR reset */ 248 /* All VFs under the rootport perform a global or IMP reset */ 249 HNS3_VF_RESET, 250 HNS3_FUNC_RESET, /* A PF function reset */ 251 /* All PFs under the rootport perform a global reset */ 252 HNS3_GLOBAL_RESET, 253 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 254 HNS3_MAX_RESET 255 }; 256 257 enum hns3_wait_result { 258 HNS3_WAIT_UNKNOWN, 259 HNS3_WAIT_REQUEST, 260 HNS3_WAIT_SUCCESS, 261 HNS3_WAIT_TIMEOUT 262 }; 263 264 #define HNS3_RESET_SYNC_US 100000 265 266 struct hns3_reset_stats { 267 uint64_t request_cnt; /* Total request reset times */ 268 uint64_t global_cnt; /* Total GLOBAL reset times */ 269 uint64_t imp_cnt; /* Total IMP reset times */ 270 uint64_t exec_cnt; /* Total reset executive times */ 271 uint64_t success_cnt; /* Total reset successful times */ 272 uint64_t fail_cnt; /* Total reset failed times */ 273 uint64_t merge_cnt; /* Total merged in high reset times */ 274 }; 275 276 typedef bool (*check_completion_func)(struct hns3_hw *hw); 277 278 struct hns3_wait_data { 279 void *hns; 280 uint64_t end_ms; 281 uint64_t interval; 282 int16_t count; 283 enum hns3_wait_result result; 284 check_completion_func check_completion; 285 }; 286 287 struct hns3_reset_ops { 288 void (*reset_service)(void *arg); 289 int (*stop_service)(struct hns3_adapter *hns); 290 int (*prepare_reset)(struct hns3_adapter *hns); 291 int (*wait_hardware_ready)(struct hns3_adapter *hns); 292 int (*reinit_dev)(struct hns3_adapter *hns); 293 int (*restore_conf)(struct hns3_adapter *hns); 294 int (*start_service)(struct hns3_adapter *hns); 295 }; 296 297 enum hns3_schedule { 298 SCHEDULE_NONE, 299 SCHEDULE_PENDING, 300 SCHEDULE_REQUESTED, 301 SCHEDULE_DEFERRED, 302 }; 303 304 struct hns3_reset_data { 305 enum hns3_reset_stage stage; 306 rte_atomic16_t schedule; 307 /* Reset flag, covering the entire reset process */ 308 rte_atomic16_t resetting; 309 /* Used to disable sending cmds during reset */ 310 rte_atomic16_t disable_cmd; 311 /* The reset level being processed */ 312 enum hns3_reset_level level; 313 /* Reset level set, each bit represents a reset level */ 314 uint64_t pending; 315 /* Request reset level set, from interrupt or mailbox */ 316 uint64_t request; 317 int attempts; /* Reset failure retry */ 318 int retries; /* Timeout failure retry in reset_post */ 319 /* 320 * At the time of global or IMP reset, the command cannot be sent to 321 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 322 * reset process, so the mbuf is required to be released after the reset 323 * is completed.The mbuf_deferred_free is used to mark whether mbuf 324 * needs to be released. 325 */ 326 bool mbuf_deferred_free; 327 struct timeval start_time; 328 struct hns3_reset_stats stats; 329 const struct hns3_reset_ops *ops; 330 struct hns3_wait_data *wait_data; 331 }; 332 333 struct hns3_hw { 334 struct rte_eth_dev_data *data; 335 void *io_base; 336 struct hns3_cmq cmq; 337 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 338 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ 339 pthread_t irq_thread_id; 340 struct hns3_mac mac; 341 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 342 struct hns3_tqp_stats tqp_stats; 343 /* Include Mac stats | Rx stats | Tx stats */ 344 struct hns3_mac_stats mac_stats; 345 uint32_t fw_version; 346 347 uint16_t num_msi; 348 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 349 uint16_t tqps_num; /* num task queue pairs of this function */ 350 uint16_t rss_size_max; /* HW defined max RSS task queue */ 351 uint16_t rx_buf_len; 352 uint16_t num_tx_desc; /* desc num of per tx queue */ 353 uint16_t num_rx_desc; /* desc num of per rx queue */ 354 355 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 356 int mc_addrs_num; /* Multicast mac addresses number */ 357 358 /* The configuration info of RSS */ 359 struct hns3_rss_conf rss_info; 360 361 uint8_t num_tc; /* Total number of enabled TCs */ 362 uint8_t hw_tc_map; 363 enum hns3_fc_mode current_mode; 364 enum hns3_fc_mode requested_mode; 365 struct hns3_dcb_info dcb_info; 366 enum hns3_fc_status current_fc_status; /* current flow control status */ 367 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 368 uint16_t alloc_tqps; 369 uint16_t alloc_rss_size; /* Queue number per TC */ 370 371 uint32_t flag; 372 /* 373 * PMD setup and configuration is not thread safe. Since it is not 374 * performance sensitive, it is better to guarantee thread-safety 375 * and add device level lock. Adapter control operations which 376 * change its state should acquire the lock. 377 */ 378 rte_spinlock_t lock; 379 enum hns3_adapter_state adapter_state; 380 struct hns3_reset_data reset; 381 }; 382 383 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 384 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 385 386 struct hns3_err_msix_intr_stats { 387 uint64_t mac_afifo_tnl_intr_cnt; 388 uint64_t ppu_mpf_abnormal_intr_st2_cnt; 389 uint64_t ssu_port_based_pf_intr_cnt; 390 uint64_t ppp_pf_abnormal_intr_cnt; 391 uint64_t ppu_pf_abnormal_intr_cnt; 392 }; 393 394 /* vlan entry information. */ 395 struct hns3_user_vlan_table { 396 LIST_ENTRY(hns3_user_vlan_table) next; 397 bool hd_tbl_status; 398 uint16_t vlan_id; 399 }; 400 401 struct hns3_port_base_vlan_config { 402 uint16_t state; 403 uint16_t pvid; 404 }; 405 406 /* Vlan tag configuration for RX direction */ 407 struct hns3_rx_vtag_cfg { 408 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */ 409 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */ 410 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */ 411 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ 412 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ 413 }; 414 415 /* Vlan tag configuration for TX direction */ 416 struct hns3_tx_vtag_cfg { 417 bool accept_tag1; /* Whether accept tag1 packet from host */ 418 bool accept_untag1; /* Whether accept untag1 packet from host */ 419 bool accept_tag2; 420 bool accept_untag2; 421 bool insert_tag1_en; /* Whether insert inner vlan tag */ 422 bool insert_tag2_en; /* Whether insert outer vlan tag */ 423 uint16_t default_tag1; /* The default inner vlan tag to insert */ 424 uint16_t default_tag2; /* The default outer vlan tag to insert */ 425 }; 426 427 struct hns3_vtag_cfg { 428 struct hns3_rx_vtag_cfg rx_vcfg; 429 struct hns3_tx_vtag_cfg tx_vcfg; 430 }; 431 432 /* Request types for IPC. */ 433 enum hns3_mp_req_type { 434 HNS3_MP_REQ_START_RXTX = 1, 435 HNS3_MP_REQ_STOP_RXTX, 436 HNS3_MP_REQ_MAX 437 }; 438 439 /* Pameters for IPC. */ 440 struct hns3_mp_param { 441 enum hns3_mp_req_type type; 442 int port_id; 443 int result; 444 }; 445 446 /* Request timeout for IPC. */ 447 #define HNS3_MP_REQ_TIMEOUT_SEC 5 448 449 /* Key string for IPC. */ 450 #define HNS3_MP_NAME "net_hns3_mp" 451 452 struct hns3_pf { 453 struct hns3_adapter *adapter; 454 bool is_main_pf; 455 456 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 457 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 458 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 459 460 uint16_t mps; /* Max packet size */ 461 462 uint8_t tx_sch_mode; 463 uint8_t tc_max; /* max number of tc driver supported */ 464 uint8_t local_max_tc; /* max number of local tc */ 465 uint8_t pfc_max; 466 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 467 uint16_t pause_time; 468 bool support_fc_autoneg; /* support FC autonegotiate */ 469 470 uint16_t wanted_umv_size; 471 uint16_t max_umv_size; 472 uint16_t used_umv_size; 473 474 /* Statistics information for abnormal interrupt */ 475 struct hns3_err_msix_intr_stats abn_int_stats; 476 477 bool support_sfp_query; 478 479 struct hns3_vtag_cfg vtag_config; 480 struct hns3_port_base_vlan_config port_base_vlan_cfg; 481 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 482 483 struct hns3_fdir_info fdir; /* flow director info */ 484 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 485 }; 486 487 struct hns3_vf { 488 struct hns3_adapter *adapter; 489 }; 490 491 struct hns3_adapter { 492 struct hns3_hw hw; 493 494 /* Specific for PF or VF */ 495 bool is_vf; /* false - PF, true - VF */ 496 union { 497 struct hns3_pf pf; 498 struct hns3_vf vf; 499 }; 500 }; 501 502 #define HNS3_DEV_SUPPORT_DCB_B 0x0 503 504 #define hns3_dev_dcb_supported(hw) \ 505 hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B) 506 507 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 508 (&((struct hns3_adapter *)adapter)->hw) 509 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \ 510 ((struct hns3_adapter *)adapter) 511 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 512 (&((struct hns3_adapter *)adapter)->pf) 513 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \ 514 (&((struct hns3_adapter *)adapter)->vf) 515 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 516 container_of(hw, struct hns3_adapter, hw) 517 518 #define hns3_set_field(origin, mask, shift, val) \ 519 do { \ 520 (origin) &= (~(mask)); \ 521 (origin) |= ((val) << (shift)) & (mask); \ 522 } while (0) 523 #define hns3_get_field(origin, mask, shift) \ 524 (((origin) & (mask)) >> (shift)) 525 #define hns3_set_bit(origin, shift, val) \ 526 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 527 #define hns3_get_bit(origin, shift) \ 528 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 529 530 /* 531 * upper_32_bits - return bits 32-63 of a number 532 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 533 * the "right shift count >= width of type" warning when that quantity is 534 * 32-bits. 535 */ 536 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 537 538 /* lower_32_bits - return bits 0-31 of a number */ 539 #define lower_32_bits(n) ((uint32_t)(n)) 540 541 #define BIT(nr) (1UL << (nr)) 542 543 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 544 #define GENMASK(h, l) \ 545 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 546 547 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 548 #define rounddown(x, y) ((x) - ((x) % (y))) 549 550 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 551 552 #define max_t(type, x, y) ({ \ 553 type __max1 = (x); \ 554 type __max2 = (y); \ 555 __max1 > __max2 ? __max1 : __max2; }) 556 557 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 558 { 559 rte_write32(value, (volatile void *)((char *)base + reg)); 560 } 561 562 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 563 { 564 return rte_read32((volatile void *)((char *)base + reg)); 565 } 566 567 #define hns3_write_dev(a, reg, value) \ 568 hns3_write_reg((a)->io_base, (reg), (value)) 569 570 #define hns3_read_dev(a, reg) \ 571 hns3_read_reg((a)->io_base, (reg)) 572 573 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 574 575 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 576 do { \ 577 act = (actions) + (index); \ 578 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 579 (index)++; \ 580 act = actions + index; \ 581 } \ 582 } while (0) 583 584 #define MSEC_PER_SEC 1000L 585 #define USEC_PER_MSEC 1000L 586 587 static inline uint64_t 588 get_timeofday_ms(void) 589 { 590 struct timeval tv; 591 592 (void)gettimeofday(&tv, NULL); 593 594 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 595 } 596 597 static inline uint64_t 598 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 599 { 600 uint64_t res; 601 602 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 603 return res; 604 } 605 606 static inline void 607 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 608 { 609 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 610 } 611 612 static inline void 613 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 614 { 615 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 616 } 617 618 static inline int64_t 619 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 620 { 621 uint64_t mask = (1UL << nr); 622 623 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 624 } 625 626 int hns3_buffer_alloc(struct hns3_hw *hw); 627 int hns3_config_gro(struct hns3_hw *hw, bool en); 628 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, 629 enum rte_filter_type filter_type, 630 enum rte_filter_op filter_op, void *arg); 631 bool hns3_is_reset_pending(struct hns3_adapter *hns); 632 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 633 634 static inline bool 635 is_reset_pending(struct hns3_adapter *hns) 636 { 637 bool ret; 638 if (hns->is_vf) 639 ret = hns3vf_is_reset_pending(hns); 640 else 641 ret = hns3_is_reset_pending(hns); 642 return ret; 643 } 644 645 #endif /* _HNS3_ETHDEV_H_ */ 646