1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <sys/time.h> 9 #include <ethdev_driver.h> 10 #include <rte_byteorder.h> 11 #include <rte_io.h> 12 #include <rte_spinlock.h> 13 14 #include "hns3_cmd.h" 15 #include "hns3_mbx.h" 16 #include "hns3_rss.h" 17 #include "hns3_fdir.h" 18 #include "hns3_stats.h" 19 #include "hns3_tm.h" 20 21 /* Vendor ID */ 22 #define PCI_VENDOR_ID_HUAWEI 0x19e5 23 24 /* Device IDs */ 25 #define HNS3_DEV_ID_GE 0xA220 26 #define HNS3_DEV_ID_25GE 0xA221 27 #define HNS3_DEV_ID_25GE_RDMA 0xA222 28 #define HNS3_DEV_ID_50GE_RDMA 0xA224 29 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 30 #define HNS3_DEV_ID_200G_RDMA 0xA228 31 #define HNS3_DEV_ID_100G_VF 0xA22E 32 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 33 34 /* PCI Config offsets */ 35 #define HNS3_PCI_REVISION_ID 0x08 36 #define HNS3_PCI_REVISION_ID_LEN 1 37 38 #define PCI_REVISION_ID_HIP08_B 0x21 39 #define PCI_REVISION_ID_HIP09_A 0x30 40 41 #define HNS3_PF_FUNC_ID 0 42 #define HNS3_1ST_VF_FUNC_ID 1 43 44 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 45 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 46 47 #define HNS3_UNLIMIT_PROMISC_MODE 0 48 #define HNS3_LIMIT_PROMISC_MODE 1 49 50 #define HNS3_UC_MACADDR_NUM 128 51 #define HNS3_VF_UC_MACADDR_NUM 48 52 #define HNS3_MC_MACADDR_NUM 128 53 54 #define HNS3_MAX_BD_SIZE 65535 55 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 56 #define HNS3_MAX_TSO_BD_PER_PKT 63 57 #define HNS3_MAX_FRAME_LEN 9728 58 #define HNS3_VLAN_TAG_SIZE 4 59 #define HNS3_DEFAULT_RX_BUF_LEN 2048 60 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 61 #define HNS3_MAX_TSO_HDR_SIZE 512 62 #define HNS3_MAX_TSO_HDR_BD_NUM 3 63 #define HNS3_MAX_LRO_SIZE 64512 64 65 #define HNS3_ETH_OVERHEAD \ 66 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 67 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 68 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 69 #define HNS3_DEFAULT_MTU 1500UL 70 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 71 #define HNS3_HIP08_MIN_TX_PKT_LEN 33 72 #define HNS3_HIP09_MIN_TX_PKT_LEN 9 73 74 #define HNS3_BITS_PER_BYTE 8 75 76 #define HNS3_4_TCS 4 77 #define HNS3_8_TCS 8 78 79 #define HNS3_MAX_PF_NUM 8 80 #define HNS3_UMV_TBL_SIZE 3072 81 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 82 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 83 84 #define HNS3_PF_CFG_BLOCK_SIZE 32 85 #define HNS3_PF_CFG_DESC_NUM \ 86 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 87 88 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 89 90 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 91 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 92 93 #define HNS3_QUIT_RESET_CNT 10 94 #define HNS3_QUIT_RESET_DELAY_MS 100 95 96 #define HNS3_POLL_RESPONE_MS 1 97 98 #define HNS3_MAX_USER_PRIO 8 99 #define HNS3_PG_NUM 4 100 enum hns3_fc_mode { 101 HNS3_FC_NONE, 102 HNS3_FC_RX_PAUSE, 103 HNS3_FC_TX_PAUSE, 104 HNS3_FC_FULL, 105 HNS3_FC_DEFAULT 106 }; 107 108 #define HNS3_SCH_MODE_SP 0 109 #define HNS3_SCH_MODE_DWRR 1 110 struct hns3_pg_info { 111 uint8_t pg_id; 112 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 113 uint8_t tc_bit_map; 114 uint32_t bw_limit; 115 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 116 }; 117 118 struct hns3_tc_info { 119 uint8_t tc_id; 120 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 121 uint8_t pgid; 122 uint32_t bw_limit; 123 uint8_t up_to_tc_map; /* user priority maping on the TC */ 124 }; 125 126 struct hns3_dcb_info { 127 uint8_t num_tc; 128 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 129 uint8_t pg_dwrr[HNS3_PG_NUM]; 130 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 131 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 132 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 133 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 134 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 135 }; 136 137 enum hns3_fc_status { 138 HNS3_FC_STATUS_NONE, 139 HNS3_FC_STATUS_MAC_PAUSE, 140 HNS3_FC_STATUS_PFC, 141 }; 142 143 struct hns3_tc_queue_info { 144 uint16_t tqp_offset; /* TQP offset from base TQP */ 145 uint16_t tqp_count; /* Total TQPs */ 146 uint8_t tc; /* TC index */ 147 bool enable; /* If this TC is enable or not */ 148 }; 149 150 struct hns3_cfg { 151 uint8_t vmdq_vport_num; 152 uint8_t tc_num; 153 uint16_t tqp_desc_num; 154 uint16_t rx_buf_len; 155 uint16_t rss_size_max; 156 uint8_t phy_addr; 157 uint8_t media_type; 158 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 159 uint8_t default_speed; 160 uint32_t numa_node_map; 161 uint8_t speed_ability; 162 uint16_t umv_space; 163 }; 164 165 /* mac media type */ 166 enum hns3_media_type { 167 HNS3_MEDIA_TYPE_UNKNOWN, 168 HNS3_MEDIA_TYPE_FIBER, 169 HNS3_MEDIA_TYPE_COPPER, 170 HNS3_MEDIA_TYPE_BACKPLANE, 171 HNS3_MEDIA_TYPE_NONE, 172 }; 173 174 struct hns3_mac { 175 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 176 bool default_addr_setted; /* whether default addr(mac_addr) is set */ 177 uint8_t media_type; 178 uint8_t phy_addr; 179 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 180 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 181 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 182 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 183 }; 184 185 struct hns3_fake_queue_data { 186 void **rx_queues; /* Array of pointers to fake RX queues. */ 187 void **tx_queues; /* Array of pointers to fake TX queues. */ 188 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 189 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 190 }; 191 192 #define HNS3_PORT_BASE_VLAN_DISABLE 0 193 #define HNS3_PORT_BASE_VLAN_ENABLE 1 194 struct hns3_port_base_vlan_config { 195 uint16_t state; 196 uint16_t pvid; 197 }; 198 199 /* Primary process maintains driver state in main thread. 200 * 201 * +---------------+ 202 * | UNINITIALIZED |<-----------+ 203 * +---------------+ | 204 * |.eth_dev_init |.eth_dev_uninit 205 * V | 206 * +---------------+------------+ 207 * | INITIALIZED | 208 * +---------------+<-----------<---------------+ 209 * |.dev_configure | | 210 * V |failed | 211 * +---------------+------------+ | 212 * | CONFIGURING | | 213 * +---------------+----+ | 214 * |success | | 215 * | | +---------------+ 216 * | | | CLOSING | 217 * | | +---------------+ 218 * | | ^ 219 * V |.dev_configure | 220 * +---------------+----+ |.dev_close 221 * | CONFIGURED |----------------------------+ 222 * +---------------+<-----------+ 223 * |.dev_start | 224 * V | 225 * +---------------+ | 226 * | STARTING |------------^ 227 * +---------------+ failed | 228 * |success | 229 * | +---------------+ 230 * | | STOPPING | 231 * | +---------------+ 232 * | ^ 233 * V |.dev_stop 234 * +---------------+------------+ 235 * | STARTED | 236 * +---------------+ 237 */ 238 enum hns3_adapter_state { 239 HNS3_NIC_UNINITIALIZED = 0, 240 HNS3_NIC_INITIALIZED, 241 HNS3_NIC_CONFIGURING, 242 HNS3_NIC_CONFIGURED, 243 HNS3_NIC_STARTING, 244 HNS3_NIC_STARTED, 245 HNS3_NIC_STOPPING, 246 HNS3_NIC_CLOSING, 247 HNS3_NIC_CLOSED, 248 HNS3_NIC_REMOVED, 249 HNS3_NIC_NSTATES 250 }; 251 252 /* Reset various stages, execute in order */ 253 enum hns3_reset_stage { 254 /* Stop query services, stop transceiver, disable MAC */ 255 RESET_STAGE_DOWN, 256 /* Clear reset completion flags, disable send command */ 257 RESET_STAGE_PREWAIT, 258 /* Inform IMP to start resetting */ 259 RESET_STAGE_REQ_HW_RESET, 260 /* Waiting for hardware reset to complete */ 261 RESET_STAGE_WAIT, 262 /* Reinitialize hardware */ 263 RESET_STAGE_DEV_INIT, 264 /* Restore user settings and enable MAC */ 265 RESET_STAGE_RESTORE, 266 /* Restart query services, start transceiver */ 267 RESET_STAGE_DONE, 268 /* Not in reset state */ 269 RESET_STAGE_NONE, 270 }; 271 272 enum hns3_reset_level { 273 HNS3_NONE_RESET, 274 HNS3_VF_FUNC_RESET, /* A VF function reset */ 275 /* 276 * All VFs under a PF perform function reset. 277 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 278 * of the reset level and the one defined in kernel driver should be 279 * same. 280 */ 281 HNS3_VF_PF_FUNC_RESET = 2, 282 /* 283 * All VFs under a PF perform FLR reset. 284 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 285 * of the reset level and the one defined in kernel driver should be 286 * same. 287 * 288 * According to the protocol of PCIe, FLR to a PF resets the PF state as 289 * well as the SR-IOV extended capability including VF Enable which 290 * means that VFs no longer exist. 291 * 292 * In PF FLR, the register state of VF is not reliable, VF's driver 293 * should not access the registers of the VF device. 294 */ 295 HNS3_VF_FULL_RESET = 3, 296 HNS3_FLR_RESET, /* A VF perform FLR reset */ 297 /* All VFs under the rootport perform a global or IMP reset */ 298 HNS3_VF_RESET, 299 HNS3_FUNC_RESET, /* A PF function reset */ 300 /* All PFs under the rootport perform a global reset */ 301 HNS3_GLOBAL_RESET, 302 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 303 HNS3_MAX_RESET 304 }; 305 306 enum hns3_wait_result { 307 HNS3_WAIT_UNKNOWN, 308 HNS3_WAIT_REQUEST, 309 HNS3_WAIT_SUCCESS, 310 HNS3_WAIT_TIMEOUT 311 }; 312 313 #define HNS3_RESET_SYNC_US 100000 314 315 struct hns3_reset_stats { 316 uint64_t request_cnt; /* Total request reset times */ 317 uint64_t global_cnt; /* Total GLOBAL reset times */ 318 uint64_t imp_cnt; /* Total IMP reset times */ 319 uint64_t exec_cnt; /* Total reset executive times */ 320 uint64_t success_cnt; /* Total reset successful times */ 321 uint64_t fail_cnt; /* Total reset failed times */ 322 uint64_t merge_cnt; /* Total merged in high reset times */ 323 }; 324 325 typedef bool (*check_completion_func)(struct hns3_hw *hw); 326 327 struct hns3_wait_data { 328 void *hns; 329 uint64_t end_ms; 330 uint64_t interval; 331 int16_t count; 332 enum hns3_wait_result result; 333 check_completion_func check_completion; 334 }; 335 336 struct hns3_reset_ops { 337 void (*reset_service)(void *arg); 338 int (*stop_service)(struct hns3_adapter *hns); 339 int (*prepare_reset)(struct hns3_adapter *hns); 340 int (*wait_hardware_ready)(struct hns3_adapter *hns); 341 int (*reinit_dev)(struct hns3_adapter *hns); 342 int (*restore_conf)(struct hns3_adapter *hns); 343 int (*start_service)(struct hns3_adapter *hns); 344 }; 345 346 enum hns3_schedule { 347 SCHEDULE_NONE, 348 SCHEDULE_PENDING, 349 SCHEDULE_REQUESTED, 350 SCHEDULE_DEFERRED, 351 }; 352 353 struct hns3_reset_data { 354 enum hns3_reset_stage stage; 355 uint16_t schedule; 356 /* Reset flag, covering the entire reset process */ 357 uint16_t resetting; 358 /* Used to disable sending cmds during reset */ 359 uint16_t disable_cmd; 360 /* The reset level being processed */ 361 enum hns3_reset_level level; 362 /* Reset level set, each bit represents a reset level */ 363 uint64_t pending; 364 /* Request reset level set, from interrupt or mailbox */ 365 uint64_t request; 366 int attempts; /* Reset failure retry */ 367 int retries; /* Timeout failure retry in reset_post */ 368 /* 369 * At the time of global or IMP reset, the command cannot be sent to 370 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 371 * reset process, so the mbuf is required to be released after the reset 372 * is completed.The mbuf_deferred_free is used to mark whether mbuf 373 * needs to be released. 374 */ 375 bool mbuf_deferred_free; 376 struct timeval start_time; 377 struct hns3_reset_stats stats; 378 const struct hns3_reset_ops *ops; 379 struct hns3_wait_data *wait_data; 380 }; 381 382 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 383 #define HNS3_INTR_MAPPING_VEC_ALL 1 384 385 #define HNS3_INTR_COALESCE_GL_UINT_2US 0 386 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 387 388 #define HNS3_INTR_QL_NONE 0 389 390 struct hns3_queue_intr { 391 /* 392 * interrupt mapping mode. 393 * value range: 394 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL 395 * 396 * - HNS3_INTR_MAPPING_VEC_RSV_ONE 397 * For some versions of hardware network engine, because of the 398 * hardware constraint, we need implement clearing the mapping 399 * relationship configurations by binding all queues to the last 400 * interrupt vector and reserving the last interrupt vector. This 401 * method results in a decrease of the maximum queues when upper 402 * applications call the rte_eth_dev_configure API function to 403 * enable Rx interrupt. 404 * 405 * - HNS3_INTR_MAPPING_VEC_ALL 406 * PMD driver can map/unmmap all interrupt vectors with queues When 407 * Rx interrupt in enabled. 408 */ 409 uint8_t mapping_mode; 410 /* 411 * The unit of GL(gap limiter) configuration for interrupt coalesce of 412 * queue's interrupt. 413 * value range: 414 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US 415 */ 416 uint8_t gl_unit; 417 /* The max QL(quantity limiter) value */ 418 uint16_t int_ql_max; 419 }; 420 421 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 422 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 423 424 struct hns3_hw { 425 struct rte_eth_dev_data *data; 426 void *io_base; 427 uint8_t revision; /* PCI revision, low byte of class word */ 428 struct hns3_cmq cmq; 429 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 430 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */ 431 pthread_t irq_thread_id; 432 struct hns3_mac mac; 433 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 434 struct hns3_tqp_stats tqp_stats; 435 /* Include Mac stats | Rx stats | Tx stats */ 436 struct hns3_mac_stats mac_stats; 437 uint32_t fw_version; 438 439 uint16_t num_msi; 440 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 441 uint16_t tqps_num; /* num task queue pairs of this function */ 442 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 443 uint16_t rss_size_max; /* HW defined max RSS task queue */ 444 uint16_t rx_buf_len; /* hold min hardware rx buf len */ 445 uint16_t num_tx_desc; /* desc num of per tx queue */ 446 uint16_t num_rx_desc; /* desc num of per rx queue */ 447 uint32_t mng_entry_num; /* number of manager table entry */ 448 uint32_t mac_entry_num; /* number of mac-vlan table entry */ 449 450 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 451 int mc_addrs_num; /* Multicast mac addresses number */ 452 453 /* The configuration info of RSS */ 454 struct hns3_rss_conf rss_info; 455 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ 456 uint16_t rss_ind_tbl_size; 457 uint16_t rss_key_size; 458 459 uint8_t num_tc; /* Total number of enabled TCs */ 460 uint8_t hw_tc_map; 461 enum hns3_fc_mode current_mode; 462 enum hns3_fc_mode requested_mode; 463 struct hns3_dcb_info dcb_info; 464 enum hns3_fc_status current_fc_status; /* current flow control status */ 465 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 466 uint16_t used_rx_queues; 467 uint16_t used_tx_queues; 468 469 /* Config max queue numbers between rx and tx queues from user */ 470 uint16_t cfg_max_queues; 471 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 472 uint16_t alloc_rss_size; /* RX queue number per TC */ 473 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 474 475 uint32_t capability; 476 uint32_t max_tm_rate; 477 /* 478 * The minimum length of the packet supported by hardware in the Tx 479 * direction. 480 */ 481 uint32_t min_tx_pkt_len; 482 483 struct hns3_queue_intr intr; 484 /* 485 * tso mode. 486 * value range: 487 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 488 * 489 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 490 * In this mode, because of the hardware constraint, network driver 491 * software need erase the L4 len value of the TCP pseudo header 492 * and recalculate the TCP pseudo header checksum of packets that 493 * need TSO. 494 * 495 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 496 * In this mode, hardware support recalculate the TCP pseudo header 497 * checksum of packets that need TSO, so network driver software 498 * not need to recalculate it. 499 */ 500 uint8_t tso_mode; 501 /* 502 * vlan mode. 503 * value range: 504 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE 505 * 506 * - HNS3_SW_SHIFT_AND_DISCARD_MODE 507 * For some versions of hardware network engine, because of the 508 * hardware limitation, PMD driver needs to detect the PVID status 509 * to work with haredware to implement PVID-related functions. 510 * For example, driver need discard the stripped PVID tag to ensure 511 * the PVID will not report to mbuf and shift the inserted VLAN tag 512 * to avoid port based VLAN covering it. 513 * 514 * - HNS3_HW_SHIT_AND_DISCARD_MODE 515 * PMD driver does not need to process PVID-related functions in 516 * I/O process, Hardware will adjust the sequence between port based 517 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by 518 * PVID will be invisible to driver. And in this mode, hns3 is able 519 * to send a multi-layer VLAN packets when hw VLAN insert offload 520 * is enabled. 521 */ 522 uint8_t vlan_mode; 523 /* 524 * promisc mode. 525 * value range: 526 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE 527 * 528 * - HNS3_UNLIMIT_PROMISC_MODE 529 * In this mode, TX unicast promisc will be configured when promisc 530 * is set, driver can receive all the ingress and outgoing traffic. 531 * In the words, all the ingress packets, all the packets sent from 532 * the PF and other VFs on the same physical port. 533 * 534 * - HNS3_LIMIT_PROMISC_MODE 535 * In this mode, TX unicast promisc is shutdown when promisc mode 536 * is set. So, driver will only receive all the ingress traffic. 537 * The packets sent from the PF and other VFs on the same physical 538 * port won't be copied to the function which has set promisc mode. 539 */ 540 uint8_t promisc_mode; 541 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 542 543 struct hns3_port_base_vlan_config port_base_vlan_cfg; 544 /* 545 * PMD setup and configuration is not thread safe. Since it is not 546 * performance sensitive, it is better to guarantee thread-safety 547 * and add device level lock. Adapter control operations which 548 * change its state should acquire the lock. 549 */ 550 rte_spinlock_t lock; 551 enum hns3_adapter_state adapter_state; 552 struct hns3_reset_data reset; 553 }; 554 555 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 556 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 557 558 struct hns3_err_msix_intr_stats { 559 uint64_t mac_afifo_tnl_int_cnt; 560 uint64_t ppu_mpf_abn_int_st2_msix_cnt; 561 uint64_t ssu_port_based_pf_int_cnt; 562 uint64_t ppp_pf_abnormal_int_cnt; 563 uint64_t ppu_pf_abnormal_int_msix_cnt; 564 565 uint64_t imp_tcm_ecc_int_cnt; 566 uint64_t cmdq_mem_ecc_int_cnt; 567 uint64_t imp_rd_poison_int_cnt; 568 uint64_t tqp_int_ecc_int_cnt; 569 uint64_t msix_ecc_int_cnt; 570 uint64_t ssu_ecc_multi_bit_int_0_cnt; 571 uint64_t ssu_ecc_multi_bit_int_1_cnt; 572 uint64_t ssu_common_ecc_int_cnt; 573 uint64_t igu_int_cnt; 574 uint64_t ppp_mpf_abnormal_int_st1_cnt; 575 uint64_t ppp_mpf_abnormal_int_st3_cnt; 576 uint64_t ppu_mpf_abnormal_int_st1_cnt; 577 uint64_t ppu_mpf_abn_int_st2_ras_cnt; 578 uint64_t ppu_mpf_abnormal_int_st3_cnt; 579 uint64_t tm_sch_int_cnt; 580 uint64_t qcn_fifo_int_cnt; 581 uint64_t qcn_ecc_int_cnt; 582 uint64_t ncsi_ecc_int_cnt; 583 uint64_t ssu_port_based_err_int_cnt; 584 uint64_t ssu_fifo_overflow_int_cnt; 585 uint64_t ssu_ets_tcg_int_cnt; 586 uint64_t igu_egu_tnl_int_cnt; 587 uint64_t ppu_pf_abnormal_int_ras_cnt; 588 }; 589 590 /* vlan entry information. */ 591 struct hns3_user_vlan_table { 592 LIST_ENTRY(hns3_user_vlan_table) next; 593 bool hd_tbl_status; 594 uint16_t vlan_id; 595 }; 596 597 /* Vlan tag configuration for RX direction */ 598 struct hns3_rx_vtag_cfg { 599 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 600 bool strip_tag1_en; /* Whether strip inner vlan tag */ 601 bool strip_tag2_en; /* Whether strip outer vlan tag */ 602 /* 603 * If strip_tag_en is enabled, this bit decide whether to map the vlan 604 * tag to descriptor. 605 */ 606 bool strip_tag1_discard_en; 607 bool strip_tag2_discard_en; 608 /* 609 * If this bit is enabled, only map inner/outer priority to descriptor 610 * and the vlan tag is always 0. 611 */ 612 bool vlan1_vlan_prionly; 613 bool vlan2_vlan_prionly; 614 }; 615 616 /* Vlan tag configuration for TX direction */ 617 struct hns3_tx_vtag_cfg { 618 bool accept_tag1; /* Whether accept tag1 packet from host */ 619 bool accept_untag1; /* Whether accept untag1 packet from host */ 620 bool accept_tag2; 621 bool accept_untag2; 622 bool insert_tag1_en; /* Whether insert outer vlan tag */ 623 bool insert_tag2_en; /* Whether insert inner vlan tag */ 624 /* 625 * In shift mode, hw will shift the sequence of port based VLAN and 626 * BD VLAN. 627 */ 628 bool tag_shift_mode_en; /* hw shift vlan tag automatically */ 629 uint16_t default_tag1; /* The default outer vlan tag to insert */ 630 uint16_t default_tag2; /* The default inner vlan tag to insert */ 631 }; 632 633 struct hns3_vtag_cfg { 634 struct hns3_rx_vtag_cfg rx_vcfg; 635 struct hns3_tx_vtag_cfg tx_vcfg; 636 }; 637 638 /* Request types for IPC. */ 639 enum hns3_mp_req_type { 640 HNS3_MP_REQ_START_RXTX = 1, 641 HNS3_MP_REQ_STOP_RXTX, 642 HNS3_MP_REQ_MAX 643 }; 644 645 /* Pameters for IPC. */ 646 struct hns3_mp_param { 647 enum hns3_mp_req_type type; 648 int port_id; 649 int result; 650 }; 651 652 /* Request timeout for IPC. */ 653 #define HNS3_MP_REQ_TIMEOUT_SEC 5 654 655 /* Key string for IPC. */ 656 #define HNS3_MP_NAME "net_hns3_mp" 657 658 #define HNS3_L2TBL_NUM 4 659 #define HNS3_L3TBL_NUM 16 660 #define HNS3_L4TBL_NUM 16 661 #define HNS3_OL2TBL_NUM 4 662 #define HNS3_OL3TBL_NUM 16 663 #define HNS3_OL4TBL_NUM 16 664 665 struct hns3_ptype_table { 666 uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM]; 667 uint32_t l4table[HNS3_L4TBL_NUM]; 668 uint32_t inner_l2table[HNS3_L2TBL_NUM]; 669 uint32_t inner_l3table[HNS3_L3TBL_NUM]; 670 uint32_t inner_l4table[HNS3_L4TBL_NUM]; 671 uint32_t ol2table[HNS3_OL2TBL_NUM]; 672 uint32_t ol3table[HNS3_OL3TBL_NUM]; 673 uint32_t ol4table[HNS3_OL4TBL_NUM]; 674 }; 675 676 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0 677 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1 678 679 struct hns3_pf { 680 struct hns3_adapter *adapter; 681 bool is_main_pf; 682 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 683 684 /* 685 * tqp_config mode 686 * tqp_config_mode value range: 687 * HNS3_FIXED_MAX_TQP_NUM_MODE, 688 * HNS3_FLEX_MAX_TQP_NUM_MODE 689 * 690 * - HNS3_FIXED_MAX_TQP_NUM_MODE 691 * There is a limitation on the number of pf interrupts available for 692 * on some versions of network engines. In this case, the maximum 693 * queue number of pf can not be greater than the interrupt number, 694 * such as pf of network engine with revision_id 0x21. So the maximum 695 * number of queues must be fixed. 696 * 697 * - HNS3_FLEX_MAX_TQP_NUM_MODE 698 * In this mode, the maximum queue number of pf has not any constraint 699 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 700 * in the config file. Users can modify the macro according to their 701 * own application scenarios, which is more flexible to use. 702 */ 703 uint8_t tqp_config_mode; 704 705 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 706 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 707 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 708 709 uint16_t mps; /* Max packet size */ 710 711 uint8_t tx_sch_mode; 712 uint8_t tc_max; /* max number of tc driver supported */ 713 uint8_t local_max_tc; /* max number of local tc */ 714 uint8_t pfc_max; 715 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 716 uint16_t pause_time; 717 bool support_fc_autoneg; /* support FC autonegotiate */ 718 719 uint16_t wanted_umv_size; 720 uint16_t max_umv_size; 721 uint16_t used_umv_size; 722 723 /* Statistics information for abnormal interrupt */ 724 struct hns3_err_msix_intr_stats abn_int_stats; 725 726 bool support_sfp_query; 727 uint32_t fec_mode; /* current FEC mode for ethdev */ 728 729 struct hns3_vtag_cfg vtag_config; 730 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 731 732 struct hns3_fdir_info fdir; /* flow director info */ 733 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 734 735 struct hns3_tm_conf tm_conf; 736 }; 737 738 struct hns3_vf { 739 struct hns3_adapter *adapter; 740 }; 741 742 struct hns3_adapter { 743 struct hns3_hw hw; 744 745 /* Specific for PF or VF */ 746 bool is_vf; /* false - PF, true - VF */ 747 union { 748 struct hns3_pf pf; 749 struct hns3_vf vf; 750 }; 751 752 bool rx_simple_allowed; 753 bool rx_vec_allowed; 754 bool tx_simple_allowed; 755 bool tx_vec_allowed; 756 757 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; 758 }; 759 760 #define HNS3_DEV_SUPPORT_DCB_B 0x0 761 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 762 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 763 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 764 #define HNS3_DEV_SUPPORT_PTP_B 0x4 765 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 766 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 767 #define HNS3_DEV_SUPPORT_STASH_B 0x7 768 769 #define hns3_dev_dcb_supported(hw) \ 770 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) 771 772 /* Support copper media type */ 773 #define hns3_dev_copper_supported(hw) \ 774 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) 775 776 /* Support UDP GSO offload */ 777 #define hns3_dev_udp_gso_supported(hw) \ 778 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) 779 780 /* Support the queue region action rule of flow directory */ 781 #define hns3_dev_fd_queue_region_supported(hw) \ 782 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) 783 784 /* Support PTP timestamp offload */ 785 #define hns3_dev_ptp_supported(hw) \ 786 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) 787 788 #define hns3_dev_tx_push_supported(hw) \ 789 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) 790 791 /* Support to Independently enable/disable/reset Tx or Rx queues */ 792 #define hns3_dev_indep_txrx_supported(hw) \ 793 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) 794 795 #define hns3_dev_stash_supported(hw) \ 796 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) 797 798 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 799 (&((struct hns3_adapter *)adapter)->hw) 800 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 801 (&((struct hns3_adapter *)adapter)->pf) 802 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 803 container_of(hw, struct hns3_adapter, hw) 804 805 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) 806 { 807 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 808 return &adapter->pf; 809 } 810 811 #define hns3_set_field(origin, mask, shift, val) \ 812 do { \ 813 (origin) &= (~(mask)); \ 814 (origin) |= ((val) << (shift)) & (mask); \ 815 } while (0) 816 #define hns3_get_field(origin, mask, shift) \ 817 (((origin) & (mask)) >> (shift)) 818 #define hns3_set_bit(origin, shift, val) \ 819 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 820 #define hns3_get_bit(origin, shift) \ 821 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 822 823 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) 824 825 /* 826 * upper_32_bits - return bits 32-63 of a number 827 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 828 * the "right shift count >= width of type" warning when that quantity is 829 * 32-bits. 830 */ 831 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 832 833 /* lower_32_bits - return bits 0-31 of a number */ 834 #define lower_32_bits(n) ((uint32_t)(n)) 835 836 #define BIT(nr) (1UL << (nr)) 837 838 #define BIT_ULL(x) (1ULL << (x)) 839 840 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 841 #define GENMASK(h, l) \ 842 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 843 844 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 845 #define rounddown(x, y) ((x) - ((x) % (y))) 846 847 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 848 849 /* 850 * Because hardware always access register in little-endian mode based on hns3 851 * network engine, so driver should also call rte_cpu_to_le_32 to convert data 852 * in little-endian mode before writing register and call rte_le_to_cpu_32 to 853 * convert data after reading from register. 854 * 855 * Here the driver encapsulates the data conversion operation in the register 856 * read/write operation function as below: 857 * hns3_write_reg 858 * hns3_write_reg_opt 859 * hns3_read_reg 860 * Therefore, when calling these functions, conversion is not required again. 861 */ 862 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 863 { 864 rte_write32(rte_cpu_to_le_32(value), 865 (volatile void *)((char *)base + reg)); 866 } 867 868 /* 869 * The optimized function for writing registers used in the '.rx_pkt_burst' and 870 * '.tx_pkt_burst' ops implementation function. 871 */ 872 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) 873 { 874 rte_io_wmb(); 875 rte_write32_relaxed(rte_cpu_to_le_32(value), addr); 876 } 877 878 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 879 { 880 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); 881 return rte_le_to_cpu_32(read_val); 882 } 883 884 #define hns3_write_dev(a, reg, value) \ 885 hns3_write_reg((a)->io_base, (reg), (value)) 886 887 #define hns3_read_dev(a, reg) \ 888 hns3_read_reg((a)->io_base, (reg)) 889 890 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 891 892 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 893 do { \ 894 act = (actions) + (index); \ 895 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 896 (index)++; \ 897 act = actions + index; \ 898 } \ 899 } while (0) 900 901 #define MSEC_PER_SEC 1000L 902 #define USEC_PER_MSEC 1000L 903 904 static inline uint64_t 905 get_timeofday_ms(void) 906 { 907 struct timeval tv; 908 909 (void)gettimeofday(&tv, NULL); 910 911 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 912 } 913 914 static inline uint64_t 915 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 916 { 917 uint64_t res; 918 919 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 920 return res; 921 } 922 923 static inline void 924 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 925 { 926 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 927 } 928 929 static inline void 930 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 931 { 932 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 933 } 934 935 static inline int64_t 936 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 937 { 938 uint64_t mask = (1UL << nr); 939 940 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 941 } 942 943 int hns3_buffer_alloc(struct hns3_hw *hw); 944 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, 945 enum rte_filter_type filter_type, 946 enum rte_filter_op filter_op, void *arg); 947 bool hns3_is_reset_pending(struct hns3_adapter *hns); 948 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 949 void hns3_update_link_status_and_event(struct hns3_hw *hw); 950 void hns3_ether_format_addr(char *buf, uint16_t size, 951 const struct rte_ether_addr *ether_addr); 952 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, 953 struct rte_eth_dev_info *info); 954 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 955 uint32_t link_speed, uint8_t link_duplex); 956 957 static inline bool 958 is_reset_pending(struct hns3_adapter *hns) 959 { 960 bool ret; 961 if (hns->is_vf) 962 ret = hns3vf_is_reset_pending(hns); 963 else 964 ret = hns3_is_reset_pending(hns); 965 return ret; 966 } 967 968 static inline uint64_t 969 hns3_txvlan_cap_get(struct hns3_hw *hw) 970 { 971 if (hw->port_base_vlan_cfg.state) 972 return DEV_TX_OFFLOAD_VLAN_INSERT; 973 else 974 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; 975 } 976 977 #endif /* _HNS3_ETHDEV_H_ */ 978