1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef _HNS3_ETHDEV_H_ 6 #define _HNS3_ETHDEV_H_ 7 8 #include <pthread.h> 9 #include <sys/time.h> 10 #include <ethdev_driver.h> 11 #include <rte_byteorder.h> 12 #include <rte_io.h> 13 #include <rte_spinlock.h> 14 15 #include "hns3_cmd.h" 16 #include "hns3_mbx.h" 17 #include "hns3_rss.h" 18 #include "hns3_fdir.h" 19 #include "hns3_stats.h" 20 #include "hns3_tm.h" 21 22 /* Vendor ID */ 23 #define PCI_VENDOR_ID_HUAWEI 0x19e5 24 25 /* Device IDs */ 26 #define HNS3_DEV_ID_GE 0xA220 27 #define HNS3_DEV_ID_25GE 0xA221 28 #define HNS3_DEV_ID_25GE_RDMA 0xA222 29 #define HNS3_DEV_ID_50GE_RDMA 0xA224 30 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 31 #define HNS3_DEV_ID_200G_RDMA 0xA228 32 #define HNS3_DEV_ID_100G_VF 0xA22E 33 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F 34 35 /* PCI Config offsets */ 36 #define HNS3_PCI_REVISION_ID 0x08 37 #define HNS3_PCI_REVISION_ID_LEN 1 38 39 #define PCI_REVISION_ID_HIP08_B 0x21 40 #define PCI_REVISION_ID_HIP09_A 0x30 41 42 #define HNS3_PF_FUNC_ID 0 43 #define HNS3_1ST_VF_FUNC_ID 1 44 45 #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 46 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 47 48 #define HNS3_UNLIMIT_PROMISC_MODE 0 49 #define HNS3_LIMIT_PROMISC_MODE 1 50 51 #define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0 52 #define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1 53 54 #define HNS3_UC_MACADDR_NUM 128 55 #define HNS3_VF_UC_MACADDR_NUM 48 56 #define HNS3_MC_MACADDR_NUM 128 57 58 #define HNS3_MAX_BD_SIZE 65535 59 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8 60 #define HNS3_MAX_TSO_BD_PER_PKT 63 61 #define HNS3_MAX_FRAME_LEN 9728 62 #define HNS3_VLAN_TAG_SIZE 4 63 #define HNS3_DEFAULT_RX_BUF_LEN 2048 64 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) 65 #define HNS3_MAX_TSO_HDR_SIZE 512 66 #define HNS3_MAX_TSO_HDR_BD_NUM 3 67 #define HNS3_MAX_LRO_SIZE 64512 68 69 #define HNS3_ETH_OVERHEAD \ 70 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) 71 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD) 72 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD) 73 #define HNS3_DEFAULT_MTU 1500UL 74 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD) 75 #define HNS3_HIP08_MIN_TX_PKT_LEN 33 76 #define HNS3_HIP09_MIN_TX_PKT_LEN 9 77 78 #define HNS3_BITS_PER_BYTE 8 79 80 #define HNS3_4_TCS 4 81 #define HNS3_8_TCS 8 82 83 #define HNS3_MAX_PF_NUM 8 84 #define HNS3_UMV_TBL_SIZE 3072 85 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \ 86 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM) 87 88 #define HNS3_PF_CFG_BLOCK_SIZE 32 89 #define HNS3_PF_CFG_DESC_NUM \ 90 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES) 91 92 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0 93 94 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5 95 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500 96 97 #define HNS3_QUIT_RESET_CNT 10 98 #define HNS3_QUIT_RESET_DELAY_MS 100 99 100 #define HNS3_POLL_RESPONE_MS 1 101 102 #define HNS3_MAX_USER_PRIO 8 103 #define HNS3_PG_NUM 4 104 enum hns3_fc_mode { 105 HNS3_FC_NONE, 106 HNS3_FC_RX_PAUSE, 107 HNS3_FC_TX_PAUSE, 108 HNS3_FC_FULL, 109 HNS3_FC_DEFAULT 110 }; 111 112 #define HNS3_SCH_MODE_SP 0 113 #define HNS3_SCH_MODE_DWRR 1 114 struct hns3_pg_info { 115 uint8_t pg_id; 116 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */ 117 uint8_t tc_bit_map; 118 uint32_t bw_limit; 119 uint8_t tc_dwrr[HNS3_MAX_TC_NUM]; 120 }; 121 122 struct hns3_tc_info { 123 uint8_t tc_id; 124 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */ 125 uint8_t pgid; 126 uint32_t bw_limit; 127 uint8_t up_to_tc_map; /* user priority maping on the TC */ 128 }; 129 130 struct hns3_dcb_info { 131 uint8_t num_tc; 132 uint8_t num_pg; /* It must be 1 if vNET-Base schd */ 133 uint8_t pg_dwrr[HNS3_PG_NUM]; 134 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; 135 struct hns3_pg_info pg_info[HNS3_PG_NUM]; 136 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM]; 137 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */ 138 uint8_t pfc_en; /* Pfc enabled or not for user priority */ 139 }; 140 141 enum hns3_fc_status { 142 HNS3_FC_STATUS_NONE, 143 HNS3_FC_STATUS_MAC_PAUSE, 144 HNS3_FC_STATUS_PFC, 145 }; 146 147 struct hns3_tc_queue_info { 148 uint16_t tqp_offset; /* TQP offset from base TQP */ 149 uint16_t tqp_count; /* Total TQPs */ 150 uint8_t tc; /* TC index */ 151 bool enable; /* If this TC is enable or not */ 152 }; 153 154 struct hns3_cfg { 155 uint8_t vmdq_vport_num; 156 uint8_t tc_num; 157 uint16_t tqp_desc_num; 158 uint16_t rx_buf_len; 159 uint16_t rss_size_max; 160 uint8_t phy_addr; 161 uint8_t media_type; 162 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 163 uint8_t default_speed; 164 uint32_t numa_node_map; 165 uint8_t speed_ability; 166 uint16_t umv_space; 167 }; 168 169 struct hns3_set_link_speed_cfg { 170 uint32_t speed; 171 uint8_t duplex : 1; 172 uint8_t autoneg : 1; 173 }; 174 175 /* mac media type */ 176 enum hns3_media_type { 177 HNS3_MEDIA_TYPE_UNKNOWN, 178 HNS3_MEDIA_TYPE_FIBER, 179 HNS3_MEDIA_TYPE_COPPER, 180 HNS3_MEDIA_TYPE_BACKPLANE, 181 HNS3_MEDIA_TYPE_NONE, 182 }; 183 184 #define HNS3_DEFAULT_QUERY 0 185 #define HNS3_ACTIVE_QUERY 1 186 187 struct hns3_mac { 188 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 189 bool default_addr_setted; /* whether default addr(mac_addr) is set */ 190 uint8_t media_type; 191 uint8_t phy_addr; 192 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */ 193 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */ 194 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */ 195 uint32_t link_speed; /* ETH_SPEED_NUM_ */ 196 /* 197 * Some firmware versions support only the SFP speed query. In addition 198 * to the SFP speed query, some firmware supports the query of the speed 199 * capability, auto-negotiation capability, and FEC mode, which can be 200 * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD. 201 * This field is used to record the SFP information query mode. 202 * Value range: 203 * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY 204 * 205 * - HNS3_DEFAULT_QUERY 206 * Speed obtained is from SFP. When the queried speed changes, the MAC 207 * speed needs to be reconfigured. 208 * 209 * - HNS3_ACTIVE_QUERY 210 * Speed obtained is from MAC. At this time, it is unnecessary for 211 * driver to reconfigured the MAC speed. In addition, more information, 212 * such as, the speed capability, auto-negotiation capability and FEC 213 * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD. 214 */ 215 uint8_t query_type; 216 uint32_t supported_speed; /* supported speed for current media type */ 217 uint32_t advertising; /* advertised capability in the local part */ 218 uint32_t lp_advertising; /* advertised capability in the link partner */ 219 uint8_t support_autoneg; 220 }; 221 222 struct hns3_fake_queue_data { 223 void **rx_queues; /* Array of pointers to fake RX queues. */ 224 void **tx_queues; /* Array of pointers to fake TX queues. */ 225 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */ 226 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */ 227 }; 228 229 #define HNS3_PORT_BASE_VLAN_DISABLE 0 230 #define HNS3_PORT_BASE_VLAN_ENABLE 1 231 struct hns3_port_base_vlan_config { 232 uint16_t state; 233 uint16_t pvid; 234 }; 235 236 /* Primary process maintains driver state in main thread. 237 * 238 * +---------------+ 239 * | UNINITIALIZED |<-----------+ 240 * +---------------+ | 241 * |.eth_dev_init |.eth_dev_uninit 242 * V | 243 * +---------------+------------+ 244 * | INITIALIZED | 245 * +---------------+<-----------<---------------+ 246 * |.dev_configure | | 247 * V |failed | 248 * +---------------+------------+ | 249 * | CONFIGURING | | 250 * +---------------+----+ | 251 * |success | | 252 * | | +---------------+ 253 * | | | CLOSING | 254 * | | +---------------+ 255 * | | ^ 256 * V |.dev_configure | 257 * +---------------+----+ |.dev_close 258 * | CONFIGURED |----------------------------+ 259 * +---------------+<-----------+ 260 * |.dev_start | 261 * V | 262 * +---------------+ | 263 * | STARTING |------------^ 264 * +---------------+ failed | 265 * |success | 266 * | +---------------+ 267 * | | STOPPING | 268 * | +---------------+ 269 * | ^ 270 * V |.dev_stop 271 * +---------------+------------+ 272 * | STARTED | 273 * +---------------+ 274 */ 275 enum hns3_adapter_state { 276 HNS3_NIC_UNINITIALIZED = 0, 277 HNS3_NIC_INITIALIZED, 278 HNS3_NIC_CONFIGURING, 279 HNS3_NIC_CONFIGURED, 280 HNS3_NIC_STARTING, 281 HNS3_NIC_STARTED, 282 HNS3_NIC_STOPPING, 283 HNS3_NIC_CLOSING, 284 HNS3_NIC_CLOSED, 285 HNS3_NIC_REMOVED, 286 HNS3_NIC_NSTATES 287 }; 288 289 /* Reset various stages, execute in order */ 290 enum hns3_reset_stage { 291 /* Stop query services, stop transceiver, disable MAC */ 292 RESET_STAGE_DOWN, 293 /* Clear reset completion flags, disable send command */ 294 RESET_STAGE_PREWAIT, 295 /* Inform IMP to start resetting */ 296 RESET_STAGE_REQ_HW_RESET, 297 /* Waiting for hardware reset to complete */ 298 RESET_STAGE_WAIT, 299 /* Reinitialize hardware */ 300 RESET_STAGE_DEV_INIT, 301 /* Restore user settings and enable MAC */ 302 RESET_STAGE_RESTORE, 303 /* Restart query services, start transceiver */ 304 RESET_STAGE_DONE, 305 /* Not in reset state */ 306 RESET_STAGE_NONE, 307 }; 308 309 enum hns3_reset_level { 310 HNS3_FLR_RESET, /* A VF perform FLR reset */ 311 HNS3_VF_FUNC_RESET, /* A VF function reset */ 312 313 /* 314 * All VFs under a PF perform function reset. 315 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 316 * of the reset level and the one defined in kernel driver should be 317 * same. 318 */ 319 HNS3_VF_PF_FUNC_RESET = 2, 320 321 /* 322 * All VFs under a PF perform FLR reset. 323 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value 324 * of the reset level and the one defined in kernel driver should be 325 * same. 326 * 327 * According to the protocol of PCIe, FLR to a PF resets the PF state as 328 * well as the SR-IOV extended capability including VF Enable which 329 * means that VFs no longer exist. 330 * 331 * In PF FLR, the register state of VF is not reliable, VF's driver 332 * should not access the registers of the VF device. 333 */ 334 HNS3_VF_FULL_RESET, 335 336 /* All VFs under the rootport perform a global or IMP reset */ 337 HNS3_VF_RESET, 338 339 /* 340 * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/ 341 * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and 342 * can not be changed. 343 */ 344 345 HNS3_FUNC_RESET = 5, /* A PF function reset */ 346 347 /* All PFs under the rootport perform a global reset */ 348 HNS3_GLOBAL_RESET, 349 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */ 350 HNS3_NONE_RESET, 351 HNS3_MAX_RESET 352 }; 353 354 enum hns3_wait_result { 355 HNS3_WAIT_UNKNOWN, 356 HNS3_WAIT_REQUEST, 357 HNS3_WAIT_SUCCESS, 358 HNS3_WAIT_TIMEOUT 359 }; 360 361 #define HNS3_RESET_SYNC_US 100000 362 363 struct hns3_reset_stats { 364 uint64_t request_cnt; /* Total request reset times */ 365 uint64_t global_cnt; /* Total GLOBAL reset times */ 366 uint64_t imp_cnt; /* Total IMP reset times */ 367 uint64_t exec_cnt; /* Total reset executive times */ 368 uint64_t success_cnt; /* Total reset successful times */ 369 uint64_t fail_cnt; /* Total reset failed times */ 370 uint64_t merge_cnt; /* Total merged in high reset times */ 371 }; 372 373 typedef bool (*check_completion_func)(struct hns3_hw *hw); 374 375 struct hns3_wait_data { 376 void *hns; 377 uint64_t end_ms; 378 uint64_t interval; 379 int16_t count; 380 enum hns3_wait_result result; 381 check_completion_func check_completion; 382 }; 383 384 struct hns3_reset_ops { 385 void (*reset_service)(void *arg); 386 int (*stop_service)(struct hns3_adapter *hns); 387 int (*prepare_reset)(struct hns3_adapter *hns); 388 int (*wait_hardware_ready)(struct hns3_adapter *hns); 389 int (*reinit_dev)(struct hns3_adapter *hns); 390 int (*restore_conf)(struct hns3_adapter *hns); 391 int (*start_service)(struct hns3_adapter *hns); 392 }; 393 394 enum hns3_schedule { 395 SCHEDULE_NONE, 396 SCHEDULE_PENDING, 397 SCHEDULE_REQUESTED, 398 SCHEDULE_DEFERRED, 399 }; 400 401 struct hns3_reset_data { 402 enum hns3_reset_stage stage; 403 uint16_t schedule; 404 /* Reset flag, covering the entire reset process */ 405 uint16_t resetting; 406 /* Used to disable sending cmds during reset */ 407 uint16_t disable_cmd; 408 /* The reset level being processed */ 409 enum hns3_reset_level level; 410 /* Reset level set, each bit represents a reset level */ 411 uint64_t pending; 412 /* Request reset level set, from interrupt or mailbox */ 413 uint64_t request; 414 int attempts; /* Reset failure retry */ 415 int retries; /* Timeout failure retry in reset_post */ 416 /* 417 * At the time of global or IMP reset, the command cannot be sent to 418 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the 419 * reset process, so the mbuf is required to be released after the reset 420 * is completed.The mbuf_deferred_free is used to mark whether mbuf 421 * needs to be released. 422 */ 423 bool mbuf_deferred_free; 424 struct timeval start_time; 425 struct hns3_reset_stats stats; 426 const struct hns3_reset_ops *ops; 427 struct hns3_wait_data *wait_data; 428 }; 429 430 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 431 #define HNS3_INTR_MAPPING_VEC_ALL 1 432 433 #define HNS3_INTR_COALESCE_GL_UINT_2US 0 434 #define HNS3_INTR_COALESCE_GL_UINT_1US 1 435 436 #define HNS3_INTR_QL_NONE 0 437 438 struct hns3_queue_intr { 439 /* 440 * interrupt mapping mode. 441 * value range: 442 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL 443 * 444 * - HNS3_INTR_MAPPING_VEC_RSV_ONE 445 * For some versions of hardware network engine, because of the 446 * hardware constraint, we need implement clearing the mapping 447 * relationship configurations by binding all queues to the last 448 * interrupt vector and reserving the last interrupt vector. This 449 * method results in a decrease of the maximum queues when upper 450 * applications call the rte_eth_dev_configure API function to 451 * enable Rx interrupt. 452 * 453 * - HNS3_INTR_MAPPING_VEC_ALL 454 * PMD driver can map/unmmap all interrupt vectors with queues When 455 * Rx interrupt in enabled. 456 */ 457 uint8_t mapping_mode; 458 /* 459 * The unit of GL(gap limiter) configuration for interrupt coalesce of 460 * queue's interrupt. 461 * value range: 462 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US 463 */ 464 uint8_t gl_unit; 465 /* The max QL(quantity limiter) value */ 466 uint16_t int_ql_max; 467 }; 468 469 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 470 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 471 472 #define HNS3_PKTS_DROP_STATS_MODE1 0 473 #define HNS3_PKTS_DROP_STATS_MODE2 1 474 475 struct hns3_hw { 476 struct rte_eth_dev_data *data; 477 void *io_base; 478 uint8_t revision; /* PCI revision, low byte of class word */ 479 struct hns3_cmq cmq; 480 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */ 481 struct hns3_mac mac; 482 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 483 struct hns3_tqp_stats tqp_stats; 484 /* Include Mac stats | Rx stats | Tx stats */ 485 struct hns3_mac_stats mac_stats; 486 struct hns3_rx_missed_stats imissed_stats; 487 uint64_t oerror_stats; 488 uint32_t fw_version; 489 490 uint16_t num_msi; 491 uint16_t total_tqps_num; /* total task queue pairs of this PF */ 492 uint16_t tqps_num; /* num task queue pairs of this function */ 493 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ 494 uint16_t rss_size_max; /* HW defined max RSS task queue */ 495 uint16_t rx_buf_len; /* hold min hardware rx buf len */ 496 uint16_t num_tx_desc; /* desc num of per tx queue */ 497 uint16_t num_rx_desc; /* desc num of per rx queue */ 498 uint32_t mng_entry_num; /* number of manager table entry */ 499 uint32_t mac_entry_num; /* number of mac-vlan table entry */ 500 501 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM]; 502 int mc_addrs_num; /* Multicast mac addresses number */ 503 504 /* The configuration info of RSS */ 505 struct hns3_rss_conf rss_info; 506 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */ 507 uint16_t rss_ind_tbl_size; 508 uint16_t rss_key_size; 509 510 uint8_t num_tc; /* Total number of enabled TCs */ 511 uint8_t hw_tc_map; 512 enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */ 513 struct hns3_dcb_info dcb_info; 514 enum hns3_fc_status current_fc_status; /* current flow control status */ 515 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM]; 516 uint16_t used_rx_queues; 517 uint16_t used_tx_queues; 518 519 /* Config max queue numbers between rx and tx queues from user */ 520 uint16_t cfg_max_queues; 521 struct hns3_fake_queue_data fkq_data; /* fake queue data */ 522 uint16_t alloc_rss_size; /* RX queue number per TC */ 523 uint16_t tx_qnum_per_tc; /* TX queue number per TC */ 524 525 uint32_t capability; 526 uint32_t max_tm_rate; 527 /* 528 * The minimum length of the packet supported by hardware in the Tx 529 * direction. 530 */ 531 uint32_t min_tx_pkt_len; 532 533 struct hns3_queue_intr intr; 534 /* 535 * tso mode. 536 * value range: 537 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 538 * 539 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 540 * In this mode, because of the hardware constraint, network driver 541 * software need erase the L4 len value of the TCP pseudo header 542 * and recalculate the TCP pseudo header checksum of packets that 543 * need TSO. 544 * 545 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 546 * In this mode, hardware support recalculate the TCP pseudo header 547 * checksum of packets that need TSO, so network driver software 548 * not need to recalculate it. 549 */ 550 uint8_t tso_mode; 551 /* 552 * vlan mode. 553 * value range: 554 * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE 555 * 556 * - HNS3_SW_SHIFT_AND_DISCARD_MODE 557 * For some versions of hardware network engine, because of the 558 * hardware limitation, PMD driver needs to detect the PVID status 559 * to work with haredware to implement PVID-related functions. 560 * For example, driver need discard the stripped PVID tag to ensure 561 * the PVID will not report to mbuf and shift the inserted VLAN tag 562 * to avoid port based VLAN covering it. 563 * 564 * - HNS3_HW_SHIT_AND_DISCARD_MODE 565 * PMD driver does not need to process PVID-related functions in 566 * I/O process, Hardware will adjust the sequence between port based 567 * VLAN tag and BD VLAN tag automatically and VLAN tag stripped by 568 * PVID will be invisible to driver. And in this mode, hns3 is able 569 * to send a multi-layer VLAN packets when hw VLAN insert offload 570 * is enabled. 571 */ 572 uint8_t vlan_mode; 573 /* 574 * promisc mode. 575 * value range: 576 * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE 577 * 578 * - HNS3_UNLIMIT_PROMISC_MODE 579 * In this mode, TX unicast promisc will be configured when promisc 580 * is set, driver can receive all the ingress and outgoing traffic. 581 * In the words, all the ingress packets, all the packets sent from 582 * the PF and other VFs on the same physical port. 583 * 584 * - HNS3_LIMIT_PROMISC_MODE 585 * In this mode, TX unicast promisc is shutdown when promisc mode 586 * is set. So, driver will only receive all the ingress traffic. 587 * The packets sent from the PF and other VFs on the same physical 588 * port won't be copied to the function which has set promisc mode. 589 */ 590 uint8_t promisc_mode; 591 592 /* 593 * drop_stats_mode mode. 594 * value range: 595 * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 596 * 597 * - HNS3_PKTS_DROP_STATS_MODE1 598 * This mode for kunpeng920. In this mode, port level imissed stats 599 * is supported. It only includes RPU drop stats. 600 * 601 * - HNS3_PKTS_DROP_STATS_MODE2 602 * This mode for kunpeng930. In this mode, imissed stats and oerrors 603 * stats is supported. Function level imissed stats is supported. It 604 * includes RPU drop stats in VF, and includes both RPU drop stats 605 * and SSU drop stats in PF. Oerror stats is also supported in PF. 606 */ 607 uint8_t drop_stats_mode; 608 609 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 610 /* 611 * udp checksum mode. 612 * value range: 613 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE 614 * 615 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE 616 * In this mode, HW can not do checksum for special UDP port like 617 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel 618 * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need 619 * do the checksum for these packets to avoid a checksum error. 620 * 621 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE 622 * In this mode, HW does not have the preceding problems and can 623 * directly calculate the checksum of these UDP packets. 624 */ 625 uint8_t udp_cksum_mode; 626 627 struct hns3_port_base_vlan_config port_base_vlan_cfg; 628 629 pthread_mutex_t flows_lock; /* rte_flow ops lock */ 630 631 /* 632 * PMD setup and configuration is not thread safe. Since it is not 633 * performance sensitive, it is better to guarantee thread-safety 634 * and add device level lock. Adapter control operations which 635 * change its state should acquire the lock. 636 */ 637 rte_spinlock_t lock; 638 enum hns3_adapter_state adapter_state; 639 struct hns3_reset_data reset; 640 }; 641 642 #define HNS3_FLAG_TC_BASE_SCH_MODE 1 643 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 644 645 /* vlan entry information. */ 646 struct hns3_user_vlan_table { 647 LIST_ENTRY(hns3_user_vlan_table) next; 648 bool hd_tbl_status; 649 uint16_t vlan_id; 650 }; 651 652 /* Vlan tag configuration for RX direction */ 653 struct hns3_rx_vtag_cfg { 654 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 655 bool strip_tag1_en; /* Whether strip inner vlan tag */ 656 bool strip_tag2_en; /* Whether strip outer vlan tag */ 657 /* 658 * If strip_tag_en is enabled, this bit decide whether to map the vlan 659 * tag to descriptor. 660 */ 661 bool strip_tag1_discard_en; 662 bool strip_tag2_discard_en; 663 /* 664 * If this bit is enabled, only map inner/outer priority to descriptor 665 * and the vlan tag is always 0. 666 */ 667 bool vlan1_vlan_prionly; 668 bool vlan2_vlan_prionly; 669 }; 670 671 /* Vlan tag configuration for TX direction */ 672 struct hns3_tx_vtag_cfg { 673 bool accept_tag1; /* Whether accept tag1 packet from host */ 674 bool accept_untag1; /* Whether accept untag1 packet from host */ 675 bool accept_tag2; 676 bool accept_untag2; 677 bool insert_tag1_en; /* Whether insert outer vlan tag */ 678 bool insert_tag2_en; /* Whether insert inner vlan tag */ 679 /* 680 * In shift mode, hw will shift the sequence of port based VLAN and 681 * BD VLAN. 682 */ 683 bool tag_shift_mode_en; /* hw shift vlan tag automatically */ 684 uint16_t default_tag1; /* The default outer vlan tag to insert */ 685 uint16_t default_tag2; /* The default inner vlan tag to insert */ 686 }; 687 688 struct hns3_vtag_cfg { 689 struct hns3_rx_vtag_cfg rx_vcfg; 690 struct hns3_tx_vtag_cfg tx_vcfg; 691 }; 692 693 /* Request types for IPC. */ 694 enum hns3_mp_req_type { 695 HNS3_MP_REQ_START_RXTX = 1, 696 HNS3_MP_REQ_STOP_RXTX, 697 HNS3_MP_REQ_MAX 698 }; 699 700 /* Pameters for IPC. */ 701 struct hns3_mp_param { 702 enum hns3_mp_req_type type; 703 int port_id; 704 int result; 705 }; 706 707 /* Request timeout for IPC. */ 708 #define HNS3_MP_REQ_TIMEOUT_SEC 5 709 710 /* Key string for IPC. */ 711 #define HNS3_MP_NAME "net_hns3_mp" 712 713 #define HNS3_L2TBL_NUM 4 714 #define HNS3_L3TBL_NUM 16 715 #define HNS3_L4TBL_NUM 16 716 #define HNS3_OL2TBL_NUM 4 717 #define HNS3_OL3TBL_NUM 16 718 #define HNS3_OL4TBL_NUM 16 719 #define HNS3_PTYPE_NUM 256 720 721 struct hns3_ptype_table { 722 /* 723 * The next fields used to calc packet-type by the 724 * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. 725 */ 726 uint32_t l3table[HNS3_L3TBL_NUM]; 727 uint32_t l4table[HNS3_L4TBL_NUM]; 728 uint32_t inner_l3table[HNS3_L3TBL_NUM]; 729 uint32_t inner_l4table[HNS3_L4TBL_NUM]; 730 uint32_t ol3table[HNS3_OL3TBL_NUM]; 731 uint32_t ol4table[HNS3_OL4TBL_NUM]; 732 733 /* 734 * The next field used to calc packet-type by the PTYPE from the Rx 735 * descriptor, it functions only when firmware report the capability of 736 * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it. 737 */ 738 uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned; 739 }; 740 741 #define HNS3_FIXED_MAX_TQP_NUM_MODE 0 742 #define HNS3_FLEX_MAX_TQP_NUM_MODE 1 743 744 struct hns3_pf { 745 struct hns3_adapter *adapter; 746 bool is_main_pf; 747 uint16_t func_num; /* num functions of this pf, include pf and vfs */ 748 749 /* 750 * tqp_config mode 751 * tqp_config_mode value range: 752 * HNS3_FIXED_MAX_TQP_NUM_MODE, 753 * HNS3_FLEX_MAX_TQP_NUM_MODE 754 * 755 * - HNS3_FIXED_MAX_TQP_NUM_MODE 756 * There is a limitation on the number of pf interrupts available for 757 * on some versions of network engines. In this case, the maximum 758 * queue number of pf can not be greater than the interrupt number, 759 * such as pf of network engine with revision_id 0x21. So the maximum 760 * number of queues must be fixed. 761 * 762 * - HNS3_FLEX_MAX_TQP_NUM_MODE 763 * In this mode, the maximum queue number of pf has not any constraint 764 * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 765 * in the config file. Users can modify the macro according to their 766 * own application scenarios, which is more flexible to use. 767 */ 768 uint8_t tqp_config_mode; 769 770 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */ 771 uint32_t tx_buf_size; /* Tx buffer size for each TC */ 772 uint32_t dv_buf_size; /* Dv buffer size for each TC */ 773 774 uint16_t mps; /* Max packet size */ 775 776 uint8_t tx_sch_mode; 777 uint8_t tc_max; /* max number of tc driver supported */ 778 uint8_t local_max_tc; /* max number of local tc */ 779 uint8_t pfc_max; 780 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */ 781 uint16_t pause_time; 782 bool support_fc_autoneg; /* support FC autonegotiate */ 783 784 uint16_t wanted_umv_size; 785 uint16_t max_umv_size; 786 uint16_t used_umv_size; 787 788 bool support_sfp_query; 789 uint32_t fec_mode; /* current FEC mode for ethdev */ 790 791 bool ptp_enable; 792 793 /* Stores timestamp of last received packet on dev */ 794 uint64_t rx_timestamp; 795 796 struct hns3_vtag_cfg vtag_config; 797 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list; 798 799 struct hns3_fdir_info fdir; /* flow director info */ 800 LIST_HEAD(counters, hns3_flow_counter) flow_counters; 801 802 struct hns3_tm_conf tm_conf; 803 }; 804 805 enum { 806 HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED, 807 HNS3_PF_PUSH_LSC_CAP_SUPPORTED, 808 HNS3_PF_PUSH_LSC_CAP_UNKNOWN 809 }; 810 811 struct hns3_vf { 812 struct hns3_adapter *adapter; 813 814 /* Whether PF support push link status change to VF */ 815 uint16_t pf_push_lsc_cap; 816 817 /* 818 * If PF support push link status change, VF still need send request to 819 * get link status in some cases (such as reset recover stage), so use 820 * the req_link_info_cnt to control max request count. 821 */ 822 uint16_t req_link_info_cnt; 823 824 uint16_t poll_job_started; /* whether poll job is started */ 825 }; 826 827 struct hns3_adapter { 828 struct hns3_hw hw; 829 830 /* Specific for PF or VF */ 831 bool is_vf; /* false - PF, true - VF */ 832 union { 833 struct hns3_pf pf; 834 struct hns3_vf vf; 835 }; 836 837 uint32_t rx_func_hint; 838 uint32_t tx_func_hint; 839 840 uint64_t dev_caps_mask; 841 842 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; 843 }; 844 845 enum { 846 HNS3_IO_FUNC_HINT_NONE = 0, 847 HNS3_IO_FUNC_HINT_VEC, 848 HNS3_IO_FUNC_HINT_SVE, 849 HNS3_IO_FUNC_HINT_SIMPLE, 850 HNS3_IO_FUNC_HINT_COMMON 851 }; 852 853 #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" 854 #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" 855 856 #define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask" 857 858 #define HNS3_DEV_SUPPORT_DCB_B 0x0 859 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 860 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 861 #define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3 862 #define HNS3_DEV_SUPPORT_PTP_B 0x4 863 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5 864 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 865 #define HNS3_DEV_SUPPORT_STASH_B 0x7 866 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 867 #define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA 868 #define HNS3_DEV_SUPPORT_RAS_IMP_B 0xB 869 870 #define hns3_dev_dcb_supported(hw) \ 871 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) 872 873 /* Support copper media type */ 874 #define hns3_dev_copper_supported(hw) \ 875 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B) 876 877 /* Support UDP GSO offload */ 878 #define hns3_dev_udp_gso_supported(hw) \ 879 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B) 880 881 /* Support the queue region action rule of flow directory */ 882 #define hns3_dev_fd_queue_region_supported(hw) \ 883 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B) 884 885 /* Support PTP timestamp offload */ 886 #define hns3_dev_ptp_supported(hw) \ 887 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B) 888 889 #define hns3_dev_tx_push_supported(hw) \ 890 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B) 891 892 /* Support to Independently enable/disable/reset Tx or Rx queues */ 893 #define hns3_dev_indep_txrx_supported(hw) \ 894 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B) 895 896 #define hns3_dev_stash_supported(hw) \ 897 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B) 898 899 #define hns3_dev_rxd_adv_layout_supported(hw) \ 900 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) 901 902 #define hns3_dev_outer_udp_cksum_supported(hw) \ 903 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) 904 905 #define hns3_dev_ras_imp_supported(hw) \ 906 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B) 907 908 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ 909 (&((struct hns3_adapter *)adapter)->hw) 910 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ 911 (&((struct hns3_adapter *)adapter)->pf) 912 #define HNS3_DEV_PRIVATE_TO_VF(adapter) \ 913 (&((struct hns3_adapter *)adapter)->vf) 914 #define HNS3_DEV_HW_TO_ADAPTER(hw) \ 915 container_of(hw, struct hns3_adapter, hw) 916 917 static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw) 918 { 919 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 920 return &adapter->pf; 921 } 922 923 static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw) 924 { 925 struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw); 926 return &adapter->vf; 927 } 928 929 #define hns3_set_field(origin, mask, shift, val) \ 930 do { \ 931 (origin) &= (~(mask)); \ 932 (origin) |= ((val) << (shift)) & (mask); \ 933 } while (0) 934 #define hns3_get_field(origin, mask, shift) \ 935 (((origin) & (mask)) >> (shift)) 936 #define hns3_set_bit(origin, shift, val) \ 937 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val)) 938 #define hns3_get_bit(origin, shift) \ 939 hns3_get_field((origin), (0x1UL << (shift)), (shift)) 940 941 #define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask)) 942 943 /* 944 * upper_32_bits - return bits 32-63 of a number 945 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress 946 * the "right shift count >= width of type" warning when that quantity is 947 * 32-bits. 948 */ 949 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 950 951 /* lower_32_bits - return bits 0-31 of a number */ 952 #define lower_32_bits(n) ((uint32_t)(n)) 953 954 #define BIT(nr) (1UL << (nr)) 955 956 #define BIT_ULL(x) (1ULL << (x)) 957 958 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 959 #define GENMASK(h, l) \ 960 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 961 962 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 963 #define rounddown(x, y) ((x) - ((x) % (y))) 964 965 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 966 967 /* 968 * Because hardware always access register in little-endian mode based on hns3 969 * network engine, so driver should also call rte_cpu_to_le_32 to convert data 970 * in little-endian mode before writing register and call rte_le_to_cpu_32 to 971 * convert data after reading from register. 972 * 973 * Here the driver encapsulates the data conversion operation in the register 974 * read/write operation function as below: 975 * hns3_write_reg 976 * hns3_write_reg_opt 977 * hns3_read_reg 978 * Therefore, when calling these functions, conversion is not required again. 979 */ 980 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value) 981 { 982 rte_write32(rte_cpu_to_le_32(value), 983 (volatile void *)((char *)base + reg)); 984 } 985 986 /* 987 * The optimized function for writing registers used in the '.rx_pkt_burst' and 988 * '.tx_pkt_burst' ops implementation function. 989 */ 990 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value) 991 { 992 rte_io_wmb(); 993 rte_write32_relaxed(rte_cpu_to_le_32(value), addr); 994 } 995 996 static inline uint32_t hns3_read_reg(void *base, uint32_t reg) 997 { 998 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg)); 999 return rte_le_to_cpu_32(read_val); 1000 } 1001 1002 #define hns3_write_dev(a, reg, value) \ 1003 hns3_write_reg((a)->io_base, (reg), (value)) 1004 1005 #define hns3_read_dev(a, reg) \ 1006 hns3_read_reg((a)->io_base, (reg)) 1007 1008 #define ARRAY_SIZE(x) RTE_DIM(x) 1009 1010 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 1011 do { \ 1012 act = (actions) + (index); \ 1013 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 1014 (index)++; \ 1015 act = actions + index; \ 1016 } \ 1017 } while (0) 1018 1019 #define MSEC_PER_SEC 1000L 1020 #define USEC_PER_MSEC 1000L 1021 1022 static inline uint64_t 1023 get_timeofday_ms(void) 1024 { 1025 struct timeval tv; 1026 1027 (void)gettimeofday(&tv, NULL); 1028 1029 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; 1030 } 1031 1032 static inline uint64_t 1033 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) 1034 { 1035 uint64_t res; 1036 1037 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0; 1038 return res; 1039 } 1040 1041 static inline void 1042 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr) 1043 { 1044 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED); 1045 } 1046 1047 static inline void 1048 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr) 1049 { 1050 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED); 1051 } 1052 1053 static inline int64_t 1054 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) 1055 { 1056 uint64_t mask = (1UL << nr); 1057 1058 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; 1059 } 1060 1061 int hns3_buffer_alloc(struct hns3_hw *hw); 1062 int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, 1063 const struct rte_flow_ops **ops); 1064 bool hns3_is_reset_pending(struct hns3_adapter *hns); 1065 bool hns3vf_is_reset_pending(struct hns3_adapter *hns); 1066 void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); 1067 void hns3_ether_format_addr(char *buf, uint16_t size, 1068 const struct rte_ether_addr *ether_addr); 1069 int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, 1070 struct rte_eth_dev_info *info); 1071 void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, 1072 uint32_t link_speed, uint8_t link_duplex); 1073 void hns3_parse_devargs(struct rte_eth_dev *dev); 1074 void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); 1075 int hns3_restore_ptp(struct hns3_adapter *hns); 1076 int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev, 1077 struct rte_eth_conf *conf); 1078 int hns3_ptp_init(struct hns3_hw *hw); 1079 int hns3_timesync_enable(struct rte_eth_dev *dev); 1080 int hns3_timesync_disable(struct rte_eth_dev *dev); 1081 int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1082 struct timespec *timestamp, 1083 uint32_t flags __rte_unused); 1084 int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1085 struct timespec *timestamp); 1086 int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts); 1087 int hns3_timesync_write_time(struct rte_eth_dev *dev, 1088 const struct timespec *ts); 1089 int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 1090 1091 static inline bool 1092 is_reset_pending(struct hns3_adapter *hns) 1093 { 1094 bool ret; 1095 if (hns->is_vf) 1096 ret = hns3vf_is_reset_pending(hns); 1097 else 1098 ret = hns3_is_reset_pending(hns); 1099 return ret; 1100 } 1101 1102 static inline uint64_t 1103 hns3_txvlan_cap_get(struct hns3_hw *hw) 1104 { 1105 if (hw->port_base_vlan_cfg.state) 1106 return DEV_TX_OFFLOAD_VLAN_INSERT; 1107 else 1108 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; 1109 } 1110 1111 #endif /* _HNS3_ETHDEV_H_ */ 1112