1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <errno.h> 6 #include <stdarg.h> 7 #include <stdbool.h> 8 #include <stdio.h> 9 #include <stdint.h> 10 #include <inttypes.h> 11 #include <unistd.h> 12 #include <rte_atomic.h> 13 #include <rte_bus_pci.h> 14 #include <rte_common.h> 15 #include <rte_cycles.h> 16 #include <rte_dev.h> 17 #include <rte_eal.h> 18 #include <rte_ether.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_interrupts.h> 22 #include <rte_io.h> 23 #include <rte_log.h> 24 #include <rte_pci.h> 25 26 #include "hns3_ethdev.h" 27 #include "hns3_logs.h" 28 #include "hns3_rxtx.h" 29 #include "hns3_intr.h" 30 #include "hns3_regs.h" 31 #include "hns3_dcb.h" 32 #include "hns3_mp.h" 33 34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 36 37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 38 #define HNS3_PORT_BASE_VLAN_DISABLE 0 39 #define HNS3_PORT_BASE_VLAN_ENABLE 1 40 #define HNS3_INVLID_PVID 0xFFFF 41 42 #define HNS3_FILTER_TYPE_VF 0 43 #define HNS3_FILTER_TYPE_PORT 1 44 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 45 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 46 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 47 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 48 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 49 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 50 | HNS3_FILTER_FE_ROCE_EGRESS_B) 51 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 52 | HNS3_FILTER_FE_ROCE_INGRESS_B) 53 54 /* Reset related Registers */ 55 #define HNS3_GLOBAL_RESET_BIT 0 56 #define HNS3_CORE_RESET_BIT 1 57 #define HNS3_IMP_RESET_BIT 2 58 #define HNS3_FUN_RST_ING_B 0 59 60 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 61 62 #define HNS3_RESET_WAIT_MS 100 63 #define HNS3_RESET_WAIT_CNT 200 64 65 int hns3_logtype_init; 66 int hns3_logtype_driver; 67 68 enum hns3_evt_cause { 69 HNS3_VECTOR0_EVENT_RST, 70 HNS3_VECTOR0_EVENT_MBX, 71 HNS3_VECTOR0_EVENT_ERR, 72 HNS3_VECTOR0_EVENT_OTHER, 73 }; 74 75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 76 uint64_t *levels); 77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 79 int on); 80 81 static void 82 hns3_pf_disable_irq0(struct hns3_hw *hw) 83 { 84 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 85 } 86 87 static void 88 hns3_pf_enable_irq0(struct hns3_hw *hw) 89 { 90 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 91 } 92 93 static enum hns3_evt_cause 94 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 95 { 96 struct hns3_hw *hw = &hns->hw; 97 uint32_t vector0_int_stats; 98 uint32_t cmdq_src_val; 99 uint32_t val; 100 enum hns3_evt_cause ret; 101 102 /* fetch the events from their corresponding regs */ 103 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 104 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 105 106 /* 107 * Assumption: If by any chance reset and mailbox events are reported 108 * together then we will only process reset event and defer the 109 * processing of the mailbox events. Since, we would have not cleared 110 * RX CMDQ event this time we would receive again another interrupt 111 * from H/W just for the mailbox. 112 */ 113 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 114 rte_atomic16_set(&hw->reset.disable_cmd, 1); 115 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 116 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 117 if (clearval) { 118 hw->reset.stats.imp_cnt++; 119 hns3_warn(hw, "IMP reset detected, clear reset status"); 120 } else { 121 hns3_schedule_delayed_reset(hns); 122 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 123 } 124 125 ret = HNS3_VECTOR0_EVENT_RST; 126 goto out; 127 } 128 129 /* Global reset */ 130 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 131 rte_atomic16_set(&hw->reset.disable_cmd, 1); 132 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 133 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 134 if (clearval) { 135 hw->reset.stats.global_cnt++; 136 hns3_warn(hw, "Global reset detected, clear reset status"); 137 } else { 138 hns3_schedule_delayed_reset(hns); 139 hns3_warn(hw, "Global reset detected, don't clear reset status"); 140 } 141 142 ret = HNS3_VECTOR0_EVENT_RST; 143 goto out; 144 } 145 146 /* check for vector0 msix event source */ 147 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) { 148 val = vector0_int_stats; 149 ret = HNS3_VECTOR0_EVENT_ERR; 150 goto out; 151 } 152 153 /* check for vector0 mailbox(=CMDQ RX) event source */ 154 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 155 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 156 val = cmdq_src_val; 157 ret = HNS3_VECTOR0_EVENT_MBX; 158 goto out; 159 } 160 161 if (clearval && (vector0_int_stats || cmdq_src_val)) 162 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x", 163 vector0_int_stats, cmdq_src_val); 164 val = vector0_int_stats; 165 ret = HNS3_VECTOR0_EVENT_OTHER; 166 out: 167 168 if (clearval) 169 *clearval = val; 170 return ret; 171 } 172 173 static void 174 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 175 { 176 if (event_type == HNS3_VECTOR0_EVENT_RST) 177 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 178 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 179 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 180 } 181 182 static void 183 hns3_clear_all_event_cause(struct hns3_hw *hw) 184 { 185 uint32_t vector0_int_stats; 186 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 187 188 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 189 hns3_warn(hw, "Probe during IMP reset interrupt"); 190 191 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 192 hns3_warn(hw, "Probe during Global reset interrupt"); 193 194 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 195 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 196 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 197 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 198 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 199 } 200 201 static void 202 hns3_interrupt_handler(void *param) 203 { 204 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 205 struct hns3_adapter *hns = dev->data->dev_private; 206 struct hns3_hw *hw = &hns->hw; 207 enum hns3_evt_cause event_cause; 208 uint32_t clearval = 0; 209 210 /* Disable interrupt */ 211 hns3_pf_disable_irq0(hw); 212 213 event_cause = hns3_check_event_cause(hns, &clearval); 214 215 /* vector 0 interrupt is shared with reset and mailbox source events. */ 216 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 217 hns3_handle_msix_error(hns, &hw->reset.request); 218 hns3_schedule_reset(hns); 219 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) 220 hns3_schedule_reset(hns); 221 else 222 hns3_err(hw, "Received unknown event"); 223 224 hns3_clear_event_cause(hw, event_cause, clearval); 225 /* Enable interrupt if it is not cause by reset */ 226 hns3_pf_enable_irq0(hw); 227 } 228 229 static int 230 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 231 { 232 #define HNS3_VLAN_OFFSET_160 160 233 struct hns3_vlan_filter_pf_cfg_cmd *req; 234 struct hns3_hw *hw = &hns->hw; 235 uint8_t vlan_offset_byte_val; 236 struct hns3_cmd_desc desc; 237 uint8_t vlan_offset_byte; 238 uint8_t vlan_offset_160; 239 int ret; 240 241 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 242 243 vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160; 244 vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8; 245 vlan_offset_byte_val = 1 << (vlan_id % 8); 246 247 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 248 req->vlan_offset = vlan_offset_160; 249 req->vlan_cfg = on ? 0 : 1; 250 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 251 252 ret = hns3_cmd_send(hw, &desc, 1); 253 if (ret) 254 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 255 vlan_id, ret); 256 257 return ret; 258 } 259 260 static void 261 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 262 { 263 struct hns3_user_vlan_table *vlan_entry; 264 struct hns3_pf *pf = &hns->pf; 265 266 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 267 if (vlan_entry->vlan_id == vlan_id) { 268 if (vlan_entry->hd_tbl_status) 269 hns3_set_port_vlan_filter(hns, vlan_id, 0); 270 LIST_REMOVE(vlan_entry, next); 271 rte_free(vlan_entry); 272 break; 273 } 274 } 275 } 276 277 static void 278 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 279 bool writen_to_tbl) 280 { 281 struct hns3_user_vlan_table *vlan_entry; 282 struct hns3_hw *hw = &hns->hw; 283 struct hns3_pf *pf = &hns->pf; 284 285 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 286 if (vlan_entry->vlan_id == vlan_id) 287 return; 288 } 289 290 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 291 if (vlan_entry == NULL) { 292 hns3_err(hw, "Failed to malloc hns3 vlan table"); 293 return; 294 } 295 296 vlan_entry->hd_tbl_status = writen_to_tbl; 297 vlan_entry->vlan_id = vlan_id; 298 299 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 300 } 301 302 static int 303 hns3_restore_vlan_table(struct hns3_adapter *hns) 304 { 305 struct hns3_user_vlan_table *vlan_entry; 306 struct hns3_pf *pf = &hns->pf; 307 uint16_t vlan_id; 308 int ret = 0; 309 310 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) { 311 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid, 312 1); 313 return ret; 314 } 315 316 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 317 if (vlan_entry->hd_tbl_status) { 318 vlan_id = vlan_entry->vlan_id; 319 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 320 if (ret) 321 break; 322 } 323 } 324 325 return ret; 326 } 327 328 static int 329 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 330 { 331 struct hns3_pf *pf = &hns->pf; 332 bool writen_to_tbl = false; 333 int ret = 0; 334 335 /* 336 * When vlan filter is enabled, hardware regards vlan id 0 as the entry 337 * for normal packet, deleting vlan id 0 is not allowed. 338 */ 339 if (on == 0 && vlan_id == 0) 340 return 0; 341 342 /* 343 * When port base vlan enabled, we use port base vlan as the vlan 344 * filter condition. In this case, we don't update vlan filter table 345 * when user add new vlan or remove exist vlan, just update the 346 * vlan list. The vlan id in vlan list will be writen in vlan filter 347 * table until port base vlan disabled 348 */ 349 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 350 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 351 writen_to_tbl = true; 352 } 353 354 if (ret == 0 && vlan_id) { 355 if (on) 356 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 357 else 358 hns3_rm_dev_vlan_table(hns, vlan_id); 359 } 360 return ret; 361 } 362 363 static int 364 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 365 { 366 struct hns3_adapter *hns = dev->data->dev_private; 367 struct hns3_hw *hw = &hns->hw; 368 int ret; 369 370 rte_spinlock_lock(&hw->lock); 371 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 372 rte_spinlock_unlock(&hw->lock); 373 return ret; 374 } 375 376 static int 377 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 378 uint16_t tpid) 379 { 380 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 381 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 382 struct hns3_hw *hw = &hns->hw; 383 struct hns3_cmd_desc desc; 384 int ret; 385 386 if ((vlan_type != ETH_VLAN_TYPE_INNER && 387 vlan_type != ETH_VLAN_TYPE_OUTER)) { 388 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 389 return -EINVAL; 390 } 391 392 if (tpid != RTE_ETHER_TYPE_VLAN) { 393 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 394 return -EINVAL; 395 } 396 397 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 398 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 399 400 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 401 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 402 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 403 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 404 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 405 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 406 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 407 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 408 } 409 410 ret = hns3_cmd_send(hw, &desc, 1); 411 if (ret) { 412 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 413 ret); 414 return ret; 415 } 416 417 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 418 419 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 420 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 421 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 422 423 ret = hns3_cmd_send(hw, &desc, 1); 424 if (ret) 425 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 426 ret); 427 return ret; 428 } 429 430 static int 431 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 432 uint16_t tpid) 433 { 434 struct hns3_adapter *hns = dev->data->dev_private; 435 struct hns3_hw *hw = &hns->hw; 436 int ret; 437 438 rte_spinlock_lock(&hw->lock); 439 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 440 rte_spinlock_unlock(&hw->lock); 441 return ret; 442 } 443 444 static int 445 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 446 struct hns3_rx_vtag_cfg *vcfg) 447 { 448 struct hns3_vport_vtag_rx_cfg_cmd *req; 449 struct hns3_hw *hw = &hns->hw; 450 struct hns3_cmd_desc desc; 451 uint16_t vport_id; 452 uint8_t bitmap; 453 int ret; 454 455 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 456 457 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 458 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 459 vcfg->strip_tag1_en ? 1 : 0); 460 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 461 vcfg->strip_tag2_en ? 1 : 0); 462 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 463 vcfg->vlan1_vlan_prionly ? 1 : 0); 464 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 465 vcfg->vlan2_vlan_prionly ? 1 : 0); 466 467 /* 468 * In current version VF is not supported when PF is driven by DPDK 469 * driver, the PF-related vf_id is 0, just need to configure parameters 470 * for vport_id 0. 471 */ 472 vport_id = 0; 473 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 474 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 475 req->vf_bitmap[req->vf_offset] = bitmap; 476 477 ret = hns3_cmd_send(hw, &desc, 1); 478 if (ret) 479 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 480 return ret; 481 } 482 483 static void 484 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 485 struct hns3_rx_vtag_cfg *vcfg) 486 { 487 struct hns3_pf *pf = &hns->pf; 488 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 489 } 490 491 static void 492 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 493 struct hns3_tx_vtag_cfg *vcfg) 494 { 495 struct hns3_pf *pf = &hns->pf; 496 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 497 } 498 499 static int 500 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 501 { 502 struct hns3_rx_vtag_cfg rxvlan_cfg; 503 struct hns3_pf *pf = &hns->pf; 504 struct hns3_hw *hw = &hns->hw; 505 int ret; 506 507 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 508 rxvlan_cfg.strip_tag1_en = false; 509 rxvlan_cfg.strip_tag2_en = enable; 510 } else { 511 rxvlan_cfg.strip_tag1_en = enable; 512 rxvlan_cfg.strip_tag2_en = true; 513 } 514 515 rxvlan_cfg.vlan1_vlan_prionly = false; 516 rxvlan_cfg.vlan2_vlan_prionly = false; 517 rxvlan_cfg.rx_vlan_offload_en = enable; 518 519 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 520 if (ret) { 521 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret); 522 return ret; 523 } 524 525 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 526 527 return ret; 528 } 529 530 static int 531 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 532 uint8_t fe_type, bool filter_en, uint8_t vf_id) 533 { 534 struct hns3_vlan_filter_ctrl_cmd *req; 535 struct hns3_cmd_desc desc; 536 int ret; 537 538 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 539 540 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 541 req->vlan_type = vlan_type; 542 req->vlan_fe = filter_en ? fe_type : 0; 543 req->vf_id = vf_id; 544 545 ret = hns3_cmd_send(hw, &desc, 1); 546 if (ret) 547 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 548 549 return ret; 550 } 551 552 static int 553 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 554 { 555 struct hns3_hw *hw = &hns->hw; 556 int ret; 557 558 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 559 HNS3_FILTER_FE_EGRESS, false, 0); 560 if (ret) { 561 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret); 562 return ret; 563 } 564 565 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 566 HNS3_FILTER_FE_INGRESS, enable, 0); 567 if (ret) 568 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret); 569 570 return ret; 571 } 572 573 static int 574 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 575 { 576 struct hns3_adapter *hns = dev->data->dev_private; 577 struct hns3_hw *hw = &hns->hw; 578 struct rte_eth_rxmode *rxmode; 579 unsigned int tmp_mask; 580 bool enable; 581 int ret = 0; 582 583 rte_spinlock_lock(&hw->lock); 584 rxmode = &dev->data->dev_conf.rxmode; 585 tmp_mask = (unsigned int)mask; 586 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 587 /* Enable or disable VLAN stripping */ 588 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 589 true : false; 590 591 ret = hns3_en_hw_strip_rxvtag(hns, enable); 592 if (ret) { 593 rte_spinlock_unlock(&hw->lock); 594 hns3_err(hw, "failed to enable rx strip, ret =%d", ret); 595 return ret; 596 } 597 } 598 599 rte_spinlock_unlock(&hw->lock); 600 601 return ret; 602 } 603 604 static int 605 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 606 struct hns3_tx_vtag_cfg *vcfg) 607 { 608 struct hns3_vport_vtag_tx_cfg_cmd *req; 609 struct hns3_cmd_desc desc; 610 struct hns3_hw *hw = &hns->hw; 611 uint16_t vport_id; 612 uint8_t bitmap; 613 int ret; 614 615 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 616 617 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 618 req->def_vlan_tag1 = vcfg->default_tag1; 619 req->def_vlan_tag2 = vcfg->default_tag2; 620 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 621 vcfg->accept_tag1 ? 1 : 0); 622 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 623 vcfg->accept_untag1 ? 1 : 0); 624 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 625 vcfg->accept_tag2 ? 1 : 0); 626 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 627 vcfg->accept_untag2 ? 1 : 0); 628 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 629 vcfg->insert_tag1_en ? 1 : 0); 630 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 631 vcfg->insert_tag2_en ? 1 : 0); 632 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 633 634 /* 635 * In current version VF is not supported when PF is driven by DPDK 636 * driver, the PF-related vf_id is 0, just need to configure parameters 637 * for vport_id 0. 638 */ 639 vport_id = 0; 640 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 641 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 642 req->vf_bitmap[req->vf_offset] = bitmap; 643 644 ret = hns3_cmd_send(hw, &desc, 1); 645 if (ret) 646 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 647 648 return ret; 649 } 650 651 static int 652 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 653 uint16_t pvid) 654 { 655 struct hns3_hw *hw = &hns->hw; 656 struct hns3_tx_vtag_cfg txvlan_cfg; 657 int ret; 658 659 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 660 txvlan_cfg.accept_tag1 = true; 661 txvlan_cfg.insert_tag1_en = false; 662 txvlan_cfg.default_tag1 = 0; 663 } else { 664 txvlan_cfg.accept_tag1 = false; 665 txvlan_cfg.insert_tag1_en = true; 666 txvlan_cfg.default_tag1 = pvid; 667 } 668 669 txvlan_cfg.accept_untag1 = true; 670 txvlan_cfg.accept_tag2 = true; 671 txvlan_cfg.accept_untag2 = true; 672 txvlan_cfg.insert_tag2_en = false; 673 txvlan_cfg.default_tag2 = 0; 674 675 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 676 if (ret) { 677 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 678 ret); 679 return ret; 680 } 681 682 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 683 return ret; 684 } 685 686 static void 687 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on) 688 { 689 struct hns3_pf *pf = &hns->pf; 690 691 pf->port_base_vlan_cfg.state = on ? 692 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 693 694 pf->port_base_vlan_cfg.pvid = pvid; 695 } 696 697 static void 698 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 699 { 700 struct hns3_user_vlan_table *vlan_entry; 701 struct hns3_pf *pf = &hns->pf; 702 703 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 704 if (vlan_entry->hd_tbl_status) 705 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 706 707 vlan_entry->hd_tbl_status = false; 708 } 709 710 if (is_del_list) { 711 vlan_entry = LIST_FIRST(&pf->vlan_list); 712 while (vlan_entry) { 713 LIST_REMOVE(vlan_entry, next); 714 rte_free(vlan_entry); 715 vlan_entry = LIST_FIRST(&pf->vlan_list); 716 } 717 } 718 } 719 720 static void 721 hns3_add_all_vlan_table(struct hns3_adapter *hns) 722 { 723 struct hns3_user_vlan_table *vlan_entry; 724 struct hns3_pf *pf = &hns->pf; 725 726 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 727 if (!vlan_entry->hd_tbl_status) 728 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 729 730 vlan_entry->hd_tbl_status = true; 731 } 732 } 733 734 static void 735 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 736 { 737 struct hns3_hw *hw = &hns->hw; 738 struct hns3_pf *pf = &hns->pf; 739 int ret; 740 741 hns3_rm_all_vlan_table(hns, true); 742 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) { 743 ret = hns3_set_port_vlan_filter(hns, 744 pf->port_base_vlan_cfg.pvid, 0); 745 if (ret) { 746 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 747 ret); 748 return; 749 } 750 } 751 } 752 753 static int 754 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 755 uint16_t port_base_vlan_state, 756 uint16_t new_pvid, uint16_t old_pvid) 757 { 758 struct hns3_pf *pf = &hns->pf; 759 struct hns3_hw *hw = &hns->hw; 760 int ret = 0; 761 762 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 763 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) { 764 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 765 if (ret) { 766 hns3_err(hw, 767 "Failed to clear clear old pvid filter, ret =%d", 768 ret); 769 return ret; 770 } 771 } 772 773 hns3_rm_all_vlan_table(hns, false); 774 return hns3_set_port_vlan_filter(hns, new_pvid, 1); 775 } 776 777 if (new_pvid != 0) { 778 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 779 if (ret) { 780 hns3_err(hw, "Failed to set port vlan filter, ret =%d", 781 ret); 782 return ret; 783 } 784 } 785 786 if (new_pvid == pf->port_base_vlan_cfg.pvid) 787 hns3_add_all_vlan_table(hns); 788 789 return ret; 790 } 791 792 static int 793 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on) 794 { 795 struct hns3_rx_vtag_cfg rx_vlan_cfg; 796 struct hns3_hw *hw = &hns->hw; 797 bool rx_strip_en; 798 int ret; 799 800 rx_strip_en = on ? true : false; 801 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 802 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 803 rx_vlan_cfg.vlan1_vlan_prionly = false; 804 rx_vlan_cfg.vlan2_vlan_prionly = false; 805 rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en; 806 807 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 808 if (ret) { 809 hns3_err(hw, "enable strip rx failed, ret =%d", ret); 810 return ret; 811 } 812 813 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 814 return ret; 815 } 816 817 static int 818 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 819 { 820 struct hns3_pf *pf = &hns->pf; 821 struct hns3_hw *hw = &hns->hw; 822 uint16_t port_base_vlan_state; 823 uint16_t old_pvid; 824 int ret; 825 826 if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) { 827 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) 828 hns3_warn(hw, "Invalid operation! As current pvid set " 829 "is %u, disable pvid %u is invalid", 830 pf->port_base_vlan_cfg.pvid, pvid); 831 return 0; 832 } 833 834 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 835 HNS3_PORT_BASE_VLAN_DISABLE; 836 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 837 if (ret) { 838 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret); 839 return ret; 840 } 841 842 ret = hns3_en_rx_strip_all(hns, on); 843 if (ret) { 844 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret); 845 return ret; 846 } 847 848 if (pvid == HNS3_INVLID_PVID) 849 goto out; 850 old_pvid = pf->port_base_vlan_cfg.pvid; 851 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid, 852 old_pvid); 853 if (ret) { 854 hns3_err(hw, "Failed to update vlan filter entries, ret =%d", 855 ret); 856 return ret; 857 } 858 859 out: 860 hns3_store_port_base_vlan_info(hns, pvid, on); 861 return ret; 862 } 863 864 static int 865 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 866 { 867 struct hns3_adapter *hns = dev->data->dev_private; 868 struct hns3_hw *hw = &hns->hw; 869 int ret; 870 871 rte_spinlock_lock(&hw->lock); 872 ret = hns3_vlan_pvid_configure(hns, pvid, on); 873 rte_spinlock_unlock(&hw->lock); 874 return ret; 875 } 876 877 static void 878 init_port_base_vlan_info(struct hns3_hw *hw) 879 { 880 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 881 struct hns3_pf *pf = &hns->pf; 882 883 pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 884 pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID; 885 } 886 887 static int 888 hns3_default_vlan_config(struct hns3_adapter *hns) 889 { 890 struct hns3_hw *hw = &hns->hw; 891 int ret; 892 893 ret = hns3_set_port_vlan_filter(hns, 0, 1); 894 if (ret) 895 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 896 return ret; 897 } 898 899 static int 900 hns3_init_vlan_config(struct hns3_adapter *hns) 901 { 902 struct hns3_hw *hw = &hns->hw; 903 int ret; 904 905 /* 906 * This function can be called in the initialization and reset process, 907 * when in reset process, it means that hardware had been reseted 908 * successfully and we need to restore the hardware configuration to 909 * ensure that the hardware configuration remains unchanged before and 910 * after reset. 911 */ 912 if (rte_atomic16_read(&hw->reset.resetting) == 0) 913 init_port_base_vlan_info(hw); 914 915 ret = hns3_enable_vlan_filter(hns, true); 916 if (ret) { 917 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 918 return ret; 919 } 920 921 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 922 RTE_ETHER_TYPE_VLAN); 923 if (ret) { 924 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 925 return ret; 926 } 927 928 /* 929 * When in the reinit dev stage of the reset process, the following 930 * vlan-related configurations may differ from those at initialization, 931 * we will restore configurations to hardware in hns3_restore_vlan_table 932 * and hns3_restore_vlan_conf later. 933 */ 934 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 935 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0); 936 if (ret) { 937 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 938 return ret; 939 } 940 941 ret = hns3_en_hw_strip_rxvtag(hns, false); 942 if (ret) { 943 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 944 ret); 945 return ret; 946 } 947 } 948 949 return hns3_default_vlan_config(hns); 950 } 951 952 static int 953 hns3_restore_vlan_conf(struct hns3_adapter *hns) 954 { 955 struct hns3_pf *pf = &hns->pf; 956 struct hns3_hw *hw = &hns->hw; 957 int ret; 958 959 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 960 if (ret) { 961 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret); 962 return ret; 963 } 964 965 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 966 if (ret) 967 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret); 968 969 return ret; 970 } 971 972 static int 973 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 974 { 975 struct hns3_adapter *hns = dev->data->dev_private; 976 struct rte_eth_dev_data *data = dev->data; 977 struct rte_eth_txmode *txmode; 978 struct hns3_hw *hw = &hns->hw; 979 int ret; 980 981 txmode = &data->dev_conf.txmode; 982 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 983 hns3_warn(hw, 984 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 985 "configuration is not supported! Ignore these two " 986 "parameters: hw_vlan_reject_tagged(%d), " 987 "hw_vlan_reject_untagged(%d)", 988 txmode->hw_vlan_reject_tagged, 989 txmode->hw_vlan_reject_untagged); 990 991 /* Apply vlan offload setting */ 992 ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK); 993 if (ret) { 994 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret); 995 return ret; 996 } 997 998 /* Apply pvid setting */ 999 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1000 txmode->hw_vlan_insert_pvid); 1001 if (ret) 1002 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d", 1003 txmode->pvid, ret); 1004 1005 return ret; 1006 } 1007 1008 static int 1009 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1010 unsigned int tso_mss_max) 1011 { 1012 struct hns3_cfg_tso_status_cmd *req; 1013 struct hns3_cmd_desc desc; 1014 uint16_t tso_mss; 1015 1016 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1017 1018 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1019 1020 tso_mss = 0; 1021 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1022 tso_mss_min); 1023 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1024 1025 tso_mss = 0; 1026 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1027 tso_mss_max); 1028 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1029 1030 return hns3_cmd_send(hw, &desc, 1); 1031 } 1032 1033 int 1034 hns3_config_gro(struct hns3_hw *hw, bool en) 1035 { 1036 struct hns3_cfg_gro_status_cmd *req; 1037 struct hns3_cmd_desc desc; 1038 int ret; 1039 1040 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false); 1041 req = (struct hns3_cfg_gro_status_cmd *)desc.data; 1042 1043 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0); 1044 1045 ret = hns3_cmd_send(hw, &desc, 1); 1046 if (ret) 1047 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret); 1048 1049 return ret; 1050 } 1051 1052 static int 1053 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1054 uint16_t *allocated_size, bool is_alloc) 1055 { 1056 struct hns3_umv_spc_alc_cmd *req; 1057 struct hns3_cmd_desc desc; 1058 int ret; 1059 1060 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1061 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1062 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1063 req->space_size = rte_cpu_to_le_32(space_size); 1064 1065 ret = hns3_cmd_send(hw, &desc, 1); 1066 if (ret) { 1067 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1068 is_alloc ? "allocate" : "free", ret); 1069 return ret; 1070 } 1071 1072 if (is_alloc && allocated_size) 1073 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1074 1075 return 0; 1076 } 1077 1078 static int 1079 hns3_init_umv_space(struct hns3_hw *hw) 1080 { 1081 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1082 struct hns3_pf *pf = &hns->pf; 1083 uint16_t allocated_size = 0; 1084 int ret; 1085 1086 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1087 true); 1088 if (ret) 1089 return ret; 1090 1091 if (allocated_size < pf->wanted_umv_size) 1092 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1093 pf->wanted_umv_size, allocated_size); 1094 1095 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1096 pf->wanted_umv_size; 1097 pf->used_umv_size = 0; 1098 return 0; 1099 } 1100 1101 static int 1102 hns3_uninit_umv_space(struct hns3_hw *hw) 1103 { 1104 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1105 struct hns3_pf *pf = &hns->pf; 1106 int ret; 1107 1108 if (pf->max_umv_size == 0) 1109 return 0; 1110 1111 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1112 if (ret) 1113 return ret; 1114 1115 pf->max_umv_size = 0; 1116 1117 return 0; 1118 } 1119 1120 static bool 1121 hns3_is_umv_space_full(struct hns3_hw *hw) 1122 { 1123 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1124 struct hns3_pf *pf = &hns->pf; 1125 bool is_full; 1126 1127 is_full = (pf->used_umv_size >= pf->max_umv_size); 1128 1129 return is_full; 1130 } 1131 1132 static void 1133 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1134 { 1135 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1136 struct hns3_pf *pf = &hns->pf; 1137 1138 if (is_free) { 1139 if (pf->used_umv_size > 0) 1140 pf->used_umv_size--; 1141 } else 1142 pf->used_umv_size++; 1143 } 1144 1145 static void 1146 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1147 const uint8_t *addr, bool is_mc) 1148 { 1149 const unsigned char *mac_addr = addr; 1150 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1151 ((uint32_t)mac_addr[2] << 16) | 1152 ((uint32_t)mac_addr[1] << 8) | 1153 (uint32_t)mac_addr[0]; 1154 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1155 1156 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1157 if (is_mc) { 1158 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1159 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1160 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1161 } 1162 1163 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1164 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1165 } 1166 1167 static int 1168 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1169 uint8_t resp_code, 1170 enum hns3_mac_vlan_tbl_opcode op) 1171 { 1172 if (cmdq_resp) { 1173 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1174 cmdq_resp); 1175 return -EIO; 1176 } 1177 1178 if (op == HNS3_MAC_VLAN_ADD) { 1179 if (resp_code == 0 || resp_code == 1) { 1180 return 0; 1181 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1182 hns3_err(hw, "add mac addr failed for uc_overflow"); 1183 return -ENOSPC; 1184 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1185 hns3_err(hw, "add mac addr failed for mc_overflow"); 1186 return -ENOSPC; 1187 } 1188 1189 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1190 resp_code); 1191 return -EIO; 1192 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1193 if (resp_code == 0) { 1194 return 0; 1195 } else if (resp_code == 1) { 1196 hns3_dbg(hw, "remove mac addr failed for miss"); 1197 return -ENOENT; 1198 } 1199 1200 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1201 resp_code); 1202 return -EIO; 1203 } else if (op == HNS3_MAC_VLAN_LKUP) { 1204 if (resp_code == 0) { 1205 return 0; 1206 } else if (resp_code == 1) { 1207 hns3_dbg(hw, "lookup mac addr failed for miss"); 1208 return -ENOENT; 1209 } 1210 1211 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1212 resp_code); 1213 return -EIO; 1214 } 1215 1216 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1217 op); 1218 1219 return -EINVAL; 1220 } 1221 1222 static int 1223 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1224 struct hns3_mac_vlan_tbl_entry_cmd *req, 1225 struct hns3_cmd_desc *desc, bool is_mc) 1226 { 1227 uint8_t resp_code; 1228 uint16_t retval; 1229 int ret; 1230 1231 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true); 1232 if (is_mc) { 1233 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1234 memcpy(desc[0].data, req, 1235 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1236 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD, 1237 true); 1238 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1239 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD, 1240 true); 1241 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1242 } else { 1243 memcpy(desc[0].data, req, 1244 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1245 ret = hns3_cmd_send(hw, desc, 1); 1246 } 1247 if (ret) { 1248 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1249 ret); 1250 return ret; 1251 } 1252 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1253 retval = rte_le_to_cpu_16(desc[0].retval); 1254 1255 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1256 HNS3_MAC_VLAN_LKUP); 1257 } 1258 1259 static int 1260 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1261 struct hns3_mac_vlan_tbl_entry_cmd *req, 1262 struct hns3_cmd_desc *mc_desc) 1263 { 1264 uint8_t resp_code; 1265 uint16_t retval; 1266 int cfg_status; 1267 int ret; 1268 1269 if (mc_desc == NULL) { 1270 struct hns3_cmd_desc desc; 1271 1272 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false); 1273 memcpy(desc.data, req, 1274 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1275 ret = hns3_cmd_send(hw, &desc, 1); 1276 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1277 retval = rte_le_to_cpu_16(desc.retval); 1278 1279 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1280 HNS3_MAC_VLAN_ADD); 1281 } else { 1282 hns3_cmd_reuse_desc(&mc_desc[0], false); 1283 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1284 hns3_cmd_reuse_desc(&mc_desc[1], false); 1285 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1286 hns3_cmd_reuse_desc(&mc_desc[2], false); 1287 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1288 memcpy(mc_desc[0].data, req, 1289 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1290 mc_desc[0].retval = 0; 1291 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1292 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff; 1293 retval = rte_le_to_cpu_16(mc_desc[0].retval); 1294 1295 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1296 HNS3_MAC_VLAN_ADD); 1297 } 1298 1299 if (ret) { 1300 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1301 return ret; 1302 } 1303 1304 return cfg_status; 1305 } 1306 1307 static int 1308 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1309 struct hns3_mac_vlan_tbl_entry_cmd *req) 1310 { 1311 struct hns3_cmd_desc desc; 1312 uint8_t resp_code; 1313 uint16_t retval; 1314 int ret; 1315 1316 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1317 1318 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1319 1320 ret = hns3_cmd_send(hw, &desc, 1); 1321 if (ret) { 1322 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1323 return ret; 1324 } 1325 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1326 retval = rte_le_to_cpu_16(desc.retval); 1327 1328 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1329 HNS3_MAC_VLAN_REMOVE); 1330 } 1331 1332 static int 1333 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1334 { 1335 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1336 struct hns3_mac_vlan_tbl_entry_cmd req; 1337 struct hns3_pf *pf = &hns->pf; 1338 struct hns3_cmd_desc desc; 1339 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1340 uint16_t egress_port = 0; 1341 uint8_t vf_id; 1342 int ret; 1343 1344 /* check if mac addr is valid */ 1345 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1346 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1347 mac_addr); 1348 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1349 mac_str); 1350 return -EINVAL; 1351 } 1352 1353 memset(&req, 0, sizeof(req)); 1354 1355 /* 1356 * In current version VF is not supported when PF is driven by DPDK 1357 * driver, the PF-related vf_id is 0, just need to configure parameters 1358 * for vf_id 0. 1359 */ 1360 vf_id = 0; 1361 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1362 HNS3_MAC_EPORT_VFID_S, vf_id); 1363 1364 req.egress_port = rte_cpu_to_le_16(egress_port); 1365 1366 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1367 1368 /* 1369 * Lookup the mac address in the mac_vlan table, and add 1370 * it if the entry is inexistent. Repeated unicast entry 1371 * is not allowed in the mac vlan table. 1372 */ 1373 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false); 1374 if (ret == -ENOENT) { 1375 if (!hns3_is_umv_space_full(hw)) { 1376 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); 1377 if (!ret) 1378 hns3_update_umv_space(hw, false); 1379 return ret; 1380 } 1381 1382 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1383 1384 return -ENOSPC; 1385 } 1386 1387 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1388 1389 /* check if we just hit the duplicate */ 1390 if (ret == 0) { 1391 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1392 return 0; 1393 } 1394 1395 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1396 mac_str); 1397 1398 return ret; 1399 } 1400 1401 static int 1402 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1403 uint32_t idx, __attribute__ ((unused)) uint32_t pool) 1404 { 1405 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1406 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1407 int ret; 1408 1409 rte_spinlock_lock(&hw->lock); 1410 ret = hns3_add_uc_addr_common(hw, mac_addr); 1411 if (ret) { 1412 rte_spinlock_unlock(&hw->lock); 1413 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1414 mac_addr); 1415 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret); 1416 return ret; 1417 } 1418 1419 if (idx == 0) 1420 hw->mac.default_addr_setted = true; 1421 rte_spinlock_unlock(&hw->lock); 1422 1423 return ret; 1424 } 1425 1426 static int 1427 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1428 { 1429 struct hns3_mac_vlan_tbl_entry_cmd req; 1430 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1431 int ret; 1432 1433 /* check if mac addr is valid */ 1434 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1435 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1436 mac_addr); 1437 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid", 1438 mac_str); 1439 return -EINVAL; 1440 } 1441 1442 memset(&req, 0, sizeof(req)); 1443 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1444 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1445 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1446 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1447 return 0; 1448 else if (ret == 0) 1449 hns3_update_umv_space(hw, true); 1450 1451 return ret; 1452 } 1453 1454 static void 1455 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1456 { 1457 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1458 /* index will be checked by upper level rte interface */ 1459 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1460 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1461 int ret; 1462 1463 rte_spinlock_lock(&hw->lock); 1464 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1465 if (ret) { 1466 rte_spinlock_unlock(&hw->lock); 1467 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1468 mac_addr); 1469 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret); 1470 return; 1471 } 1472 1473 if (idx == 0) 1474 hw->mac.default_addr_setted = false; 1475 rte_spinlock_unlock(&hw->lock); 1476 } 1477 1478 static int 1479 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1480 struct rte_ether_addr *mac_addr) 1481 { 1482 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1483 struct rte_ether_addr *oaddr; 1484 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1485 bool default_addr_setted; 1486 bool rm_succes = false; 1487 int ret, ret_val; 1488 1489 /* check if mac addr is valid */ 1490 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1491 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1492 mac_addr); 1493 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid", 1494 mac_str); 1495 return -EINVAL; 1496 } 1497 1498 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1499 default_addr_setted = hw->mac.default_addr_setted; 1500 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr)) 1501 return 0; 1502 1503 rte_spinlock_lock(&hw->lock); 1504 if (default_addr_setted) { 1505 ret = hns3_remove_uc_addr_common(hw, oaddr); 1506 if (ret) { 1507 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1508 oaddr); 1509 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1510 mac_str, ret); 1511 rm_succes = false; 1512 } else 1513 rm_succes = true; 1514 } 1515 1516 ret = hns3_add_uc_addr_common(hw, mac_addr); 1517 if (ret) { 1518 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1519 mac_addr); 1520 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1521 goto err_add_uc_addr; 1522 } 1523 1524 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1525 if (ret) { 1526 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1527 goto err_pause_addr_cfg; 1528 } 1529 1530 rte_ether_addr_copy(mac_addr, 1531 (struct rte_ether_addr *)hw->mac.mac_addr); 1532 hw->mac.default_addr_setted = true; 1533 rte_spinlock_unlock(&hw->lock); 1534 1535 return 0; 1536 1537 err_pause_addr_cfg: 1538 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1539 if (ret_val) { 1540 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1541 mac_addr); 1542 hns3_warn(hw, 1543 "Failed to roll back to del setted mac addr(%s): %d", 1544 mac_str, ret_val); 1545 } 1546 1547 err_add_uc_addr: 1548 if (rm_succes) { 1549 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1550 if (ret_val) { 1551 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1552 oaddr); 1553 hns3_warn(hw, 1554 "Failed to restore old uc mac addr(%s): %d", 1555 mac_str, ret_val); 1556 hw->mac.default_addr_setted = false; 1557 } 1558 } 1559 rte_spinlock_unlock(&hw->lock); 1560 1561 return ret; 1562 } 1563 1564 static int 1565 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1566 { 1567 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1568 struct hns3_hw *hw = &hns->hw; 1569 struct rte_ether_addr *addr; 1570 int err = 0; 1571 int ret; 1572 int i; 1573 1574 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1575 addr = &hw->data->mac_addrs[i]; 1576 if (!rte_is_valid_assigned_ether_addr(addr)) 1577 continue; 1578 if (del) 1579 ret = hns3_remove_uc_addr_common(hw, addr); 1580 else 1581 ret = hns3_add_uc_addr_common(hw, addr); 1582 if (ret) { 1583 err = ret; 1584 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1585 addr); 1586 hns3_dbg(hw, 1587 "Failed to %s mac addr(%s). ret:%d i:%d", 1588 del ? "remove" : "restore", mac_str, ret, i); 1589 } 1590 } 1591 return err; 1592 } 1593 1594 static void 1595 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1596 { 1597 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1598 uint8_t word_num; 1599 uint8_t bit_num; 1600 1601 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1602 word_num = vfid / 32; 1603 bit_num = vfid % 32; 1604 if (clr) 1605 desc[1].data[word_num] &= 1606 rte_cpu_to_le_32(~(1UL << bit_num)); 1607 else 1608 desc[1].data[word_num] |= 1609 rte_cpu_to_le_32(1UL << bit_num); 1610 } else { 1611 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1612 bit_num = vfid % 32; 1613 if (clr) 1614 desc[2].data[word_num] &= 1615 rte_cpu_to_le_32(~(1UL << bit_num)); 1616 else 1617 desc[2].data[word_num] |= 1618 rte_cpu_to_le_32(1UL << bit_num); 1619 } 1620 } 1621 1622 static int 1623 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1624 { 1625 struct hns3_mac_vlan_tbl_entry_cmd req; 1626 struct hns3_cmd_desc desc[3]; 1627 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1628 uint8_t vf_id; 1629 int ret; 1630 1631 /* Check if mac addr is valid */ 1632 if (!rte_is_multicast_ether_addr(mac_addr)) { 1633 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1634 mac_addr); 1635 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid", 1636 mac_str); 1637 return -EINVAL; 1638 } 1639 1640 memset(&req, 0, sizeof(req)); 1641 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1642 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1643 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1644 if (ret) { 1645 /* This mac addr do not exist, add new entry for it */ 1646 memset(desc[0].data, 0, sizeof(desc[0].data)); 1647 memset(desc[1].data, 0, sizeof(desc[0].data)); 1648 memset(desc[2].data, 0, sizeof(desc[0].data)); 1649 } 1650 1651 /* 1652 * In current version VF is not supported when PF is driven by DPDK 1653 * driver, the PF-related vf_id is 0, just need to configure parameters 1654 * for vf_id 0. 1655 */ 1656 vf_id = 0; 1657 hns3_update_desc_vfid(desc, vf_id, false); 1658 ret = hns3_add_mac_vlan_tbl(hw, &req, desc); 1659 if (ret) { 1660 if (ret == -ENOSPC) 1661 hns3_err(hw, "mc mac vlan table is full"); 1662 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1663 mac_addr); 1664 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret); 1665 } 1666 1667 return ret; 1668 } 1669 1670 static int 1671 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1672 { 1673 struct hns3_mac_vlan_tbl_entry_cmd req; 1674 struct hns3_cmd_desc desc[3]; 1675 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1676 uint8_t vf_id; 1677 int ret; 1678 1679 /* Check if mac addr is valid */ 1680 if (!rte_is_multicast_ether_addr(mac_addr)) { 1681 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1682 mac_addr); 1683 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1684 mac_str); 1685 return -EINVAL; 1686 } 1687 1688 memset(&req, 0, sizeof(req)); 1689 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1690 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1691 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1692 if (ret == 0) { 1693 /* 1694 * This mac addr exist, remove this handle's VFID for it. 1695 * In current version VF is not supported when PF is driven by 1696 * DPDK driver, the PF-related vf_id is 0, just need to 1697 * configure parameters for vf_id 0. 1698 */ 1699 vf_id = 0; 1700 hns3_update_desc_vfid(desc, vf_id, true); 1701 1702 /* All the vfid is zero, so need to delete this entry */ 1703 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1704 } else if (ret == -ENOENT) { 1705 /* This mac addr doesn't exist. */ 1706 return 0; 1707 } 1708 1709 if (ret) { 1710 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1711 mac_addr); 1712 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1713 } 1714 1715 return ret; 1716 } 1717 1718 static int 1719 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1720 struct rte_ether_addr *mc_addr_set, 1721 uint32_t nb_mc_addr) 1722 { 1723 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1724 struct rte_ether_addr *addr; 1725 uint32_t i; 1726 uint32_t j; 1727 1728 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1729 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) " 1730 "invalid. valid range: 0~%d", 1731 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1732 return -EINVAL; 1733 } 1734 1735 /* Check if input mac addresses are valid */ 1736 for (i = 0; i < nb_mc_addr; i++) { 1737 addr = &mc_addr_set[i]; 1738 if (!rte_is_multicast_ether_addr(addr)) { 1739 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1740 addr); 1741 hns3_err(hw, 1742 "Failed to set mc mac addr, addr(%s) invalid.", 1743 mac_str); 1744 return -EINVAL; 1745 } 1746 1747 /* Check if there are duplicate addresses */ 1748 for (j = i + 1; j < nb_mc_addr; j++) { 1749 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1750 rte_ether_format_addr(mac_str, 1751 RTE_ETHER_ADDR_FMT_SIZE, 1752 addr); 1753 hns3_err(hw, "Failed to set mc mac addr, " 1754 "addrs invalid. two same addrs(%s).", 1755 mac_str); 1756 return -EINVAL; 1757 } 1758 } 1759 } 1760 1761 return 0; 1762 } 1763 1764 static void 1765 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 1766 struct rte_ether_addr *mc_addr_set, 1767 int mc_addr_num, 1768 struct rte_ether_addr *reserved_addr_list, 1769 int *reserved_addr_num, 1770 struct rte_ether_addr *add_addr_list, 1771 int *add_addr_num, 1772 struct rte_ether_addr *rm_addr_list, 1773 int *rm_addr_num) 1774 { 1775 struct rte_ether_addr *addr; 1776 int current_addr_num; 1777 int reserved_num = 0; 1778 int add_num = 0; 1779 int rm_num = 0; 1780 int num; 1781 int i; 1782 int j; 1783 bool same_addr; 1784 1785 /* Calculate the mc mac address list that should be removed */ 1786 current_addr_num = hw->mc_addrs_num; 1787 for (i = 0; i < current_addr_num; i++) { 1788 addr = &hw->mc_addrs[i]; 1789 same_addr = false; 1790 for (j = 0; j < mc_addr_num; j++) { 1791 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1792 same_addr = true; 1793 break; 1794 } 1795 } 1796 1797 if (!same_addr) { 1798 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 1799 rm_num++; 1800 } else { 1801 rte_ether_addr_copy(addr, 1802 &reserved_addr_list[reserved_num]); 1803 reserved_num++; 1804 } 1805 } 1806 1807 /* Calculate the mc mac address list that should be added */ 1808 for (i = 0; i < mc_addr_num; i++) { 1809 addr = &mc_addr_set[i]; 1810 same_addr = false; 1811 for (j = 0; j < current_addr_num; j++) { 1812 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 1813 same_addr = true; 1814 break; 1815 } 1816 } 1817 1818 if (!same_addr) { 1819 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 1820 add_num++; 1821 } 1822 } 1823 1824 /* Reorder the mc mac address list maintained by driver */ 1825 for (i = 0; i < reserved_num; i++) 1826 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 1827 1828 for (i = 0; i < rm_num; i++) { 1829 num = reserved_num + i; 1830 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 1831 } 1832 1833 *reserved_addr_num = reserved_num; 1834 *add_addr_num = add_num; 1835 *rm_addr_num = rm_num; 1836 } 1837 1838 static int 1839 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 1840 struct rte_ether_addr *mc_addr_set, 1841 uint32_t nb_mc_addr) 1842 { 1843 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1844 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 1845 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 1846 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 1847 struct rte_ether_addr *addr; 1848 int reserved_addr_num; 1849 int add_addr_num; 1850 int rm_addr_num; 1851 int mc_addr_num; 1852 int num; 1853 int ret; 1854 int i; 1855 1856 /* Check if input parameters are valid */ 1857 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 1858 if (ret) 1859 return ret; 1860 1861 rte_spinlock_lock(&hw->lock); 1862 1863 /* 1864 * Calculate the mc mac address lists those should be removed and be 1865 * added, Reorder the mc mac address list maintained by driver. 1866 */ 1867 mc_addr_num = (int)nb_mc_addr; 1868 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 1869 reserved_addr_list, &reserved_addr_num, 1870 add_addr_list, &add_addr_num, 1871 rm_addr_list, &rm_addr_num); 1872 1873 /* Remove mc mac addresses */ 1874 for (i = 0; i < rm_addr_num; i++) { 1875 num = rm_addr_num - i - 1; 1876 addr = &rm_addr_list[num]; 1877 ret = hns3_remove_mc_addr(hw, addr); 1878 if (ret) { 1879 rte_spinlock_unlock(&hw->lock); 1880 return ret; 1881 } 1882 hw->mc_addrs_num--; 1883 } 1884 1885 /* Add mc mac addresses */ 1886 for (i = 0; i < add_addr_num; i++) { 1887 addr = &add_addr_list[i]; 1888 ret = hns3_add_mc_addr(hw, addr); 1889 if (ret) { 1890 rte_spinlock_unlock(&hw->lock); 1891 return ret; 1892 } 1893 1894 num = reserved_addr_num + i; 1895 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 1896 hw->mc_addrs_num++; 1897 } 1898 rte_spinlock_unlock(&hw->lock); 1899 1900 return 0; 1901 } 1902 1903 static int 1904 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 1905 { 1906 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1907 struct hns3_hw *hw = &hns->hw; 1908 struct rte_ether_addr *addr; 1909 int err = 0; 1910 int ret; 1911 int i; 1912 1913 for (i = 0; i < hw->mc_addrs_num; i++) { 1914 addr = &hw->mc_addrs[i]; 1915 if (!rte_is_multicast_ether_addr(addr)) 1916 continue; 1917 if (del) 1918 ret = hns3_remove_mc_addr(hw, addr); 1919 else 1920 ret = hns3_add_mc_addr(hw, addr); 1921 if (ret) { 1922 err = ret; 1923 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1924 addr); 1925 hns3_dbg(hw, "%s mc mac addr: %s failed", 1926 del ? "Remove" : "Restore", mac_str); 1927 } 1928 } 1929 return err; 1930 } 1931 1932 static int 1933 hns3_check_mq_mode(struct rte_eth_dev *dev) 1934 { 1935 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1936 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 1937 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1938 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1939 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 1940 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 1941 uint8_t num_tc; 1942 int max_tc = 0; 1943 int i; 1944 1945 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 1946 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 1947 1948 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 1949 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. " 1950 "rx_mq_mode = %d", rx_mq_mode); 1951 return -EINVAL; 1952 } 1953 1954 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB || 1955 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) { 1956 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB " 1957 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d", 1958 rx_mq_mode, tx_mq_mode); 1959 return -EINVAL; 1960 } 1961 1962 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) { 1963 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 1964 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 1965 dcb_rx_conf->nb_tcs, pf->tc_max); 1966 return -EINVAL; 1967 } 1968 1969 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 1970 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 1971 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 1972 "nb_tcs(%d) != %d or %d in rx direction.", 1973 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 1974 return -EINVAL; 1975 } 1976 1977 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 1978 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 1979 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 1980 return -EINVAL; 1981 } 1982 1983 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 1984 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 1985 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, " 1986 "is not equal to one in tx direction.", 1987 i, dcb_rx_conf->dcb_tc[i]); 1988 return -EINVAL; 1989 } 1990 if (dcb_rx_conf->dcb_tc[i] > max_tc) 1991 max_tc = dcb_rx_conf->dcb_tc[i]; 1992 } 1993 1994 num_tc = max_tc + 1; 1995 if (num_tc > dcb_rx_conf->nb_tcs) { 1996 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 1997 num_tc, dcb_rx_conf->nb_tcs); 1998 return -EINVAL; 1999 } 2000 } 2001 2002 return 0; 2003 } 2004 2005 static int 2006 hns3_check_dcb_cfg(struct rte_eth_dev *dev) 2007 { 2008 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2009 2010 if (!hns3_dev_dcb_supported(hw)) { 2011 hns3_err(hw, "this port does not support dcb configurations."); 2012 return -EOPNOTSUPP; 2013 } 2014 2015 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2016 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2017 return -EOPNOTSUPP; 2018 } 2019 2020 /* Check multiple queue mode */ 2021 return hns3_check_mq_mode(dev); 2022 } 2023 2024 static int 2025 hns3_dev_configure(struct rte_eth_dev *dev) 2026 { 2027 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2028 struct hns3_rss_conf *rss_cfg = &hw->rss_info; 2029 struct rte_eth_conf *conf = &dev->data->dev_conf; 2030 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2031 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2032 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2033 struct rte_eth_rss_conf rss_conf; 2034 uint16_t mtu; 2035 int ret; 2036 2037 /* 2038 * Hardware does not support where the number of rx and tx queues is 2039 * not equal in hip08. 2040 */ 2041 if (nb_rx_q != nb_tx_q) { 2042 hns3_err(hw, 2043 "nb_rx_queues(%u) not equal with nb_tx_queues(%u)! " 2044 "Hardware does not support this configuration!", 2045 nb_rx_q, nb_tx_q); 2046 return -EINVAL; 2047 } 2048 2049 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 2050 hns3_err(hw, "setting link speed/duplex not supported"); 2051 return -EINVAL; 2052 } 2053 2054 hw->adapter_state = HNS3_NIC_CONFIGURING; 2055 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2056 ret = hns3_check_dcb_cfg(dev); 2057 if (ret) 2058 goto cfg_err; 2059 } 2060 2061 /* When RSS is not configured, redirect the packet queue 0 */ 2062 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2063 rss_conf = conf->rx_adv_conf.rss_conf; 2064 if (rss_conf.rss_key == NULL) { 2065 rss_conf.rss_key = rss_cfg->key; 2066 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE; 2067 } 2068 2069 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2070 if (ret) 2071 goto cfg_err; 2072 } 2073 2074 /* 2075 * If jumbo frames are enabled, MTU needs to be refreshed 2076 * according to the maximum RX packet length. 2077 */ 2078 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 2079 /* 2080 * Security of max_rx_pkt_len is guaranteed in dpdk frame. 2081 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it 2082 * can safely assign to "uint16_t" type variable. 2083 */ 2084 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len); 2085 ret = hns3_dev_mtu_set(dev, mtu); 2086 if (ret) 2087 goto cfg_err; 2088 dev->data->mtu = mtu; 2089 } 2090 2091 ret = hns3_dev_configure_vlan(dev); 2092 if (ret) 2093 goto cfg_err; 2094 2095 hw->adapter_state = HNS3_NIC_CONFIGURED; 2096 2097 return 0; 2098 2099 cfg_err: 2100 hw->adapter_state = HNS3_NIC_INITIALIZED; 2101 return ret; 2102 } 2103 2104 static int 2105 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2106 { 2107 struct hns3_config_max_frm_size_cmd *req; 2108 struct hns3_cmd_desc desc; 2109 2110 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2111 2112 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2113 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2114 req->min_frm_size = HNS3_MIN_FRAME_LEN; 2115 2116 return hns3_cmd_send(hw, &desc, 1); 2117 } 2118 2119 static int 2120 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2121 { 2122 int ret; 2123 2124 ret = hns3_set_mac_mtu(hw, mps); 2125 if (ret) { 2126 hns3_err(hw, "Failed to set mtu, ret = %d", ret); 2127 return ret; 2128 } 2129 2130 ret = hns3_buffer_alloc(hw); 2131 if (ret) { 2132 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret); 2133 return ret; 2134 } 2135 2136 return 0; 2137 } 2138 2139 static int 2140 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2141 { 2142 struct hns3_adapter *hns = dev->data->dev_private; 2143 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2144 struct hns3_hw *hw = &hns->hw; 2145 bool is_jumbo_frame; 2146 int ret; 2147 2148 if (dev->data->dev_started) { 2149 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2150 "before configuration", dev->data->port_id); 2151 return -EBUSY; 2152 } 2153 2154 rte_spinlock_lock(&hw->lock); 2155 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false; 2156 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2157 2158 /* 2159 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2160 * assign to "uint16_t" type variable. 2161 */ 2162 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2163 if (ret) { 2164 rte_spinlock_unlock(&hw->lock); 2165 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2166 dev->data->port_id, mtu, ret); 2167 return ret; 2168 } 2169 hns->pf.mps = (uint16_t)frame_size; 2170 if (is_jumbo_frame) 2171 dev->data->dev_conf.rxmode.offloads |= 2172 DEV_RX_OFFLOAD_JUMBO_FRAME; 2173 else 2174 dev->data->dev_conf.rxmode.offloads &= 2175 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2176 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2177 rte_spinlock_unlock(&hw->lock); 2178 2179 return 0; 2180 } 2181 2182 static int 2183 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2184 { 2185 struct hns3_adapter *hns = eth_dev->data->dev_private; 2186 struct hns3_hw *hw = &hns->hw; 2187 2188 info->max_rx_queues = hw->tqps_num; 2189 info->max_tx_queues = hw->tqps_num; 2190 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2191 info->min_rx_bufsize = hw->rx_buf_len; 2192 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2193 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2194 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2195 DEV_RX_OFFLOAD_TCP_CKSUM | 2196 DEV_RX_OFFLOAD_UDP_CKSUM | 2197 DEV_RX_OFFLOAD_SCTP_CKSUM | 2198 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2199 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2200 DEV_RX_OFFLOAD_KEEP_CRC | 2201 DEV_RX_OFFLOAD_SCATTER | 2202 DEV_RX_OFFLOAD_VLAN_STRIP | 2203 DEV_RX_OFFLOAD_QINQ_STRIP | 2204 DEV_RX_OFFLOAD_VLAN_FILTER | 2205 DEV_RX_OFFLOAD_VLAN_EXTEND | 2206 DEV_RX_OFFLOAD_JUMBO_FRAME); 2207 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 2208 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2209 DEV_TX_OFFLOAD_IPV4_CKSUM | 2210 DEV_TX_OFFLOAD_TCP_CKSUM | 2211 DEV_TX_OFFLOAD_UDP_CKSUM | 2212 DEV_TX_OFFLOAD_SCTP_CKSUM | 2213 DEV_TX_OFFLOAD_VLAN_INSERT | 2214 DEV_TX_OFFLOAD_QINQ_INSERT | 2215 DEV_TX_OFFLOAD_MULTI_SEGS | 2216 info->tx_queue_offload_capa); 2217 2218 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2219 .nb_max = HNS3_MAX_RING_DESC, 2220 .nb_min = HNS3_MIN_RING_DESC, 2221 .nb_align = HNS3_ALIGN_RING_DESC, 2222 }; 2223 2224 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2225 .nb_max = HNS3_MAX_RING_DESC, 2226 .nb_min = HNS3_MIN_RING_DESC, 2227 .nb_align = HNS3_ALIGN_RING_DESC, 2228 }; 2229 2230 info->vmdq_queue_num = 0; 2231 2232 info->reta_size = HNS3_RSS_IND_TBL_SIZE; 2233 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2234 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2235 2236 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2237 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2238 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2239 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2240 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2241 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2242 2243 return 0; 2244 } 2245 2246 static int 2247 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2248 size_t fw_size) 2249 { 2250 struct hns3_adapter *hns = eth_dev->data->dev_private; 2251 struct hns3_hw *hw = &hns->hw; 2252 int ret; 2253 2254 ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version); 2255 ret += 1; /* add the size of '\0' */ 2256 if (fw_size < (uint32_t)ret) 2257 return ret; 2258 else 2259 return 0; 2260 } 2261 2262 static int 2263 hns3_dev_link_update(struct rte_eth_dev *eth_dev, 2264 __rte_unused int wait_to_complete) 2265 { 2266 struct hns3_adapter *hns = eth_dev->data->dev_private; 2267 struct hns3_hw *hw = &hns->hw; 2268 struct hns3_mac *mac = &hw->mac; 2269 struct rte_eth_link new_link; 2270 2271 memset(&new_link, 0, sizeof(new_link)); 2272 switch (mac->link_speed) { 2273 case ETH_SPEED_NUM_10M: 2274 case ETH_SPEED_NUM_100M: 2275 case ETH_SPEED_NUM_1G: 2276 case ETH_SPEED_NUM_10G: 2277 case ETH_SPEED_NUM_25G: 2278 case ETH_SPEED_NUM_40G: 2279 case ETH_SPEED_NUM_50G: 2280 case ETH_SPEED_NUM_100G: 2281 new_link.link_speed = mac->link_speed; 2282 break; 2283 default: 2284 new_link.link_speed = ETH_SPEED_NUM_100M; 2285 break; 2286 } 2287 2288 new_link.link_duplex = mac->link_duplex; 2289 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2290 new_link.link_autoneg = 2291 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2292 2293 return rte_eth_linkstatus_set(eth_dev, &new_link); 2294 } 2295 2296 static int 2297 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2298 { 2299 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2300 struct hns3_pf *pf = &hns->pf; 2301 2302 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2303 return -EINVAL; 2304 2305 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2306 2307 return 0; 2308 } 2309 2310 static int 2311 hns3_query_function_status(struct hns3_hw *hw) 2312 { 2313 #define HNS3_QUERY_MAX_CNT 10 2314 #define HNS3_QUERY_SLEEP_MSCOEND 1 2315 struct hns3_func_status_cmd *req; 2316 struct hns3_cmd_desc desc; 2317 int timeout = 0; 2318 int ret; 2319 2320 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2321 req = (struct hns3_func_status_cmd *)desc.data; 2322 2323 do { 2324 ret = hns3_cmd_send(hw, &desc, 1); 2325 if (ret) { 2326 PMD_INIT_LOG(ERR, "query function status failed %d", 2327 ret); 2328 return ret; 2329 } 2330 2331 /* Check pf reset is done */ 2332 if (req->pf_state) 2333 break; 2334 2335 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2336 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2337 2338 return hns3_parse_func_status(hw, req); 2339 } 2340 2341 static int 2342 hns3_query_pf_resource(struct hns3_hw *hw) 2343 { 2344 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2345 struct hns3_pf *pf = &hns->pf; 2346 struct hns3_pf_res_cmd *req; 2347 struct hns3_cmd_desc desc; 2348 int ret; 2349 2350 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 2351 ret = hns3_cmd_send(hw, &desc, 1); 2352 if (ret) { 2353 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 2354 return ret; 2355 } 2356 2357 req = (struct hns3_pf_res_cmd *)desc.data; 2358 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num); 2359 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 2360 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 2361 2362 if (req->tx_buf_size) 2363 pf->tx_buf_size = 2364 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 2365 else 2366 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 2367 2368 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 2369 2370 if (req->dv_buf_size) 2371 pf->dv_buf_size = 2372 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 2373 else 2374 pf->dv_buf_size = HNS3_DEFAULT_DV; 2375 2376 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 2377 2378 hw->num_msi = 2379 hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number), 2380 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 2381 2382 return 0; 2383 } 2384 2385 static void 2386 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 2387 { 2388 struct hns3_cfg_param_cmd *req; 2389 uint64_t mac_addr_tmp_high; 2390 uint64_t mac_addr_tmp; 2391 uint32_t i; 2392 2393 req = (struct hns3_cfg_param_cmd *)desc[0].data; 2394 2395 /* get the configuration */ 2396 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2397 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S); 2398 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2399 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 2400 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2401 HNS3_CFG_TQP_DESC_N_M, 2402 HNS3_CFG_TQP_DESC_N_S); 2403 2404 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2405 HNS3_CFG_PHY_ADDR_M, 2406 HNS3_CFG_PHY_ADDR_S); 2407 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2408 HNS3_CFG_MEDIA_TP_M, 2409 HNS3_CFG_MEDIA_TP_S); 2410 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2411 HNS3_CFG_RX_BUF_LEN_M, 2412 HNS3_CFG_RX_BUF_LEN_S); 2413 /* get mac address */ 2414 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 2415 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2416 HNS3_CFG_MAC_ADDR_H_M, 2417 HNS3_CFG_MAC_ADDR_H_S); 2418 2419 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 2420 2421 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2422 HNS3_CFG_DEFAULT_SPEED_M, 2423 HNS3_CFG_DEFAULT_SPEED_S); 2424 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2425 HNS3_CFG_RSS_SIZE_M, 2426 HNS3_CFG_RSS_SIZE_S); 2427 2428 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2429 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 2430 2431 req = (struct hns3_cfg_param_cmd *)desc[1].data; 2432 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 2433 2434 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2435 HNS3_CFG_SPEED_ABILITY_M, 2436 HNS3_CFG_SPEED_ABILITY_S); 2437 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2438 HNS3_CFG_UMV_TBL_SPACE_M, 2439 HNS3_CFG_UMV_TBL_SPACE_S); 2440 if (!cfg->umv_space) 2441 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 2442 } 2443 2444 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 2445 * @hw: pointer to struct hns3_hw 2446 * @hcfg: the config structure to be getted 2447 */ 2448 static int 2449 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 2450 { 2451 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 2452 struct hns3_cfg_param_cmd *req; 2453 uint32_t offset; 2454 uint32_t i; 2455 int ret; 2456 2457 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 2458 offset = 0; 2459 req = (struct hns3_cfg_param_cmd *)desc[i].data; 2460 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 2461 true); 2462 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 2463 i * HNS3_CFG_RD_LEN_BYTES); 2464 /* Len should be divided by 4 when send to hardware */ 2465 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 2466 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 2467 req->offset = rte_cpu_to_le_32(offset); 2468 } 2469 2470 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 2471 if (ret) { 2472 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 2473 return ret; 2474 } 2475 2476 hns3_parse_cfg(hcfg, desc); 2477 2478 return 0; 2479 } 2480 2481 static int 2482 hns3_parse_speed(int speed_cmd, uint32_t *speed) 2483 { 2484 switch (speed_cmd) { 2485 case HNS3_CFG_SPEED_10M: 2486 *speed = ETH_SPEED_NUM_10M; 2487 break; 2488 case HNS3_CFG_SPEED_100M: 2489 *speed = ETH_SPEED_NUM_100M; 2490 break; 2491 case HNS3_CFG_SPEED_1G: 2492 *speed = ETH_SPEED_NUM_1G; 2493 break; 2494 case HNS3_CFG_SPEED_10G: 2495 *speed = ETH_SPEED_NUM_10G; 2496 break; 2497 case HNS3_CFG_SPEED_25G: 2498 *speed = ETH_SPEED_NUM_25G; 2499 break; 2500 case HNS3_CFG_SPEED_40G: 2501 *speed = ETH_SPEED_NUM_40G; 2502 break; 2503 case HNS3_CFG_SPEED_50G: 2504 *speed = ETH_SPEED_NUM_50G; 2505 break; 2506 case HNS3_CFG_SPEED_100G: 2507 *speed = ETH_SPEED_NUM_100G; 2508 break; 2509 default: 2510 return -EINVAL; 2511 } 2512 2513 return 0; 2514 } 2515 2516 static int 2517 hns3_get_board_configuration(struct hns3_hw *hw) 2518 { 2519 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2520 struct hns3_pf *pf = &hns->pf; 2521 struct hns3_cfg cfg; 2522 int ret; 2523 2524 ret = hns3_get_board_cfg(hw, &cfg); 2525 if (ret) { 2526 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 2527 return ret; 2528 } 2529 2530 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) { 2531 PMD_INIT_LOG(ERR, "media type is copper, not supported."); 2532 return -EOPNOTSUPP; 2533 } 2534 2535 hw->mac.media_type = cfg.media_type; 2536 hw->rss_size_max = cfg.rss_size_max; 2537 hw->rx_buf_len = cfg.rx_buf_len; 2538 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 2539 hw->mac.phy_addr = cfg.phy_addr; 2540 hw->mac.default_addr_setted = false; 2541 hw->num_tx_desc = cfg.tqp_desc_num; 2542 hw->num_rx_desc = cfg.tqp_desc_num; 2543 hw->dcb_info.num_pg = 1; 2544 hw->dcb_info.hw_pfc_map = 0; 2545 2546 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 2547 if (ret) { 2548 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d", 2549 cfg.default_speed, ret); 2550 return ret; 2551 } 2552 2553 pf->tc_max = cfg.tc_num; 2554 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 2555 PMD_INIT_LOG(WARNING, 2556 "Get TC num(%u) from flash, set TC num to 1", 2557 pf->tc_max); 2558 pf->tc_max = 1; 2559 } 2560 2561 /* Dev does not support DCB */ 2562 if (!hns3_dev_dcb_supported(hw)) { 2563 pf->tc_max = 1; 2564 pf->pfc_max = 0; 2565 } else 2566 pf->pfc_max = pf->tc_max; 2567 2568 hw->dcb_info.num_tc = 1; 2569 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 2570 hw->tqps_num / hw->dcb_info.num_tc); 2571 hns3_set_bit(hw->hw_tc_map, 0, 1); 2572 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 2573 2574 pf->wanted_umv_size = cfg.umv_space; 2575 2576 return ret; 2577 } 2578 2579 static int 2580 hns3_get_configuration(struct hns3_hw *hw) 2581 { 2582 int ret; 2583 2584 ret = hns3_query_function_status(hw); 2585 if (ret) { 2586 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 2587 return ret; 2588 } 2589 2590 /* Get pf resource */ 2591 ret = hns3_query_pf_resource(hw); 2592 if (ret) { 2593 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 2594 return ret; 2595 } 2596 2597 ret = hns3_get_board_configuration(hw); 2598 if (ret) { 2599 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret); 2600 return ret; 2601 } 2602 2603 return 0; 2604 } 2605 2606 static int 2607 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 2608 uint16_t tqp_vid, bool is_pf) 2609 { 2610 struct hns3_tqp_map_cmd *req; 2611 struct hns3_cmd_desc desc; 2612 int ret; 2613 2614 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 2615 2616 req = (struct hns3_tqp_map_cmd *)desc.data; 2617 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 2618 req->tqp_vf = func_id; 2619 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 2620 if (!is_pf) 2621 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 2622 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 2623 2624 ret = hns3_cmd_send(hw, &desc, 1); 2625 if (ret) 2626 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 2627 2628 return ret; 2629 } 2630 2631 static int 2632 hns3_map_tqp(struct hns3_hw *hw) 2633 { 2634 uint16_t tqps_num = hw->total_tqps_num; 2635 uint16_t func_id; 2636 uint16_t tqp_id; 2637 int num; 2638 int ret; 2639 int i; 2640 2641 /* 2642 * In current version VF is not supported when PF is driven by DPDK 2643 * driver, so we allocate tqps to PF as much as possible. 2644 */ 2645 tqp_id = 0; 2646 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 2647 for (func_id = 0; func_id < num; func_id++) { 2648 for (i = 0; 2649 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) { 2650 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i, 2651 true); 2652 if (ret) 2653 return ret; 2654 } 2655 } 2656 2657 return 0; 2658 } 2659 2660 static int 2661 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 2662 { 2663 struct hns3_config_mac_speed_dup_cmd *req; 2664 struct hns3_cmd_desc desc; 2665 int ret; 2666 2667 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 2668 2669 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 2670 2671 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 2672 2673 switch (speed) { 2674 case ETH_SPEED_NUM_10M: 2675 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2676 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 2677 break; 2678 case ETH_SPEED_NUM_100M: 2679 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2680 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 2681 break; 2682 case ETH_SPEED_NUM_1G: 2683 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2684 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 2685 break; 2686 case ETH_SPEED_NUM_10G: 2687 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2688 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 2689 break; 2690 case ETH_SPEED_NUM_25G: 2691 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2692 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 2693 break; 2694 case ETH_SPEED_NUM_40G: 2695 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2696 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 2697 break; 2698 case ETH_SPEED_NUM_50G: 2699 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2700 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 2701 break; 2702 case ETH_SPEED_NUM_100G: 2703 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2704 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 2705 break; 2706 default: 2707 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 2708 return -EINVAL; 2709 } 2710 2711 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 2712 2713 ret = hns3_cmd_send(hw, &desc, 1); 2714 if (ret) 2715 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 2716 2717 return ret; 2718 } 2719 2720 static int 2721 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 2722 { 2723 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2724 struct hns3_pf *pf = &hns->pf; 2725 struct hns3_priv_buf *priv; 2726 uint32_t i, total_size; 2727 2728 total_size = pf->pkt_buf_size; 2729 2730 /* alloc tx buffer for all enabled tc */ 2731 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 2732 priv = &buf_alloc->priv_buf[i]; 2733 2734 if (hw->hw_tc_map & BIT(i)) { 2735 if (total_size < pf->tx_buf_size) 2736 return -ENOMEM; 2737 2738 priv->tx_buf_size = pf->tx_buf_size; 2739 } else 2740 priv->tx_buf_size = 0; 2741 2742 total_size -= priv->tx_buf_size; 2743 } 2744 2745 return 0; 2746 } 2747 2748 static int 2749 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 2750 { 2751 /* TX buffer size is unit by 128 byte */ 2752 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 2753 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 2754 struct hns3_tx_buff_alloc_cmd *req; 2755 struct hns3_cmd_desc desc; 2756 uint32_t buf_size; 2757 uint32_t i; 2758 int ret; 2759 2760 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 2761 2762 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 2763 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 2764 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 2765 2766 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 2767 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 2768 HNS3_BUF_SIZE_UPDATE_EN_MSK); 2769 } 2770 2771 ret = hns3_cmd_send(hw, &desc, 1); 2772 if (ret) 2773 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 2774 2775 return ret; 2776 } 2777 2778 static int 2779 hns3_get_tc_num(struct hns3_hw *hw) 2780 { 2781 int cnt = 0; 2782 uint8_t i; 2783 2784 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 2785 if (hw->hw_tc_map & BIT(i)) 2786 cnt++; 2787 return cnt; 2788 } 2789 2790 static uint32_t 2791 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 2792 { 2793 struct hns3_priv_buf *priv; 2794 uint32_t rx_priv = 0; 2795 int i; 2796 2797 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 2798 priv = &buf_alloc->priv_buf[i]; 2799 if (priv->enable) 2800 rx_priv += priv->buf_size; 2801 } 2802 return rx_priv; 2803 } 2804 2805 static uint32_t 2806 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 2807 { 2808 uint32_t total_tx_size = 0; 2809 uint32_t i; 2810 2811 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 2812 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 2813 2814 return total_tx_size; 2815 } 2816 2817 /* Get the number of pfc enabled TCs, which have private buffer */ 2818 static int 2819 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 2820 { 2821 struct hns3_priv_buf *priv; 2822 int cnt = 0; 2823 uint8_t i; 2824 2825 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 2826 priv = &buf_alloc->priv_buf[i]; 2827 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 2828 cnt++; 2829 } 2830 2831 return cnt; 2832 } 2833 2834 /* Get the number of pfc disabled TCs, which have private buffer */ 2835 static int 2836 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 2837 struct hns3_pkt_buf_alloc *buf_alloc) 2838 { 2839 struct hns3_priv_buf *priv; 2840 int cnt = 0; 2841 uint8_t i; 2842 2843 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 2844 priv = &buf_alloc->priv_buf[i]; 2845 if (hw->hw_tc_map & BIT(i) && 2846 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 2847 cnt++; 2848 } 2849 2850 return cnt; 2851 } 2852 2853 static bool 2854 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 2855 uint32_t rx_all) 2856 { 2857 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2858 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2859 struct hns3_pf *pf = &hns->pf; 2860 uint32_t shared_buf, aligned_mps; 2861 uint32_t rx_priv; 2862 uint8_t tc_num; 2863 uint8_t i; 2864 2865 tc_num = hns3_get_tc_num(hw); 2866 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 2867 2868 if (hns3_dev_dcb_supported(hw)) 2869 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 2870 pf->dv_buf_size; 2871 else 2872 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 2873 + pf->dv_buf_size; 2874 2875 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2876 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc), 2877 HNS3_BUF_SIZE_UNIT); 2878 2879 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 2880 if (rx_all < rx_priv + shared_std) 2881 return false; 2882 2883 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 2884 buf_alloc->s_buf.buf_size = shared_buf; 2885 if (hns3_dev_dcb_supported(hw)) { 2886 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 2887 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2888 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 2889 HNS3_BUF_SIZE_UNIT); 2890 } else { 2891 buf_alloc->s_buf.self.high = 2892 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 2893 buf_alloc->s_buf.self.low = aligned_mps; 2894 } 2895 2896 if (hns3_dev_dcb_supported(hw)) { 2897 hi_thrd = shared_buf - pf->dv_buf_size; 2898 2899 if (tc_num <= NEED_RESERVE_TC_NUM) 2900 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2901 / BUF_MAX_PERCENT; 2902 2903 if (tc_num) 2904 hi_thrd = hi_thrd / tc_num; 2905 2906 hi_thrd = max_t(uint32_t, hi_thrd, 2907 HNS3_BUF_MUL_BY * aligned_mps); 2908 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 2909 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 2910 } else { 2911 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 2912 lo_thrd = aligned_mps; 2913 } 2914 2915 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 2916 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2917 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2918 } 2919 2920 return true; 2921 } 2922 2923 static bool 2924 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 2925 struct hns3_pkt_buf_alloc *buf_alloc) 2926 { 2927 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2928 struct hns3_pf *pf = &hns->pf; 2929 struct hns3_priv_buf *priv; 2930 uint32_t aligned_mps; 2931 uint32_t rx_all; 2932 uint8_t i; 2933 2934 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 2935 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 2936 2937 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 2938 priv = &buf_alloc->priv_buf[i]; 2939 2940 priv->enable = 0; 2941 priv->wl.low = 0; 2942 priv->wl.high = 0; 2943 priv->buf_size = 0; 2944 2945 if (!(hw->hw_tc_map & BIT(i))) 2946 continue; 2947 2948 priv->enable = 1; 2949 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 2950 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 2951 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2952 HNS3_BUF_SIZE_UNIT); 2953 } else { 2954 priv->wl.low = 0; 2955 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 2956 aligned_mps; 2957 } 2958 2959 priv->buf_size = priv->wl.high + pf->dv_buf_size; 2960 } 2961 2962 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 2963 } 2964 2965 static bool 2966 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 2967 struct hns3_pkt_buf_alloc *buf_alloc) 2968 { 2969 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2970 struct hns3_pf *pf = &hns->pf; 2971 struct hns3_priv_buf *priv; 2972 int no_pfc_priv_num; 2973 uint32_t rx_all; 2974 uint8_t mask; 2975 int i; 2976 2977 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 2978 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 2979 2980 /* let the last to be cleared first */ 2981 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 2982 priv = &buf_alloc->priv_buf[i]; 2983 mask = BIT((uint8_t)i); 2984 2985 if (hw->hw_tc_map & mask && 2986 !(hw->dcb_info.hw_pfc_map & mask)) { 2987 /* Clear the no pfc TC private buffer */ 2988 priv->wl.low = 0; 2989 priv->wl.high = 0; 2990 priv->buf_size = 0; 2991 priv->enable = 0; 2992 no_pfc_priv_num--; 2993 } 2994 2995 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 2996 no_pfc_priv_num == 0) 2997 break; 2998 } 2999 3000 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3001 } 3002 3003 static bool 3004 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3005 struct hns3_pkt_buf_alloc *buf_alloc) 3006 { 3007 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3008 struct hns3_pf *pf = &hns->pf; 3009 struct hns3_priv_buf *priv; 3010 uint32_t rx_all; 3011 int pfc_priv_num; 3012 uint8_t mask; 3013 int i; 3014 3015 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3016 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3017 3018 /* let the last to be cleared first */ 3019 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3020 priv = &buf_alloc->priv_buf[i]; 3021 mask = BIT((uint8_t)i); 3022 3023 if (hw->hw_tc_map & mask && 3024 hw->dcb_info.hw_pfc_map & mask) { 3025 /* Reduce the number of pfc TC with private buffer */ 3026 priv->wl.low = 0; 3027 priv->enable = 0; 3028 priv->wl.high = 0; 3029 priv->buf_size = 0; 3030 pfc_priv_num--; 3031 } 3032 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3033 pfc_priv_num == 0) 3034 break; 3035 } 3036 3037 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3038 } 3039 3040 static bool 3041 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3042 struct hns3_pkt_buf_alloc *buf_alloc) 3043 { 3044 #define COMPENSATE_BUFFER 0x3C00 3045 #define COMPENSATE_HALF_MPS_NUM 5 3046 #define PRIV_WL_GAP 0x1800 3047 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3048 struct hns3_pf *pf = &hns->pf; 3049 uint32_t tc_num = hns3_get_tc_num(hw); 3050 uint32_t half_mps = pf->mps >> 1; 3051 struct hns3_priv_buf *priv; 3052 uint32_t min_rx_priv; 3053 uint32_t rx_priv; 3054 uint8_t i; 3055 3056 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3057 if (tc_num) 3058 rx_priv = rx_priv / tc_num; 3059 3060 if (tc_num <= NEED_RESERVE_TC_NUM) 3061 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3062 3063 /* 3064 * Minimum value of private buffer in rx direction (min_rx_priv) is 3065 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3066 * buffer if rx_priv is greater than min_rx_priv. 3067 */ 3068 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3069 COMPENSATE_HALF_MPS_NUM * half_mps; 3070 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3071 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3072 3073 if (rx_priv < min_rx_priv) 3074 return false; 3075 3076 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3077 priv = &buf_alloc->priv_buf[i]; 3078 3079 priv->enable = 0; 3080 priv->wl.low = 0; 3081 priv->wl.high = 0; 3082 priv->buf_size = 0; 3083 3084 if (!(hw->hw_tc_map & BIT(i))) 3085 continue; 3086 3087 priv->enable = 1; 3088 priv->buf_size = rx_priv; 3089 priv->wl.high = rx_priv - pf->dv_buf_size; 3090 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3091 } 3092 3093 buf_alloc->s_buf.buf_size = 0; 3094 3095 return true; 3096 } 3097 3098 /* 3099 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3100 * @hw: pointer to struct hns3_hw 3101 * @buf_alloc: pointer to buffer calculation data 3102 * @return: 0: calculate sucessful, negative: fail 3103 */ 3104 static int 3105 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3106 { 3107 /* When DCB is not supported, rx private buffer is not allocated. */ 3108 if (!hns3_dev_dcb_supported(hw)) { 3109 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3110 struct hns3_pf *pf = &hns->pf; 3111 uint32_t rx_all = pf->pkt_buf_size; 3112 3113 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3114 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3115 return -ENOMEM; 3116 3117 return 0; 3118 } 3119 3120 /* 3121 * Try to allocate privated packet buffer for all TCs without share 3122 * buffer. 3123 */ 3124 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3125 return 0; 3126 3127 /* 3128 * Try to allocate privated packet buffer for all TCs with share 3129 * buffer. 3130 */ 3131 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3132 return 0; 3133 3134 /* 3135 * For different application scenes, the enabled port number, TC number 3136 * and no_drop TC number are different. In order to obtain the better 3137 * performance, software could allocate the buffer size and configure 3138 * the waterline by tring to decrease the private buffer size according 3139 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc 3140 * enabled tc. 3141 */ 3142 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 3143 return 0; 3144 3145 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 3146 return 0; 3147 3148 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 3149 return 0; 3150 3151 return -ENOMEM; 3152 } 3153 3154 static int 3155 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3156 { 3157 struct hns3_rx_priv_buff_cmd *req; 3158 struct hns3_cmd_desc desc; 3159 uint32_t buf_size; 3160 int ret; 3161 int i; 3162 3163 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 3164 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 3165 3166 /* Alloc private buffer TCs */ 3167 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3168 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 3169 3170 req->buf_num[i] = 3171 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 3172 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 3173 } 3174 3175 buf_size = buf_alloc->s_buf.buf_size; 3176 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 3177 (1 << HNS3_TC0_PRI_BUF_EN_B)); 3178 3179 ret = hns3_cmd_send(hw, &desc, 1); 3180 if (ret) 3181 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 3182 3183 return ret; 3184 } 3185 3186 static int 3187 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3188 { 3189 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 3190 struct hns3_rx_priv_wl_buf *req; 3191 struct hns3_priv_buf *priv; 3192 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 3193 int i, j; 3194 int ret; 3195 3196 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 3197 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 3198 false); 3199 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 3200 3201 /* The first descriptor set the NEXT bit to 1 */ 3202 if (i == 0) 3203 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3204 else 3205 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3206 3207 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3208 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 3209 3210 priv = &buf_alloc->priv_buf[idx]; 3211 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 3212 HNS3_BUF_UNIT_S); 3213 req->tc_wl[j].high |= 3214 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3215 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 3216 HNS3_BUF_UNIT_S); 3217 req->tc_wl[j].low |= 3218 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3219 } 3220 } 3221 3222 /* Send 2 descriptor at one time */ 3223 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 3224 if (ret) 3225 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 3226 ret); 3227 return ret; 3228 } 3229 3230 static int 3231 hns3_common_thrd_config(struct hns3_hw *hw, 3232 struct hns3_pkt_buf_alloc *buf_alloc) 3233 { 3234 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 3235 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 3236 struct hns3_rx_com_thrd *req; 3237 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 3238 struct hns3_tc_thrd *tc; 3239 int tc_idx; 3240 int i, j; 3241 int ret; 3242 3243 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 3244 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 3245 false); 3246 req = (struct hns3_rx_com_thrd *)&desc[i].data; 3247 3248 /* The first descriptor set the NEXT bit to 1 */ 3249 if (i == 0) 3250 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3251 else 3252 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3253 3254 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3255 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 3256 tc = &s_buf->tc_thrd[tc_idx]; 3257 3258 req->com_thrd[j].high = 3259 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 3260 req->com_thrd[j].high |= 3261 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3262 req->com_thrd[j].low = 3263 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 3264 req->com_thrd[j].low |= 3265 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3266 } 3267 } 3268 3269 /* Send 2 descriptors at one time */ 3270 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 3271 if (ret) 3272 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 3273 3274 return ret; 3275 } 3276 3277 static int 3278 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3279 { 3280 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 3281 struct hns3_rx_com_wl *req; 3282 struct hns3_cmd_desc desc; 3283 int ret; 3284 3285 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 3286 3287 req = (struct hns3_rx_com_wl *)desc.data; 3288 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 3289 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3290 3291 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 3292 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3293 3294 ret = hns3_cmd_send(hw, &desc, 1); 3295 if (ret) 3296 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 3297 3298 return ret; 3299 } 3300 3301 int 3302 hns3_buffer_alloc(struct hns3_hw *hw) 3303 { 3304 struct hns3_pkt_buf_alloc pkt_buf; 3305 int ret; 3306 3307 memset(&pkt_buf, 0, sizeof(pkt_buf)); 3308 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 3309 if (ret) { 3310 PMD_INIT_LOG(ERR, 3311 "could not calc tx buffer size for all TCs %d", 3312 ret); 3313 return ret; 3314 } 3315 3316 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 3317 if (ret) { 3318 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 3319 return ret; 3320 } 3321 3322 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 3323 if (ret) { 3324 PMD_INIT_LOG(ERR, 3325 "could not calc rx priv buffer size for all TCs %d", 3326 ret); 3327 return ret; 3328 } 3329 3330 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 3331 if (ret) { 3332 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 3333 return ret; 3334 } 3335 3336 if (hns3_dev_dcb_supported(hw)) { 3337 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 3338 if (ret) { 3339 PMD_INIT_LOG(ERR, 3340 "could not configure rx private waterline %d", 3341 ret); 3342 return ret; 3343 } 3344 3345 ret = hns3_common_thrd_config(hw, &pkt_buf); 3346 if (ret) { 3347 PMD_INIT_LOG(ERR, 3348 "could not configure common threshold %d", 3349 ret); 3350 return ret; 3351 } 3352 } 3353 3354 ret = hns3_common_wl_config(hw, &pkt_buf); 3355 if (ret) 3356 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 3357 ret); 3358 3359 return ret; 3360 } 3361 3362 static int 3363 hns3_mac_init(struct hns3_hw *hw) 3364 { 3365 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3366 struct hns3_mac *mac = &hw->mac; 3367 struct hns3_pf *pf = &hns->pf; 3368 int ret; 3369 3370 pf->support_sfp_query = true; 3371 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 3372 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 3373 if (ret) { 3374 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 3375 return ret; 3376 } 3377 3378 mac->link_status = ETH_LINK_DOWN; 3379 3380 return hns3_config_mtu(hw, pf->mps); 3381 } 3382 3383 static int 3384 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 3385 { 3386 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 3387 #define HNS3_ETHERTYPE_ALREADY_ADD 1 3388 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 3389 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 3390 int return_status; 3391 3392 if (cmdq_resp) { 3393 PMD_INIT_LOG(ERR, 3394 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 3395 cmdq_resp); 3396 return -EIO; 3397 } 3398 3399 switch (resp_code) { 3400 case HNS3_ETHERTYPE_SUCCESS_ADD: 3401 case HNS3_ETHERTYPE_ALREADY_ADD: 3402 return_status = 0; 3403 break; 3404 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 3405 PMD_INIT_LOG(ERR, 3406 "add mac ethertype failed for manager table overflow."); 3407 return_status = -EIO; 3408 break; 3409 case HNS3_ETHERTYPE_KEY_CONFLICT: 3410 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 3411 return_status = -EIO; 3412 break; 3413 default: 3414 PMD_INIT_LOG(ERR, 3415 "add mac ethertype failed for undefined, code=%d.", 3416 resp_code); 3417 return_status = -EIO; 3418 } 3419 3420 return return_status; 3421 } 3422 3423 static int 3424 hns3_add_mgr_tbl(struct hns3_hw *hw, 3425 const struct hns3_mac_mgr_tbl_entry_cmd *req) 3426 { 3427 struct hns3_cmd_desc desc; 3428 uint8_t resp_code; 3429 uint16_t retval; 3430 int ret; 3431 3432 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 3433 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 3434 3435 ret = hns3_cmd_send(hw, &desc, 1); 3436 if (ret) { 3437 PMD_INIT_LOG(ERR, 3438 "add mac ethertype failed for cmd_send, ret =%d.", 3439 ret); 3440 return ret; 3441 } 3442 3443 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 3444 retval = rte_le_to_cpu_16(desc.retval); 3445 3446 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 3447 } 3448 3449 static void 3450 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 3451 int *table_item_num) 3452 { 3453 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 3454 3455 /* 3456 * In current version, we add one item in management table as below: 3457 * 0x0180C200000E -- LLDP MC address 3458 */ 3459 tbl = mgr_table; 3460 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 3461 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 3462 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 3463 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 3464 tbl->i_port_bitmap = 0x1; 3465 *table_item_num = 1; 3466 } 3467 3468 static int 3469 hns3_init_mgr_tbl(struct hns3_hw *hw) 3470 { 3471 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 3472 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 3473 int table_item_num; 3474 int ret; 3475 int i; 3476 3477 memset(mgr_table, 0, sizeof(mgr_table)); 3478 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 3479 for (i = 0; i < table_item_num; i++) { 3480 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 3481 if (ret) { 3482 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 3483 ret); 3484 return ret; 3485 } 3486 } 3487 3488 return 0; 3489 } 3490 3491 static void 3492 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 3493 bool en_mc, bool en_bc, int vport_id) 3494 { 3495 if (!param) 3496 return; 3497 3498 memset(param, 0, sizeof(struct hns3_promisc_param)); 3499 if (en_uc) 3500 param->enable = HNS3_PROMISC_EN_UC; 3501 if (en_mc) 3502 param->enable |= HNS3_PROMISC_EN_MC; 3503 if (en_bc) 3504 param->enable |= HNS3_PROMISC_EN_BC; 3505 param->vf_id = vport_id; 3506 } 3507 3508 static int 3509 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 3510 { 3511 struct hns3_promisc_cfg_cmd *req; 3512 struct hns3_cmd_desc desc; 3513 int ret; 3514 3515 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 3516 3517 req = (struct hns3_promisc_cfg_cmd *)desc.data; 3518 req->vf_id = param->vf_id; 3519 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 3520 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 3521 3522 ret = hns3_cmd_send(hw, &desc, 1); 3523 if (ret) 3524 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret); 3525 3526 return ret; 3527 } 3528 3529 static int 3530 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 3531 { 3532 struct hns3_promisc_param param; 3533 bool en_bc_pmc = true; 3534 uint8_t vf_id; 3535 int ret; 3536 3537 /* 3538 * In current version VF is not supported when PF is driven by DPDK 3539 * driver, the PF-related vf_id is 0, just need to configure parameters 3540 * for vf_id 0. 3541 */ 3542 vf_id = 0; 3543 3544 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 3545 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3546 if (ret) 3547 return ret; 3548 3549 return 0; 3550 } 3551 3552 static int 3553 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 3554 { 3555 struct hns3_adapter *hns = dev->data->dev_private; 3556 struct hns3_hw *hw = &hns->hw; 3557 bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false; 3558 int ret = 0; 3559 3560 rte_spinlock_lock(&hw->lock); 3561 ret = hns3_set_promisc_mode(hw, true, en_mc_pmc); 3562 rte_spinlock_unlock(&hw->lock); 3563 if (ret) 3564 hns3_err(hw, "Failed to enable promiscuous mode: %d", ret); 3565 3566 return ret; 3567 } 3568 3569 static int 3570 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 3571 { 3572 struct hns3_adapter *hns = dev->data->dev_private; 3573 struct hns3_hw *hw = &hns->hw; 3574 bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false; 3575 int ret = 0; 3576 3577 /* If now in all_multicast mode, must remain in all_multicast mode. */ 3578 rte_spinlock_lock(&hw->lock); 3579 ret = hns3_set_promisc_mode(hw, false, en_mc_pmc); 3580 rte_spinlock_unlock(&hw->lock); 3581 if (ret) 3582 hns3_err(hw, "Failed to disable promiscuous mode: %d", ret); 3583 3584 return ret; 3585 } 3586 3587 static int 3588 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 3589 { 3590 struct hns3_adapter *hns = dev->data->dev_private; 3591 struct hns3_hw *hw = &hns->hw; 3592 bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false; 3593 int ret = 0; 3594 3595 rte_spinlock_lock(&hw->lock); 3596 ret = hns3_set_promisc_mode(hw, en_uc_pmc, true); 3597 rte_spinlock_unlock(&hw->lock); 3598 if (ret) 3599 hns3_err(hw, "Failed to enable allmulticast mode: %d", ret); 3600 3601 return ret; 3602 } 3603 3604 static int 3605 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 3606 { 3607 struct hns3_adapter *hns = dev->data->dev_private; 3608 struct hns3_hw *hw = &hns->hw; 3609 bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false; 3610 int ret = 0; 3611 3612 /* If now in promiscuous mode, must remain in all_multicast mode. */ 3613 if (dev->data->promiscuous == 1) 3614 return 0; 3615 3616 rte_spinlock_lock(&hw->lock); 3617 ret = hns3_set_promisc_mode(hw, en_uc_pmc, false); 3618 rte_spinlock_unlock(&hw->lock); 3619 if (ret) 3620 hns3_err(hw, "Failed to disable allmulticast mode: %d", ret); 3621 3622 return ret; 3623 } 3624 3625 static int 3626 hns3_dev_promisc_restore(struct hns3_adapter *hns) 3627 { 3628 struct hns3_hw *hw = &hns->hw; 3629 bool en_mc_pmc; 3630 bool en_uc_pmc; 3631 3632 en_uc_pmc = (hw->data->promiscuous == 1) ? true : false; 3633 en_mc_pmc = (hw->data->all_multicast == 1) ? true : false; 3634 3635 return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc); 3636 } 3637 3638 static int 3639 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed) 3640 { 3641 struct hns3_sfp_speed_cmd *resp; 3642 struct hns3_cmd_desc desc; 3643 int ret; 3644 3645 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true); 3646 resp = (struct hns3_sfp_speed_cmd *)desc.data; 3647 ret = hns3_cmd_send(hw, &desc, 1); 3648 if (ret == -EOPNOTSUPP) { 3649 hns3_err(hw, "IMP do not support get SFP speed %d", ret); 3650 return ret; 3651 } else if (ret) { 3652 hns3_err(hw, "get sfp speed failed %d", ret); 3653 return ret; 3654 } 3655 3656 *speed = resp->sfp_speed; 3657 3658 return 0; 3659 } 3660 3661 static uint8_t 3662 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 3663 { 3664 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 3665 duplex = ETH_LINK_FULL_DUPLEX; 3666 3667 return duplex; 3668 } 3669 3670 static int 3671 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 3672 { 3673 struct hns3_mac *mac = &hw->mac; 3674 int ret; 3675 3676 duplex = hns3_check_speed_dup(duplex, speed); 3677 if (mac->link_speed == speed && mac->link_duplex == duplex) 3678 return 0; 3679 3680 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 3681 if (ret) 3682 return ret; 3683 3684 mac->link_speed = speed; 3685 mac->link_duplex = duplex; 3686 3687 return 0; 3688 } 3689 3690 static int 3691 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev) 3692 { 3693 struct hns3_adapter *hns = eth_dev->data->dev_private; 3694 struct hns3_hw *hw = &hns->hw; 3695 struct hns3_pf *pf = &hns->pf; 3696 uint32_t speed; 3697 int ret; 3698 3699 /* If IMP do not support get SFP/qSFP speed, return directly */ 3700 if (!pf->support_sfp_query) 3701 return 0; 3702 3703 ret = hns3_get_sfp_speed(hw, &speed); 3704 if (ret == -EOPNOTSUPP) { 3705 pf->support_sfp_query = false; 3706 return ret; 3707 } else if (ret) 3708 return ret; 3709 3710 if (speed == ETH_SPEED_NUM_NONE) 3711 return 0; /* do nothing if no SFP */ 3712 3713 /* Config full duplex for SFP */ 3714 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX); 3715 } 3716 3717 static int 3718 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 3719 { 3720 struct hns3_config_mac_mode_cmd *req; 3721 struct hns3_cmd_desc desc; 3722 uint32_t loop_en = 0; 3723 uint8_t val = 0; 3724 int ret; 3725 3726 req = (struct hns3_config_mac_mode_cmd *)desc.data; 3727 3728 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 3729 if (enable) 3730 val = 1; 3731 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 3732 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 3733 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 3734 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 3735 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 3736 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 3737 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 3738 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 3739 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 3740 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 3741 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 3742 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 3743 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 3744 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 3745 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 3746 3747 ret = hns3_cmd_send(hw, &desc, 1); 3748 if (ret) 3749 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 3750 3751 return ret; 3752 } 3753 3754 static int 3755 hns3_get_mac_link_status(struct hns3_hw *hw) 3756 { 3757 struct hns3_link_status_cmd *req; 3758 struct hns3_cmd_desc desc; 3759 int link_status; 3760 int ret; 3761 3762 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 3763 ret = hns3_cmd_send(hw, &desc, 1); 3764 if (ret) { 3765 hns3_err(hw, "get link status cmd failed %d", ret); 3766 return ret; 3767 } 3768 3769 req = (struct hns3_link_status_cmd *)desc.data; 3770 link_status = req->status & HNS3_LINK_STATUS_UP_M; 3771 3772 return !!link_status; 3773 } 3774 3775 static void 3776 hns3_update_link_status(struct hns3_hw *hw) 3777 { 3778 int state; 3779 3780 state = hns3_get_mac_link_status(hw); 3781 if (state != hw->mac.link_status) 3782 hw->mac.link_status = state; 3783 } 3784 3785 static void 3786 hns3_service_handler(void *param) 3787 { 3788 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 3789 struct hns3_adapter *hns = eth_dev->data->dev_private; 3790 struct hns3_hw *hw = &hns->hw; 3791 3792 if (!hns3_is_reset_pending(hns)) { 3793 hns3_update_speed_duplex(eth_dev); 3794 hns3_update_link_status(hw); 3795 } else 3796 hns3_warn(hw, "Cancel the query when reset is pending"); 3797 3798 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 3799 } 3800 3801 static int 3802 hns3_init_hardware(struct hns3_adapter *hns) 3803 { 3804 struct hns3_hw *hw = &hns->hw; 3805 int ret; 3806 3807 ret = hns3_map_tqp(hw); 3808 if (ret) { 3809 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 3810 return ret; 3811 } 3812 3813 ret = hns3_init_umv_space(hw); 3814 if (ret) { 3815 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 3816 return ret; 3817 } 3818 3819 ret = hns3_mac_init(hw); 3820 if (ret) { 3821 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 3822 goto err_mac_init; 3823 } 3824 3825 ret = hns3_init_mgr_tbl(hw); 3826 if (ret) { 3827 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 3828 goto err_mac_init; 3829 } 3830 3831 ret = hns3_set_promisc_mode(hw, false, false); 3832 if (ret) { 3833 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret); 3834 goto err_mac_init; 3835 } 3836 3837 ret = hns3_init_vlan_config(hns); 3838 if (ret) { 3839 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 3840 goto err_mac_init; 3841 } 3842 3843 ret = hns3_dcb_init(hw); 3844 if (ret) { 3845 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 3846 goto err_mac_init; 3847 } 3848 3849 ret = hns3_init_fd_config(hns); 3850 if (ret) { 3851 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 3852 goto err_mac_init; 3853 } 3854 3855 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 3856 if (ret) { 3857 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 3858 goto err_mac_init; 3859 } 3860 3861 ret = hns3_config_gro(hw, false); 3862 if (ret) { 3863 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 3864 goto err_mac_init; 3865 } 3866 return 0; 3867 3868 err_mac_init: 3869 hns3_uninit_umv_space(hw); 3870 return ret; 3871 } 3872 3873 static int 3874 hns3_init_pf(struct rte_eth_dev *eth_dev) 3875 { 3876 struct rte_device *dev = eth_dev->device; 3877 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 3878 struct hns3_adapter *hns = eth_dev->data->dev_private; 3879 struct hns3_hw *hw = &hns->hw; 3880 int ret; 3881 3882 PMD_INIT_FUNC_TRACE(); 3883 3884 /* Get hardware io base address from pcie BAR2 IO space */ 3885 hw->io_base = pci_dev->mem_resource[2].addr; 3886 3887 /* Firmware command queue initialize */ 3888 ret = hns3_cmd_init_queue(hw); 3889 if (ret) { 3890 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 3891 goto err_cmd_init_queue; 3892 } 3893 3894 hns3_clear_all_event_cause(hw); 3895 3896 /* Firmware command initialize */ 3897 ret = hns3_cmd_init(hw); 3898 if (ret) { 3899 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 3900 goto err_cmd_init; 3901 } 3902 3903 ret = rte_intr_callback_register(&pci_dev->intr_handle, 3904 hns3_interrupt_handler, 3905 eth_dev); 3906 if (ret) { 3907 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 3908 goto err_intr_callback_register; 3909 } 3910 3911 /* Enable interrupt */ 3912 rte_intr_enable(&pci_dev->intr_handle); 3913 hns3_pf_enable_irq0(hw); 3914 3915 /* Get configuration */ 3916 ret = hns3_get_configuration(hw); 3917 if (ret) { 3918 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 3919 goto err_get_config; 3920 } 3921 3922 ret = hns3_init_hardware(hns); 3923 if (ret) { 3924 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 3925 goto err_get_config; 3926 } 3927 3928 /* Initialize flow director filter list & hash */ 3929 ret = hns3_fdir_filter_init(hns); 3930 if (ret) { 3931 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 3932 goto err_hw_init; 3933 } 3934 3935 hns3_set_default_rss_args(hw); 3936 3937 ret = hns3_enable_hw_error_intr(hns, true); 3938 if (ret) { 3939 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 3940 ret); 3941 goto err_fdir; 3942 } 3943 3944 return 0; 3945 3946 err_fdir: 3947 hns3_fdir_filter_uninit(hns); 3948 err_hw_init: 3949 hns3_uninit_umv_space(hw); 3950 3951 err_get_config: 3952 hns3_pf_disable_irq0(hw); 3953 rte_intr_disable(&pci_dev->intr_handle); 3954 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 3955 eth_dev); 3956 3957 err_intr_callback_register: 3958 hns3_cmd_uninit(hw); 3959 3960 err_cmd_init: 3961 hns3_cmd_destroy_queue(hw); 3962 3963 err_cmd_init_queue: 3964 hw->io_base = NULL; 3965 3966 return ret; 3967 } 3968 3969 static void 3970 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 3971 { 3972 struct hns3_adapter *hns = eth_dev->data->dev_private; 3973 struct rte_device *dev = eth_dev->device; 3974 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 3975 struct hns3_hw *hw = &hns->hw; 3976 3977 PMD_INIT_FUNC_TRACE(); 3978 3979 hns3_enable_hw_error_intr(hns, false); 3980 hns3_rss_uninit(hns); 3981 hns3_fdir_filter_uninit(hns); 3982 hns3_uninit_umv_space(hw); 3983 hns3_pf_disable_irq0(hw); 3984 rte_intr_disable(&pci_dev->intr_handle); 3985 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 3986 eth_dev); 3987 hns3_cmd_uninit(hw); 3988 hns3_cmd_destroy_queue(hw); 3989 hw->io_base = NULL; 3990 } 3991 3992 static int 3993 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 3994 { 3995 struct hns3_hw *hw = &hns->hw; 3996 int ret; 3997 3998 ret = hns3_dcb_cfg_update(hns); 3999 if (ret) 4000 return ret; 4001 4002 /* Enable queues */ 4003 ret = hns3_start_queues(hns, reset_queue); 4004 if (ret) { 4005 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret); 4006 return ret; 4007 } 4008 4009 /* Enable MAC */ 4010 ret = hns3_cfg_mac_mode(hw, true); 4011 if (ret) { 4012 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret); 4013 goto err_config_mac_mode; 4014 } 4015 return 0; 4016 4017 err_config_mac_mode: 4018 hns3_stop_queues(hns, true); 4019 return ret; 4020 } 4021 4022 static int 4023 hns3_dev_start(struct rte_eth_dev *eth_dev) 4024 { 4025 struct hns3_adapter *hns = eth_dev->data->dev_private; 4026 struct hns3_hw *hw = &hns->hw; 4027 int ret; 4028 4029 PMD_INIT_FUNC_TRACE(); 4030 if (rte_atomic16_read(&hw->reset.resetting)) 4031 return -EBUSY; 4032 rte_spinlock_lock(&hw->lock); 4033 hw->adapter_state = HNS3_NIC_STARTING; 4034 4035 ret = hns3_do_start(hns, true); 4036 if (ret) { 4037 hw->adapter_state = HNS3_NIC_CONFIGURED; 4038 rte_spinlock_unlock(&hw->lock); 4039 return ret; 4040 } 4041 4042 hw->adapter_state = HNS3_NIC_STARTED; 4043 rte_spinlock_unlock(&hw->lock); 4044 hns3_set_rxtx_function(eth_dev); 4045 hns3_mp_req_start_rxtx(eth_dev); 4046 4047 hns3_info(hw, "hns3 dev start successful!"); 4048 return 0; 4049 } 4050 4051 static int 4052 hns3_do_stop(struct hns3_adapter *hns) 4053 { 4054 struct hns3_hw *hw = &hns->hw; 4055 bool reset_queue; 4056 int ret; 4057 4058 ret = hns3_cfg_mac_mode(hw, false); 4059 if (ret) 4060 return ret; 4061 hw->mac.link_status = ETH_LINK_DOWN; 4062 4063 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) { 4064 hns3_configure_all_mac_addr(hns, true); 4065 reset_queue = true; 4066 } else 4067 reset_queue = false; 4068 hw->mac.default_addr_setted = false; 4069 return hns3_stop_queues(hns, reset_queue); 4070 } 4071 4072 static void 4073 hns3_dev_stop(struct rte_eth_dev *eth_dev) 4074 { 4075 struct hns3_adapter *hns = eth_dev->data->dev_private; 4076 struct hns3_hw *hw = &hns->hw; 4077 4078 PMD_INIT_FUNC_TRACE(); 4079 4080 hw->adapter_state = HNS3_NIC_STOPPING; 4081 hns3_set_rxtx_function(eth_dev); 4082 rte_wmb(); 4083 /* Disable datapath on secondary process. */ 4084 hns3_mp_req_stop_rxtx(eth_dev); 4085 /* Prevent crashes when queues are still in use. */ 4086 rte_delay_ms(hw->tqps_num); 4087 4088 rte_spinlock_lock(&hw->lock); 4089 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 4090 hns3_do_stop(hns); 4091 hns3_dev_release_mbufs(hns); 4092 hw->adapter_state = HNS3_NIC_CONFIGURED; 4093 } 4094 rte_spinlock_unlock(&hw->lock); 4095 } 4096 4097 static void 4098 hns3_dev_close(struct rte_eth_dev *eth_dev) 4099 { 4100 struct hns3_adapter *hns = eth_dev->data->dev_private; 4101 struct hns3_hw *hw = &hns->hw; 4102 4103 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 4104 rte_free(eth_dev->process_private); 4105 eth_dev->process_private = NULL; 4106 return; 4107 } 4108 4109 if (hw->adapter_state == HNS3_NIC_STARTED) 4110 hns3_dev_stop(eth_dev); 4111 4112 hw->adapter_state = HNS3_NIC_CLOSING; 4113 hns3_reset_abort(hns); 4114 hw->adapter_state = HNS3_NIC_CLOSED; 4115 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 4116 4117 hns3_configure_all_mc_mac_addr(hns, true); 4118 hns3_remove_all_vlan_table(hns); 4119 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 4120 hns3_uninit_pf(eth_dev); 4121 hns3_free_all_queues(eth_dev); 4122 rte_free(hw->reset.wait_data); 4123 rte_free(eth_dev->process_private); 4124 eth_dev->process_private = NULL; 4125 hns3_mp_uninit_primary(); 4126 hns3_warn(hw, "Close port %d finished", hw->data->port_id); 4127 } 4128 4129 static int 4130 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4131 { 4132 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4133 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4134 4135 fc_conf->pause_time = pf->pause_time; 4136 4137 /* return fc current mode */ 4138 switch (hw->current_mode) { 4139 case HNS3_FC_FULL: 4140 fc_conf->mode = RTE_FC_FULL; 4141 break; 4142 case HNS3_FC_TX_PAUSE: 4143 fc_conf->mode = RTE_FC_TX_PAUSE; 4144 break; 4145 case HNS3_FC_RX_PAUSE: 4146 fc_conf->mode = RTE_FC_RX_PAUSE; 4147 break; 4148 case HNS3_FC_NONE: 4149 default: 4150 fc_conf->mode = RTE_FC_NONE; 4151 break; 4152 } 4153 4154 return 0; 4155 } 4156 4157 static void 4158 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode) 4159 { 4160 switch (mode) { 4161 case RTE_FC_NONE: 4162 hw->requested_mode = HNS3_FC_NONE; 4163 break; 4164 case RTE_FC_RX_PAUSE: 4165 hw->requested_mode = HNS3_FC_RX_PAUSE; 4166 break; 4167 case RTE_FC_TX_PAUSE: 4168 hw->requested_mode = HNS3_FC_TX_PAUSE; 4169 break; 4170 case RTE_FC_FULL: 4171 hw->requested_mode = HNS3_FC_FULL; 4172 break; 4173 default: 4174 hw->requested_mode = HNS3_FC_NONE; 4175 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is " 4176 "configured to RTE_FC_NONE", mode); 4177 break; 4178 } 4179 } 4180 4181 static int 4182 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4183 { 4184 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4185 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4186 int ret; 4187 4188 if (fc_conf->high_water || fc_conf->low_water || 4189 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 4190 hns3_err(hw, "Unsupported flow control settings specified, " 4191 "high_water(%u), low_water(%u), send_xon(%u) and " 4192 "mac_ctrl_frame_fwd(%u) must be set to '0'", 4193 fc_conf->high_water, fc_conf->low_water, 4194 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 4195 return -EINVAL; 4196 } 4197 if (fc_conf->autoneg) { 4198 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 4199 return -EINVAL; 4200 } 4201 if (!fc_conf->pause_time) { 4202 hns3_err(hw, "Invalid pause time %d setting.", 4203 fc_conf->pause_time); 4204 return -EINVAL; 4205 } 4206 4207 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 4208 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 4209 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 4210 "current_fc_status = %d", hw->current_fc_status); 4211 return -EOPNOTSUPP; 4212 } 4213 4214 hns3_get_fc_mode(hw, fc_conf->mode); 4215 if (hw->requested_mode == hw->current_mode && 4216 pf->pause_time == fc_conf->pause_time) 4217 return 0; 4218 4219 rte_spinlock_lock(&hw->lock); 4220 ret = hns3_fc_enable(dev, fc_conf); 4221 rte_spinlock_unlock(&hw->lock); 4222 4223 return ret; 4224 } 4225 4226 static int 4227 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 4228 struct rte_eth_pfc_conf *pfc_conf) 4229 { 4230 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4231 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4232 uint8_t priority; 4233 int ret; 4234 4235 if (!hns3_dev_dcb_supported(hw)) { 4236 hns3_err(hw, "This port does not support dcb configurations."); 4237 return -EOPNOTSUPP; 4238 } 4239 4240 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 4241 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 4242 hns3_err(hw, "Unsupported flow control settings specified, " 4243 "high_water(%u), low_water(%u), send_xon(%u) and " 4244 "mac_ctrl_frame_fwd(%u) must be set to '0'", 4245 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 4246 pfc_conf->fc.send_xon, 4247 pfc_conf->fc.mac_ctrl_frame_fwd); 4248 return -EINVAL; 4249 } 4250 if (pfc_conf->fc.autoneg) { 4251 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 4252 return -EINVAL; 4253 } 4254 if (pfc_conf->fc.pause_time == 0) { 4255 hns3_err(hw, "Invalid pause time %d setting.", 4256 pfc_conf->fc.pause_time); 4257 return -EINVAL; 4258 } 4259 4260 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 4261 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 4262 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 4263 "current_fc_status = %d", hw->current_fc_status); 4264 return -EOPNOTSUPP; 4265 } 4266 4267 priority = pfc_conf->priority; 4268 hns3_get_fc_mode(hw, pfc_conf->fc.mode); 4269 if (hw->dcb_info.pfc_en & BIT(priority) && 4270 hw->requested_mode == hw->current_mode && 4271 pfc_conf->fc.pause_time == pf->pause_time) 4272 return 0; 4273 4274 rte_spinlock_lock(&hw->lock); 4275 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 4276 rte_spinlock_unlock(&hw->lock); 4277 4278 return ret; 4279 } 4280 4281 static int 4282 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 4283 { 4284 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4285 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4286 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 4287 int i; 4288 4289 rte_spinlock_lock(&hw->lock); 4290 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 4291 dcb_info->nb_tcs = pf->local_max_tc; 4292 else 4293 dcb_info->nb_tcs = 1; 4294 4295 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 4296 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 4297 for (i = 0; i < dcb_info->nb_tcs; i++) 4298 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 4299 4300 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 4301 dcb_info->tc_queue.tc_rxq[0][i].base = 4302 hw->tc_queue[i].tqp_offset; 4303 dcb_info->tc_queue.tc_txq[0][i].base = 4304 hw->tc_queue[i].tqp_offset; 4305 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 4306 hw->tc_queue[i].tqp_count; 4307 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 4308 hw->tc_queue[i].tqp_count; 4309 } 4310 rte_spinlock_unlock(&hw->lock); 4311 4312 return 0; 4313 } 4314 4315 static int 4316 hns3_reinit_dev(struct hns3_adapter *hns) 4317 { 4318 struct hns3_hw *hw = &hns->hw; 4319 int ret; 4320 4321 ret = hns3_cmd_init(hw); 4322 if (ret) { 4323 hns3_err(hw, "Failed to init cmd: %d", ret); 4324 return ret; 4325 } 4326 4327 ret = hns3_reset_all_queues(hns); 4328 if (ret) { 4329 hns3_err(hw, "Failed to reset all queues: %d", ret); 4330 goto err_init; 4331 } 4332 4333 ret = hns3_init_hardware(hns); 4334 if (ret) { 4335 hns3_err(hw, "Failed to init hardware: %d", ret); 4336 goto err_init; 4337 } 4338 4339 ret = hns3_enable_hw_error_intr(hns, true); 4340 if (ret) { 4341 hns3_err(hw, "fail to enable hw error interrupts: %d", 4342 ret); 4343 goto err_mac_init; 4344 } 4345 hns3_info(hw, "Reset done, driver initialization finished."); 4346 4347 return 0; 4348 4349 err_mac_init: 4350 hns3_uninit_umv_space(hw); 4351 err_init: 4352 hns3_cmd_uninit(hw); 4353 4354 return ret; 4355 } 4356 4357 static bool 4358 is_pf_reset_done(struct hns3_hw *hw) 4359 { 4360 uint32_t val, reg, reg_bit; 4361 4362 switch (hw->reset.level) { 4363 case HNS3_IMP_RESET: 4364 reg = HNS3_GLOBAL_RESET_REG; 4365 reg_bit = HNS3_IMP_RESET_BIT; 4366 break; 4367 case HNS3_GLOBAL_RESET: 4368 reg = HNS3_GLOBAL_RESET_REG; 4369 reg_bit = HNS3_GLOBAL_RESET_BIT; 4370 break; 4371 case HNS3_FUNC_RESET: 4372 reg = HNS3_FUN_RST_ING; 4373 reg_bit = HNS3_FUN_RST_ING_B; 4374 break; 4375 case HNS3_FLR_RESET: 4376 default: 4377 hns3_err(hw, "Wait for unsupported reset level: %d", 4378 hw->reset.level); 4379 return true; 4380 } 4381 val = hns3_read_dev(hw, reg); 4382 if (hns3_get_bit(val, reg_bit)) 4383 return false; 4384 else 4385 return true; 4386 } 4387 4388 bool 4389 hns3_is_reset_pending(struct hns3_adapter *hns) 4390 { 4391 struct hns3_hw *hw = &hns->hw; 4392 enum hns3_reset_level reset; 4393 4394 hns3_check_event_cause(hns, NULL); 4395 reset = hns3_get_reset_level(hns, &hw->reset.pending); 4396 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 4397 hns3_warn(hw, "High level reset %d is pending", reset); 4398 return true; 4399 } 4400 reset = hns3_get_reset_level(hns, &hw->reset.request); 4401 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 4402 hns3_warn(hw, "High level reset %d is request", reset); 4403 return true; 4404 } 4405 return false; 4406 } 4407 4408 static int 4409 hns3_wait_hardware_ready(struct hns3_adapter *hns) 4410 { 4411 struct hns3_hw *hw = &hns->hw; 4412 struct hns3_wait_data *wait_data = hw->reset.wait_data; 4413 struct timeval tv; 4414 4415 if (wait_data->result == HNS3_WAIT_SUCCESS) 4416 return 0; 4417 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 4418 gettimeofday(&tv, NULL); 4419 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 4420 tv.tv_sec, tv.tv_usec); 4421 return -ETIME; 4422 } else if (wait_data->result == HNS3_WAIT_REQUEST) 4423 return -EAGAIN; 4424 4425 wait_data->hns = hns; 4426 wait_data->check_completion = is_pf_reset_done; 4427 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 4428 HNS3_RESET_WAIT_MS + get_timeofday_ms(); 4429 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 4430 wait_data->count = HNS3_RESET_WAIT_CNT; 4431 wait_data->result = HNS3_WAIT_REQUEST; 4432 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 4433 return -EAGAIN; 4434 } 4435 4436 static int 4437 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 4438 { 4439 struct hns3_cmd_desc desc; 4440 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 4441 4442 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 4443 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 4444 req->fun_reset_vfid = func_id; 4445 4446 return hns3_cmd_send(hw, &desc, 1); 4447 } 4448 4449 static int 4450 hns3_imp_reset_cmd(struct hns3_hw *hw) 4451 { 4452 struct hns3_cmd_desc desc; 4453 4454 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 4455 desc.data[0] = 0xeedd; 4456 4457 return hns3_cmd_send(hw, &desc, 1); 4458 } 4459 4460 static void 4461 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 4462 { 4463 struct hns3_hw *hw = &hns->hw; 4464 struct timeval tv; 4465 uint32_t val; 4466 4467 gettimeofday(&tv, NULL); 4468 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 4469 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 4470 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 4471 tv.tv_sec, tv.tv_usec); 4472 return; 4473 } 4474 4475 switch (reset_level) { 4476 case HNS3_IMP_RESET: 4477 hns3_imp_reset_cmd(hw); 4478 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 4479 tv.tv_sec, tv.tv_usec); 4480 break; 4481 case HNS3_GLOBAL_RESET: 4482 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 4483 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 4484 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 4485 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 4486 tv.tv_sec, tv.tv_usec); 4487 break; 4488 case HNS3_FUNC_RESET: 4489 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 4490 tv.tv_sec, tv.tv_usec); 4491 /* schedule again to check later */ 4492 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 4493 hns3_schedule_reset(hns); 4494 break; 4495 default: 4496 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 4497 return; 4498 } 4499 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 4500 } 4501 4502 static enum hns3_reset_level 4503 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 4504 { 4505 struct hns3_hw *hw = &hns->hw; 4506 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 4507 4508 /* Return the highest priority reset level amongst all */ 4509 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 4510 reset_level = HNS3_IMP_RESET; 4511 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 4512 reset_level = HNS3_GLOBAL_RESET; 4513 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 4514 reset_level = HNS3_FUNC_RESET; 4515 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 4516 reset_level = HNS3_FLR_RESET; 4517 4518 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 4519 return HNS3_NONE_RESET; 4520 4521 return reset_level; 4522 } 4523 4524 static int 4525 hns3_prepare_reset(struct hns3_adapter *hns) 4526 { 4527 struct hns3_hw *hw = &hns->hw; 4528 uint32_t reg_val; 4529 int ret; 4530 4531 switch (hw->reset.level) { 4532 case HNS3_FUNC_RESET: 4533 ret = hns3_func_reset_cmd(hw, 0); 4534 if (ret) 4535 return ret; 4536 4537 /* 4538 * After performaning pf reset, it is not necessary to do the 4539 * mailbox handling or send any command to firmware, because 4540 * any mailbox handling or command to firmware is only valid 4541 * after hns3_cmd_init is called. 4542 */ 4543 rte_atomic16_set(&hw->reset.disable_cmd, 1); 4544 hw->reset.stats.request_cnt++; 4545 break; 4546 case HNS3_IMP_RESET: 4547 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 4548 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 4549 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 4550 break; 4551 default: 4552 break; 4553 } 4554 return 0; 4555 } 4556 4557 static int 4558 hns3_set_rst_done(struct hns3_hw *hw) 4559 { 4560 struct hns3_pf_rst_done_cmd *req; 4561 struct hns3_cmd_desc desc; 4562 4563 req = (struct hns3_pf_rst_done_cmd *)desc.data; 4564 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 4565 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 4566 return hns3_cmd_send(hw, &desc, 1); 4567 } 4568 4569 static int 4570 hns3_stop_service(struct hns3_adapter *hns) 4571 { 4572 struct hns3_hw *hw = &hns->hw; 4573 struct rte_eth_dev *eth_dev; 4574 4575 eth_dev = &rte_eth_devices[hw->data->port_id]; 4576 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 4577 hw->mac.link_status = ETH_LINK_DOWN; 4578 4579 hns3_set_rxtx_function(eth_dev); 4580 rte_wmb(); 4581 /* Disable datapath on secondary process. */ 4582 hns3_mp_req_stop_rxtx(eth_dev); 4583 rte_delay_ms(hw->tqps_num); 4584 4585 rte_spinlock_lock(&hw->lock); 4586 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 4587 hw->adapter_state == HNS3_NIC_STOPPING) { 4588 hns3_do_stop(hns); 4589 hw->reset.mbuf_deferred_free = true; 4590 } else 4591 hw->reset.mbuf_deferred_free = false; 4592 4593 /* 4594 * It is cumbersome for hardware to pick-and-choose entries for deletion 4595 * from table space. Hence, for function reset software intervention is 4596 * required to delete the entries 4597 */ 4598 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) 4599 hns3_configure_all_mc_mac_addr(hns, true); 4600 rte_spinlock_unlock(&hw->lock); 4601 4602 return 0; 4603 } 4604 4605 static int 4606 hns3_start_service(struct hns3_adapter *hns) 4607 { 4608 struct hns3_hw *hw = &hns->hw; 4609 struct rte_eth_dev *eth_dev; 4610 4611 if (hw->reset.level == HNS3_IMP_RESET || 4612 hw->reset.level == HNS3_GLOBAL_RESET) 4613 hns3_set_rst_done(hw); 4614 eth_dev = &rte_eth_devices[hw->data->port_id]; 4615 hns3_set_rxtx_function(eth_dev); 4616 hns3_mp_req_start_rxtx(eth_dev); 4617 hns3_service_handler(eth_dev); 4618 return 0; 4619 } 4620 4621 static int 4622 hns3_restore_conf(struct hns3_adapter *hns) 4623 { 4624 struct hns3_hw *hw = &hns->hw; 4625 int ret; 4626 4627 ret = hns3_configure_all_mac_addr(hns, false); 4628 if (ret) 4629 return ret; 4630 4631 ret = hns3_configure_all_mc_mac_addr(hns, false); 4632 if (ret) 4633 goto err_mc_mac; 4634 4635 ret = hns3_dev_promisc_restore(hns); 4636 if (ret) 4637 goto err_promisc; 4638 4639 ret = hns3_restore_vlan_table(hns); 4640 if (ret) 4641 goto err_promisc; 4642 4643 ret = hns3_restore_vlan_conf(hns); 4644 if (ret) 4645 goto err_promisc; 4646 4647 ret = hns3_restore_all_fdir_filter(hns); 4648 if (ret) 4649 goto err_promisc; 4650 4651 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 4652 ret = hns3_do_start(hns, false); 4653 if (ret) 4654 goto err_promisc; 4655 hns3_info(hw, "hns3 dev restart successful!"); 4656 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 4657 hw->adapter_state = HNS3_NIC_CONFIGURED; 4658 return 0; 4659 4660 err_promisc: 4661 hns3_configure_all_mc_mac_addr(hns, true); 4662 err_mc_mac: 4663 hns3_configure_all_mac_addr(hns, true); 4664 return ret; 4665 } 4666 4667 static void 4668 hns3_reset_service(void *param) 4669 { 4670 struct hns3_adapter *hns = (struct hns3_adapter *)param; 4671 struct hns3_hw *hw = &hns->hw; 4672 enum hns3_reset_level reset_level; 4673 struct timeval tv_delta; 4674 struct timeval tv_start; 4675 struct timeval tv; 4676 uint64_t msec; 4677 int ret; 4678 4679 /* 4680 * The interrupt is not triggered within the delay time. 4681 * The interrupt may have been lost. It is necessary to handle 4682 * the interrupt to recover from the error. 4683 */ 4684 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) { 4685 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); 4686 hns3_err(hw, "Handling interrupts in delayed tasks"); 4687 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 4688 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 4689 if (reset_level == HNS3_NONE_RESET) { 4690 hns3_err(hw, "No reset level is set, try IMP reset"); 4691 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 4692 } 4693 } 4694 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); 4695 4696 /* 4697 * Check if there is any ongoing reset in the hardware. This status can 4698 * be checked from reset_pending. If there is then, we need to wait for 4699 * hardware to complete reset. 4700 * a. If we are able to figure out in reasonable time that hardware 4701 * has fully resetted then, we can proceed with driver, client 4702 * reset. 4703 * b. else, we can come back later to check this status so re-sched 4704 * now. 4705 */ 4706 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 4707 if (reset_level != HNS3_NONE_RESET) { 4708 gettimeofday(&tv_start, NULL); 4709 ret = hns3_reset_process(hns, reset_level); 4710 gettimeofday(&tv, NULL); 4711 timersub(&tv, &tv_start, &tv_delta); 4712 msec = tv_delta.tv_sec * MSEC_PER_SEC + 4713 tv_delta.tv_usec / USEC_PER_MSEC; 4714 if (msec > HNS3_RESET_PROCESS_MS) 4715 hns3_err(hw, "%d handle long time delta %" PRIx64 4716 " ms time=%ld.%.6ld", 4717 hw->reset.level, msec, 4718 tv.tv_sec, tv.tv_usec); 4719 if (ret == -EAGAIN) 4720 return; 4721 } 4722 4723 /* Check if we got any *new* reset requests to be honored */ 4724 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 4725 if (reset_level != HNS3_NONE_RESET) 4726 hns3_msix_process(hns, reset_level); 4727 } 4728 4729 static const struct eth_dev_ops hns3_eth_dev_ops = { 4730 .dev_start = hns3_dev_start, 4731 .dev_stop = hns3_dev_stop, 4732 .dev_close = hns3_dev_close, 4733 .promiscuous_enable = hns3_dev_promiscuous_enable, 4734 .promiscuous_disable = hns3_dev_promiscuous_disable, 4735 .allmulticast_enable = hns3_dev_allmulticast_enable, 4736 .allmulticast_disable = hns3_dev_allmulticast_disable, 4737 .mtu_set = hns3_dev_mtu_set, 4738 .stats_get = hns3_stats_get, 4739 .stats_reset = hns3_stats_reset, 4740 .xstats_get = hns3_dev_xstats_get, 4741 .xstats_get_names = hns3_dev_xstats_get_names, 4742 .xstats_reset = hns3_dev_xstats_reset, 4743 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 4744 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 4745 .dev_infos_get = hns3_dev_infos_get, 4746 .fw_version_get = hns3_fw_version_get, 4747 .rx_queue_setup = hns3_rx_queue_setup, 4748 .tx_queue_setup = hns3_tx_queue_setup, 4749 .rx_queue_release = hns3_dev_rx_queue_release, 4750 .tx_queue_release = hns3_dev_tx_queue_release, 4751 .dev_configure = hns3_dev_configure, 4752 .flow_ctrl_get = hns3_flow_ctrl_get, 4753 .flow_ctrl_set = hns3_flow_ctrl_set, 4754 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 4755 .mac_addr_add = hns3_add_mac_addr, 4756 .mac_addr_remove = hns3_remove_mac_addr, 4757 .mac_addr_set = hns3_set_default_mac_addr, 4758 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 4759 .link_update = hns3_dev_link_update, 4760 .rss_hash_update = hns3_dev_rss_hash_update, 4761 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 4762 .reta_update = hns3_dev_rss_reta_update, 4763 .reta_query = hns3_dev_rss_reta_query, 4764 .filter_ctrl = hns3_dev_filter_ctrl, 4765 .vlan_filter_set = hns3_vlan_filter_set, 4766 .vlan_tpid_set = hns3_vlan_tpid_set, 4767 .vlan_offload_set = hns3_vlan_offload_set, 4768 .vlan_pvid_set = hns3_vlan_pvid_set, 4769 .get_reg = hns3_get_regs, 4770 .get_dcb_info = hns3_get_dcb_info, 4771 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 4772 }; 4773 4774 static const struct hns3_reset_ops hns3_reset_ops = { 4775 .reset_service = hns3_reset_service, 4776 .stop_service = hns3_stop_service, 4777 .prepare_reset = hns3_prepare_reset, 4778 .wait_hardware_ready = hns3_wait_hardware_ready, 4779 .reinit_dev = hns3_reinit_dev, 4780 .restore_conf = hns3_restore_conf, 4781 .start_service = hns3_start_service, 4782 }; 4783 4784 static int 4785 hns3_dev_init(struct rte_eth_dev *eth_dev) 4786 { 4787 struct rte_device *dev = eth_dev->device; 4788 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4789 struct hns3_adapter *hns = eth_dev->data->dev_private; 4790 struct hns3_hw *hw = &hns->hw; 4791 uint16_t device_id = pci_dev->id.device_id; 4792 int ret; 4793 4794 PMD_INIT_FUNC_TRACE(); 4795 eth_dev->process_private = (struct hns3_process_private *) 4796 rte_zmalloc_socket("hns3_filter_list", 4797 sizeof(struct hns3_process_private), 4798 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 4799 if (eth_dev->process_private == NULL) { 4800 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 4801 return -ENOMEM; 4802 } 4803 /* initialize flow filter lists */ 4804 hns3_filterlist_init(eth_dev); 4805 4806 hns3_set_rxtx_function(eth_dev); 4807 eth_dev->dev_ops = &hns3_eth_dev_ops; 4808 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 4809 hns3_mp_init_secondary(); 4810 hw->secondary_cnt++; 4811 return 0; 4812 } 4813 4814 hns3_mp_init_primary(); 4815 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 4816 4817 if (device_id == HNS3_DEV_ID_25GE_RDMA || 4818 device_id == HNS3_DEV_ID_50GE_RDMA || 4819 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC) 4820 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1); 4821 4822 hns->is_vf = false; 4823 hw->data = eth_dev->data; 4824 4825 /* 4826 * Set default max packet size according to the mtu 4827 * default vale in DPDK frame. 4828 */ 4829 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 4830 4831 ret = hns3_reset_init(hw); 4832 if (ret) 4833 goto err_init_reset; 4834 hw->reset.ops = &hns3_reset_ops; 4835 4836 ret = hns3_init_pf(eth_dev); 4837 if (ret) { 4838 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 4839 goto err_init_pf; 4840 } 4841 4842 /* Allocate memory for storing MAC addresses */ 4843 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 4844 sizeof(struct rte_ether_addr) * 4845 HNS3_UC_MACADDR_NUM, 0); 4846 if (eth_dev->data->mac_addrs == NULL) { 4847 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 4848 "to store MAC addresses", 4849 sizeof(struct rte_ether_addr) * 4850 HNS3_UC_MACADDR_NUM); 4851 ret = -ENOMEM; 4852 goto err_rte_zmalloc; 4853 } 4854 4855 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 4856 ð_dev->data->mac_addrs[0]); 4857 4858 hw->adapter_state = HNS3_NIC_INITIALIZED; 4859 /* 4860 * Pass the information to the rte_eth_dev_close() that it should also 4861 * release the private port resources. 4862 */ 4863 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 4864 4865 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) { 4866 hns3_err(hw, "Reschedule reset service after dev_init"); 4867 hns3_schedule_reset(hns); 4868 } else { 4869 /* IMP will wait ready flag before reset */ 4870 hns3_notify_reset_ready(hw, false); 4871 } 4872 4873 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4874 hns3_info(hw, "hns3 dev initialization successful!"); 4875 return 0; 4876 4877 err_rte_zmalloc: 4878 hns3_uninit_pf(eth_dev); 4879 4880 err_init_pf: 4881 rte_free(hw->reset.wait_data); 4882 err_init_reset: 4883 eth_dev->dev_ops = NULL; 4884 eth_dev->rx_pkt_burst = NULL; 4885 eth_dev->tx_pkt_burst = NULL; 4886 eth_dev->tx_pkt_prepare = NULL; 4887 rte_free(eth_dev->process_private); 4888 eth_dev->process_private = NULL; 4889 return ret; 4890 } 4891 4892 static int 4893 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 4894 { 4895 struct hns3_adapter *hns = eth_dev->data->dev_private; 4896 struct hns3_hw *hw = &hns->hw; 4897 4898 PMD_INIT_FUNC_TRACE(); 4899 4900 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4901 return -EPERM; 4902 4903 eth_dev->dev_ops = NULL; 4904 eth_dev->rx_pkt_burst = NULL; 4905 eth_dev->tx_pkt_burst = NULL; 4906 eth_dev->tx_pkt_prepare = NULL; 4907 if (hw->adapter_state < HNS3_NIC_CLOSING) 4908 hns3_dev_close(eth_dev); 4909 4910 hw->adapter_state = HNS3_NIC_REMOVED; 4911 return 0; 4912 } 4913 4914 static int 4915 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 4916 struct rte_pci_device *pci_dev) 4917 { 4918 return rte_eth_dev_pci_generic_probe(pci_dev, 4919 sizeof(struct hns3_adapter), 4920 hns3_dev_init); 4921 } 4922 4923 static int 4924 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 4925 { 4926 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 4927 } 4928 4929 static const struct rte_pci_id pci_id_hns3_map[] = { 4930 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 4931 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 4932 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 4933 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 4934 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 4935 { .vendor_id = 0, /* sentinel */ }, 4936 }; 4937 4938 static struct rte_pci_driver rte_hns3_pmd = { 4939 .id_table = pci_id_hns3_map, 4940 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 4941 .probe = eth_hns3_pci_probe, 4942 .remove = eth_hns3_pci_remove, 4943 }; 4944 4945 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 4946 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 4947 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 4948 4949 RTE_INIT(hns3_init_log) 4950 { 4951 hns3_logtype_init = rte_log_register("pmd.net.hns3.init"); 4952 if (hns3_logtype_init >= 0) 4953 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE); 4954 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver"); 4955 if (hns3_logtype_driver >= 0) 4956 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE); 4957 } 4958