1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <rte_alarm.h> 6 #include <rte_bus_pci.h> 7 #include <ethdev_pci.h> 8 #include <rte_pci.h> 9 #include <rte_kvargs.h> 10 11 #include "hns3_ethdev.h" 12 #include "hns3_logs.h" 13 #include "hns3_rxtx.h" 14 #include "hns3_intr.h" 15 #include "hns3_regs.h" 16 #include "hns3_dcb.h" 17 #include "hns3_mp.h" 18 19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 21 22 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 23 #define HNS3_SERVICE_QUICK_INTERVAL 10 24 #define HNS3_INVALID_PVID 0xFFFF 25 26 #define HNS3_FILTER_TYPE_VF 0 27 #define HNS3_FILTER_TYPE_PORT 1 28 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 29 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 30 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 31 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 32 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 33 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 34 | HNS3_FILTER_FE_ROCE_EGRESS_B) 35 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 36 | HNS3_FILTER_FE_ROCE_INGRESS_B) 37 38 /* Reset related Registers */ 39 #define HNS3_GLOBAL_RESET_BIT 0 40 #define HNS3_CORE_RESET_BIT 1 41 #define HNS3_IMP_RESET_BIT 2 42 #define HNS3_FUN_RST_ING_B 0 43 44 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 46 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 48 49 #define HNS3_RESET_WAIT_MS 100 50 #define HNS3_RESET_WAIT_CNT 200 51 52 /* FEC mode order defined in HNS3 hardware */ 53 #define HNS3_HW_FEC_MODE_NOFEC 0 54 #define HNS3_HW_FEC_MODE_BASER 1 55 #define HNS3_HW_FEC_MODE_RS 2 56 57 enum hns3_evt_cause { 58 HNS3_VECTOR0_EVENT_RST, 59 HNS3_VECTOR0_EVENT_MBX, 60 HNS3_VECTOR0_EVENT_ERR, 61 HNS3_VECTOR0_EVENT_PTP, 62 HNS3_VECTOR0_EVENT_OTHER, 63 }; 64 65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { 66 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 67 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 68 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 69 70 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 71 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 72 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 73 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 74 75 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 76 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 77 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 78 79 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 80 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 81 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 82 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 83 84 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 85 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 86 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 87 88 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 89 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 90 RTE_ETH_FEC_MODE_CAPA_MASK(RS) } 91 }; 92 93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 94 uint64_t *levels); 95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 97 int on); 98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev); 99 static bool hns3_update_link_status(struct hns3_hw *hw); 100 101 static int hns3_add_mc_addr(struct hns3_hw *hw, 102 struct rte_ether_addr *mac_addr); 103 static int hns3_remove_mc_addr(struct hns3_hw *hw, 104 struct rte_ether_addr *mac_addr); 105 static int hns3_restore_fec(struct hns3_hw *hw); 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw); 107 static int hns3_do_stop(struct hns3_adapter *hns); 108 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds); 109 110 void hns3_ether_format_addr(char *buf, uint16_t size, 111 const struct rte_ether_addr *ether_addr) 112 { 113 snprintf(buf, size, "%02X:**:**:**:%02X:%02X", 114 ether_addr->addr_bytes[0], 115 ether_addr->addr_bytes[4], 116 ether_addr->addr_bytes[5]); 117 } 118 119 static void 120 hns3_pf_disable_irq0(struct hns3_hw *hw) 121 { 122 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 123 } 124 125 static void 126 hns3_pf_enable_irq0(struct hns3_hw *hw) 127 { 128 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 129 } 130 131 static enum hns3_evt_cause 132 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, 133 uint32_t *vec_val) 134 { 135 struct hns3_hw *hw = &hns->hw; 136 137 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 138 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 139 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 140 if (!is_delay) { 141 hw->reset.stats.imp_cnt++; 142 hns3_warn(hw, "IMP reset detected, clear reset status"); 143 } else { 144 hns3_schedule_delayed_reset(hns); 145 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 146 } 147 148 return HNS3_VECTOR0_EVENT_RST; 149 } 150 151 static enum hns3_evt_cause 152 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, 153 uint32_t *vec_val) 154 { 155 struct hns3_hw *hw = &hns->hw; 156 157 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 158 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 159 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 160 if (!is_delay) { 161 hw->reset.stats.global_cnt++; 162 hns3_warn(hw, "Global reset detected, clear reset status"); 163 } else { 164 hns3_schedule_delayed_reset(hns); 165 hns3_warn(hw, 166 "Global reset detected, don't clear reset status"); 167 } 168 169 return HNS3_VECTOR0_EVENT_RST; 170 } 171 172 static enum hns3_evt_cause 173 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 174 { 175 struct hns3_hw *hw = &hns->hw; 176 uint32_t vector0_int_stats; 177 uint32_t cmdq_src_val; 178 uint32_t hw_err_src_reg; 179 uint32_t val; 180 enum hns3_evt_cause ret; 181 bool is_delay; 182 183 /* fetch the events from their corresponding regs */ 184 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 185 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 186 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 187 188 is_delay = clearval == NULL ? true : false; 189 /* 190 * Assumption: If by any chance reset and mailbox events are reported 191 * together then we will only process reset event and defer the 192 * processing of the mailbox events. Since, we would have not cleared 193 * RX CMDQ event this time we would receive again another interrupt 194 * from H/W just for the mailbox. 195 */ 196 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 197 ret = hns3_proc_imp_reset_event(hns, is_delay, &val); 198 goto out; 199 } 200 201 /* Global reset */ 202 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 203 ret = hns3_proc_global_reset_event(hns, is_delay, &val); 204 goto out; 205 } 206 207 /* Check for vector0 1588 event source */ 208 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) { 209 val = BIT(HNS3_VECTOR0_1588_INT_B); 210 ret = HNS3_VECTOR0_EVENT_PTP; 211 goto out; 212 } 213 214 /* check for vector0 msix event source */ 215 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 216 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 217 val = vector0_int_stats | hw_err_src_reg; 218 ret = HNS3_VECTOR0_EVENT_ERR; 219 goto out; 220 } 221 222 /* check for vector0 mailbox(=CMDQ RX) event source */ 223 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 224 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 225 val = cmdq_src_val; 226 ret = HNS3_VECTOR0_EVENT_MBX; 227 goto out; 228 } 229 230 val = vector0_int_stats; 231 ret = HNS3_VECTOR0_EVENT_OTHER; 232 out: 233 234 if (clearval) 235 *clearval = val; 236 return ret; 237 } 238 239 static bool 240 hns3_is_1588_event_type(uint32_t event_type) 241 { 242 return (event_type == HNS3_VECTOR0_EVENT_PTP); 243 } 244 245 static void 246 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 247 { 248 if (event_type == HNS3_VECTOR0_EVENT_RST || 249 hns3_is_1588_event_type(event_type)) 250 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 251 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 252 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 253 } 254 255 static void 256 hns3_clear_all_event_cause(struct hns3_hw *hw) 257 { 258 uint32_t vector0_int_stats; 259 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 260 261 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 262 hns3_warn(hw, "Probe during IMP reset interrupt"); 263 264 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 265 hns3_warn(hw, "Probe during Global reset interrupt"); 266 267 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 268 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 269 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 270 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 271 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 272 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP, 273 BIT(HNS3_VECTOR0_1588_INT_B)); 274 } 275 276 static void 277 hns3_handle_mac_tnl(struct hns3_hw *hw) 278 { 279 struct hns3_cmd_desc desc; 280 uint32_t status; 281 int ret; 282 283 /* query and clear mac tnl interrupt */ 284 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true); 285 ret = hns3_cmd_send(hw, &desc, 1); 286 if (ret) { 287 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret); 288 return; 289 } 290 291 status = rte_le_to_cpu_32(desc.data[0]); 292 if (status) { 293 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status); 294 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT, 295 false); 296 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR); 297 ret = hns3_cmd_send(hw, &desc, 1); 298 if (ret) 299 hns3_err(hw, "failed to clear mac tnl int, ret = %d.", 300 ret); 301 } 302 } 303 304 static void 305 hns3_interrupt_handler(void *param) 306 { 307 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 308 struct hns3_adapter *hns = dev->data->dev_private; 309 struct hns3_hw *hw = &hns->hw; 310 enum hns3_evt_cause event_cause; 311 uint32_t clearval = 0; 312 uint32_t vector0_int; 313 uint32_t ras_int; 314 uint32_t cmdq_int; 315 316 /* Disable interrupt */ 317 hns3_pf_disable_irq0(hw); 318 319 event_cause = hns3_check_event_cause(hns, &clearval); 320 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 321 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 322 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 323 /* vector 0 interrupt is shared with reset and mailbox source events. */ 324 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 325 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " 326 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 327 vector0_int, ras_int, cmdq_int); 328 hns3_handle_mac_tnl(hw); 329 hns3_handle_error(hns); 330 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 331 hns3_warn(hw, "received reset interrupt"); 332 hns3_schedule_reset(hns); 333 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) { 334 hns3_dev_handle_mbx_msg(hw); 335 } else { 336 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x " 337 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 338 vector0_int, ras_int, cmdq_int); 339 } 340 341 hns3_clear_event_cause(hw, event_cause, clearval); 342 /* Enable interrupt if it is not cause by reset */ 343 hns3_pf_enable_irq0(hw); 344 } 345 346 static int 347 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 348 { 349 #define HNS3_VLAN_ID_OFFSET_STEP 160 350 #define HNS3_VLAN_BYTE_SIZE 8 351 struct hns3_vlan_filter_pf_cfg_cmd *req; 352 struct hns3_hw *hw = &hns->hw; 353 uint8_t vlan_offset_byte_val; 354 struct hns3_cmd_desc desc; 355 uint8_t vlan_offset_byte; 356 uint8_t vlan_offset_base; 357 int ret; 358 359 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 360 361 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 362 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 363 HNS3_VLAN_BYTE_SIZE; 364 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 365 366 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 367 req->vlan_offset = vlan_offset_base; 368 req->vlan_cfg = on ? 0 : 1; 369 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 370 371 ret = hns3_cmd_send(hw, &desc, 1); 372 if (ret) 373 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 374 vlan_id, ret); 375 376 return ret; 377 } 378 379 static void 380 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 381 { 382 struct hns3_user_vlan_table *vlan_entry; 383 struct hns3_pf *pf = &hns->pf; 384 385 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 386 if (vlan_entry->vlan_id == vlan_id) { 387 if (vlan_entry->hd_tbl_status) 388 hns3_set_port_vlan_filter(hns, vlan_id, 0); 389 LIST_REMOVE(vlan_entry, next); 390 rte_free(vlan_entry); 391 break; 392 } 393 } 394 } 395 396 static void 397 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 398 bool writen_to_tbl) 399 { 400 struct hns3_user_vlan_table *vlan_entry; 401 struct hns3_hw *hw = &hns->hw; 402 struct hns3_pf *pf = &hns->pf; 403 404 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 405 if (vlan_entry->vlan_id == vlan_id) 406 return; 407 } 408 409 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 410 if (vlan_entry == NULL) { 411 hns3_err(hw, "Failed to malloc hns3 vlan table"); 412 return; 413 } 414 415 vlan_entry->hd_tbl_status = writen_to_tbl; 416 vlan_entry->vlan_id = vlan_id; 417 418 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 419 } 420 421 static int 422 hns3_restore_vlan_table(struct hns3_adapter *hns) 423 { 424 struct hns3_user_vlan_table *vlan_entry; 425 struct hns3_hw *hw = &hns->hw; 426 struct hns3_pf *pf = &hns->pf; 427 uint16_t vlan_id; 428 int ret = 0; 429 430 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 431 return hns3_vlan_pvid_configure(hns, 432 hw->port_base_vlan_cfg.pvid, 1); 433 434 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 435 if (vlan_entry->hd_tbl_status) { 436 vlan_id = vlan_entry->vlan_id; 437 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 438 if (ret) 439 break; 440 } 441 } 442 443 return ret; 444 } 445 446 static int 447 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 448 { 449 struct hns3_hw *hw = &hns->hw; 450 bool writen_to_tbl = false; 451 int ret = 0; 452 453 /* 454 * When vlan filter is enabled, hardware regards packets without vlan 455 * as packets with vlan 0. So, to receive packets without vlan, vlan id 456 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter. 457 */ 458 if (on == 0 && vlan_id == 0) 459 return 0; 460 461 /* 462 * When port base vlan enabled, we use port base vlan as the vlan 463 * filter condition. In this case, we don't update vlan filter table 464 * when user add new vlan or remove exist vlan, just update the 465 * vlan list. The vlan id in vlan list will be written in vlan filter 466 * table until port base vlan disabled 467 */ 468 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 469 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 470 writen_to_tbl = true; 471 } 472 473 if (ret == 0) { 474 if (on) 475 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 476 else 477 hns3_rm_dev_vlan_table(hns, vlan_id); 478 } 479 return ret; 480 } 481 482 static int 483 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 484 { 485 struct hns3_adapter *hns = dev->data->dev_private; 486 struct hns3_hw *hw = &hns->hw; 487 int ret; 488 489 rte_spinlock_lock(&hw->lock); 490 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 491 rte_spinlock_unlock(&hw->lock); 492 return ret; 493 } 494 495 static int 496 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 497 uint16_t tpid) 498 { 499 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 500 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 501 struct hns3_hw *hw = &hns->hw; 502 struct hns3_cmd_desc desc; 503 int ret; 504 505 if ((vlan_type != ETH_VLAN_TYPE_INNER && 506 vlan_type != ETH_VLAN_TYPE_OUTER)) { 507 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 508 return -EINVAL; 509 } 510 511 if (tpid != RTE_ETHER_TYPE_VLAN) { 512 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 513 return -EINVAL; 514 } 515 516 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 517 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 518 519 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 520 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 521 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 522 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 523 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 524 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 525 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 526 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 527 } 528 529 ret = hns3_cmd_send(hw, &desc, 1); 530 if (ret) { 531 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 532 ret); 533 return ret; 534 } 535 536 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 537 538 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 539 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 540 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 541 542 ret = hns3_cmd_send(hw, &desc, 1); 543 if (ret) 544 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 545 ret); 546 return ret; 547 } 548 549 static int 550 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 551 uint16_t tpid) 552 { 553 struct hns3_adapter *hns = dev->data->dev_private; 554 struct hns3_hw *hw = &hns->hw; 555 int ret; 556 557 rte_spinlock_lock(&hw->lock); 558 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 559 rte_spinlock_unlock(&hw->lock); 560 return ret; 561 } 562 563 static int 564 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 565 struct hns3_rx_vtag_cfg *vcfg) 566 { 567 struct hns3_vport_vtag_rx_cfg_cmd *req; 568 struct hns3_hw *hw = &hns->hw; 569 struct hns3_cmd_desc desc; 570 uint16_t vport_id; 571 uint8_t bitmap; 572 int ret; 573 574 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 575 576 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 577 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 578 vcfg->strip_tag1_en ? 1 : 0); 579 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 580 vcfg->strip_tag2_en ? 1 : 0); 581 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 582 vcfg->vlan1_vlan_prionly ? 1 : 0); 583 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 584 vcfg->vlan2_vlan_prionly ? 1 : 0); 585 586 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 587 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B, 588 vcfg->strip_tag1_discard_en ? 1 : 0); 589 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B, 590 vcfg->strip_tag2_discard_en ? 1 : 0); 591 /* 592 * In current version VF is not supported when PF is driven by DPDK 593 * driver, just need to configure parameters for PF vport. 594 */ 595 vport_id = HNS3_PF_FUNC_ID; 596 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 597 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 598 req->vf_bitmap[req->vf_offset] = bitmap; 599 600 ret = hns3_cmd_send(hw, &desc, 1); 601 if (ret) 602 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 603 return ret; 604 } 605 606 static void 607 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 608 struct hns3_rx_vtag_cfg *vcfg) 609 { 610 struct hns3_pf *pf = &hns->pf; 611 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 612 } 613 614 static void 615 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 616 struct hns3_tx_vtag_cfg *vcfg) 617 { 618 struct hns3_pf *pf = &hns->pf; 619 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 620 } 621 622 static int 623 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 624 { 625 struct hns3_rx_vtag_cfg rxvlan_cfg; 626 struct hns3_hw *hw = &hns->hw; 627 int ret; 628 629 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 630 rxvlan_cfg.strip_tag1_en = false; 631 rxvlan_cfg.strip_tag2_en = enable; 632 rxvlan_cfg.strip_tag2_discard_en = false; 633 } else { 634 rxvlan_cfg.strip_tag1_en = enable; 635 rxvlan_cfg.strip_tag2_en = true; 636 rxvlan_cfg.strip_tag2_discard_en = true; 637 } 638 639 rxvlan_cfg.strip_tag1_discard_en = false; 640 rxvlan_cfg.vlan1_vlan_prionly = false; 641 rxvlan_cfg.vlan2_vlan_prionly = false; 642 rxvlan_cfg.rx_vlan_offload_en = enable; 643 644 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 645 if (ret) { 646 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret); 647 return ret; 648 } 649 650 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 651 652 return ret; 653 } 654 655 static int 656 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 657 uint8_t fe_type, bool filter_en, uint8_t vf_id) 658 { 659 struct hns3_vlan_filter_ctrl_cmd *req; 660 struct hns3_cmd_desc desc; 661 int ret; 662 663 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 664 665 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 666 req->vlan_type = vlan_type; 667 req->vlan_fe = filter_en ? fe_type : 0; 668 req->vf_id = vf_id; 669 670 ret = hns3_cmd_send(hw, &desc, 1); 671 if (ret) 672 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 673 674 return ret; 675 } 676 677 static int 678 hns3_vlan_filter_init(struct hns3_adapter *hns) 679 { 680 struct hns3_hw *hw = &hns->hw; 681 int ret; 682 683 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 684 HNS3_FILTER_FE_EGRESS, false, 685 HNS3_PF_FUNC_ID); 686 if (ret) { 687 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 688 return ret; 689 } 690 691 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 692 HNS3_FILTER_FE_INGRESS, false, 693 HNS3_PF_FUNC_ID); 694 if (ret) 695 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 696 697 return ret; 698 } 699 700 static int 701 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 702 { 703 struct hns3_hw *hw = &hns->hw; 704 int ret; 705 706 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 707 HNS3_FILTER_FE_INGRESS, enable, 708 HNS3_PF_FUNC_ID); 709 if (ret) 710 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 711 enable ? "enable" : "disable", ret); 712 713 return ret; 714 } 715 716 static int 717 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 718 { 719 struct hns3_adapter *hns = dev->data->dev_private; 720 struct hns3_hw *hw = &hns->hw; 721 struct rte_eth_rxmode *rxmode; 722 unsigned int tmp_mask; 723 bool enable; 724 int ret = 0; 725 726 rte_spinlock_lock(&hw->lock); 727 rxmode = &dev->data->dev_conf.rxmode; 728 tmp_mask = (unsigned int)mask; 729 if (tmp_mask & ETH_VLAN_FILTER_MASK) { 730 /* ignore vlan filter configuration during promiscuous mode */ 731 if (!dev->data->promiscuous) { 732 /* Enable or disable VLAN filter */ 733 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? 734 true : false; 735 736 ret = hns3_enable_vlan_filter(hns, enable); 737 if (ret) { 738 rte_spinlock_unlock(&hw->lock); 739 hns3_err(hw, "failed to %s rx filter, ret = %d", 740 enable ? "enable" : "disable", ret); 741 return ret; 742 } 743 } 744 } 745 746 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 747 /* Enable or disable VLAN stripping */ 748 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 749 true : false; 750 751 ret = hns3_en_hw_strip_rxvtag(hns, enable); 752 if (ret) { 753 rte_spinlock_unlock(&hw->lock); 754 hns3_err(hw, "failed to %s rx strip, ret = %d", 755 enable ? "enable" : "disable", ret); 756 return ret; 757 } 758 } 759 760 rte_spinlock_unlock(&hw->lock); 761 762 return ret; 763 } 764 765 static int 766 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 767 struct hns3_tx_vtag_cfg *vcfg) 768 { 769 struct hns3_vport_vtag_tx_cfg_cmd *req; 770 struct hns3_cmd_desc desc; 771 struct hns3_hw *hw = &hns->hw; 772 uint16_t vport_id; 773 uint8_t bitmap; 774 int ret; 775 776 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 777 778 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 779 req->def_vlan_tag1 = vcfg->default_tag1; 780 req->def_vlan_tag2 = vcfg->default_tag2; 781 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 782 vcfg->accept_tag1 ? 1 : 0); 783 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 784 vcfg->accept_untag1 ? 1 : 0); 785 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 786 vcfg->accept_tag2 ? 1 : 0); 787 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 788 vcfg->accept_untag2 ? 1 : 0); 789 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 790 vcfg->insert_tag1_en ? 1 : 0); 791 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 792 vcfg->insert_tag2_en ? 1 : 0); 793 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 794 795 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 796 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B, 797 vcfg->tag_shift_mode_en ? 1 : 0); 798 799 /* 800 * In current version VF is not supported when PF is driven by DPDK 801 * driver, just need to configure parameters for PF vport. 802 */ 803 vport_id = HNS3_PF_FUNC_ID; 804 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 805 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 806 req->vf_bitmap[req->vf_offset] = bitmap; 807 808 ret = hns3_cmd_send(hw, &desc, 1); 809 if (ret) 810 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 811 812 return ret; 813 } 814 815 static int 816 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 817 uint16_t pvid) 818 { 819 struct hns3_hw *hw = &hns->hw; 820 struct hns3_tx_vtag_cfg txvlan_cfg; 821 int ret; 822 823 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 824 txvlan_cfg.accept_tag1 = true; 825 txvlan_cfg.insert_tag1_en = false; 826 txvlan_cfg.default_tag1 = 0; 827 } else { 828 txvlan_cfg.accept_tag1 = 829 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE; 830 txvlan_cfg.insert_tag1_en = true; 831 txvlan_cfg.default_tag1 = pvid; 832 } 833 834 txvlan_cfg.accept_untag1 = true; 835 txvlan_cfg.accept_tag2 = true; 836 txvlan_cfg.accept_untag2 = true; 837 txvlan_cfg.insert_tag2_en = false; 838 txvlan_cfg.default_tag2 = 0; 839 txvlan_cfg.tag_shift_mode_en = true; 840 841 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 842 if (ret) { 843 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 844 ret); 845 return ret; 846 } 847 848 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 849 return ret; 850 } 851 852 853 static void 854 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 855 { 856 struct hns3_user_vlan_table *vlan_entry; 857 struct hns3_pf *pf = &hns->pf; 858 859 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 860 if (vlan_entry->hd_tbl_status) { 861 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 862 vlan_entry->hd_tbl_status = false; 863 } 864 } 865 866 if (is_del_list) { 867 vlan_entry = LIST_FIRST(&pf->vlan_list); 868 while (vlan_entry) { 869 LIST_REMOVE(vlan_entry, next); 870 rte_free(vlan_entry); 871 vlan_entry = LIST_FIRST(&pf->vlan_list); 872 } 873 } 874 } 875 876 static void 877 hns3_add_all_vlan_table(struct hns3_adapter *hns) 878 { 879 struct hns3_user_vlan_table *vlan_entry; 880 struct hns3_pf *pf = &hns->pf; 881 882 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 883 if (!vlan_entry->hd_tbl_status) { 884 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 885 vlan_entry->hd_tbl_status = true; 886 } 887 } 888 } 889 890 static void 891 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 892 { 893 struct hns3_hw *hw = &hns->hw; 894 int ret; 895 896 hns3_rm_all_vlan_table(hns, true); 897 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) { 898 ret = hns3_set_port_vlan_filter(hns, 899 hw->port_base_vlan_cfg.pvid, 0); 900 if (ret) { 901 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 902 ret); 903 return; 904 } 905 } 906 } 907 908 static int 909 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 910 uint16_t port_base_vlan_state, uint16_t new_pvid) 911 { 912 struct hns3_hw *hw = &hns->hw; 913 uint16_t old_pvid; 914 int ret; 915 916 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 917 old_pvid = hw->port_base_vlan_cfg.pvid; 918 if (old_pvid != HNS3_INVALID_PVID) { 919 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 920 if (ret) { 921 hns3_err(hw, "failed to remove old pvid %u, " 922 "ret = %d", old_pvid, ret); 923 return ret; 924 } 925 } 926 927 hns3_rm_all_vlan_table(hns, false); 928 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1); 929 if (ret) { 930 hns3_err(hw, "failed to add new pvid %u, ret = %d", 931 new_pvid, ret); 932 return ret; 933 } 934 } else { 935 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 936 if (ret) { 937 hns3_err(hw, "failed to remove pvid %u, ret = %d", 938 new_pvid, ret); 939 return ret; 940 } 941 942 hns3_add_all_vlan_table(hns); 943 } 944 return 0; 945 } 946 947 static int 948 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 949 { 950 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 951 struct hns3_rx_vtag_cfg rx_vlan_cfg; 952 bool rx_strip_en; 953 int ret; 954 955 rx_strip_en = old_cfg->rx_vlan_offload_en; 956 if (on) { 957 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 958 rx_vlan_cfg.strip_tag2_en = true; 959 rx_vlan_cfg.strip_tag2_discard_en = true; 960 } else { 961 rx_vlan_cfg.strip_tag1_en = false; 962 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 963 rx_vlan_cfg.strip_tag2_discard_en = false; 964 } 965 rx_vlan_cfg.strip_tag1_discard_en = false; 966 rx_vlan_cfg.vlan1_vlan_prionly = false; 967 rx_vlan_cfg.vlan2_vlan_prionly = false; 968 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 969 970 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 971 if (ret) 972 return ret; 973 974 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 975 return ret; 976 } 977 978 static int 979 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 980 { 981 struct hns3_hw *hw = &hns->hw; 982 uint16_t port_base_vlan_state; 983 int ret, err; 984 985 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 986 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) 987 hns3_warn(hw, "Invalid operation! As current pvid set " 988 "is %u, disable pvid %u is invalid", 989 hw->port_base_vlan_cfg.pvid, pvid); 990 return 0; 991 } 992 993 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 994 HNS3_PORT_BASE_VLAN_DISABLE; 995 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 996 if (ret) { 997 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 998 ret); 999 return ret; 1000 } 1001 1002 ret = hns3_en_pvid_strip(hns, on); 1003 if (ret) { 1004 hns3_err(hw, "failed to config rx vlan strip for pvid, " 1005 "ret = %d", ret); 1006 goto pvid_vlan_strip_fail; 1007 } 1008 1009 if (pvid == HNS3_INVALID_PVID) 1010 goto out; 1011 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid); 1012 if (ret) { 1013 hns3_err(hw, "failed to update vlan filter entries, ret = %d", 1014 ret); 1015 goto vlan_filter_set_fail; 1016 } 1017 1018 out: 1019 hw->port_base_vlan_cfg.state = port_base_vlan_state; 1020 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID; 1021 return ret; 1022 1023 vlan_filter_set_fail: 1024 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state == 1025 HNS3_PORT_BASE_VLAN_ENABLE); 1026 if (err) 1027 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err); 1028 1029 pvid_vlan_strip_fail: 1030 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state, 1031 hw->port_base_vlan_cfg.pvid); 1032 if (err) 1033 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err); 1034 1035 return ret; 1036 } 1037 1038 static int 1039 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 1040 { 1041 struct hns3_adapter *hns = dev->data->dev_private; 1042 struct hns3_hw *hw = &hns->hw; 1043 bool pvid_en_state_change; 1044 uint16_t pvid_state; 1045 int ret; 1046 1047 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 1048 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 1049 RTE_ETHER_MAX_VLAN_ID); 1050 return -EINVAL; 1051 } 1052 1053 /* 1054 * If PVID configuration state change, should refresh the PVID 1055 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 1056 */ 1057 pvid_state = hw->port_base_vlan_cfg.state; 1058 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 1059 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 1060 pvid_en_state_change = false; 1061 else 1062 pvid_en_state_change = true; 1063 1064 rte_spinlock_lock(&hw->lock); 1065 ret = hns3_vlan_pvid_configure(hns, pvid, on); 1066 rte_spinlock_unlock(&hw->lock); 1067 if (ret) 1068 return ret; 1069 /* 1070 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx 1071 * need be processed by PMD driver. 1072 */ 1073 if (pvid_en_state_change && 1074 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 1075 hns3_update_all_queues_pvid_proc_en(hw); 1076 1077 return 0; 1078 } 1079 1080 static int 1081 hns3_default_vlan_config(struct hns3_adapter *hns) 1082 { 1083 struct hns3_hw *hw = &hns->hw; 1084 int ret; 1085 1086 /* 1087 * When vlan filter is enabled, hardware regards packets without vlan 1088 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan 1089 * table, packets without vlan won't be received. So, add vlan 0 as 1090 * the default vlan. 1091 */ 1092 ret = hns3_vlan_filter_configure(hns, 0, 1); 1093 if (ret) 1094 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 1095 return ret; 1096 } 1097 1098 static int 1099 hns3_init_vlan_config(struct hns3_adapter *hns) 1100 { 1101 struct hns3_hw *hw = &hns->hw; 1102 int ret; 1103 1104 /* 1105 * This function can be called in the initialization and reset process, 1106 * when in reset process, it means that hardware had been reseted 1107 * successfully and we need to restore the hardware configuration to 1108 * ensure that the hardware configuration remains unchanged before and 1109 * after reset. 1110 */ 1111 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1112 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 1113 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID; 1114 } 1115 1116 ret = hns3_vlan_filter_init(hns); 1117 if (ret) { 1118 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 1119 return ret; 1120 } 1121 1122 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 1123 RTE_ETHER_TYPE_VLAN); 1124 if (ret) { 1125 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 1126 return ret; 1127 } 1128 1129 /* 1130 * When in the reinit dev stage of the reset process, the following 1131 * vlan-related configurations may differ from those at initialization, 1132 * we will restore configurations to hardware in hns3_restore_vlan_table 1133 * and hns3_restore_vlan_conf later. 1134 */ 1135 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1136 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0); 1137 if (ret) { 1138 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1139 return ret; 1140 } 1141 1142 ret = hns3_en_hw_strip_rxvtag(hns, false); 1143 if (ret) { 1144 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1145 ret); 1146 return ret; 1147 } 1148 } 1149 1150 return hns3_default_vlan_config(hns); 1151 } 1152 1153 static int 1154 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1155 { 1156 struct hns3_pf *pf = &hns->pf; 1157 struct hns3_hw *hw = &hns->hw; 1158 uint64_t offloads; 1159 bool enable; 1160 int ret; 1161 1162 if (!hw->data->promiscuous) { 1163 /* restore vlan filter states */ 1164 offloads = hw->data->dev_conf.rxmode.offloads; 1165 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false; 1166 ret = hns3_enable_vlan_filter(hns, enable); 1167 if (ret) { 1168 hns3_err(hw, "failed to restore vlan rx filter conf, " 1169 "ret = %d", ret); 1170 return ret; 1171 } 1172 } 1173 1174 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1175 if (ret) { 1176 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1177 return ret; 1178 } 1179 1180 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1181 if (ret) 1182 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1183 1184 return ret; 1185 } 1186 1187 static int 1188 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1189 { 1190 struct hns3_adapter *hns = dev->data->dev_private; 1191 struct rte_eth_dev_data *data = dev->data; 1192 struct rte_eth_txmode *txmode; 1193 struct hns3_hw *hw = &hns->hw; 1194 int mask; 1195 int ret; 1196 1197 txmode = &data->dev_conf.txmode; 1198 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1199 hns3_warn(hw, 1200 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1201 "configuration is not supported! Ignore these two " 1202 "parameters: hw_vlan_reject_tagged(%u), " 1203 "hw_vlan_reject_untagged(%u)", 1204 txmode->hw_vlan_reject_tagged, 1205 txmode->hw_vlan_reject_untagged); 1206 1207 /* Apply vlan offload setting */ 1208 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK; 1209 ret = hns3_vlan_offload_set(dev, mask); 1210 if (ret) { 1211 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1212 ret); 1213 return ret; 1214 } 1215 1216 /* 1217 * If pvid config is not set in rte_eth_conf, driver needn't to set 1218 * VLAN pvid related configuration to hardware. 1219 */ 1220 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1221 return 0; 1222 1223 /* Apply pvid setting */ 1224 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1225 txmode->hw_vlan_insert_pvid); 1226 if (ret) 1227 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d", 1228 txmode->pvid, ret); 1229 1230 return ret; 1231 } 1232 1233 static int 1234 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1235 unsigned int tso_mss_max) 1236 { 1237 struct hns3_cfg_tso_status_cmd *req; 1238 struct hns3_cmd_desc desc; 1239 uint16_t tso_mss; 1240 1241 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1242 1243 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1244 1245 tso_mss = 0; 1246 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1247 tso_mss_min); 1248 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1249 1250 tso_mss = 0; 1251 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1252 tso_mss_max); 1253 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1254 1255 return hns3_cmd_send(hw, &desc, 1); 1256 } 1257 1258 static int 1259 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1260 uint16_t *allocated_size, bool is_alloc) 1261 { 1262 struct hns3_umv_spc_alc_cmd *req; 1263 struct hns3_cmd_desc desc; 1264 int ret; 1265 1266 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1267 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1268 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1269 req->space_size = rte_cpu_to_le_32(space_size); 1270 1271 ret = hns3_cmd_send(hw, &desc, 1); 1272 if (ret) { 1273 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1274 is_alloc ? "allocate" : "free", ret); 1275 return ret; 1276 } 1277 1278 if (is_alloc && allocated_size) 1279 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1280 1281 return 0; 1282 } 1283 1284 static int 1285 hns3_init_umv_space(struct hns3_hw *hw) 1286 { 1287 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1288 struct hns3_pf *pf = &hns->pf; 1289 uint16_t allocated_size = 0; 1290 int ret; 1291 1292 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1293 true); 1294 if (ret) 1295 return ret; 1296 1297 if (allocated_size < pf->wanted_umv_size) 1298 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1299 pf->wanted_umv_size, allocated_size); 1300 1301 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1302 pf->wanted_umv_size; 1303 pf->used_umv_size = 0; 1304 return 0; 1305 } 1306 1307 static int 1308 hns3_uninit_umv_space(struct hns3_hw *hw) 1309 { 1310 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1311 struct hns3_pf *pf = &hns->pf; 1312 int ret; 1313 1314 if (pf->max_umv_size == 0) 1315 return 0; 1316 1317 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1318 if (ret) 1319 return ret; 1320 1321 pf->max_umv_size = 0; 1322 1323 return 0; 1324 } 1325 1326 static bool 1327 hns3_is_umv_space_full(struct hns3_hw *hw) 1328 { 1329 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1330 struct hns3_pf *pf = &hns->pf; 1331 bool is_full; 1332 1333 is_full = (pf->used_umv_size >= pf->max_umv_size); 1334 1335 return is_full; 1336 } 1337 1338 static void 1339 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1340 { 1341 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1342 struct hns3_pf *pf = &hns->pf; 1343 1344 if (is_free) { 1345 if (pf->used_umv_size > 0) 1346 pf->used_umv_size--; 1347 } else 1348 pf->used_umv_size++; 1349 } 1350 1351 static void 1352 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1353 const uint8_t *addr, bool is_mc) 1354 { 1355 const unsigned char *mac_addr = addr; 1356 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1357 ((uint32_t)mac_addr[2] << 16) | 1358 ((uint32_t)mac_addr[1] << 8) | 1359 (uint32_t)mac_addr[0]; 1360 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1361 1362 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1363 if (is_mc) { 1364 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1365 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1366 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1367 } 1368 1369 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1370 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1371 } 1372 1373 static int 1374 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1375 uint8_t resp_code, 1376 enum hns3_mac_vlan_tbl_opcode op) 1377 { 1378 if (cmdq_resp) { 1379 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1380 cmdq_resp); 1381 return -EIO; 1382 } 1383 1384 if (op == HNS3_MAC_VLAN_ADD) { 1385 if (resp_code == 0 || resp_code == 1) { 1386 return 0; 1387 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1388 hns3_err(hw, "add mac addr failed for uc_overflow"); 1389 return -ENOSPC; 1390 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1391 hns3_err(hw, "add mac addr failed for mc_overflow"); 1392 return -ENOSPC; 1393 } 1394 1395 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1396 resp_code); 1397 return -EIO; 1398 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1399 if (resp_code == 0) { 1400 return 0; 1401 } else if (resp_code == 1) { 1402 hns3_dbg(hw, "remove mac addr failed for miss"); 1403 return -ENOENT; 1404 } 1405 1406 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1407 resp_code); 1408 return -EIO; 1409 } else if (op == HNS3_MAC_VLAN_LKUP) { 1410 if (resp_code == 0) { 1411 return 0; 1412 } else if (resp_code == 1) { 1413 hns3_dbg(hw, "lookup mac addr failed for miss"); 1414 return -ENOENT; 1415 } 1416 1417 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1418 resp_code); 1419 return -EIO; 1420 } 1421 1422 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1423 op); 1424 1425 return -EINVAL; 1426 } 1427 1428 static int 1429 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1430 struct hns3_mac_vlan_tbl_entry_cmd *req, 1431 struct hns3_cmd_desc *desc, bool is_mc) 1432 { 1433 uint8_t resp_code; 1434 uint16_t retval; 1435 int ret; 1436 1437 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true); 1438 if (is_mc) { 1439 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1440 memcpy(desc[0].data, req, 1441 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1442 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD, 1443 true); 1444 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1445 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD, 1446 true); 1447 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1448 } else { 1449 memcpy(desc[0].data, req, 1450 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1451 ret = hns3_cmd_send(hw, desc, 1); 1452 } 1453 if (ret) { 1454 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1455 ret); 1456 return ret; 1457 } 1458 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1459 retval = rte_le_to_cpu_16(desc[0].retval); 1460 1461 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1462 HNS3_MAC_VLAN_LKUP); 1463 } 1464 1465 static int 1466 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1467 struct hns3_mac_vlan_tbl_entry_cmd *req, 1468 struct hns3_cmd_desc *mc_desc) 1469 { 1470 uint8_t resp_code; 1471 uint16_t retval; 1472 int cfg_status; 1473 int ret; 1474 1475 if (mc_desc == NULL) { 1476 struct hns3_cmd_desc desc; 1477 1478 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false); 1479 memcpy(desc.data, req, 1480 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1481 ret = hns3_cmd_send(hw, &desc, 1); 1482 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1483 retval = rte_le_to_cpu_16(desc.retval); 1484 1485 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1486 HNS3_MAC_VLAN_ADD); 1487 } else { 1488 hns3_cmd_reuse_desc(&mc_desc[0], false); 1489 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1490 hns3_cmd_reuse_desc(&mc_desc[1], false); 1491 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1492 hns3_cmd_reuse_desc(&mc_desc[2], false); 1493 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1494 memcpy(mc_desc[0].data, req, 1495 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1496 mc_desc[0].retval = 0; 1497 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1498 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff; 1499 retval = rte_le_to_cpu_16(mc_desc[0].retval); 1500 1501 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1502 HNS3_MAC_VLAN_ADD); 1503 } 1504 1505 if (ret) { 1506 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1507 return ret; 1508 } 1509 1510 return cfg_status; 1511 } 1512 1513 static int 1514 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1515 struct hns3_mac_vlan_tbl_entry_cmd *req) 1516 { 1517 struct hns3_cmd_desc desc; 1518 uint8_t resp_code; 1519 uint16_t retval; 1520 int ret; 1521 1522 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1523 1524 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1525 1526 ret = hns3_cmd_send(hw, &desc, 1); 1527 if (ret) { 1528 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1529 return ret; 1530 } 1531 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1532 retval = rte_le_to_cpu_16(desc.retval); 1533 1534 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1535 HNS3_MAC_VLAN_REMOVE); 1536 } 1537 1538 static int 1539 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1540 { 1541 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1542 struct hns3_mac_vlan_tbl_entry_cmd req; 1543 struct hns3_pf *pf = &hns->pf; 1544 struct hns3_cmd_desc desc[3]; 1545 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1546 uint16_t egress_port = 0; 1547 uint8_t vf_id; 1548 int ret; 1549 1550 /* check if mac addr is valid */ 1551 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1552 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1553 mac_addr); 1554 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1555 mac_str); 1556 return -EINVAL; 1557 } 1558 1559 memset(&req, 0, sizeof(req)); 1560 1561 /* 1562 * In current version VF is not supported when PF is driven by DPDK 1563 * driver, just need to configure parameters for PF vport. 1564 */ 1565 vf_id = HNS3_PF_FUNC_ID; 1566 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1567 HNS3_MAC_EPORT_VFID_S, vf_id); 1568 1569 req.egress_port = rte_cpu_to_le_16(egress_port); 1570 1571 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1572 1573 /* 1574 * Lookup the mac address in the mac_vlan table, and add 1575 * it if the entry is inexistent. Repeated unicast entry 1576 * is not allowed in the mac vlan table. 1577 */ 1578 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false); 1579 if (ret == -ENOENT) { 1580 if (!hns3_is_umv_space_full(hw)) { 1581 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); 1582 if (!ret) 1583 hns3_update_umv_space(hw, false); 1584 return ret; 1585 } 1586 1587 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1588 1589 return -ENOSPC; 1590 } 1591 1592 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1593 1594 /* check if we just hit the duplicate */ 1595 if (ret == 0) { 1596 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1597 return 0; 1598 } 1599 1600 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1601 mac_str); 1602 1603 return ret; 1604 } 1605 1606 static int 1607 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1608 { 1609 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1610 struct rte_ether_addr *addr; 1611 int ret; 1612 int i; 1613 1614 for (i = 0; i < hw->mc_addrs_num; i++) { 1615 addr = &hw->mc_addrs[i]; 1616 /* Check if there are duplicate addresses */ 1617 if (rte_is_same_ether_addr(addr, mac_addr)) { 1618 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1619 addr); 1620 hns3_err(hw, "failed to add mc mac addr, same addrs" 1621 "(%s) is added by the set_mc_mac_addr_list " 1622 "API", mac_str); 1623 return -EINVAL; 1624 } 1625 } 1626 1627 ret = hns3_add_mc_addr(hw, mac_addr); 1628 if (ret) { 1629 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1630 mac_addr); 1631 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 1632 mac_str, ret); 1633 } 1634 return ret; 1635 } 1636 1637 static int 1638 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1639 { 1640 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1641 int ret; 1642 1643 ret = hns3_remove_mc_addr(hw, mac_addr); 1644 if (ret) { 1645 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1646 mac_addr); 1647 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d", 1648 mac_str, ret); 1649 } 1650 return ret; 1651 } 1652 1653 static int 1654 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1655 uint32_t idx, __rte_unused uint32_t pool) 1656 { 1657 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1658 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1659 int ret; 1660 1661 rte_spinlock_lock(&hw->lock); 1662 1663 /* 1664 * In hns3 network engine adding UC and MC mac address with different 1665 * commands with firmware. We need to determine whether the input 1666 * address is a UC or a MC address to call different commands. 1667 * By the way, it is recommended calling the API function named 1668 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 1669 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 1670 * may affect the specifications of UC mac addresses. 1671 */ 1672 if (rte_is_multicast_ether_addr(mac_addr)) 1673 ret = hns3_add_mc_addr_common(hw, mac_addr); 1674 else 1675 ret = hns3_add_uc_addr_common(hw, mac_addr); 1676 1677 if (ret) { 1678 rte_spinlock_unlock(&hw->lock); 1679 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1680 mac_addr); 1681 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 1682 ret); 1683 return ret; 1684 } 1685 1686 if (idx == 0) 1687 hw->mac.default_addr_setted = true; 1688 rte_spinlock_unlock(&hw->lock); 1689 1690 return ret; 1691 } 1692 1693 static int 1694 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1695 { 1696 struct hns3_mac_vlan_tbl_entry_cmd req; 1697 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1698 int ret; 1699 1700 /* check if mac addr is valid */ 1701 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1702 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1703 mac_addr); 1704 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1705 mac_str); 1706 return -EINVAL; 1707 } 1708 1709 memset(&req, 0, sizeof(req)); 1710 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1711 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1712 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1713 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1714 return 0; 1715 else if (ret == 0) 1716 hns3_update_umv_space(hw, true); 1717 1718 return ret; 1719 } 1720 1721 static void 1722 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1723 { 1724 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1725 /* index will be checked by upper level rte interface */ 1726 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1727 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1728 int ret; 1729 1730 rte_spinlock_lock(&hw->lock); 1731 1732 if (rte_is_multicast_ether_addr(mac_addr)) 1733 ret = hns3_remove_mc_addr_common(hw, mac_addr); 1734 else 1735 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1736 rte_spinlock_unlock(&hw->lock); 1737 if (ret) { 1738 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1739 mac_addr); 1740 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, 1741 ret); 1742 } 1743 } 1744 1745 static int 1746 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1747 struct rte_ether_addr *mac_addr) 1748 { 1749 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1750 struct rte_ether_addr *oaddr; 1751 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1752 bool default_addr_setted; 1753 bool rm_succes = false; 1754 int ret, ret_val; 1755 1756 /* 1757 * It has been guaranteed that input parameter named mac_addr is valid 1758 * address in the rte layer of DPDK framework. 1759 */ 1760 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1761 default_addr_setted = hw->mac.default_addr_setted; 1762 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr)) 1763 return 0; 1764 1765 rte_spinlock_lock(&hw->lock); 1766 if (default_addr_setted) { 1767 ret = hns3_remove_uc_addr_common(hw, oaddr); 1768 if (ret) { 1769 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1770 oaddr); 1771 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1772 mac_str, ret); 1773 rm_succes = false; 1774 } else 1775 rm_succes = true; 1776 } 1777 1778 ret = hns3_add_uc_addr_common(hw, mac_addr); 1779 if (ret) { 1780 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1781 mac_addr); 1782 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1783 goto err_add_uc_addr; 1784 } 1785 1786 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1787 if (ret) { 1788 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1789 goto err_pause_addr_cfg; 1790 } 1791 1792 rte_ether_addr_copy(mac_addr, 1793 (struct rte_ether_addr *)hw->mac.mac_addr); 1794 hw->mac.default_addr_setted = true; 1795 rte_spinlock_unlock(&hw->lock); 1796 1797 return 0; 1798 1799 err_pause_addr_cfg: 1800 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1801 if (ret_val) { 1802 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1803 mac_addr); 1804 hns3_warn(hw, 1805 "Failed to roll back to del setted mac addr(%s): %d", 1806 mac_str, ret_val); 1807 } 1808 1809 err_add_uc_addr: 1810 if (rm_succes) { 1811 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1812 if (ret_val) { 1813 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1814 oaddr); 1815 hns3_warn(hw, 1816 "Failed to restore old uc mac addr(%s): %d", 1817 mac_str, ret_val); 1818 hw->mac.default_addr_setted = false; 1819 } 1820 } 1821 rte_spinlock_unlock(&hw->lock); 1822 1823 return ret; 1824 } 1825 1826 static int 1827 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1828 { 1829 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1830 struct hns3_hw *hw = &hns->hw; 1831 struct rte_ether_addr *addr; 1832 int err = 0; 1833 int ret; 1834 int i; 1835 1836 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1837 addr = &hw->data->mac_addrs[i]; 1838 if (rte_is_zero_ether_addr(addr)) 1839 continue; 1840 if (rte_is_multicast_ether_addr(addr)) 1841 ret = del ? hns3_remove_mc_addr(hw, addr) : 1842 hns3_add_mc_addr(hw, addr); 1843 else 1844 ret = del ? hns3_remove_uc_addr_common(hw, addr) : 1845 hns3_add_uc_addr_common(hw, addr); 1846 1847 if (ret) { 1848 err = ret; 1849 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1850 addr); 1851 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 1852 "ret = %d.", del ? "remove" : "restore", 1853 mac_str, i, ret); 1854 } 1855 } 1856 return err; 1857 } 1858 1859 static void 1860 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1861 { 1862 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1863 uint8_t word_num; 1864 uint8_t bit_num; 1865 1866 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1867 word_num = vfid / 32; 1868 bit_num = vfid % 32; 1869 if (clr) 1870 desc[1].data[word_num] &= 1871 rte_cpu_to_le_32(~(1UL << bit_num)); 1872 else 1873 desc[1].data[word_num] |= 1874 rte_cpu_to_le_32(1UL << bit_num); 1875 } else { 1876 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1877 bit_num = vfid % 32; 1878 if (clr) 1879 desc[2].data[word_num] &= 1880 rte_cpu_to_le_32(~(1UL << bit_num)); 1881 else 1882 desc[2].data[word_num] |= 1883 rte_cpu_to_le_32(1UL << bit_num); 1884 } 1885 } 1886 1887 static int 1888 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1889 { 1890 struct hns3_mac_vlan_tbl_entry_cmd req; 1891 struct hns3_cmd_desc desc[3]; 1892 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1893 uint8_t vf_id; 1894 int ret; 1895 1896 /* Check if mac addr is valid */ 1897 if (!rte_is_multicast_ether_addr(mac_addr)) { 1898 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1899 mac_addr); 1900 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1901 mac_str); 1902 return -EINVAL; 1903 } 1904 1905 memset(&req, 0, sizeof(req)); 1906 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1907 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1908 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1909 if (ret) { 1910 /* This mac addr do not exist, add new entry for it */ 1911 memset(desc[0].data, 0, sizeof(desc[0].data)); 1912 memset(desc[1].data, 0, sizeof(desc[0].data)); 1913 memset(desc[2].data, 0, sizeof(desc[0].data)); 1914 } 1915 1916 /* 1917 * In current version VF is not supported when PF is driven by DPDK 1918 * driver, just need to configure parameters for PF vport. 1919 */ 1920 vf_id = HNS3_PF_FUNC_ID; 1921 hns3_update_desc_vfid(desc, vf_id, false); 1922 ret = hns3_add_mac_vlan_tbl(hw, &req, desc); 1923 if (ret) { 1924 if (ret == -ENOSPC) 1925 hns3_err(hw, "mc mac vlan table is full"); 1926 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1927 mac_addr); 1928 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1929 } 1930 1931 return ret; 1932 } 1933 1934 static int 1935 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1936 { 1937 struct hns3_mac_vlan_tbl_entry_cmd req; 1938 struct hns3_cmd_desc desc[3]; 1939 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1940 uint8_t vf_id; 1941 int ret; 1942 1943 /* Check if mac addr is valid */ 1944 if (!rte_is_multicast_ether_addr(mac_addr)) { 1945 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1946 mac_addr); 1947 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1948 mac_str); 1949 return -EINVAL; 1950 } 1951 1952 memset(&req, 0, sizeof(req)); 1953 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1954 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1955 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1956 if (ret == 0) { 1957 /* 1958 * This mac addr exist, remove this handle's VFID for it. 1959 * In current version VF is not supported when PF is driven by 1960 * DPDK driver, just need to configure parameters for PF vport. 1961 */ 1962 vf_id = HNS3_PF_FUNC_ID; 1963 hns3_update_desc_vfid(desc, vf_id, true); 1964 1965 /* All the vfid is zero, so need to delete this entry */ 1966 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1967 } else if (ret == -ENOENT) { 1968 /* This mac addr doesn't exist. */ 1969 return 0; 1970 } 1971 1972 if (ret) { 1973 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1974 mac_addr); 1975 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1976 } 1977 1978 return ret; 1979 } 1980 1981 static int 1982 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1983 struct rte_ether_addr *mc_addr_set, 1984 uint32_t nb_mc_addr) 1985 { 1986 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1987 struct rte_ether_addr *addr; 1988 uint32_t i; 1989 uint32_t j; 1990 1991 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1992 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 1993 "invalid. valid range: 0~%d", 1994 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1995 return -EINVAL; 1996 } 1997 1998 /* Check if input mac addresses are valid */ 1999 for (i = 0; i < nb_mc_addr; i++) { 2000 addr = &mc_addr_set[i]; 2001 if (!rte_is_multicast_ether_addr(addr)) { 2002 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2003 addr); 2004 hns3_err(hw, 2005 "failed to set mc mac addr, addr(%s) invalid.", 2006 mac_str); 2007 return -EINVAL; 2008 } 2009 2010 /* Check if there are duplicate addresses */ 2011 for (j = i + 1; j < nb_mc_addr; j++) { 2012 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 2013 hns3_ether_format_addr(mac_str, 2014 RTE_ETHER_ADDR_FMT_SIZE, 2015 addr); 2016 hns3_err(hw, "failed to set mc mac addr, " 2017 "addrs invalid. two same addrs(%s).", 2018 mac_str); 2019 return -EINVAL; 2020 } 2021 } 2022 2023 /* 2024 * Check if there are duplicate addresses between mac_addrs 2025 * and mc_addr_set 2026 */ 2027 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) { 2028 if (rte_is_same_ether_addr(addr, 2029 &hw->data->mac_addrs[j])) { 2030 hns3_ether_format_addr(mac_str, 2031 RTE_ETHER_ADDR_FMT_SIZE, 2032 addr); 2033 hns3_err(hw, "failed to set mc mac addr, " 2034 "addrs invalid. addrs(%s) has already " 2035 "configured in mac_addr add API", 2036 mac_str); 2037 return -EINVAL; 2038 } 2039 } 2040 } 2041 2042 return 0; 2043 } 2044 2045 static void 2046 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 2047 struct rte_ether_addr *mc_addr_set, 2048 int mc_addr_num, 2049 struct rte_ether_addr *reserved_addr_list, 2050 int *reserved_addr_num, 2051 struct rte_ether_addr *add_addr_list, 2052 int *add_addr_num, 2053 struct rte_ether_addr *rm_addr_list, 2054 int *rm_addr_num) 2055 { 2056 struct rte_ether_addr *addr; 2057 int current_addr_num; 2058 int reserved_num = 0; 2059 int add_num = 0; 2060 int rm_num = 0; 2061 int num; 2062 int i; 2063 int j; 2064 bool same_addr; 2065 2066 /* Calculate the mc mac address list that should be removed */ 2067 current_addr_num = hw->mc_addrs_num; 2068 for (i = 0; i < current_addr_num; i++) { 2069 addr = &hw->mc_addrs[i]; 2070 same_addr = false; 2071 for (j = 0; j < mc_addr_num; j++) { 2072 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 2073 same_addr = true; 2074 break; 2075 } 2076 } 2077 2078 if (!same_addr) { 2079 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 2080 rm_num++; 2081 } else { 2082 rte_ether_addr_copy(addr, 2083 &reserved_addr_list[reserved_num]); 2084 reserved_num++; 2085 } 2086 } 2087 2088 /* Calculate the mc mac address list that should be added */ 2089 for (i = 0; i < mc_addr_num; i++) { 2090 addr = &mc_addr_set[i]; 2091 same_addr = false; 2092 for (j = 0; j < current_addr_num; j++) { 2093 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 2094 same_addr = true; 2095 break; 2096 } 2097 } 2098 2099 if (!same_addr) { 2100 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 2101 add_num++; 2102 } 2103 } 2104 2105 /* Reorder the mc mac address list maintained by driver */ 2106 for (i = 0; i < reserved_num; i++) 2107 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 2108 2109 for (i = 0; i < rm_num; i++) { 2110 num = reserved_num + i; 2111 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 2112 } 2113 2114 *reserved_addr_num = reserved_num; 2115 *add_addr_num = add_num; 2116 *rm_addr_num = rm_num; 2117 } 2118 2119 static int 2120 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 2121 struct rte_ether_addr *mc_addr_set, 2122 uint32_t nb_mc_addr) 2123 { 2124 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2125 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 2126 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 2127 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 2128 struct rte_ether_addr *addr; 2129 int reserved_addr_num; 2130 int add_addr_num; 2131 int rm_addr_num; 2132 int mc_addr_num; 2133 int num; 2134 int ret; 2135 int i; 2136 2137 /* Check if input parameters are valid */ 2138 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 2139 if (ret) 2140 return ret; 2141 2142 rte_spinlock_lock(&hw->lock); 2143 2144 /* 2145 * Calculate the mc mac address lists those should be removed and be 2146 * added, Reorder the mc mac address list maintained by driver. 2147 */ 2148 mc_addr_num = (int)nb_mc_addr; 2149 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 2150 reserved_addr_list, &reserved_addr_num, 2151 add_addr_list, &add_addr_num, 2152 rm_addr_list, &rm_addr_num); 2153 2154 /* Remove mc mac addresses */ 2155 for (i = 0; i < rm_addr_num; i++) { 2156 num = rm_addr_num - i - 1; 2157 addr = &rm_addr_list[num]; 2158 ret = hns3_remove_mc_addr(hw, addr); 2159 if (ret) { 2160 rte_spinlock_unlock(&hw->lock); 2161 return ret; 2162 } 2163 hw->mc_addrs_num--; 2164 } 2165 2166 /* Add mc mac addresses */ 2167 for (i = 0; i < add_addr_num; i++) { 2168 addr = &add_addr_list[i]; 2169 ret = hns3_add_mc_addr(hw, addr); 2170 if (ret) { 2171 rte_spinlock_unlock(&hw->lock); 2172 return ret; 2173 } 2174 2175 num = reserved_addr_num + i; 2176 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 2177 hw->mc_addrs_num++; 2178 } 2179 rte_spinlock_unlock(&hw->lock); 2180 2181 return 0; 2182 } 2183 2184 static int 2185 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 2186 { 2187 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2188 struct hns3_hw *hw = &hns->hw; 2189 struct rte_ether_addr *addr; 2190 int err = 0; 2191 int ret; 2192 int i; 2193 2194 for (i = 0; i < hw->mc_addrs_num; i++) { 2195 addr = &hw->mc_addrs[i]; 2196 if (!rte_is_multicast_ether_addr(addr)) 2197 continue; 2198 if (del) 2199 ret = hns3_remove_mc_addr(hw, addr); 2200 else 2201 ret = hns3_add_mc_addr(hw, addr); 2202 if (ret) { 2203 err = ret; 2204 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2205 addr); 2206 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d", 2207 del ? "Remove" : "Restore", mac_str, ret); 2208 } 2209 } 2210 return err; 2211 } 2212 2213 static int 2214 hns3_check_mq_mode(struct rte_eth_dev *dev) 2215 { 2216 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 2217 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 2218 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2219 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2220 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 2221 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 2222 uint8_t num_tc; 2223 int max_tc = 0; 2224 int i; 2225 2226 if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) || 2227 (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB || 2228 tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) { 2229 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.", 2230 rx_mq_mode, tx_mq_mode); 2231 return -EOPNOTSUPP; 2232 } 2233 2234 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 2235 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 2236 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) { 2237 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 2238 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 2239 dcb_rx_conf->nb_tcs, pf->tc_max); 2240 return -EINVAL; 2241 } 2242 2243 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 2244 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 2245 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 2246 "nb_tcs(%d) != %d or %d in rx direction.", 2247 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 2248 return -EINVAL; 2249 } 2250 2251 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 2252 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 2253 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 2254 return -EINVAL; 2255 } 2256 2257 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 2258 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 2259 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, " 2260 "is not equal to one in tx direction.", 2261 i, dcb_rx_conf->dcb_tc[i]); 2262 return -EINVAL; 2263 } 2264 if (dcb_rx_conf->dcb_tc[i] > max_tc) 2265 max_tc = dcb_rx_conf->dcb_tc[i]; 2266 } 2267 2268 num_tc = max_tc + 1; 2269 if (num_tc > dcb_rx_conf->nb_tcs) { 2270 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 2271 num_tc, dcb_rx_conf->nb_tcs); 2272 return -EINVAL; 2273 } 2274 } 2275 2276 return 0; 2277 } 2278 2279 static int 2280 hns3_check_dcb_cfg(struct rte_eth_dev *dev) 2281 { 2282 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2283 2284 if (!hns3_dev_dcb_supported(hw)) { 2285 hns3_err(hw, "this port does not support dcb configurations."); 2286 return -EOPNOTSUPP; 2287 } 2288 2289 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2290 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2291 return -EOPNOTSUPP; 2292 } 2293 2294 return 0; 2295 } 2296 2297 static int 2298 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, 2299 enum hns3_ring_type queue_type, uint16_t queue_id) 2300 { 2301 struct hns3_cmd_desc desc; 2302 struct hns3_ctrl_vector_chain_cmd *req = 2303 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 2304 enum hns3_opcode_type op; 2305 uint16_t tqp_type_and_id = 0; 2306 uint16_t type; 2307 uint16_t gl; 2308 int ret; 2309 2310 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 2311 hns3_cmd_setup_basic_desc(&desc, op, false); 2312 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M, 2313 HNS3_TQP_INT_ID_L_S); 2314 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M, 2315 HNS3_TQP_INT_ID_H_S); 2316 2317 if (queue_type == HNS3_RING_TYPE_RX) 2318 gl = HNS3_RING_GL_RX; 2319 else 2320 gl = HNS3_RING_GL_TX; 2321 2322 type = queue_type; 2323 2324 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 2325 type); 2326 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 2327 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 2328 gl); 2329 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 2330 req->int_cause_num = 1; 2331 ret = hns3_cmd_send(hw, &desc, 1); 2332 if (ret) { 2333 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.", 2334 en ? "Map" : "Unmap", queue_id, vector_id, ret); 2335 return ret; 2336 } 2337 2338 return 0; 2339 } 2340 2341 static int 2342 hns3_init_ring_with_vector(struct hns3_hw *hw) 2343 { 2344 uint16_t vec; 2345 int ret; 2346 int i; 2347 2348 /* 2349 * In hns3 network engine, vector 0 is always the misc interrupt of this 2350 * function, vector 1~N can be used respectively for the queues of the 2351 * function. Tx and Rx queues with the same number share the interrupt 2352 * vector. In the initialization clearing the all hardware mapping 2353 * relationship configurations between queues and interrupt vectors is 2354 * needed, so some error caused by the residual configurations, such as 2355 * the unexpected Tx interrupt, can be avoid. 2356 */ 2357 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 2358 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 2359 vec = vec - 1; /* the last interrupt is reserved */ 2360 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 2361 for (i = 0; i < hw->intr_tqps_num; i++) { 2362 /* 2363 * Set gap limiter/rate limiter/quanity limiter algorithm 2364 * configuration for interrupt coalesce of queue's interrupt. 2365 */ 2366 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 2367 HNS3_TQP_INTR_GL_DEFAULT); 2368 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 2369 HNS3_TQP_INTR_GL_DEFAULT); 2370 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 2371 /* 2372 * QL(quantity limiter) is not used currently, just set 0 to 2373 * close it. 2374 */ 2375 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 2376 2377 ret = hns3_bind_ring_with_vector(hw, vec, false, 2378 HNS3_RING_TYPE_TX, i); 2379 if (ret) { 2380 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " 2381 "vector: %u, ret=%d", i, vec, ret); 2382 return ret; 2383 } 2384 2385 ret = hns3_bind_ring_with_vector(hw, vec, false, 2386 HNS3_RING_TYPE_RX, i); 2387 if (ret) { 2388 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " 2389 "vector: %u, ret=%d", i, vec, ret); 2390 return ret; 2391 } 2392 } 2393 2394 return 0; 2395 } 2396 2397 static int 2398 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf) 2399 { 2400 struct hns3_adapter *hns = dev->data->dev_private; 2401 struct hns3_hw *hw = &hns->hw; 2402 uint32_t max_rx_pkt_len; 2403 uint16_t mtu; 2404 int ret; 2405 2406 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)) 2407 return 0; 2408 2409 /* 2410 * If jumbo frames are enabled, MTU needs to be refreshed 2411 * according to the maximum RX packet length. 2412 */ 2413 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len; 2414 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN || 2415 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) { 2416 hns3_err(hw, "maximum Rx packet length must be greater than %u " 2417 "and no more than %u when jumbo frame enabled.", 2418 (uint16_t)HNS3_DEFAULT_FRAME_LEN, 2419 (uint16_t)HNS3_MAX_FRAME_LEN); 2420 return -EINVAL; 2421 } 2422 2423 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len); 2424 ret = hns3_dev_mtu_set(dev, mtu); 2425 if (ret) 2426 return ret; 2427 dev->data->mtu = mtu; 2428 2429 return 0; 2430 } 2431 2432 static int 2433 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds) 2434 { 2435 int ret; 2436 2437 /* 2438 * Some hardware doesn't support auto-negotiation, but users may not 2439 * configure link_speeds (default 0), which means auto-negotiation. 2440 * In this case, a warning message need to be printed, instead of 2441 * an error. 2442 */ 2443 if (link_speeds == ETH_LINK_SPEED_AUTONEG && 2444 hw->mac.support_autoneg == 0) { 2445 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!"); 2446 return 0; 2447 } 2448 2449 if (link_speeds != ETH_LINK_SPEED_AUTONEG) { 2450 ret = hns3_check_port_speed(hw, link_speeds); 2451 if (ret) 2452 return ret; 2453 } 2454 2455 return 0; 2456 } 2457 2458 static int 2459 hns3_check_dev_conf(struct rte_eth_dev *dev) 2460 { 2461 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2462 struct rte_eth_conf *conf = &dev->data->dev_conf; 2463 int ret; 2464 2465 ret = hns3_check_mq_mode(dev); 2466 if (ret) 2467 return ret; 2468 2469 return hns3_check_link_speed(hw, conf->link_speeds); 2470 } 2471 2472 static int 2473 hns3_dev_configure(struct rte_eth_dev *dev) 2474 { 2475 struct hns3_adapter *hns = dev->data->dev_private; 2476 struct rte_eth_conf *conf = &dev->data->dev_conf; 2477 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2478 struct hns3_hw *hw = &hns->hw; 2479 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2480 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2481 struct rte_eth_rss_conf rss_conf; 2482 bool gro_en; 2483 int ret; 2484 2485 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 2486 2487 /* 2488 * Some versions of hardware network engine does not support 2489 * individually enable/disable/reset the Tx or Rx queue. These devices 2490 * must enable/disable/reset Tx and Rx queues at the same time. When the 2491 * numbers of Tx queues allocated by upper applications are not equal to 2492 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 2493 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 2494 * work as usual. But these fake queues are imperceptible, and can not 2495 * be used by upper applications. 2496 */ 2497 if (!hns3_dev_indep_txrx_supported(hw)) { 2498 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2499 if (ret) { 2500 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", 2501 ret); 2502 return ret; 2503 } 2504 } 2505 2506 hw->adapter_state = HNS3_NIC_CONFIGURING; 2507 ret = hns3_check_dev_conf(dev); 2508 if (ret) 2509 goto cfg_err; 2510 2511 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2512 ret = hns3_check_dcb_cfg(dev); 2513 if (ret) 2514 goto cfg_err; 2515 } 2516 2517 /* When RSS is not configured, redirect the packet queue 0 */ 2518 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2519 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2520 rss_conf = conf->rx_adv_conf.rss_conf; 2521 hw->rss_dis_flag = false; 2522 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2523 if (ret) 2524 goto cfg_err; 2525 } 2526 2527 ret = hns3_refresh_mtu(dev, conf); 2528 if (ret) 2529 goto cfg_err; 2530 2531 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf); 2532 if (ret) 2533 goto cfg_err; 2534 2535 ret = hns3_dev_configure_vlan(dev); 2536 if (ret) 2537 goto cfg_err; 2538 2539 /* config hardware GRO */ 2540 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 2541 ret = hns3_config_gro(hw, gro_en); 2542 if (ret) 2543 goto cfg_err; 2544 2545 hns3_init_rx_ptype_tble(dev); 2546 hw->adapter_state = HNS3_NIC_CONFIGURED; 2547 2548 return 0; 2549 2550 cfg_err: 2551 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2552 hw->adapter_state = HNS3_NIC_INITIALIZED; 2553 2554 return ret; 2555 } 2556 2557 static int 2558 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2559 { 2560 struct hns3_config_max_frm_size_cmd *req; 2561 struct hns3_cmd_desc desc; 2562 2563 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2564 2565 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2566 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2567 req->min_frm_size = RTE_ETHER_MIN_LEN; 2568 2569 return hns3_cmd_send(hw, &desc, 1); 2570 } 2571 2572 static int 2573 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2574 { 2575 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2576 uint16_t original_mps = hns->pf.mps; 2577 int err; 2578 int ret; 2579 2580 ret = hns3_set_mac_mtu(hw, mps); 2581 if (ret) { 2582 hns3_err(hw, "failed to set mtu, ret = %d", ret); 2583 return ret; 2584 } 2585 2586 hns->pf.mps = mps; 2587 ret = hns3_buffer_alloc(hw); 2588 if (ret) { 2589 hns3_err(hw, "failed to allocate buffer, ret = %d", ret); 2590 goto rollback; 2591 } 2592 2593 return 0; 2594 2595 rollback: 2596 err = hns3_set_mac_mtu(hw, original_mps); 2597 if (err) { 2598 hns3_err(hw, "fail to rollback MTU, err = %d", err); 2599 return ret; 2600 } 2601 hns->pf.mps = original_mps; 2602 2603 return ret; 2604 } 2605 2606 static int 2607 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2608 { 2609 struct hns3_adapter *hns = dev->data->dev_private; 2610 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2611 struct hns3_hw *hw = &hns->hw; 2612 bool is_jumbo_frame; 2613 int ret; 2614 2615 if (dev->data->dev_started) { 2616 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2617 "before configuration", dev->data->port_id); 2618 return -EBUSY; 2619 } 2620 2621 rte_spinlock_lock(&hw->lock); 2622 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false; 2623 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2624 2625 /* 2626 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2627 * assign to "uint16_t" type variable. 2628 */ 2629 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2630 if (ret) { 2631 rte_spinlock_unlock(&hw->lock); 2632 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2633 dev->data->port_id, mtu, ret); 2634 return ret; 2635 } 2636 2637 if (is_jumbo_frame) 2638 dev->data->dev_conf.rxmode.offloads |= 2639 DEV_RX_OFFLOAD_JUMBO_FRAME; 2640 else 2641 dev->data->dev_conf.rxmode.offloads &= 2642 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2643 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2644 rte_spinlock_unlock(&hw->lock); 2645 2646 return 0; 2647 } 2648 2649 static uint32_t 2650 hns3_get_copper_port_speed_capa(uint32_t supported_speed) 2651 { 2652 uint32_t speed_capa = 0; 2653 2654 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT) 2655 speed_capa |= ETH_LINK_SPEED_10M_HD; 2656 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT) 2657 speed_capa |= ETH_LINK_SPEED_10M; 2658 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT) 2659 speed_capa |= ETH_LINK_SPEED_100M_HD; 2660 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT) 2661 speed_capa |= ETH_LINK_SPEED_100M; 2662 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT) 2663 speed_capa |= ETH_LINK_SPEED_1G; 2664 2665 return speed_capa; 2666 } 2667 2668 static uint32_t 2669 hns3_get_firber_port_speed_capa(uint32_t supported_speed) 2670 { 2671 uint32_t speed_capa = 0; 2672 2673 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT) 2674 speed_capa |= ETH_LINK_SPEED_1G; 2675 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT) 2676 speed_capa |= ETH_LINK_SPEED_10G; 2677 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT) 2678 speed_capa |= ETH_LINK_SPEED_25G; 2679 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT) 2680 speed_capa |= ETH_LINK_SPEED_40G; 2681 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT) 2682 speed_capa |= ETH_LINK_SPEED_50G; 2683 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT) 2684 speed_capa |= ETH_LINK_SPEED_100G; 2685 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT) 2686 speed_capa |= ETH_LINK_SPEED_200G; 2687 2688 return speed_capa; 2689 } 2690 2691 static uint32_t 2692 hns3_get_speed_capa(struct hns3_hw *hw) 2693 { 2694 struct hns3_mac *mac = &hw->mac; 2695 uint32_t speed_capa; 2696 2697 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 2698 speed_capa = 2699 hns3_get_copper_port_speed_capa(mac->supported_speed); 2700 else 2701 speed_capa = 2702 hns3_get_firber_port_speed_capa(mac->supported_speed); 2703 2704 if (mac->support_autoneg == 0) 2705 speed_capa |= ETH_LINK_SPEED_FIXED; 2706 2707 return speed_capa; 2708 } 2709 2710 int 2711 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2712 { 2713 struct hns3_adapter *hns = eth_dev->data->dev_private; 2714 struct hns3_hw *hw = &hns->hw; 2715 uint16_t queue_num = hw->tqps_num; 2716 2717 /* 2718 * In interrupt mode, 'max_rx_queues' is set based on the number of 2719 * MSI-X interrupt resources of the hardware. 2720 */ 2721 if (hw->data->dev_conf.intr_conf.rxq == 1) 2722 queue_num = hw->intr_tqps_num; 2723 2724 info->max_rx_queues = queue_num; 2725 info->max_tx_queues = hw->tqps_num; 2726 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2727 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 2728 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2729 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2730 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 2731 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2732 DEV_RX_OFFLOAD_TCP_CKSUM | 2733 DEV_RX_OFFLOAD_UDP_CKSUM | 2734 DEV_RX_OFFLOAD_SCTP_CKSUM | 2735 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2736 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2737 DEV_RX_OFFLOAD_KEEP_CRC | 2738 DEV_RX_OFFLOAD_SCATTER | 2739 DEV_RX_OFFLOAD_VLAN_STRIP | 2740 DEV_RX_OFFLOAD_VLAN_FILTER | 2741 DEV_RX_OFFLOAD_JUMBO_FRAME | 2742 DEV_RX_OFFLOAD_RSS_HASH | 2743 DEV_RX_OFFLOAD_TCP_LRO); 2744 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2745 DEV_TX_OFFLOAD_IPV4_CKSUM | 2746 DEV_TX_OFFLOAD_TCP_CKSUM | 2747 DEV_TX_OFFLOAD_UDP_CKSUM | 2748 DEV_TX_OFFLOAD_SCTP_CKSUM | 2749 DEV_TX_OFFLOAD_MULTI_SEGS | 2750 DEV_TX_OFFLOAD_TCP_TSO | 2751 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2752 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2753 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2754 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 2755 hns3_txvlan_cap_get(hw)); 2756 2757 if (hns3_dev_outer_udp_cksum_supported(hw)) 2758 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 2759 2760 if (hns3_dev_indep_txrx_supported(hw)) 2761 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 2762 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 2763 2764 if (hns3_dev_ptp_supported(hw)) 2765 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 2766 2767 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2768 .nb_max = HNS3_MAX_RING_DESC, 2769 .nb_min = HNS3_MIN_RING_DESC, 2770 .nb_align = HNS3_ALIGN_RING_DESC, 2771 }; 2772 2773 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2774 .nb_max = HNS3_MAX_RING_DESC, 2775 .nb_min = HNS3_MIN_RING_DESC, 2776 .nb_align = HNS3_ALIGN_RING_DESC, 2777 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 2778 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 2779 }; 2780 2781 info->speed_capa = hns3_get_speed_capa(hw); 2782 info->default_rxconf = (struct rte_eth_rxconf) { 2783 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 2784 /* 2785 * If there are no available Rx buffer descriptors, incoming 2786 * packets are always dropped by hardware based on hns3 network 2787 * engine. 2788 */ 2789 .rx_drop_en = 1, 2790 .offloads = 0, 2791 }; 2792 info->default_txconf = (struct rte_eth_txconf) { 2793 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 2794 .offloads = 0, 2795 }; 2796 2797 info->vmdq_queue_num = 0; 2798 2799 info->reta_size = hw->rss_ind_tbl_size; 2800 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2801 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2802 2803 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2804 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2805 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2806 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2807 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2808 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2809 2810 return 0; 2811 } 2812 2813 static int 2814 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2815 size_t fw_size) 2816 { 2817 struct hns3_adapter *hns = eth_dev->data->dev_private; 2818 struct hns3_hw *hw = &hns->hw; 2819 uint32_t version = hw->fw_version; 2820 int ret; 2821 2822 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2823 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2824 HNS3_FW_VERSION_BYTE3_S), 2825 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2826 HNS3_FW_VERSION_BYTE2_S), 2827 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2828 HNS3_FW_VERSION_BYTE1_S), 2829 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2830 HNS3_FW_VERSION_BYTE0_S)); 2831 if (ret < 0) 2832 return -EINVAL; 2833 2834 ret += 1; /* add the size of '\0' */ 2835 if (fw_size < (size_t)ret) 2836 return ret; 2837 else 2838 return 0; 2839 } 2840 2841 static int 2842 hns3_update_port_link_info(struct rte_eth_dev *eth_dev) 2843 { 2844 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2845 int ret; 2846 2847 (void)hns3_update_link_status(hw); 2848 2849 ret = hns3_update_link_info(eth_dev); 2850 if (ret) 2851 hw->mac.link_status = ETH_LINK_DOWN; 2852 2853 return ret; 2854 } 2855 2856 static void 2857 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev, 2858 struct rte_eth_link *new_link) 2859 { 2860 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2861 struct hns3_mac *mac = &hw->mac; 2862 2863 switch (mac->link_speed) { 2864 case ETH_SPEED_NUM_10M: 2865 case ETH_SPEED_NUM_100M: 2866 case ETH_SPEED_NUM_1G: 2867 case ETH_SPEED_NUM_10G: 2868 case ETH_SPEED_NUM_25G: 2869 case ETH_SPEED_NUM_40G: 2870 case ETH_SPEED_NUM_50G: 2871 case ETH_SPEED_NUM_100G: 2872 case ETH_SPEED_NUM_200G: 2873 if (mac->link_status) 2874 new_link->link_speed = mac->link_speed; 2875 break; 2876 default: 2877 if (mac->link_status) 2878 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN; 2879 break; 2880 } 2881 2882 if (!mac->link_status) 2883 new_link->link_speed = ETH_SPEED_NUM_NONE; 2884 2885 new_link->link_duplex = mac->link_duplex; 2886 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2887 new_link->link_autoneg = mac->link_autoneg; 2888 } 2889 2890 static int 2891 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) 2892 { 2893 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */ 2894 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */ 2895 2896 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2897 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES; 2898 struct hns3_mac *mac = &hw->mac; 2899 struct rte_eth_link new_link; 2900 int ret; 2901 2902 /* When port is stopped, report link down. */ 2903 if (eth_dev->data->dev_started == 0) { 2904 new_link.link_autoneg = mac->link_autoneg; 2905 new_link.link_duplex = mac->link_duplex; 2906 new_link.link_speed = ETH_SPEED_NUM_NONE; 2907 new_link.link_status = ETH_LINK_DOWN; 2908 goto out; 2909 } 2910 2911 do { 2912 ret = hns3_update_port_link_info(eth_dev); 2913 if (ret) { 2914 hns3_err(hw, "failed to get port link info, ret = %d.", 2915 ret); 2916 break; 2917 } 2918 2919 if (!wait_to_complete || mac->link_status == ETH_LINK_UP) 2920 break; 2921 2922 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL); 2923 } while (retry_cnt--); 2924 2925 memset(&new_link, 0, sizeof(new_link)); 2926 hns3_setup_linkstatus(eth_dev, &new_link); 2927 2928 out: 2929 return rte_eth_linkstatus_set(eth_dev, &new_link); 2930 } 2931 2932 static int 2933 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2934 { 2935 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2936 struct hns3_pf *pf = &hns->pf; 2937 2938 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2939 return -EINVAL; 2940 2941 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2942 2943 return 0; 2944 } 2945 2946 static int 2947 hns3_query_function_status(struct hns3_hw *hw) 2948 { 2949 #define HNS3_QUERY_MAX_CNT 10 2950 #define HNS3_QUERY_SLEEP_MSCOEND 1 2951 struct hns3_func_status_cmd *req; 2952 struct hns3_cmd_desc desc; 2953 int timeout = 0; 2954 int ret; 2955 2956 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2957 req = (struct hns3_func_status_cmd *)desc.data; 2958 2959 do { 2960 ret = hns3_cmd_send(hw, &desc, 1); 2961 if (ret) { 2962 PMD_INIT_LOG(ERR, "query function status failed %d", 2963 ret); 2964 return ret; 2965 } 2966 2967 /* Check pf reset is done */ 2968 if (req->pf_state) 2969 break; 2970 2971 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2972 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2973 2974 return hns3_parse_func_status(hw, req); 2975 } 2976 2977 static int 2978 hns3_get_pf_max_tqp_num(struct hns3_hw *hw) 2979 { 2980 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2981 struct hns3_pf *pf = &hns->pf; 2982 2983 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) { 2984 /* 2985 * The total_tqps_num obtained from firmware is maximum tqp 2986 * numbers of this port, which should be used for PF and VFs. 2987 * There is no need for pf to have so many tqp numbers in 2988 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2989 * coming from config file, is assigned to maximum queue number 2990 * for the PF of this port by user. So users can modify the 2991 * maximum queue number of PF according to their own application 2992 * scenarios, which is more flexible to use. In addition, many 2993 * memories can be saved due to allocating queue statistics 2994 * room according to the actual number of queues required. The 2995 * maximum queue number of PF for network engine with 2996 * revision_id greater than 0x30 is assigned by config file. 2997 */ 2998 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) { 2999 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) " 3000 "must be greater than 0.", 3001 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF); 3002 return -EINVAL; 3003 } 3004 3005 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 3006 hw->total_tqps_num); 3007 } else { 3008 /* 3009 * Due to the limitation on the number of PF interrupts 3010 * available, the maximum queue number assigned to PF on 3011 * the network engine with revision_id 0x21 is 64. 3012 */ 3013 hw->tqps_num = RTE_MIN(hw->total_tqps_num, 3014 HNS3_MAX_TQP_NUM_HIP08_PF); 3015 } 3016 3017 return 0; 3018 } 3019 3020 static int 3021 hns3_query_pf_resource(struct hns3_hw *hw) 3022 { 3023 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3024 struct hns3_pf *pf = &hns->pf; 3025 struct hns3_pf_res_cmd *req; 3026 struct hns3_cmd_desc desc; 3027 int ret; 3028 3029 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 3030 ret = hns3_cmd_send(hw, &desc, 1); 3031 if (ret) { 3032 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 3033 return ret; 3034 } 3035 3036 req = (struct hns3_pf_res_cmd *)desc.data; 3037 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) + 3038 rte_le_to_cpu_16(req->ext_tqp_num); 3039 ret = hns3_get_pf_max_tqp_num(hw); 3040 if (ret) 3041 return ret; 3042 3043 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 3044 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 3045 3046 if (req->tx_buf_size) 3047 pf->tx_buf_size = 3048 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 3049 else 3050 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 3051 3052 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 3053 3054 if (req->dv_buf_size) 3055 pf->dv_buf_size = 3056 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 3057 else 3058 pf->dv_buf_size = HNS3_DEFAULT_DV; 3059 3060 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 3061 3062 hw->num_msi = 3063 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 3064 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 3065 3066 return 0; 3067 } 3068 3069 static void 3070 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 3071 { 3072 struct hns3_cfg_param_cmd *req; 3073 uint64_t mac_addr_tmp_high; 3074 uint8_t ext_rss_size_max; 3075 uint64_t mac_addr_tmp; 3076 uint32_t i; 3077 3078 req = (struct hns3_cfg_param_cmd *)desc[0].data; 3079 3080 /* get the configuration */ 3081 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3082 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S); 3083 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3084 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 3085 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3086 HNS3_CFG_TQP_DESC_N_M, 3087 HNS3_CFG_TQP_DESC_N_S); 3088 3089 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3090 HNS3_CFG_PHY_ADDR_M, 3091 HNS3_CFG_PHY_ADDR_S); 3092 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3093 HNS3_CFG_MEDIA_TP_M, 3094 HNS3_CFG_MEDIA_TP_S); 3095 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3096 HNS3_CFG_RX_BUF_LEN_M, 3097 HNS3_CFG_RX_BUF_LEN_S); 3098 /* get mac address */ 3099 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 3100 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3101 HNS3_CFG_MAC_ADDR_H_M, 3102 HNS3_CFG_MAC_ADDR_H_S); 3103 3104 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 3105 3106 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3107 HNS3_CFG_DEFAULT_SPEED_M, 3108 HNS3_CFG_DEFAULT_SPEED_S); 3109 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3110 HNS3_CFG_RSS_SIZE_M, 3111 HNS3_CFG_RSS_SIZE_S); 3112 3113 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3114 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 3115 3116 req = (struct hns3_cfg_param_cmd *)desc[1].data; 3117 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 3118 3119 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3120 HNS3_CFG_SPEED_ABILITY_M, 3121 HNS3_CFG_SPEED_ABILITY_S); 3122 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3123 HNS3_CFG_UMV_TBL_SPACE_M, 3124 HNS3_CFG_UMV_TBL_SPACE_S); 3125 if (!cfg->umv_space) 3126 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 3127 3128 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]), 3129 HNS3_CFG_EXT_RSS_SIZE_M, 3130 HNS3_CFG_EXT_RSS_SIZE_S); 3131 3132 /* 3133 * Field ext_rss_size_max obtained from firmware will be more flexible 3134 * for future changes and expansions, which is an exponent of 2, instead 3135 * of reading out directly. If this field is not zero, hns3 PF PMD 3136 * driver uses it as rss_size_max under one TC. Device, whose revision 3137 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the 3138 * maximum number of queues supported under a TC through this field. 3139 */ 3140 if (ext_rss_size_max) 3141 cfg->rss_size_max = 1U << ext_rss_size_max; 3142 } 3143 3144 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 3145 * @hw: pointer to struct hns3_hw 3146 * @hcfg: the config structure to be getted 3147 */ 3148 static int 3149 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 3150 { 3151 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 3152 struct hns3_cfg_param_cmd *req; 3153 uint32_t offset; 3154 uint32_t i; 3155 int ret; 3156 3157 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 3158 offset = 0; 3159 req = (struct hns3_cfg_param_cmd *)desc[i].data; 3160 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 3161 true); 3162 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 3163 i * HNS3_CFG_RD_LEN_BYTES); 3164 /* Len should be divided by 4 when send to hardware */ 3165 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 3166 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 3167 req->offset = rte_cpu_to_le_32(offset); 3168 } 3169 3170 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 3171 if (ret) { 3172 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 3173 return ret; 3174 } 3175 3176 hns3_parse_cfg(hcfg, desc); 3177 3178 return 0; 3179 } 3180 3181 static int 3182 hns3_parse_speed(int speed_cmd, uint32_t *speed) 3183 { 3184 switch (speed_cmd) { 3185 case HNS3_CFG_SPEED_10M: 3186 *speed = ETH_SPEED_NUM_10M; 3187 break; 3188 case HNS3_CFG_SPEED_100M: 3189 *speed = ETH_SPEED_NUM_100M; 3190 break; 3191 case HNS3_CFG_SPEED_1G: 3192 *speed = ETH_SPEED_NUM_1G; 3193 break; 3194 case HNS3_CFG_SPEED_10G: 3195 *speed = ETH_SPEED_NUM_10G; 3196 break; 3197 case HNS3_CFG_SPEED_25G: 3198 *speed = ETH_SPEED_NUM_25G; 3199 break; 3200 case HNS3_CFG_SPEED_40G: 3201 *speed = ETH_SPEED_NUM_40G; 3202 break; 3203 case HNS3_CFG_SPEED_50G: 3204 *speed = ETH_SPEED_NUM_50G; 3205 break; 3206 case HNS3_CFG_SPEED_100G: 3207 *speed = ETH_SPEED_NUM_100G; 3208 break; 3209 case HNS3_CFG_SPEED_200G: 3210 *speed = ETH_SPEED_NUM_200G; 3211 break; 3212 default: 3213 return -EINVAL; 3214 } 3215 3216 return 0; 3217 } 3218 3219 static void 3220 hns3_set_default_dev_specifications(struct hns3_hw *hw) 3221 { 3222 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 3223 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 3224 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 3225 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 3226 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 3227 } 3228 3229 static void 3230 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 3231 { 3232 struct hns3_dev_specs_0_cmd *req0; 3233 3234 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 3235 3236 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 3237 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 3238 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 3239 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 3240 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 3241 } 3242 3243 static int 3244 hns3_check_dev_specifications(struct hns3_hw *hw) 3245 { 3246 if (hw->rss_ind_tbl_size == 0 || 3247 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 3248 hns3_err(hw, "the size of hash lookup table configured (%u)" 3249 " exceeds the maximum(%u)", hw->rss_ind_tbl_size, 3250 HNS3_RSS_IND_TBL_SIZE_MAX); 3251 return -EINVAL; 3252 } 3253 3254 return 0; 3255 } 3256 3257 static int 3258 hns3_query_dev_specifications(struct hns3_hw *hw) 3259 { 3260 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 3261 int ret; 3262 int i; 3263 3264 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3265 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 3266 true); 3267 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3268 } 3269 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 3270 3271 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 3272 if (ret) 3273 return ret; 3274 3275 hns3_parse_dev_specifications(hw, desc); 3276 3277 return hns3_check_dev_specifications(hw); 3278 } 3279 3280 static int 3281 hns3_get_capability(struct hns3_hw *hw) 3282 { 3283 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3284 struct rte_pci_device *pci_dev; 3285 struct hns3_pf *pf = &hns->pf; 3286 struct rte_eth_dev *eth_dev; 3287 uint16_t device_id; 3288 uint8_t revision; 3289 int ret; 3290 3291 eth_dev = &rte_eth_devices[hw->data->port_id]; 3292 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3293 device_id = pci_dev->id.device_id; 3294 3295 if (device_id == HNS3_DEV_ID_25GE_RDMA || 3296 device_id == HNS3_DEV_ID_50GE_RDMA || 3297 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 3298 device_id == HNS3_DEV_ID_200G_RDMA) 3299 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 3300 3301 /* Get PCI revision id */ 3302 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 3303 HNS3_PCI_REVISION_ID); 3304 if (ret != HNS3_PCI_REVISION_ID_LEN) { 3305 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 3306 ret); 3307 return -EIO; 3308 } 3309 hw->revision = revision; 3310 3311 if (revision < PCI_REVISION_ID_HIP09_A) { 3312 hns3_set_default_dev_specifications(hw); 3313 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 3314 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 3315 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 3316 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; 3317 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 3318 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 3319 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; 3320 hw->rss_info.ipv6_sctp_offload_supported = false; 3321 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE; 3322 return 0; 3323 } 3324 3325 ret = hns3_query_dev_specifications(hw); 3326 if (ret) { 3327 PMD_INIT_LOG(ERR, 3328 "failed to query dev specifications, ret = %d", 3329 ret); 3330 return ret; 3331 } 3332 3333 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 3334 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 3335 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 3336 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; 3337 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 3338 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 3339 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; 3340 hw->rss_info.ipv6_sctp_offload_supported = true; 3341 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE; 3342 3343 return 0; 3344 } 3345 3346 static int 3347 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type) 3348 { 3349 int ret; 3350 3351 switch (media_type) { 3352 case HNS3_MEDIA_TYPE_COPPER: 3353 if (!hns3_dev_copper_supported(hw)) { 3354 PMD_INIT_LOG(ERR, 3355 "Media type is copper, not supported."); 3356 ret = -EOPNOTSUPP; 3357 } else { 3358 ret = 0; 3359 } 3360 break; 3361 case HNS3_MEDIA_TYPE_FIBER: 3362 ret = 0; 3363 break; 3364 case HNS3_MEDIA_TYPE_BACKPLANE: 3365 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported."); 3366 ret = -EOPNOTSUPP; 3367 break; 3368 default: 3369 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type); 3370 ret = -EINVAL; 3371 break; 3372 } 3373 3374 return ret; 3375 } 3376 3377 static int 3378 hns3_get_board_configuration(struct hns3_hw *hw) 3379 { 3380 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3381 struct hns3_pf *pf = &hns->pf; 3382 struct hns3_cfg cfg; 3383 int ret; 3384 3385 ret = hns3_get_board_cfg(hw, &cfg); 3386 if (ret) { 3387 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 3388 return ret; 3389 } 3390 3391 ret = hns3_check_media_type(hw, cfg.media_type); 3392 if (ret) 3393 return ret; 3394 3395 hw->mac.media_type = cfg.media_type; 3396 hw->rss_size_max = cfg.rss_size_max; 3397 hw->rss_dis_flag = false; 3398 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 3399 hw->mac.phy_addr = cfg.phy_addr; 3400 hw->mac.default_addr_setted = false; 3401 hw->num_tx_desc = cfg.tqp_desc_num; 3402 hw->num_rx_desc = cfg.tqp_desc_num; 3403 hw->dcb_info.num_pg = 1; 3404 hw->dcb_info.hw_pfc_map = 0; 3405 3406 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 3407 if (ret) { 3408 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d", 3409 cfg.default_speed, ret); 3410 return ret; 3411 } 3412 3413 pf->tc_max = cfg.tc_num; 3414 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 3415 PMD_INIT_LOG(WARNING, 3416 "Get TC num(%u) from flash, set TC num to 1", 3417 pf->tc_max); 3418 pf->tc_max = 1; 3419 } 3420 3421 /* Dev does not support DCB */ 3422 if (!hns3_dev_dcb_supported(hw)) { 3423 pf->tc_max = 1; 3424 pf->pfc_max = 0; 3425 } else 3426 pf->pfc_max = pf->tc_max; 3427 3428 hw->dcb_info.num_tc = 1; 3429 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 3430 hw->tqps_num / hw->dcb_info.num_tc); 3431 hns3_set_bit(hw->hw_tc_map, 0, 1); 3432 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 3433 3434 pf->wanted_umv_size = cfg.umv_space; 3435 3436 return ret; 3437 } 3438 3439 static int 3440 hns3_get_configuration(struct hns3_hw *hw) 3441 { 3442 int ret; 3443 3444 ret = hns3_query_function_status(hw); 3445 if (ret) { 3446 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 3447 return ret; 3448 } 3449 3450 /* Get device capability */ 3451 ret = hns3_get_capability(hw); 3452 if (ret) { 3453 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 3454 return ret; 3455 } 3456 3457 /* Get pf resource */ 3458 ret = hns3_query_pf_resource(hw); 3459 if (ret) { 3460 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 3461 return ret; 3462 } 3463 3464 ret = hns3_get_board_configuration(hw); 3465 if (ret) { 3466 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret); 3467 return ret; 3468 } 3469 3470 ret = hns3_query_dev_fec_info(hw); 3471 if (ret) 3472 PMD_INIT_LOG(ERR, 3473 "failed to query FEC information, ret = %d", ret); 3474 3475 return ret; 3476 } 3477 3478 static int 3479 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 3480 uint16_t tqp_vid, bool is_pf) 3481 { 3482 struct hns3_tqp_map_cmd *req; 3483 struct hns3_cmd_desc desc; 3484 int ret; 3485 3486 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 3487 3488 req = (struct hns3_tqp_map_cmd *)desc.data; 3489 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 3490 req->tqp_vf = func_id; 3491 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 3492 if (!is_pf) 3493 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 3494 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 3495 3496 ret = hns3_cmd_send(hw, &desc, 1); 3497 if (ret) 3498 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 3499 3500 return ret; 3501 } 3502 3503 static int 3504 hns3_map_tqp(struct hns3_hw *hw) 3505 { 3506 int ret; 3507 int i; 3508 3509 /* 3510 * In current version, VF is not supported when PF is driven by DPDK 3511 * driver, so we assign total tqps_num tqps allocated to this port 3512 * to PF. 3513 */ 3514 for (i = 0; i < hw->total_tqps_num; i++) { 3515 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true); 3516 if (ret) 3517 return ret; 3518 } 3519 3520 return 0; 3521 } 3522 3523 static int 3524 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 3525 { 3526 struct hns3_config_mac_speed_dup_cmd *req; 3527 struct hns3_cmd_desc desc; 3528 int ret; 3529 3530 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 3531 3532 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 3533 3534 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 3535 3536 switch (speed) { 3537 case ETH_SPEED_NUM_10M: 3538 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3539 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 3540 break; 3541 case ETH_SPEED_NUM_100M: 3542 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3543 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 3544 break; 3545 case ETH_SPEED_NUM_1G: 3546 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3547 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 3548 break; 3549 case ETH_SPEED_NUM_10G: 3550 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3551 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 3552 break; 3553 case ETH_SPEED_NUM_25G: 3554 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3555 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 3556 break; 3557 case ETH_SPEED_NUM_40G: 3558 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3559 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 3560 break; 3561 case ETH_SPEED_NUM_50G: 3562 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3563 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 3564 break; 3565 case ETH_SPEED_NUM_100G: 3566 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3567 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 3568 break; 3569 case ETH_SPEED_NUM_200G: 3570 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3571 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 3572 break; 3573 default: 3574 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 3575 return -EINVAL; 3576 } 3577 3578 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3579 3580 ret = hns3_cmd_send(hw, &desc, 1); 3581 if (ret) 3582 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3583 3584 return ret; 3585 } 3586 3587 static int 3588 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3589 { 3590 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3591 struct hns3_pf *pf = &hns->pf; 3592 struct hns3_priv_buf *priv; 3593 uint32_t i, total_size; 3594 3595 total_size = pf->pkt_buf_size; 3596 3597 /* alloc tx buffer for all enabled tc */ 3598 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3599 priv = &buf_alloc->priv_buf[i]; 3600 3601 if (hw->hw_tc_map & BIT(i)) { 3602 if (total_size < pf->tx_buf_size) 3603 return -ENOMEM; 3604 3605 priv->tx_buf_size = pf->tx_buf_size; 3606 } else 3607 priv->tx_buf_size = 0; 3608 3609 total_size -= priv->tx_buf_size; 3610 } 3611 3612 return 0; 3613 } 3614 3615 static int 3616 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3617 { 3618 /* TX buffer size is unit by 128 byte */ 3619 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3620 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3621 struct hns3_tx_buff_alloc_cmd *req; 3622 struct hns3_cmd_desc desc; 3623 uint32_t buf_size; 3624 uint32_t i; 3625 int ret; 3626 3627 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3628 3629 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3630 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3631 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3632 3633 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3634 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3635 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3636 } 3637 3638 ret = hns3_cmd_send(hw, &desc, 1); 3639 if (ret) 3640 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3641 3642 return ret; 3643 } 3644 3645 static int 3646 hns3_get_tc_num(struct hns3_hw *hw) 3647 { 3648 int cnt = 0; 3649 uint8_t i; 3650 3651 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3652 if (hw->hw_tc_map & BIT(i)) 3653 cnt++; 3654 return cnt; 3655 } 3656 3657 static uint32_t 3658 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3659 { 3660 struct hns3_priv_buf *priv; 3661 uint32_t rx_priv = 0; 3662 int i; 3663 3664 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3665 priv = &buf_alloc->priv_buf[i]; 3666 if (priv->enable) 3667 rx_priv += priv->buf_size; 3668 } 3669 return rx_priv; 3670 } 3671 3672 static uint32_t 3673 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3674 { 3675 uint32_t total_tx_size = 0; 3676 uint32_t i; 3677 3678 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3679 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3680 3681 return total_tx_size; 3682 } 3683 3684 /* Get the number of pfc enabled TCs, which have private buffer */ 3685 static int 3686 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3687 { 3688 struct hns3_priv_buf *priv; 3689 int cnt = 0; 3690 uint8_t i; 3691 3692 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3693 priv = &buf_alloc->priv_buf[i]; 3694 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3695 cnt++; 3696 } 3697 3698 return cnt; 3699 } 3700 3701 /* Get the number of pfc disabled TCs, which have private buffer */ 3702 static int 3703 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3704 struct hns3_pkt_buf_alloc *buf_alloc) 3705 { 3706 struct hns3_priv_buf *priv; 3707 int cnt = 0; 3708 uint8_t i; 3709 3710 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3711 priv = &buf_alloc->priv_buf[i]; 3712 if (hw->hw_tc_map & BIT(i) && 3713 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3714 cnt++; 3715 } 3716 3717 return cnt; 3718 } 3719 3720 static bool 3721 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3722 uint32_t rx_all) 3723 { 3724 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3725 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3726 struct hns3_pf *pf = &hns->pf; 3727 uint32_t shared_buf, aligned_mps; 3728 uint32_t rx_priv; 3729 uint8_t tc_num; 3730 uint8_t i; 3731 3732 tc_num = hns3_get_tc_num(hw); 3733 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3734 3735 if (hns3_dev_dcb_supported(hw)) 3736 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3737 pf->dv_buf_size; 3738 else 3739 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3740 + pf->dv_buf_size; 3741 3742 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3743 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3744 HNS3_BUF_SIZE_UNIT); 3745 3746 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3747 if (rx_all < rx_priv + shared_std) 3748 return false; 3749 3750 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3751 buf_alloc->s_buf.buf_size = shared_buf; 3752 if (hns3_dev_dcb_supported(hw)) { 3753 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3754 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3755 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3756 HNS3_BUF_SIZE_UNIT); 3757 } else { 3758 buf_alloc->s_buf.self.high = 3759 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3760 buf_alloc->s_buf.self.low = aligned_mps; 3761 } 3762 3763 if (hns3_dev_dcb_supported(hw)) { 3764 hi_thrd = shared_buf - pf->dv_buf_size; 3765 3766 if (tc_num <= NEED_RESERVE_TC_NUM) 3767 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT / 3768 BUF_MAX_PERCENT; 3769 3770 if (tc_num) 3771 hi_thrd = hi_thrd / tc_num; 3772 3773 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3774 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3775 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3776 } else { 3777 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3778 lo_thrd = aligned_mps; 3779 } 3780 3781 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3782 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3783 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3784 } 3785 3786 return true; 3787 } 3788 3789 static bool 3790 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3791 struct hns3_pkt_buf_alloc *buf_alloc) 3792 { 3793 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3794 struct hns3_pf *pf = &hns->pf; 3795 struct hns3_priv_buf *priv; 3796 uint32_t aligned_mps; 3797 uint32_t rx_all; 3798 uint8_t i; 3799 3800 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3801 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3802 3803 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3804 priv = &buf_alloc->priv_buf[i]; 3805 3806 priv->enable = 0; 3807 priv->wl.low = 0; 3808 priv->wl.high = 0; 3809 priv->buf_size = 0; 3810 3811 if (!(hw->hw_tc_map & BIT(i))) 3812 continue; 3813 3814 priv->enable = 1; 3815 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3816 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3817 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3818 HNS3_BUF_SIZE_UNIT); 3819 } else { 3820 priv->wl.low = 0; 3821 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3822 aligned_mps; 3823 } 3824 3825 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3826 } 3827 3828 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3829 } 3830 3831 static bool 3832 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3833 struct hns3_pkt_buf_alloc *buf_alloc) 3834 { 3835 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3836 struct hns3_pf *pf = &hns->pf; 3837 struct hns3_priv_buf *priv; 3838 int no_pfc_priv_num; 3839 uint32_t rx_all; 3840 uint8_t mask; 3841 int i; 3842 3843 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3844 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3845 3846 /* let the last to be cleared first */ 3847 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3848 priv = &buf_alloc->priv_buf[i]; 3849 mask = BIT((uint8_t)i); 3850 3851 if (hw->hw_tc_map & mask && 3852 !(hw->dcb_info.hw_pfc_map & mask)) { 3853 /* Clear the no pfc TC private buffer */ 3854 priv->wl.low = 0; 3855 priv->wl.high = 0; 3856 priv->buf_size = 0; 3857 priv->enable = 0; 3858 no_pfc_priv_num--; 3859 } 3860 3861 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3862 no_pfc_priv_num == 0) 3863 break; 3864 } 3865 3866 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3867 } 3868 3869 static bool 3870 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3871 struct hns3_pkt_buf_alloc *buf_alloc) 3872 { 3873 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3874 struct hns3_pf *pf = &hns->pf; 3875 struct hns3_priv_buf *priv; 3876 uint32_t rx_all; 3877 int pfc_priv_num; 3878 uint8_t mask; 3879 int i; 3880 3881 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3882 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3883 3884 /* let the last to be cleared first */ 3885 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3886 priv = &buf_alloc->priv_buf[i]; 3887 mask = BIT((uint8_t)i); 3888 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) { 3889 /* Reduce the number of pfc TC with private buffer */ 3890 priv->wl.low = 0; 3891 priv->enable = 0; 3892 priv->wl.high = 0; 3893 priv->buf_size = 0; 3894 pfc_priv_num--; 3895 } 3896 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3897 pfc_priv_num == 0) 3898 break; 3899 } 3900 3901 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3902 } 3903 3904 static bool 3905 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3906 struct hns3_pkt_buf_alloc *buf_alloc) 3907 { 3908 #define COMPENSATE_BUFFER 0x3C00 3909 #define COMPENSATE_HALF_MPS_NUM 5 3910 #define PRIV_WL_GAP 0x1800 3911 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3912 struct hns3_pf *pf = &hns->pf; 3913 uint32_t tc_num = hns3_get_tc_num(hw); 3914 uint32_t half_mps = pf->mps >> 1; 3915 struct hns3_priv_buf *priv; 3916 uint32_t min_rx_priv; 3917 uint32_t rx_priv; 3918 uint8_t i; 3919 3920 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3921 if (tc_num) 3922 rx_priv = rx_priv / tc_num; 3923 3924 if (tc_num <= NEED_RESERVE_TC_NUM) 3925 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3926 3927 /* 3928 * Minimum value of private buffer in rx direction (min_rx_priv) is 3929 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3930 * buffer if rx_priv is greater than min_rx_priv. 3931 */ 3932 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3933 COMPENSATE_HALF_MPS_NUM * half_mps; 3934 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3935 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3936 3937 if (rx_priv < min_rx_priv) 3938 return false; 3939 3940 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3941 priv = &buf_alloc->priv_buf[i]; 3942 priv->enable = 0; 3943 priv->wl.low = 0; 3944 priv->wl.high = 0; 3945 priv->buf_size = 0; 3946 3947 if (!(hw->hw_tc_map & BIT(i))) 3948 continue; 3949 3950 priv->enable = 1; 3951 priv->buf_size = rx_priv; 3952 priv->wl.high = rx_priv - pf->dv_buf_size; 3953 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3954 } 3955 3956 buf_alloc->s_buf.buf_size = 0; 3957 3958 return true; 3959 } 3960 3961 /* 3962 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3963 * @hw: pointer to struct hns3_hw 3964 * @buf_alloc: pointer to buffer calculation data 3965 * @return: 0: calculate sucessful, negative: fail 3966 */ 3967 static int 3968 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3969 { 3970 /* When DCB is not supported, rx private buffer is not allocated. */ 3971 if (!hns3_dev_dcb_supported(hw)) { 3972 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3973 struct hns3_pf *pf = &hns->pf; 3974 uint32_t rx_all = pf->pkt_buf_size; 3975 3976 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3977 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3978 return -ENOMEM; 3979 3980 return 0; 3981 } 3982 3983 /* 3984 * Try to allocate privated packet buffer for all TCs without share 3985 * buffer. 3986 */ 3987 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3988 return 0; 3989 3990 /* 3991 * Try to allocate privated packet buffer for all TCs with share 3992 * buffer. 3993 */ 3994 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3995 return 0; 3996 3997 /* 3998 * For different application scenes, the enabled port number, TC number 3999 * and no_drop TC number are different. In order to obtain the better 4000 * performance, software could allocate the buffer size and configure 4001 * the waterline by trying to decrease the private buffer size according 4002 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc 4003 * enabled tc. 4004 */ 4005 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 4006 return 0; 4007 4008 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 4009 return 0; 4010 4011 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 4012 return 0; 4013 4014 return -ENOMEM; 4015 } 4016 4017 static int 4018 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4019 { 4020 struct hns3_rx_priv_buff_cmd *req; 4021 struct hns3_cmd_desc desc; 4022 uint32_t buf_size; 4023 int ret; 4024 int i; 4025 4026 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 4027 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 4028 4029 /* Alloc private buffer TCs */ 4030 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 4031 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 4032 4033 req->buf_num[i] = 4034 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 4035 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 4036 } 4037 4038 buf_size = buf_alloc->s_buf.buf_size; 4039 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 4040 (1 << HNS3_TC0_PRI_BUF_EN_B)); 4041 4042 ret = hns3_cmd_send(hw, &desc, 1); 4043 if (ret) 4044 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 4045 4046 return ret; 4047 } 4048 4049 static int 4050 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4051 { 4052 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 4053 struct hns3_rx_priv_wl_buf *req; 4054 struct hns3_priv_buf *priv; 4055 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 4056 int i, j; 4057 int ret; 4058 4059 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 4060 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 4061 false); 4062 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 4063 4064 /* The first descriptor set the NEXT bit to 1 */ 4065 if (i == 0) 4066 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4067 else 4068 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4069 4070 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 4071 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 4072 4073 priv = &buf_alloc->priv_buf[idx]; 4074 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 4075 HNS3_BUF_UNIT_S); 4076 req->tc_wl[j].high |= 4077 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4078 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 4079 HNS3_BUF_UNIT_S); 4080 req->tc_wl[j].low |= 4081 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4082 } 4083 } 4084 4085 /* Send 2 descriptor at one time */ 4086 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 4087 if (ret) 4088 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 4089 ret); 4090 return ret; 4091 } 4092 4093 static int 4094 hns3_common_thrd_config(struct hns3_hw *hw, 4095 struct hns3_pkt_buf_alloc *buf_alloc) 4096 { 4097 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 4098 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 4099 struct hns3_rx_com_thrd *req; 4100 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 4101 struct hns3_tc_thrd *tc; 4102 int tc_idx; 4103 int i, j; 4104 int ret; 4105 4106 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 4107 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 4108 false); 4109 req = (struct hns3_rx_com_thrd *)&desc[i].data; 4110 4111 /* The first descriptor set the NEXT bit to 1 */ 4112 if (i == 0) 4113 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4114 else 4115 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4116 4117 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 4118 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 4119 tc = &s_buf->tc_thrd[tc_idx]; 4120 4121 req->com_thrd[j].high = 4122 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 4123 req->com_thrd[j].high |= 4124 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4125 req->com_thrd[j].low = 4126 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 4127 req->com_thrd[j].low |= 4128 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4129 } 4130 } 4131 4132 /* Send 2 descriptors at one time */ 4133 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 4134 if (ret) 4135 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 4136 4137 return ret; 4138 } 4139 4140 static int 4141 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4142 { 4143 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 4144 struct hns3_rx_com_wl *req; 4145 struct hns3_cmd_desc desc; 4146 int ret; 4147 4148 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 4149 4150 req = (struct hns3_rx_com_wl *)desc.data; 4151 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 4152 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4153 4154 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 4155 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4156 4157 ret = hns3_cmd_send(hw, &desc, 1); 4158 if (ret) 4159 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 4160 4161 return ret; 4162 } 4163 4164 int 4165 hns3_buffer_alloc(struct hns3_hw *hw) 4166 { 4167 struct hns3_pkt_buf_alloc pkt_buf; 4168 int ret; 4169 4170 memset(&pkt_buf, 0, sizeof(pkt_buf)); 4171 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 4172 if (ret) { 4173 PMD_INIT_LOG(ERR, 4174 "could not calc tx buffer size for all TCs %d", 4175 ret); 4176 return ret; 4177 } 4178 4179 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 4180 if (ret) { 4181 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 4182 return ret; 4183 } 4184 4185 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 4186 if (ret) { 4187 PMD_INIT_LOG(ERR, 4188 "could not calc rx priv buffer size for all TCs %d", 4189 ret); 4190 return ret; 4191 } 4192 4193 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 4194 if (ret) { 4195 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 4196 return ret; 4197 } 4198 4199 if (hns3_dev_dcb_supported(hw)) { 4200 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 4201 if (ret) { 4202 PMD_INIT_LOG(ERR, 4203 "could not configure rx private waterline %d", 4204 ret); 4205 return ret; 4206 } 4207 4208 ret = hns3_common_thrd_config(hw, &pkt_buf); 4209 if (ret) { 4210 PMD_INIT_LOG(ERR, 4211 "could not configure common threshold %d", 4212 ret); 4213 return ret; 4214 } 4215 } 4216 4217 ret = hns3_common_wl_config(hw, &pkt_buf); 4218 if (ret) 4219 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 4220 ret); 4221 4222 return ret; 4223 } 4224 4225 static int 4226 hns3_mac_init(struct hns3_hw *hw) 4227 { 4228 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4229 struct hns3_mac *mac = &hw->mac; 4230 struct hns3_pf *pf = &hns->pf; 4231 int ret; 4232 4233 pf->support_sfp_query = true; 4234 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 4235 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 4236 if (ret) { 4237 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 4238 return ret; 4239 } 4240 4241 mac->link_status = ETH_LINK_DOWN; 4242 4243 return hns3_config_mtu(hw, pf->mps); 4244 } 4245 4246 static int 4247 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 4248 { 4249 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 4250 #define HNS3_ETHERTYPE_ALREADY_ADD 1 4251 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 4252 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 4253 int return_status; 4254 4255 if (cmdq_resp) { 4256 PMD_INIT_LOG(ERR, 4257 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 4258 cmdq_resp); 4259 return -EIO; 4260 } 4261 4262 switch (resp_code) { 4263 case HNS3_ETHERTYPE_SUCCESS_ADD: 4264 case HNS3_ETHERTYPE_ALREADY_ADD: 4265 return_status = 0; 4266 break; 4267 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 4268 PMD_INIT_LOG(ERR, 4269 "add mac ethertype failed for manager table overflow."); 4270 return_status = -EIO; 4271 break; 4272 case HNS3_ETHERTYPE_KEY_CONFLICT: 4273 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 4274 return_status = -EIO; 4275 break; 4276 default: 4277 PMD_INIT_LOG(ERR, 4278 "add mac ethertype failed for undefined, code=%u.", 4279 resp_code); 4280 return_status = -EIO; 4281 break; 4282 } 4283 4284 return return_status; 4285 } 4286 4287 static int 4288 hns3_add_mgr_tbl(struct hns3_hw *hw, 4289 const struct hns3_mac_mgr_tbl_entry_cmd *req) 4290 { 4291 struct hns3_cmd_desc desc; 4292 uint8_t resp_code; 4293 uint16_t retval; 4294 int ret; 4295 4296 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 4297 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 4298 4299 ret = hns3_cmd_send(hw, &desc, 1); 4300 if (ret) { 4301 PMD_INIT_LOG(ERR, 4302 "add mac ethertype failed for cmd_send, ret =%d.", 4303 ret); 4304 return ret; 4305 } 4306 4307 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 4308 retval = rte_le_to_cpu_16(desc.retval); 4309 4310 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 4311 } 4312 4313 static void 4314 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 4315 int *table_item_num) 4316 { 4317 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 4318 4319 /* 4320 * In current version, we add one item in management table as below: 4321 * 0x0180C200000E -- LLDP MC address 4322 */ 4323 tbl = mgr_table; 4324 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 4325 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 4326 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 4327 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 4328 tbl->i_port_bitmap = 0x1; 4329 *table_item_num = 1; 4330 } 4331 4332 static int 4333 hns3_init_mgr_tbl(struct hns3_hw *hw) 4334 { 4335 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 4336 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 4337 int table_item_num; 4338 int ret; 4339 int i; 4340 4341 memset(mgr_table, 0, sizeof(mgr_table)); 4342 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 4343 for (i = 0; i < table_item_num; i++) { 4344 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 4345 if (ret) { 4346 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 4347 ret); 4348 return ret; 4349 } 4350 } 4351 4352 return 0; 4353 } 4354 4355 static void 4356 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 4357 bool en_mc, bool en_bc, int vport_id) 4358 { 4359 if (!param) 4360 return; 4361 4362 memset(param, 0, sizeof(struct hns3_promisc_param)); 4363 if (en_uc) 4364 param->enable = HNS3_PROMISC_EN_UC; 4365 if (en_mc) 4366 param->enable |= HNS3_PROMISC_EN_MC; 4367 if (en_bc) 4368 param->enable |= HNS3_PROMISC_EN_BC; 4369 param->vf_id = vport_id; 4370 } 4371 4372 static int 4373 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 4374 { 4375 struct hns3_promisc_cfg_cmd *req; 4376 struct hns3_cmd_desc desc; 4377 int ret; 4378 4379 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 4380 4381 req = (struct hns3_promisc_cfg_cmd *)desc.data; 4382 req->vf_id = param->vf_id; 4383 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 4384 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 4385 4386 ret = hns3_cmd_send(hw, &desc, 1); 4387 if (ret) 4388 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 4389 4390 return ret; 4391 } 4392 4393 static int 4394 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 4395 { 4396 struct hns3_promisc_param param; 4397 bool en_bc_pmc = true; 4398 uint8_t vf_id; 4399 4400 /* 4401 * In current version VF is not supported when PF is driven by DPDK 4402 * driver, just need to configure parameters for PF vport. 4403 */ 4404 vf_id = HNS3_PF_FUNC_ID; 4405 4406 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 4407 return hns3_cmd_set_promisc_mode(hw, ¶m); 4408 } 4409 4410 static int 4411 hns3_promisc_init(struct hns3_hw *hw) 4412 { 4413 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4414 struct hns3_pf *pf = &hns->pf; 4415 struct hns3_promisc_param param; 4416 uint16_t func_id; 4417 int ret; 4418 4419 ret = hns3_set_promisc_mode(hw, false, false); 4420 if (ret) { 4421 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 4422 return ret; 4423 } 4424 4425 /* 4426 * In current version VFs are not supported when PF is driven by DPDK 4427 * driver. After PF has been taken over by DPDK, the original VF will 4428 * be invalid. So, there is a possibility of entry residues. It should 4429 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 4430 * during init. 4431 */ 4432 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 4433 hns3_promisc_param_init(¶m, false, false, false, func_id); 4434 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4435 if (ret) { 4436 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode," 4437 " ret = %d", func_id, ret); 4438 return ret; 4439 } 4440 } 4441 4442 return 0; 4443 } 4444 4445 static void 4446 hns3_promisc_uninit(struct hns3_hw *hw) 4447 { 4448 struct hns3_promisc_param param; 4449 uint16_t func_id; 4450 int ret; 4451 4452 func_id = HNS3_PF_FUNC_ID; 4453 4454 /* 4455 * In current version VFs are not supported when PF is driven by 4456 * DPDK driver, and VFs' promisc mode status has been cleared during 4457 * init and their status will not change. So just clear PF's promisc 4458 * mode status during uninit. 4459 */ 4460 hns3_promisc_param_init(¶m, false, false, false, func_id); 4461 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4462 if (ret) 4463 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 4464 " uninit, ret = %d", ret); 4465 } 4466 4467 static int 4468 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 4469 { 4470 bool allmulti = dev->data->all_multicast ? true : false; 4471 struct hns3_adapter *hns = dev->data->dev_private; 4472 struct hns3_hw *hw = &hns->hw; 4473 uint64_t offloads; 4474 int err; 4475 int ret; 4476 4477 rte_spinlock_lock(&hw->lock); 4478 ret = hns3_set_promisc_mode(hw, true, true); 4479 if (ret) { 4480 rte_spinlock_unlock(&hw->lock); 4481 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 4482 ret); 4483 return ret; 4484 } 4485 4486 /* 4487 * When promiscuous mode was enabled, disable the vlan filter to let 4488 * all packets coming in in the receiving direction. 4489 */ 4490 offloads = dev->data->dev_conf.rxmode.offloads; 4491 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4492 ret = hns3_enable_vlan_filter(hns, false); 4493 if (ret) { 4494 hns3_err(hw, "failed to enable promiscuous mode due to " 4495 "failure to disable vlan filter, ret = %d", 4496 ret); 4497 err = hns3_set_promisc_mode(hw, false, allmulti); 4498 if (err) 4499 hns3_err(hw, "failed to restore promiscuous " 4500 "status after disable vlan filter " 4501 "failed during enabling promiscuous " 4502 "mode, ret = %d", ret); 4503 } 4504 } 4505 4506 rte_spinlock_unlock(&hw->lock); 4507 4508 return ret; 4509 } 4510 4511 static int 4512 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 4513 { 4514 bool allmulti = dev->data->all_multicast ? true : false; 4515 struct hns3_adapter *hns = dev->data->dev_private; 4516 struct hns3_hw *hw = &hns->hw; 4517 uint64_t offloads; 4518 int err; 4519 int ret; 4520 4521 /* If now in all_multicast mode, must remain in all_multicast mode. */ 4522 rte_spinlock_lock(&hw->lock); 4523 ret = hns3_set_promisc_mode(hw, false, allmulti); 4524 if (ret) { 4525 rte_spinlock_unlock(&hw->lock); 4526 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 4527 ret); 4528 return ret; 4529 } 4530 /* when promiscuous mode was disabled, restore the vlan filter status */ 4531 offloads = dev->data->dev_conf.rxmode.offloads; 4532 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4533 ret = hns3_enable_vlan_filter(hns, true); 4534 if (ret) { 4535 hns3_err(hw, "failed to disable promiscuous mode due to" 4536 " failure to restore vlan filter, ret = %d", 4537 ret); 4538 err = hns3_set_promisc_mode(hw, true, true); 4539 if (err) 4540 hns3_err(hw, "failed to restore promiscuous " 4541 "status after enabling vlan filter " 4542 "failed during disabling promiscuous " 4543 "mode, ret = %d", ret); 4544 } 4545 } 4546 rte_spinlock_unlock(&hw->lock); 4547 4548 return ret; 4549 } 4550 4551 static int 4552 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 4553 { 4554 struct hns3_adapter *hns = dev->data->dev_private; 4555 struct hns3_hw *hw = &hns->hw; 4556 int ret; 4557 4558 if (dev->data->promiscuous) 4559 return 0; 4560 4561 rte_spinlock_lock(&hw->lock); 4562 ret = hns3_set_promisc_mode(hw, false, true); 4563 rte_spinlock_unlock(&hw->lock); 4564 if (ret) 4565 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 4566 ret); 4567 4568 return ret; 4569 } 4570 4571 static int 4572 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 4573 { 4574 struct hns3_adapter *hns = dev->data->dev_private; 4575 struct hns3_hw *hw = &hns->hw; 4576 int ret; 4577 4578 /* If now in promiscuous mode, must remain in all_multicast mode. */ 4579 if (dev->data->promiscuous) 4580 return 0; 4581 4582 rte_spinlock_lock(&hw->lock); 4583 ret = hns3_set_promisc_mode(hw, false, false); 4584 rte_spinlock_unlock(&hw->lock); 4585 if (ret) 4586 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4587 ret); 4588 4589 return ret; 4590 } 4591 4592 static int 4593 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4594 { 4595 struct hns3_hw *hw = &hns->hw; 4596 bool allmulti = hw->data->all_multicast ? true : false; 4597 int ret; 4598 4599 if (hw->data->promiscuous) { 4600 ret = hns3_set_promisc_mode(hw, true, true); 4601 if (ret) 4602 hns3_err(hw, "failed to restore promiscuous mode, " 4603 "ret = %d", ret); 4604 return ret; 4605 } 4606 4607 ret = hns3_set_promisc_mode(hw, false, allmulti); 4608 if (ret) 4609 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4610 ret); 4611 return ret; 4612 } 4613 4614 static int 4615 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) 4616 { 4617 struct hns3_sfp_info_cmd *resp; 4618 struct hns3_cmd_desc desc; 4619 int ret; 4620 4621 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 4622 resp = (struct hns3_sfp_info_cmd *)desc.data; 4623 resp->query_type = HNS3_ACTIVE_QUERY; 4624 4625 ret = hns3_cmd_send(hw, &desc, 1); 4626 if (ret == -EOPNOTSUPP) { 4627 hns3_warn(hw, "firmware does not support get SFP info," 4628 " ret = %d.", ret); 4629 return ret; 4630 } else if (ret) { 4631 hns3_err(hw, "get sfp info failed, ret = %d.", ret); 4632 return ret; 4633 } 4634 4635 /* 4636 * In some case, the speed of MAC obtained from firmware may be 0, it 4637 * shouldn't be set to mac->speed. 4638 */ 4639 if (!rte_le_to_cpu_32(resp->sfp_speed)) 4640 return 0; 4641 4642 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed); 4643 /* 4644 * if resp->supported_speed is 0, it means it's an old version 4645 * firmware, do not update these params. 4646 */ 4647 if (resp->supported_speed) { 4648 mac_info->query_type = HNS3_ACTIVE_QUERY; 4649 mac_info->supported_speed = 4650 rte_le_to_cpu_32(resp->supported_speed); 4651 mac_info->support_autoneg = resp->autoneg_ability; 4652 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED 4653 : ETH_LINK_AUTONEG; 4654 } else { 4655 mac_info->query_type = HNS3_DEFAULT_QUERY; 4656 } 4657 4658 return 0; 4659 } 4660 4661 static uint8_t 4662 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4663 { 4664 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 4665 duplex = ETH_LINK_FULL_DUPLEX; 4666 4667 return duplex; 4668 } 4669 4670 static int 4671 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4672 { 4673 struct hns3_mac *mac = &hw->mac; 4674 int ret; 4675 4676 duplex = hns3_check_speed_dup(duplex, speed); 4677 if (mac->link_speed == speed && mac->link_duplex == duplex) 4678 return 0; 4679 4680 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4681 if (ret) 4682 return ret; 4683 4684 ret = hns3_port_shaper_update(hw, speed); 4685 if (ret) 4686 return ret; 4687 4688 mac->link_speed = speed; 4689 mac->link_duplex = duplex; 4690 4691 return 0; 4692 } 4693 4694 static int 4695 hns3_update_fiber_link_info(struct hns3_hw *hw) 4696 { 4697 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 4698 struct hns3_mac *mac = &hw->mac; 4699 struct hns3_mac mac_info; 4700 int ret; 4701 4702 /* If firmware do not support get SFP/qSFP speed, return directly */ 4703 if (!pf->support_sfp_query) 4704 return 0; 4705 4706 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4707 ret = hns3_get_sfp_info(hw, &mac_info); 4708 if (ret == -EOPNOTSUPP) { 4709 pf->support_sfp_query = false; 4710 return ret; 4711 } else if (ret) 4712 return ret; 4713 4714 /* Do nothing if no SFP */ 4715 if (mac_info.link_speed == ETH_SPEED_NUM_NONE) 4716 return 0; 4717 4718 /* 4719 * If query_type is HNS3_ACTIVE_QUERY, it is no need 4720 * to reconfigure the speed of MAC. Otherwise, it indicates 4721 * that the current firmware only supports to obtain the 4722 * speed of the SFP, and the speed of MAC needs to reconfigure. 4723 */ 4724 mac->query_type = mac_info.query_type; 4725 if (mac->query_type == HNS3_ACTIVE_QUERY) { 4726 if (mac_info.link_speed != mac->link_speed) { 4727 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4728 if (ret) 4729 return ret; 4730 } 4731 4732 mac->link_speed = mac_info.link_speed; 4733 mac->supported_speed = mac_info.supported_speed; 4734 mac->support_autoneg = mac_info.support_autoneg; 4735 mac->link_autoneg = mac_info.link_autoneg; 4736 4737 return 0; 4738 } 4739 4740 /* Config full duplex for SFP */ 4741 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, 4742 ETH_LINK_FULL_DUPLEX); 4743 } 4744 4745 static void 4746 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac) 4747 { 4748 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f 4749 4750 struct hns3_phy_params_bd0_cmd *req; 4751 uint32_t supported; 4752 4753 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 4754 mac->link_speed = rte_le_to_cpu_32(req->speed); 4755 mac->link_duplex = hns3_get_bit(req->duplex, 4756 HNS3_PHY_DUPLEX_CFG_B); 4757 mac->link_autoneg = hns3_get_bit(req->autoneg, 4758 HNS3_PHY_AUTONEG_CFG_B); 4759 mac->advertising = rte_le_to_cpu_32(req->advertising); 4760 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising); 4761 supported = rte_le_to_cpu_32(req->supported); 4762 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK; 4763 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT); 4764 } 4765 4766 static int 4767 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac) 4768 { 4769 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 4770 uint16_t i; 4771 int ret; 4772 4773 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 4774 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 4775 true); 4776 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4777 } 4778 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true); 4779 4780 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 4781 if (ret) { 4782 hns3_err(hw, "get phy parameters failed, ret = %d.", ret); 4783 return ret; 4784 } 4785 4786 hns3_parse_copper_phy_params(desc, mac); 4787 4788 return 0; 4789 } 4790 4791 static int 4792 hns3_update_copper_link_info(struct hns3_hw *hw) 4793 { 4794 struct hns3_mac *mac = &hw->mac; 4795 struct hns3_mac mac_info; 4796 int ret; 4797 4798 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4799 ret = hns3_get_copper_phy_params(hw, &mac_info); 4800 if (ret) 4801 return ret; 4802 4803 if (mac_info.link_speed != mac->link_speed) { 4804 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4805 if (ret) 4806 return ret; 4807 } 4808 4809 mac->link_speed = mac_info.link_speed; 4810 mac->link_duplex = mac_info.link_duplex; 4811 mac->link_autoneg = mac_info.link_autoneg; 4812 mac->supported_speed = mac_info.supported_speed; 4813 mac->advertising = mac_info.advertising; 4814 mac->lp_advertising = mac_info.lp_advertising; 4815 mac->support_autoneg = mac_info.support_autoneg; 4816 4817 return 0; 4818 } 4819 4820 static int 4821 hns3_update_link_info(struct rte_eth_dev *eth_dev) 4822 { 4823 struct hns3_adapter *hns = eth_dev->data->dev_private; 4824 struct hns3_hw *hw = &hns->hw; 4825 int ret = 0; 4826 4827 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) 4828 ret = hns3_update_copper_link_info(hw); 4829 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) 4830 ret = hns3_update_fiber_link_info(hw); 4831 4832 return ret; 4833 } 4834 4835 static int 4836 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4837 { 4838 struct hns3_config_mac_mode_cmd *req; 4839 struct hns3_cmd_desc desc; 4840 uint32_t loop_en = 0; 4841 uint8_t val = 0; 4842 int ret; 4843 4844 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4845 4846 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4847 if (enable) 4848 val = 1; 4849 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4850 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4851 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4852 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4853 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4854 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4855 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4856 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4857 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4858 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4859 4860 /* 4861 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4862 * when receiving frames. Otherwise, CRC will be stripped. 4863 */ 4864 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 4865 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4866 else 4867 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4868 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4869 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4870 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4871 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4872 4873 ret = hns3_cmd_send(hw, &desc, 1); 4874 if (ret) 4875 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4876 4877 return ret; 4878 } 4879 4880 static int 4881 hns3_get_mac_link_status(struct hns3_hw *hw) 4882 { 4883 struct hns3_link_status_cmd *req; 4884 struct hns3_cmd_desc desc; 4885 int link_status; 4886 int ret; 4887 4888 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4889 ret = hns3_cmd_send(hw, &desc, 1); 4890 if (ret) { 4891 hns3_err(hw, "get link status cmd failed %d", ret); 4892 return ETH_LINK_DOWN; 4893 } 4894 4895 req = (struct hns3_link_status_cmd *)desc.data; 4896 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4897 4898 return !!link_status; 4899 } 4900 4901 static bool 4902 hns3_update_link_status(struct hns3_hw *hw) 4903 { 4904 int state; 4905 4906 state = hns3_get_mac_link_status(hw); 4907 if (state != hw->mac.link_status) { 4908 hw->mac.link_status = state; 4909 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4910 return true; 4911 } 4912 4913 return false; 4914 } 4915 4916 void 4917 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query) 4918 { 4919 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4920 struct rte_eth_link new_link; 4921 int ret; 4922 4923 if (query) 4924 hns3_update_port_link_info(dev); 4925 4926 memset(&new_link, 0, sizeof(new_link)); 4927 hns3_setup_linkstatus(dev, &new_link); 4928 4929 ret = rte_eth_linkstatus_set(dev, &new_link); 4930 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0) 4931 hns3_start_report_lse(dev); 4932 } 4933 4934 static void 4935 hns3_service_handler(void *param) 4936 { 4937 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4938 struct hns3_adapter *hns = eth_dev->data->dev_private; 4939 struct hns3_hw *hw = &hns->hw; 4940 4941 if (!hns3_is_reset_pending(hns)) 4942 hns3_update_linkstatus_and_event(hw, true); 4943 else 4944 hns3_warn(hw, "Cancel the query when reset is pending"); 4945 4946 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4947 } 4948 4949 static int 4950 hns3_init_hardware(struct hns3_adapter *hns) 4951 { 4952 struct hns3_hw *hw = &hns->hw; 4953 int ret; 4954 4955 ret = hns3_map_tqp(hw); 4956 if (ret) { 4957 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4958 return ret; 4959 } 4960 4961 ret = hns3_init_umv_space(hw); 4962 if (ret) { 4963 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4964 return ret; 4965 } 4966 4967 ret = hns3_mac_init(hw); 4968 if (ret) { 4969 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4970 goto err_mac_init; 4971 } 4972 4973 ret = hns3_init_mgr_tbl(hw); 4974 if (ret) { 4975 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4976 goto err_mac_init; 4977 } 4978 4979 ret = hns3_promisc_init(hw); 4980 if (ret) { 4981 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4982 ret); 4983 goto err_mac_init; 4984 } 4985 4986 ret = hns3_init_vlan_config(hns); 4987 if (ret) { 4988 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4989 goto err_mac_init; 4990 } 4991 4992 ret = hns3_dcb_init(hw); 4993 if (ret) { 4994 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4995 goto err_mac_init; 4996 } 4997 4998 ret = hns3_init_fd_config(hns); 4999 if (ret) { 5000 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 5001 goto err_mac_init; 5002 } 5003 5004 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 5005 if (ret) { 5006 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 5007 goto err_mac_init; 5008 } 5009 5010 ret = hns3_config_gro(hw, false); 5011 if (ret) { 5012 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 5013 goto err_mac_init; 5014 } 5015 5016 /* 5017 * In the initialization clearing the all hardware mapping relationship 5018 * configurations between queues and interrupt vectors is needed, so 5019 * some error caused by the residual configurations, such as the 5020 * unexpected interrupt, can be avoid. 5021 */ 5022 ret = hns3_init_ring_with_vector(hw); 5023 if (ret) { 5024 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 5025 goto err_mac_init; 5026 } 5027 5028 return 0; 5029 5030 err_mac_init: 5031 hns3_uninit_umv_space(hw); 5032 return ret; 5033 } 5034 5035 static int 5036 hns3_clear_hw(struct hns3_hw *hw) 5037 { 5038 struct hns3_cmd_desc desc; 5039 int ret; 5040 5041 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 5042 5043 ret = hns3_cmd_send(hw, &desc, 1); 5044 if (ret && ret != -EOPNOTSUPP) 5045 return ret; 5046 5047 return 0; 5048 } 5049 5050 static void 5051 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 5052 { 5053 uint32_t val; 5054 5055 /* 5056 * The new firmware support report more hardware error types by 5057 * msix mode. These errors are defined as RAS errors in hardware 5058 * and belong to a different type from the MSI-x errors processed 5059 * by the network driver. 5060 * 5061 * Network driver should open the new error report on initialization. 5062 */ 5063 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5064 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 5065 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 5066 } 5067 5068 static uint32_t 5069 hns3_set_firber_default_support_speed(struct hns3_hw *hw) 5070 { 5071 struct hns3_mac *mac = &hw->mac; 5072 5073 switch (mac->link_speed) { 5074 case ETH_SPEED_NUM_1G: 5075 return HNS3_FIBER_LINK_SPEED_1G_BIT; 5076 case ETH_SPEED_NUM_10G: 5077 return HNS3_FIBER_LINK_SPEED_10G_BIT; 5078 case ETH_SPEED_NUM_25G: 5079 return HNS3_FIBER_LINK_SPEED_25G_BIT; 5080 case ETH_SPEED_NUM_40G: 5081 return HNS3_FIBER_LINK_SPEED_40G_BIT; 5082 case ETH_SPEED_NUM_50G: 5083 return HNS3_FIBER_LINK_SPEED_50G_BIT; 5084 case ETH_SPEED_NUM_100G: 5085 return HNS3_FIBER_LINK_SPEED_100G_BIT; 5086 case ETH_SPEED_NUM_200G: 5087 return HNS3_FIBER_LINK_SPEED_200G_BIT; 5088 default: 5089 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed); 5090 return 0; 5091 } 5092 } 5093 5094 /* 5095 * Validity of supported_speed for firber and copper media type can be 5096 * guaranteed by the following policy: 5097 * Copper: 5098 * Although the initialization of the phy in the firmware may not be 5099 * completed, the firmware can guarantees that the supported_speed is 5100 * an valid value. 5101 * Firber: 5102 * If the version of firmware supports the acitive query way of the 5103 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained 5104 * through it. If unsupported, use the SFP's speed as the value of the 5105 * supported_speed. 5106 */ 5107 static int 5108 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev) 5109 { 5110 struct hns3_adapter *hns = eth_dev->data->dev_private; 5111 struct hns3_hw *hw = &hns->hw; 5112 struct hns3_mac *mac = &hw->mac; 5113 int ret; 5114 5115 ret = hns3_update_link_info(eth_dev); 5116 if (ret) 5117 return ret; 5118 5119 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) { 5120 /* 5121 * Some firmware does not support the report of supported_speed, 5122 * and only report the effective speed of SFP. In this case, it 5123 * is necessary to use the SFP's speed as the supported_speed. 5124 */ 5125 if (mac->supported_speed == 0) 5126 mac->supported_speed = 5127 hns3_set_firber_default_support_speed(hw); 5128 } 5129 5130 return 0; 5131 } 5132 5133 static void 5134 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns) 5135 { 5136 struct hns3_mac *mac = &hns->hw.mac; 5137 5138 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) { 5139 hns->pf.support_fc_autoneg = true; 5140 return; 5141 } 5142 5143 /* 5144 * Flow control auto-negotiation requires the cooperation of the driver 5145 * and firmware. Currently, the optical port does not support flow 5146 * control auto-negotiation. 5147 */ 5148 hns->pf.support_fc_autoneg = false; 5149 } 5150 5151 static int 5152 hns3_init_pf(struct rte_eth_dev *eth_dev) 5153 { 5154 struct rte_device *dev = eth_dev->device; 5155 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5156 struct hns3_adapter *hns = eth_dev->data->dev_private; 5157 struct hns3_hw *hw = &hns->hw; 5158 int ret; 5159 5160 PMD_INIT_FUNC_TRACE(); 5161 5162 /* Get hardware io base address from pcie BAR2 IO space */ 5163 hw->io_base = pci_dev->mem_resource[2].addr; 5164 5165 /* Firmware command queue initialize */ 5166 ret = hns3_cmd_init_queue(hw); 5167 if (ret) { 5168 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 5169 goto err_cmd_init_queue; 5170 } 5171 5172 hns3_clear_all_event_cause(hw); 5173 5174 /* Firmware command initialize */ 5175 ret = hns3_cmd_init(hw); 5176 if (ret) { 5177 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 5178 goto err_cmd_init; 5179 } 5180 5181 /* 5182 * To ensure that the hardware environment is clean during 5183 * initialization, the driver actively clear the hardware environment 5184 * during initialization, including PF and corresponding VFs' vlan, mac, 5185 * flow table configurations, etc. 5186 */ 5187 ret = hns3_clear_hw(hw); 5188 if (ret) { 5189 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 5190 goto err_cmd_init; 5191 } 5192 5193 /* Hardware statistics of imissed registers cleared. */ 5194 ret = hns3_update_imissed_stats(hw, true); 5195 if (ret) { 5196 hns3_err(hw, "clear imissed stats failed, ret = %d", ret); 5197 goto err_cmd_init; 5198 } 5199 5200 hns3_config_all_msix_error(hw, true); 5201 5202 ret = rte_intr_callback_register(&pci_dev->intr_handle, 5203 hns3_interrupt_handler, 5204 eth_dev); 5205 if (ret) { 5206 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 5207 goto err_intr_callback_register; 5208 } 5209 5210 ret = hns3_ptp_init(hw); 5211 if (ret) 5212 goto err_get_config; 5213 5214 /* Enable interrupt */ 5215 rte_intr_enable(&pci_dev->intr_handle); 5216 hns3_pf_enable_irq0(hw); 5217 5218 /* Get configuration */ 5219 ret = hns3_get_configuration(hw); 5220 if (ret) { 5221 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 5222 goto err_get_config; 5223 } 5224 5225 ret = hns3_tqp_stats_init(hw); 5226 if (ret) 5227 goto err_get_config; 5228 5229 ret = hns3_init_hardware(hns); 5230 if (ret) { 5231 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 5232 goto err_init_hw; 5233 } 5234 5235 /* Initialize flow director filter list & hash */ 5236 ret = hns3_fdir_filter_init(hns); 5237 if (ret) { 5238 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 5239 goto err_fdir; 5240 } 5241 5242 hns3_rss_set_default_args(hw); 5243 5244 ret = hns3_enable_hw_error_intr(hns, true); 5245 if (ret) { 5246 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 5247 ret); 5248 goto err_enable_intr; 5249 } 5250 5251 ret = hns3_get_port_supported_speed(eth_dev); 5252 if (ret) { 5253 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported " 5254 "by device, ret = %d.", ret); 5255 goto err_supported_speed; 5256 } 5257 5258 hns3_get_fc_autoneg_capability(hns); 5259 5260 hns3_tm_conf_init(eth_dev); 5261 5262 return 0; 5263 5264 err_supported_speed: 5265 (void)hns3_enable_hw_error_intr(hns, false); 5266 err_enable_intr: 5267 hns3_fdir_filter_uninit(hns); 5268 err_fdir: 5269 hns3_uninit_umv_space(hw); 5270 err_init_hw: 5271 hns3_tqp_stats_uninit(hw); 5272 err_get_config: 5273 hns3_pf_disable_irq0(hw); 5274 rte_intr_disable(&pci_dev->intr_handle); 5275 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 5276 eth_dev); 5277 err_intr_callback_register: 5278 err_cmd_init: 5279 hns3_cmd_uninit(hw); 5280 hns3_cmd_destroy_queue(hw); 5281 err_cmd_init_queue: 5282 hw->io_base = NULL; 5283 5284 return ret; 5285 } 5286 5287 static void 5288 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 5289 { 5290 struct hns3_adapter *hns = eth_dev->data->dev_private; 5291 struct rte_device *dev = eth_dev->device; 5292 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5293 struct hns3_hw *hw = &hns->hw; 5294 5295 PMD_INIT_FUNC_TRACE(); 5296 5297 hns3_tm_conf_uninit(eth_dev); 5298 hns3_enable_hw_error_intr(hns, false); 5299 hns3_rss_uninit(hns); 5300 (void)hns3_config_gro(hw, false); 5301 hns3_promisc_uninit(hw); 5302 hns3_fdir_filter_uninit(hns); 5303 hns3_uninit_umv_space(hw); 5304 hns3_tqp_stats_uninit(hw); 5305 hns3_config_mac_tnl_int(hw, false); 5306 hns3_pf_disable_irq0(hw); 5307 rte_intr_disable(&pci_dev->intr_handle); 5308 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 5309 eth_dev); 5310 hns3_config_all_msix_error(hw, false); 5311 hns3_cmd_uninit(hw); 5312 hns3_cmd_destroy_queue(hw); 5313 hw->io_base = NULL; 5314 } 5315 5316 static uint32_t 5317 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds) 5318 { 5319 uint32_t speed_bit; 5320 5321 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) { 5322 case ETH_LINK_SPEED_10M: 5323 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT; 5324 break; 5325 case ETH_LINK_SPEED_10M_HD: 5326 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT; 5327 break; 5328 case ETH_LINK_SPEED_100M: 5329 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT; 5330 break; 5331 case ETH_LINK_SPEED_100M_HD: 5332 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT; 5333 break; 5334 case ETH_LINK_SPEED_1G: 5335 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT; 5336 break; 5337 default: 5338 speed_bit = 0; 5339 break; 5340 } 5341 5342 return speed_bit; 5343 } 5344 5345 static uint32_t 5346 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds) 5347 { 5348 uint32_t speed_bit; 5349 5350 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) { 5351 case ETH_LINK_SPEED_1G: 5352 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT; 5353 break; 5354 case ETH_LINK_SPEED_10G: 5355 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT; 5356 break; 5357 case ETH_LINK_SPEED_25G: 5358 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT; 5359 break; 5360 case ETH_LINK_SPEED_40G: 5361 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT; 5362 break; 5363 case ETH_LINK_SPEED_50G: 5364 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT; 5365 break; 5366 case ETH_LINK_SPEED_100G: 5367 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT; 5368 break; 5369 case ETH_LINK_SPEED_200G: 5370 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT; 5371 break; 5372 default: 5373 speed_bit = 0; 5374 break; 5375 } 5376 5377 return speed_bit; 5378 } 5379 5380 static int 5381 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds) 5382 { 5383 struct hns3_mac *mac = &hw->mac; 5384 uint32_t supported_speed = mac->supported_speed; 5385 uint32_t speed_bit = 0; 5386 5387 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 5388 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds); 5389 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) 5390 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds); 5391 5392 if (!(speed_bit & supported_speed)) { 5393 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.", 5394 link_speeds); 5395 return -EINVAL; 5396 } 5397 5398 return 0; 5399 } 5400 5401 static inline uint32_t 5402 hns3_get_link_speed(uint32_t link_speeds) 5403 { 5404 uint32_t speed = ETH_SPEED_NUM_NONE; 5405 5406 if (link_speeds & ETH_LINK_SPEED_10M || 5407 link_speeds & ETH_LINK_SPEED_10M_HD) 5408 speed = ETH_SPEED_NUM_10M; 5409 if (link_speeds & ETH_LINK_SPEED_100M || 5410 link_speeds & ETH_LINK_SPEED_100M_HD) 5411 speed = ETH_SPEED_NUM_100M; 5412 if (link_speeds & ETH_LINK_SPEED_1G) 5413 speed = ETH_SPEED_NUM_1G; 5414 if (link_speeds & ETH_LINK_SPEED_10G) 5415 speed = ETH_SPEED_NUM_10G; 5416 if (link_speeds & ETH_LINK_SPEED_25G) 5417 speed = ETH_SPEED_NUM_25G; 5418 if (link_speeds & ETH_LINK_SPEED_40G) 5419 speed = ETH_SPEED_NUM_40G; 5420 if (link_speeds & ETH_LINK_SPEED_50G) 5421 speed = ETH_SPEED_NUM_50G; 5422 if (link_speeds & ETH_LINK_SPEED_100G) 5423 speed = ETH_SPEED_NUM_100G; 5424 if (link_speeds & ETH_LINK_SPEED_200G) 5425 speed = ETH_SPEED_NUM_200G; 5426 5427 return speed; 5428 } 5429 5430 static uint8_t 5431 hns3_get_link_duplex(uint32_t link_speeds) 5432 { 5433 if ((link_speeds & ETH_LINK_SPEED_10M_HD) || 5434 (link_speeds & ETH_LINK_SPEED_100M_HD)) 5435 return ETH_LINK_HALF_DUPLEX; 5436 else 5437 return ETH_LINK_FULL_DUPLEX; 5438 } 5439 5440 static int 5441 hns3_set_copper_port_link_speed(struct hns3_hw *hw, 5442 struct hns3_set_link_speed_cfg *cfg) 5443 { 5444 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 5445 struct hns3_phy_params_bd0_cmd *req; 5446 uint16_t i; 5447 5448 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 5449 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 5450 false); 5451 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 5452 } 5453 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false); 5454 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 5455 req->autoneg = cfg->autoneg; 5456 5457 /* 5458 * The full speed capability is used to negotiate when 5459 * auto-negotiation is enabled. 5460 */ 5461 if (cfg->autoneg) { 5462 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT | 5463 HNS3_PHY_LINK_SPEED_10M_HD_BIT | 5464 HNS3_PHY_LINK_SPEED_100M_BIT | 5465 HNS3_PHY_LINK_SPEED_100M_HD_BIT | 5466 HNS3_PHY_LINK_SPEED_1000M_BIT; 5467 } else { 5468 req->speed = cfg->speed; 5469 req->duplex = cfg->duplex; 5470 } 5471 5472 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 5473 } 5474 5475 static int 5476 hns3_set_autoneg(struct hns3_hw *hw, bool enable) 5477 { 5478 struct hns3_config_auto_neg_cmd *req; 5479 struct hns3_cmd_desc desc; 5480 uint32_t flag = 0; 5481 int ret; 5482 5483 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false); 5484 5485 req = (struct hns3_config_auto_neg_cmd *)desc.data; 5486 if (enable) 5487 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1); 5488 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag); 5489 5490 ret = hns3_cmd_send(hw, &desc, 1); 5491 if (ret) 5492 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret); 5493 5494 return ret; 5495 } 5496 5497 static int 5498 hns3_set_fiber_port_link_speed(struct hns3_hw *hw, 5499 struct hns3_set_link_speed_cfg *cfg) 5500 { 5501 int ret; 5502 5503 if (hw->mac.support_autoneg) { 5504 ret = hns3_set_autoneg(hw, cfg->autoneg); 5505 if (ret) { 5506 hns3_err(hw, "failed to configure auto-negotiation."); 5507 return ret; 5508 } 5509 5510 /* 5511 * To enable auto-negotiation, we only need to open the switch 5512 * of auto-negotiation, then firmware sets all speed 5513 * capabilities. 5514 */ 5515 if (cfg->autoneg) 5516 return 0; 5517 } 5518 5519 /* 5520 * Some hardware doesn't support auto-negotiation, but users may not 5521 * configure link_speeds (default 0), which means auto-negotiation. 5522 * In this case, it should return success. 5523 */ 5524 if (cfg->autoneg) 5525 return 0; 5526 5527 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex); 5528 } 5529 5530 static int 5531 hns3_set_port_link_speed(struct hns3_hw *hw, 5532 struct hns3_set_link_speed_cfg *cfg) 5533 { 5534 int ret; 5535 5536 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) { 5537 #if defined(RTE_HNS3_ONLY_1630_FPGA) 5538 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 5539 if (pf->is_tmp_phy) 5540 return 0; 5541 #endif 5542 5543 ret = hns3_set_copper_port_link_speed(hw, cfg); 5544 if (ret) { 5545 hns3_err(hw, "failed to set copper port link speed," 5546 "ret = %d.", ret); 5547 return ret; 5548 } 5549 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) { 5550 ret = hns3_set_fiber_port_link_speed(hw, cfg); 5551 if (ret) { 5552 hns3_err(hw, "failed to set fiber port link speed," 5553 "ret = %d.", ret); 5554 return ret; 5555 } 5556 } 5557 5558 return 0; 5559 } 5560 5561 static int 5562 hns3_apply_link_speed(struct hns3_hw *hw) 5563 { 5564 struct rte_eth_conf *conf = &hw->data->dev_conf; 5565 struct hns3_set_link_speed_cfg cfg; 5566 5567 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg)); 5568 cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ? 5569 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 5570 if (cfg.autoneg != ETH_LINK_AUTONEG) { 5571 cfg.speed = hns3_get_link_speed(conf->link_speeds); 5572 cfg.duplex = hns3_get_link_duplex(conf->link_speeds); 5573 } 5574 5575 return hns3_set_port_link_speed(hw, &cfg); 5576 } 5577 5578 static int 5579 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 5580 { 5581 struct hns3_hw *hw = &hns->hw; 5582 int ret; 5583 5584 ret = hns3_dcb_cfg_update(hns); 5585 if (ret) 5586 return ret; 5587 5588 /* 5589 * The hns3_dcb_cfg_update may configure TM module, so 5590 * hns3_tm_conf_update must called later. 5591 */ 5592 ret = hns3_tm_conf_update(hw); 5593 if (ret) { 5594 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret); 5595 return ret; 5596 } 5597 5598 hns3_enable_rxd_adv_layout(hw); 5599 5600 ret = hns3_init_queues(hns, reset_queue); 5601 if (ret) { 5602 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret); 5603 return ret; 5604 } 5605 5606 ret = hns3_cfg_mac_mode(hw, true); 5607 if (ret) { 5608 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret); 5609 goto err_config_mac_mode; 5610 } 5611 5612 ret = hns3_apply_link_speed(hw); 5613 if (ret) 5614 goto err_config_mac_mode; 5615 5616 return 0; 5617 5618 err_config_mac_mode: 5619 (void)hns3_cfg_mac_mode(hw, false); 5620 hns3_dev_release_mbufs(hns); 5621 /* 5622 * Here is exception handling, hns3_reset_all_tqps will have the 5623 * corresponding error message if it is handled incorrectly, so it is 5624 * not necessary to check hns3_reset_all_tqps return value, here keep 5625 * ret as the error code causing the exception. 5626 */ 5627 (void)hns3_reset_all_tqps(hns); 5628 return ret; 5629 } 5630 5631 static int 5632 hns3_map_rx_interrupt(struct rte_eth_dev *dev) 5633 { 5634 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5635 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5636 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5637 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET; 5638 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET; 5639 uint32_t intr_vector; 5640 uint16_t q_id; 5641 int ret; 5642 5643 /* 5644 * hns3 needs a separate interrupt to be used as event interrupt which 5645 * could not be shared with task queue pair, so KERNEL drivers need 5646 * support multiple interrupt vectors. 5647 */ 5648 if (dev->data->dev_conf.intr_conf.rxq == 0 || 5649 !rte_intr_cap_multiple(intr_handle)) 5650 return 0; 5651 5652 rte_intr_disable(intr_handle); 5653 intr_vector = hw->used_rx_queues; 5654 /* creates event fd for each intr vector when MSIX is used */ 5655 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5656 return -EINVAL; 5657 5658 if (intr_handle->intr_vec == NULL) { 5659 intr_handle->intr_vec = 5660 rte_zmalloc("intr_vec", 5661 hw->used_rx_queues * sizeof(int), 0); 5662 if (intr_handle->intr_vec == NULL) { 5663 hns3_err(hw, "failed to allocate %u rx_queues intr_vec", 5664 hw->used_rx_queues); 5665 ret = -ENOMEM; 5666 goto alloc_intr_vec_error; 5667 } 5668 } 5669 5670 if (rte_intr_allow_others(intr_handle)) { 5671 vec = RTE_INTR_VEC_RXTX_OFFSET; 5672 base = RTE_INTR_VEC_RXTX_OFFSET; 5673 } 5674 5675 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5676 ret = hns3_bind_ring_with_vector(hw, vec, true, 5677 HNS3_RING_TYPE_RX, q_id); 5678 if (ret) 5679 goto bind_vector_error; 5680 intr_handle->intr_vec[q_id] = vec; 5681 /* 5682 * If there are not enough efds (e.g. not enough interrupt), 5683 * remaining queues will be bond to the last interrupt. 5684 */ 5685 if (vec < base + intr_handle->nb_efd - 1) 5686 vec++; 5687 } 5688 rte_intr_enable(intr_handle); 5689 return 0; 5690 5691 bind_vector_error: 5692 rte_free(intr_handle->intr_vec); 5693 intr_handle->intr_vec = NULL; 5694 alloc_intr_vec_error: 5695 rte_intr_efd_disable(intr_handle); 5696 return ret; 5697 } 5698 5699 static int 5700 hns3_restore_rx_interrupt(struct hns3_hw *hw) 5701 { 5702 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 5703 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5704 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5705 uint16_t q_id; 5706 int ret; 5707 5708 if (dev->data->dev_conf.intr_conf.rxq == 0) 5709 return 0; 5710 5711 if (rte_intr_dp_is_en(intr_handle)) { 5712 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5713 ret = hns3_bind_ring_with_vector(hw, 5714 intr_handle->intr_vec[q_id], true, 5715 HNS3_RING_TYPE_RX, q_id); 5716 if (ret) 5717 return ret; 5718 } 5719 } 5720 5721 return 0; 5722 } 5723 5724 static void 5725 hns3_restore_filter(struct rte_eth_dev *dev) 5726 { 5727 hns3_restore_rss_filter(dev); 5728 } 5729 5730 static int 5731 hns3_dev_start(struct rte_eth_dev *dev) 5732 { 5733 struct hns3_adapter *hns = dev->data->dev_private; 5734 struct hns3_hw *hw = &hns->hw; 5735 int ret; 5736 5737 PMD_INIT_FUNC_TRACE(); 5738 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 5739 return -EBUSY; 5740 5741 rte_spinlock_lock(&hw->lock); 5742 hw->adapter_state = HNS3_NIC_STARTING; 5743 5744 ret = hns3_do_start(hns, true); 5745 if (ret) { 5746 hw->adapter_state = HNS3_NIC_CONFIGURED; 5747 rte_spinlock_unlock(&hw->lock); 5748 return ret; 5749 } 5750 ret = hns3_map_rx_interrupt(dev); 5751 if (ret) 5752 goto map_rx_inter_err; 5753 5754 /* 5755 * There are three register used to control the status of a TQP 5756 * (contains a pair of Tx queue and Rx queue) in the new version network 5757 * engine. One is used to control the enabling of Tx queue, the other is 5758 * used to control the enabling of Rx queue, and the last is the master 5759 * switch used to control the enabling of the tqp. The Tx register and 5760 * TQP register must be enabled at the same time to enable a Tx queue. 5761 * The same applies to the Rx queue. For the older network engine, this 5762 * function only refresh the enabled flag, and it is used to update the 5763 * status of queue in the dpdk framework. 5764 */ 5765 ret = hns3_start_all_txqs(dev); 5766 if (ret) 5767 goto map_rx_inter_err; 5768 5769 ret = hns3_start_all_rxqs(dev); 5770 if (ret) 5771 goto start_all_rxqs_fail; 5772 5773 hw->adapter_state = HNS3_NIC_STARTED; 5774 rte_spinlock_unlock(&hw->lock); 5775 5776 hns3_rx_scattered_calc(dev); 5777 hns3_set_rxtx_function(dev); 5778 hns3_mp_req_start_rxtx(dev); 5779 5780 hns3_restore_filter(dev); 5781 5782 /* Enable interrupt of all rx queues before enabling queues */ 5783 hns3_dev_all_rx_queue_intr_enable(hw, true); 5784 5785 /* 5786 * After finished the initialization, enable tqps to receive/transmit 5787 * packets and refresh all queue status. 5788 */ 5789 hns3_start_tqps(hw); 5790 5791 hns3_tm_dev_start_proc(hw); 5792 5793 if (dev->data->dev_conf.intr_conf.lsc != 0) 5794 hns3_dev_link_update(dev, 0); 5795 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 5796 5797 hns3_info(hw, "hns3 dev start successful!"); 5798 5799 return 0; 5800 5801 start_all_rxqs_fail: 5802 hns3_stop_all_txqs(dev); 5803 map_rx_inter_err: 5804 (void)hns3_do_stop(hns); 5805 hw->adapter_state = HNS3_NIC_CONFIGURED; 5806 rte_spinlock_unlock(&hw->lock); 5807 5808 return ret; 5809 } 5810 5811 static int 5812 hns3_do_stop(struct hns3_adapter *hns) 5813 { 5814 struct hns3_hw *hw = &hns->hw; 5815 int ret; 5816 5817 /* 5818 * The "hns3_do_stop" function will also be called by .stop_service to 5819 * prepare reset. At the time of global or IMP reset, the command cannot 5820 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 5821 * accessed during the reset process. So the mbuf can not be released 5822 * during reset and is required to be released after the reset is 5823 * completed. 5824 */ 5825 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 5826 hns3_dev_release_mbufs(hns); 5827 5828 ret = hns3_cfg_mac_mode(hw, false); 5829 if (ret) 5830 return ret; 5831 hw->mac.link_status = ETH_LINK_DOWN; 5832 5833 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 5834 hns3_configure_all_mac_addr(hns, true); 5835 ret = hns3_reset_all_tqps(hns); 5836 if (ret) { 5837 hns3_err(hw, "failed to reset all queues ret = %d.", 5838 ret); 5839 return ret; 5840 } 5841 } 5842 hw->mac.default_addr_setted = false; 5843 return 0; 5844 } 5845 5846 static void 5847 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) 5848 { 5849 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5850 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5851 struct hns3_adapter *hns = dev->data->dev_private; 5852 struct hns3_hw *hw = &hns->hw; 5853 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 5854 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 5855 uint16_t q_id; 5856 5857 if (dev->data->dev_conf.intr_conf.rxq == 0) 5858 return; 5859 5860 /* unmap the ring with vector */ 5861 if (rte_intr_allow_others(intr_handle)) { 5862 vec = RTE_INTR_VEC_RXTX_OFFSET; 5863 base = RTE_INTR_VEC_RXTX_OFFSET; 5864 } 5865 if (rte_intr_dp_is_en(intr_handle)) { 5866 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5867 (void)hns3_bind_ring_with_vector(hw, vec, false, 5868 HNS3_RING_TYPE_RX, 5869 q_id); 5870 if (vec < base + intr_handle->nb_efd - 1) 5871 vec++; 5872 } 5873 } 5874 /* Clean datapath event and queue/vec mapping */ 5875 rte_intr_efd_disable(intr_handle); 5876 if (intr_handle->intr_vec) { 5877 rte_free(intr_handle->intr_vec); 5878 intr_handle->intr_vec = NULL; 5879 } 5880 } 5881 5882 static int 5883 hns3_dev_stop(struct rte_eth_dev *dev) 5884 { 5885 struct hns3_adapter *hns = dev->data->dev_private; 5886 struct hns3_hw *hw = &hns->hw; 5887 5888 PMD_INIT_FUNC_TRACE(); 5889 dev->data->dev_started = 0; 5890 5891 hw->adapter_state = HNS3_NIC_STOPPING; 5892 hns3_set_rxtx_function(dev); 5893 rte_wmb(); 5894 /* Disable datapath on secondary process. */ 5895 hns3_mp_req_stop_rxtx(dev); 5896 /* Prevent crashes when queues are still in use. */ 5897 rte_delay_ms(hw->tqps_num); 5898 5899 rte_spinlock_lock(&hw->lock); 5900 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 5901 hns3_tm_dev_stop_proc(hw); 5902 hns3_config_mac_tnl_int(hw, false); 5903 hns3_stop_tqps(hw); 5904 hns3_do_stop(hns); 5905 hns3_unmap_rx_interrupt(dev); 5906 hw->adapter_state = HNS3_NIC_CONFIGURED; 5907 } 5908 hns3_rx_scattered_reset(dev); 5909 rte_eal_alarm_cancel(hns3_service_handler, dev); 5910 hns3_stop_report_lse(dev); 5911 rte_spinlock_unlock(&hw->lock); 5912 5913 return 0; 5914 } 5915 5916 static int 5917 hns3_dev_close(struct rte_eth_dev *eth_dev) 5918 { 5919 struct hns3_adapter *hns = eth_dev->data->dev_private; 5920 struct hns3_hw *hw = &hns->hw; 5921 int ret = 0; 5922 5923 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5924 rte_free(eth_dev->process_private); 5925 eth_dev->process_private = NULL; 5926 return 0; 5927 } 5928 5929 if (hw->adapter_state == HNS3_NIC_STARTED) 5930 ret = hns3_dev_stop(eth_dev); 5931 5932 hw->adapter_state = HNS3_NIC_CLOSING; 5933 hns3_reset_abort(hns); 5934 hw->adapter_state = HNS3_NIC_CLOSED; 5935 5936 hns3_configure_all_mc_mac_addr(hns, true); 5937 hns3_remove_all_vlan_table(hns); 5938 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 5939 hns3_uninit_pf(eth_dev); 5940 hns3_free_all_queues(eth_dev); 5941 rte_free(hw->reset.wait_data); 5942 rte_free(eth_dev->process_private); 5943 eth_dev->process_private = NULL; 5944 hns3_mp_uninit_primary(); 5945 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 5946 5947 return ret; 5948 } 5949 5950 static void 5951 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause, 5952 bool *tx_pause) 5953 { 5954 struct hns3_mac *mac = &hw->mac; 5955 uint32_t advertising = mac->advertising; 5956 uint32_t lp_advertising = mac->lp_advertising; 5957 *rx_pause = false; 5958 *tx_pause = false; 5959 5960 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) { 5961 *rx_pause = true; 5962 *tx_pause = true; 5963 } else if (advertising & lp_advertising & 5964 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) { 5965 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5966 *rx_pause = true; 5967 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5968 *tx_pause = true; 5969 } 5970 } 5971 5972 static enum hns3_fc_mode 5973 hns3_get_autoneg_fc_mode(struct hns3_hw *hw) 5974 { 5975 enum hns3_fc_mode current_mode; 5976 bool rx_pause = false; 5977 bool tx_pause = false; 5978 5979 switch (hw->mac.media_type) { 5980 case HNS3_MEDIA_TYPE_COPPER: 5981 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause); 5982 break; 5983 5984 /* 5985 * Flow control auto-negotiation is not supported for fiber and 5986 * backpalne media type. 5987 */ 5988 case HNS3_MEDIA_TYPE_FIBER: 5989 case HNS3_MEDIA_TYPE_BACKPLANE: 5990 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled."); 5991 current_mode = hw->requested_fc_mode; 5992 goto out; 5993 default: 5994 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).", 5995 hw->mac.media_type); 5996 current_mode = HNS3_FC_NONE; 5997 goto out; 5998 } 5999 6000 if (rx_pause && tx_pause) 6001 current_mode = HNS3_FC_FULL; 6002 else if (rx_pause) 6003 current_mode = HNS3_FC_RX_PAUSE; 6004 else if (tx_pause) 6005 current_mode = HNS3_FC_TX_PAUSE; 6006 else 6007 current_mode = HNS3_FC_NONE; 6008 6009 out: 6010 return current_mode; 6011 } 6012 6013 static enum hns3_fc_mode 6014 hns3_get_current_fc_mode(struct rte_eth_dev *dev) 6015 { 6016 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6017 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6018 struct hns3_mac *mac = &hw->mac; 6019 6020 /* 6021 * When the flow control mode is obtained, the device may not complete 6022 * auto-negotiation. It is necessary to wait for link establishment. 6023 */ 6024 (void)hns3_dev_link_update(dev, 1); 6025 6026 /* 6027 * If the link auto-negotiation of the nic is disabled, or the flow 6028 * control auto-negotiation is not supported, the forced flow control 6029 * mode is used. 6030 */ 6031 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg) 6032 return hw->requested_fc_mode; 6033 6034 return hns3_get_autoneg_fc_mode(hw); 6035 } 6036 6037 static int 6038 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 6039 { 6040 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6041 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6042 enum hns3_fc_mode current_mode; 6043 6044 current_mode = hns3_get_current_fc_mode(dev); 6045 switch (current_mode) { 6046 case HNS3_FC_FULL: 6047 fc_conf->mode = RTE_FC_FULL; 6048 break; 6049 case HNS3_FC_TX_PAUSE: 6050 fc_conf->mode = RTE_FC_TX_PAUSE; 6051 break; 6052 case HNS3_FC_RX_PAUSE: 6053 fc_conf->mode = RTE_FC_RX_PAUSE; 6054 break; 6055 case HNS3_FC_NONE: 6056 default: 6057 fc_conf->mode = RTE_FC_NONE; 6058 break; 6059 } 6060 6061 fc_conf->pause_time = pf->pause_time; 6062 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0; 6063 6064 return 0; 6065 } 6066 6067 static void 6068 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode) 6069 { 6070 switch (mode) { 6071 case RTE_FC_NONE: 6072 hw->requested_fc_mode = HNS3_FC_NONE; 6073 break; 6074 case RTE_FC_RX_PAUSE: 6075 hw->requested_fc_mode = HNS3_FC_RX_PAUSE; 6076 break; 6077 case RTE_FC_TX_PAUSE: 6078 hw->requested_fc_mode = HNS3_FC_TX_PAUSE; 6079 break; 6080 case RTE_FC_FULL: 6081 hw->requested_fc_mode = HNS3_FC_FULL; 6082 break; 6083 default: 6084 hw->requested_fc_mode = HNS3_FC_NONE; 6085 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is " 6086 "configured to RTE_FC_NONE", mode); 6087 break; 6088 } 6089 } 6090 6091 static int 6092 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg) 6093 { 6094 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 6095 6096 if (!pf->support_fc_autoneg) { 6097 if (autoneg != 0) { 6098 hns3_err(hw, "unsupported fc auto-negotiation setting."); 6099 return -EOPNOTSUPP; 6100 } 6101 6102 /* 6103 * Flow control auto-negotiation of the NIC is not supported, 6104 * but other auto-negotiation features may be supported. 6105 */ 6106 if (autoneg != hw->mac.link_autoneg) { 6107 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!"); 6108 return -EOPNOTSUPP; 6109 } 6110 6111 return 0; 6112 } 6113 6114 /* 6115 * If flow control auto-negotiation of the NIC is supported, all 6116 * auto-negotiation features are supported. 6117 */ 6118 if (autoneg != hw->mac.link_autoneg) { 6119 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!"); 6120 return -EOPNOTSUPP; 6121 } 6122 6123 return 0; 6124 } 6125 6126 static int 6127 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 6128 { 6129 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6130 int ret; 6131 6132 if (fc_conf->high_water || fc_conf->low_water || 6133 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 6134 hns3_err(hw, "Unsupported flow control settings specified, " 6135 "high_water(%u), low_water(%u), send_xon(%u) and " 6136 "mac_ctrl_frame_fwd(%u) must be set to '0'", 6137 fc_conf->high_water, fc_conf->low_water, 6138 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 6139 return -EINVAL; 6140 } 6141 6142 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg); 6143 if (ret) 6144 return ret; 6145 6146 if (!fc_conf->pause_time) { 6147 hns3_err(hw, "Invalid pause time %u setting.", 6148 fc_conf->pause_time); 6149 return -EINVAL; 6150 } 6151 6152 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 6153 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 6154 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 6155 "current_fc_status = %d", hw->current_fc_status); 6156 return -EOPNOTSUPP; 6157 } 6158 6159 if (hw->num_tc > 1) { 6160 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported."); 6161 return -EOPNOTSUPP; 6162 } 6163 6164 hns3_get_fc_mode(hw, fc_conf->mode); 6165 6166 rte_spinlock_lock(&hw->lock); 6167 ret = hns3_fc_enable(dev, fc_conf); 6168 rte_spinlock_unlock(&hw->lock); 6169 6170 return ret; 6171 } 6172 6173 static int 6174 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 6175 struct rte_eth_pfc_conf *pfc_conf) 6176 { 6177 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6178 int ret; 6179 6180 if (!hns3_dev_dcb_supported(hw)) { 6181 hns3_err(hw, "This port does not support dcb configurations."); 6182 return -EOPNOTSUPP; 6183 } 6184 6185 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 6186 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 6187 hns3_err(hw, "Unsupported flow control settings specified, " 6188 "high_water(%u), low_water(%u), send_xon(%u) and " 6189 "mac_ctrl_frame_fwd(%u) must be set to '0'", 6190 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 6191 pfc_conf->fc.send_xon, 6192 pfc_conf->fc.mac_ctrl_frame_fwd); 6193 return -EINVAL; 6194 } 6195 if (pfc_conf->fc.autoneg) { 6196 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 6197 return -EINVAL; 6198 } 6199 if (pfc_conf->fc.pause_time == 0) { 6200 hns3_err(hw, "Invalid pause time %u setting.", 6201 pfc_conf->fc.pause_time); 6202 return -EINVAL; 6203 } 6204 6205 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 6206 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 6207 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 6208 "current_fc_status = %d", hw->current_fc_status); 6209 return -EOPNOTSUPP; 6210 } 6211 6212 hns3_get_fc_mode(hw, pfc_conf->fc.mode); 6213 6214 rte_spinlock_lock(&hw->lock); 6215 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 6216 rte_spinlock_unlock(&hw->lock); 6217 6218 return ret; 6219 } 6220 6221 static int 6222 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 6223 { 6224 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6225 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6226 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 6227 int i; 6228 6229 rte_spinlock_lock(&hw->lock); 6230 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 6231 dcb_info->nb_tcs = pf->local_max_tc; 6232 else 6233 dcb_info->nb_tcs = 1; 6234 6235 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 6236 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 6237 for (i = 0; i < dcb_info->nb_tcs; i++) 6238 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 6239 6240 for (i = 0; i < hw->num_tc; i++) { 6241 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 6242 dcb_info->tc_queue.tc_txq[0][i].base = 6243 hw->tc_queue[i].tqp_offset; 6244 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 6245 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 6246 hw->tc_queue[i].tqp_count; 6247 } 6248 rte_spinlock_unlock(&hw->lock); 6249 6250 return 0; 6251 } 6252 6253 static int 6254 hns3_reinit_dev(struct hns3_adapter *hns) 6255 { 6256 struct hns3_hw *hw = &hns->hw; 6257 int ret; 6258 6259 ret = hns3_cmd_init(hw); 6260 if (ret) { 6261 hns3_err(hw, "Failed to init cmd: %d", ret); 6262 return ret; 6263 } 6264 6265 ret = hns3_reset_all_tqps(hns); 6266 if (ret) { 6267 hns3_err(hw, "Failed to reset all queues: %d", ret); 6268 return ret; 6269 } 6270 6271 ret = hns3_init_hardware(hns); 6272 if (ret) { 6273 hns3_err(hw, "Failed to init hardware: %d", ret); 6274 return ret; 6275 } 6276 6277 ret = hns3_enable_hw_error_intr(hns, true); 6278 if (ret) { 6279 hns3_err(hw, "fail to enable hw error interrupts: %d", 6280 ret); 6281 return ret; 6282 } 6283 hns3_info(hw, "Reset done, driver initialization finished."); 6284 6285 return 0; 6286 } 6287 6288 static bool 6289 is_pf_reset_done(struct hns3_hw *hw) 6290 { 6291 uint32_t val, reg, reg_bit; 6292 6293 switch (hw->reset.level) { 6294 case HNS3_IMP_RESET: 6295 reg = HNS3_GLOBAL_RESET_REG; 6296 reg_bit = HNS3_IMP_RESET_BIT; 6297 break; 6298 case HNS3_GLOBAL_RESET: 6299 reg = HNS3_GLOBAL_RESET_REG; 6300 reg_bit = HNS3_GLOBAL_RESET_BIT; 6301 break; 6302 case HNS3_FUNC_RESET: 6303 reg = HNS3_FUN_RST_ING; 6304 reg_bit = HNS3_FUN_RST_ING_B; 6305 break; 6306 case HNS3_FLR_RESET: 6307 default: 6308 hns3_err(hw, "Wait for unsupported reset level: %d", 6309 hw->reset.level); 6310 return true; 6311 } 6312 val = hns3_read_dev(hw, reg); 6313 if (hns3_get_bit(val, reg_bit)) 6314 return false; 6315 else 6316 return true; 6317 } 6318 6319 bool 6320 hns3_is_reset_pending(struct hns3_adapter *hns) 6321 { 6322 struct hns3_hw *hw = &hns->hw; 6323 enum hns3_reset_level reset; 6324 6325 hns3_check_event_cause(hns, NULL); 6326 reset = hns3_get_reset_level(hns, &hw->reset.pending); 6327 6328 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 6329 hw->reset.level < reset) { 6330 hns3_warn(hw, "High level reset %d is pending", reset); 6331 return true; 6332 } 6333 reset = hns3_get_reset_level(hns, &hw->reset.request); 6334 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 6335 hw->reset.level < reset) { 6336 hns3_warn(hw, "High level reset %d is request", reset); 6337 return true; 6338 } 6339 return false; 6340 } 6341 6342 static int 6343 hns3_wait_hardware_ready(struct hns3_adapter *hns) 6344 { 6345 struct hns3_hw *hw = &hns->hw; 6346 struct hns3_wait_data *wait_data = hw->reset.wait_data; 6347 struct timeval tv; 6348 6349 if (wait_data->result == HNS3_WAIT_SUCCESS) 6350 return 0; 6351 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 6352 gettimeofday(&tv, NULL); 6353 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 6354 tv.tv_sec, tv.tv_usec); 6355 return -ETIME; 6356 } else if (wait_data->result == HNS3_WAIT_REQUEST) 6357 return -EAGAIN; 6358 6359 wait_data->hns = hns; 6360 wait_data->check_completion = is_pf_reset_done; 6361 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 6362 HNS3_RESET_WAIT_MS + get_timeofday_ms(); 6363 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 6364 wait_data->count = HNS3_RESET_WAIT_CNT; 6365 wait_data->result = HNS3_WAIT_REQUEST; 6366 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 6367 return -EAGAIN; 6368 } 6369 6370 static int 6371 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 6372 { 6373 struct hns3_cmd_desc desc; 6374 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 6375 6376 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 6377 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 6378 req->fun_reset_vfid = func_id; 6379 6380 return hns3_cmd_send(hw, &desc, 1); 6381 } 6382 6383 static int 6384 hns3_imp_reset_cmd(struct hns3_hw *hw) 6385 { 6386 struct hns3_cmd_desc desc; 6387 6388 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 6389 desc.data[0] = 0xeedd; 6390 6391 return hns3_cmd_send(hw, &desc, 1); 6392 } 6393 6394 static void 6395 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 6396 { 6397 struct hns3_hw *hw = &hns->hw; 6398 struct timeval tv; 6399 uint32_t val; 6400 6401 gettimeofday(&tv, NULL); 6402 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 6403 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 6404 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 6405 tv.tv_sec, tv.tv_usec); 6406 return; 6407 } 6408 6409 switch (reset_level) { 6410 case HNS3_IMP_RESET: 6411 hns3_imp_reset_cmd(hw); 6412 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 6413 tv.tv_sec, tv.tv_usec); 6414 break; 6415 case HNS3_GLOBAL_RESET: 6416 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 6417 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 6418 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 6419 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 6420 tv.tv_sec, tv.tv_usec); 6421 break; 6422 case HNS3_FUNC_RESET: 6423 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 6424 tv.tv_sec, tv.tv_usec); 6425 /* schedule again to check later */ 6426 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 6427 hns3_schedule_reset(hns); 6428 break; 6429 default: 6430 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 6431 return; 6432 } 6433 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 6434 } 6435 6436 static enum hns3_reset_level 6437 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 6438 { 6439 struct hns3_hw *hw = &hns->hw; 6440 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 6441 6442 /* Return the highest priority reset level amongst all */ 6443 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 6444 reset_level = HNS3_IMP_RESET; 6445 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 6446 reset_level = HNS3_GLOBAL_RESET; 6447 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 6448 reset_level = HNS3_FUNC_RESET; 6449 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 6450 reset_level = HNS3_FLR_RESET; 6451 6452 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 6453 return HNS3_NONE_RESET; 6454 6455 return reset_level; 6456 } 6457 6458 static void 6459 hns3_record_imp_error(struct hns3_adapter *hns) 6460 { 6461 struct hns3_hw *hw = &hns->hw; 6462 uint32_t reg_val; 6463 6464 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 6465 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 6466 hns3_warn(hw, "Detected IMP RD poison!"); 6467 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 6468 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 6469 } 6470 6471 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 6472 hns3_warn(hw, "Detected IMP CMDQ error!"); 6473 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 6474 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 6475 } 6476 } 6477 6478 static int 6479 hns3_prepare_reset(struct hns3_adapter *hns) 6480 { 6481 struct hns3_hw *hw = &hns->hw; 6482 uint32_t reg_val; 6483 int ret; 6484 6485 switch (hw->reset.level) { 6486 case HNS3_FUNC_RESET: 6487 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 6488 if (ret) 6489 return ret; 6490 6491 /* 6492 * After performaning pf reset, it is not necessary to do the 6493 * mailbox handling or send any command to firmware, because 6494 * any mailbox handling or command to firmware is only valid 6495 * after hns3_cmd_init is called. 6496 */ 6497 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 6498 hw->reset.stats.request_cnt++; 6499 break; 6500 case HNS3_IMP_RESET: 6501 hns3_record_imp_error(hns); 6502 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 6503 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 6504 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 6505 break; 6506 default: 6507 break; 6508 } 6509 return 0; 6510 } 6511 6512 static int 6513 hns3_set_rst_done(struct hns3_hw *hw) 6514 { 6515 struct hns3_pf_rst_done_cmd *req; 6516 struct hns3_cmd_desc desc; 6517 6518 req = (struct hns3_pf_rst_done_cmd *)desc.data; 6519 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 6520 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 6521 return hns3_cmd_send(hw, &desc, 1); 6522 } 6523 6524 static int 6525 hns3_stop_service(struct hns3_adapter *hns) 6526 { 6527 struct hns3_hw *hw = &hns->hw; 6528 struct rte_eth_dev *eth_dev; 6529 6530 eth_dev = &rte_eth_devices[hw->data->port_id]; 6531 hw->mac.link_status = ETH_LINK_DOWN; 6532 if (hw->adapter_state == HNS3_NIC_STARTED) { 6533 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 6534 hns3_update_linkstatus_and_event(hw, false); 6535 } 6536 6537 hns3_set_rxtx_function(eth_dev); 6538 rte_wmb(); 6539 /* Disable datapath on secondary process. */ 6540 hns3_mp_req_stop_rxtx(eth_dev); 6541 rte_delay_ms(hw->tqps_num); 6542 6543 rte_spinlock_lock(&hw->lock); 6544 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 6545 hw->adapter_state == HNS3_NIC_STOPPING) { 6546 hns3_enable_all_queues(hw, false); 6547 hns3_do_stop(hns); 6548 hw->reset.mbuf_deferred_free = true; 6549 } else 6550 hw->reset.mbuf_deferred_free = false; 6551 6552 /* 6553 * It is cumbersome for hardware to pick-and-choose entries for deletion 6554 * from table space. Hence, for function reset software intervention is 6555 * required to delete the entries 6556 */ 6557 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 6558 hns3_configure_all_mc_mac_addr(hns, true); 6559 rte_spinlock_unlock(&hw->lock); 6560 6561 return 0; 6562 } 6563 6564 static int 6565 hns3_start_service(struct hns3_adapter *hns) 6566 { 6567 struct hns3_hw *hw = &hns->hw; 6568 struct rte_eth_dev *eth_dev; 6569 6570 if (hw->reset.level == HNS3_IMP_RESET || 6571 hw->reset.level == HNS3_GLOBAL_RESET) 6572 hns3_set_rst_done(hw); 6573 eth_dev = &rte_eth_devices[hw->data->port_id]; 6574 hns3_set_rxtx_function(eth_dev); 6575 hns3_mp_req_start_rxtx(eth_dev); 6576 if (hw->adapter_state == HNS3_NIC_STARTED) { 6577 /* 6578 * This API parent function already hold the hns3_hw.lock, the 6579 * hns3_service_handler may report lse, in bonding application 6580 * it will call driver's ops which may acquire the hns3_hw.lock 6581 * again, thus lead to deadlock. 6582 * We defer calls hns3_service_handler to avoid the deadlock. 6583 */ 6584 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL, 6585 hns3_service_handler, eth_dev); 6586 6587 /* Enable interrupt of all rx queues before enabling queues */ 6588 hns3_dev_all_rx_queue_intr_enable(hw, true); 6589 /* 6590 * Enable state of each rxq and txq will be recovered after 6591 * reset, so we need to restore them before enable all tqps; 6592 */ 6593 hns3_restore_tqp_enable_state(hw); 6594 /* 6595 * When finished the initialization, enable queues to receive 6596 * and transmit packets. 6597 */ 6598 hns3_enable_all_queues(hw, true); 6599 } 6600 6601 return 0; 6602 } 6603 6604 static int 6605 hns3_restore_conf(struct hns3_adapter *hns) 6606 { 6607 struct hns3_hw *hw = &hns->hw; 6608 int ret; 6609 6610 ret = hns3_configure_all_mac_addr(hns, false); 6611 if (ret) 6612 return ret; 6613 6614 ret = hns3_configure_all_mc_mac_addr(hns, false); 6615 if (ret) 6616 goto err_mc_mac; 6617 6618 ret = hns3_dev_promisc_restore(hns); 6619 if (ret) 6620 goto err_promisc; 6621 6622 ret = hns3_restore_vlan_table(hns); 6623 if (ret) 6624 goto err_promisc; 6625 6626 ret = hns3_restore_vlan_conf(hns); 6627 if (ret) 6628 goto err_promisc; 6629 6630 ret = hns3_restore_all_fdir_filter(hns); 6631 if (ret) 6632 goto err_promisc; 6633 6634 ret = hns3_restore_ptp(hns); 6635 if (ret) 6636 goto err_promisc; 6637 6638 ret = hns3_restore_rx_interrupt(hw); 6639 if (ret) 6640 goto err_promisc; 6641 6642 ret = hns3_restore_gro_conf(hw); 6643 if (ret) 6644 goto err_promisc; 6645 6646 ret = hns3_restore_fec(hw); 6647 if (ret) 6648 goto err_promisc; 6649 6650 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 6651 ret = hns3_do_start(hns, false); 6652 if (ret) 6653 goto err_promisc; 6654 hns3_info(hw, "hns3 dev restart successful!"); 6655 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 6656 hw->adapter_state = HNS3_NIC_CONFIGURED; 6657 return 0; 6658 6659 err_promisc: 6660 hns3_configure_all_mc_mac_addr(hns, true); 6661 err_mc_mac: 6662 hns3_configure_all_mac_addr(hns, true); 6663 return ret; 6664 } 6665 6666 static void 6667 hns3_reset_service(void *param) 6668 { 6669 struct hns3_adapter *hns = (struct hns3_adapter *)param; 6670 struct hns3_hw *hw = &hns->hw; 6671 enum hns3_reset_level reset_level; 6672 struct timeval tv_delta; 6673 struct timeval tv_start; 6674 struct timeval tv; 6675 uint64_t msec; 6676 int ret; 6677 6678 /* 6679 * The interrupt is not triggered within the delay time. 6680 * The interrupt may have been lost. It is necessary to handle 6681 * the interrupt to recover from the error. 6682 */ 6683 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 6684 SCHEDULE_DEFERRED) { 6685 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 6686 __ATOMIC_RELAXED); 6687 hns3_err(hw, "Handling interrupts in delayed tasks"); 6688 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 6689 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 6690 if (reset_level == HNS3_NONE_RESET) { 6691 hns3_err(hw, "No reset level is set, try IMP reset"); 6692 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 6693 } 6694 } 6695 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 6696 6697 /* 6698 * Check if there is any ongoing reset in the hardware. This status can 6699 * be checked from reset_pending. If there is then, we need to wait for 6700 * hardware to complete reset. 6701 * a. If we are able to figure out in reasonable time that hardware 6702 * has fully resetted then, we can proceed with driver, client 6703 * reset. 6704 * b. else, we can come back later to check this status so re-sched 6705 * now. 6706 */ 6707 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 6708 if (reset_level != HNS3_NONE_RESET) { 6709 gettimeofday(&tv_start, NULL); 6710 ret = hns3_reset_process(hns, reset_level); 6711 gettimeofday(&tv, NULL); 6712 timersub(&tv, &tv_start, &tv_delta); 6713 msec = tv_delta.tv_sec * MSEC_PER_SEC + 6714 tv_delta.tv_usec / USEC_PER_MSEC; 6715 if (msec > HNS3_RESET_PROCESS_MS) 6716 hns3_err(hw, "%d handle long time delta %" PRIx64 6717 " ms time=%ld.%.6ld", 6718 hw->reset.level, msec, 6719 tv.tv_sec, tv.tv_usec); 6720 if (ret == -EAGAIN) 6721 return; 6722 } 6723 6724 /* Check if we got any *new* reset requests to be honored */ 6725 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 6726 if (reset_level != HNS3_NONE_RESET) 6727 hns3_msix_process(hns, reset_level); 6728 } 6729 6730 static unsigned int 6731 hns3_get_speed_capa_num(uint16_t device_id) 6732 { 6733 unsigned int num; 6734 6735 switch (device_id) { 6736 case HNS3_DEV_ID_25GE: 6737 case HNS3_DEV_ID_25GE_RDMA: 6738 num = 2; 6739 break; 6740 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6741 case HNS3_DEV_ID_200G_RDMA: 6742 num = 1; 6743 break; 6744 default: 6745 num = 0; 6746 break; 6747 } 6748 6749 return num; 6750 } 6751 6752 static int 6753 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, 6754 uint16_t device_id) 6755 { 6756 switch (device_id) { 6757 case HNS3_DEV_ID_25GE: 6758 /* fallthrough */ 6759 case HNS3_DEV_ID_25GE_RDMA: 6760 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed; 6761 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa; 6762 6763 /* In HNS3 device, the 25G NIC is compatible with 10G rate */ 6764 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed; 6765 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa; 6766 break; 6767 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6768 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed; 6769 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa; 6770 break; 6771 case HNS3_DEV_ID_200G_RDMA: 6772 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed; 6773 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa; 6774 break; 6775 default: 6776 return -ENOTSUP; 6777 } 6778 6779 return 0; 6780 } 6781 6782 static int 6783 hns3_fec_get_capability(struct rte_eth_dev *dev, 6784 struct rte_eth_fec_capa *speed_fec_capa, 6785 unsigned int num) 6786 { 6787 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6789 uint16_t device_id = pci_dev->id.device_id; 6790 unsigned int capa_num; 6791 int ret; 6792 6793 capa_num = hns3_get_speed_capa_num(device_id); 6794 if (capa_num == 0) { 6795 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD", 6796 device_id); 6797 return -ENOTSUP; 6798 } 6799 6800 if (speed_fec_capa == NULL || num < capa_num) 6801 return capa_num; 6802 6803 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id); 6804 if (ret) 6805 return -ENOTSUP; 6806 6807 return capa_num; 6808 } 6809 6810 static int 6811 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state) 6812 { 6813 struct hns3_config_fec_cmd *req; 6814 struct hns3_cmd_desc desc; 6815 int ret; 6816 6817 /* 6818 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported 6819 * in device of link speed 6820 * below 10 Gbps. 6821 */ 6822 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) { 6823 *state = 0; 6824 return 0; 6825 } 6826 6827 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true); 6828 req = (struct hns3_config_fec_cmd *)desc.data; 6829 ret = hns3_cmd_send(hw, &desc, 1); 6830 if (ret) { 6831 hns3_err(hw, "get current fec auto state failed, ret = %d", 6832 ret); 6833 return ret; 6834 } 6835 6836 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B); 6837 return 0; 6838 } 6839 6840 static int 6841 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa) 6842 { 6843 struct hns3_sfp_info_cmd *resp; 6844 uint32_t tmp_fec_capa; 6845 uint8_t auto_state; 6846 struct hns3_cmd_desc desc; 6847 int ret; 6848 6849 /* 6850 * If link is down and AUTO is enabled, AUTO is returned, otherwise, 6851 * configured FEC mode is returned. 6852 * If link is up, current FEC mode is returned. 6853 */ 6854 if (hw->mac.link_status == ETH_LINK_DOWN) { 6855 ret = get_current_fec_auto_state(hw, &auto_state); 6856 if (ret) 6857 return ret; 6858 6859 if (auto_state == 0x1) { 6860 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 6861 return 0; 6862 } 6863 } 6864 6865 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 6866 resp = (struct hns3_sfp_info_cmd *)desc.data; 6867 resp->query_type = HNS3_ACTIVE_QUERY; 6868 6869 ret = hns3_cmd_send(hw, &desc, 1); 6870 if (ret == -EOPNOTSUPP) { 6871 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret); 6872 return ret; 6873 } else if (ret) { 6874 hns3_err(hw, "get FEC failed, ret = %d", ret); 6875 return ret; 6876 } 6877 6878 /* 6879 * FEC mode order defined in hns3 hardware is inconsistend with 6880 * that defined in the ethdev library. So the sequence needs 6881 * to be converted. 6882 */ 6883 switch (resp->active_fec) { 6884 case HNS3_HW_FEC_MODE_NOFEC: 6885 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6886 break; 6887 case HNS3_HW_FEC_MODE_BASER: 6888 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 6889 break; 6890 case HNS3_HW_FEC_MODE_RS: 6891 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 6892 break; 6893 default: 6894 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6895 break; 6896 } 6897 6898 *fec_capa = tmp_fec_capa; 6899 return 0; 6900 } 6901 6902 static int 6903 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 6904 { 6905 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6906 6907 return hns3_fec_get_internal(hw, fec_capa); 6908 } 6909 6910 static int 6911 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode) 6912 { 6913 struct hns3_config_fec_cmd *req; 6914 struct hns3_cmd_desc desc; 6915 int ret; 6916 6917 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false); 6918 6919 req = (struct hns3_config_fec_cmd *)desc.data; 6920 switch (mode) { 6921 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC): 6922 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6923 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF); 6924 break; 6925 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER): 6926 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6927 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER); 6928 break; 6929 case RTE_ETH_FEC_MODE_CAPA_MASK(RS): 6930 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6931 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS); 6932 break; 6933 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO): 6934 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1); 6935 break; 6936 default: 6937 return 0; 6938 } 6939 ret = hns3_cmd_send(hw, &desc, 1); 6940 if (ret) 6941 hns3_err(hw, "set fec mode failed, ret = %d", ret); 6942 6943 return ret; 6944 } 6945 6946 static uint32_t 6947 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa) 6948 { 6949 struct hns3_mac *mac = &hw->mac; 6950 uint32_t cur_capa; 6951 6952 switch (mac->link_speed) { 6953 case ETH_SPEED_NUM_10G: 6954 cur_capa = fec_capa[1].capa; 6955 break; 6956 case ETH_SPEED_NUM_25G: 6957 case ETH_SPEED_NUM_100G: 6958 case ETH_SPEED_NUM_200G: 6959 cur_capa = fec_capa[0].capa; 6960 break; 6961 default: 6962 cur_capa = 0; 6963 break; 6964 } 6965 6966 return cur_capa; 6967 } 6968 6969 static bool 6970 is_fec_mode_one_bit_set(uint32_t mode) 6971 { 6972 int cnt = 0; 6973 uint8_t i; 6974 6975 for (i = 0; i < sizeof(mode); i++) 6976 if (mode >> i & 0x1) 6977 cnt++; 6978 6979 return cnt == 1 ? true : false; 6980 } 6981 6982 static int 6983 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) 6984 { 6985 #define FEC_CAPA_NUM 2 6986 struct hns3_adapter *hns = dev->data->dev_private; 6987 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6988 struct hns3_pf *pf = &hns->pf; 6989 6990 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM]; 6991 uint32_t cur_capa; 6992 uint32_t num = FEC_CAPA_NUM; 6993 int ret; 6994 6995 ret = hns3_fec_get_capability(dev, fec_capa, num); 6996 if (ret < 0) 6997 return ret; 6998 6999 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */ 7000 if (!is_fec_mode_one_bit_set(mode)) 7001 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD," 7002 "FEC mode should be only one bit set", mode); 7003 7004 /* 7005 * Check whether the configured mode is within the FEC capability. 7006 * If not, the configured mode will not be supported. 7007 */ 7008 cur_capa = get_current_speed_fec_cap(hw, fec_capa); 7009 if (!(cur_capa & mode)) { 7010 hns3_err(hw, "unsupported FEC mode = 0x%x", mode); 7011 return -EINVAL; 7012 } 7013 7014 rte_spinlock_lock(&hw->lock); 7015 ret = hns3_set_fec_hw(hw, mode); 7016 if (ret) { 7017 rte_spinlock_unlock(&hw->lock); 7018 return ret; 7019 } 7020 7021 pf->fec_mode = mode; 7022 rte_spinlock_unlock(&hw->lock); 7023 7024 return 0; 7025 } 7026 7027 static int 7028 hns3_restore_fec(struct hns3_hw *hw) 7029 { 7030 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 7031 struct hns3_pf *pf = &hns->pf; 7032 uint32_t mode = pf->fec_mode; 7033 int ret; 7034 7035 ret = hns3_set_fec_hw(hw, mode); 7036 if (ret) 7037 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d", 7038 mode, ret); 7039 7040 return ret; 7041 } 7042 7043 static int 7044 hns3_query_dev_fec_info(struct hns3_hw *hw) 7045 { 7046 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 7047 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns); 7048 int ret; 7049 7050 ret = hns3_fec_get_internal(hw, &pf->fec_mode); 7051 if (ret) 7052 hns3_err(hw, "query device FEC info failed, ret = %d", ret); 7053 7054 return ret; 7055 } 7056 7057 static bool 7058 hns3_optical_module_existed(struct hns3_hw *hw) 7059 { 7060 struct hns3_cmd_desc desc; 7061 bool existed; 7062 int ret; 7063 7064 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true); 7065 ret = hns3_cmd_send(hw, &desc, 1); 7066 if (ret) { 7067 hns3_err(hw, 7068 "fail to get optical module exist state, ret = %d.\n", 7069 ret); 7070 return false; 7071 } 7072 existed = !!desc.data[0]; 7073 7074 return existed; 7075 } 7076 7077 static int 7078 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset, 7079 uint32_t len, uint8_t *data) 7080 { 7081 #define HNS3_SFP_INFO_CMD_NUM 6 7082 #define HNS3_SFP_INFO_MAX_LEN \ 7083 (HNS3_SFP_INFO_BD0_LEN + \ 7084 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN) 7085 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM]; 7086 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0; 7087 uint16_t read_len; 7088 uint16_t copy_len; 7089 int ret; 7090 int i; 7091 7092 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) { 7093 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM, 7094 true); 7095 if (i < HNS3_SFP_INFO_CMD_NUM - 1) 7096 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 7097 } 7098 7099 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data; 7100 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset); 7101 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN); 7102 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len); 7103 7104 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM); 7105 if (ret) { 7106 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n", 7107 ret); 7108 return ret; 7109 } 7110 7111 /* The data format in BD0 is different with the others. */ 7112 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN); 7113 memcpy(data, sfp_info_bd0->data, copy_len); 7114 read_len = copy_len; 7115 7116 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) { 7117 if (read_len >= len) 7118 break; 7119 7120 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN); 7121 memcpy(data + read_len, desc[i].data, copy_len); 7122 read_len += copy_len; 7123 } 7124 7125 return (int)read_len; 7126 } 7127 7128 static int 7129 hns3_get_module_eeprom(struct rte_eth_dev *dev, 7130 struct rte_dev_eeprom_info *info) 7131 { 7132 struct hns3_adapter *hns = dev->data->dev_private; 7133 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7134 uint32_t offset = info->offset; 7135 uint32_t len = info->length; 7136 uint8_t *data = info->data; 7137 uint32_t read_len = 0; 7138 7139 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER) 7140 return -ENOTSUP; 7141 7142 if (!hns3_optical_module_existed(hw)) { 7143 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n"); 7144 return -EIO; 7145 } 7146 7147 while (read_len < len) { 7148 int ret; 7149 ret = hns3_get_module_eeprom_data(hw, offset + read_len, 7150 len - read_len, 7151 data + read_len); 7152 if (ret < 0) 7153 return -EIO; 7154 read_len += ret; 7155 } 7156 7157 return 0; 7158 } 7159 7160 static int 7161 hns3_get_module_info(struct rte_eth_dev *dev, 7162 struct rte_eth_dev_module_info *modinfo) 7163 { 7164 #define HNS3_SFF8024_ID_SFP 0x03 7165 #define HNS3_SFF8024_ID_QSFP_8438 0x0c 7166 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d 7167 #define HNS3_SFF8024_ID_QSFP28_8636 0x11 7168 #define HNS3_SFF_8636_V1_3 0x03 7169 struct hns3_adapter *hns = dev->data->dev_private; 7170 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7171 struct rte_dev_eeprom_info info; 7172 struct hns3_sfp_type sfp_type; 7173 int ret; 7174 7175 memset(&sfp_type, 0, sizeof(sfp_type)); 7176 memset(&info, 0, sizeof(info)); 7177 info.data = (uint8_t *)&sfp_type; 7178 info.length = sizeof(sfp_type); 7179 ret = hns3_get_module_eeprom(dev, &info); 7180 if (ret) 7181 return ret; 7182 7183 switch (sfp_type.type) { 7184 case HNS3_SFF8024_ID_SFP: 7185 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7186 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7187 break; 7188 case HNS3_SFF8024_ID_QSFP_8438: 7189 modinfo->type = RTE_ETH_MODULE_SFF_8436; 7190 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 7191 break; 7192 case HNS3_SFF8024_ID_QSFP_8436_8636: 7193 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) { 7194 modinfo->type = RTE_ETH_MODULE_SFF_8436; 7195 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 7196 } else { 7197 modinfo->type = RTE_ETH_MODULE_SFF_8636; 7198 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 7199 } 7200 break; 7201 case HNS3_SFF8024_ID_QSFP28_8636: 7202 modinfo->type = RTE_ETH_MODULE_SFF_8636; 7203 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 7204 break; 7205 default: 7206 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n", 7207 sfp_type.type, sfp_type.ext_type); 7208 return -EINVAL; 7209 } 7210 7211 return 0; 7212 } 7213 7214 static int 7215 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) 7216 { 7217 uint32_t hint = HNS3_IO_FUNC_HINT_NONE; 7218 7219 RTE_SET_USED(key); 7220 7221 if (strcmp(value, "vec") == 0) 7222 hint = HNS3_IO_FUNC_HINT_VEC; 7223 else if (strcmp(value, "sve") == 0) 7224 hint = HNS3_IO_FUNC_HINT_SVE; 7225 else if (strcmp(value, "simple") == 0) 7226 hint = HNS3_IO_FUNC_HINT_SIMPLE; 7227 else if (strcmp(value, "common") == 0) 7228 hint = HNS3_IO_FUNC_HINT_COMMON; 7229 7230 /* If the hint is valid then update output parameters */ 7231 if (hint != HNS3_IO_FUNC_HINT_NONE) 7232 *(uint32_t *)extra_args = hint; 7233 7234 return 0; 7235 } 7236 7237 static const char * 7238 hns3_get_io_hint_func_name(uint32_t hint) 7239 { 7240 switch (hint) { 7241 case HNS3_IO_FUNC_HINT_VEC: 7242 return "vec"; 7243 case HNS3_IO_FUNC_HINT_SVE: 7244 return "sve"; 7245 case HNS3_IO_FUNC_HINT_SIMPLE: 7246 return "simple"; 7247 case HNS3_IO_FUNC_HINT_COMMON: 7248 return "common"; 7249 default: 7250 return "none"; 7251 } 7252 } 7253 7254 static int 7255 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args) 7256 { 7257 uint64_t val; 7258 7259 RTE_SET_USED(key); 7260 7261 val = strtoull(value, NULL, 16); 7262 *(uint64_t *)extra_args = val; 7263 7264 return 0; 7265 } 7266 7267 void 7268 hns3_parse_devargs(struct rte_eth_dev *dev) 7269 { 7270 struct hns3_adapter *hns = dev->data->dev_private; 7271 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; 7272 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; 7273 struct hns3_hw *hw = &hns->hw; 7274 uint64_t dev_caps_mask = 0; 7275 struct rte_kvargs *kvlist; 7276 7277 if (dev->device->devargs == NULL) 7278 return; 7279 7280 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); 7281 if (!kvlist) 7282 return; 7283 7284 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, 7285 &hns3_parse_io_hint_func, &rx_func_hint); 7286 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, 7287 &hns3_parse_io_hint_func, &tx_func_hint); 7288 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK, 7289 &hns3_parse_dev_caps_mask, &dev_caps_mask); 7290 rte_kvargs_free(kvlist); 7291 7292 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) 7293 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, 7294 hns3_get_io_hint_func_name(rx_func_hint)); 7295 hns->rx_func_hint = rx_func_hint; 7296 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) 7297 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, 7298 hns3_get_io_hint_func_name(tx_func_hint)); 7299 hns->tx_func_hint = tx_func_hint; 7300 7301 if (dev_caps_mask != 0) 7302 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".", 7303 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask); 7304 hns->dev_caps_mask = dev_caps_mask; 7305 } 7306 7307 static const struct eth_dev_ops hns3_eth_dev_ops = { 7308 .dev_configure = hns3_dev_configure, 7309 .dev_start = hns3_dev_start, 7310 .dev_stop = hns3_dev_stop, 7311 .dev_close = hns3_dev_close, 7312 .promiscuous_enable = hns3_dev_promiscuous_enable, 7313 .promiscuous_disable = hns3_dev_promiscuous_disable, 7314 .allmulticast_enable = hns3_dev_allmulticast_enable, 7315 .allmulticast_disable = hns3_dev_allmulticast_disable, 7316 .mtu_set = hns3_dev_mtu_set, 7317 .stats_get = hns3_stats_get, 7318 .stats_reset = hns3_stats_reset, 7319 .xstats_get = hns3_dev_xstats_get, 7320 .xstats_get_names = hns3_dev_xstats_get_names, 7321 .xstats_reset = hns3_dev_xstats_reset, 7322 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 7323 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 7324 .dev_infos_get = hns3_dev_infos_get, 7325 .fw_version_get = hns3_fw_version_get, 7326 .rx_queue_setup = hns3_rx_queue_setup, 7327 .tx_queue_setup = hns3_tx_queue_setup, 7328 .rx_queue_release = hns3_dev_rx_queue_release, 7329 .tx_queue_release = hns3_dev_tx_queue_release, 7330 .rx_queue_start = hns3_dev_rx_queue_start, 7331 .rx_queue_stop = hns3_dev_rx_queue_stop, 7332 .tx_queue_start = hns3_dev_tx_queue_start, 7333 .tx_queue_stop = hns3_dev_tx_queue_stop, 7334 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 7335 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 7336 .rxq_info_get = hns3_rxq_info_get, 7337 .txq_info_get = hns3_txq_info_get, 7338 .rx_burst_mode_get = hns3_rx_burst_mode_get, 7339 .tx_burst_mode_get = hns3_tx_burst_mode_get, 7340 .flow_ctrl_get = hns3_flow_ctrl_get, 7341 .flow_ctrl_set = hns3_flow_ctrl_set, 7342 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 7343 .mac_addr_add = hns3_add_mac_addr, 7344 .mac_addr_remove = hns3_remove_mac_addr, 7345 .mac_addr_set = hns3_set_default_mac_addr, 7346 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 7347 .link_update = hns3_dev_link_update, 7348 .rss_hash_update = hns3_dev_rss_hash_update, 7349 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 7350 .reta_update = hns3_dev_rss_reta_update, 7351 .reta_query = hns3_dev_rss_reta_query, 7352 .flow_ops_get = hns3_dev_flow_ops_get, 7353 .vlan_filter_set = hns3_vlan_filter_set, 7354 .vlan_tpid_set = hns3_vlan_tpid_set, 7355 .vlan_offload_set = hns3_vlan_offload_set, 7356 .vlan_pvid_set = hns3_vlan_pvid_set, 7357 .get_reg = hns3_get_regs, 7358 .get_module_info = hns3_get_module_info, 7359 .get_module_eeprom = hns3_get_module_eeprom, 7360 .get_dcb_info = hns3_get_dcb_info, 7361 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 7362 .fec_get_capability = hns3_fec_get_capability, 7363 .fec_get = hns3_fec_get, 7364 .fec_set = hns3_fec_set, 7365 .tm_ops_get = hns3_tm_ops_get, 7366 .tx_done_cleanup = hns3_tx_done_cleanup, 7367 .timesync_enable = hns3_timesync_enable, 7368 .timesync_disable = hns3_timesync_disable, 7369 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp, 7370 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp, 7371 .timesync_adjust_time = hns3_timesync_adjust_time, 7372 .timesync_read_time = hns3_timesync_read_time, 7373 .timesync_write_time = hns3_timesync_write_time, 7374 }; 7375 7376 static const struct hns3_reset_ops hns3_reset_ops = { 7377 .reset_service = hns3_reset_service, 7378 .stop_service = hns3_stop_service, 7379 .prepare_reset = hns3_prepare_reset, 7380 .wait_hardware_ready = hns3_wait_hardware_ready, 7381 .reinit_dev = hns3_reinit_dev, 7382 .restore_conf = hns3_restore_conf, 7383 .start_service = hns3_start_service, 7384 }; 7385 7386 static int 7387 hns3_dev_init(struct rte_eth_dev *eth_dev) 7388 { 7389 struct hns3_adapter *hns = eth_dev->data->dev_private; 7390 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 7391 struct rte_ether_addr *eth_addr; 7392 struct hns3_hw *hw = &hns->hw; 7393 int ret; 7394 7395 PMD_INIT_FUNC_TRACE(); 7396 7397 eth_dev->process_private = (struct hns3_process_private *) 7398 rte_zmalloc_socket("hns3_filter_list", 7399 sizeof(struct hns3_process_private), 7400 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 7401 if (eth_dev->process_private == NULL) { 7402 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 7403 return -ENOMEM; 7404 } 7405 7406 hns3_flow_init(eth_dev); 7407 7408 hns3_set_rxtx_function(eth_dev); 7409 eth_dev->dev_ops = &hns3_eth_dev_ops; 7410 eth_dev->rx_queue_count = hns3_rx_queue_count; 7411 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 7412 ret = hns3_mp_init_secondary(); 7413 if (ret) { 7414 PMD_INIT_LOG(ERR, "Failed to init for secondary " 7415 "process, ret = %d", ret); 7416 goto err_mp_init_secondary; 7417 } 7418 7419 hw->secondary_cnt++; 7420 return 0; 7421 } 7422 7423 ret = hns3_mp_init_primary(); 7424 if (ret) { 7425 PMD_INIT_LOG(ERR, 7426 "Failed to init for primary process, ret = %d", 7427 ret); 7428 goto err_mp_init_primary; 7429 } 7430 7431 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 7432 hns->is_vf = false; 7433 hw->data = eth_dev->data; 7434 hns3_parse_devargs(eth_dev); 7435 7436 /* 7437 * Set default max packet size according to the mtu 7438 * default vale in DPDK frame. 7439 */ 7440 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 7441 7442 ret = hns3_reset_init(hw); 7443 if (ret) 7444 goto err_init_reset; 7445 hw->reset.ops = &hns3_reset_ops; 7446 7447 ret = hns3_init_pf(eth_dev); 7448 if (ret) { 7449 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 7450 goto err_init_pf; 7451 } 7452 7453 /* Allocate memory for storing MAC addresses */ 7454 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 7455 sizeof(struct rte_ether_addr) * 7456 HNS3_UC_MACADDR_NUM, 0); 7457 if (eth_dev->data->mac_addrs == NULL) { 7458 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 7459 "to store MAC addresses", 7460 sizeof(struct rte_ether_addr) * 7461 HNS3_UC_MACADDR_NUM); 7462 ret = -ENOMEM; 7463 goto err_rte_zmalloc; 7464 } 7465 7466 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 7467 if (!rte_is_valid_assigned_ether_addr(eth_addr)) { 7468 rte_eth_random_addr(hw->mac.mac_addr); 7469 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 7470 (struct rte_ether_addr *)hw->mac.mac_addr); 7471 hns3_warn(hw, "default mac_addr from firmware is an invalid " 7472 "unicast address, using random MAC address %s", 7473 mac_str); 7474 } 7475 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 7476 ð_dev->data->mac_addrs[0]); 7477 7478 hw->adapter_state = HNS3_NIC_INITIALIZED; 7479 7480 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 7481 SCHEDULE_PENDING) { 7482 hns3_err(hw, "Reschedule reset service after dev_init"); 7483 hns3_schedule_reset(hns); 7484 } else { 7485 /* IMP will wait ready flag before reset */ 7486 hns3_notify_reset_ready(hw, false); 7487 } 7488 7489 hns3_info(hw, "hns3 dev initialization successful!"); 7490 return 0; 7491 7492 err_rte_zmalloc: 7493 hns3_uninit_pf(eth_dev); 7494 7495 err_init_pf: 7496 rte_free(hw->reset.wait_data); 7497 7498 err_init_reset: 7499 hns3_mp_uninit_primary(); 7500 7501 err_mp_init_primary: 7502 err_mp_init_secondary: 7503 eth_dev->dev_ops = NULL; 7504 eth_dev->rx_pkt_burst = NULL; 7505 eth_dev->rx_descriptor_status = NULL; 7506 eth_dev->tx_pkt_burst = NULL; 7507 eth_dev->tx_pkt_prepare = NULL; 7508 eth_dev->tx_descriptor_status = NULL; 7509 rte_free(eth_dev->process_private); 7510 eth_dev->process_private = NULL; 7511 return ret; 7512 } 7513 7514 static int 7515 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 7516 { 7517 struct hns3_adapter *hns = eth_dev->data->dev_private; 7518 struct hns3_hw *hw = &hns->hw; 7519 7520 PMD_INIT_FUNC_TRACE(); 7521 7522 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 7523 rte_free(eth_dev->process_private); 7524 eth_dev->process_private = NULL; 7525 return 0; 7526 } 7527 7528 if (hw->adapter_state < HNS3_NIC_CLOSING) 7529 hns3_dev_close(eth_dev); 7530 7531 hw->adapter_state = HNS3_NIC_REMOVED; 7532 return 0; 7533 } 7534 7535 static int 7536 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 7537 struct rte_pci_device *pci_dev) 7538 { 7539 return rte_eth_dev_pci_generic_probe(pci_dev, 7540 sizeof(struct hns3_adapter), 7541 hns3_dev_init); 7542 } 7543 7544 static int 7545 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 7546 { 7547 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 7548 } 7549 7550 static const struct rte_pci_id pci_id_hns3_map[] = { 7551 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 7552 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 7553 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 7554 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 7555 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 7556 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 7557 { .vendor_id = 0, }, /* sentinel */ 7558 }; 7559 7560 static struct rte_pci_driver rte_hns3_pmd = { 7561 .id_table = pci_id_hns3_map, 7562 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 7563 .probe = eth_hns3_pci_probe, 7564 .remove = eth_hns3_pci_remove, 7565 }; 7566 7567 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 7568 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 7569 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 7570 RTE_PMD_REGISTER_PARAM_STRING(net_hns3, 7571 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 7572 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " 7573 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "); 7574 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); 7575 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); 7576