1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <rte_alarm.h> 6 #include <rte_bus_pci.h> 7 #include <ethdev_pci.h> 8 #include <rte_pci.h> 9 #include <rte_kvargs.h> 10 11 #include "hns3_ethdev.h" 12 #include "hns3_logs.h" 13 #include "hns3_rxtx.h" 14 #include "hns3_intr.h" 15 #include "hns3_regs.h" 16 #include "hns3_dcb.h" 17 #include "hns3_mp.h" 18 19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 20 #define HNS3_SERVICE_QUICK_INTERVAL 10 21 #define HNS3_INVALID_PVID 0xFFFF 22 23 #define HNS3_FILTER_TYPE_VF 0 24 #define HNS3_FILTER_TYPE_PORT 1 25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 31 | HNS3_FILTER_FE_ROCE_EGRESS_B) 32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 33 | HNS3_FILTER_FE_ROCE_INGRESS_B) 34 35 /* Reset related Registers */ 36 #define HNS3_GLOBAL_RESET_BIT 0 37 #define HNS3_CORE_RESET_BIT 1 38 #define HNS3_IMP_RESET_BIT 2 39 #define HNS3_FUN_RST_ING_B 0 40 41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 45 46 #define HNS3_RESET_WAIT_MS 100 47 #define HNS3_RESET_WAIT_CNT 200 48 49 /* FEC mode order defined in HNS3 hardware */ 50 #define HNS3_HW_FEC_MODE_NOFEC 0 51 #define HNS3_HW_FEC_MODE_BASER 1 52 #define HNS3_HW_FEC_MODE_RS 2 53 54 enum hns3_evt_cause { 55 HNS3_VECTOR0_EVENT_RST, 56 HNS3_VECTOR0_EVENT_MBX, 57 HNS3_VECTOR0_EVENT_ERR, 58 HNS3_VECTOR0_EVENT_PTP, 59 HNS3_VECTOR0_EVENT_OTHER, 60 }; 61 62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { 63 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 66 67 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 71 72 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 75 76 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 80 81 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 84 85 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) } 88 }; 89 90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 91 uint64_t *levels); 92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 94 int on); 95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev); 96 static bool hns3_update_link_status(struct hns3_hw *hw); 97 98 static int hns3_add_mc_addr(struct hns3_hw *hw, 99 struct rte_ether_addr *mac_addr); 100 static int hns3_remove_mc_addr(struct hns3_hw *hw, 101 struct rte_ether_addr *mac_addr); 102 static int hns3_restore_fec(struct hns3_hw *hw); 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw); 104 static int hns3_do_stop(struct hns3_adapter *hns); 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds); 106 107 void hns3_ether_format_addr(char *buf, uint16_t size, 108 const struct rte_ether_addr *ether_addr) 109 { 110 snprintf(buf, size, "%02X:**:**:**:%02X:%02X", 111 ether_addr->addr_bytes[0], 112 ether_addr->addr_bytes[4], 113 ether_addr->addr_bytes[5]); 114 } 115 116 static void 117 hns3_pf_disable_irq0(struct hns3_hw *hw) 118 { 119 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 120 } 121 122 static void 123 hns3_pf_enable_irq0(struct hns3_hw *hw) 124 { 125 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 126 } 127 128 static enum hns3_evt_cause 129 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, 130 uint32_t *vec_val) 131 { 132 struct hns3_hw *hw = &hns->hw; 133 134 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 135 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 136 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 137 if (!is_delay) { 138 hw->reset.stats.imp_cnt++; 139 hns3_warn(hw, "IMP reset detected, clear reset status"); 140 } else { 141 hns3_schedule_delayed_reset(hns); 142 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 143 } 144 145 return HNS3_VECTOR0_EVENT_RST; 146 } 147 148 static enum hns3_evt_cause 149 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, 150 uint32_t *vec_val) 151 { 152 struct hns3_hw *hw = &hns->hw; 153 154 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 155 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 156 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 157 if (!is_delay) { 158 hw->reset.stats.global_cnt++; 159 hns3_warn(hw, "Global reset detected, clear reset status"); 160 } else { 161 hns3_schedule_delayed_reset(hns); 162 hns3_warn(hw, 163 "Global reset detected, don't clear reset status"); 164 } 165 166 return HNS3_VECTOR0_EVENT_RST; 167 } 168 169 static enum hns3_evt_cause 170 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 171 { 172 struct hns3_hw *hw = &hns->hw; 173 uint32_t vector0_int_stats; 174 uint32_t cmdq_src_val; 175 uint32_t hw_err_src_reg; 176 uint32_t val; 177 enum hns3_evt_cause ret; 178 bool is_delay; 179 180 /* fetch the events from their corresponding regs */ 181 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 182 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 183 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 184 185 is_delay = clearval == NULL ? true : false; 186 /* 187 * Assumption: If by any chance reset and mailbox events are reported 188 * together then we will only process reset event and defer the 189 * processing of the mailbox events. Since, we would have not cleared 190 * RX CMDQ event this time we would receive again another interrupt 191 * from H/W just for the mailbox. 192 */ 193 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 194 ret = hns3_proc_imp_reset_event(hns, is_delay, &val); 195 goto out; 196 } 197 198 /* Global reset */ 199 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 200 ret = hns3_proc_global_reset_event(hns, is_delay, &val); 201 goto out; 202 } 203 204 /* Check for vector0 1588 event source */ 205 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) { 206 val = BIT(HNS3_VECTOR0_1588_INT_B); 207 ret = HNS3_VECTOR0_EVENT_PTP; 208 goto out; 209 } 210 211 /* check for vector0 msix event source */ 212 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 213 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 214 val = vector0_int_stats | hw_err_src_reg; 215 ret = HNS3_VECTOR0_EVENT_ERR; 216 goto out; 217 } 218 219 /* check for vector0 mailbox(=CMDQ RX) event source */ 220 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 221 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 222 val = cmdq_src_val; 223 ret = HNS3_VECTOR0_EVENT_MBX; 224 goto out; 225 } 226 227 val = vector0_int_stats; 228 ret = HNS3_VECTOR0_EVENT_OTHER; 229 out: 230 231 if (clearval) 232 *clearval = val; 233 return ret; 234 } 235 236 static bool 237 hns3_is_1588_event_type(uint32_t event_type) 238 { 239 return (event_type == HNS3_VECTOR0_EVENT_PTP); 240 } 241 242 static void 243 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 244 { 245 if (event_type == HNS3_VECTOR0_EVENT_RST || 246 hns3_is_1588_event_type(event_type)) 247 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 248 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 249 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 250 } 251 252 static void 253 hns3_clear_all_event_cause(struct hns3_hw *hw) 254 { 255 uint32_t vector0_int_stats; 256 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 257 258 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 259 hns3_warn(hw, "Probe during IMP reset interrupt"); 260 261 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 262 hns3_warn(hw, "Probe during Global reset interrupt"); 263 264 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 265 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 266 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 267 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 268 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 269 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP, 270 BIT(HNS3_VECTOR0_1588_INT_B)); 271 } 272 273 static void 274 hns3_handle_mac_tnl(struct hns3_hw *hw) 275 { 276 struct hns3_cmd_desc desc; 277 uint32_t status; 278 int ret; 279 280 /* query and clear mac tnl interrupt */ 281 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true); 282 ret = hns3_cmd_send(hw, &desc, 1); 283 if (ret) { 284 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret); 285 return; 286 } 287 288 status = rte_le_to_cpu_32(desc.data[0]); 289 if (status) { 290 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status); 291 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT, 292 false); 293 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR); 294 ret = hns3_cmd_send(hw, &desc, 1); 295 if (ret) 296 hns3_err(hw, "failed to clear mac tnl int, ret = %d.", 297 ret); 298 } 299 } 300 301 static void 302 hns3_interrupt_handler(void *param) 303 { 304 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 305 struct hns3_adapter *hns = dev->data->dev_private; 306 struct hns3_hw *hw = &hns->hw; 307 enum hns3_evt_cause event_cause; 308 uint32_t clearval = 0; 309 uint32_t vector0_int; 310 uint32_t ras_int; 311 uint32_t cmdq_int; 312 313 /* Disable interrupt */ 314 hns3_pf_disable_irq0(hw); 315 316 event_cause = hns3_check_event_cause(hns, &clearval); 317 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 318 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 319 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 320 /* vector 0 interrupt is shared with reset and mailbox source events. */ 321 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 322 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " 323 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 324 vector0_int, ras_int, cmdq_int); 325 hns3_handle_mac_tnl(hw); 326 hns3_handle_error(hns); 327 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 328 hns3_warn(hw, "received reset interrupt"); 329 hns3_schedule_reset(hns); 330 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) { 331 hns3_dev_handle_mbx_msg(hw); 332 } else { 333 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x " 334 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 335 vector0_int, ras_int, cmdq_int); 336 } 337 338 hns3_clear_event_cause(hw, event_cause, clearval); 339 /* Enable interrupt if it is not cause by reset */ 340 hns3_pf_enable_irq0(hw); 341 } 342 343 static int 344 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 345 { 346 #define HNS3_VLAN_ID_OFFSET_STEP 160 347 #define HNS3_VLAN_BYTE_SIZE 8 348 struct hns3_vlan_filter_pf_cfg_cmd *req; 349 struct hns3_hw *hw = &hns->hw; 350 uint8_t vlan_offset_byte_val; 351 struct hns3_cmd_desc desc; 352 uint8_t vlan_offset_byte; 353 uint8_t vlan_offset_base; 354 int ret; 355 356 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 357 358 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 359 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 360 HNS3_VLAN_BYTE_SIZE; 361 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 362 363 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 364 req->vlan_offset = vlan_offset_base; 365 req->vlan_cfg = on ? 0 : 1; 366 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 367 368 ret = hns3_cmd_send(hw, &desc, 1); 369 if (ret) 370 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 371 vlan_id, ret); 372 373 return ret; 374 } 375 376 static void 377 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 378 { 379 struct hns3_user_vlan_table *vlan_entry; 380 struct hns3_pf *pf = &hns->pf; 381 382 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 383 if (vlan_entry->vlan_id == vlan_id) { 384 if (vlan_entry->hd_tbl_status) 385 hns3_set_port_vlan_filter(hns, vlan_id, 0); 386 LIST_REMOVE(vlan_entry, next); 387 rte_free(vlan_entry); 388 break; 389 } 390 } 391 } 392 393 static void 394 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 395 bool writen_to_tbl) 396 { 397 struct hns3_user_vlan_table *vlan_entry; 398 struct hns3_hw *hw = &hns->hw; 399 struct hns3_pf *pf = &hns->pf; 400 401 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 402 if (vlan_entry->vlan_id == vlan_id) 403 return; 404 } 405 406 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 407 if (vlan_entry == NULL) { 408 hns3_err(hw, "Failed to malloc hns3 vlan table"); 409 return; 410 } 411 412 vlan_entry->hd_tbl_status = writen_to_tbl; 413 vlan_entry->vlan_id = vlan_id; 414 415 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 416 } 417 418 static int 419 hns3_restore_vlan_table(struct hns3_adapter *hns) 420 { 421 struct hns3_user_vlan_table *vlan_entry; 422 struct hns3_hw *hw = &hns->hw; 423 struct hns3_pf *pf = &hns->pf; 424 uint16_t vlan_id; 425 int ret = 0; 426 427 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 428 return hns3_vlan_pvid_configure(hns, 429 hw->port_base_vlan_cfg.pvid, 1); 430 431 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 432 if (vlan_entry->hd_tbl_status) { 433 vlan_id = vlan_entry->vlan_id; 434 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 435 if (ret) 436 break; 437 } 438 } 439 440 return ret; 441 } 442 443 static int 444 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 445 { 446 struct hns3_hw *hw = &hns->hw; 447 bool writen_to_tbl = false; 448 int ret = 0; 449 450 /* 451 * When vlan filter is enabled, hardware regards packets without vlan 452 * as packets with vlan 0. So, to receive packets without vlan, vlan id 453 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter. 454 */ 455 if (on == 0 && vlan_id == 0) 456 return 0; 457 458 /* 459 * When port base vlan enabled, we use port base vlan as the vlan 460 * filter condition. In this case, we don't update vlan filter table 461 * when user add new vlan or remove exist vlan, just update the 462 * vlan list. The vlan id in vlan list will be written in vlan filter 463 * table until port base vlan disabled 464 */ 465 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 466 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 467 writen_to_tbl = true; 468 } 469 470 if (ret == 0) { 471 if (on) 472 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 473 else 474 hns3_rm_dev_vlan_table(hns, vlan_id); 475 } 476 return ret; 477 } 478 479 static int 480 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 481 { 482 struct hns3_adapter *hns = dev->data->dev_private; 483 struct hns3_hw *hw = &hns->hw; 484 int ret; 485 486 rte_spinlock_lock(&hw->lock); 487 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 488 rte_spinlock_unlock(&hw->lock); 489 return ret; 490 } 491 492 static int 493 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 494 uint16_t tpid) 495 { 496 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 497 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 498 struct hns3_hw *hw = &hns->hw; 499 struct hns3_cmd_desc desc; 500 int ret; 501 502 if ((vlan_type != ETH_VLAN_TYPE_INNER && 503 vlan_type != ETH_VLAN_TYPE_OUTER)) { 504 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 505 return -EINVAL; 506 } 507 508 if (tpid != RTE_ETHER_TYPE_VLAN) { 509 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 510 return -EINVAL; 511 } 512 513 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 514 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 515 516 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 517 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 518 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 519 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 520 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 521 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 522 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 523 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 524 } 525 526 ret = hns3_cmd_send(hw, &desc, 1); 527 if (ret) { 528 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 529 ret); 530 return ret; 531 } 532 533 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 534 535 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 536 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 537 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 538 539 ret = hns3_cmd_send(hw, &desc, 1); 540 if (ret) 541 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 542 ret); 543 return ret; 544 } 545 546 static int 547 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 548 uint16_t tpid) 549 { 550 struct hns3_adapter *hns = dev->data->dev_private; 551 struct hns3_hw *hw = &hns->hw; 552 int ret; 553 554 rte_spinlock_lock(&hw->lock); 555 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 556 rte_spinlock_unlock(&hw->lock); 557 return ret; 558 } 559 560 static int 561 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 562 struct hns3_rx_vtag_cfg *vcfg) 563 { 564 struct hns3_vport_vtag_rx_cfg_cmd *req; 565 struct hns3_hw *hw = &hns->hw; 566 struct hns3_cmd_desc desc; 567 uint16_t vport_id; 568 uint8_t bitmap; 569 int ret; 570 571 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 572 573 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 574 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 575 vcfg->strip_tag1_en ? 1 : 0); 576 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 577 vcfg->strip_tag2_en ? 1 : 0); 578 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 579 vcfg->vlan1_vlan_prionly ? 1 : 0); 580 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 581 vcfg->vlan2_vlan_prionly ? 1 : 0); 582 583 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 584 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B, 585 vcfg->strip_tag1_discard_en ? 1 : 0); 586 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B, 587 vcfg->strip_tag2_discard_en ? 1 : 0); 588 /* 589 * In current version VF is not supported when PF is driven by DPDK 590 * driver, just need to configure parameters for PF vport. 591 */ 592 vport_id = HNS3_PF_FUNC_ID; 593 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 594 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 595 req->vf_bitmap[req->vf_offset] = bitmap; 596 597 ret = hns3_cmd_send(hw, &desc, 1); 598 if (ret) 599 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 600 return ret; 601 } 602 603 static void 604 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 605 struct hns3_rx_vtag_cfg *vcfg) 606 { 607 struct hns3_pf *pf = &hns->pf; 608 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 609 } 610 611 static void 612 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 613 struct hns3_tx_vtag_cfg *vcfg) 614 { 615 struct hns3_pf *pf = &hns->pf; 616 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 617 } 618 619 static int 620 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 621 { 622 struct hns3_rx_vtag_cfg rxvlan_cfg; 623 struct hns3_hw *hw = &hns->hw; 624 int ret; 625 626 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 627 rxvlan_cfg.strip_tag1_en = false; 628 rxvlan_cfg.strip_tag2_en = enable; 629 rxvlan_cfg.strip_tag2_discard_en = false; 630 } else { 631 rxvlan_cfg.strip_tag1_en = enable; 632 rxvlan_cfg.strip_tag2_en = true; 633 rxvlan_cfg.strip_tag2_discard_en = true; 634 } 635 636 rxvlan_cfg.strip_tag1_discard_en = false; 637 rxvlan_cfg.vlan1_vlan_prionly = false; 638 rxvlan_cfg.vlan2_vlan_prionly = false; 639 rxvlan_cfg.rx_vlan_offload_en = enable; 640 641 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 642 if (ret) { 643 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret); 644 return ret; 645 } 646 647 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 648 649 return ret; 650 } 651 652 static int 653 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 654 uint8_t fe_type, bool filter_en, uint8_t vf_id) 655 { 656 struct hns3_vlan_filter_ctrl_cmd *req; 657 struct hns3_cmd_desc desc; 658 int ret; 659 660 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 661 662 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 663 req->vlan_type = vlan_type; 664 req->vlan_fe = filter_en ? fe_type : 0; 665 req->vf_id = vf_id; 666 667 ret = hns3_cmd_send(hw, &desc, 1); 668 if (ret) 669 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 670 671 return ret; 672 } 673 674 static int 675 hns3_vlan_filter_init(struct hns3_adapter *hns) 676 { 677 struct hns3_hw *hw = &hns->hw; 678 int ret; 679 680 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 681 HNS3_FILTER_FE_EGRESS, false, 682 HNS3_PF_FUNC_ID); 683 if (ret) { 684 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 685 return ret; 686 } 687 688 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 689 HNS3_FILTER_FE_INGRESS, false, 690 HNS3_PF_FUNC_ID); 691 if (ret) 692 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 693 694 return ret; 695 } 696 697 static int 698 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 699 { 700 struct hns3_hw *hw = &hns->hw; 701 int ret; 702 703 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 704 HNS3_FILTER_FE_INGRESS, enable, 705 HNS3_PF_FUNC_ID); 706 if (ret) 707 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 708 enable ? "enable" : "disable", ret); 709 710 return ret; 711 } 712 713 static int 714 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 715 { 716 struct hns3_adapter *hns = dev->data->dev_private; 717 struct hns3_hw *hw = &hns->hw; 718 struct rte_eth_rxmode *rxmode; 719 unsigned int tmp_mask; 720 bool enable; 721 int ret = 0; 722 723 rte_spinlock_lock(&hw->lock); 724 rxmode = &dev->data->dev_conf.rxmode; 725 tmp_mask = (unsigned int)mask; 726 if (tmp_mask & ETH_VLAN_FILTER_MASK) { 727 /* ignore vlan filter configuration during promiscuous mode */ 728 if (!dev->data->promiscuous) { 729 /* Enable or disable VLAN filter */ 730 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? 731 true : false; 732 733 ret = hns3_enable_vlan_filter(hns, enable); 734 if (ret) { 735 rte_spinlock_unlock(&hw->lock); 736 hns3_err(hw, "failed to %s rx filter, ret = %d", 737 enable ? "enable" : "disable", ret); 738 return ret; 739 } 740 } 741 } 742 743 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 744 /* Enable or disable VLAN stripping */ 745 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 746 true : false; 747 748 ret = hns3_en_hw_strip_rxvtag(hns, enable); 749 if (ret) { 750 rte_spinlock_unlock(&hw->lock); 751 hns3_err(hw, "failed to %s rx strip, ret = %d", 752 enable ? "enable" : "disable", ret); 753 return ret; 754 } 755 } 756 757 rte_spinlock_unlock(&hw->lock); 758 759 return ret; 760 } 761 762 static int 763 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 764 struct hns3_tx_vtag_cfg *vcfg) 765 { 766 struct hns3_vport_vtag_tx_cfg_cmd *req; 767 struct hns3_cmd_desc desc; 768 struct hns3_hw *hw = &hns->hw; 769 uint16_t vport_id; 770 uint8_t bitmap; 771 int ret; 772 773 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 774 775 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 776 req->def_vlan_tag1 = vcfg->default_tag1; 777 req->def_vlan_tag2 = vcfg->default_tag2; 778 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 779 vcfg->accept_tag1 ? 1 : 0); 780 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 781 vcfg->accept_untag1 ? 1 : 0); 782 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 783 vcfg->accept_tag2 ? 1 : 0); 784 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 785 vcfg->accept_untag2 ? 1 : 0); 786 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 787 vcfg->insert_tag1_en ? 1 : 0); 788 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 789 vcfg->insert_tag2_en ? 1 : 0); 790 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 791 792 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 793 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B, 794 vcfg->tag_shift_mode_en ? 1 : 0); 795 796 /* 797 * In current version VF is not supported when PF is driven by DPDK 798 * driver, just need to configure parameters for PF vport. 799 */ 800 vport_id = HNS3_PF_FUNC_ID; 801 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 802 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 803 req->vf_bitmap[req->vf_offset] = bitmap; 804 805 ret = hns3_cmd_send(hw, &desc, 1); 806 if (ret) 807 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 808 809 return ret; 810 } 811 812 static int 813 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 814 uint16_t pvid) 815 { 816 struct hns3_hw *hw = &hns->hw; 817 struct hns3_tx_vtag_cfg txvlan_cfg; 818 int ret; 819 820 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 821 txvlan_cfg.accept_tag1 = true; 822 txvlan_cfg.insert_tag1_en = false; 823 txvlan_cfg.default_tag1 = 0; 824 } else { 825 txvlan_cfg.accept_tag1 = 826 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE; 827 txvlan_cfg.insert_tag1_en = true; 828 txvlan_cfg.default_tag1 = pvid; 829 } 830 831 txvlan_cfg.accept_untag1 = true; 832 txvlan_cfg.accept_tag2 = true; 833 txvlan_cfg.accept_untag2 = true; 834 txvlan_cfg.insert_tag2_en = false; 835 txvlan_cfg.default_tag2 = 0; 836 txvlan_cfg.tag_shift_mode_en = true; 837 838 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 839 if (ret) { 840 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 841 ret); 842 return ret; 843 } 844 845 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 846 return ret; 847 } 848 849 850 static void 851 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 852 { 853 struct hns3_user_vlan_table *vlan_entry; 854 struct hns3_pf *pf = &hns->pf; 855 856 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 857 if (vlan_entry->hd_tbl_status) { 858 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 859 vlan_entry->hd_tbl_status = false; 860 } 861 } 862 863 if (is_del_list) { 864 vlan_entry = LIST_FIRST(&pf->vlan_list); 865 while (vlan_entry) { 866 LIST_REMOVE(vlan_entry, next); 867 rte_free(vlan_entry); 868 vlan_entry = LIST_FIRST(&pf->vlan_list); 869 } 870 } 871 } 872 873 static void 874 hns3_add_all_vlan_table(struct hns3_adapter *hns) 875 { 876 struct hns3_user_vlan_table *vlan_entry; 877 struct hns3_pf *pf = &hns->pf; 878 879 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 880 if (!vlan_entry->hd_tbl_status) { 881 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 882 vlan_entry->hd_tbl_status = true; 883 } 884 } 885 } 886 887 static void 888 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 889 { 890 struct hns3_hw *hw = &hns->hw; 891 int ret; 892 893 hns3_rm_all_vlan_table(hns, true); 894 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) { 895 ret = hns3_set_port_vlan_filter(hns, 896 hw->port_base_vlan_cfg.pvid, 0); 897 if (ret) { 898 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 899 ret); 900 return; 901 } 902 } 903 } 904 905 static int 906 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 907 uint16_t port_base_vlan_state, uint16_t new_pvid) 908 { 909 struct hns3_hw *hw = &hns->hw; 910 uint16_t old_pvid; 911 int ret; 912 913 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 914 old_pvid = hw->port_base_vlan_cfg.pvid; 915 if (old_pvid != HNS3_INVALID_PVID) { 916 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 917 if (ret) { 918 hns3_err(hw, "failed to remove old pvid %u, " 919 "ret = %d", old_pvid, ret); 920 return ret; 921 } 922 } 923 924 hns3_rm_all_vlan_table(hns, false); 925 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1); 926 if (ret) { 927 hns3_err(hw, "failed to add new pvid %u, ret = %d", 928 new_pvid, ret); 929 return ret; 930 } 931 } else { 932 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 933 if (ret) { 934 hns3_err(hw, "failed to remove pvid %u, ret = %d", 935 new_pvid, ret); 936 return ret; 937 } 938 939 hns3_add_all_vlan_table(hns); 940 } 941 return 0; 942 } 943 944 static int 945 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 946 { 947 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 948 struct hns3_rx_vtag_cfg rx_vlan_cfg; 949 bool rx_strip_en; 950 int ret; 951 952 rx_strip_en = old_cfg->rx_vlan_offload_en; 953 if (on) { 954 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 955 rx_vlan_cfg.strip_tag2_en = true; 956 rx_vlan_cfg.strip_tag2_discard_en = true; 957 } else { 958 rx_vlan_cfg.strip_tag1_en = false; 959 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 960 rx_vlan_cfg.strip_tag2_discard_en = false; 961 } 962 rx_vlan_cfg.strip_tag1_discard_en = false; 963 rx_vlan_cfg.vlan1_vlan_prionly = false; 964 rx_vlan_cfg.vlan2_vlan_prionly = false; 965 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 966 967 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 968 if (ret) 969 return ret; 970 971 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 972 return ret; 973 } 974 975 static int 976 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 977 { 978 struct hns3_hw *hw = &hns->hw; 979 uint16_t port_base_vlan_state; 980 int ret, err; 981 982 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 983 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) 984 hns3_warn(hw, "Invalid operation! As current pvid set " 985 "is %u, disable pvid %u is invalid", 986 hw->port_base_vlan_cfg.pvid, pvid); 987 return 0; 988 } 989 990 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 991 HNS3_PORT_BASE_VLAN_DISABLE; 992 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 993 if (ret) { 994 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 995 ret); 996 return ret; 997 } 998 999 ret = hns3_en_pvid_strip(hns, on); 1000 if (ret) { 1001 hns3_err(hw, "failed to config rx vlan strip for pvid, " 1002 "ret = %d", ret); 1003 goto pvid_vlan_strip_fail; 1004 } 1005 1006 if (pvid == HNS3_INVALID_PVID) 1007 goto out; 1008 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid); 1009 if (ret) { 1010 hns3_err(hw, "failed to update vlan filter entries, ret = %d", 1011 ret); 1012 goto vlan_filter_set_fail; 1013 } 1014 1015 out: 1016 hw->port_base_vlan_cfg.state = port_base_vlan_state; 1017 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID; 1018 return ret; 1019 1020 vlan_filter_set_fail: 1021 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state == 1022 HNS3_PORT_BASE_VLAN_ENABLE); 1023 if (err) 1024 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err); 1025 1026 pvid_vlan_strip_fail: 1027 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state, 1028 hw->port_base_vlan_cfg.pvid); 1029 if (err) 1030 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err); 1031 1032 return ret; 1033 } 1034 1035 static int 1036 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 1037 { 1038 struct hns3_adapter *hns = dev->data->dev_private; 1039 struct hns3_hw *hw = &hns->hw; 1040 bool pvid_en_state_change; 1041 uint16_t pvid_state; 1042 int ret; 1043 1044 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 1045 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 1046 RTE_ETHER_MAX_VLAN_ID); 1047 return -EINVAL; 1048 } 1049 1050 /* 1051 * If PVID configuration state change, should refresh the PVID 1052 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 1053 */ 1054 pvid_state = hw->port_base_vlan_cfg.state; 1055 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 1056 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 1057 pvid_en_state_change = false; 1058 else 1059 pvid_en_state_change = true; 1060 1061 rte_spinlock_lock(&hw->lock); 1062 ret = hns3_vlan_pvid_configure(hns, pvid, on); 1063 rte_spinlock_unlock(&hw->lock); 1064 if (ret) 1065 return ret; 1066 /* 1067 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx 1068 * need be processed by PMD driver. 1069 */ 1070 if (pvid_en_state_change && 1071 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 1072 hns3_update_all_queues_pvid_proc_en(hw); 1073 1074 return 0; 1075 } 1076 1077 static int 1078 hns3_default_vlan_config(struct hns3_adapter *hns) 1079 { 1080 struct hns3_hw *hw = &hns->hw; 1081 int ret; 1082 1083 /* 1084 * When vlan filter is enabled, hardware regards packets without vlan 1085 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan 1086 * table, packets without vlan won't be received. So, add vlan 0 as 1087 * the default vlan. 1088 */ 1089 ret = hns3_vlan_filter_configure(hns, 0, 1); 1090 if (ret) 1091 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 1092 return ret; 1093 } 1094 1095 static int 1096 hns3_init_vlan_config(struct hns3_adapter *hns) 1097 { 1098 struct hns3_hw *hw = &hns->hw; 1099 int ret; 1100 1101 /* 1102 * This function can be called in the initialization and reset process, 1103 * when in reset process, it means that hardware had been reseted 1104 * successfully and we need to restore the hardware configuration to 1105 * ensure that the hardware configuration remains unchanged before and 1106 * after reset. 1107 */ 1108 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1109 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 1110 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID; 1111 } 1112 1113 ret = hns3_vlan_filter_init(hns); 1114 if (ret) { 1115 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 1116 return ret; 1117 } 1118 1119 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 1120 RTE_ETHER_TYPE_VLAN); 1121 if (ret) { 1122 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 1123 return ret; 1124 } 1125 1126 /* 1127 * When in the reinit dev stage of the reset process, the following 1128 * vlan-related configurations may differ from those at initialization, 1129 * we will restore configurations to hardware in hns3_restore_vlan_table 1130 * and hns3_restore_vlan_conf later. 1131 */ 1132 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1133 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0); 1134 if (ret) { 1135 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1136 return ret; 1137 } 1138 1139 ret = hns3_en_hw_strip_rxvtag(hns, false); 1140 if (ret) { 1141 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1142 ret); 1143 return ret; 1144 } 1145 } 1146 1147 return hns3_default_vlan_config(hns); 1148 } 1149 1150 static int 1151 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1152 { 1153 struct hns3_pf *pf = &hns->pf; 1154 struct hns3_hw *hw = &hns->hw; 1155 uint64_t offloads; 1156 bool enable; 1157 int ret; 1158 1159 if (!hw->data->promiscuous) { 1160 /* restore vlan filter states */ 1161 offloads = hw->data->dev_conf.rxmode.offloads; 1162 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false; 1163 ret = hns3_enable_vlan_filter(hns, enable); 1164 if (ret) { 1165 hns3_err(hw, "failed to restore vlan rx filter conf, " 1166 "ret = %d", ret); 1167 return ret; 1168 } 1169 } 1170 1171 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1172 if (ret) { 1173 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1174 return ret; 1175 } 1176 1177 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1178 if (ret) 1179 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1180 1181 return ret; 1182 } 1183 1184 static int 1185 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1186 { 1187 struct hns3_adapter *hns = dev->data->dev_private; 1188 struct rte_eth_dev_data *data = dev->data; 1189 struct rte_eth_txmode *txmode; 1190 struct hns3_hw *hw = &hns->hw; 1191 int mask; 1192 int ret; 1193 1194 txmode = &data->dev_conf.txmode; 1195 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1196 hns3_warn(hw, 1197 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1198 "configuration is not supported! Ignore these two " 1199 "parameters: hw_vlan_reject_tagged(%u), " 1200 "hw_vlan_reject_untagged(%u)", 1201 txmode->hw_vlan_reject_tagged, 1202 txmode->hw_vlan_reject_untagged); 1203 1204 /* Apply vlan offload setting */ 1205 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK; 1206 ret = hns3_vlan_offload_set(dev, mask); 1207 if (ret) { 1208 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1209 ret); 1210 return ret; 1211 } 1212 1213 /* 1214 * If pvid config is not set in rte_eth_conf, driver needn't to set 1215 * VLAN pvid related configuration to hardware. 1216 */ 1217 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1218 return 0; 1219 1220 /* Apply pvid setting */ 1221 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1222 txmode->hw_vlan_insert_pvid); 1223 if (ret) 1224 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d", 1225 txmode->pvid, ret); 1226 1227 return ret; 1228 } 1229 1230 static int 1231 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1232 unsigned int tso_mss_max) 1233 { 1234 struct hns3_cfg_tso_status_cmd *req; 1235 struct hns3_cmd_desc desc; 1236 uint16_t tso_mss; 1237 1238 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1239 1240 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1241 1242 tso_mss = 0; 1243 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1244 tso_mss_min); 1245 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1246 1247 tso_mss = 0; 1248 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1249 tso_mss_max); 1250 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1251 1252 return hns3_cmd_send(hw, &desc, 1); 1253 } 1254 1255 static int 1256 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1257 uint16_t *allocated_size, bool is_alloc) 1258 { 1259 struct hns3_umv_spc_alc_cmd *req; 1260 struct hns3_cmd_desc desc; 1261 int ret; 1262 1263 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1264 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1265 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1266 req->space_size = rte_cpu_to_le_32(space_size); 1267 1268 ret = hns3_cmd_send(hw, &desc, 1); 1269 if (ret) { 1270 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1271 is_alloc ? "allocate" : "free", ret); 1272 return ret; 1273 } 1274 1275 if (is_alloc && allocated_size) 1276 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1277 1278 return 0; 1279 } 1280 1281 static int 1282 hns3_init_umv_space(struct hns3_hw *hw) 1283 { 1284 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1285 struct hns3_pf *pf = &hns->pf; 1286 uint16_t allocated_size = 0; 1287 int ret; 1288 1289 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1290 true); 1291 if (ret) 1292 return ret; 1293 1294 if (allocated_size < pf->wanted_umv_size) 1295 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1296 pf->wanted_umv_size, allocated_size); 1297 1298 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1299 pf->wanted_umv_size; 1300 pf->used_umv_size = 0; 1301 return 0; 1302 } 1303 1304 static int 1305 hns3_uninit_umv_space(struct hns3_hw *hw) 1306 { 1307 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1308 struct hns3_pf *pf = &hns->pf; 1309 int ret; 1310 1311 if (pf->max_umv_size == 0) 1312 return 0; 1313 1314 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1315 if (ret) 1316 return ret; 1317 1318 pf->max_umv_size = 0; 1319 1320 return 0; 1321 } 1322 1323 static bool 1324 hns3_is_umv_space_full(struct hns3_hw *hw) 1325 { 1326 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1327 struct hns3_pf *pf = &hns->pf; 1328 bool is_full; 1329 1330 is_full = (pf->used_umv_size >= pf->max_umv_size); 1331 1332 return is_full; 1333 } 1334 1335 static void 1336 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1337 { 1338 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1339 struct hns3_pf *pf = &hns->pf; 1340 1341 if (is_free) { 1342 if (pf->used_umv_size > 0) 1343 pf->used_umv_size--; 1344 } else 1345 pf->used_umv_size++; 1346 } 1347 1348 static void 1349 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1350 const uint8_t *addr, bool is_mc) 1351 { 1352 const unsigned char *mac_addr = addr; 1353 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1354 ((uint32_t)mac_addr[2] << 16) | 1355 ((uint32_t)mac_addr[1] << 8) | 1356 (uint32_t)mac_addr[0]; 1357 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1358 1359 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1360 if (is_mc) { 1361 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1362 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1363 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1364 } 1365 1366 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1367 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1368 } 1369 1370 static int 1371 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1372 uint8_t resp_code, 1373 enum hns3_mac_vlan_tbl_opcode op) 1374 { 1375 if (cmdq_resp) { 1376 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1377 cmdq_resp); 1378 return -EIO; 1379 } 1380 1381 if (op == HNS3_MAC_VLAN_ADD) { 1382 if (resp_code == 0 || resp_code == 1) { 1383 return 0; 1384 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1385 hns3_err(hw, "add mac addr failed for uc_overflow"); 1386 return -ENOSPC; 1387 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1388 hns3_err(hw, "add mac addr failed for mc_overflow"); 1389 return -ENOSPC; 1390 } 1391 1392 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1393 resp_code); 1394 return -EIO; 1395 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1396 if (resp_code == 0) { 1397 return 0; 1398 } else if (resp_code == 1) { 1399 hns3_dbg(hw, "remove mac addr failed for miss"); 1400 return -ENOENT; 1401 } 1402 1403 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1404 resp_code); 1405 return -EIO; 1406 } else if (op == HNS3_MAC_VLAN_LKUP) { 1407 if (resp_code == 0) { 1408 return 0; 1409 } else if (resp_code == 1) { 1410 hns3_dbg(hw, "lookup mac addr failed for miss"); 1411 return -ENOENT; 1412 } 1413 1414 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1415 resp_code); 1416 return -EIO; 1417 } 1418 1419 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1420 op); 1421 1422 return -EINVAL; 1423 } 1424 1425 static int 1426 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1427 struct hns3_mac_vlan_tbl_entry_cmd *req, 1428 struct hns3_cmd_desc *desc, bool is_mc) 1429 { 1430 uint8_t resp_code; 1431 uint16_t retval; 1432 int ret; 1433 1434 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true); 1435 if (is_mc) { 1436 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1437 memcpy(desc[0].data, req, 1438 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1439 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD, 1440 true); 1441 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1442 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD, 1443 true); 1444 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1445 } else { 1446 memcpy(desc[0].data, req, 1447 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1448 ret = hns3_cmd_send(hw, desc, 1); 1449 } 1450 if (ret) { 1451 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1452 ret); 1453 return ret; 1454 } 1455 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1456 retval = rte_le_to_cpu_16(desc[0].retval); 1457 1458 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1459 HNS3_MAC_VLAN_LKUP); 1460 } 1461 1462 static int 1463 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1464 struct hns3_mac_vlan_tbl_entry_cmd *req, 1465 struct hns3_cmd_desc *mc_desc) 1466 { 1467 uint8_t resp_code; 1468 uint16_t retval; 1469 int cfg_status; 1470 int ret; 1471 1472 if (mc_desc == NULL) { 1473 struct hns3_cmd_desc desc; 1474 1475 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false); 1476 memcpy(desc.data, req, 1477 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1478 ret = hns3_cmd_send(hw, &desc, 1); 1479 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1480 retval = rte_le_to_cpu_16(desc.retval); 1481 1482 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1483 HNS3_MAC_VLAN_ADD); 1484 } else { 1485 hns3_cmd_reuse_desc(&mc_desc[0], false); 1486 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1487 hns3_cmd_reuse_desc(&mc_desc[1], false); 1488 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1489 hns3_cmd_reuse_desc(&mc_desc[2], false); 1490 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1491 memcpy(mc_desc[0].data, req, 1492 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1493 mc_desc[0].retval = 0; 1494 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1495 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff; 1496 retval = rte_le_to_cpu_16(mc_desc[0].retval); 1497 1498 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1499 HNS3_MAC_VLAN_ADD); 1500 } 1501 1502 if (ret) { 1503 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1504 return ret; 1505 } 1506 1507 return cfg_status; 1508 } 1509 1510 static int 1511 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1512 struct hns3_mac_vlan_tbl_entry_cmd *req) 1513 { 1514 struct hns3_cmd_desc desc; 1515 uint8_t resp_code; 1516 uint16_t retval; 1517 int ret; 1518 1519 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1520 1521 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1522 1523 ret = hns3_cmd_send(hw, &desc, 1); 1524 if (ret) { 1525 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1526 return ret; 1527 } 1528 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1529 retval = rte_le_to_cpu_16(desc.retval); 1530 1531 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1532 HNS3_MAC_VLAN_REMOVE); 1533 } 1534 1535 static int 1536 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1537 { 1538 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1539 struct hns3_mac_vlan_tbl_entry_cmd req; 1540 struct hns3_pf *pf = &hns->pf; 1541 struct hns3_cmd_desc desc[3]; 1542 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1543 uint16_t egress_port = 0; 1544 uint8_t vf_id; 1545 int ret; 1546 1547 /* check if mac addr is valid */ 1548 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1549 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1550 mac_addr); 1551 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1552 mac_str); 1553 return -EINVAL; 1554 } 1555 1556 memset(&req, 0, sizeof(req)); 1557 1558 /* 1559 * In current version VF is not supported when PF is driven by DPDK 1560 * driver, just need to configure parameters for PF vport. 1561 */ 1562 vf_id = HNS3_PF_FUNC_ID; 1563 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1564 HNS3_MAC_EPORT_VFID_S, vf_id); 1565 1566 req.egress_port = rte_cpu_to_le_16(egress_port); 1567 1568 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1569 1570 /* 1571 * Lookup the mac address in the mac_vlan table, and add 1572 * it if the entry is inexistent. Repeated unicast entry 1573 * is not allowed in the mac vlan table. 1574 */ 1575 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false); 1576 if (ret == -ENOENT) { 1577 if (!hns3_is_umv_space_full(hw)) { 1578 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); 1579 if (!ret) 1580 hns3_update_umv_space(hw, false); 1581 return ret; 1582 } 1583 1584 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1585 1586 return -ENOSPC; 1587 } 1588 1589 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1590 1591 /* check if we just hit the duplicate */ 1592 if (ret == 0) { 1593 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1594 return 0; 1595 } 1596 1597 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1598 mac_str); 1599 1600 return ret; 1601 } 1602 1603 static int 1604 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1605 { 1606 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1607 struct rte_ether_addr *addr; 1608 int ret; 1609 int i; 1610 1611 for (i = 0; i < hw->mc_addrs_num; i++) { 1612 addr = &hw->mc_addrs[i]; 1613 /* Check if there are duplicate addresses */ 1614 if (rte_is_same_ether_addr(addr, mac_addr)) { 1615 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1616 addr); 1617 hns3_err(hw, "failed to add mc mac addr, same addrs" 1618 "(%s) is added by the set_mc_mac_addr_list " 1619 "API", mac_str); 1620 return -EINVAL; 1621 } 1622 } 1623 1624 ret = hns3_add_mc_addr(hw, mac_addr); 1625 if (ret) { 1626 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1627 mac_addr); 1628 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 1629 mac_str, ret); 1630 } 1631 return ret; 1632 } 1633 1634 static int 1635 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1636 { 1637 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1638 int ret; 1639 1640 ret = hns3_remove_mc_addr(hw, mac_addr); 1641 if (ret) { 1642 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1643 mac_addr); 1644 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d", 1645 mac_str, ret); 1646 } 1647 return ret; 1648 } 1649 1650 static int 1651 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1652 uint32_t idx, __rte_unused uint32_t pool) 1653 { 1654 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1655 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1656 int ret; 1657 1658 rte_spinlock_lock(&hw->lock); 1659 1660 /* 1661 * In hns3 network engine adding UC and MC mac address with different 1662 * commands with firmware. We need to determine whether the input 1663 * address is a UC or a MC address to call different commands. 1664 * By the way, it is recommended calling the API function named 1665 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 1666 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 1667 * may affect the specifications of UC mac addresses. 1668 */ 1669 if (rte_is_multicast_ether_addr(mac_addr)) 1670 ret = hns3_add_mc_addr_common(hw, mac_addr); 1671 else 1672 ret = hns3_add_uc_addr_common(hw, mac_addr); 1673 1674 if (ret) { 1675 rte_spinlock_unlock(&hw->lock); 1676 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1677 mac_addr); 1678 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 1679 ret); 1680 return ret; 1681 } 1682 1683 if (idx == 0) 1684 hw->mac.default_addr_setted = true; 1685 rte_spinlock_unlock(&hw->lock); 1686 1687 return ret; 1688 } 1689 1690 static int 1691 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1692 { 1693 struct hns3_mac_vlan_tbl_entry_cmd req; 1694 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1695 int ret; 1696 1697 /* check if mac addr is valid */ 1698 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1699 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1700 mac_addr); 1701 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1702 mac_str); 1703 return -EINVAL; 1704 } 1705 1706 memset(&req, 0, sizeof(req)); 1707 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1708 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1709 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1710 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1711 return 0; 1712 else if (ret == 0) 1713 hns3_update_umv_space(hw, true); 1714 1715 return ret; 1716 } 1717 1718 static void 1719 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1720 { 1721 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1722 /* index will be checked by upper level rte interface */ 1723 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1724 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1725 int ret; 1726 1727 rte_spinlock_lock(&hw->lock); 1728 1729 if (rte_is_multicast_ether_addr(mac_addr)) 1730 ret = hns3_remove_mc_addr_common(hw, mac_addr); 1731 else 1732 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1733 rte_spinlock_unlock(&hw->lock); 1734 if (ret) { 1735 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1736 mac_addr); 1737 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, 1738 ret); 1739 } 1740 } 1741 1742 static int 1743 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1744 struct rte_ether_addr *mac_addr) 1745 { 1746 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1747 struct rte_ether_addr *oaddr; 1748 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1749 bool default_addr_setted; 1750 bool rm_succes = false; 1751 int ret, ret_val; 1752 1753 /* 1754 * It has been guaranteed that input parameter named mac_addr is valid 1755 * address in the rte layer of DPDK framework. 1756 */ 1757 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1758 default_addr_setted = hw->mac.default_addr_setted; 1759 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr)) 1760 return 0; 1761 1762 rte_spinlock_lock(&hw->lock); 1763 if (default_addr_setted) { 1764 ret = hns3_remove_uc_addr_common(hw, oaddr); 1765 if (ret) { 1766 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1767 oaddr); 1768 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1769 mac_str, ret); 1770 rm_succes = false; 1771 } else 1772 rm_succes = true; 1773 } 1774 1775 ret = hns3_add_uc_addr_common(hw, mac_addr); 1776 if (ret) { 1777 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1778 mac_addr); 1779 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1780 goto err_add_uc_addr; 1781 } 1782 1783 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1784 if (ret) { 1785 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1786 goto err_pause_addr_cfg; 1787 } 1788 1789 rte_ether_addr_copy(mac_addr, 1790 (struct rte_ether_addr *)hw->mac.mac_addr); 1791 hw->mac.default_addr_setted = true; 1792 rte_spinlock_unlock(&hw->lock); 1793 1794 return 0; 1795 1796 err_pause_addr_cfg: 1797 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1798 if (ret_val) { 1799 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1800 mac_addr); 1801 hns3_warn(hw, 1802 "Failed to roll back to del setted mac addr(%s): %d", 1803 mac_str, ret_val); 1804 } 1805 1806 err_add_uc_addr: 1807 if (rm_succes) { 1808 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1809 if (ret_val) { 1810 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1811 oaddr); 1812 hns3_warn(hw, 1813 "Failed to restore old uc mac addr(%s): %d", 1814 mac_str, ret_val); 1815 hw->mac.default_addr_setted = false; 1816 } 1817 } 1818 rte_spinlock_unlock(&hw->lock); 1819 1820 return ret; 1821 } 1822 1823 static int 1824 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1825 { 1826 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1827 struct hns3_hw *hw = &hns->hw; 1828 struct rte_ether_addr *addr; 1829 int err = 0; 1830 int ret; 1831 int i; 1832 1833 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1834 addr = &hw->data->mac_addrs[i]; 1835 if (rte_is_zero_ether_addr(addr)) 1836 continue; 1837 if (rte_is_multicast_ether_addr(addr)) 1838 ret = del ? hns3_remove_mc_addr(hw, addr) : 1839 hns3_add_mc_addr(hw, addr); 1840 else 1841 ret = del ? hns3_remove_uc_addr_common(hw, addr) : 1842 hns3_add_uc_addr_common(hw, addr); 1843 1844 if (ret) { 1845 err = ret; 1846 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1847 addr); 1848 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 1849 "ret = %d.", del ? "remove" : "restore", 1850 mac_str, i, ret); 1851 } 1852 } 1853 return err; 1854 } 1855 1856 static void 1857 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1858 { 1859 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1860 uint8_t word_num; 1861 uint8_t bit_num; 1862 1863 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1864 word_num = vfid / 32; 1865 bit_num = vfid % 32; 1866 if (clr) 1867 desc[1].data[word_num] &= 1868 rte_cpu_to_le_32(~(1UL << bit_num)); 1869 else 1870 desc[1].data[word_num] |= 1871 rte_cpu_to_le_32(1UL << bit_num); 1872 } else { 1873 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1874 bit_num = vfid % 32; 1875 if (clr) 1876 desc[2].data[word_num] &= 1877 rte_cpu_to_le_32(~(1UL << bit_num)); 1878 else 1879 desc[2].data[word_num] |= 1880 rte_cpu_to_le_32(1UL << bit_num); 1881 } 1882 } 1883 1884 static int 1885 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1886 { 1887 struct hns3_mac_vlan_tbl_entry_cmd req; 1888 struct hns3_cmd_desc desc[3]; 1889 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1890 uint8_t vf_id; 1891 int ret; 1892 1893 /* Check if mac addr is valid */ 1894 if (!rte_is_multicast_ether_addr(mac_addr)) { 1895 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1896 mac_addr); 1897 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1898 mac_str); 1899 return -EINVAL; 1900 } 1901 1902 memset(&req, 0, sizeof(req)); 1903 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1904 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1905 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1906 if (ret) { 1907 /* This mac addr do not exist, add new entry for it */ 1908 memset(desc[0].data, 0, sizeof(desc[0].data)); 1909 memset(desc[1].data, 0, sizeof(desc[0].data)); 1910 memset(desc[2].data, 0, sizeof(desc[0].data)); 1911 } 1912 1913 /* 1914 * In current version VF is not supported when PF is driven by DPDK 1915 * driver, just need to configure parameters for PF vport. 1916 */ 1917 vf_id = HNS3_PF_FUNC_ID; 1918 hns3_update_desc_vfid(desc, vf_id, false); 1919 ret = hns3_add_mac_vlan_tbl(hw, &req, desc); 1920 if (ret) { 1921 if (ret == -ENOSPC) 1922 hns3_err(hw, "mc mac vlan table is full"); 1923 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1924 mac_addr); 1925 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1926 } 1927 1928 return ret; 1929 } 1930 1931 static int 1932 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1933 { 1934 struct hns3_mac_vlan_tbl_entry_cmd req; 1935 struct hns3_cmd_desc desc[3]; 1936 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1937 uint8_t vf_id; 1938 int ret; 1939 1940 /* Check if mac addr is valid */ 1941 if (!rte_is_multicast_ether_addr(mac_addr)) { 1942 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1943 mac_addr); 1944 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1945 mac_str); 1946 return -EINVAL; 1947 } 1948 1949 memset(&req, 0, sizeof(req)); 1950 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1951 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1952 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1953 if (ret == 0) { 1954 /* 1955 * This mac addr exist, remove this handle's VFID for it. 1956 * In current version VF is not supported when PF is driven by 1957 * DPDK driver, just need to configure parameters for PF vport. 1958 */ 1959 vf_id = HNS3_PF_FUNC_ID; 1960 hns3_update_desc_vfid(desc, vf_id, true); 1961 1962 /* All the vfid is zero, so need to delete this entry */ 1963 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1964 } else if (ret == -ENOENT) { 1965 /* This mac addr doesn't exist. */ 1966 return 0; 1967 } 1968 1969 if (ret) { 1970 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1971 mac_addr); 1972 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1973 } 1974 1975 return ret; 1976 } 1977 1978 static int 1979 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1980 struct rte_ether_addr *mc_addr_set, 1981 uint32_t nb_mc_addr) 1982 { 1983 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1984 struct rte_ether_addr *addr; 1985 uint32_t i; 1986 uint32_t j; 1987 1988 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1989 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 1990 "invalid. valid range: 0~%d", 1991 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1992 return -EINVAL; 1993 } 1994 1995 /* Check if input mac addresses are valid */ 1996 for (i = 0; i < nb_mc_addr; i++) { 1997 addr = &mc_addr_set[i]; 1998 if (!rte_is_multicast_ether_addr(addr)) { 1999 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2000 addr); 2001 hns3_err(hw, 2002 "failed to set mc mac addr, addr(%s) invalid.", 2003 mac_str); 2004 return -EINVAL; 2005 } 2006 2007 /* Check if there are duplicate addresses */ 2008 for (j = i + 1; j < nb_mc_addr; j++) { 2009 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 2010 hns3_ether_format_addr(mac_str, 2011 RTE_ETHER_ADDR_FMT_SIZE, 2012 addr); 2013 hns3_err(hw, "failed to set mc mac addr, " 2014 "addrs invalid. two same addrs(%s).", 2015 mac_str); 2016 return -EINVAL; 2017 } 2018 } 2019 2020 /* 2021 * Check if there are duplicate addresses between mac_addrs 2022 * and mc_addr_set 2023 */ 2024 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) { 2025 if (rte_is_same_ether_addr(addr, 2026 &hw->data->mac_addrs[j])) { 2027 hns3_ether_format_addr(mac_str, 2028 RTE_ETHER_ADDR_FMT_SIZE, 2029 addr); 2030 hns3_err(hw, "failed to set mc mac addr, " 2031 "addrs invalid. addrs(%s) has already " 2032 "configured in mac_addr add API", 2033 mac_str); 2034 return -EINVAL; 2035 } 2036 } 2037 } 2038 2039 return 0; 2040 } 2041 2042 static void 2043 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 2044 struct rte_ether_addr *mc_addr_set, 2045 int mc_addr_num, 2046 struct rte_ether_addr *reserved_addr_list, 2047 int *reserved_addr_num, 2048 struct rte_ether_addr *add_addr_list, 2049 int *add_addr_num, 2050 struct rte_ether_addr *rm_addr_list, 2051 int *rm_addr_num) 2052 { 2053 struct rte_ether_addr *addr; 2054 int current_addr_num; 2055 int reserved_num = 0; 2056 int add_num = 0; 2057 int rm_num = 0; 2058 int num; 2059 int i; 2060 int j; 2061 bool same_addr; 2062 2063 /* Calculate the mc mac address list that should be removed */ 2064 current_addr_num = hw->mc_addrs_num; 2065 for (i = 0; i < current_addr_num; i++) { 2066 addr = &hw->mc_addrs[i]; 2067 same_addr = false; 2068 for (j = 0; j < mc_addr_num; j++) { 2069 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 2070 same_addr = true; 2071 break; 2072 } 2073 } 2074 2075 if (!same_addr) { 2076 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 2077 rm_num++; 2078 } else { 2079 rte_ether_addr_copy(addr, 2080 &reserved_addr_list[reserved_num]); 2081 reserved_num++; 2082 } 2083 } 2084 2085 /* Calculate the mc mac address list that should be added */ 2086 for (i = 0; i < mc_addr_num; i++) { 2087 addr = &mc_addr_set[i]; 2088 same_addr = false; 2089 for (j = 0; j < current_addr_num; j++) { 2090 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 2091 same_addr = true; 2092 break; 2093 } 2094 } 2095 2096 if (!same_addr) { 2097 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 2098 add_num++; 2099 } 2100 } 2101 2102 /* Reorder the mc mac address list maintained by driver */ 2103 for (i = 0; i < reserved_num; i++) 2104 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 2105 2106 for (i = 0; i < rm_num; i++) { 2107 num = reserved_num + i; 2108 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 2109 } 2110 2111 *reserved_addr_num = reserved_num; 2112 *add_addr_num = add_num; 2113 *rm_addr_num = rm_num; 2114 } 2115 2116 static int 2117 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 2118 struct rte_ether_addr *mc_addr_set, 2119 uint32_t nb_mc_addr) 2120 { 2121 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2122 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 2123 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 2124 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 2125 struct rte_ether_addr *addr; 2126 int reserved_addr_num; 2127 int add_addr_num; 2128 int rm_addr_num; 2129 int mc_addr_num; 2130 int num; 2131 int ret; 2132 int i; 2133 2134 /* Check if input parameters are valid */ 2135 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 2136 if (ret) 2137 return ret; 2138 2139 rte_spinlock_lock(&hw->lock); 2140 2141 /* 2142 * Calculate the mc mac address lists those should be removed and be 2143 * added, Reorder the mc mac address list maintained by driver. 2144 */ 2145 mc_addr_num = (int)nb_mc_addr; 2146 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 2147 reserved_addr_list, &reserved_addr_num, 2148 add_addr_list, &add_addr_num, 2149 rm_addr_list, &rm_addr_num); 2150 2151 /* Remove mc mac addresses */ 2152 for (i = 0; i < rm_addr_num; i++) { 2153 num = rm_addr_num - i - 1; 2154 addr = &rm_addr_list[num]; 2155 ret = hns3_remove_mc_addr(hw, addr); 2156 if (ret) { 2157 rte_spinlock_unlock(&hw->lock); 2158 return ret; 2159 } 2160 hw->mc_addrs_num--; 2161 } 2162 2163 /* Add mc mac addresses */ 2164 for (i = 0; i < add_addr_num; i++) { 2165 addr = &add_addr_list[i]; 2166 ret = hns3_add_mc_addr(hw, addr); 2167 if (ret) { 2168 rte_spinlock_unlock(&hw->lock); 2169 return ret; 2170 } 2171 2172 num = reserved_addr_num + i; 2173 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 2174 hw->mc_addrs_num++; 2175 } 2176 rte_spinlock_unlock(&hw->lock); 2177 2178 return 0; 2179 } 2180 2181 static int 2182 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 2183 { 2184 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2185 struct hns3_hw *hw = &hns->hw; 2186 struct rte_ether_addr *addr; 2187 int err = 0; 2188 int ret; 2189 int i; 2190 2191 for (i = 0; i < hw->mc_addrs_num; i++) { 2192 addr = &hw->mc_addrs[i]; 2193 if (!rte_is_multicast_ether_addr(addr)) 2194 continue; 2195 if (del) 2196 ret = hns3_remove_mc_addr(hw, addr); 2197 else 2198 ret = hns3_add_mc_addr(hw, addr); 2199 if (ret) { 2200 err = ret; 2201 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2202 addr); 2203 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d", 2204 del ? "Remove" : "Restore", mac_str, ret); 2205 } 2206 } 2207 return err; 2208 } 2209 2210 static int 2211 hns3_check_mq_mode(struct rte_eth_dev *dev) 2212 { 2213 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 2214 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 2215 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2216 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2217 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 2218 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 2219 uint8_t num_tc; 2220 int max_tc = 0; 2221 int i; 2222 2223 if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) || 2224 (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB || 2225 tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) { 2226 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.", 2227 rx_mq_mode, tx_mq_mode); 2228 return -EOPNOTSUPP; 2229 } 2230 2231 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 2232 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 2233 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) { 2234 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 2235 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 2236 dcb_rx_conf->nb_tcs, pf->tc_max); 2237 return -EINVAL; 2238 } 2239 2240 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 2241 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 2242 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 2243 "nb_tcs(%d) != %d or %d in rx direction.", 2244 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 2245 return -EINVAL; 2246 } 2247 2248 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 2249 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 2250 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 2251 return -EINVAL; 2252 } 2253 2254 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 2255 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 2256 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, " 2257 "is not equal to one in tx direction.", 2258 i, dcb_rx_conf->dcb_tc[i]); 2259 return -EINVAL; 2260 } 2261 if (dcb_rx_conf->dcb_tc[i] > max_tc) 2262 max_tc = dcb_rx_conf->dcb_tc[i]; 2263 } 2264 2265 num_tc = max_tc + 1; 2266 if (num_tc > dcb_rx_conf->nb_tcs) { 2267 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 2268 num_tc, dcb_rx_conf->nb_tcs); 2269 return -EINVAL; 2270 } 2271 } 2272 2273 return 0; 2274 } 2275 2276 static int 2277 hns3_check_dcb_cfg(struct rte_eth_dev *dev) 2278 { 2279 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2280 2281 if (!hns3_dev_dcb_supported(hw)) { 2282 hns3_err(hw, "this port does not support dcb configurations."); 2283 return -EOPNOTSUPP; 2284 } 2285 2286 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2287 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2288 return -EOPNOTSUPP; 2289 } 2290 2291 return 0; 2292 } 2293 2294 static int 2295 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, 2296 enum hns3_ring_type queue_type, uint16_t queue_id) 2297 { 2298 struct hns3_cmd_desc desc; 2299 struct hns3_ctrl_vector_chain_cmd *req = 2300 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 2301 enum hns3_opcode_type op; 2302 uint16_t tqp_type_and_id = 0; 2303 uint16_t type; 2304 uint16_t gl; 2305 int ret; 2306 2307 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 2308 hns3_cmd_setup_basic_desc(&desc, op, false); 2309 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M, 2310 HNS3_TQP_INT_ID_L_S); 2311 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M, 2312 HNS3_TQP_INT_ID_H_S); 2313 2314 if (queue_type == HNS3_RING_TYPE_RX) 2315 gl = HNS3_RING_GL_RX; 2316 else 2317 gl = HNS3_RING_GL_TX; 2318 2319 type = queue_type; 2320 2321 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 2322 type); 2323 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 2324 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 2325 gl); 2326 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 2327 req->int_cause_num = 1; 2328 ret = hns3_cmd_send(hw, &desc, 1); 2329 if (ret) { 2330 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.", 2331 en ? "Map" : "Unmap", queue_id, vector_id, ret); 2332 return ret; 2333 } 2334 2335 return 0; 2336 } 2337 2338 static int 2339 hns3_init_ring_with_vector(struct hns3_hw *hw) 2340 { 2341 uint16_t vec; 2342 int ret; 2343 int i; 2344 2345 /* 2346 * In hns3 network engine, vector 0 is always the misc interrupt of this 2347 * function, vector 1~N can be used respectively for the queues of the 2348 * function. Tx and Rx queues with the same number share the interrupt 2349 * vector. In the initialization clearing the all hardware mapping 2350 * relationship configurations between queues and interrupt vectors is 2351 * needed, so some error caused by the residual configurations, such as 2352 * the unexpected Tx interrupt, can be avoid. 2353 */ 2354 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 2355 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 2356 vec = vec - 1; /* the last interrupt is reserved */ 2357 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 2358 for (i = 0; i < hw->intr_tqps_num; i++) { 2359 /* 2360 * Set gap limiter/rate limiter/quanity limiter algorithm 2361 * configuration for interrupt coalesce of queue's interrupt. 2362 */ 2363 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 2364 HNS3_TQP_INTR_GL_DEFAULT); 2365 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 2366 HNS3_TQP_INTR_GL_DEFAULT); 2367 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 2368 /* 2369 * QL(quantity limiter) is not used currently, just set 0 to 2370 * close it. 2371 */ 2372 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 2373 2374 ret = hns3_bind_ring_with_vector(hw, vec, false, 2375 HNS3_RING_TYPE_TX, i); 2376 if (ret) { 2377 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " 2378 "vector: %u, ret=%d", i, vec, ret); 2379 return ret; 2380 } 2381 2382 ret = hns3_bind_ring_with_vector(hw, vec, false, 2383 HNS3_RING_TYPE_RX, i); 2384 if (ret) { 2385 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " 2386 "vector: %u, ret=%d", i, vec, ret); 2387 return ret; 2388 } 2389 } 2390 2391 return 0; 2392 } 2393 2394 static int 2395 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf) 2396 { 2397 struct hns3_adapter *hns = dev->data->dev_private; 2398 struct hns3_hw *hw = &hns->hw; 2399 uint32_t max_rx_pkt_len; 2400 uint16_t mtu; 2401 int ret; 2402 2403 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)) 2404 return 0; 2405 2406 /* 2407 * If jumbo frames are enabled, MTU needs to be refreshed 2408 * according to the maximum RX packet length. 2409 */ 2410 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len; 2411 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN || 2412 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) { 2413 hns3_err(hw, "maximum Rx packet length must be greater than %u " 2414 "and no more than %u when jumbo frame enabled.", 2415 (uint16_t)HNS3_DEFAULT_FRAME_LEN, 2416 (uint16_t)HNS3_MAX_FRAME_LEN); 2417 return -EINVAL; 2418 } 2419 2420 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len); 2421 ret = hns3_dev_mtu_set(dev, mtu); 2422 if (ret) 2423 return ret; 2424 dev->data->mtu = mtu; 2425 2426 return 0; 2427 } 2428 2429 static int 2430 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds) 2431 { 2432 int ret; 2433 2434 /* 2435 * Some hardware doesn't support auto-negotiation, but users may not 2436 * configure link_speeds (default 0), which means auto-negotiation. 2437 * In this case, a warning message need to be printed, instead of 2438 * an error. 2439 */ 2440 if (link_speeds == ETH_LINK_SPEED_AUTONEG && 2441 hw->mac.support_autoneg == 0) { 2442 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!"); 2443 return 0; 2444 } 2445 2446 if (link_speeds != ETH_LINK_SPEED_AUTONEG) { 2447 ret = hns3_check_port_speed(hw, link_speeds); 2448 if (ret) 2449 return ret; 2450 } 2451 2452 return 0; 2453 } 2454 2455 static int 2456 hns3_check_dev_conf(struct rte_eth_dev *dev) 2457 { 2458 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2459 struct rte_eth_conf *conf = &dev->data->dev_conf; 2460 int ret; 2461 2462 ret = hns3_check_mq_mode(dev); 2463 if (ret) 2464 return ret; 2465 2466 return hns3_check_link_speed(hw, conf->link_speeds); 2467 } 2468 2469 static int 2470 hns3_dev_configure(struct rte_eth_dev *dev) 2471 { 2472 struct hns3_adapter *hns = dev->data->dev_private; 2473 struct rte_eth_conf *conf = &dev->data->dev_conf; 2474 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2475 struct hns3_hw *hw = &hns->hw; 2476 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2477 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2478 struct rte_eth_rss_conf rss_conf; 2479 bool gro_en; 2480 int ret; 2481 2482 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 2483 2484 /* 2485 * Some versions of hardware network engine does not support 2486 * individually enable/disable/reset the Tx or Rx queue. These devices 2487 * must enable/disable/reset Tx and Rx queues at the same time. When the 2488 * numbers of Tx queues allocated by upper applications are not equal to 2489 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 2490 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 2491 * work as usual. But these fake queues are imperceptible, and can not 2492 * be used by upper applications. 2493 */ 2494 if (!hns3_dev_indep_txrx_supported(hw)) { 2495 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2496 if (ret) { 2497 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", 2498 ret); 2499 return ret; 2500 } 2501 } 2502 2503 hw->adapter_state = HNS3_NIC_CONFIGURING; 2504 ret = hns3_check_dev_conf(dev); 2505 if (ret) 2506 goto cfg_err; 2507 2508 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2509 ret = hns3_check_dcb_cfg(dev); 2510 if (ret) 2511 goto cfg_err; 2512 } 2513 2514 /* When RSS is not configured, redirect the packet queue 0 */ 2515 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2516 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2517 rss_conf = conf->rx_adv_conf.rss_conf; 2518 hw->rss_dis_flag = false; 2519 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2520 if (ret) 2521 goto cfg_err; 2522 } 2523 2524 ret = hns3_refresh_mtu(dev, conf); 2525 if (ret) 2526 goto cfg_err; 2527 2528 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf); 2529 if (ret) 2530 goto cfg_err; 2531 2532 ret = hns3_dev_configure_vlan(dev); 2533 if (ret) 2534 goto cfg_err; 2535 2536 /* config hardware GRO */ 2537 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 2538 ret = hns3_config_gro(hw, gro_en); 2539 if (ret) 2540 goto cfg_err; 2541 2542 hns3_init_rx_ptype_tble(dev); 2543 hw->adapter_state = HNS3_NIC_CONFIGURED; 2544 2545 return 0; 2546 2547 cfg_err: 2548 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2549 hw->adapter_state = HNS3_NIC_INITIALIZED; 2550 2551 return ret; 2552 } 2553 2554 static int 2555 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2556 { 2557 struct hns3_config_max_frm_size_cmd *req; 2558 struct hns3_cmd_desc desc; 2559 2560 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2561 2562 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2563 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2564 req->min_frm_size = RTE_ETHER_MIN_LEN; 2565 2566 return hns3_cmd_send(hw, &desc, 1); 2567 } 2568 2569 static int 2570 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2571 { 2572 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2573 uint16_t original_mps = hns->pf.mps; 2574 int err; 2575 int ret; 2576 2577 ret = hns3_set_mac_mtu(hw, mps); 2578 if (ret) { 2579 hns3_err(hw, "failed to set mtu, ret = %d", ret); 2580 return ret; 2581 } 2582 2583 hns->pf.mps = mps; 2584 ret = hns3_buffer_alloc(hw); 2585 if (ret) { 2586 hns3_err(hw, "failed to allocate buffer, ret = %d", ret); 2587 goto rollback; 2588 } 2589 2590 return 0; 2591 2592 rollback: 2593 err = hns3_set_mac_mtu(hw, original_mps); 2594 if (err) { 2595 hns3_err(hw, "fail to rollback MTU, err = %d", err); 2596 return ret; 2597 } 2598 hns->pf.mps = original_mps; 2599 2600 return ret; 2601 } 2602 2603 static int 2604 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2605 { 2606 struct hns3_adapter *hns = dev->data->dev_private; 2607 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2608 struct hns3_hw *hw = &hns->hw; 2609 bool is_jumbo_frame; 2610 int ret; 2611 2612 if (dev->data->dev_started) { 2613 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2614 "before configuration", dev->data->port_id); 2615 return -EBUSY; 2616 } 2617 2618 rte_spinlock_lock(&hw->lock); 2619 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false; 2620 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2621 2622 /* 2623 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2624 * assign to "uint16_t" type variable. 2625 */ 2626 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2627 if (ret) { 2628 rte_spinlock_unlock(&hw->lock); 2629 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2630 dev->data->port_id, mtu, ret); 2631 return ret; 2632 } 2633 2634 if (is_jumbo_frame) 2635 dev->data->dev_conf.rxmode.offloads |= 2636 DEV_RX_OFFLOAD_JUMBO_FRAME; 2637 else 2638 dev->data->dev_conf.rxmode.offloads &= 2639 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2640 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2641 rte_spinlock_unlock(&hw->lock); 2642 2643 return 0; 2644 } 2645 2646 static uint32_t 2647 hns3_get_copper_port_speed_capa(uint32_t supported_speed) 2648 { 2649 uint32_t speed_capa = 0; 2650 2651 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT) 2652 speed_capa |= ETH_LINK_SPEED_10M_HD; 2653 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT) 2654 speed_capa |= ETH_LINK_SPEED_10M; 2655 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT) 2656 speed_capa |= ETH_LINK_SPEED_100M_HD; 2657 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT) 2658 speed_capa |= ETH_LINK_SPEED_100M; 2659 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT) 2660 speed_capa |= ETH_LINK_SPEED_1G; 2661 2662 return speed_capa; 2663 } 2664 2665 static uint32_t 2666 hns3_get_firber_port_speed_capa(uint32_t supported_speed) 2667 { 2668 uint32_t speed_capa = 0; 2669 2670 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT) 2671 speed_capa |= ETH_LINK_SPEED_1G; 2672 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT) 2673 speed_capa |= ETH_LINK_SPEED_10G; 2674 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT) 2675 speed_capa |= ETH_LINK_SPEED_25G; 2676 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT) 2677 speed_capa |= ETH_LINK_SPEED_40G; 2678 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT) 2679 speed_capa |= ETH_LINK_SPEED_50G; 2680 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT) 2681 speed_capa |= ETH_LINK_SPEED_100G; 2682 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT) 2683 speed_capa |= ETH_LINK_SPEED_200G; 2684 2685 return speed_capa; 2686 } 2687 2688 static uint32_t 2689 hns3_get_speed_capa(struct hns3_hw *hw) 2690 { 2691 struct hns3_mac *mac = &hw->mac; 2692 uint32_t speed_capa; 2693 2694 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 2695 speed_capa = 2696 hns3_get_copper_port_speed_capa(mac->supported_speed); 2697 else 2698 speed_capa = 2699 hns3_get_firber_port_speed_capa(mac->supported_speed); 2700 2701 if (mac->support_autoneg == 0) 2702 speed_capa |= ETH_LINK_SPEED_FIXED; 2703 2704 return speed_capa; 2705 } 2706 2707 int 2708 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2709 { 2710 struct hns3_adapter *hns = eth_dev->data->dev_private; 2711 struct hns3_hw *hw = &hns->hw; 2712 uint16_t queue_num = hw->tqps_num; 2713 2714 /* 2715 * In interrupt mode, 'max_rx_queues' is set based on the number of 2716 * MSI-X interrupt resources of the hardware. 2717 */ 2718 if (hw->data->dev_conf.intr_conf.rxq == 1) 2719 queue_num = hw->intr_tqps_num; 2720 2721 info->max_rx_queues = queue_num; 2722 info->max_tx_queues = hw->tqps_num; 2723 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2724 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 2725 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2726 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2727 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 2728 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2729 DEV_RX_OFFLOAD_TCP_CKSUM | 2730 DEV_RX_OFFLOAD_UDP_CKSUM | 2731 DEV_RX_OFFLOAD_SCTP_CKSUM | 2732 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2733 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2734 DEV_RX_OFFLOAD_KEEP_CRC | 2735 DEV_RX_OFFLOAD_SCATTER | 2736 DEV_RX_OFFLOAD_VLAN_STRIP | 2737 DEV_RX_OFFLOAD_VLAN_FILTER | 2738 DEV_RX_OFFLOAD_JUMBO_FRAME | 2739 DEV_RX_OFFLOAD_RSS_HASH | 2740 DEV_RX_OFFLOAD_TCP_LRO); 2741 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2742 DEV_TX_OFFLOAD_IPV4_CKSUM | 2743 DEV_TX_OFFLOAD_TCP_CKSUM | 2744 DEV_TX_OFFLOAD_UDP_CKSUM | 2745 DEV_TX_OFFLOAD_SCTP_CKSUM | 2746 DEV_TX_OFFLOAD_MULTI_SEGS | 2747 DEV_TX_OFFLOAD_TCP_TSO | 2748 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2749 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2750 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2751 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 2752 hns3_txvlan_cap_get(hw)); 2753 2754 if (hns3_dev_outer_udp_cksum_supported(hw)) 2755 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 2756 2757 if (hns3_dev_indep_txrx_supported(hw)) 2758 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 2759 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 2760 2761 if (hns3_dev_ptp_supported(hw)) 2762 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 2763 2764 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2765 .nb_max = HNS3_MAX_RING_DESC, 2766 .nb_min = HNS3_MIN_RING_DESC, 2767 .nb_align = HNS3_ALIGN_RING_DESC, 2768 }; 2769 2770 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2771 .nb_max = HNS3_MAX_RING_DESC, 2772 .nb_min = HNS3_MIN_RING_DESC, 2773 .nb_align = HNS3_ALIGN_RING_DESC, 2774 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 2775 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 2776 }; 2777 2778 info->speed_capa = hns3_get_speed_capa(hw); 2779 info->default_rxconf = (struct rte_eth_rxconf) { 2780 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 2781 /* 2782 * If there are no available Rx buffer descriptors, incoming 2783 * packets are always dropped by hardware based on hns3 network 2784 * engine. 2785 */ 2786 .rx_drop_en = 1, 2787 .offloads = 0, 2788 }; 2789 info->default_txconf = (struct rte_eth_txconf) { 2790 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 2791 .offloads = 0, 2792 }; 2793 2794 info->reta_size = hw->rss_ind_tbl_size; 2795 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2796 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2797 2798 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2799 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2800 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2801 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2802 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2803 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2804 2805 return 0; 2806 } 2807 2808 static int 2809 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2810 size_t fw_size) 2811 { 2812 struct hns3_adapter *hns = eth_dev->data->dev_private; 2813 struct hns3_hw *hw = &hns->hw; 2814 uint32_t version = hw->fw_version; 2815 int ret; 2816 2817 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2818 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2819 HNS3_FW_VERSION_BYTE3_S), 2820 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2821 HNS3_FW_VERSION_BYTE2_S), 2822 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2823 HNS3_FW_VERSION_BYTE1_S), 2824 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2825 HNS3_FW_VERSION_BYTE0_S)); 2826 if (ret < 0) 2827 return -EINVAL; 2828 2829 ret += 1; /* add the size of '\0' */ 2830 if (fw_size < (size_t)ret) 2831 return ret; 2832 else 2833 return 0; 2834 } 2835 2836 static int 2837 hns3_update_port_link_info(struct rte_eth_dev *eth_dev) 2838 { 2839 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2840 int ret; 2841 2842 (void)hns3_update_link_status(hw); 2843 2844 ret = hns3_update_link_info(eth_dev); 2845 if (ret) 2846 hw->mac.link_status = ETH_LINK_DOWN; 2847 2848 return ret; 2849 } 2850 2851 static void 2852 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev, 2853 struct rte_eth_link *new_link) 2854 { 2855 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2856 struct hns3_mac *mac = &hw->mac; 2857 2858 switch (mac->link_speed) { 2859 case ETH_SPEED_NUM_10M: 2860 case ETH_SPEED_NUM_100M: 2861 case ETH_SPEED_NUM_1G: 2862 case ETH_SPEED_NUM_10G: 2863 case ETH_SPEED_NUM_25G: 2864 case ETH_SPEED_NUM_40G: 2865 case ETH_SPEED_NUM_50G: 2866 case ETH_SPEED_NUM_100G: 2867 case ETH_SPEED_NUM_200G: 2868 if (mac->link_status) 2869 new_link->link_speed = mac->link_speed; 2870 break; 2871 default: 2872 if (mac->link_status) 2873 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN; 2874 break; 2875 } 2876 2877 if (!mac->link_status) 2878 new_link->link_speed = ETH_SPEED_NUM_NONE; 2879 2880 new_link->link_duplex = mac->link_duplex; 2881 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2882 new_link->link_autoneg = mac->link_autoneg; 2883 } 2884 2885 static int 2886 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) 2887 { 2888 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */ 2889 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */ 2890 2891 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2892 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES; 2893 struct hns3_mac *mac = &hw->mac; 2894 struct rte_eth_link new_link; 2895 int ret; 2896 2897 /* When port is stopped, report link down. */ 2898 if (eth_dev->data->dev_started == 0) { 2899 new_link.link_autoneg = mac->link_autoneg; 2900 new_link.link_duplex = mac->link_duplex; 2901 new_link.link_speed = ETH_SPEED_NUM_NONE; 2902 new_link.link_status = ETH_LINK_DOWN; 2903 goto out; 2904 } 2905 2906 do { 2907 ret = hns3_update_port_link_info(eth_dev); 2908 if (ret) { 2909 hns3_err(hw, "failed to get port link info, ret = %d.", 2910 ret); 2911 break; 2912 } 2913 2914 if (!wait_to_complete || mac->link_status == ETH_LINK_UP) 2915 break; 2916 2917 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL); 2918 } while (retry_cnt--); 2919 2920 memset(&new_link, 0, sizeof(new_link)); 2921 hns3_setup_linkstatus(eth_dev, &new_link); 2922 2923 out: 2924 return rte_eth_linkstatus_set(eth_dev, &new_link); 2925 } 2926 2927 static int 2928 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2929 { 2930 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2931 struct hns3_pf *pf = &hns->pf; 2932 2933 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2934 return -EINVAL; 2935 2936 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2937 2938 return 0; 2939 } 2940 2941 static int 2942 hns3_query_function_status(struct hns3_hw *hw) 2943 { 2944 #define HNS3_QUERY_MAX_CNT 10 2945 #define HNS3_QUERY_SLEEP_MSCOEND 1 2946 struct hns3_func_status_cmd *req; 2947 struct hns3_cmd_desc desc; 2948 int timeout = 0; 2949 int ret; 2950 2951 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2952 req = (struct hns3_func_status_cmd *)desc.data; 2953 2954 do { 2955 ret = hns3_cmd_send(hw, &desc, 1); 2956 if (ret) { 2957 PMD_INIT_LOG(ERR, "query function status failed %d", 2958 ret); 2959 return ret; 2960 } 2961 2962 /* Check pf reset is done */ 2963 if (req->pf_state) 2964 break; 2965 2966 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2967 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2968 2969 return hns3_parse_func_status(hw, req); 2970 } 2971 2972 static int 2973 hns3_get_pf_max_tqp_num(struct hns3_hw *hw) 2974 { 2975 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2976 struct hns3_pf *pf = &hns->pf; 2977 2978 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) { 2979 /* 2980 * The total_tqps_num obtained from firmware is maximum tqp 2981 * numbers of this port, which should be used for PF and VFs. 2982 * There is no need for pf to have so many tqp numbers in 2983 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2984 * coming from config file, is assigned to maximum queue number 2985 * for the PF of this port by user. So users can modify the 2986 * maximum queue number of PF according to their own application 2987 * scenarios, which is more flexible to use. In addition, many 2988 * memories can be saved due to allocating queue statistics 2989 * room according to the actual number of queues required. The 2990 * maximum queue number of PF for network engine with 2991 * revision_id greater than 0x30 is assigned by config file. 2992 */ 2993 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) { 2994 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) " 2995 "must be greater than 0.", 2996 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF); 2997 return -EINVAL; 2998 } 2999 3000 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 3001 hw->total_tqps_num); 3002 } else { 3003 /* 3004 * Due to the limitation on the number of PF interrupts 3005 * available, the maximum queue number assigned to PF on 3006 * the network engine with revision_id 0x21 is 64. 3007 */ 3008 hw->tqps_num = RTE_MIN(hw->total_tqps_num, 3009 HNS3_MAX_TQP_NUM_HIP08_PF); 3010 } 3011 3012 return 0; 3013 } 3014 3015 static int 3016 hns3_query_pf_resource(struct hns3_hw *hw) 3017 { 3018 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3019 struct hns3_pf *pf = &hns->pf; 3020 struct hns3_pf_res_cmd *req; 3021 struct hns3_cmd_desc desc; 3022 int ret; 3023 3024 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 3025 ret = hns3_cmd_send(hw, &desc, 1); 3026 if (ret) { 3027 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 3028 return ret; 3029 } 3030 3031 req = (struct hns3_pf_res_cmd *)desc.data; 3032 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) + 3033 rte_le_to_cpu_16(req->ext_tqp_num); 3034 ret = hns3_get_pf_max_tqp_num(hw); 3035 if (ret) 3036 return ret; 3037 3038 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 3039 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 3040 3041 if (req->tx_buf_size) 3042 pf->tx_buf_size = 3043 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 3044 else 3045 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 3046 3047 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 3048 3049 if (req->dv_buf_size) 3050 pf->dv_buf_size = 3051 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 3052 else 3053 pf->dv_buf_size = HNS3_DEFAULT_DV; 3054 3055 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 3056 3057 hw->num_msi = 3058 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 3059 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 3060 3061 return 0; 3062 } 3063 3064 static void 3065 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 3066 { 3067 struct hns3_cfg_param_cmd *req; 3068 uint64_t mac_addr_tmp_high; 3069 uint8_t ext_rss_size_max; 3070 uint64_t mac_addr_tmp; 3071 uint32_t i; 3072 3073 req = (struct hns3_cfg_param_cmd *)desc[0].data; 3074 3075 /* get the configuration */ 3076 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3077 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 3078 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3079 HNS3_CFG_TQP_DESC_N_M, 3080 HNS3_CFG_TQP_DESC_N_S); 3081 3082 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3083 HNS3_CFG_PHY_ADDR_M, 3084 HNS3_CFG_PHY_ADDR_S); 3085 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3086 HNS3_CFG_MEDIA_TP_M, 3087 HNS3_CFG_MEDIA_TP_S); 3088 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3089 HNS3_CFG_RX_BUF_LEN_M, 3090 HNS3_CFG_RX_BUF_LEN_S); 3091 /* get mac address */ 3092 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 3093 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3094 HNS3_CFG_MAC_ADDR_H_M, 3095 HNS3_CFG_MAC_ADDR_H_S); 3096 3097 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 3098 3099 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3100 HNS3_CFG_DEFAULT_SPEED_M, 3101 HNS3_CFG_DEFAULT_SPEED_S); 3102 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3103 HNS3_CFG_RSS_SIZE_M, 3104 HNS3_CFG_RSS_SIZE_S); 3105 3106 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3107 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 3108 3109 req = (struct hns3_cfg_param_cmd *)desc[1].data; 3110 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 3111 3112 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3113 HNS3_CFG_SPEED_ABILITY_M, 3114 HNS3_CFG_SPEED_ABILITY_S); 3115 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3116 HNS3_CFG_UMV_TBL_SPACE_M, 3117 HNS3_CFG_UMV_TBL_SPACE_S); 3118 if (!cfg->umv_space) 3119 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 3120 3121 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]), 3122 HNS3_CFG_EXT_RSS_SIZE_M, 3123 HNS3_CFG_EXT_RSS_SIZE_S); 3124 3125 /* 3126 * Field ext_rss_size_max obtained from firmware will be more flexible 3127 * for future changes and expansions, which is an exponent of 2, instead 3128 * of reading out directly. If this field is not zero, hns3 PF PMD 3129 * driver uses it as rss_size_max under one TC. Device, whose revision 3130 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the 3131 * maximum number of queues supported under a TC through this field. 3132 */ 3133 if (ext_rss_size_max) 3134 cfg->rss_size_max = 1U << ext_rss_size_max; 3135 } 3136 3137 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 3138 * @hw: pointer to struct hns3_hw 3139 * @hcfg: the config structure to be getted 3140 */ 3141 static int 3142 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 3143 { 3144 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 3145 struct hns3_cfg_param_cmd *req; 3146 uint32_t offset; 3147 uint32_t i; 3148 int ret; 3149 3150 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 3151 offset = 0; 3152 req = (struct hns3_cfg_param_cmd *)desc[i].data; 3153 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 3154 true); 3155 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 3156 i * HNS3_CFG_RD_LEN_BYTES); 3157 /* Len should be divided by 4 when send to hardware */ 3158 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 3159 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 3160 req->offset = rte_cpu_to_le_32(offset); 3161 } 3162 3163 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 3164 if (ret) { 3165 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 3166 return ret; 3167 } 3168 3169 hns3_parse_cfg(hcfg, desc); 3170 3171 return 0; 3172 } 3173 3174 static int 3175 hns3_parse_speed(int speed_cmd, uint32_t *speed) 3176 { 3177 switch (speed_cmd) { 3178 case HNS3_CFG_SPEED_10M: 3179 *speed = ETH_SPEED_NUM_10M; 3180 break; 3181 case HNS3_CFG_SPEED_100M: 3182 *speed = ETH_SPEED_NUM_100M; 3183 break; 3184 case HNS3_CFG_SPEED_1G: 3185 *speed = ETH_SPEED_NUM_1G; 3186 break; 3187 case HNS3_CFG_SPEED_10G: 3188 *speed = ETH_SPEED_NUM_10G; 3189 break; 3190 case HNS3_CFG_SPEED_25G: 3191 *speed = ETH_SPEED_NUM_25G; 3192 break; 3193 case HNS3_CFG_SPEED_40G: 3194 *speed = ETH_SPEED_NUM_40G; 3195 break; 3196 case HNS3_CFG_SPEED_50G: 3197 *speed = ETH_SPEED_NUM_50G; 3198 break; 3199 case HNS3_CFG_SPEED_100G: 3200 *speed = ETH_SPEED_NUM_100G; 3201 break; 3202 case HNS3_CFG_SPEED_200G: 3203 *speed = ETH_SPEED_NUM_200G; 3204 break; 3205 default: 3206 return -EINVAL; 3207 } 3208 3209 return 0; 3210 } 3211 3212 static void 3213 hns3_set_default_dev_specifications(struct hns3_hw *hw) 3214 { 3215 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 3216 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 3217 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 3218 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 3219 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 3220 } 3221 3222 static void 3223 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 3224 { 3225 struct hns3_dev_specs_0_cmd *req0; 3226 3227 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 3228 3229 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 3230 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 3231 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 3232 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 3233 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 3234 } 3235 3236 static int 3237 hns3_check_dev_specifications(struct hns3_hw *hw) 3238 { 3239 if (hw->rss_ind_tbl_size == 0 || 3240 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 3241 hns3_err(hw, "the size of hash lookup table configured (%u)" 3242 " exceeds the maximum(%u)", hw->rss_ind_tbl_size, 3243 HNS3_RSS_IND_TBL_SIZE_MAX); 3244 return -EINVAL; 3245 } 3246 3247 return 0; 3248 } 3249 3250 static int 3251 hns3_query_dev_specifications(struct hns3_hw *hw) 3252 { 3253 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 3254 int ret; 3255 int i; 3256 3257 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3258 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 3259 true); 3260 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3261 } 3262 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 3263 3264 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 3265 if (ret) 3266 return ret; 3267 3268 hns3_parse_dev_specifications(hw, desc); 3269 3270 return hns3_check_dev_specifications(hw); 3271 } 3272 3273 static int 3274 hns3_get_capability(struct hns3_hw *hw) 3275 { 3276 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3277 struct rte_pci_device *pci_dev; 3278 struct hns3_pf *pf = &hns->pf; 3279 struct rte_eth_dev *eth_dev; 3280 uint16_t device_id; 3281 uint8_t revision; 3282 int ret; 3283 3284 eth_dev = &rte_eth_devices[hw->data->port_id]; 3285 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3286 device_id = pci_dev->id.device_id; 3287 3288 if (device_id == HNS3_DEV_ID_25GE_RDMA || 3289 device_id == HNS3_DEV_ID_50GE_RDMA || 3290 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 3291 device_id == HNS3_DEV_ID_200G_RDMA) 3292 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 3293 3294 /* Get PCI revision id */ 3295 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 3296 HNS3_PCI_REVISION_ID); 3297 if (ret != HNS3_PCI_REVISION_ID_LEN) { 3298 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 3299 ret); 3300 return -EIO; 3301 } 3302 hw->revision = revision; 3303 3304 if (revision < PCI_REVISION_ID_HIP09_A) { 3305 hns3_set_default_dev_specifications(hw); 3306 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 3307 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 3308 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 3309 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; 3310 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 3311 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 3312 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; 3313 hw->rss_info.ipv6_sctp_offload_supported = false; 3314 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE; 3315 return 0; 3316 } 3317 3318 ret = hns3_query_dev_specifications(hw); 3319 if (ret) { 3320 PMD_INIT_LOG(ERR, 3321 "failed to query dev specifications, ret = %d", 3322 ret); 3323 return ret; 3324 } 3325 3326 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 3327 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 3328 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 3329 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; 3330 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 3331 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 3332 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; 3333 hw->rss_info.ipv6_sctp_offload_supported = true; 3334 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE; 3335 3336 return 0; 3337 } 3338 3339 static int 3340 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type) 3341 { 3342 int ret; 3343 3344 switch (media_type) { 3345 case HNS3_MEDIA_TYPE_COPPER: 3346 if (!hns3_dev_copper_supported(hw)) { 3347 PMD_INIT_LOG(ERR, 3348 "Media type is copper, not supported."); 3349 ret = -EOPNOTSUPP; 3350 } else { 3351 ret = 0; 3352 } 3353 break; 3354 case HNS3_MEDIA_TYPE_FIBER: 3355 ret = 0; 3356 break; 3357 case HNS3_MEDIA_TYPE_BACKPLANE: 3358 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported."); 3359 ret = -EOPNOTSUPP; 3360 break; 3361 default: 3362 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type); 3363 ret = -EINVAL; 3364 break; 3365 } 3366 3367 return ret; 3368 } 3369 3370 static int 3371 hns3_get_board_configuration(struct hns3_hw *hw) 3372 { 3373 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3374 struct hns3_pf *pf = &hns->pf; 3375 struct hns3_cfg cfg; 3376 int ret; 3377 3378 ret = hns3_get_board_cfg(hw, &cfg); 3379 if (ret) { 3380 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 3381 return ret; 3382 } 3383 3384 ret = hns3_check_media_type(hw, cfg.media_type); 3385 if (ret) 3386 return ret; 3387 3388 hw->mac.media_type = cfg.media_type; 3389 hw->rss_size_max = cfg.rss_size_max; 3390 hw->rss_dis_flag = false; 3391 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 3392 hw->mac.phy_addr = cfg.phy_addr; 3393 hw->mac.default_addr_setted = false; 3394 hw->num_tx_desc = cfg.tqp_desc_num; 3395 hw->num_rx_desc = cfg.tqp_desc_num; 3396 hw->dcb_info.num_pg = 1; 3397 hw->dcb_info.hw_pfc_map = 0; 3398 3399 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 3400 if (ret) { 3401 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d", 3402 cfg.default_speed, ret); 3403 return ret; 3404 } 3405 3406 pf->tc_max = cfg.tc_num; 3407 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 3408 PMD_INIT_LOG(WARNING, 3409 "Get TC num(%u) from flash, set TC num to 1", 3410 pf->tc_max); 3411 pf->tc_max = 1; 3412 } 3413 3414 /* Dev does not support DCB */ 3415 if (!hns3_dev_dcb_supported(hw)) { 3416 pf->tc_max = 1; 3417 pf->pfc_max = 0; 3418 } else 3419 pf->pfc_max = pf->tc_max; 3420 3421 hw->dcb_info.num_tc = 1; 3422 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 3423 hw->tqps_num / hw->dcb_info.num_tc); 3424 hns3_set_bit(hw->hw_tc_map, 0, 1); 3425 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 3426 3427 pf->wanted_umv_size = cfg.umv_space; 3428 3429 return ret; 3430 } 3431 3432 static int 3433 hns3_get_configuration(struct hns3_hw *hw) 3434 { 3435 int ret; 3436 3437 ret = hns3_query_function_status(hw); 3438 if (ret) { 3439 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 3440 return ret; 3441 } 3442 3443 /* Get device capability */ 3444 ret = hns3_get_capability(hw); 3445 if (ret) { 3446 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 3447 return ret; 3448 } 3449 3450 /* Get pf resource */ 3451 ret = hns3_query_pf_resource(hw); 3452 if (ret) { 3453 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 3454 return ret; 3455 } 3456 3457 ret = hns3_get_board_configuration(hw); 3458 if (ret) { 3459 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret); 3460 return ret; 3461 } 3462 3463 ret = hns3_query_dev_fec_info(hw); 3464 if (ret) 3465 PMD_INIT_LOG(ERR, 3466 "failed to query FEC information, ret = %d", ret); 3467 3468 return ret; 3469 } 3470 3471 static int 3472 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 3473 uint16_t tqp_vid, bool is_pf) 3474 { 3475 struct hns3_tqp_map_cmd *req; 3476 struct hns3_cmd_desc desc; 3477 int ret; 3478 3479 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 3480 3481 req = (struct hns3_tqp_map_cmd *)desc.data; 3482 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 3483 req->tqp_vf = func_id; 3484 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 3485 if (!is_pf) 3486 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 3487 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 3488 3489 ret = hns3_cmd_send(hw, &desc, 1); 3490 if (ret) 3491 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 3492 3493 return ret; 3494 } 3495 3496 static int 3497 hns3_map_tqp(struct hns3_hw *hw) 3498 { 3499 int ret; 3500 int i; 3501 3502 /* 3503 * In current version, VF is not supported when PF is driven by DPDK 3504 * driver, so we assign total tqps_num tqps allocated to this port 3505 * to PF. 3506 */ 3507 for (i = 0; i < hw->total_tqps_num; i++) { 3508 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true); 3509 if (ret) 3510 return ret; 3511 } 3512 3513 return 0; 3514 } 3515 3516 static int 3517 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 3518 { 3519 struct hns3_config_mac_speed_dup_cmd *req; 3520 struct hns3_cmd_desc desc; 3521 int ret; 3522 3523 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 3524 3525 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 3526 3527 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 3528 3529 switch (speed) { 3530 case ETH_SPEED_NUM_10M: 3531 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3532 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 3533 break; 3534 case ETH_SPEED_NUM_100M: 3535 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3536 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 3537 break; 3538 case ETH_SPEED_NUM_1G: 3539 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3540 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 3541 break; 3542 case ETH_SPEED_NUM_10G: 3543 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3544 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 3545 break; 3546 case ETH_SPEED_NUM_25G: 3547 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3548 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 3549 break; 3550 case ETH_SPEED_NUM_40G: 3551 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3552 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 3553 break; 3554 case ETH_SPEED_NUM_50G: 3555 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3556 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 3557 break; 3558 case ETH_SPEED_NUM_100G: 3559 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3560 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 3561 break; 3562 case ETH_SPEED_NUM_200G: 3563 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3564 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 3565 break; 3566 default: 3567 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 3568 return -EINVAL; 3569 } 3570 3571 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3572 3573 ret = hns3_cmd_send(hw, &desc, 1); 3574 if (ret) 3575 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3576 3577 return ret; 3578 } 3579 3580 static int 3581 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3582 { 3583 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3584 struct hns3_pf *pf = &hns->pf; 3585 struct hns3_priv_buf *priv; 3586 uint32_t i, total_size; 3587 3588 total_size = pf->pkt_buf_size; 3589 3590 /* alloc tx buffer for all enabled tc */ 3591 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3592 priv = &buf_alloc->priv_buf[i]; 3593 3594 if (hw->hw_tc_map & BIT(i)) { 3595 if (total_size < pf->tx_buf_size) 3596 return -ENOMEM; 3597 3598 priv->tx_buf_size = pf->tx_buf_size; 3599 } else 3600 priv->tx_buf_size = 0; 3601 3602 total_size -= priv->tx_buf_size; 3603 } 3604 3605 return 0; 3606 } 3607 3608 static int 3609 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3610 { 3611 /* TX buffer size is unit by 128 byte */ 3612 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3613 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3614 struct hns3_tx_buff_alloc_cmd *req; 3615 struct hns3_cmd_desc desc; 3616 uint32_t buf_size; 3617 uint32_t i; 3618 int ret; 3619 3620 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3621 3622 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3623 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3624 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3625 3626 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3627 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3628 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3629 } 3630 3631 ret = hns3_cmd_send(hw, &desc, 1); 3632 if (ret) 3633 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3634 3635 return ret; 3636 } 3637 3638 static int 3639 hns3_get_tc_num(struct hns3_hw *hw) 3640 { 3641 int cnt = 0; 3642 uint8_t i; 3643 3644 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3645 if (hw->hw_tc_map & BIT(i)) 3646 cnt++; 3647 return cnt; 3648 } 3649 3650 static uint32_t 3651 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3652 { 3653 struct hns3_priv_buf *priv; 3654 uint32_t rx_priv = 0; 3655 int i; 3656 3657 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3658 priv = &buf_alloc->priv_buf[i]; 3659 if (priv->enable) 3660 rx_priv += priv->buf_size; 3661 } 3662 return rx_priv; 3663 } 3664 3665 static uint32_t 3666 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3667 { 3668 uint32_t total_tx_size = 0; 3669 uint32_t i; 3670 3671 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3672 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3673 3674 return total_tx_size; 3675 } 3676 3677 /* Get the number of pfc enabled TCs, which have private buffer */ 3678 static int 3679 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3680 { 3681 struct hns3_priv_buf *priv; 3682 int cnt = 0; 3683 uint8_t i; 3684 3685 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3686 priv = &buf_alloc->priv_buf[i]; 3687 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3688 cnt++; 3689 } 3690 3691 return cnt; 3692 } 3693 3694 /* Get the number of pfc disabled TCs, which have private buffer */ 3695 static int 3696 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3697 struct hns3_pkt_buf_alloc *buf_alloc) 3698 { 3699 struct hns3_priv_buf *priv; 3700 int cnt = 0; 3701 uint8_t i; 3702 3703 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3704 priv = &buf_alloc->priv_buf[i]; 3705 if (hw->hw_tc_map & BIT(i) && 3706 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3707 cnt++; 3708 } 3709 3710 return cnt; 3711 } 3712 3713 static bool 3714 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3715 uint32_t rx_all) 3716 { 3717 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3718 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3719 struct hns3_pf *pf = &hns->pf; 3720 uint32_t shared_buf, aligned_mps; 3721 uint32_t rx_priv; 3722 uint8_t tc_num; 3723 uint8_t i; 3724 3725 tc_num = hns3_get_tc_num(hw); 3726 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3727 3728 if (hns3_dev_dcb_supported(hw)) 3729 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3730 pf->dv_buf_size; 3731 else 3732 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3733 + pf->dv_buf_size; 3734 3735 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3736 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3737 HNS3_BUF_SIZE_UNIT); 3738 3739 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3740 if (rx_all < rx_priv + shared_std) 3741 return false; 3742 3743 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3744 buf_alloc->s_buf.buf_size = shared_buf; 3745 if (hns3_dev_dcb_supported(hw)) { 3746 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3747 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3748 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3749 HNS3_BUF_SIZE_UNIT); 3750 } else { 3751 buf_alloc->s_buf.self.high = 3752 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3753 buf_alloc->s_buf.self.low = aligned_mps; 3754 } 3755 3756 if (hns3_dev_dcb_supported(hw)) { 3757 hi_thrd = shared_buf - pf->dv_buf_size; 3758 3759 if (tc_num <= NEED_RESERVE_TC_NUM) 3760 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT / 3761 BUF_MAX_PERCENT; 3762 3763 if (tc_num) 3764 hi_thrd = hi_thrd / tc_num; 3765 3766 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3767 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3768 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3769 } else { 3770 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3771 lo_thrd = aligned_mps; 3772 } 3773 3774 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3775 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3776 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3777 } 3778 3779 return true; 3780 } 3781 3782 static bool 3783 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3784 struct hns3_pkt_buf_alloc *buf_alloc) 3785 { 3786 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3787 struct hns3_pf *pf = &hns->pf; 3788 struct hns3_priv_buf *priv; 3789 uint32_t aligned_mps; 3790 uint32_t rx_all; 3791 uint8_t i; 3792 3793 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3794 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3795 3796 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3797 priv = &buf_alloc->priv_buf[i]; 3798 3799 priv->enable = 0; 3800 priv->wl.low = 0; 3801 priv->wl.high = 0; 3802 priv->buf_size = 0; 3803 3804 if (!(hw->hw_tc_map & BIT(i))) 3805 continue; 3806 3807 priv->enable = 1; 3808 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3809 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3810 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3811 HNS3_BUF_SIZE_UNIT); 3812 } else { 3813 priv->wl.low = 0; 3814 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3815 aligned_mps; 3816 } 3817 3818 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3819 } 3820 3821 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3822 } 3823 3824 static bool 3825 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3826 struct hns3_pkt_buf_alloc *buf_alloc) 3827 { 3828 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3829 struct hns3_pf *pf = &hns->pf; 3830 struct hns3_priv_buf *priv; 3831 int no_pfc_priv_num; 3832 uint32_t rx_all; 3833 uint8_t mask; 3834 int i; 3835 3836 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3837 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3838 3839 /* let the last to be cleared first */ 3840 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3841 priv = &buf_alloc->priv_buf[i]; 3842 mask = BIT((uint8_t)i); 3843 3844 if (hw->hw_tc_map & mask && 3845 !(hw->dcb_info.hw_pfc_map & mask)) { 3846 /* Clear the no pfc TC private buffer */ 3847 priv->wl.low = 0; 3848 priv->wl.high = 0; 3849 priv->buf_size = 0; 3850 priv->enable = 0; 3851 no_pfc_priv_num--; 3852 } 3853 3854 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3855 no_pfc_priv_num == 0) 3856 break; 3857 } 3858 3859 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3860 } 3861 3862 static bool 3863 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3864 struct hns3_pkt_buf_alloc *buf_alloc) 3865 { 3866 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3867 struct hns3_pf *pf = &hns->pf; 3868 struct hns3_priv_buf *priv; 3869 uint32_t rx_all; 3870 int pfc_priv_num; 3871 uint8_t mask; 3872 int i; 3873 3874 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3875 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3876 3877 /* let the last to be cleared first */ 3878 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3879 priv = &buf_alloc->priv_buf[i]; 3880 mask = BIT((uint8_t)i); 3881 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) { 3882 /* Reduce the number of pfc TC with private buffer */ 3883 priv->wl.low = 0; 3884 priv->enable = 0; 3885 priv->wl.high = 0; 3886 priv->buf_size = 0; 3887 pfc_priv_num--; 3888 } 3889 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3890 pfc_priv_num == 0) 3891 break; 3892 } 3893 3894 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3895 } 3896 3897 static bool 3898 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3899 struct hns3_pkt_buf_alloc *buf_alloc) 3900 { 3901 #define COMPENSATE_BUFFER 0x3C00 3902 #define COMPENSATE_HALF_MPS_NUM 5 3903 #define PRIV_WL_GAP 0x1800 3904 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3905 struct hns3_pf *pf = &hns->pf; 3906 uint32_t tc_num = hns3_get_tc_num(hw); 3907 uint32_t half_mps = pf->mps >> 1; 3908 struct hns3_priv_buf *priv; 3909 uint32_t min_rx_priv; 3910 uint32_t rx_priv; 3911 uint8_t i; 3912 3913 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3914 if (tc_num) 3915 rx_priv = rx_priv / tc_num; 3916 3917 if (tc_num <= NEED_RESERVE_TC_NUM) 3918 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3919 3920 /* 3921 * Minimum value of private buffer in rx direction (min_rx_priv) is 3922 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3923 * buffer if rx_priv is greater than min_rx_priv. 3924 */ 3925 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3926 COMPENSATE_HALF_MPS_NUM * half_mps; 3927 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3928 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3929 3930 if (rx_priv < min_rx_priv) 3931 return false; 3932 3933 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3934 priv = &buf_alloc->priv_buf[i]; 3935 priv->enable = 0; 3936 priv->wl.low = 0; 3937 priv->wl.high = 0; 3938 priv->buf_size = 0; 3939 3940 if (!(hw->hw_tc_map & BIT(i))) 3941 continue; 3942 3943 priv->enable = 1; 3944 priv->buf_size = rx_priv; 3945 priv->wl.high = rx_priv - pf->dv_buf_size; 3946 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3947 } 3948 3949 buf_alloc->s_buf.buf_size = 0; 3950 3951 return true; 3952 } 3953 3954 /* 3955 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3956 * @hw: pointer to struct hns3_hw 3957 * @buf_alloc: pointer to buffer calculation data 3958 * @return: 0: calculate sucessful, negative: fail 3959 */ 3960 static int 3961 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3962 { 3963 /* When DCB is not supported, rx private buffer is not allocated. */ 3964 if (!hns3_dev_dcb_supported(hw)) { 3965 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3966 struct hns3_pf *pf = &hns->pf; 3967 uint32_t rx_all = pf->pkt_buf_size; 3968 3969 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3970 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3971 return -ENOMEM; 3972 3973 return 0; 3974 } 3975 3976 /* 3977 * Try to allocate privated packet buffer for all TCs without share 3978 * buffer. 3979 */ 3980 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3981 return 0; 3982 3983 /* 3984 * Try to allocate privated packet buffer for all TCs with share 3985 * buffer. 3986 */ 3987 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3988 return 0; 3989 3990 /* 3991 * For different application scenes, the enabled port number, TC number 3992 * and no_drop TC number are different. In order to obtain the better 3993 * performance, software could allocate the buffer size and configure 3994 * the waterline by trying to decrease the private buffer size according 3995 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc 3996 * enabled tc. 3997 */ 3998 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 3999 return 0; 4000 4001 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 4002 return 0; 4003 4004 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 4005 return 0; 4006 4007 return -ENOMEM; 4008 } 4009 4010 static int 4011 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4012 { 4013 struct hns3_rx_priv_buff_cmd *req; 4014 struct hns3_cmd_desc desc; 4015 uint32_t buf_size; 4016 int ret; 4017 int i; 4018 4019 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 4020 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 4021 4022 /* Alloc private buffer TCs */ 4023 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 4024 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 4025 4026 req->buf_num[i] = 4027 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 4028 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 4029 } 4030 4031 buf_size = buf_alloc->s_buf.buf_size; 4032 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 4033 (1 << HNS3_TC0_PRI_BUF_EN_B)); 4034 4035 ret = hns3_cmd_send(hw, &desc, 1); 4036 if (ret) 4037 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 4038 4039 return ret; 4040 } 4041 4042 static int 4043 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4044 { 4045 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 4046 struct hns3_rx_priv_wl_buf *req; 4047 struct hns3_priv_buf *priv; 4048 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 4049 int i, j; 4050 int ret; 4051 4052 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 4053 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 4054 false); 4055 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 4056 4057 /* The first descriptor set the NEXT bit to 1 */ 4058 if (i == 0) 4059 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4060 else 4061 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4062 4063 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 4064 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 4065 4066 priv = &buf_alloc->priv_buf[idx]; 4067 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 4068 HNS3_BUF_UNIT_S); 4069 req->tc_wl[j].high |= 4070 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4071 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 4072 HNS3_BUF_UNIT_S); 4073 req->tc_wl[j].low |= 4074 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4075 } 4076 } 4077 4078 /* Send 2 descriptor at one time */ 4079 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 4080 if (ret) 4081 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 4082 ret); 4083 return ret; 4084 } 4085 4086 static int 4087 hns3_common_thrd_config(struct hns3_hw *hw, 4088 struct hns3_pkt_buf_alloc *buf_alloc) 4089 { 4090 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 4091 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 4092 struct hns3_rx_com_thrd *req; 4093 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 4094 struct hns3_tc_thrd *tc; 4095 int tc_idx; 4096 int i, j; 4097 int ret; 4098 4099 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 4100 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 4101 false); 4102 req = (struct hns3_rx_com_thrd *)&desc[i].data; 4103 4104 /* The first descriptor set the NEXT bit to 1 */ 4105 if (i == 0) 4106 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4107 else 4108 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4109 4110 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 4111 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 4112 tc = &s_buf->tc_thrd[tc_idx]; 4113 4114 req->com_thrd[j].high = 4115 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 4116 req->com_thrd[j].high |= 4117 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4118 req->com_thrd[j].low = 4119 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 4120 req->com_thrd[j].low |= 4121 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4122 } 4123 } 4124 4125 /* Send 2 descriptors at one time */ 4126 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 4127 if (ret) 4128 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 4129 4130 return ret; 4131 } 4132 4133 static int 4134 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4135 { 4136 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 4137 struct hns3_rx_com_wl *req; 4138 struct hns3_cmd_desc desc; 4139 int ret; 4140 4141 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 4142 4143 req = (struct hns3_rx_com_wl *)desc.data; 4144 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 4145 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4146 4147 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 4148 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4149 4150 ret = hns3_cmd_send(hw, &desc, 1); 4151 if (ret) 4152 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 4153 4154 return ret; 4155 } 4156 4157 int 4158 hns3_buffer_alloc(struct hns3_hw *hw) 4159 { 4160 struct hns3_pkt_buf_alloc pkt_buf; 4161 int ret; 4162 4163 memset(&pkt_buf, 0, sizeof(pkt_buf)); 4164 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 4165 if (ret) { 4166 PMD_INIT_LOG(ERR, 4167 "could not calc tx buffer size for all TCs %d", 4168 ret); 4169 return ret; 4170 } 4171 4172 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 4173 if (ret) { 4174 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 4175 return ret; 4176 } 4177 4178 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 4179 if (ret) { 4180 PMD_INIT_LOG(ERR, 4181 "could not calc rx priv buffer size for all TCs %d", 4182 ret); 4183 return ret; 4184 } 4185 4186 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 4187 if (ret) { 4188 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 4189 return ret; 4190 } 4191 4192 if (hns3_dev_dcb_supported(hw)) { 4193 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 4194 if (ret) { 4195 PMD_INIT_LOG(ERR, 4196 "could not configure rx private waterline %d", 4197 ret); 4198 return ret; 4199 } 4200 4201 ret = hns3_common_thrd_config(hw, &pkt_buf); 4202 if (ret) { 4203 PMD_INIT_LOG(ERR, 4204 "could not configure common threshold %d", 4205 ret); 4206 return ret; 4207 } 4208 } 4209 4210 ret = hns3_common_wl_config(hw, &pkt_buf); 4211 if (ret) 4212 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 4213 ret); 4214 4215 return ret; 4216 } 4217 4218 static int 4219 hns3_mac_init(struct hns3_hw *hw) 4220 { 4221 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4222 struct hns3_mac *mac = &hw->mac; 4223 struct hns3_pf *pf = &hns->pf; 4224 int ret; 4225 4226 pf->support_sfp_query = true; 4227 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 4228 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 4229 if (ret) { 4230 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 4231 return ret; 4232 } 4233 4234 mac->link_status = ETH_LINK_DOWN; 4235 4236 return hns3_config_mtu(hw, pf->mps); 4237 } 4238 4239 static int 4240 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 4241 { 4242 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 4243 #define HNS3_ETHERTYPE_ALREADY_ADD 1 4244 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 4245 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 4246 int return_status; 4247 4248 if (cmdq_resp) { 4249 PMD_INIT_LOG(ERR, 4250 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 4251 cmdq_resp); 4252 return -EIO; 4253 } 4254 4255 switch (resp_code) { 4256 case HNS3_ETHERTYPE_SUCCESS_ADD: 4257 case HNS3_ETHERTYPE_ALREADY_ADD: 4258 return_status = 0; 4259 break; 4260 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 4261 PMD_INIT_LOG(ERR, 4262 "add mac ethertype failed for manager table overflow."); 4263 return_status = -EIO; 4264 break; 4265 case HNS3_ETHERTYPE_KEY_CONFLICT: 4266 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 4267 return_status = -EIO; 4268 break; 4269 default: 4270 PMD_INIT_LOG(ERR, 4271 "add mac ethertype failed for undefined, code=%u.", 4272 resp_code); 4273 return_status = -EIO; 4274 break; 4275 } 4276 4277 return return_status; 4278 } 4279 4280 static int 4281 hns3_add_mgr_tbl(struct hns3_hw *hw, 4282 const struct hns3_mac_mgr_tbl_entry_cmd *req) 4283 { 4284 struct hns3_cmd_desc desc; 4285 uint8_t resp_code; 4286 uint16_t retval; 4287 int ret; 4288 4289 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 4290 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 4291 4292 ret = hns3_cmd_send(hw, &desc, 1); 4293 if (ret) { 4294 PMD_INIT_LOG(ERR, 4295 "add mac ethertype failed for cmd_send, ret =%d.", 4296 ret); 4297 return ret; 4298 } 4299 4300 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 4301 retval = rte_le_to_cpu_16(desc.retval); 4302 4303 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 4304 } 4305 4306 static void 4307 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 4308 int *table_item_num) 4309 { 4310 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 4311 4312 /* 4313 * In current version, we add one item in management table as below: 4314 * 0x0180C200000E -- LLDP MC address 4315 */ 4316 tbl = mgr_table; 4317 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 4318 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 4319 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 4320 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 4321 tbl->i_port_bitmap = 0x1; 4322 *table_item_num = 1; 4323 } 4324 4325 static int 4326 hns3_init_mgr_tbl(struct hns3_hw *hw) 4327 { 4328 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 4329 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 4330 int table_item_num; 4331 int ret; 4332 int i; 4333 4334 memset(mgr_table, 0, sizeof(mgr_table)); 4335 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 4336 for (i = 0; i < table_item_num; i++) { 4337 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 4338 if (ret) { 4339 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 4340 ret); 4341 return ret; 4342 } 4343 } 4344 4345 return 0; 4346 } 4347 4348 static void 4349 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 4350 bool en_mc, bool en_bc, int vport_id) 4351 { 4352 if (!param) 4353 return; 4354 4355 memset(param, 0, sizeof(struct hns3_promisc_param)); 4356 if (en_uc) 4357 param->enable = HNS3_PROMISC_EN_UC; 4358 if (en_mc) 4359 param->enable |= HNS3_PROMISC_EN_MC; 4360 if (en_bc) 4361 param->enable |= HNS3_PROMISC_EN_BC; 4362 param->vf_id = vport_id; 4363 } 4364 4365 static int 4366 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 4367 { 4368 struct hns3_promisc_cfg_cmd *req; 4369 struct hns3_cmd_desc desc; 4370 int ret; 4371 4372 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 4373 4374 req = (struct hns3_promisc_cfg_cmd *)desc.data; 4375 req->vf_id = param->vf_id; 4376 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 4377 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 4378 4379 ret = hns3_cmd_send(hw, &desc, 1); 4380 if (ret) 4381 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 4382 4383 return ret; 4384 } 4385 4386 static int 4387 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 4388 { 4389 struct hns3_promisc_param param; 4390 bool en_bc_pmc = true; 4391 uint8_t vf_id; 4392 4393 /* 4394 * In current version VF is not supported when PF is driven by DPDK 4395 * driver, just need to configure parameters for PF vport. 4396 */ 4397 vf_id = HNS3_PF_FUNC_ID; 4398 4399 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 4400 return hns3_cmd_set_promisc_mode(hw, ¶m); 4401 } 4402 4403 static int 4404 hns3_promisc_init(struct hns3_hw *hw) 4405 { 4406 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4407 struct hns3_pf *pf = &hns->pf; 4408 struct hns3_promisc_param param; 4409 uint16_t func_id; 4410 int ret; 4411 4412 ret = hns3_set_promisc_mode(hw, false, false); 4413 if (ret) { 4414 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 4415 return ret; 4416 } 4417 4418 /* 4419 * In current version VFs are not supported when PF is driven by DPDK 4420 * driver. After PF has been taken over by DPDK, the original VF will 4421 * be invalid. So, there is a possibility of entry residues. It should 4422 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 4423 * during init. 4424 */ 4425 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 4426 hns3_promisc_param_init(¶m, false, false, false, func_id); 4427 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4428 if (ret) { 4429 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode," 4430 " ret = %d", func_id, ret); 4431 return ret; 4432 } 4433 } 4434 4435 return 0; 4436 } 4437 4438 static void 4439 hns3_promisc_uninit(struct hns3_hw *hw) 4440 { 4441 struct hns3_promisc_param param; 4442 uint16_t func_id; 4443 int ret; 4444 4445 func_id = HNS3_PF_FUNC_ID; 4446 4447 /* 4448 * In current version VFs are not supported when PF is driven by 4449 * DPDK driver, and VFs' promisc mode status has been cleared during 4450 * init and their status will not change. So just clear PF's promisc 4451 * mode status during uninit. 4452 */ 4453 hns3_promisc_param_init(¶m, false, false, false, func_id); 4454 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4455 if (ret) 4456 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 4457 " uninit, ret = %d", ret); 4458 } 4459 4460 static int 4461 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 4462 { 4463 bool allmulti = dev->data->all_multicast ? true : false; 4464 struct hns3_adapter *hns = dev->data->dev_private; 4465 struct hns3_hw *hw = &hns->hw; 4466 uint64_t offloads; 4467 int err; 4468 int ret; 4469 4470 rte_spinlock_lock(&hw->lock); 4471 ret = hns3_set_promisc_mode(hw, true, true); 4472 if (ret) { 4473 rte_spinlock_unlock(&hw->lock); 4474 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 4475 ret); 4476 return ret; 4477 } 4478 4479 /* 4480 * When promiscuous mode was enabled, disable the vlan filter to let 4481 * all packets coming in in the receiving direction. 4482 */ 4483 offloads = dev->data->dev_conf.rxmode.offloads; 4484 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4485 ret = hns3_enable_vlan_filter(hns, false); 4486 if (ret) { 4487 hns3_err(hw, "failed to enable promiscuous mode due to " 4488 "failure to disable vlan filter, ret = %d", 4489 ret); 4490 err = hns3_set_promisc_mode(hw, false, allmulti); 4491 if (err) 4492 hns3_err(hw, "failed to restore promiscuous " 4493 "status after disable vlan filter " 4494 "failed during enabling promiscuous " 4495 "mode, ret = %d", ret); 4496 } 4497 } 4498 4499 rte_spinlock_unlock(&hw->lock); 4500 4501 return ret; 4502 } 4503 4504 static int 4505 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 4506 { 4507 bool allmulti = dev->data->all_multicast ? true : false; 4508 struct hns3_adapter *hns = dev->data->dev_private; 4509 struct hns3_hw *hw = &hns->hw; 4510 uint64_t offloads; 4511 int err; 4512 int ret; 4513 4514 /* If now in all_multicast mode, must remain in all_multicast mode. */ 4515 rte_spinlock_lock(&hw->lock); 4516 ret = hns3_set_promisc_mode(hw, false, allmulti); 4517 if (ret) { 4518 rte_spinlock_unlock(&hw->lock); 4519 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 4520 ret); 4521 return ret; 4522 } 4523 /* when promiscuous mode was disabled, restore the vlan filter status */ 4524 offloads = dev->data->dev_conf.rxmode.offloads; 4525 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4526 ret = hns3_enable_vlan_filter(hns, true); 4527 if (ret) { 4528 hns3_err(hw, "failed to disable promiscuous mode due to" 4529 " failure to restore vlan filter, ret = %d", 4530 ret); 4531 err = hns3_set_promisc_mode(hw, true, true); 4532 if (err) 4533 hns3_err(hw, "failed to restore promiscuous " 4534 "status after enabling vlan filter " 4535 "failed during disabling promiscuous " 4536 "mode, ret = %d", ret); 4537 } 4538 } 4539 rte_spinlock_unlock(&hw->lock); 4540 4541 return ret; 4542 } 4543 4544 static int 4545 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 4546 { 4547 struct hns3_adapter *hns = dev->data->dev_private; 4548 struct hns3_hw *hw = &hns->hw; 4549 int ret; 4550 4551 if (dev->data->promiscuous) 4552 return 0; 4553 4554 rte_spinlock_lock(&hw->lock); 4555 ret = hns3_set_promisc_mode(hw, false, true); 4556 rte_spinlock_unlock(&hw->lock); 4557 if (ret) 4558 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 4559 ret); 4560 4561 return ret; 4562 } 4563 4564 static int 4565 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 4566 { 4567 struct hns3_adapter *hns = dev->data->dev_private; 4568 struct hns3_hw *hw = &hns->hw; 4569 int ret; 4570 4571 /* If now in promiscuous mode, must remain in all_multicast mode. */ 4572 if (dev->data->promiscuous) 4573 return 0; 4574 4575 rte_spinlock_lock(&hw->lock); 4576 ret = hns3_set_promisc_mode(hw, false, false); 4577 rte_spinlock_unlock(&hw->lock); 4578 if (ret) 4579 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4580 ret); 4581 4582 return ret; 4583 } 4584 4585 static int 4586 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4587 { 4588 struct hns3_hw *hw = &hns->hw; 4589 bool allmulti = hw->data->all_multicast ? true : false; 4590 int ret; 4591 4592 if (hw->data->promiscuous) { 4593 ret = hns3_set_promisc_mode(hw, true, true); 4594 if (ret) 4595 hns3_err(hw, "failed to restore promiscuous mode, " 4596 "ret = %d", ret); 4597 return ret; 4598 } 4599 4600 ret = hns3_set_promisc_mode(hw, false, allmulti); 4601 if (ret) 4602 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4603 ret); 4604 return ret; 4605 } 4606 4607 static int 4608 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) 4609 { 4610 struct hns3_sfp_info_cmd *resp; 4611 struct hns3_cmd_desc desc; 4612 int ret; 4613 4614 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 4615 resp = (struct hns3_sfp_info_cmd *)desc.data; 4616 resp->query_type = HNS3_ACTIVE_QUERY; 4617 4618 ret = hns3_cmd_send(hw, &desc, 1); 4619 if (ret == -EOPNOTSUPP) { 4620 hns3_warn(hw, "firmware does not support get SFP info," 4621 " ret = %d.", ret); 4622 return ret; 4623 } else if (ret) { 4624 hns3_err(hw, "get sfp info failed, ret = %d.", ret); 4625 return ret; 4626 } 4627 4628 /* 4629 * In some case, the speed of MAC obtained from firmware may be 0, it 4630 * shouldn't be set to mac->speed. 4631 */ 4632 if (!rte_le_to_cpu_32(resp->sfp_speed)) 4633 return 0; 4634 4635 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed); 4636 /* 4637 * if resp->supported_speed is 0, it means it's an old version 4638 * firmware, do not update these params. 4639 */ 4640 if (resp->supported_speed) { 4641 mac_info->query_type = HNS3_ACTIVE_QUERY; 4642 mac_info->supported_speed = 4643 rte_le_to_cpu_32(resp->supported_speed); 4644 mac_info->support_autoneg = resp->autoneg_ability; 4645 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED 4646 : ETH_LINK_AUTONEG; 4647 } else { 4648 mac_info->query_type = HNS3_DEFAULT_QUERY; 4649 } 4650 4651 return 0; 4652 } 4653 4654 static uint8_t 4655 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4656 { 4657 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 4658 duplex = ETH_LINK_FULL_DUPLEX; 4659 4660 return duplex; 4661 } 4662 4663 static int 4664 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4665 { 4666 struct hns3_mac *mac = &hw->mac; 4667 int ret; 4668 4669 duplex = hns3_check_speed_dup(duplex, speed); 4670 if (mac->link_speed == speed && mac->link_duplex == duplex) 4671 return 0; 4672 4673 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4674 if (ret) 4675 return ret; 4676 4677 ret = hns3_port_shaper_update(hw, speed); 4678 if (ret) 4679 return ret; 4680 4681 mac->link_speed = speed; 4682 mac->link_duplex = duplex; 4683 4684 return 0; 4685 } 4686 4687 static int 4688 hns3_update_fiber_link_info(struct hns3_hw *hw) 4689 { 4690 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 4691 struct hns3_mac *mac = &hw->mac; 4692 struct hns3_mac mac_info; 4693 int ret; 4694 4695 /* If firmware do not support get SFP/qSFP speed, return directly */ 4696 if (!pf->support_sfp_query) 4697 return 0; 4698 4699 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4700 ret = hns3_get_sfp_info(hw, &mac_info); 4701 if (ret == -EOPNOTSUPP) { 4702 pf->support_sfp_query = false; 4703 return ret; 4704 } else if (ret) 4705 return ret; 4706 4707 /* Do nothing if no SFP */ 4708 if (mac_info.link_speed == ETH_SPEED_NUM_NONE) 4709 return 0; 4710 4711 /* 4712 * If query_type is HNS3_ACTIVE_QUERY, it is no need 4713 * to reconfigure the speed of MAC. Otherwise, it indicates 4714 * that the current firmware only supports to obtain the 4715 * speed of the SFP, and the speed of MAC needs to reconfigure. 4716 */ 4717 mac->query_type = mac_info.query_type; 4718 if (mac->query_type == HNS3_ACTIVE_QUERY) { 4719 if (mac_info.link_speed != mac->link_speed) { 4720 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4721 if (ret) 4722 return ret; 4723 } 4724 4725 mac->link_speed = mac_info.link_speed; 4726 mac->supported_speed = mac_info.supported_speed; 4727 mac->support_autoneg = mac_info.support_autoneg; 4728 mac->link_autoneg = mac_info.link_autoneg; 4729 4730 return 0; 4731 } 4732 4733 /* Config full duplex for SFP */ 4734 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, 4735 ETH_LINK_FULL_DUPLEX); 4736 } 4737 4738 static void 4739 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac) 4740 { 4741 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f 4742 4743 struct hns3_phy_params_bd0_cmd *req; 4744 uint32_t supported; 4745 4746 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 4747 mac->link_speed = rte_le_to_cpu_32(req->speed); 4748 mac->link_duplex = hns3_get_bit(req->duplex, 4749 HNS3_PHY_DUPLEX_CFG_B); 4750 mac->link_autoneg = hns3_get_bit(req->autoneg, 4751 HNS3_PHY_AUTONEG_CFG_B); 4752 mac->advertising = rte_le_to_cpu_32(req->advertising); 4753 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising); 4754 supported = rte_le_to_cpu_32(req->supported); 4755 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK; 4756 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT); 4757 } 4758 4759 static int 4760 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac) 4761 { 4762 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 4763 uint16_t i; 4764 int ret; 4765 4766 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 4767 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 4768 true); 4769 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4770 } 4771 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true); 4772 4773 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 4774 if (ret) { 4775 hns3_err(hw, "get phy parameters failed, ret = %d.", ret); 4776 return ret; 4777 } 4778 4779 hns3_parse_copper_phy_params(desc, mac); 4780 4781 return 0; 4782 } 4783 4784 static int 4785 hns3_update_copper_link_info(struct hns3_hw *hw) 4786 { 4787 struct hns3_mac *mac = &hw->mac; 4788 struct hns3_mac mac_info; 4789 int ret; 4790 4791 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4792 ret = hns3_get_copper_phy_params(hw, &mac_info); 4793 if (ret) 4794 return ret; 4795 4796 if (mac_info.link_speed != mac->link_speed) { 4797 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4798 if (ret) 4799 return ret; 4800 } 4801 4802 mac->link_speed = mac_info.link_speed; 4803 mac->link_duplex = mac_info.link_duplex; 4804 mac->link_autoneg = mac_info.link_autoneg; 4805 mac->supported_speed = mac_info.supported_speed; 4806 mac->advertising = mac_info.advertising; 4807 mac->lp_advertising = mac_info.lp_advertising; 4808 mac->support_autoneg = mac_info.support_autoneg; 4809 4810 return 0; 4811 } 4812 4813 static int 4814 hns3_update_link_info(struct rte_eth_dev *eth_dev) 4815 { 4816 struct hns3_adapter *hns = eth_dev->data->dev_private; 4817 struct hns3_hw *hw = &hns->hw; 4818 int ret = 0; 4819 4820 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) 4821 ret = hns3_update_copper_link_info(hw); 4822 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) 4823 ret = hns3_update_fiber_link_info(hw); 4824 4825 return ret; 4826 } 4827 4828 static int 4829 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4830 { 4831 struct hns3_config_mac_mode_cmd *req; 4832 struct hns3_cmd_desc desc; 4833 uint32_t loop_en = 0; 4834 uint8_t val = 0; 4835 int ret; 4836 4837 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4838 4839 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4840 if (enable) 4841 val = 1; 4842 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4843 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4844 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4845 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4846 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4847 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4848 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4849 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4850 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4851 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4852 4853 /* 4854 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4855 * when receiving frames. Otherwise, CRC will be stripped. 4856 */ 4857 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 4858 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4859 else 4860 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4861 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4862 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4863 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4864 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4865 4866 ret = hns3_cmd_send(hw, &desc, 1); 4867 if (ret) 4868 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4869 4870 return ret; 4871 } 4872 4873 static int 4874 hns3_get_mac_link_status(struct hns3_hw *hw) 4875 { 4876 struct hns3_link_status_cmd *req; 4877 struct hns3_cmd_desc desc; 4878 int link_status; 4879 int ret; 4880 4881 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4882 ret = hns3_cmd_send(hw, &desc, 1); 4883 if (ret) { 4884 hns3_err(hw, "get link status cmd failed %d", ret); 4885 return ETH_LINK_DOWN; 4886 } 4887 4888 req = (struct hns3_link_status_cmd *)desc.data; 4889 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4890 4891 return !!link_status; 4892 } 4893 4894 static bool 4895 hns3_update_link_status(struct hns3_hw *hw) 4896 { 4897 int state; 4898 4899 state = hns3_get_mac_link_status(hw); 4900 if (state != hw->mac.link_status) { 4901 hw->mac.link_status = state; 4902 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4903 return true; 4904 } 4905 4906 return false; 4907 } 4908 4909 void 4910 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query) 4911 { 4912 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4913 struct rte_eth_link new_link; 4914 int ret; 4915 4916 if (query) 4917 hns3_update_port_link_info(dev); 4918 4919 memset(&new_link, 0, sizeof(new_link)); 4920 hns3_setup_linkstatus(dev, &new_link); 4921 4922 ret = rte_eth_linkstatus_set(dev, &new_link); 4923 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0) 4924 hns3_start_report_lse(dev); 4925 } 4926 4927 static void 4928 hns3_service_handler(void *param) 4929 { 4930 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4931 struct hns3_adapter *hns = eth_dev->data->dev_private; 4932 struct hns3_hw *hw = &hns->hw; 4933 4934 if (!hns3_is_reset_pending(hns)) 4935 hns3_update_linkstatus_and_event(hw, true); 4936 else 4937 hns3_warn(hw, "Cancel the query when reset is pending"); 4938 4939 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4940 } 4941 4942 static int 4943 hns3_init_hardware(struct hns3_adapter *hns) 4944 { 4945 struct hns3_hw *hw = &hns->hw; 4946 int ret; 4947 4948 ret = hns3_map_tqp(hw); 4949 if (ret) { 4950 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4951 return ret; 4952 } 4953 4954 ret = hns3_init_umv_space(hw); 4955 if (ret) { 4956 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4957 return ret; 4958 } 4959 4960 ret = hns3_mac_init(hw); 4961 if (ret) { 4962 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4963 goto err_mac_init; 4964 } 4965 4966 ret = hns3_init_mgr_tbl(hw); 4967 if (ret) { 4968 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4969 goto err_mac_init; 4970 } 4971 4972 ret = hns3_promisc_init(hw); 4973 if (ret) { 4974 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4975 ret); 4976 goto err_mac_init; 4977 } 4978 4979 ret = hns3_init_vlan_config(hns); 4980 if (ret) { 4981 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4982 goto err_mac_init; 4983 } 4984 4985 ret = hns3_dcb_init(hw); 4986 if (ret) { 4987 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4988 goto err_mac_init; 4989 } 4990 4991 ret = hns3_init_fd_config(hns); 4992 if (ret) { 4993 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 4994 goto err_mac_init; 4995 } 4996 4997 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 4998 if (ret) { 4999 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 5000 goto err_mac_init; 5001 } 5002 5003 ret = hns3_config_gro(hw, false); 5004 if (ret) { 5005 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 5006 goto err_mac_init; 5007 } 5008 5009 /* 5010 * In the initialization clearing the all hardware mapping relationship 5011 * configurations between queues and interrupt vectors is needed, so 5012 * some error caused by the residual configurations, such as the 5013 * unexpected interrupt, can be avoid. 5014 */ 5015 ret = hns3_init_ring_with_vector(hw); 5016 if (ret) { 5017 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 5018 goto err_mac_init; 5019 } 5020 5021 return 0; 5022 5023 err_mac_init: 5024 hns3_uninit_umv_space(hw); 5025 return ret; 5026 } 5027 5028 static int 5029 hns3_clear_hw(struct hns3_hw *hw) 5030 { 5031 struct hns3_cmd_desc desc; 5032 int ret; 5033 5034 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 5035 5036 ret = hns3_cmd_send(hw, &desc, 1); 5037 if (ret && ret != -EOPNOTSUPP) 5038 return ret; 5039 5040 return 0; 5041 } 5042 5043 static void 5044 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 5045 { 5046 uint32_t val; 5047 5048 /* 5049 * The new firmware support report more hardware error types by 5050 * msix mode. These errors are defined as RAS errors in hardware 5051 * and belong to a different type from the MSI-x errors processed 5052 * by the network driver. 5053 * 5054 * Network driver should open the new error report on initialization. 5055 */ 5056 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5057 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 5058 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 5059 } 5060 5061 static uint32_t 5062 hns3_set_firber_default_support_speed(struct hns3_hw *hw) 5063 { 5064 struct hns3_mac *mac = &hw->mac; 5065 5066 switch (mac->link_speed) { 5067 case ETH_SPEED_NUM_1G: 5068 return HNS3_FIBER_LINK_SPEED_1G_BIT; 5069 case ETH_SPEED_NUM_10G: 5070 return HNS3_FIBER_LINK_SPEED_10G_BIT; 5071 case ETH_SPEED_NUM_25G: 5072 return HNS3_FIBER_LINK_SPEED_25G_BIT; 5073 case ETH_SPEED_NUM_40G: 5074 return HNS3_FIBER_LINK_SPEED_40G_BIT; 5075 case ETH_SPEED_NUM_50G: 5076 return HNS3_FIBER_LINK_SPEED_50G_BIT; 5077 case ETH_SPEED_NUM_100G: 5078 return HNS3_FIBER_LINK_SPEED_100G_BIT; 5079 case ETH_SPEED_NUM_200G: 5080 return HNS3_FIBER_LINK_SPEED_200G_BIT; 5081 default: 5082 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed); 5083 return 0; 5084 } 5085 } 5086 5087 /* 5088 * Validity of supported_speed for firber and copper media type can be 5089 * guaranteed by the following policy: 5090 * Copper: 5091 * Although the initialization of the phy in the firmware may not be 5092 * completed, the firmware can guarantees that the supported_speed is 5093 * an valid value. 5094 * Firber: 5095 * If the version of firmware supports the acitive query way of the 5096 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained 5097 * through it. If unsupported, use the SFP's speed as the value of the 5098 * supported_speed. 5099 */ 5100 static int 5101 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev) 5102 { 5103 struct hns3_adapter *hns = eth_dev->data->dev_private; 5104 struct hns3_hw *hw = &hns->hw; 5105 struct hns3_mac *mac = &hw->mac; 5106 int ret; 5107 5108 ret = hns3_update_link_info(eth_dev); 5109 if (ret) 5110 return ret; 5111 5112 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) { 5113 /* 5114 * Some firmware does not support the report of supported_speed, 5115 * and only report the effective speed of SFP. In this case, it 5116 * is necessary to use the SFP's speed as the supported_speed. 5117 */ 5118 if (mac->supported_speed == 0) 5119 mac->supported_speed = 5120 hns3_set_firber_default_support_speed(hw); 5121 } 5122 5123 return 0; 5124 } 5125 5126 static void 5127 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns) 5128 { 5129 struct hns3_mac *mac = &hns->hw.mac; 5130 5131 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) { 5132 hns->pf.support_fc_autoneg = true; 5133 return; 5134 } 5135 5136 /* 5137 * Flow control auto-negotiation requires the cooperation of the driver 5138 * and firmware. Currently, the optical port does not support flow 5139 * control auto-negotiation. 5140 */ 5141 hns->pf.support_fc_autoneg = false; 5142 } 5143 5144 static int 5145 hns3_init_pf(struct rte_eth_dev *eth_dev) 5146 { 5147 struct rte_device *dev = eth_dev->device; 5148 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5149 struct hns3_adapter *hns = eth_dev->data->dev_private; 5150 struct hns3_hw *hw = &hns->hw; 5151 int ret; 5152 5153 PMD_INIT_FUNC_TRACE(); 5154 5155 /* Get hardware io base address from pcie BAR2 IO space */ 5156 hw->io_base = pci_dev->mem_resource[2].addr; 5157 5158 /* Firmware command queue initialize */ 5159 ret = hns3_cmd_init_queue(hw); 5160 if (ret) { 5161 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 5162 goto err_cmd_init_queue; 5163 } 5164 5165 hns3_clear_all_event_cause(hw); 5166 5167 /* Firmware command initialize */ 5168 ret = hns3_cmd_init(hw); 5169 if (ret) { 5170 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 5171 goto err_cmd_init; 5172 } 5173 5174 /* 5175 * To ensure that the hardware environment is clean during 5176 * initialization, the driver actively clear the hardware environment 5177 * during initialization, including PF and corresponding VFs' vlan, mac, 5178 * flow table configurations, etc. 5179 */ 5180 ret = hns3_clear_hw(hw); 5181 if (ret) { 5182 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 5183 goto err_cmd_init; 5184 } 5185 5186 /* Hardware statistics of imissed registers cleared. */ 5187 ret = hns3_update_imissed_stats(hw, true); 5188 if (ret) { 5189 hns3_err(hw, "clear imissed stats failed, ret = %d", ret); 5190 goto err_cmd_init; 5191 } 5192 5193 hns3_config_all_msix_error(hw, true); 5194 5195 ret = rte_intr_callback_register(&pci_dev->intr_handle, 5196 hns3_interrupt_handler, 5197 eth_dev); 5198 if (ret) { 5199 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 5200 goto err_intr_callback_register; 5201 } 5202 5203 ret = hns3_ptp_init(hw); 5204 if (ret) 5205 goto err_get_config; 5206 5207 /* Enable interrupt */ 5208 rte_intr_enable(&pci_dev->intr_handle); 5209 hns3_pf_enable_irq0(hw); 5210 5211 /* Get configuration */ 5212 ret = hns3_get_configuration(hw); 5213 if (ret) { 5214 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 5215 goto err_get_config; 5216 } 5217 5218 ret = hns3_tqp_stats_init(hw); 5219 if (ret) 5220 goto err_get_config; 5221 5222 ret = hns3_init_hardware(hns); 5223 if (ret) { 5224 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 5225 goto err_init_hw; 5226 } 5227 5228 /* Initialize flow director filter list & hash */ 5229 ret = hns3_fdir_filter_init(hns); 5230 if (ret) { 5231 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 5232 goto err_fdir; 5233 } 5234 5235 hns3_rss_set_default_args(hw); 5236 5237 ret = hns3_enable_hw_error_intr(hns, true); 5238 if (ret) { 5239 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 5240 ret); 5241 goto err_enable_intr; 5242 } 5243 5244 ret = hns3_get_port_supported_speed(eth_dev); 5245 if (ret) { 5246 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported " 5247 "by device, ret = %d.", ret); 5248 goto err_supported_speed; 5249 } 5250 5251 hns3_get_fc_autoneg_capability(hns); 5252 5253 hns3_tm_conf_init(eth_dev); 5254 5255 return 0; 5256 5257 err_supported_speed: 5258 (void)hns3_enable_hw_error_intr(hns, false); 5259 err_enable_intr: 5260 hns3_fdir_filter_uninit(hns); 5261 err_fdir: 5262 hns3_uninit_umv_space(hw); 5263 err_init_hw: 5264 hns3_tqp_stats_uninit(hw); 5265 err_get_config: 5266 hns3_pf_disable_irq0(hw); 5267 rte_intr_disable(&pci_dev->intr_handle); 5268 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 5269 eth_dev); 5270 err_intr_callback_register: 5271 err_cmd_init: 5272 hns3_cmd_uninit(hw); 5273 hns3_cmd_destroy_queue(hw); 5274 err_cmd_init_queue: 5275 hw->io_base = NULL; 5276 5277 return ret; 5278 } 5279 5280 static void 5281 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 5282 { 5283 struct hns3_adapter *hns = eth_dev->data->dev_private; 5284 struct rte_device *dev = eth_dev->device; 5285 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5286 struct hns3_hw *hw = &hns->hw; 5287 5288 PMD_INIT_FUNC_TRACE(); 5289 5290 hns3_tm_conf_uninit(eth_dev); 5291 hns3_enable_hw_error_intr(hns, false); 5292 hns3_rss_uninit(hns); 5293 (void)hns3_config_gro(hw, false); 5294 hns3_promisc_uninit(hw); 5295 hns3_fdir_filter_uninit(hns); 5296 hns3_uninit_umv_space(hw); 5297 hns3_tqp_stats_uninit(hw); 5298 hns3_config_mac_tnl_int(hw, false); 5299 hns3_pf_disable_irq0(hw); 5300 rte_intr_disable(&pci_dev->intr_handle); 5301 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 5302 eth_dev); 5303 hns3_config_all_msix_error(hw, false); 5304 hns3_cmd_uninit(hw); 5305 hns3_cmd_destroy_queue(hw); 5306 hw->io_base = NULL; 5307 } 5308 5309 static uint32_t 5310 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds) 5311 { 5312 uint32_t speed_bit; 5313 5314 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) { 5315 case ETH_LINK_SPEED_10M: 5316 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT; 5317 break; 5318 case ETH_LINK_SPEED_10M_HD: 5319 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT; 5320 break; 5321 case ETH_LINK_SPEED_100M: 5322 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT; 5323 break; 5324 case ETH_LINK_SPEED_100M_HD: 5325 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT; 5326 break; 5327 case ETH_LINK_SPEED_1G: 5328 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT; 5329 break; 5330 default: 5331 speed_bit = 0; 5332 break; 5333 } 5334 5335 return speed_bit; 5336 } 5337 5338 static uint32_t 5339 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds) 5340 { 5341 uint32_t speed_bit; 5342 5343 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) { 5344 case ETH_LINK_SPEED_1G: 5345 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT; 5346 break; 5347 case ETH_LINK_SPEED_10G: 5348 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT; 5349 break; 5350 case ETH_LINK_SPEED_25G: 5351 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT; 5352 break; 5353 case ETH_LINK_SPEED_40G: 5354 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT; 5355 break; 5356 case ETH_LINK_SPEED_50G: 5357 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT; 5358 break; 5359 case ETH_LINK_SPEED_100G: 5360 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT; 5361 break; 5362 case ETH_LINK_SPEED_200G: 5363 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT; 5364 break; 5365 default: 5366 speed_bit = 0; 5367 break; 5368 } 5369 5370 return speed_bit; 5371 } 5372 5373 static int 5374 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds) 5375 { 5376 struct hns3_mac *mac = &hw->mac; 5377 uint32_t supported_speed = mac->supported_speed; 5378 uint32_t speed_bit = 0; 5379 5380 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 5381 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds); 5382 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) 5383 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds); 5384 5385 if (!(speed_bit & supported_speed)) { 5386 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.", 5387 link_speeds); 5388 return -EINVAL; 5389 } 5390 5391 return 0; 5392 } 5393 5394 static inline uint32_t 5395 hns3_get_link_speed(uint32_t link_speeds) 5396 { 5397 uint32_t speed = ETH_SPEED_NUM_NONE; 5398 5399 if (link_speeds & ETH_LINK_SPEED_10M || 5400 link_speeds & ETH_LINK_SPEED_10M_HD) 5401 speed = ETH_SPEED_NUM_10M; 5402 if (link_speeds & ETH_LINK_SPEED_100M || 5403 link_speeds & ETH_LINK_SPEED_100M_HD) 5404 speed = ETH_SPEED_NUM_100M; 5405 if (link_speeds & ETH_LINK_SPEED_1G) 5406 speed = ETH_SPEED_NUM_1G; 5407 if (link_speeds & ETH_LINK_SPEED_10G) 5408 speed = ETH_SPEED_NUM_10G; 5409 if (link_speeds & ETH_LINK_SPEED_25G) 5410 speed = ETH_SPEED_NUM_25G; 5411 if (link_speeds & ETH_LINK_SPEED_40G) 5412 speed = ETH_SPEED_NUM_40G; 5413 if (link_speeds & ETH_LINK_SPEED_50G) 5414 speed = ETH_SPEED_NUM_50G; 5415 if (link_speeds & ETH_LINK_SPEED_100G) 5416 speed = ETH_SPEED_NUM_100G; 5417 if (link_speeds & ETH_LINK_SPEED_200G) 5418 speed = ETH_SPEED_NUM_200G; 5419 5420 return speed; 5421 } 5422 5423 static uint8_t 5424 hns3_get_link_duplex(uint32_t link_speeds) 5425 { 5426 if ((link_speeds & ETH_LINK_SPEED_10M_HD) || 5427 (link_speeds & ETH_LINK_SPEED_100M_HD)) 5428 return ETH_LINK_HALF_DUPLEX; 5429 else 5430 return ETH_LINK_FULL_DUPLEX; 5431 } 5432 5433 static int 5434 hns3_set_copper_port_link_speed(struct hns3_hw *hw, 5435 struct hns3_set_link_speed_cfg *cfg) 5436 { 5437 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 5438 struct hns3_phy_params_bd0_cmd *req; 5439 uint16_t i; 5440 5441 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 5442 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 5443 false); 5444 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 5445 } 5446 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false); 5447 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 5448 req->autoneg = cfg->autoneg; 5449 5450 /* 5451 * The full speed capability is used to negotiate when 5452 * auto-negotiation is enabled. 5453 */ 5454 if (cfg->autoneg) { 5455 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT | 5456 HNS3_PHY_LINK_SPEED_10M_HD_BIT | 5457 HNS3_PHY_LINK_SPEED_100M_BIT | 5458 HNS3_PHY_LINK_SPEED_100M_HD_BIT | 5459 HNS3_PHY_LINK_SPEED_1000M_BIT; 5460 } else { 5461 req->speed = cfg->speed; 5462 req->duplex = cfg->duplex; 5463 } 5464 5465 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 5466 } 5467 5468 static int 5469 hns3_set_autoneg(struct hns3_hw *hw, bool enable) 5470 { 5471 struct hns3_config_auto_neg_cmd *req; 5472 struct hns3_cmd_desc desc; 5473 uint32_t flag = 0; 5474 int ret; 5475 5476 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false); 5477 5478 req = (struct hns3_config_auto_neg_cmd *)desc.data; 5479 if (enable) 5480 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1); 5481 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag); 5482 5483 ret = hns3_cmd_send(hw, &desc, 1); 5484 if (ret) 5485 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret); 5486 5487 return ret; 5488 } 5489 5490 static int 5491 hns3_set_fiber_port_link_speed(struct hns3_hw *hw, 5492 struct hns3_set_link_speed_cfg *cfg) 5493 { 5494 int ret; 5495 5496 if (hw->mac.support_autoneg) { 5497 ret = hns3_set_autoneg(hw, cfg->autoneg); 5498 if (ret) { 5499 hns3_err(hw, "failed to configure auto-negotiation."); 5500 return ret; 5501 } 5502 5503 /* 5504 * To enable auto-negotiation, we only need to open the switch 5505 * of auto-negotiation, then firmware sets all speed 5506 * capabilities. 5507 */ 5508 if (cfg->autoneg) 5509 return 0; 5510 } 5511 5512 /* 5513 * Some hardware doesn't support auto-negotiation, but users may not 5514 * configure link_speeds (default 0), which means auto-negotiation. 5515 * In this case, it should return success. 5516 */ 5517 if (cfg->autoneg) 5518 return 0; 5519 5520 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex); 5521 } 5522 5523 static int 5524 hns3_set_port_link_speed(struct hns3_hw *hw, 5525 struct hns3_set_link_speed_cfg *cfg) 5526 { 5527 int ret; 5528 5529 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) { 5530 #if defined(RTE_HNS3_ONLY_1630_FPGA) 5531 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 5532 if (pf->is_tmp_phy) 5533 return 0; 5534 #endif 5535 5536 ret = hns3_set_copper_port_link_speed(hw, cfg); 5537 if (ret) { 5538 hns3_err(hw, "failed to set copper port link speed," 5539 "ret = %d.", ret); 5540 return ret; 5541 } 5542 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) { 5543 ret = hns3_set_fiber_port_link_speed(hw, cfg); 5544 if (ret) { 5545 hns3_err(hw, "failed to set fiber port link speed," 5546 "ret = %d.", ret); 5547 return ret; 5548 } 5549 } 5550 5551 return 0; 5552 } 5553 5554 static int 5555 hns3_apply_link_speed(struct hns3_hw *hw) 5556 { 5557 struct rte_eth_conf *conf = &hw->data->dev_conf; 5558 struct hns3_set_link_speed_cfg cfg; 5559 5560 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg)); 5561 cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ? 5562 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 5563 if (cfg.autoneg != ETH_LINK_AUTONEG) { 5564 cfg.speed = hns3_get_link_speed(conf->link_speeds); 5565 cfg.duplex = hns3_get_link_duplex(conf->link_speeds); 5566 } 5567 5568 return hns3_set_port_link_speed(hw, &cfg); 5569 } 5570 5571 static int 5572 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 5573 { 5574 struct hns3_hw *hw = &hns->hw; 5575 int ret; 5576 5577 ret = hns3_dcb_cfg_update(hns); 5578 if (ret) 5579 return ret; 5580 5581 /* 5582 * The hns3_dcb_cfg_update may configure TM module, so 5583 * hns3_tm_conf_update must called later. 5584 */ 5585 ret = hns3_tm_conf_update(hw); 5586 if (ret) { 5587 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret); 5588 return ret; 5589 } 5590 5591 hns3_enable_rxd_adv_layout(hw); 5592 5593 ret = hns3_init_queues(hns, reset_queue); 5594 if (ret) { 5595 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret); 5596 return ret; 5597 } 5598 5599 ret = hns3_cfg_mac_mode(hw, true); 5600 if (ret) { 5601 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret); 5602 goto err_config_mac_mode; 5603 } 5604 5605 ret = hns3_apply_link_speed(hw); 5606 if (ret) 5607 goto err_set_link_speed; 5608 5609 return 0; 5610 5611 err_set_link_speed: 5612 (void)hns3_cfg_mac_mode(hw, false); 5613 5614 err_config_mac_mode: 5615 hns3_dev_release_mbufs(hns); 5616 /* 5617 * Here is exception handling, hns3_reset_all_tqps will have the 5618 * corresponding error message if it is handled incorrectly, so it is 5619 * not necessary to check hns3_reset_all_tqps return value, here keep 5620 * ret as the error code causing the exception. 5621 */ 5622 (void)hns3_reset_all_tqps(hns); 5623 return ret; 5624 } 5625 5626 static int 5627 hns3_map_rx_interrupt(struct rte_eth_dev *dev) 5628 { 5629 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5630 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5631 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5632 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET; 5633 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET; 5634 uint32_t intr_vector; 5635 uint16_t q_id; 5636 int ret; 5637 5638 /* 5639 * hns3 needs a separate interrupt to be used as event interrupt which 5640 * could not be shared with task queue pair, so KERNEL drivers need 5641 * support multiple interrupt vectors. 5642 */ 5643 if (dev->data->dev_conf.intr_conf.rxq == 0 || 5644 !rte_intr_cap_multiple(intr_handle)) 5645 return 0; 5646 5647 rte_intr_disable(intr_handle); 5648 intr_vector = hw->used_rx_queues; 5649 /* creates event fd for each intr vector when MSIX is used */ 5650 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5651 return -EINVAL; 5652 5653 if (intr_handle->intr_vec == NULL) { 5654 intr_handle->intr_vec = 5655 rte_zmalloc("intr_vec", 5656 hw->used_rx_queues * sizeof(int), 0); 5657 if (intr_handle->intr_vec == NULL) { 5658 hns3_err(hw, "failed to allocate %u rx_queues intr_vec", 5659 hw->used_rx_queues); 5660 ret = -ENOMEM; 5661 goto alloc_intr_vec_error; 5662 } 5663 } 5664 5665 if (rte_intr_allow_others(intr_handle)) { 5666 vec = RTE_INTR_VEC_RXTX_OFFSET; 5667 base = RTE_INTR_VEC_RXTX_OFFSET; 5668 } 5669 5670 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5671 ret = hns3_bind_ring_with_vector(hw, vec, true, 5672 HNS3_RING_TYPE_RX, q_id); 5673 if (ret) 5674 goto bind_vector_error; 5675 intr_handle->intr_vec[q_id] = vec; 5676 /* 5677 * If there are not enough efds (e.g. not enough interrupt), 5678 * remaining queues will be bond to the last interrupt. 5679 */ 5680 if (vec < base + intr_handle->nb_efd - 1) 5681 vec++; 5682 } 5683 rte_intr_enable(intr_handle); 5684 return 0; 5685 5686 bind_vector_error: 5687 rte_free(intr_handle->intr_vec); 5688 intr_handle->intr_vec = NULL; 5689 alloc_intr_vec_error: 5690 rte_intr_efd_disable(intr_handle); 5691 return ret; 5692 } 5693 5694 static int 5695 hns3_restore_rx_interrupt(struct hns3_hw *hw) 5696 { 5697 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 5698 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5699 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5700 uint16_t q_id; 5701 int ret; 5702 5703 if (dev->data->dev_conf.intr_conf.rxq == 0) 5704 return 0; 5705 5706 if (rte_intr_dp_is_en(intr_handle)) { 5707 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5708 ret = hns3_bind_ring_with_vector(hw, 5709 intr_handle->intr_vec[q_id], true, 5710 HNS3_RING_TYPE_RX, q_id); 5711 if (ret) 5712 return ret; 5713 } 5714 } 5715 5716 return 0; 5717 } 5718 5719 static void 5720 hns3_restore_filter(struct rte_eth_dev *dev) 5721 { 5722 hns3_restore_rss_filter(dev); 5723 } 5724 5725 static int 5726 hns3_dev_start(struct rte_eth_dev *dev) 5727 { 5728 struct hns3_adapter *hns = dev->data->dev_private; 5729 struct hns3_hw *hw = &hns->hw; 5730 int ret; 5731 5732 PMD_INIT_FUNC_TRACE(); 5733 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 5734 return -EBUSY; 5735 5736 rte_spinlock_lock(&hw->lock); 5737 hw->adapter_state = HNS3_NIC_STARTING; 5738 5739 ret = hns3_do_start(hns, true); 5740 if (ret) { 5741 hw->adapter_state = HNS3_NIC_CONFIGURED; 5742 rte_spinlock_unlock(&hw->lock); 5743 return ret; 5744 } 5745 ret = hns3_map_rx_interrupt(dev); 5746 if (ret) 5747 goto map_rx_inter_err; 5748 5749 /* 5750 * There are three register used to control the status of a TQP 5751 * (contains a pair of Tx queue and Rx queue) in the new version network 5752 * engine. One is used to control the enabling of Tx queue, the other is 5753 * used to control the enabling of Rx queue, and the last is the master 5754 * switch used to control the enabling of the tqp. The Tx register and 5755 * TQP register must be enabled at the same time to enable a Tx queue. 5756 * The same applies to the Rx queue. For the older network engine, this 5757 * function only refresh the enabled flag, and it is used to update the 5758 * status of queue in the dpdk framework. 5759 */ 5760 ret = hns3_start_all_txqs(dev); 5761 if (ret) 5762 goto map_rx_inter_err; 5763 5764 ret = hns3_start_all_rxqs(dev); 5765 if (ret) 5766 goto start_all_rxqs_fail; 5767 5768 hw->adapter_state = HNS3_NIC_STARTED; 5769 rte_spinlock_unlock(&hw->lock); 5770 5771 hns3_rx_scattered_calc(dev); 5772 hns3_set_rxtx_function(dev); 5773 hns3_mp_req_start_rxtx(dev); 5774 5775 hns3_restore_filter(dev); 5776 5777 /* Enable interrupt of all rx queues before enabling queues */ 5778 hns3_dev_all_rx_queue_intr_enable(hw, true); 5779 5780 /* 5781 * After finished the initialization, enable tqps to receive/transmit 5782 * packets and refresh all queue status. 5783 */ 5784 hns3_start_tqps(hw); 5785 5786 hns3_tm_dev_start_proc(hw); 5787 5788 if (dev->data->dev_conf.intr_conf.lsc != 0) 5789 hns3_dev_link_update(dev, 0); 5790 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 5791 5792 hns3_info(hw, "hns3 dev start successful!"); 5793 5794 return 0; 5795 5796 start_all_rxqs_fail: 5797 hns3_stop_all_txqs(dev); 5798 map_rx_inter_err: 5799 (void)hns3_do_stop(hns); 5800 hw->adapter_state = HNS3_NIC_CONFIGURED; 5801 rte_spinlock_unlock(&hw->lock); 5802 5803 return ret; 5804 } 5805 5806 static int 5807 hns3_do_stop(struct hns3_adapter *hns) 5808 { 5809 struct hns3_hw *hw = &hns->hw; 5810 int ret; 5811 5812 /* 5813 * The "hns3_do_stop" function will also be called by .stop_service to 5814 * prepare reset. At the time of global or IMP reset, the command cannot 5815 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 5816 * accessed during the reset process. So the mbuf can not be released 5817 * during reset and is required to be released after the reset is 5818 * completed. 5819 */ 5820 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 5821 hns3_dev_release_mbufs(hns); 5822 5823 ret = hns3_cfg_mac_mode(hw, false); 5824 if (ret) 5825 return ret; 5826 hw->mac.link_status = ETH_LINK_DOWN; 5827 5828 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 5829 hns3_configure_all_mac_addr(hns, true); 5830 ret = hns3_reset_all_tqps(hns); 5831 if (ret) { 5832 hns3_err(hw, "failed to reset all queues ret = %d.", 5833 ret); 5834 return ret; 5835 } 5836 } 5837 hw->mac.default_addr_setted = false; 5838 return 0; 5839 } 5840 5841 static void 5842 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) 5843 { 5844 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5845 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5846 struct hns3_adapter *hns = dev->data->dev_private; 5847 struct hns3_hw *hw = &hns->hw; 5848 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 5849 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 5850 uint16_t q_id; 5851 5852 if (dev->data->dev_conf.intr_conf.rxq == 0) 5853 return; 5854 5855 /* unmap the ring with vector */ 5856 if (rte_intr_allow_others(intr_handle)) { 5857 vec = RTE_INTR_VEC_RXTX_OFFSET; 5858 base = RTE_INTR_VEC_RXTX_OFFSET; 5859 } 5860 if (rte_intr_dp_is_en(intr_handle)) { 5861 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5862 (void)hns3_bind_ring_with_vector(hw, vec, false, 5863 HNS3_RING_TYPE_RX, 5864 q_id); 5865 if (vec < base + intr_handle->nb_efd - 1) 5866 vec++; 5867 } 5868 } 5869 /* Clean datapath event and queue/vec mapping */ 5870 rte_intr_efd_disable(intr_handle); 5871 if (intr_handle->intr_vec) { 5872 rte_free(intr_handle->intr_vec); 5873 intr_handle->intr_vec = NULL; 5874 } 5875 } 5876 5877 static int 5878 hns3_dev_stop(struct rte_eth_dev *dev) 5879 { 5880 struct hns3_adapter *hns = dev->data->dev_private; 5881 struct hns3_hw *hw = &hns->hw; 5882 5883 PMD_INIT_FUNC_TRACE(); 5884 dev->data->dev_started = 0; 5885 5886 hw->adapter_state = HNS3_NIC_STOPPING; 5887 hns3_set_rxtx_function(dev); 5888 rte_wmb(); 5889 /* Disable datapath on secondary process. */ 5890 hns3_mp_req_stop_rxtx(dev); 5891 /* Prevent crashes when queues are still in use. */ 5892 rte_delay_ms(hw->tqps_num); 5893 5894 rte_spinlock_lock(&hw->lock); 5895 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 5896 hns3_tm_dev_stop_proc(hw); 5897 hns3_config_mac_tnl_int(hw, false); 5898 hns3_stop_tqps(hw); 5899 hns3_do_stop(hns); 5900 hns3_unmap_rx_interrupt(dev); 5901 hw->adapter_state = HNS3_NIC_CONFIGURED; 5902 } 5903 hns3_rx_scattered_reset(dev); 5904 rte_eal_alarm_cancel(hns3_service_handler, dev); 5905 hns3_stop_report_lse(dev); 5906 rte_spinlock_unlock(&hw->lock); 5907 5908 return 0; 5909 } 5910 5911 static int 5912 hns3_dev_close(struct rte_eth_dev *eth_dev) 5913 { 5914 struct hns3_adapter *hns = eth_dev->data->dev_private; 5915 struct hns3_hw *hw = &hns->hw; 5916 int ret = 0; 5917 5918 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5919 rte_free(eth_dev->process_private); 5920 eth_dev->process_private = NULL; 5921 return 0; 5922 } 5923 5924 if (hw->adapter_state == HNS3_NIC_STARTED) 5925 ret = hns3_dev_stop(eth_dev); 5926 5927 hw->adapter_state = HNS3_NIC_CLOSING; 5928 hns3_reset_abort(hns); 5929 hw->adapter_state = HNS3_NIC_CLOSED; 5930 5931 hns3_configure_all_mc_mac_addr(hns, true); 5932 hns3_remove_all_vlan_table(hns); 5933 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 5934 hns3_uninit_pf(eth_dev); 5935 hns3_free_all_queues(eth_dev); 5936 rte_free(hw->reset.wait_data); 5937 rte_free(eth_dev->process_private); 5938 eth_dev->process_private = NULL; 5939 hns3_mp_uninit_primary(); 5940 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 5941 5942 return ret; 5943 } 5944 5945 static void 5946 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause, 5947 bool *tx_pause) 5948 { 5949 struct hns3_mac *mac = &hw->mac; 5950 uint32_t advertising = mac->advertising; 5951 uint32_t lp_advertising = mac->lp_advertising; 5952 *rx_pause = false; 5953 *tx_pause = false; 5954 5955 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) { 5956 *rx_pause = true; 5957 *tx_pause = true; 5958 } else if (advertising & lp_advertising & 5959 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) { 5960 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5961 *rx_pause = true; 5962 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5963 *tx_pause = true; 5964 } 5965 } 5966 5967 static enum hns3_fc_mode 5968 hns3_get_autoneg_fc_mode(struct hns3_hw *hw) 5969 { 5970 enum hns3_fc_mode current_mode; 5971 bool rx_pause = false; 5972 bool tx_pause = false; 5973 5974 switch (hw->mac.media_type) { 5975 case HNS3_MEDIA_TYPE_COPPER: 5976 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause); 5977 break; 5978 5979 /* 5980 * Flow control auto-negotiation is not supported for fiber and 5981 * backpalne media type. 5982 */ 5983 case HNS3_MEDIA_TYPE_FIBER: 5984 case HNS3_MEDIA_TYPE_BACKPLANE: 5985 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled."); 5986 current_mode = hw->requested_fc_mode; 5987 goto out; 5988 default: 5989 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).", 5990 hw->mac.media_type); 5991 current_mode = HNS3_FC_NONE; 5992 goto out; 5993 } 5994 5995 if (rx_pause && tx_pause) 5996 current_mode = HNS3_FC_FULL; 5997 else if (rx_pause) 5998 current_mode = HNS3_FC_RX_PAUSE; 5999 else if (tx_pause) 6000 current_mode = HNS3_FC_TX_PAUSE; 6001 else 6002 current_mode = HNS3_FC_NONE; 6003 6004 out: 6005 return current_mode; 6006 } 6007 6008 static enum hns3_fc_mode 6009 hns3_get_current_fc_mode(struct rte_eth_dev *dev) 6010 { 6011 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6012 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6013 struct hns3_mac *mac = &hw->mac; 6014 6015 /* 6016 * When the flow control mode is obtained, the device may not complete 6017 * auto-negotiation. It is necessary to wait for link establishment. 6018 */ 6019 (void)hns3_dev_link_update(dev, 1); 6020 6021 /* 6022 * If the link auto-negotiation of the nic is disabled, or the flow 6023 * control auto-negotiation is not supported, the forced flow control 6024 * mode is used. 6025 */ 6026 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg) 6027 return hw->requested_fc_mode; 6028 6029 return hns3_get_autoneg_fc_mode(hw); 6030 } 6031 6032 static int 6033 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 6034 { 6035 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6036 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6037 enum hns3_fc_mode current_mode; 6038 6039 current_mode = hns3_get_current_fc_mode(dev); 6040 switch (current_mode) { 6041 case HNS3_FC_FULL: 6042 fc_conf->mode = RTE_FC_FULL; 6043 break; 6044 case HNS3_FC_TX_PAUSE: 6045 fc_conf->mode = RTE_FC_TX_PAUSE; 6046 break; 6047 case HNS3_FC_RX_PAUSE: 6048 fc_conf->mode = RTE_FC_RX_PAUSE; 6049 break; 6050 case HNS3_FC_NONE: 6051 default: 6052 fc_conf->mode = RTE_FC_NONE; 6053 break; 6054 } 6055 6056 fc_conf->pause_time = pf->pause_time; 6057 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0; 6058 6059 return 0; 6060 } 6061 6062 static void 6063 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode) 6064 { 6065 switch (mode) { 6066 case RTE_FC_NONE: 6067 hw->requested_fc_mode = HNS3_FC_NONE; 6068 break; 6069 case RTE_FC_RX_PAUSE: 6070 hw->requested_fc_mode = HNS3_FC_RX_PAUSE; 6071 break; 6072 case RTE_FC_TX_PAUSE: 6073 hw->requested_fc_mode = HNS3_FC_TX_PAUSE; 6074 break; 6075 case RTE_FC_FULL: 6076 hw->requested_fc_mode = HNS3_FC_FULL; 6077 break; 6078 default: 6079 hw->requested_fc_mode = HNS3_FC_NONE; 6080 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is " 6081 "configured to RTE_FC_NONE", mode); 6082 break; 6083 } 6084 } 6085 6086 static int 6087 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg) 6088 { 6089 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 6090 6091 if (!pf->support_fc_autoneg) { 6092 if (autoneg != 0) { 6093 hns3_err(hw, "unsupported fc auto-negotiation setting."); 6094 return -EOPNOTSUPP; 6095 } 6096 6097 /* 6098 * Flow control auto-negotiation of the NIC is not supported, 6099 * but other auto-negotiation features may be supported. 6100 */ 6101 if (autoneg != hw->mac.link_autoneg) { 6102 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!"); 6103 return -EOPNOTSUPP; 6104 } 6105 6106 return 0; 6107 } 6108 6109 /* 6110 * If flow control auto-negotiation of the NIC is supported, all 6111 * auto-negotiation features are supported. 6112 */ 6113 if (autoneg != hw->mac.link_autoneg) { 6114 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!"); 6115 return -EOPNOTSUPP; 6116 } 6117 6118 return 0; 6119 } 6120 6121 static int 6122 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 6123 { 6124 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6125 int ret; 6126 6127 if (fc_conf->high_water || fc_conf->low_water || 6128 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 6129 hns3_err(hw, "Unsupported flow control settings specified, " 6130 "high_water(%u), low_water(%u), send_xon(%u) and " 6131 "mac_ctrl_frame_fwd(%u) must be set to '0'", 6132 fc_conf->high_water, fc_conf->low_water, 6133 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 6134 return -EINVAL; 6135 } 6136 6137 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg); 6138 if (ret) 6139 return ret; 6140 6141 if (!fc_conf->pause_time) { 6142 hns3_err(hw, "Invalid pause time %u setting.", 6143 fc_conf->pause_time); 6144 return -EINVAL; 6145 } 6146 6147 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 6148 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 6149 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 6150 "current_fc_status = %d", hw->current_fc_status); 6151 return -EOPNOTSUPP; 6152 } 6153 6154 if (hw->num_tc > 1) { 6155 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported."); 6156 return -EOPNOTSUPP; 6157 } 6158 6159 hns3_get_fc_mode(hw, fc_conf->mode); 6160 6161 rte_spinlock_lock(&hw->lock); 6162 ret = hns3_fc_enable(dev, fc_conf); 6163 rte_spinlock_unlock(&hw->lock); 6164 6165 return ret; 6166 } 6167 6168 static int 6169 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 6170 struct rte_eth_pfc_conf *pfc_conf) 6171 { 6172 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6173 int ret; 6174 6175 if (!hns3_dev_dcb_supported(hw)) { 6176 hns3_err(hw, "This port does not support dcb configurations."); 6177 return -EOPNOTSUPP; 6178 } 6179 6180 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 6181 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 6182 hns3_err(hw, "Unsupported flow control settings specified, " 6183 "high_water(%u), low_water(%u), send_xon(%u) and " 6184 "mac_ctrl_frame_fwd(%u) must be set to '0'", 6185 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 6186 pfc_conf->fc.send_xon, 6187 pfc_conf->fc.mac_ctrl_frame_fwd); 6188 return -EINVAL; 6189 } 6190 if (pfc_conf->fc.autoneg) { 6191 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 6192 return -EINVAL; 6193 } 6194 if (pfc_conf->fc.pause_time == 0) { 6195 hns3_err(hw, "Invalid pause time %u setting.", 6196 pfc_conf->fc.pause_time); 6197 return -EINVAL; 6198 } 6199 6200 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 6201 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 6202 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 6203 "current_fc_status = %d", hw->current_fc_status); 6204 return -EOPNOTSUPP; 6205 } 6206 6207 hns3_get_fc_mode(hw, pfc_conf->fc.mode); 6208 6209 rte_spinlock_lock(&hw->lock); 6210 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 6211 rte_spinlock_unlock(&hw->lock); 6212 6213 return ret; 6214 } 6215 6216 static int 6217 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 6218 { 6219 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6220 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6221 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 6222 int i; 6223 6224 rte_spinlock_lock(&hw->lock); 6225 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 6226 dcb_info->nb_tcs = pf->local_max_tc; 6227 else 6228 dcb_info->nb_tcs = 1; 6229 6230 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 6231 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 6232 for (i = 0; i < dcb_info->nb_tcs; i++) 6233 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 6234 6235 for (i = 0; i < hw->num_tc; i++) { 6236 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 6237 dcb_info->tc_queue.tc_txq[0][i].base = 6238 hw->tc_queue[i].tqp_offset; 6239 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 6240 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 6241 hw->tc_queue[i].tqp_count; 6242 } 6243 rte_spinlock_unlock(&hw->lock); 6244 6245 return 0; 6246 } 6247 6248 static int 6249 hns3_reinit_dev(struct hns3_adapter *hns) 6250 { 6251 struct hns3_hw *hw = &hns->hw; 6252 int ret; 6253 6254 ret = hns3_cmd_init(hw); 6255 if (ret) { 6256 hns3_err(hw, "Failed to init cmd: %d", ret); 6257 return ret; 6258 } 6259 6260 ret = hns3_reset_all_tqps(hns); 6261 if (ret) { 6262 hns3_err(hw, "Failed to reset all queues: %d", ret); 6263 return ret; 6264 } 6265 6266 ret = hns3_init_hardware(hns); 6267 if (ret) { 6268 hns3_err(hw, "Failed to init hardware: %d", ret); 6269 return ret; 6270 } 6271 6272 ret = hns3_enable_hw_error_intr(hns, true); 6273 if (ret) { 6274 hns3_err(hw, "fail to enable hw error interrupts: %d", 6275 ret); 6276 return ret; 6277 } 6278 hns3_info(hw, "Reset done, driver initialization finished."); 6279 6280 return 0; 6281 } 6282 6283 static bool 6284 is_pf_reset_done(struct hns3_hw *hw) 6285 { 6286 uint32_t val, reg, reg_bit; 6287 6288 switch (hw->reset.level) { 6289 case HNS3_IMP_RESET: 6290 reg = HNS3_GLOBAL_RESET_REG; 6291 reg_bit = HNS3_IMP_RESET_BIT; 6292 break; 6293 case HNS3_GLOBAL_RESET: 6294 reg = HNS3_GLOBAL_RESET_REG; 6295 reg_bit = HNS3_GLOBAL_RESET_BIT; 6296 break; 6297 case HNS3_FUNC_RESET: 6298 reg = HNS3_FUN_RST_ING; 6299 reg_bit = HNS3_FUN_RST_ING_B; 6300 break; 6301 case HNS3_FLR_RESET: 6302 default: 6303 hns3_err(hw, "Wait for unsupported reset level: %d", 6304 hw->reset.level); 6305 return true; 6306 } 6307 val = hns3_read_dev(hw, reg); 6308 if (hns3_get_bit(val, reg_bit)) 6309 return false; 6310 else 6311 return true; 6312 } 6313 6314 bool 6315 hns3_is_reset_pending(struct hns3_adapter *hns) 6316 { 6317 struct hns3_hw *hw = &hns->hw; 6318 enum hns3_reset_level reset; 6319 6320 hns3_check_event_cause(hns, NULL); 6321 reset = hns3_get_reset_level(hns, &hw->reset.pending); 6322 6323 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 6324 hw->reset.level < reset) { 6325 hns3_warn(hw, "High level reset %d is pending", reset); 6326 return true; 6327 } 6328 reset = hns3_get_reset_level(hns, &hw->reset.request); 6329 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 6330 hw->reset.level < reset) { 6331 hns3_warn(hw, "High level reset %d is request", reset); 6332 return true; 6333 } 6334 return false; 6335 } 6336 6337 static int 6338 hns3_wait_hardware_ready(struct hns3_adapter *hns) 6339 { 6340 struct hns3_hw *hw = &hns->hw; 6341 struct hns3_wait_data *wait_data = hw->reset.wait_data; 6342 struct timeval tv; 6343 6344 if (wait_data->result == HNS3_WAIT_SUCCESS) 6345 return 0; 6346 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 6347 hns3_clock_gettime(&tv); 6348 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 6349 tv.tv_sec, tv.tv_usec); 6350 return -ETIME; 6351 } else if (wait_data->result == HNS3_WAIT_REQUEST) 6352 return -EAGAIN; 6353 6354 wait_data->hns = hns; 6355 wait_data->check_completion = is_pf_reset_done; 6356 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 6357 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms(); 6358 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 6359 wait_data->count = HNS3_RESET_WAIT_CNT; 6360 wait_data->result = HNS3_WAIT_REQUEST; 6361 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 6362 return -EAGAIN; 6363 } 6364 6365 static int 6366 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 6367 { 6368 struct hns3_cmd_desc desc; 6369 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 6370 6371 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 6372 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 6373 req->fun_reset_vfid = func_id; 6374 6375 return hns3_cmd_send(hw, &desc, 1); 6376 } 6377 6378 static int 6379 hns3_imp_reset_cmd(struct hns3_hw *hw) 6380 { 6381 struct hns3_cmd_desc desc; 6382 6383 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 6384 desc.data[0] = 0xeedd; 6385 6386 return hns3_cmd_send(hw, &desc, 1); 6387 } 6388 6389 static void 6390 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 6391 { 6392 struct hns3_hw *hw = &hns->hw; 6393 struct timeval tv; 6394 uint32_t val; 6395 6396 hns3_clock_gettime(&tv); 6397 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 6398 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 6399 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 6400 tv.tv_sec, tv.tv_usec); 6401 return; 6402 } 6403 6404 switch (reset_level) { 6405 case HNS3_IMP_RESET: 6406 hns3_imp_reset_cmd(hw); 6407 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 6408 tv.tv_sec, tv.tv_usec); 6409 break; 6410 case HNS3_GLOBAL_RESET: 6411 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 6412 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 6413 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 6414 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 6415 tv.tv_sec, tv.tv_usec); 6416 break; 6417 case HNS3_FUNC_RESET: 6418 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 6419 tv.tv_sec, tv.tv_usec); 6420 /* schedule again to check later */ 6421 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 6422 hns3_schedule_reset(hns); 6423 break; 6424 default: 6425 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 6426 return; 6427 } 6428 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 6429 } 6430 6431 static enum hns3_reset_level 6432 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 6433 { 6434 struct hns3_hw *hw = &hns->hw; 6435 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 6436 6437 /* Return the highest priority reset level amongst all */ 6438 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 6439 reset_level = HNS3_IMP_RESET; 6440 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 6441 reset_level = HNS3_GLOBAL_RESET; 6442 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 6443 reset_level = HNS3_FUNC_RESET; 6444 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 6445 reset_level = HNS3_FLR_RESET; 6446 6447 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 6448 return HNS3_NONE_RESET; 6449 6450 return reset_level; 6451 } 6452 6453 static void 6454 hns3_record_imp_error(struct hns3_adapter *hns) 6455 { 6456 struct hns3_hw *hw = &hns->hw; 6457 uint32_t reg_val; 6458 6459 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 6460 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 6461 hns3_warn(hw, "Detected IMP RD poison!"); 6462 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 6463 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 6464 } 6465 6466 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 6467 hns3_warn(hw, "Detected IMP CMDQ error!"); 6468 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 6469 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 6470 } 6471 } 6472 6473 static int 6474 hns3_prepare_reset(struct hns3_adapter *hns) 6475 { 6476 struct hns3_hw *hw = &hns->hw; 6477 uint32_t reg_val; 6478 int ret; 6479 6480 switch (hw->reset.level) { 6481 case HNS3_FUNC_RESET: 6482 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 6483 if (ret) 6484 return ret; 6485 6486 /* 6487 * After performaning pf reset, it is not necessary to do the 6488 * mailbox handling or send any command to firmware, because 6489 * any mailbox handling or command to firmware is only valid 6490 * after hns3_cmd_init is called. 6491 */ 6492 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 6493 hw->reset.stats.request_cnt++; 6494 break; 6495 case HNS3_IMP_RESET: 6496 hns3_record_imp_error(hns); 6497 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 6498 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 6499 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 6500 break; 6501 default: 6502 break; 6503 } 6504 return 0; 6505 } 6506 6507 static int 6508 hns3_set_rst_done(struct hns3_hw *hw) 6509 { 6510 struct hns3_pf_rst_done_cmd *req; 6511 struct hns3_cmd_desc desc; 6512 6513 req = (struct hns3_pf_rst_done_cmd *)desc.data; 6514 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 6515 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 6516 return hns3_cmd_send(hw, &desc, 1); 6517 } 6518 6519 static int 6520 hns3_stop_service(struct hns3_adapter *hns) 6521 { 6522 struct hns3_hw *hw = &hns->hw; 6523 struct rte_eth_dev *eth_dev; 6524 6525 eth_dev = &rte_eth_devices[hw->data->port_id]; 6526 hw->mac.link_status = ETH_LINK_DOWN; 6527 if (hw->adapter_state == HNS3_NIC_STARTED) { 6528 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 6529 hns3_update_linkstatus_and_event(hw, false); 6530 } 6531 6532 hns3_set_rxtx_function(eth_dev); 6533 rte_wmb(); 6534 /* Disable datapath on secondary process. */ 6535 hns3_mp_req_stop_rxtx(eth_dev); 6536 rte_delay_ms(hw->tqps_num); 6537 6538 rte_spinlock_lock(&hw->lock); 6539 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 6540 hw->adapter_state == HNS3_NIC_STOPPING) { 6541 hns3_enable_all_queues(hw, false); 6542 hns3_do_stop(hns); 6543 hw->reset.mbuf_deferred_free = true; 6544 } else 6545 hw->reset.mbuf_deferred_free = false; 6546 6547 /* 6548 * It is cumbersome for hardware to pick-and-choose entries for deletion 6549 * from table space. Hence, for function reset software intervention is 6550 * required to delete the entries 6551 */ 6552 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 6553 hns3_configure_all_mc_mac_addr(hns, true); 6554 rte_spinlock_unlock(&hw->lock); 6555 6556 return 0; 6557 } 6558 6559 static int 6560 hns3_start_service(struct hns3_adapter *hns) 6561 { 6562 struct hns3_hw *hw = &hns->hw; 6563 struct rte_eth_dev *eth_dev; 6564 6565 if (hw->reset.level == HNS3_IMP_RESET || 6566 hw->reset.level == HNS3_GLOBAL_RESET) 6567 hns3_set_rst_done(hw); 6568 eth_dev = &rte_eth_devices[hw->data->port_id]; 6569 hns3_set_rxtx_function(eth_dev); 6570 hns3_mp_req_start_rxtx(eth_dev); 6571 if (hw->adapter_state == HNS3_NIC_STARTED) { 6572 /* 6573 * This API parent function already hold the hns3_hw.lock, the 6574 * hns3_service_handler may report lse, in bonding application 6575 * it will call driver's ops which may acquire the hns3_hw.lock 6576 * again, thus lead to deadlock. 6577 * We defer calls hns3_service_handler to avoid the deadlock. 6578 */ 6579 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL, 6580 hns3_service_handler, eth_dev); 6581 6582 /* Enable interrupt of all rx queues before enabling queues */ 6583 hns3_dev_all_rx_queue_intr_enable(hw, true); 6584 /* 6585 * Enable state of each rxq and txq will be recovered after 6586 * reset, so we need to restore them before enable all tqps; 6587 */ 6588 hns3_restore_tqp_enable_state(hw); 6589 /* 6590 * When finished the initialization, enable queues to receive 6591 * and transmit packets. 6592 */ 6593 hns3_enable_all_queues(hw, true); 6594 } 6595 6596 return 0; 6597 } 6598 6599 static int 6600 hns3_restore_conf(struct hns3_adapter *hns) 6601 { 6602 struct hns3_hw *hw = &hns->hw; 6603 int ret; 6604 6605 ret = hns3_configure_all_mac_addr(hns, false); 6606 if (ret) 6607 return ret; 6608 6609 ret = hns3_configure_all_mc_mac_addr(hns, false); 6610 if (ret) 6611 goto err_mc_mac; 6612 6613 ret = hns3_dev_promisc_restore(hns); 6614 if (ret) 6615 goto err_promisc; 6616 6617 ret = hns3_restore_vlan_table(hns); 6618 if (ret) 6619 goto err_promisc; 6620 6621 ret = hns3_restore_vlan_conf(hns); 6622 if (ret) 6623 goto err_promisc; 6624 6625 ret = hns3_restore_all_fdir_filter(hns); 6626 if (ret) 6627 goto err_promisc; 6628 6629 ret = hns3_restore_ptp(hns); 6630 if (ret) 6631 goto err_promisc; 6632 6633 ret = hns3_restore_rx_interrupt(hw); 6634 if (ret) 6635 goto err_promisc; 6636 6637 ret = hns3_restore_gro_conf(hw); 6638 if (ret) 6639 goto err_promisc; 6640 6641 ret = hns3_restore_fec(hw); 6642 if (ret) 6643 goto err_promisc; 6644 6645 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 6646 ret = hns3_do_start(hns, false); 6647 if (ret) 6648 goto err_promisc; 6649 hns3_info(hw, "hns3 dev restart successful!"); 6650 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 6651 hw->adapter_state = HNS3_NIC_CONFIGURED; 6652 return 0; 6653 6654 err_promisc: 6655 hns3_configure_all_mc_mac_addr(hns, true); 6656 err_mc_mac: 6657 hns3_configure_all_mac_addr(hns, true); 6658 return ret; 6659 } 6660 6661 static void 6662 hns3_reset_service(void *param) 6663 { 6664 struct hns3_adapter *hns = (struct hns3_adapter *)param; 6665 struct hns3_hw *hw = &hns->hw; 6666 enum hns3_reset_level reset_level; 6667 struct timeval tv_delta; 6668 struct timeval tv_start; 6669 struct timeval tv; 6670 uint64_t msec; 6671 int ret; 6672 6673 /* 6674 * The interrupt is not triggered within the delay time. 6675 * The interrupt may have been lost. It is necessary to handle 6676 * the interrupt to recover from the error. 6677 */ 6678 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 6679 SCHEDULE_DEFERRED) { 6680 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 6681 __ATOMIC_RELAXED); 6682 hns3_err(hw, "Handling interrupts in delayed tasks"); 6683 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 6684 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 6685 if (reset_level == HNS3_NONE_RESET) { 6686 hns3_err(hw, "No reset level is set, try IMP reset"); 6687 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 6688 } 6689 } 6690 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 6691 6692 /* 6693 * Check if there is any ongoing reset in the hardware. This status can 6694 * be checked from reset_pending. If there is then, we need to wait for 6695 * hardware to complete reset. 6696 * a. If we are able to figure out in reasonable time that hardware 6697 * has fully resetted then, we can proceed with driver, client 6698 * reset. 6699 * b. else, we can come back later to check this status so re-sched 6700 * now. 6701 */ 6702 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 6703 if (reset_level != HNS3_NONE_RESET) { 6704 hns3_clock_gettime(&tv_start); 6705 ret = hns3_reset_process(hns, reset_level); 6706 hns3_clock_gettime(&tv); 6707 timersub(&tv, &tv_start, &tv_delta); 6708 msec = hns3_clock_calctime_ms(&tv_delta); 6709 if (msec > HNS3_RESET_PROCESS_MS) 6710 hns3_err(hw, "%d handle long time delta %" PRIu64 6711 " ms time=%ld.%.6ld", 6712 hw->reset.level, msec, 6713 tv.tv_sec, tv.tv_usec); 6714 if (ret == -EAGAIN) 6715 return; 6716 } 6717 6718 /* Check if we got any *new* reset requests to be honored */ 6719 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 6720 if (reset_level != HNS3_NONE_RESET) 6721 hns3_msix_process(hns, reset_level); 6722 } 6723 6724 static unsigned int 6725 hns3_get_speed_capa_num(uint16_t device_id) 6726 { 6727 unsigned int num; 6728 6729 switch (device_id) { 6730 case HNS3_DEV_ID_25GE: 6731 case HNS3_DEV_ID_25GE_RDMA: 6732 num = 2; 6733 break; 6734 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6735 case HNS3_DEV_ID_200G_RDMA: 6736 num = 1; 6737 break; 6738 default: 6739 num = 0; 6740 break; 6741 } 6742 6743 return num; 6744 } 6745 6746 static int 6747 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, 6748 uint16_t device_id) 6749 { 6750 switch (device_id) { 6751 case HNS3_DEV_ID_25GE: 6752 /* fallthrough */ 6753 case HNS3_DEV_ID_25GE_RDMA: 6754 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed; 6755 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa; 6756 6757 /* In HNS3 device, the 25G NIC is compatible with 10G rate */ 6758 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed; 6759 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa; 6760 break; 6761 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6762 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed; 6763 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa; 6764 break; 6765 case HNS3_DEV_ID_200G_RDMA: 6766 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed; 6767 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa; 6768 break; 6769 default: 6770 return -ENOTSUP; 6771 } 6772 6773 return 0; 6774 } 6775 6776 static int 6777 hns3_fec_get_capability(struct rte_eth_dev *dev, 6778 struct rte_eth_fec_capa *speed_fec_capa, 6779 unsigned int num) 6780 { 6781 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6782 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6783 uint16_t device_id = pci_dev->id.device_id; 6784 unsigned int capa_num; 6785 int ret; 6786 6787 capa_num = hns3_get_speed_capa_num(device_id); 6788 if (capa_num == 0) { 6789 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD", 6790 device_id); 6791 return -ENOTSUP; 6792 } 6793 6794 if (speed_fec_capa == NULL || num < capa_num) 6795 return capa_num; 6796 6797 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id); 6798 if (ret) 6799 return -ENOTSUP; 6800 6801 return capa_num; 6802 } 6803 6804 static int 6805 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state) 6806 { 6807 struct hns3_config_fec_cmd *req; 6808 struct hns3_cmd_desc desc; 6809 int ret; 6810 6811 /* 6812 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported 6813 * in device of link speed 6814 * below 10 Gbps. 6815 */ 6816 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) { 6817 *state = 0; 6818 return 0; 6819 } 6820 6821 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true); 6822 req = (struct hns3_config_fec_cmd *)desc.data; 6823 ret = hns3_cmd_send(hw, &desc, 1); 6824 if (ret) { 6825 hns3_err(hw, "get current fec auto state failed, ret = %d", 6826 ret); 6827 return ret; 6828 } 6829 6830 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B); 6831 return 0; 6832 } 6833 6834 static int 6835 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa) 6836 { 6837 struct hns3_sfp_info_cmd *resp; 6838 uint32_t tmp_fec_capa; 6839 uint8_t auto_state; 6840 struct hns3_cmd_desc desc; 6841 int ret; 6842 6843 /* 6844 * If link is down and AUTO is enabled, AUTO is returned, otherwise, 6845 * configured FEC mode is returned. 6846 * If link is up, current FEC mode is returned. 6847 */ 6848 if (hw->mac.link_status == ETH_LINK_DOWN) { 6849 ret = get_current_fec_auto_state(hw, &auto_state); 6850 if (ret) 6851 return ret; 6852 6853 if (auto_state == 0x1) { 6854 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 6855 return 0; 6856 } 6857 } 6858 6859 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 6860 resp = (struct hns3_sfp_info_cmd *)desc.data; 6861 resp->query_type = HNS3_ACTIVE_QUERY; 6862 6863 ret = hns3_cmd_send(hw, &desc, 1); 6864 if (ret == -EOPNOTSUPP) { 6865 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret); 6866 return ret; 6867 } else if (ret) { 6868 hns3_err(hw, "get FEC failed, ret = %d", ret); 6869 return ret; 6870 } 6871 6872 /* 6873 * FEC mode order defined in hns3 hardware is inconsistend with 6874 * that defined in the ethdev library. So the sequence needs 6875 * to be converted. 6876 */ 6877 switch (resp->active_fec) { 6878 case HNS3_HW_FEC_MODE_NOFEC: 6879 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6880 break; 6881 case HNS3_HW_FEC_MODE_BASER: 6882 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 6883 break; 6884 case HNS3_HW_FEC_MODE_RS: 6885 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 6886 break; 6887 default: 6888 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6889 break; 6890 } 6891 6892 *fec_capa = tmp_fec_capa; 6893 return 0; 6894 } 6895 6896 static int 6897 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 6898 { 6899 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6900 6901 return hns3_fec_get_internal(hw, fec_capa); 6902 } 6903 6904 static int 6905 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode) 6906 { 6907 struct hns3_config_fec_cmd *req; 6908 struct hns3_cmd_desc desc; 6909 int ret; 6910 6911 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false); 6912 6913 req = (struct hns3_config_fec_cmd *)desc.data; 6914 switch (mode) { 6915 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC): 6916 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6917 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF); 6918 break; 6919 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER): 6920 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6921 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER); 6922 break; 6923 case RTE_ETH_FEC_MODE_CAPA_MASK(RS): 6924 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6925 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS); 6926 break; 6927 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO): 6928 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1); 6929 break; 6930 default: 6931 return 0; 6932 } 6933 ret = hns3_cmd_send(hw, &desc, 1); 6934 if (ret) 6935 hns3_err(hw, "set fec mode failed, ret = %d", ret); 6936 6937 return ret; 6938 } 6939 6940 static uint32_t 6941 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa) 6942 { 6943 struct hns3_mac *mac = &hw->mac; 6944 uint32_t cur_capa; 6945 6946 switch (mac->link_speed) { 6947 case ETH_SPEED_NUM_10G: 6948 cur_capa = fec_capa[1].capa; 6949 break; 6950 case ETH_SPEED_NUM_25G: 6951 case ETH_SPEED_NUM_100G: 6952 case ETH_SPEED_NUM_200G: 6953 cur_capa = fec_capa[0].capa; 6954 break; 6955 default: 6956 cur_capa = 0; 6957 break; 6958 } 6959 6960 return cur_capa; 6961 } 6962 6963 static bool 6964 is_fec_mode_one_bit_set(uint32_t mode) 6965 { 6966 int cnt = 0; 6967 uint8_t i; 6968 6969 for (i = 0; i < sizeof(mode); i++) 6970 if (mode >> i & 0x1) 6971 cnt++; 6972 6973 return cnt == 1 ? true : false; 6974 } 6975 6976 static int 6977 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) 6978 { 6979 #define FEC_CAPA_NUM 2 6980 struct hns3_adapter *hns = dev->data->dev_private; 6981 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6982 struct hns3_pf *pf = &hns->pf; 6983 6984 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM]; 6985 uint32_t cur_capa; 6986 uint32_t num = FEC_CAPA_NUM; 6987 int ret; 6988 6989 ret = hns3_fec_get_capability(dev, fec_capa, num); 6990 if (ret < 0) 6991 return ret; 6992 6993 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */ 6994 if (!is_fec_mode_one_bit_set(mode)) 6995 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD," 6996 "FEC mode should be only one bit set", mode); 6997 6998 /* 6999 * Check whether the configured mode is within the FEC capability. 7000 * If not, the configured mode will not be supported. 7001 */ 7002 cur_capa = get_current_speed_fec_cap(hw, fec_capa); 7003 if (!(cur_capa & mode)) { 7004 hns3_err(hw, "unsupported FEC mode = 0x%x", mode); 7005 return -EINVAL; 7006 } 7007 7008 rte_spinlock_lock(&hw->lock); 7009 ret = hns3_set_fec_hw(hw, mode); 7010 if (ret) { 7011 rte_spinlock_unlock(&hw->lock); 7012 return ret; 7013 } 7014 7015 pf->fec_mode = mode; 7016 rte_spinlock_unlock(&hw->lock); 7017 7018 return 0; 7019 } 7020 7021 static int 7022 hns3_restore_fec(struct hns3_hw *hw) 7023 { 7024 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 7025 struct hns3_pf *pf = &hns->pf; 7026 uint32_t mode = pf->fec_mode; 7027 int ret; 7028 7029 ret = hns3_set_fec_hw(hw, mode); 7030 if (ret) 7031 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d", 7032 mode, ret); 7033 7034 return ret; 7035 } 7036 7037 static int 7038 hns3_query_dev_fec_info(struct hns3_hw *hw) 7039 { 7040 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 7041 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns); 7042 int ret; 7043 7044 ret = hns3_fec_get_internal(hw, &pf->fec_mode); 7045 if (ret) 7046 hns3_err(hw, "query device FEC info failed, ret = %d", ret); 7047 7048 return ret; 7049 } 7050 7051 static bool 7052 hns3_optical_module_existed(struct hns3_hw *hw) 7053 { 7054 struct hns3_cmd_desc desc; 7055 bool existed; 7056 int ret; 7057 7058 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true); 7059 ret = hns3_cmd_send(hw, &desc, 1); 7060 if (ret) { 7061 hns3_err(hw, 7062 "fail to get optical module exist state, ret = %d.\n", 7063 ret); 7064 return false; 7065 } 7066 existed = !!desc.data[0]; 7067 7068 return existed; 7069 } 7070 7071 static int 7072 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset, 7073 uint32_t len, uint8_t *data) 7074 { 7075 #define HNS3_SFP_INFO_CMD_NUM 6 7076 #define HNS3_SFP_INFO_MAX_LEN \ 7077 (HNS3_SFP_INFO_BD0_LEN + \ 7078 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN) 7079 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM]; 7080 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0; 7081 uint16_t read_len; 7082 uint16_t copy_len; 7083 int ret; 7084 int i; 7085 7086 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) { 7087 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM, 7088 true); 7089 if (i < HNS3_SFP_INFO_CMD_NUM - 1) 7090 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 7091 } 7092 7093 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data; 7094 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset); 7095 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN); 7096 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len); 7097 7098 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM); 7099 if (ret) { 7100 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n", 7101 ret); 7102 return ret; 7103 } 7104 7105 /* The data format in BD0 is different with the others. */ 7106 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN); 7107 memcpy(data, sfp_info_bd0->data, copy_len); 7108 read_len = copy_len; 7109 7110 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) { 7111 if (read_len >= len) 7112 break; 7113 7114 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN); 7115 memcpy(data + read_len, desc[i].data, copy_len); 7116 read_len += copy_len; 7117 } 7118 7119 return (int)read_len; 7120 } 7121 7122 static int 7123 hns3_get_module_eeprom(struct rte_eth_dev *dev, 7124 struct rte_dev_eeprom_info *info) 7125 { 7126 struct hns3_adapter *hns = dev->data->dev_private; 7127 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7128 uint32_t offset = info->offset; 7129 uint32_t len = info->length; 7130 uint8_t *data = info->data; 7131 uint32_t read_len = 0; 7132 7133 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER) 7134 return -ENOTSUP; 7135 7136 if (!hns3_optical_module_existed(hw)) { 7137 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n"); 7138 return -EIO; 7139 } 7140 7141 while (read_len < len) { 7142 int ret; 7143 ret = hns3_get_module_eeprom_data(hw, offset + read_len, 7144 len - read_len, 7145 data + read_len); 7146 if (ret < 0) 7147 return -EIO; 7148 read_len += ret; 7149 } 7150 7151 return 0; 7152 } 7153 7154 static int 7155 hns3_get_module_info(struct rte_eth_dev *dev, 7156 struct rte_eth_dev_module_info *modinfo) 7157 { 7158 #define HNS3_SFF8024_ID_SFP 0x03 7159 #define HNS3_SFF8024_ID_QSFP_8438 0x0c 7160 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d 7161 #define HNS3_SFF8024_ID_QSFP28_8636 0x11 7162 #define HNS3_SFF_8636_V1_3 0x03 7163 struct hns3_adapter *hns = dev->data->dev_private; 7164 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7165 struct rte_dev_eeprom_info info; 7166 struct hns3_sfp_type sfp_type; 7167 int ret; 7168 7169 memset(&sfp_type, 0, sizeof(sfp_type)); 7170 memset(&info, 0, sizeof(info)); 7171 info.data = (uint8_t *)&sfp_type; 7172 info.length = sizeof(sfp_type); 7173 ret = hns3_get_module_eeprom(dev, &info); 7174 if (ret) 7175 return ret; 7176 7177 switch (sfp_type.type) { 7178 case HNS3_SFF8024_ID_SFP: 7179 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7180 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7181 break; 7182 case HNS3_SFF8024_ID_QSFP_8438: 7183 modinfo->type = RTE_ETH_MODULE_SFF_8436; 7184 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 7185 break; 7186 case HNS3_SFF8024_ID_QSFP_8436_8636: 7187 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) { 7188 modinfo->type = RTE_ETH_MODULE_SFF_8436; 7189 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 7190 } else { 7191 modinfo->type = RTE_ETH_MODULE_SFF_8636; 7192 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 7193 } 7194 break; 7195 case HNS3_SFF8024_ID_QSFP28_8636: 7196 modinfo->type = RTE_ETH_MODULE_SFF_8636; 7197 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 7198 break; 7199 default: 7200 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n", 7201 sfp_type.type, sfp_type.ext_type); 7202 return -EINVAL; 7203 } 7204 7205 return 0; 7206 } 7207 7208 void 7209 hns3_clock_gettime(struct timeval *tv) 7210 { 7211 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ 7212 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW 7213 #else 7214 #define CLOCK_TYPE CLOCK_MONOTONIC 7215 #endif 7216 #define NSEC_TO_USEC_DIV 1000 7217 7218 struct timespec spec; 7219 (void)clock_gettime(CLOCK_TYPE, &spec); 7220 7221 tv->tv_sec = spec.tv_sec; 7222 tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV; 7223 } 7224 7225 uint64_t 7226 hns3_clock_calctime_ms(struct timeval *tv) 7227 { 7228 return (uint64_t)tv->tv_sec * MSEC_PER_SEC + 7229 tv->tv_usec / USEC_PER_MSEC; 7230 } 7231 7232 uint64_t 7233 hns3_clock_gettime_ms(void) 7234 { 7235 struct timeval tv; 7236 7237 hns3_clock_gettime(&tv); 7238 return hns3_clock_calctime_ms(&tv); 7239 } 7240 7241 static int 7242 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) 7243 { 7244 uint32_t hint = HNS3_IO_FUNC_HINT_NONE; 7245 7246 RTE_SET_USED(key); 7247 7248 if (strcmp(value, "vec") == 0) 7249 hint = HNS3_IO_FUNC_HINT_VEC; 7250 else if (strcmp(value, "sve") == 0) 7251 hint = HNS3_IO_FUNC_HINT_SVE; 7252 else if (strcmp(value, "simple") == 0) 7253 hint = HNS3_IO_FUNC_HINT_SIMPLE; 7254 else if (strcmp(value, "common") == 0) 7255 hint = HNS3_IO_FUNC_HINT_COMMON; 7256 7257 /* If the hint is valid then update output parameters */ 7258 if (hint != HNS3_IO_FUNC_HINT_NONE) 7259 *(uint32_t *)extra_args = hint; 7260 7261 return 0; 7262 } 7263 7264 static const char * 7265 hns3_get_io_hint_func_name(uint32_t hint) 7266 { 7267 switch (hint) { 7268 case HNS3_IO_FUNC_HINT_VEC: 7269 return "vec"; 7270 case HNS3_IO_FUNC_HINT_SVE: 7271 return "sve"; 7272 case HNS3_IO_FUNC_HINT_SIMPLE: 7273 return "simple"; 7274 case HNS3_IO_FUNC_HINT_COMMON: 7275 return "common"; 7276 default: 7277 return "none"; 7278 } 7279 } 7280 7281 static int 7282 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args) 7283 { 7284 uint64_t val; 7285 7286 RTE_SET_USED(key); 7287 7288 val = strtoull(value, NULL, 16); 7289 *(uint64_t *)extra_args = val; 7290 7291 return 0; 7292 } 7293 7294 void 7295 hns3_parse_devargs(struct rte_eth_dev *dev) 7296 { 7297 struct hns3_adapter *hns = dev->data->dev_private; 7298 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; 7299 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; 7300 struct hns3_hw *hw = &hns->hw; 7301 uint64_t dev_caps_mask = 0; 7302 struct rte_kvargs *kvlist; 7303 7304 if (dev->device->devargs == NULL) 7305 return; 7306 7307 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); 7308 if (!kvlist) 7309 return; 7310 7311 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, 7312 &hns3_parse_io_hint_func, &rx_func_hint); 7313 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, 7314 &hns3_parse_io_hint_func, &tx_func_hint); 7315 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK, 7316 &hns3_parse_dev_caps_mask, &dev_caps_mask); 7317 rte_kvargs_free(kvlist); 7318 7319 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) 7320 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, 7321 hns3_get_io_hint_func_name(rx_func_hint)); 7322 hns->rx_func_hint = rx_func_hint; 7323 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) 7324 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, 7325 hns3_get_io_hint_func_name(tx_func_hint)); 7326 hns->tx_func_hint = tx_func_hint; 7327 7328 if (dev_caps_mask != 0) 7329 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".", 7330 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask); 7331 hns->dev_caps_mask = dev_caps_mask; 7332 } 7333 7334 static const struct eth_dev_ops hns3_eth_dev_ops = { 7335 .dev_configure = hns3_dev_configure, 7336 .dev_start = hns3_dev_start, 7337 .dev_stop = hns3_dev_stop, 7338 .dev_close = hns3_dev_close, 7339 .promiscuous_enable = hns3_dev_promiscuous_enable, 7340 .promiscuous_disable = hns3_dev_promiscuous_disable, 7341 .allmulticast_enable = hns3_dev_allmulticast_enable, 7342 .allmulticast_disable = hns3_dev_allmulticast_disable, 7343 .mtu_set = hns3_dev_mtu_set, 7344 .stats_get = hns3_stats_get, 7345 .stats_reset = hns3_stats_reset, 7346 .xstats_get = hns3_dev_xstats_get, 7347 .xstats_get_names = hns3_dev_xstats_get_names, 7348 .xstats_reset = hns3_dev_xstats_reset, 7349 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 7350 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 7351 .dev_infos_get = hns3_dev_infos_get, 7352 .fw_version_get = hns3_fw_version_get, 7353 .rx_queue_setup = hns3_rx_queue_setup, 7354 .tx_queue_setup = hns3_tx_queue_setup, 7355 .rx_queue_release = hns3_dev_rx_queue_release, 7356 .tx_queue_release = hns3_dev_tx_queue_release, 7357 .rx_queue_start = hns3_dev_rx_queue_start, 7358 .rx_queue_stop = hns3_dev_rx_queue_stop, 7359 .tx_queue_start = hns3_dev_tx_queue_start, 7360 .tx_queue_stop = hns3_dev_tx_queue_stop, 7361 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 7362 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 7363 .rxq_info_get = hns3_rxq_info_get, 7364 .txq_info_get = hns3_txq_info_get, 7365 .rx_burst_mode_get = hns3_rx_burst_mode_get, 7366 .tx_burst_mode_get = hns3_tx_burst_mode_get, 7367 .flow_ctrl_get = hns3_flow_ctrl_get, 7368 .flow_ctrl_set = hns3_flow_ctrl_set, 7369 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 7370 .mac_addr_add = hns3_add_mac_addr, 7371 .mac_addr_remove = hns3_remove_mac_addr, 7372 .mac_addr_set = hns3_set_default_mac_addr, 7373 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 7374 .link_update = hns3_dev_link_update, 7375 .rss_hash_update = hns3_dev_rss_hash_update, 7376 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 7377 .reta_update = hns3_dev_rss_reta_update, 7378 .reta_query = hns3_dev_rss_reta_query, 7379 .flow_ops_get = hns3_dev_flow_ops_get, 7380 .vlan_filter_set = hns3_vlan_filter_set, 7381 .vlan_tpid_set = hns3_vlan_tpid_set, 7382 .vlan_offload_set = hns3_vlan_offload_set, 7383 .vlan_pvid_set = hns3_vlan_pvid_set, 7384 .get_reg = hns3_get_regs, 7385 .get_module_info = hns3_get_module_info, 7386 .get_module_eeprom = hns3_get_module_eeprom, 7387 .get_dcb_info = hns3_get_dcb_info, 7388 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 7389 .fec_get_capability = hns3_fec_get_capability, 7390 .fec_get = hns3_fec_get, 7391 .fec_set = hns3_fec_set, 7392 .tm_ops_get = hns3_tm_ops_get, 7393 .tx_done_cleanup = hns3_tx_done_cleanup, 7394 .timesync_enable = hns3_timesync_enable, 7395 .timesync_disable = hns3_timesync_disable, 7396 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp, 7397 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp, 7398 .timesync_adjust_time = hns3_timesync_adjust_time, 7399 .timesync_read_time = hns3_timesync_read_time, 7400 .timesync_write_time = hns3_timesync_write_time, 7401 }; 7402 7403 static const struct hns3_reset_ops hns3_reset_ops = { 7404 .reset_service = hns3_reset_service, 7405 .stop_service = hns3_stop_service, 7406 .prepare_reset = hns3_prepare_reset, 7407 .wait_hardware_ready = hns3_wait_hardware_ready, 7408 .reinit_dev = hns3_reinit_dev, 7409 .restore_conf = hns3_restore_conf, 7410 .start_service = hns3_start_service, 7411 }; 7412 7413 static int 7414 hns3_dev_init(struct rte_eth_dev *eth_dev) 7415 { 7416 struct hns3_adapter *hns = eth_dev->data->dev_private; 7417 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 7418 struct rte_ether_addr *eth_addr; 7419 struct hns3_hw *hw = &hns->hw; 7420 int ret; 7421 7422 PMD_INIT_FUNC_TRACE(); 7423 7424 eth_dev->process_private = (struct hns3_process_private *) 7425 rte_zmalloc_socket("hns3_filter_list", 7426 sizeof(struct hns3_process_private), 7427 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 7428 if (eth_dev->process_private == NULL) { 7429 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 7430 return -ENOMEM; 7431 } 7432 7433 hns3_flow_init(eth_dev); 7434 7435 hns3_set_rxtx_function(eth_dev); 7436 eth_dev->dev_ops = &hns3_eth_dev_ops; 7437 eth_dev->rx_queue_count = hns3_rx_queue_count; 7438 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 7439 ret = hns3_mp_init_secondary(); 7440 if (ret) { 7441 PMD_INIT_LOG(ERR, "Failed to init for secondary " 7442 "process, ret = %d", ret); 7443 goto err_mp_init_secondary; 7444 } 7445 7446 hw->secondary_cnt++; 7447 return 0; 7448 } 7449 7450 ret = hns3_mp_init_primary(); 7451 if (ret) { 7452 PMD_INIT_LOG(ERR, 7453 "Failed to init for primary process, ret = %d", 7454 ret); 7455 goto err_mp_init_primary; 7456 } 7457 7458 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 7459 hns->is_vf = false; 7460 hw->data = eth_dev->data; 7461 hns3_parse_devargs(eth_dev); 7462 7463 /* 7464 * Set default max packet size according to the mtu 7465 * default vale in DPDK frame. 7466 */ 7467 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 7468 7469 ret = hns3_reset_init(hw); 7470 if (ret) 7471 goto err_init_reset; 7472 hw->reset.ops = &hns3_reset_ops; 7473 7474 ret = hns3_init_pf(eth_dev); 7475 if (ret) { 7476 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 7477 goto err_init_pf; 7478 } 7479 7480 /* Allocate memory for storing MAC addresses */ 7481 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 7482 sizeof(struct rte_ether_addr) * 7483 HNS3_UC_MACADDR_NUM, 0); 7484 if (eth_dev->data->mac_addrs == NULL) { 7485 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 7486 "to store MAC addresses", 7487 sizeof(struct rte_ether_addr) * 7488 HNS3_UC_MACADDR_NUM); 7489 ret = -ENOMEM; 7490 goto err_rte_zmalloc; 7491 } 7492 7493 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 7494 if (!rte_is_valid_assigned_ether_addr(eth_addr)) { 7495 rte_eth_random_addr(hw->mac.mac_addr); 7496 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 7497 (struct rte_ether_addr *)hw->mac.mac_addr); 7498 hns3_warn(hw, "default mac_addr from firmware is an invalid " 7499 "unicast address, using random MAC address %s", 7500 mac_str); 7501 } 7502 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 7503 ð_dev->data->mac_addrs[0]); 7504 7505 hw->adapter_state = HNS3_NIC_INITIALIZED; 7506 7507 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 7508 SCHEDULE_PENDING) { 7509 hns3_err(hw, "Reschedule reset service after dev_init"); 7510 hns3_schedule_reset(hns); 7511 } else { 7512 /* IMP will wait ready flag before reset */ 7513 hns3_notify_reset_ready(hw, false); 7514 } 7515 7516 hns3_info(hw, "hns3 dev initialization successful!"); 7517 return 0; 7518 7519 err_rte_zmalloc: 7520 hns3_uninit_pf(eth_dev); 7521 7522 err_init_pf: 7523 rte_free(hw->reset.wait_data); 7524 7525 err_init_reset: 7526 hns3_mp_uninit_primary(); 7527 7528 err_mp_init_primary: 7529 err_mp_init_secondary: 7530 eth_dev->dev_ops = NULL; 7531 eth_dev->rx_pkt_burst = NULL; 7532 eth_dev->rx_descriptor_status = NULL; 7533 eth_dev->tx_pkt_burst = NULL; 7534 eth_dev->tx_pkt_prepare = NULL; 7535 eth_dev->tx_descriptor_status = NULL; 7536 rte_free(eth_dev->process_private); 7537 eth_dev->process_private = NULL; 7538 return ret; 7539 } 7540 7541 static int 7542 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 7543 { 7544 struct hns3_adapter *hns = eth_dev->data->dev_private; 7545 struct hns3_hw *hw = &hns->hw; 7546 7547 PMD_INIT_FUNC_TRACE(); 7548 7549 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 7550 rte_free(eth_dev->process_private); 7551 eth_dev->process_private = NULL; 7552 return 0; 7553 } 7554 7555 if (hw->adapter_state < HNS3_NIC_CLOSING) 7556 hns3_dev_close(eth_dev); 7557 7558 hw->adapter_state = HNS3_NIC_REMOVED; 7559 return 0; 7560 } 7561 7562 static int 7563 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 7564 struct rte_pci_device *pci_dev) 7565 { 7566 return rte_eth_dev_pci_generic_probe(pci_dev, 7567 sizeof(struct hns3_adapter), 7568 hns3_dev_init); 7569 } 7570 7571 static int 7572 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 7573 { 7574 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 7575 } 7576 7577 static const struct rte_pci_id pci_id_hns3_map[] = { 7578 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 7579 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 7580 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 7581 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 7582 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 7583 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 7584 { .vendor_id = 0, }, /* sentinel */ 7585 }; 7586 7587 static struct rte_pci_driver rte_hns3_pmd = { 7588 .id_table = pci_id_hns3_map, 7589 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 7590 .probe = eth_hns3_pci_probe, 7591 .remove = eth_hns3_pci_remove, 7592 }; 7593 7594 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 7595 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 7596 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 7597 RTE_PMD_REGISTER_PARAM_STRING(net_hns3, 7598 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 7599 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " 7600 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "); 7601 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE); 7602 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE); 7603