1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <rte_alarm.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev_pci.h> 8 #include <rte_io.h> 9 #include <rte_pci.h> 10 11 #include "hns3_ethdev.h" 12 #include "hns3_logs.h" 13 #include "hns3_rxtx.h" 14 #include "hns3_intr.h" 15 #include "hns3_regs.h" 16 #include "hns3_dcb.h" 17 #include "hns3_mp.h" 18 19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 21 22 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 23 #define HNS3_INVALID_PVID 0xFFFF 24 25 #define HNS3_FILTER_TYPE_VF 0 26 #define HNS3_FILTER_TYPE_PORT 1 27 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 28 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 29 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 30 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 31 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 32 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 33 | HNS3_FILTER_FE_ROCE_EGRESS_B) 34 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 35 | HNS3_FILTER_FE_ROCE_INGRESS_B) 36 37 /* Reset related Registers */ 38 #define HNS3_GLOBAL_RESET_BIT 0 39 #define HNS3_CORE_RESET_BIT 1 40 #define HNS3_IMP_RESET_BIT 2 41 #define HNS3_FUN_RST_ING_B 0 42 43 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 45 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 47 48 #define HNS3_RESET_WAIT_MS 100 49 #define HNS3_RESET_WAIT_CNT 200 50 51 /* FEC mode order defined in HNS3 hardware */ 52 #define HNS3_HW_FEC_MODE_NOFEC 0 53 #define HNS3_HW_FEC_MODE_BASER 1 54 #define HNS3_HW_FEC_MODE_RS 2 55 56 enum hns3_evt_cause { 57 HNS3_VECTOR0_EVENT_RST, 58 HNS3_VECTOR0_EVENT_MBX, 59 HNS3_VECTOR0_EVENT_ERR, 60 HNS3_VECTOR0_EVENT_OTHER, 61 }; 62 63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { 64 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 65 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 66 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 67 68 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 69 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 70 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 71 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 72 73 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 74 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 75 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 76 77 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 78 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 79 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 80 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 81 82 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 83 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 84 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 85 86 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 87 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 88 RTE_ETH_FEC_MODE_CAPA_MASK(RS) } 89 }; 90 91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 92 uint64_t *levels); 93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 95 int on); 96 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev); 97 98 static int hns3_add_mc_addr(struct hns3_hw *hw, 99 struct rte_ether_addr *mac_addr); 100 static int hns3_remove_mc_addr(struct hns3_hw *hw, 101 struct rte_ether_addr *mac_addr); 102 static int hns3_restore_fec(struct hns3_hw *hw); 103 static int hns3_query_dev_fec_info(struct rte_eth_dev *dev); 104 105 static void 106 hns3_pf_disable_irq0(struct hns3_hw *hw) 107 { 108 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 109 } 110 111 static void 112 hns3_pf_enable_irq0(struct hns3_hw *hw) 113 { 114 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 115 } 116 117 static enum hns3_evt_cause 118 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 119 { 120 struct hns3_hw *hw = &hns->hw; 121 uint32_t vector0_int_stats; 122 uint32_t cmdq_src_val; 123 uint32_t hw_err_src_reg; 124 uint32_t val; 125 enum hns3_evt_cause ret; 126 127 /* fetch the events from their corresponding regs */ 128 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 129 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 130 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 131 132 /* 133 * Assumption: If by any chance reset and mailbox events are reported 134 * together then we will only process reset event and defer the 135 * processing of the mailbox events. Since, we would have not cleared 136 * RX CMDQ event this time we would receive again another interrupt 137 * from H/W just for the mailbox. 138 */ 139 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 140 rte_atomic16_set(&hw->reset.disable_cmd, 1); 141 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 142 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 143 if (clearval) { 144 hw->reset.stats.imp_cnt++; 145 hns3_warn(hw, "IMP reset detected, clear reset status"); 146 } else { 147 hns3_schedule_delayed_reset(hns); 148 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 149 } 150 151 ret = HNS3_VECTOR0_EVENT_RST; 152 goto out; 153 } 154 155 /* Global reset */ 156 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 157 rte_atomic16_set(&hw->reset.disable_cmd, 1); 158 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 159 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 160 if (clearval) { 161 hw->reset.stats.global_cnt++; 162 hns3_warn(hw, "Global reset detected, clear reset status"); 163 } else { 164 hns3_schedule_delayed_reset(hns); 165 hns3_warn(hw, "Global reset detected, don't clear reset status"); 166 } 167 168 ret = HNS3_VECTOR0_EVENT_RST; 169 goto out; 170 } 171 172 /* check for vector0 msix event source */ 173 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 174 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 175 val = vector0_int_stats | hw_err_src_reg; 176 ret = HNS3_VECTOR0_EVENT_ERR; 177 goto out; 178 } 179 180 /* check for vector0 mailbox(=CMDQ RX) event source */ 181 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 182 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 183 val = cmdq_src_val; 184 ret = HNS3_VECTOR0_EVENT_MBX; 185 goto out; 186 } 187 188 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg)) 189 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x", 190 vector0_int_stats, cmdq_src_val, hw_err_src_reg); 191 val = vector0_int_stats; 192 ret = HNS3_VECTOR0_EVENT_OTHER; 193 out: 194 195 if (clearval) 196 *clearval = val; 197 return ret; 198 } 199 200 static void 201 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 202 { 203 if (event_type == HNS3_VECTOR0_EVENT_RST) 204 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 205 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 206 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 207 } 208 209 static void 210 hns3_clear_all_event_cause(struct hns3_hw *hw) 211 { 212 uint32_t vector0_int_stats; 213 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 214 215 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 216 hns3_warn(hw, "Probe during IMP reset interrupt"); 217 218 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 219 hns3_warn(hw, "Probe during Global reset interrupt"); 220 221 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 222 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 223 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 224 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 225 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 226 } 227 228 static void 229 hns3_interrupt_handler(void *param) 230 { 231 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 232 struct hns3_adapter *hns = dev->data->dev_private; 233 struct hns3_hw *hw = &hns->hw; 234 enum hns3_evt_cause event_cause; 235 uint32_t clearval = 0; 236 237 /* Disable interrupt */ 238 hns3_pf_disable_irq0(hw); 239 240 event_cause = hns3_check_event_cause(hns, &clearval); 241 242 /* vector 0 interrupt is shared with reset and mailbox source events. */ 243 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 244 hns3_warn(hw, "Received err interrupt"); 245 hns3_handle_msix_error(hns, &hw->reset.request); 246 hns3_handle_ras_error(hns, &hw->reset.request); 247 hns3_schedule_reset(hns); 248 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 249 hns3_warn(hw, "Received reset interrupt"); 250 hns3_schedule_reset(hns); 251 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) 252 hns3_dev_handle_mbx_msg(hw); 253 else 254 hns3_err(hw, "Received unknown event"); 255 256 hns3_clear_event_cause(hw, event_cause, clearval); 257 /* Enable interrupt if it is not cause by reset */ 258 hns3_pf_enable_irq0(hw); 259 } 260 261 static int 262 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 263 { 264 #define HNS3_VLAN_ID_OFFSET_STEP 160 265 #define HNS3_VLAN_BYTE_SIZE 8 266 struct hns3_vlan_filter_pf_cfg_cmd *req; 267 struct hns3_hw *hw = &hns->hw; 268 uint8_t vlan_offset_byte_val; 269 struct hns3_cmd_desc desc; 270 uint8_t vlan_offset_byte; 271 uint8_t vlan_offset_base; 272 int ret; 273 274 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 275 276 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 277 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 278 HNS3_VLAN_BYTE_SIZE; 279 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 280 281 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 282 req->vlan_offset = vlan_offset_base; 283 req->vlan_cfg = on ? 0 : 1; 284 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 285 286 ret = hns3_cmd_send(hw, &desc, 1); 287 if (ret) 288 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 289 vlan_id, ret); 290 291 return ret; 292 } 293 294 static void 295 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 296 { 297 struct hns3_user_vlan_table *vlan_entry; 298 struct hns3_pf *pf = &hns->pf; 299 300 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 301 if (vlan_entry->vlan_id == vlan_id) { 302 if (vlan_entry->hd_tbl_status) 303 hns3_set_port_vlan_filter(hns, vlan_id, 0); 304 LIST_REMOVE(vlan_entry, next); 305 rte_free(vlan_entry); 306 break; 307 } 308 } 309 } 310 311 static void 312 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 313 bool writen_to_tbl) 314 { 315 struct hns3_user_vlan_table *vlan_entry; 316 struct hns3_hw *hw = &hns->hw; 317 struct hns3_pf *pf = &hns->pf; 318 319 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 320 if (vlan_entry->vlan_id == vlan_id) 321 return; 322 } 323 324 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 325 if (vlan_entry == NULL) { 326 hns3_err(hw, "Failed to malloc hns3 vlan table"); 327 return; 328 } 329 330 vlan_entry->hd_tbl_status = writen_to_tbl; 331 vlan_entry->vlan_id = vlan_id; 332 333 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 334 } 335 336 static int 337 hns3_restore_vlan_table(struct hns3_adapter *hns) 338 { 339 struct hns3_user_vlan_table *vlan_entry; 340 struct hns3_hw *hw = &hns->hw; 341 struct hns3_pf *pf = &hns->pf; 342 uint16_t vlan_id; 343 int ret = 0; 344 345 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 346 return hns3_vlan_pvid_configure(hns, 347 hw->port_base_vlan_cfg.pvid, 1); 348 349 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 350 if (vlan_entry->hd_tbl_status) { 351 vlan_id = vlan_entry->vlan_id; 352 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 353 if (ret) 354 break; 355 } 356 } 357 358 return ret; 359 } 360 361 static int 362 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 363 { 364 struct hns3_hw *hw = &hns->hw; 365 bool writen_to_tbl = false; 366 int ret = 0; 367 368 /* 369 * When vlan filter is enabled, hardware regards packets without vlan 370 * as packets with vlan 0. So, to receive packets without vlan, vlan id 371 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter. 372 */ 373 if (on == 0 && vlan_id == 0) 374 return 0; 375 376 /* 377 * When port base vlan enabled, we use port base vlan as the vlan 378 * filter condition. In this case, we don't update vlan filter table 379 * when user add new vlan or remove exist vlan, just update the 380 * vlan list. The vlan id in vlan list will be writen in vlan filter 381 * table until port base vlan disabled 382 */ 383 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 384 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 385 writen_to_tbl = true; 386 } 387 388 if (ret == 0) { 389 if (on) 390 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 391 else 392 hns3_rm_dev_vlan_table(hns, vlan_id); 393 } 394 return ret; 395 } 396 397 static int 398 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 399 { 400 struct hns3_adapter *hns = dev->data->dev_private; 401 struct hns3_hw *hw = &hns->hw; 402 int ret; 403 404 rte_spinlock_lock(&hw->lock); 405 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 406 rte_spinlock_unlock(&hw->lock); 407 return ret; 408 } 409 410 static int 411 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 412 uint16_t tpid) 413 { 414 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 415 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 416 struct hns3_hw *hw = &hns->hw; 417 struct hns3_cmd_desc desc; 418 int ret; 419 420 if ((vlan_type != ETH_VLAN_TYPE_INNER && 421 vlan_type != ETH_VLAN_TYPE_OUTER)) { 422 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 423 return -EINVAL; 424 } 425 426 if (tpid != RTE_ETHER_TYPE_VLAN) { 427 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 428 return -EINVAL; 429 } 430 431 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 432 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 433 434 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 435 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 436 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 437 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 438 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 439 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 440 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 441 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 442 } 443 444 ret = hns3_cmd_send(hw, &desc, 1); 445 if (ret) { 446 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 447 ret); 448 return ret; 449 } 450 451 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 452 453 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 454 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 455 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 456 457 ret = hns3_cmd_send(hw, &desc, 1); 458 if (ret) 459 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 460 ret); 461 return ret; 462 } 463 464 static int 465 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 466 uint16_t tpid) 467 { 468 struct hns3_adapter *hns = dev->data->dev_private; 469 struct hns3_hw *hw = &hns->hw; 470 int ret; 471 472 rte_spinlock_lock(&hw->lock); 473 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 474 rte_spinlock_unlock(&hw->lock); 475 return ret; 476 } 477 478 static int 479 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 480 struct hns3_rx_vtag_cfg *vcfg) 481 { 482 struct hns3_vport_vtag_rx_cfg_cmd *req; 483 struct hns3_hw *hw = &hns->hw; 484 struct hns3_cmd_desc desc; 485 uint16_t vport_id; 486 uint8_t bitmap; 487 int ret; 488 489 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 490 491 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 492 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 493 vcfg->strip_tag1_en ? 1 : 0); 494 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 495 vcfg->strip_tag2_en ? 1 : 0); 496 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 497 vcfg->vlan1_vlan_prionly ? 1 : 0); 498 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 499 vcfg->vlan2_vlan_prionly ? 1 : 0); 500 501 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 502 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B, 503 vcfg->strip_tag1_discard_en ? 1 : 0); 504 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B, 505 vcfg->strip_tag2_discard_en ? 1 : 0); 506 /* 507 * In current version VF is not supported when PF is driven by DPDK 508 * driver, just need to configure parameters for PF vport. 509 */ 510 vport_id = HNS3_PF_FUNC_ID; 511 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 512 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 513 req->vf_bitmap[req->vf_offset] = bitmap; 514 515 ret = hns3_cmd_send(hw, &desc, 1); 516 if (ret) 517 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 518 return ret; 519 } 520 521 static void 522 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 523 struct hns3_rx_vtag_cfg *vcfg) 524 { 525 struct hns3_pf *pf = &hns->pf; 526 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 527 } 528 529 static void 530 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 531 struct hns3_tx_vtag_cfg *vcfg) 532 { 533 struct hns3_pf *pf = &hns->pf; 534 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 535 } 536 537 static int 538 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 539 { 540 struct hns3_rx_vtag_cfg rxvlan_cfg; 541 struct hns3_hw *hw = &hns->hw; 542 int ret; 543 544 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 545 rxvlan_cfg.strip_tag1_en = false; 546 rxvlan_cfg.strip_tag2_en = enable; 547 rxvlan_cfg.strip_tag2_discard_en = false; 548 } else { 549 rxvlan_cfg.strip_tag1_en = enable; 550 rxvlan_cfg.strip_tag2_en = true; 551 rxvlan_cfg.strip_tag2_discard_en = true; 552 } 553 554 rxvlan_cfg.strip_tag1_discard_en = false; 555 rxvlan_cfg.vlan1_vlan_prionly = false; 556 rxvlan_cfg.vlan2_vlan_prionly = false; 557 rxvlan_cfg.rx_vlan_offload_en = enable; 558 559 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 560 if (ret) { 561 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret); 562 return ret; 563 } 564 565 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 566 567 return ret; 568 } 569 570 static int 571 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 572 uint8_t fe_type, bool filter_en, uint8_t vf_id) 573 { 574 struct hns3_vlan_filter_ctrl_cmd *req; 575 struct hns3_cmd_desc desc; 576 int ret; 577 578 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 579 580 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 581 req->vlan_type = vlan_type; 582 req->vlan_fe = filter_en ? fe_type : 0; 583 req->vf_id = vf_id; 584 585 ret = hns3_cmd_send(hw, &desc, 1); 586 if (ret) 587 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 588 589 return ret; 590 } 591 592 static int 593 hns3_vlan_filter_init(struct hns3_adapter *hns) 594 { 595 struct hns3_hw *hw = &hns->hw; 596 int ret; 597 598 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 599 HNS3_FILTER_FE_EGRESS, false, 600 HNS3_PF_FUNC_ID); 601 if (ret) { 602 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 603 return ret; 604 } 605 606 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 607 HNS3_FILTER_FE_INGRESS, false, 608 HNS3_PF_FUNC_ID); 609 if (ret) 610 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 611 612 return ret; 613 } 614 615 static int 616 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 617 { 618 struct hns3_hw *hw = &hns->hw; 619 int ret; 620 621 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 622 HNS3_FILTER_FE_INGRESS, enable, 623 HNS3_PF_FUNC_ID); 624 if (ret) 625 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 626 enable ? "enable" : "disable", ret); 627 628 return ret; 629 } 630 631 static int 632 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 633 { 634 struct hns3_adapter *hns = dev->data->dev_private; 635 struct hns3_hw *hw = &hns->hw; 636 struct rte_eth_rxmode *rxmode; 637 unsigned int tmp_mask; 638 bool enable; 639 int ret = 0; 640 641 rte_spinlock_lock(&hw->lock); 642 rxmode = &dev->data->dev_conf.rxmode; 643 tmp_mask = (unsigned int)mask; 644 if (tmp_mask & ETH_VLAN_FILTER_MASK) { 645 /* ignore vlan filter configuration during promiscuous mode */ 646 if (!dev->data->promiscuous) { 647 /* Enable or disable VLAN filter */ 648 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? 649 true : false; 650 651 ret = hns3_enable_vlan_filter(hns, enable); 652 if (ret) { 653 rte_spinlock_unlock(&hw->lock); 654 hns3_err(hw, "failed to %s rx filter, ret = %d", 655 enable ? "enable" : "disable", ret); 656 return ret; 657 } 658 } 659 } 660 661 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 662 /* Enable or disable VLAN stripping */ 663 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 664 true : false; 665 666 ret = hns3_en_hw_strip_rxvtag(hns, enable); 667 if (ret) { 668 rte_spinlock_unlock(&hw->lock); 669 hns3_err(hw, "failed to %s rx strip, ret = %d", 670 enable ? "enable" : "disable", ret); 671 return ret; 672 } 673 } 674 675 rte_spinlock_unlock(&hw->lock); 676 677 return ret; 678 } 679 680 static int 681 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 682 struct hns3_tx_vtag_cfg *vcfg) 683 { 684 struct hns3_vport_vtag_tx_cfg_cmd *req; 685 struct hns3_cmd_desc desc; 686 struct hns3_hw *hw = &hns->hw; 687 uint16_t vport_id; 688 uint8_t bitmap; 689 int ret; 690 691 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 692 693 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 694 req->def_vlan_tag1 = vcfg->default_tag1; 695 req->def_vlan_tag2 = vcfg->default_tag2; 696 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 697 vcfg->accept_tag1 ? 1 : 0); 698 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 699 vcfg->accept_untag1 ? 1 : 0); 700 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 701 vcfg->accept_tag2 ? 1 : 0); 702 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 703 vcfg->accept_untag2 ? 1 : 0); 704 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 705 vcfg->insert_tag1_en ? 1 : 0); 706 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 707 vcfg->insert_tag2_en ? 1 : 0); 708 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 709 710 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 711 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B, 712 vcfg->tag_shift_mode_en ? 1 : 0); 713 714 /* 715 * In current version VF is not supported when PF is driven by DPDK 716 * driver, just need to configure parameters for PF vport. 717 */ 718 vport_id = HNS3_PF_FUNC_ID; 719 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 720 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 721 req->vf_bitmap[req->vf_offset] = bitmap; 722 723 ret = hns3_cmd_send(hw, &desc, 1); 724 if (ret) 725 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 726 727 return ret; 728 } 729 730 static int 731 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 732 uint16_t pvid) 733 { 734 struct hns3_hw *hw = &hns->hw; 735 struct hns3_tx_vtag_cfg txvlan_cfg; 736 int ret; 737 738 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 739 txvlan_cfg.accept_tag1 = true; 740 txvlan_cfg.insert_tag1_en = false; 741 txvlan_cfg.default_tag1 = 0; 742 } else { 743 txvlan_cfg.accept_tag1 = 744 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE; 745 txvlan_cfg.insert_tag1_en = true; 746 txvlan_cfg.default_tag1 = pvid; 747 } 748 749 txvlan_cfg.accept_untag1 = true; 750 txvlan_cfg.accept_tag2 = true; 751 txvlan_cfg.accept_untag2 = true; 752 txvlan_cfg.insert_tag2_en = false; 753 txvlan_cfg.default_tag2 = 0; 754 txvlan_cfg.tag_shift_mode_en = true; 755 756 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 757 if (ret) { 758 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 759 ret); 760 return ret; 761 } 762 763 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 764 return ret; 765 } 766 767 768 static void 769 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 770 { 771 struct hns3_user_vlan_table *vlan_entry; 772 struct hns3_pf *pf = &hns->pf; 773 774 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 775 if (vlan_entry->hd_tbl_status) { 776 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 777 vlan_entry->hd_tbl_status = false; 778 } 779 } 780 781 if (is_del_list) { 782 vlan_entry = LIST_FIRST(&pf->vlan_list); 783 while (vlan_entry) { 784 LIST_REMOVE(vlan_entry, next); 785 rte_free(vlan_entry); 786 vlan_entry = LIST_FIRST(&pf->vlan_list); 787 } 788 } 789 } 790 791 static void 792 hns3_add_all_vlan_table(struct hns3_adapter *hns) 793 { 794 struct hns3_user_vlan_table *vlan_entry; 795 struct hns3_pf *pf = &hns->pf; 796 797 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 798 if (!vlan_entry->hd_tbl_status) { 799 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 800 vlan_entry->hd_tbl_status = true; 801 } 802 } 803 } 804 805 static void 806 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 807 { 808 struct hns3_hw *hw = &hns->hw; 809 int ret; 810 811 hns3_rm_all_vlan_table(hns, true); 812 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) { 813 ret = hns3_set_port_vlan_filter(hns, 814 hw->port_base_vlan_cfg.pvid, 0); 815 if (ret) { 816 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 817 ret); 818 return; 819 } 820 } 821 } 822 823 static int 824 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 825 uint16_t port_base_vlan_state, uint16_t new_pvid) 826 { 827 struct hns3_hw *hw = &hns->hw; 828 uint16_t old_pvid; 829 int ret; 830 831 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 832 old_pvid = hw->port_base_vlan_cfg.pvid; 833 if (old_pvid != HNS3_INVALID_PVID) { 834 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 835 if (ret) { 836 hns3_err(hw, "failed to remove old pvid %u, " 837 "ret = %d", old_pvid, ret); 838 return ret; 839 } 840 } 841 842 hns3_rm_all_vlan_table(hns, false); 843 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1); 844 if (ret) { 845 hns3_err(hw, "failed to add new pvid %u, ret = %d", 846 new_pvid, ret); 847 return ret; 848 } 849 } else { 850 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 851 if (ret) { 852 hns3_err(hw, "failed to remove pvid %u, ret = %d", 853 new_pvid, ret); 854 return ret; 855 } 856 857 hns3_add_all_vlan_table(hns); 858 } 859 return 0; 860 } 861 862 static int 863 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 864 { 865 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 866 struct hns3_rx_vtag_cfg rx_vlan_cfg; 867 bool rx_strip_en; 868 int ret; 869 870 rx_strip_en = old_cfg->rx_vlan_offload_en; 871 if (on) { 872 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 873 rx_vlan_cfg.strip_tag2_en = true; 874 rx_vlan_cfg.strip_tag2_discard_en = true; 875 } else { 876 rx_vlan_cfg.strip_tag1_en = false; 877 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 878 rx_vlan_cfg.strip_tag2_discard_en = false; 879 } 880 rx_vlan_cfg.strip_tag1_discard_en = false; 881 rx_vlan_cfg.vlan1_vlan_prionly = false; 882 rx_vlan_cfg.vlan2_vlan_prionly = false; 883 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 884 885 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 886 if (ret) 887 return ret; 888 889 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 890 return ret; 891 } 892 893 static int 894 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 895 { 896 struct hns3_hw *hw = &hns->hw; 897 uint16_t port_base_vlan_state; 898 int ret; 899 900 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 901 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) 902 hns3_warn(hw, "Invalid operation! As current pvid set " 903 "is %u, disable pvid %u is invalid", 904 hw->port_base_vlan_cfg.pvid, pvid); 905 return 0; 906 } 907 908 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 909 HNS3_PORT_BASE_VLAN_DISABLE; 910 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 911 if (ret) { 912 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 913 ret); 914 return ret; 915 } 916 917 ret = hns3_en_pvid_strip(hns, on); 918 if (ret) { 919 hns3_err(hw, "failed to config rx vlan strip for pvid, " 920 "ret = %d", ret); 921 return ret; 922 } 923 924 if (pvid == HNS3_INVALID_PVID) 925 goto out; 926 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid); 927 if (ret) { 928 hns3_err(hw, "failed to update vlan filter entries, ret = %d", 929 ret); 930 return ret; 931 } 932 933 out: 934 hw->port_base_vlan_cfg.state = port_base_vlan_state; 935 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID; 936 return ret; 937 } 938 939 static int 940 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 941 { 942 struct hns3_adapter *hns = dev->data->dev_private; 943 struct hns3_hw *hw = &hns->hw; 944 bool pvid_en_state_change; 945 uint16_t pvid_state; 946 int ret; 947 948 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 949 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 950 RTE_ETHER_MAX_VLAN_ID); 951 return -EINVAL; 952 } 953 954 /* 955 * If PVID configuration state change, should refresh the PVID 956 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 957 */ 958 pvid_state = hw->port_base_vlan_cfg.state; 959 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 960 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 961 pvid_en_state_change = false; 962 else 963 pvid_en_state_change = true; 964 965 rte_spinlock_lock(&hw->lock); 966 ret = hns3_vlan_pvid_configure(hns, pvid, on); 967 rte_spinlock_unlock(&hw->lock); 968 if (ret) 969 return ret; 970 /* 971 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx 972 * need be processed by PMD driver. 973 */ 974 if (pvid_en_state_change && 975 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 976 hns3_update_all_queues_pvid_proc_en(hw); 977 978 return 0; 979 } 980 981 static int 982 hns3_default_vlan_config(struct hns3_adapter *hns) 983 { 984 struct hns3_hw *hw = &hns->hw; 985 int ret; 986 987 /* 988 * When vlan filter is enabled, hardware regards packets without vlan 989 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan 990 * table, packets without vlan won't be received. So, add vlan 0 as 991 * the default vlan. 992 */ 993 ret = hns3_vlan_filter_configure(hns, 0, 1); 994 if (ret) 995 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 996 return ret; 997 } 998 999 static int 1000 hns3_init_vlan_config(struct hns3_adapter *hns) 1001 { 1002 struct hns3_hw *hw = &hns->hw; 1003 int ret; 1004 1005 /* 1006 * This function can be called in the initialization and reset process, 1007 * when in reset process, it means that hardware had been reseted 1008 * successfully and we need to restore the hardware configuration to 1009 * ensure that the hardware configuration remains unchanged before and 1010 * after reset. 1011 */ 1012 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 1013 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 1014 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID; 1015 } 1016 1017 ret = hns3_vlan_filter_init(hns); 1018 if (ret) { 1019 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 1020 return ret; 1021 } 1022 1023 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 1024 RTE_ETHER_TYPE_VLAN); 1025 if (ret) { 1026 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 1027 return ret; 1028 } 1029 1030 /* 1031 * When in the reinit dev stage of the reset process, the following 1032 * vlan-related configurations may differ from those at initialization, 1033 * we will restore configurations to hardware in hns3_restore_vlan_table 1034 * and hns3_restore_vlan_conf later. 1035 */ 1036 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 1037 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0); 1038 if (ret) { 1039 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1040 return ret; 1041 } 1042 1043 ret = hns3_en_hw_strip_rxvtag(hns, false); 1044 if (ret) { 1045 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1046 ret); 1047 return ret; 1048 } 1049 } 1050 1051 return hns3_default_vlan_config(hns); 1052 } 1053 1054 static int 1055 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1056 { 1057 struct hns3_pf *pf = &hns->pf; 1058 struct hns3_hw *hw = &hns->hw; 1059 uint64_t offloads; 1060 bool enable; 1061 int ret; 1062 1063 if (!hw->data->promiscuous) { 1064 /* restore vlan filter states */ 1065 offloads = hw->data->dev_conf.rxmode.offloads; 1066 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false; 1067 ret = hns3_enable_vlan_filter(hns, enable); 1068 if (ret) { 1069 hns3_err(hw, "failed to restore vlan rx filter conf, " 1070 "ret = %d", ret); 1071 return ret; 1072 } 1073 } 1074 1075 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1076 if (ret) { 1077 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1078 return ret; 1079 } 1080 1081 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1082 if (ret) 1083 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1084 1085 return ret; 1086 } 1087 1088 static int 1089 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1090 { 1091 struct hns3_adapter *hns = dev->data->dev_private; 1092 struct rte_eth_dev_data *data = dev->data; 1093 struct rte_eth_txmode *txmode; 1094 struct hns3_hw *hw = &hns->hw; 1095 int mask; 1096 int ret; 1097 1098 txmode = &data->dev_conf.txmode; 1099 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1100 hns3_warn(hw, 1101 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1102 "configuration is not supported! Ignore these two " 1103 "parameters: hw_vlan_reject_tagged(%d), " 1104 "hw_vlan_reject_untagged(%d)", 1105 txmode->hw_vlan_reject_tagged, 1106 txmode->hw_vlan_reject_untagged); 1107 1108 /* Apply vlan offload setting */ 1109 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK; 1110 ret = hns3_vlan_offload_set(dev, mask); 1111 if (ret) { 1112 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1113 ret); 1114 return ret; 1115 } 1116 1117 /* 1118 * If pvid config is not set in rte_eth_conf, driver needn't to set 1119 * VLAN pvid related configuration to hardware. 1120 */ 1121 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1122 return 0; 1123 1124 /* Apply pvid setting */ 1125 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1126 txmode->hw_vlan_insert_pvid); 1127 if (ret) 1128 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d", 1129 txmode->pvid, ret); 1130 1131 return ret; 1132 } 1133 1134 static int 1135 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1136 unsigned int tso_mss_max) 1137 { 1138 struct hns3_cfg_tso_status_cmd *req; 1139 struct hns3_cmd_desc desc; 1140 uint16_t tso_mss; 1141 1142 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1143 1144 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1145 1146 tso_mss = 0; 1147 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1148 tso_mss_min); 1149 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1150 1151 tso_mss = 0; 1152 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1153 tso_mss_max); 1154 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1155 1156 return hns3_cmd_send(hw, &desc, 1); 1157 } 1158 1159 static int 1160 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1161 uint16_t *allocated_size, bool is_alloc) 1162 { 1163 struct hns3_umv_spc_alc_cmd *req; 1164 struct hns3_cmd_desc desc; 1165 int ret; 1166 1167 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1168 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1169 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1170 req->space_size = rte_cpu_to_le_32(space_size); 1171 1172 ret = hns3_cmd_send(hw, &desc, 1); 1173 if (ret) { 1174 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1175 is_alloc ? "allocate" : "free", ret); 1176 return ret; 1177 } 1178 1179 if (is_alloc && allocated_size) 1180 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1181 1182 return 0; 1183 } 1184 1185 static int 1186 hns3_init_umv_space(struct hns3_hw *hw) 1187 { 1188 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1189 struct hns3_pf *pf = &hns->pf; 1190 uint16_t allocated_size = 0; 1191 int ret; 1192 1193 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1194 true); 1195 if (ret) 1196 return ret; 1197 1198 if (allocated_size < pf->wanted_umv_size) 1199 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1200 pf->wanted_umv_size, allocated_size); 1201 1202 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1203 pf->wanted_umv_size; 1204 pf->used_umv_size = 0; 1205 return 0; 1206 } 1207 1208 static int 1209 hns3_uninit_umv_space(struct hns3_hw *hw) 1210 { 1211 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1212 struct hns3_pf *pf = &hns->pf; 1213 int ret; 1214 1215 if (pf->max_umv_size == 0) 1216 return 0; 1217 1218 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1219 if (ret) 1220 return ret; 1221 1222 pf->max_umv_size = 0; 1223 1224 return 0; 1225 } 1226 1227 static bool 1228 hns3_is_umv_space_full(struct hns3_hw *hw) 1229 { 1230 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1231 struct hns3_pf *pf = &hns->pf; 1232 bool is_full; 1233 1234 is_full = (pf->used_umv_size >= pf->max_umv_size); 1235 1236 return is_full; 1237 } 1238 1239 static void 1240 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1241 { 1242 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1243 struct hns3_pf *pf = &hns->pf; 1244 1245 if (is_free) { 1246 if (pf->used_umv_size > 0) 1247 pf->used_umv_size--; 1248 } else 1249 pf->used_umv_size++; 1250 } 1251 1252 static void 1253 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1254 const uint8_t *addr, bool is_mc) 1255 { 1256 const unsigned char *mac_addr = addr; 1257 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1258 ((uint32_t)mac_addr[2] << 16) | 1259 ((uint32_t)mac_addr[1] << 8) | 1260 (uint32_t)mac_addr[0]; 1261 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1262 1263 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1264 if (is_mc) { 1265 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1266 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1267 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1268 } 1269 1270 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1271 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1272 } 1273 1274 static int 1275 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1276 uint8_t resp_code, 1277 enum hns3_mac_vlan_tbl_opcode op) 1278 { 1279 if (cmdq_resp) { 1280 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1281 cmdq_resp); 1282 return -EIO; 1283 } 1284 1285 if (op == HNS3_MAC_VLAN_ADD) { 1286 if (resp_code == 0 || resp_code == 1) { 1287 return 0; 1288 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1289 hns3_err(hw, "add mac addr failed for uc_overflow"); 1290 return -ENOSPC; 1291 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1292 hns3_err(hw, "add mac addr failed for mc_overflow"); 1293 return -ENOSPC; 1294 } 1295 1296 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1297 resp_code); 1298 return -EIO; 1299 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1300 if (resp_code == 0) { 1301 return 0; 1302 } else if (resp_code == 1) { 1303 hns3_dbg(hw, "remove mac addr failed for miss"); 1304 return -ENOENT; 1305 } 1306 1307 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1308 resp_code); 1309 return -EIO; 1310 } else if (op == HNS3_MAC_VLAN_LKUP) { 1311 if (resp_code == 0) { 1312 return 0; 1313 } else if (resp_code == 1) { 1314 hns3_dbg(hw, "lookup mac addr failed for miss"); 1315 return -ENOENT; 1316 } 1317 1318 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1319 resp_code); 1320 return -EIO; 1321 } 1322 1323 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1324 op); 1325 1326 return -EINVAL; 1327 } 1328 1329 static int 1330 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1331 struct hns3_mac_vlan_tbl_entry_cmd *req, 1332 struct hns3_cmd_desc *desc, bool is_mc) 1333 { 1334 uint8_t resp_code; 1335 uint16_t retval; 1336 int ret; 1337 1338 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true); 1339 if (is_mc) { 1340 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1341 memcpy(desc[0].data, req, 1342 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1343 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD, 1344 true); 1345 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1346 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD, 1347 true); 1348 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1349 } else { 1350 memcpy(desc[0].data, req, 1351 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1352 ret = hns3_cmd_send(hw, desc, 1); 1353 } 1354 if (ret) { 1355 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1356 ret); 1357 return ret; 1358 } 1359 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1360 retval = rte_le_to_cpu_16(desc[0].retval); 1361 1362 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1363 HNS3_MAC_VLAN_LKUP); 1364 } 1365 1366 static int 1367 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1368 struct hns3_mac_vlan_tbl_entry_cmd *req, 1369 struct hns3_cmd_desc *mc_desc) 1370 { 1371 uint8_t resp_code; 1372 uint16_t retval; 1373 int cfg_status; 1374 int ret; 1375 1376 if (mc_desc == NULL) { 1377 struct hns3_cmd_desc desc; 1378 1379 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false); 1380 memcpy(desc.data, req, 1381 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1382 ret = hns3_cmd_send(hw, &desc, 1); 1383 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1384 retval = rte_le_to_cpu_16(desc.retval); 1385 1386 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1387 HNS3_MAC_VLAN_ADD); 1388 } else { 1389 hns3_cmd_reuse_desc(&mc_desc[0], false); 1390 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1391 hns3_cmd_reuse_desc(&mc_desc[1], false); 1392 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1393 hns3_cmd_reuse_desc(&mc_desc[2], false); 1394 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1395 memcpy(mc_desc[0].data, req, 1396 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1397 mc_desc[0].retval = 0; 1398 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1399 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff; 1400 retval = rte_le_to_cpu_16(mc_desc[0].retval); 1401 1402 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1403 HNS3_MAC_VLAN_ADD); 1404 } 1405 1406 if (ret) { 1407 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1408 return ret; 1409 } 1410 1411 return cfg_status; 1412 } 1413 1414 static int 1415 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1416 struct hns3_mac_vlan_tbl_entry_cmd *req) 1417 { 1418 struct hns3_cmd_desc desc; 1419 uint8_t resp_code; 1420 uint16_t retval; 1421 int ret; 1422 1423 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1424 1425 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1426 1427 ret = hns3_cmd_send(hw, &desc, 1); 1428 if (ret) { 1429 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1430 return ret; 1431 } 1432 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1433 retval = rte_le_to_cpu_16(desc.retval); 1434 1435 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1436 HNS3_MAC_VLAN_REMOVE); 1437 } 1438 1439 static int 1440 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1441 { 1442 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1443 struct hns3_mac_vlan_tbl_entry_cmd req; 1444 struct hns3_pf *pf = &hns->pf; 1445 struct hns3_cmd_desc desc[3]; 1446 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1447 uint16_t egress_port = 0; 1448 uint8_t vf_id; 1449 int ret; 1450 1451 /* check if mac addr is valid */ 1452 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1453 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1454 mac_addr); 1455 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1456 mac_str); 1457 return -EINVAL; 1458 } 1459 1460 memset(&req, 0, sizeof(req)); 1461 1462 /* 1463 * In current version VF is not supported when PF is driven by DPDK 1464 * driver, just need to configure parameters for PF vport. 1465 */ 1466 vf_id = HNS3_PF_FUNC_ID; 1467 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1468 HNS3_MAC_EPORT_VFID_S, vf_id); 1469 1470 req.egress_port = rte_cpu_to_le_16(egress_port); 1471 1472 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1473 1474 /* 1475 * Lookup the mac address in the mac_vlan table, and add 1476 * it if the entry is inexistent. Repeated unicast entry 1477 * is not allowed in the mac vlan table. 1478 */ 1479 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false); 1480 if (ret == -ENOENT) { 1481 if (!hns3_is_umv_space_full(hw)) { 1482 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); 1483 if (!ret) 1484 hns3_update_umv_space(hw, false); 1485 return ret; 1486 } 1487 1488 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1489 1490 return -ENOSPC; 1491 } 1492 1493 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1494 1495 /* check if we just hit the duplicate */ 1496 if (ret == 0) { 1497 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1498 return 0; 1499 } 1500 1501 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1502 mac_str); 1503 1504 return ret; 1505 } 1506 1507 static int 1508 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1509 { 1510 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1511 struct rte_ether_addr *addr; 1512 int ret; 1513 int i; 1514 1515 for (i = 0; i < hw->mc_addrs_num; i++) { 1516 addr = &hw->mc_addrs[i]; 1517 /* Check if there are duplicate addresses */ 1518 if (rte_is_same_ether_addr(addr, mac_addr)) { 1519 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1520 addr); 1521 hns3_err(hw, "failed to add mc mac addr, same addrs" 1522 "(%s) is added by the set_mc_mac_addr_list " 1523 "API", mac_str); 1524 return -EINVAL; 1525 } 1526 } 1527 1528 ret = hns3_add_mc_addr(hw, mac_addr); 1529 if (ret) { 1530 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1531 mac_addr); 1532 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 1533 mac_str, ret); 1534 } 1535 return ret; 1536 } 1537 1538 static int 1539 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1540 { 1541 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1542 int ret; 1543 1544 ret = hns3_remove_mc_addr(hw, mac_addr); 1545 if (ret) { 1546 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1547 mac_addr); 1548 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d", 1549 mac_str, ret); 1550 } 1551 return ret; 1552 } 1553 1554 static int 1555 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1556 uint32_t idx, __rte_unused uint32_t pool) 1557 { 1558 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1559 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1560 int ret; 1561 1562 rte_spinlock_lock(&hw->lock); 1563 1564 /* 1565 * In hns3 network engine adding UC and MC mac address with different 1566 * commands with firmware. We need to determine whether the input 1567 * address is a UC or a MC address to call different commands. 1568 * By the way, it is recommended calling the API function named 1569 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 1570 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 1571 * may affect the specifications of UC mac addresses. 1572 */ 1573 if (rte_is_multicast_ether_addr(mac_addr)) 1574 ret = hns3_add_mc_addr_common(hw, mac_addr); 1575 else 1576 ret = hns3_add_uc_addr_common(hw, mac_addr); 1577 1578 if (ret) { 1579 rte_spinlock_unlock(&hw->lock); 1580 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1581 mac_addr); 1582 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 1583 ret); 1584 return ret; 1585 } 1586 1587 if (idx == 0) 1588 hw->mac.default_addr_setted = true; 1589 rte_spinlock_unlock(&hw->lock); 1590 1591 return ret; 1592 } 1593 1594 static int 1595 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1596 { 1597 struct hns3_mac_vlan_tbl_entry_cmd req; 1598 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1599 int ret; 1600 1601 /* check if mac addr is valid */ 1602 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1603 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1604 mac_addr); 1605 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1606 mac_str); 1607 return -EINVAL; 1608 } 1609 1610 memset(&req, 0, sizeof(req)); 1611 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1612 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1613 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1614 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1615 return 0; 1616 else if (ret == 0) 1617 hns3_update_umv_space(hw, true); 1618 1619 return ret; 1620 } 1621 1622 static void 1623 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1624 { 1625 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1626 /* index will be checked by upper level rte interface */ 1627 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1628 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1629 int ret; 1630 1631 rte_spinlock_lock(&hw->lock); 1632 1633 if (rte_is_multicast_ether_addr(mac_addr)) 1634 ret = hns3_remove_mc_addr_common(hw, mac_addr); 1635 else 1636 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1637 rte_spinlock_unlock(&hw->lock); 1638 if (ret) { 1639 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1640 mac_addr); 1641 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, 1642 ret); 1643 } 1644 } 1645 1646 static int 1647 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1648 struct rte_ether_addr *mac_addr) 1649 { 1650 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1651 struct rte_ether_addr *oaddr; 1652 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1653 bool default_addr_setted; 1654 bool rm_succes = false; 1655 int ret, ret_val; 1656 1657 /* 1658 * It has been guaranteed that input parameter named mac_addr is valid 1659 * address in the rte layer of DPDK framework. 1660 */ 1661 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1662 default_addr_setted = hw->mac.default_addr_setted; 1663 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr)) 1664 return 0; 1665 1666 rte_spinlock_lock(&hw->lock); 1667 if (default_addr_setted) { 1668 ret = hns3_remove_uc_addr_common(hw, oaddr); 1669 if (ret) { 1670 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1671 oaddr); 1672 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1673 mac_str, ret); 1674 rm_succes = false; 1675 } else 1676 rm_succes = true; 1677 } 1678 1679 ret = hns3_add_uc_addr_common(hw, mac_addr); 1680 if (ret) { 1681 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1682 mac_addr); 1683 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1684 goto err_add_uc_addr; 1685 } 1686 1687 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1688 if (ret) { 1689 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1690 goto err_pause_addr_cfg; 1691 } 1692 1693 rte_ether_addr_copy(mac_addr, 1694 (struct rte_ether_addr *)hw->mac.mac_addr); 1695 hw->mac.default_addr_setted = true; 1696 rte_spinlock_unlock(&hw->lock); 1697 1698 return 0; 1699 1700 err_pause_addr_cfg: 1701 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1702 if (ret_val) { 1703 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1704 mac_addr); 1705 hns3_warn(hw, 1706 "Failed to roll back to del setted mac addr(%s): %d", 1707 mac_str, ret_val); 1708 } 1709 1710 err_add_uc_addr: 1711 if (rm_succes) { 1712 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1713 if (ret_val) { 1714 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1715 oaddr); 1716 hns3_warn(hw, 1717 "Failed to restore old uc mac addr(%s): %d", 1718 mac_str, ret_val); 1719 hw->mac.default_addr_setted = false; 1720 } 1721 } 1722 rte_spinlock_unlock(&hw->lock); 1723 1724 return ret; 1725 } 1726 1727 static int 1728 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1729 { 1730 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1731 struct hns3_hw *hw = &hns->hw; 1732 struct rte_ether_addr *addr; 1733 int err = 0; 1734 int ret; 1735 int i; 1736 1737 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1738 addr = &hw->data->mac_addrs[i]; 1739 if (rte_is_zero_ether_addr(addr)) 1740 continue; 1741 if (rte_is_multicast_ether_addr(addr)) 1742 ret = del ? hns3_remove_mc_addr(hw, addr) : 1743 hns3_add_mc_addr(hw, addr); 1744 else 1745 ret = del ? hns3_remove_uc_addr_common(hw, addr) : 1746 hns3_add_uc_addr_common(hw, addr); 1747 1748 if (ret) { 1749 err = ret; 1750 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1751 addr); 1752 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 1753 "ret = %d.", del ? "remove" : "restore", 1754 mac_str, i, ret); 1755 } 1756 } 1757 return err; 1758 } 1759 1760 static void 1761 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1762 { 1763 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1764 uint8_t word_num; 1765 uint8_t bit_num; 1766 1767 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1768 word_num = vfid / 32; 1769 bit_num = vfid % 32; 1770 if (clr) 1771 desc[1].data[word_num] &= 1772 rte_cpu_to_le_32(~(1UL << bit_num)); 1773 else 1774 desc[1].data[word_num] |= 1775 rte_cpu_to_le_32(1UL << bit_num); 1776 } else { 1777 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1778 bit_num = vfid % 32; 1779 if (clr) 1780 desc[2].data[word_num] &= 1781 rte_cpu_to_le_32(~(1UL << bit_num)); 1782 else 1783 desc[2].data[word_num] |= 1784 rte_cpu_to_le_32(1UL << bit_num); 1785 } 1786 } 1787 1788 static int 1789 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1790 { 1791 struct hns3_mac_vlan_tbl_entry_cmd req; 1792 struct hns3_cmd_desc desc[3]; 1793 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1794 uint8_t vf_id; 1795 int ret; 1796 1797 /* Check if mac addr is valid */ 1798 if (!rte_is_multicast_ether_addr(mac_addr)) { 1799 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1800 mac_addr); 1801 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1802 mac_str); 1803 return -EINVAL; 1804 } 1805 1806 memset(&req, 0, sizeof(req)); 1807 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1808 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1809 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1810 if (ret) { 1811 /* This mac addr do not exist, add new entry for it */ 1812 memset(desc[0].data, 0, sizeof(desc[0].data)); 1813 memset(desc[1].data, 0, sizeof(desc[0].data)); 1814 memset(desc[2].data, 0, sizeof(desc[0].data)); 1815 } 1816 1817 /* 1818 * In current version VF is not supported when PF is driven by DPDK 1819 * driver, just need to configure parameters for PF vport. 1820 */ 1821 vf_id = HNS3_PF_FUNC_ID; 1822 hns3_update_desc_vfid(desc, vf_id, false); 1823 ret = hns3_add_mac_vlan_tbl(hw, &req, desc); 1824 if (ret) { 1825 if (ret == -ENOSPC) 1826 hns3_err(hw, "mc mac vlan table is full"); 1827 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1828 mac_addr); 1829 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1830 } 1831 1832 return ret; 1833 } 1834 1835 static int 1836 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1837 { 1838 struct hns3_mac_vlan_tbl_entry_cmd req; 1839 struct hns3_cmd_desc desc[3]; 1840 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1841 uint8_t vf_id; 1842 int ret; 1843 1844 /* Check if mac addr is valid */ 1845 if (!rte_is_multicast_ether_addr(mac_addr)) { 1846 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1847 mac_addr); 1848 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1849 mac_str); 1850 return -EINVAL; 1851 } 1852 1853 memset(&req, 0, sizeof(req)); 1854 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1855 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1856 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1857 if (ret == 0) { 1858 /* 1859 * This mac addr exist, remove this handle's VFID for it. 1860 * In current version VF is not supported when PF is driven by 1861 * DPDK driver, just need to configure parameters for PF vport. 1862 */ 1863 vf_id = HNS3_PF_FUNC_ID; 1864 hns3_update_desc_vfid(desc, vf_id, true); 1865 1866 /* All the vfid is zero, so need to delete this entry */ 1867 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1868 } else if (ret == -ENOENT) { 1869 /* This mac addr doesn't exist. */ 1870 return 0; 1871 } 1872 1873 if (ret) { 1874 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1875 mac_addr); 1876 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1877 } 1878 1879 return ret; 1880 } 1881 1882 static int 1883 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1884 struct rte_ether_addr *mc_addr_set, 1885 uint32_t nb_mc_addr) 1886 { 1887 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1888 struct rte_ether_addr *addr; 1889 uint32_t i; 1890 uint32_t j; 1891 1892 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1893 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) " 1894 "invalid. valid range: 0~%d", 1895 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1896 return -EINVAL; 1897 } 1898 1899 /* Check if input mac addresses are valid */ 1900 for (i = 0; i < nb_mc_addr; i++) { 1901 addr = &mc_addr_set[i]; 1902 if (!rte_is_multicast_ether_addr(addr)) { 1903 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1904 addr); 1905 hns3_err(hw, 1906 "failed to set mc mac addr, addr(%s) invalid.", 1907 mac_str); 1908 return -EINVAL; 1909 } 1910 1911 /* Check if there are duplicate addresses */ 1912 for (j = i + 1; j < nb_mc_addr; j++) { 1913 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1914 rte_ether_format_addr(mac_str, 1915 RTE_ETHER_ADDR_FMT_SIZE, 1916 addr); 1917 hns3_err(hw, "failed to set mc mac addr, " 1918 "addrs invalid. two same addrs(%s).", 1919 mac_str); 1920 return -EINVAL; 1921 } 1922 } 1923 1924 /* 1925 * Check if there are duplicate addresses between mac_addrs 1926 * and mc_addr_set 1927 */ 1928 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) { 1929 if (rte_is_same_ether_addr(addr, 1930 &hw->data->mac_addrs[j])) { 1931 rte_ether_format_addr(mac_str, 1932 RTE_ETHER_ADDR_FMT_SIZE, 1933 addr); 1934 hns3_err(hw, "failed to set mc mac addr, " 1935 "addrs invalid. addrs(%s) has already " 1936 "configured in mac_addr add API", 1937 mac_str); 1938 return -EINVAL; 1939 } 1940 } 1941 } 1942 1943 return 0; 1944 } 1945 1946 static void 1947 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 1948 struct rte_ether_addr *mc_addr_set, 1949 int mc_addr_num, 1950 struct rte_ether_addr *reserved_addr_list, 1951 int *reserved_addr_num, 1952 struct rte_ether_addr *add_addr_list, 1953 int *add_addr_num, 1954 struct rte_ether_addr *rm_addr_list, 1955 int *rm_addr_num) 1956 { 1957 struct rte_ether_addr *addr; 1958 int current_addr_num; 1959 int reserved_num = 0; 1960 int add_num = 0; 1961 int rm_num = 0; 1962 int num; 1963 int i; 1964 int j; 1965 bool same_addr; 1966 1967 /* Calculate the mc mac address list that should be removed */ 1968 current_addr_num = hw->mc_addrs_num; 1969 for (i = 0; i < current_addr_num; i++) { 1970 addr = &hw->mc_addrs[i]; 1971 same_addr = false; 1972 for (j = 0; j < mc_addr_num; j++) { 1973 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1974 same_addr = true; 1975 break; 1976 } 1977 } 1978 1979 if (!same_addr) { 1980 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 1981 rm_num++; 1982 } else { 1983 rte_ether_addr_copy(addr, 1984 &reserved_addr_list[reserved_num]); 1985 reserved_num++; 1986 } 1987 } 1988 1989 /* Calculate the mc mac address list that should be added */ 1990 for (i = 0; i < mc_addr_num; i++) { 1991 addr = &mc_addr_set[i]; 1992 same_addr = false; 1993 for (j = 0; j < current_addr_num; j++) { 1994 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 1995 same_addr = true; 1996 break; 1997 } 1998 } 1999 2000 if (!same_addr) { 2001 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 2002 add_num++; 2003 } 2004 } 2005 2006 /* Reorder the mc mac address list maintained by driver */ 2007 for (i = 0; i < reserved_num; i++) 2008 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 2009 2010 for (i = 0; i < rm_num; i++) { 2011 num = reserved_num + i; 2012 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 2013 } 2014 2015 *reserved_addr_num = reserved_num; 2016 *add_addr_num = add_num; 2017 *rm_addr_num = rm_num; 2018 } 2019 2020 static int 2021 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 2022 struct rte_ether_addr *mc_addr_set, 2023 uint32_t nb_mc_addr) 2024 { 2025 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2026 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 2027 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 2028 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 2029 struct rte_ether_addr *addr; 2030 int reserved_addr_num; 2031 int add_addr_num; 2032 int rm_addr_num; 2033 int mc_addr_num; 2034 int num; 2035 int ret; 2036 int i; 2037 2038 /* Check if input parameters are valid */ 2039 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 2040 if (ret) 2041 return ret; 2042 2043 rte_spinlock_lock(&hw->lock); 2044 2045 /* 2046 * Calculate the mc mac address lists those should be removed and be 2047 * added, Reorder the mc mac address list maintained by driver. 2048 */ 2049 mc_addr_num = (int)nb_mc_addr; 2050 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 2051 reserved_addr_list, &reserved_addr_num, 2052 add_addr_list, &add_addr_num, 2053 rm_addr_list, &rm_addr_num); 2054 2055 /* Remove mc mac addresses */ 2056 for (i = 0; i < rm_addr_num; i++) { 2057 num = rm_addr_num - i - 1; 2058 addr = &rm_addr_list[num]; 2059 ret = hns3_remove_mc_addr(hw, addr); 2060 if (ret) { 2061 rte_spinlock_unlock(&hw->lock); 2062 return ret; 2063 } 2064 hw->mc_addrs_num--; 2065 } 2066 2067 /* Add mc mac addresses */ 2068 for (i = 0; i < add_addr_num; i++) { 2069 addr = &add_addr_list[i]; 2070 ret = hns3_add_mc_addr(hw, addr); 2071 if (ret) { 2072 rte_spinlock_unlock(&hw->lock); 2073 return ret; 2074 } 2075 2076 num = reserved_addr_num + i; 2077 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 2078 hw->mc_addrs_num++; 2079 } 2080 rte_spinlock_unlock(&hw->lock); 2081 2082 return 0; 2083 } 2084 2085 static int 2086 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 2087 { 2088 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2089 struct hns3_hw *hw = &hns->hw; 2090 struct rte_ether_addr *addr; 2091 int err = 0; 2092 int ret; 2093 int i; 2094 2095 for (i = 0; i < hw->mc_addrs_num; i++) { 2096 addr = &hw->mc_addrs[i]; 2097 if (!rte_is_multicast_ether_addr(addr)) 2098 continue; 2099 if (del) 2100 ret = hns3_remove_mc_addr(hw, addr); 2101 else 2102 ret = hns3_add_mc_addr(hw, addr); 2103 if (ret) { 2104 err = ret; 2105 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2106 addr); 2107 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d", 2108 del ? "Remove" : "Restore", mac_str, ret); 2109 } 2110 } 2111 return err; 2112 } 2113 2114 static int 2115 hns3_check_mq_mode(struct rte_eth_dev *dev) 2116 { 2117 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 2118 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 2119 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2120 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2121 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 2122 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 2123 uint8_t num_tc; 2124 int max_tc = 0; 2125 int i; 2126 2127 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 2128 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 2129 2130 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2131 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. " 2132 "rx_mq_mode = %d", rx_mq_mode); 2133 return -EINVAL; 2134 } 2135 2136 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB || 2137 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2138 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB " 2139 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d", 2140 rx_mq_mode, tx_mq_mode); 2141 return -EINVAL; 2142 } 2143 2144 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) { 2145 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 2146 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 2147 dcb_rx_conf->nb_tcs, pf->tc_max); 2148 return -EINVAL; 2149 } 2150 2151 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 2152 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 2153 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 2154 "nb_tcs(%d) != %d or %d in rx direction.", 2155 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 2156 return -EINVAL; 2157 } 2158 2159 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 2160 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 2161 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 2162 return -EINVAL; 2163 } 2164 2165 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 2166 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 2167 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, " 2168 "is not equal to one in tx direction.", 2169 i, dcb_rx_conf->dcb_tc[i]); 2170 return -EINVAL; 2171 } 2172 if (dcb_rx_conf->dcb_tc[i] > max_tc) 2173 max_tc = dcb_rx_conf->dcb_tc[i]; 2174 } 2175 2176 num_tc = max_tc + 1; 2177 if (num_tc > dcb_rx_conf->nb_tcs) { 2178 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 2179 num_tc, dcb_rx_conf->nb_tcs); 2180 return -EINVAL; 2181 } 2182 } 2183 2184 return 0; 2185 } 2186 2187 static int 2188 hns3_check_dcb_cfg(struct rte_eth_dev *dev) 2189 { 2190 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2191 2192 if (!hns3_dev_dcb_supported(hw)) { 2193 hns3_err(hw, "this port does not support dcb configurations."); 2194 return -EOPNOTSUPP; 2195 } 2196 2197 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2198 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2199 return -EOPNOTSUPP; 2200 } 2201 2202 /* Check multiple queue mode */ 2203 return hns3_check_mq_mode(dev); 2204 } 2205 2206 static int 2207 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap, 2208 enum hns3_ring_type queue_type, uint16_t queue_id) 2209 { 2210 struct hns3_cmd_desc desc; 2211 struct hns3_ctrl_vector_chain_cmd *req = 2212 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 2213 enum hns3_cmd_status status; 2214 enum hns3_opcode_type op; 2215 uint16_t tqp_type_and_id = 0; 2216 const char *op_str; 2217 uint16_t type; 2218 uint16_t gl; 2219 2220 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 2221 hns3_cmd_setup_basic_desc(&desc, op, false); 2222 req->int_vector_id = vector_id; 2223 2224 if (queue_type == HNS3_RING_TYPE_RX) 2225 gl = HNS3_RING_GL_RX; 2226 else 2227 gl = HNS3_RING_GL_TX; 2228 2229 type = queue_type; 2230 2231 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 2232 type); 2233 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 2234 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 2235 gl); 2236 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 2237 req->int_cause_num = 1; 2238 op_str = mmap ? "Map" : "Unmap"; 2239 status = hns3_cmd_send(hw, &desc, 1); 2240 if (status) { 2241 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.", 2242 op_str, queue_id, req->int_vector_id, status); 2243 return status; 2244 } 2245 2246 return 0; 2247 } 2248 2249 static int 2250 hns3_init_ring_with_vector(struct hns3_hw *hw) 2251 { 2252 uint16_t vec; 2253 int ret; 2254 int i; 2255 2256 /* 2257 * In hns3 network engine, vector 0 is always the misc interrupt of this 2258 * function, vector 1~N can be used respectively for the queues of the 2259 * function. Tx and Rx queues with the same number share the interrupt 2260 * vector. In the initialization clearing the all hardware mapping 2261 * relationship configurations between queues and interrupt vectors is 2262 * needed, so some error caused by the residual configurations, such as 2263 * the unexpected Tx interrupt, can be avoid. 2264 */ 2265 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 2266 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 2267 vec = vec - 1; /* the last interrupt is reserved */ 2268 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 2269 for (i = 0; i < hw->intr_tqps_num; i++) { 2270 /* 2271 * Set gap limiter/rate limiter/quanity limiter algorithm 2272 * configuration for interrupt coalesce of queue's interrupt. 2273 */ 2274 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 2275 HNS3_TQP_INTR_GL_DEFAULT); 2276 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 2277 HNS3_TQP_INTR_GL_DEFAULT); 2278 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 2279 /* 2280 * QL(quantity limiter) is not used currently, just set 0 to 2281 * close it. 2282 */ 2283 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 2284 2285 ret = hns3_bind_ring_with_vector(hw, vec, false, 2286 HNS3_RING_TYPE_TX, i); 2287 if (ret) { 2288 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " 2289 "vector: %d, ret=%d", i, vec, ret); 2290 return ret; 2291 } 2292 2293 ret = hns3_bind_ring_with_vector(hw, vec, false, 2294 HNS3_RING_TYPE_RX, i); 2295 if (ret) { 2296 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " 2297 "vector: %d, ret=%d", i, vec, ret); 2298 return ret; 2299 } 2300 } 2301 2302 return 0; 2303 } 2304 2305 static int 2306 hns3_dev_configure(struct rte_eth_dev *dev) 2307 { 2308 struct hns3_adapter *hns = dev->data->dev_private; 2309 struct rte_eth_conf *conf = &dev->data->dev_conf; 2310 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2311 struct hns3_hw *hw = &hns->hw; 2312 struct hns3_rss_conf *rss_cfg = &hw->rss_info; 2313 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2314 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2315 struct rte_eth_rss_conf rss_conf; 2316 uint16_t mtu; 2317 bool gro_en; 2318 int ret; 2319 2320 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 2321 2322 /* 2323 * Some versions of hardware network engine does not support 2324 * individually enable/disable/reset the Tx or Rx queue. These devices 2325 * must enable/disable/reset Tx and Rx queues at the same time. When the 2326 * numbers of Tx queues allocated by upper applications are not equal to 2327 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 2328 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 2329 * work as usual. But these fake queues are imperceptible, and can not 2330 * be used by upper applications. 2331 */ 2332 if (!hns3_dev_indep_txrx_supported(hw)) { 2333 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2334 if (ret) { 2335 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", 2336 ret); 2337 return ret; 2338 } 2339 } 2340 2341 hw->adapter_state = HNS3_NIC_CONFIGURING; 2342 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 2343 hns3_err(hw, "setting link speed/duplex not supported"); 2344 ret = -EINVAL; 2345 goto cfg_err; 2346 } 2347 2348 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2349 ret = hns3_check_dcb_cfg(dev); 2350 if (ret) 2351 goto cfg_err; 2352 } 2353 2354 /* When RSS is not configured, redirect the packet queue 0 */ 2355 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2356 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2357 rss_conf = conf->rx_adv_conf.rss_conf; 2358 hw->rss_dis_flag = false; 2359 if (rss_conf.rss_key == NULL) { 2360 rss_conf.rss_key = rss_cfg->key; 2361 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE; 2362 } 2363 2364 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2365 if (ret) 2366 goto cfg_err; 2367 } 2368 2369 /* 2370 * If jumbo frames are enabled, MTU needs to be refreshed 2371 * according to the maximum RX packet length. 2372 */ 2373 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 2374 /* 2375 * Security of max_rx_pkt_len is guaranteed in dpdk frame. 2376 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it 2377 * can safely assign to "uint16_t" type variable. 2378 */ 2379 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len); 2380 ret = hns3_dev_mtu_set(dev, mtu); 2381 if (ret) 2382 goto cfg_err; 2383 dev->data->mtu = mtu; 2384 } 2385 2386 ret = hns3_dev_configure_vlan(dev); 2387 if (ret) 2388 goto cfg_err; 2389 2390 /* config hardware GRO */ 2391 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 2392 ret = hns3_config_gro(hw, gro_en); 2393 if (ret) 2394 goto cfg_err; 2395 2396 hns->rx_simple_allowed = true; 2397 hns->rx_vec_allowed = true; 2398 hns->tx_simple_allowed = true; 2399 hns->tx_vec_allowed = true; 2400 2401 hns3_init_rx_ptype_tble(dev); 2402 hw->adapter_state = HNS3_NIC_CONFIGURED; 2403 2404 return 0; 2405 2406 cfg_err: 2407 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2408 hw->adapter_state = HNS3_NIC_INITIALIZED; 2409 2410 return ret; 2411 } 2412 2413 static int 2414 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2415 { 2416 struct hns3_config_max_frm_size_cmd *req; 2417 struct hns3_cmd_desc desc; 2418 2419 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2420 2421 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2422 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2423 req->min_frm_size = RTE_ETHER_MIN_LEN; 2424 2425 return hns3_cmd_send(hw, &desc, 1); 2426 } 2427 2428 static int 2429 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2430 { 2431 int ret; 2432 2433 ret = hns3_set_mac_mtu(hw, mps); 2434 if (ret) { 2435 hns3_err(hw, "Failed to set mtu, ret = %d", ret); 2436 return ret; 2437 } 2438 2439 ret = hns3_buffer_alloc(hw); 2440 if (ret) 2441 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret); 2442 2443 return ret; 2444 } 2445 2446 static int 2447 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2448 { 2449 struct hns3_adapter *hns = dev->data->dev_private; 2450 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2451 struct hns3_hw *hw = &hns->hw; 2452 bool is_jumbo_frame; 2453 int ret; 2454 2455 if (dev->data->dev_started) { 2456 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2457 "before configuration", dev->data->port_id); 2458 return -EBUSY; 2459 } 2460 2461 rte_spinlock_lock(&hw->lock); 2462 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false; 2463 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2464 2465 /* 2466 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2467 * assign to "uint16_t" type variable. 2468 */ 2469 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2470 if (ret) { 2471 rte_spinlock_unlock(&hw->lock); 2472 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2473 dev->data->port_id, mtu, ret); 2474 return ret; 2475 } 2476 hns->pf.mps = (uint16_t)frame_size; 2477 if (is_jumbo_frame) 2478 dev->data->dev_conf.rxmode.offloads |= 2479 DEV_RX_OFFLOAD_JUMBO_FRAME; 2480 else 2481 dev->data->dev_conf.rxmode.offloads &= 2482 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2483 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2484 rte_spinlock_unlock(&hw->lock); 2485 2486 return 0; 2487 } 2488 2489 static int 2490 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2491 { 2492 struct hns3_adapter *hns = eth_dev->data->dev_private; 2493 struct hns3_hw *hw = &hns->hw; 2494 uint16_t queue_num = hw->tqps_num; 2495 2496 /* 2497 * In interrupt mode, 'max_rx_queues' is set based on the number of 2498 * MSI-X interrupt resources of the hardware. 2499 */ 2500 if (hw->data->dev_conf.intr_conf.rxq == 1) 2501 queue_num = hw->intr_tqps_num; 2502 2503 info->max_rx_queues = queue_num; 2504 info->max_tx_queues = hw->tqps_num; 2505 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2506 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 2507 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2508 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2509 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 2510 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2511 DEV_RX_OFFLOAD_TCP_CKSUM | 2512 DEV_RX_OFFLOAD_UDP_CKSUM | 2513 DEV_RX_OFFLOAD_SCTP_CKSUM | 2514 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2515 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2516 DEV_RX_OFFLOAD_KEEP_CRC | 2517 DEV_RX_OFFLOAD_SCATTER | 2518 DEV_RX_OFFLOAD_VLAN_STRIP | 2519 DEV_RX_OFFLOAD_VLAN_FILTER | 2520 DEV_RX_OFFLOAD_JUMBO_FRAME | 2521 DEV_RX_OFFLOAD_RSS_HASH | 2522 DEV_RX_OFFLOAD_TCP_LRO); 2523 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2524 DEV_TX_OFFLOAD_IPV4_CKSUM | 2525 DEV_TX_OFFLOAD_TCP_CKSUM | 2526 DEV_TX_OFFLOAD_UDP_CKSUM | 2527 DEV_TX_OFFLOAD_SCTP_CKSUM | 2528 DEV_TX_OFFLOAD_MULTI_SEGS | 2529 DEV_TX_OFFLOAD_TCP_TSO | 2530 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2531 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2532 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2533 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 2534 hns3_txvlan_cap_get(hw)); 2535 2536 if (hns3_dev_indep_txrx_supported(hw)) 2537 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 2538 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 2539 2540 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2541 .nb_max = HNS3_MAX_RING_DESC, 2542 .nb_min = HNS3_MIN_RING_DESC, 2543 .nb_align = HNS3_ALIGN_RING_DESC, 2544 }; 2545 2546 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2547 .nb_max = HNS3_MAX_RING_DESC, 2548 .nb_min = HNS3_MIN_RING_DESC, 2549 .nb_align = HNS3_ALIGN_RING_DESC, 2550 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 2551 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 2552 }; 2553 2554 info->default_rxconf = (struct rte_eth_rxconf) { 2555 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 2556 /* 2557 * If there are no available Rx buffer descriptors, incoming 2558 * packets are always dropped by hardware based on hns3 network 2559 * engine. 2560 */ 2561 .rx_drop_en = 1, 2562 .offloads = 0, 2563 }; 2564 info->default_txconf = (struct rte_eth_txconf) { 2565 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 2566 .offloads = 0, 2567 }; 2568 2569 info->vmdq_queue_num = 0; 2570 2571 info->reta_size = HNS3_RSS_IND_TBL_SIZE; 2572 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2573 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2574 2575 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2576 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2577 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2578 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2579 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2580 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2581 2582 return 0; 2583 } 2584 2585 static int 2586 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2587 size_t fw_size) 2588 { 2589 struct hns3_adapter *hns = eth_dev->data->dev_private; 2590 struct hns3_hw *hw = &hns->hw; 2591 uint32_t version = hw->fw_version; 2592 int ret; 2593 2594 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2595 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2596 HNS3_FW_VERSION_BYTE3_S), 2597 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2598 HNS3_FW_VERSION_BYTE2_S), 2599 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2600 HNS3_FW_VERSION_BYTE1_S), 2601 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2602 HNS3_FW_VERSION_BYTE0_S)); 2603 ret += 1; /* add the size of '\0' */ 2604 if (fw_size < (uint32_t)ret) 2605 return ret; 2606 else 2607 return 0; 2608 } 2609 2610 static int 2611 hns3_dev_link_update(struct rte_eth_dev *eth_dev, 2612 __rte_unused int wait_to_complete) 2613 { 2614 struct hns3_adapter *hns = eth_dev->data->dev_private; 2615 struct hns3_hw *hw = &hns->hw; 2616 struct hns3_mac *mac = &hw->mac; 2617 struct rte_eth_link new_link; 2618 2619 if (!hns3_is_reset_pending(hns)) { 2620 hns3_update_speed_duplex(eth_dev); 2621 hns3_update_link_status(hw); 2622 } 2623 2624 memset(&new_link, 0, sizeof(new_link)); 2625 switch (mac->link_speed) { 2626 case ETH_SPEED_NUM_10M: 2627 case ETH_SPEED_NUM_100M: 2628 case ETH_SPEED_NUM_1G: 2629 case ETH_SPEED_NUM_10G: 2630 case ETH_SPEED_NUM_25G: 2631 case ETH_SPEED_NUM_40G: 2632 case ETH_SPEED_NUM_50G: 2633 case ETH_SPEED_NUM_100G: 2634 case ETH_SPEED_NUM_200G: 2635 new_link.link_speed = mac->link_speed; 2636 break; 2637 default: 2638 new_link.link_speed = ETH_SPEED_NUM_100M; 2639 break; 2640 } 2641 2642 new_link.link_duplex = mac->link_duplex; 2643 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2644 new_link.link_autoneg = 2645 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2646 2647 return rte_eth_linkstatus_set(eth_dev, &new_link); 2648 } 2649 2650 static int 2651 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2652 { 2653 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2654 struct hns3_pf *pf = &hns->pf; 2655 2656 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2657 return -EINVAL; 2658 2659 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2660 2661 return 0; 2662 } 2663 2664 static int 2665 hns3_query_function_status(struct hns3_hw *hw) 2666 { 2667 #define HNS3_QUERY_MAX_CNT 10 2668 #define HNS3_QUERY_SLEEP_MSCOEND 1 2669 struct hns3_func_status_cmd *req; 2670 struct hns3_cmd_desc desc; 2671 int timeout = 0; 2672 int ret; 2673 2674 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2675 req = (struct hns3_func_status_cmd *)desc.data; 2676 2677 do { 2678 ret = hns3_cmd_send(hw, &desc, 1); 2679 if (ret) { 2680 PMD_INIT_LOG(ERR, "query function status failed %d", 2681 ret); 2682 return ret; 2683 } 2684 2685 /* Check pf reset is done */ 2686 if (req->pf_state) 2687 break; 2688 2689 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2690 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2691 2692 return hns3_parse_func_status(hw, req); 2693 } 2694 2695 static int 2696 hns3_get_pf_max_tqp_num(struct hns3_hw *hw) 2697 { 2698 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2699 struct hns3_pf *pf = &hns->pf; 2700 2701 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) { 2702 /* 2703 * The total_tqps_num obtained from firmware is maximum tqp 2704 * numbers of this port, which should be used for PF and VFs. 2705 * There is no need for pf to have so many tqp numbers in 2706 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2707 * coming from config file, is assigned to maximum queue number 2708 * for the PF of this port by user. So users can modify the 2709 * maximum queue number of PF according to their own application 2710 * scenarios, which is more flexible to use. In addition, many 2711 * memories can be saved due to allocating queue statistics 2712 * room according to the actual number of queues required. The 2713 * maximum queue number of PF for network engine with 2714 * revision_id greater than 0x30 is assigned by config file. 2715 */ 2716 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) { 2717 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) " 2718 "must be greater than 0.", 2719 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF); 2720 return -EINVAL; 2721 } 2722 2723 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2724 hw->total_tqps_num); 2725 } else { 2726 /* 2727 * Due to the limitation on the number of PF interrupts 2728 * available, the maximum queue number assigned to PF on 2729 * the network engine with revision_id 0x21 is 64. 2730 */ 2731 hw->tqps_num = RTE_MIN(hw->total_tqps_num, 2732 HNS3_MAX_TQP_NUM_HIP08_PF); 2733 } 2734 2735 return 0; 2736 } 2737 2738 static int 2739 hns3_query_pf_resource(struct hns3_hw *hw) 2740 { 2741 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2742 struct hns3_pf *pf = &hns->pf; 2743 struct hns3_pf_res_cmd *req; 2744 struct hns3_cmd_desc desc; 2745 int ret; 2746 2747 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 2748 ret = hns3_cmd_send(hw, &desc, 1); 2749 if (ret) { 2750 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 2751 return ret; 2752 } 2753 2754 req = (struct hns3_pf_res_cmd *)desc.data; 2755 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) + 2756 rte_le_to_cpu_16(req->ext_tqp_num); 2757 ret = hns3_get_pf_max_tqp_num(hw); 2758 if (ret) 2759 return ret; 2760 2761 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 2762 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 2763 2764 if (req->tx_buf_size) 2765 pf->tx_buf_size = 2766 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 2767 else 2768 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 2769 2770 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 2771 2772 if (req->dv_buf_size) 2773 pf->dv_buf_size = 2774 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 2775 else 2776 pf->dv_buf_size = HNS3_DEFAULT_DV; 2777 2778 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 2779 2780 hw->num_msi = 2781 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 2782 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 2783 2784 return 0; 2785 } 2786 2787 static void 2788 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 2789 { 2790 struct hns3_cfg_param_cmd *req; 2791 uint64_t mac_addr_tmp_high; 2792 uint8_t ext_rss_size_max; 2793 uint64_t mac_addr_tmp; 2794 uint32_t i; 2795 2796 req = (struct hns3_cfg_param_cmd *)desc[0].data; 2797 2798 /* get the configuration */ 2799 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2800 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S); 2801 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2802 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 2803 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2804 HNS3_CFG_TQP_DESC_N_M, 2805 HNS3_CFG_TQP_DESC_N_S); 2806 2807 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2808 HNS3_CFG_PHY_ADDR_M, 2809 HNS3_CFG_PHY_ADDR_S); 2810 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2811 HNS3_CFG_MEDIA_TP_M, 2812 HNS3_CFG_MEDIA_TP_S); 2813 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2814 HNS3_CFG_RX_BUF_LEN_M, 2815 HNS3_CFG_RX_BUF_LEN_S); 2816 /* get mac address */ 2817 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 2818 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2819 HNS3_CFG_MAC_ADDR_H_M, 2820 HNS3_CFG_MAC_ADDR_H_S); 2821 2822 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 2823 2824 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2825 HNS3_CFG_DEFAULT_SPEED_M, 2826 HNS3_CFG_DEFAULT_SPEED_S); 2827 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2828 HNS3_CFG_RSS_SIZE_M, 2829 HNS3_CFG_RSS_SIZE_S); 2830 2831 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2832 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 2833 2834 req = (struct hns3_cfg_param_cmd *)desc[1].data; 2835 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 2836 2837 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2838 HNS3_CFG_SPEED_ABILITY_M, 2839 HNS3_CFG_SPEED_ABILITY_S); 2840 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2841 HNS3_CFG_UMV_TBL_SPACE_M, 2842 HNS3_CFG_UMV_TBL_SPACE_S); 2843 if (!cfg->umv_space) 2844 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 2845 2846 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]), 2847 HNS3_CFG_EXT_RSS_SIZE_M, 2848 HNS3_CFG_EXT_RSS_SIZE_S); 2849 2850 /* 2851 * Field ext_rss_size_max obtained from firmware will be more flexible 2852 * for future changes and expansions, which is an exponent of 2, instead 2853 * of reading out directly. If this field is not zero, hns3 PF PMD 2854 * driver uses it as rss_size_max under one TC. Device, whose revision 2855 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the 2856 * maximum number of queues supported under a TC through this field. 2857 */ 2858 if (ext_rss_size_max) 2859 cfg->rss_size_max = 1U << ext_rss_size_max; 2860 } 2861 2862 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 2863 * @hw: pointer to struct hns3_hw 2864 * @hcfg: the config structure to be getted 2865 */ 2866 static int 2867 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 2868 { 2869 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 2870 struct hns3_cfg_param_cmd *req; 2871 uint32_t offset; 2872 uint32_t i; 2873 int ret; 2874 2875 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 2876 offset = 0; 2877 req = (struct hns3_cfg_param_cmd *)desc[i].data; 2878 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 2879 true); 2880 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 2881 i * HNS3_CFG_RD_LEN_BYTES); 2882 /* Len should be divided by 4 when send to hardware */ 2883 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 2884 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 2885 req->offset = rte_cpu_to_le_32(offset); 2886 } 2887 2888 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 2889 if (ret) { 2890 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 2891 return ret; 2892 } 2893 2894 hns3_parse_cfg(hcfg, desc); 2895 2896 return 0; 2897 } 2898 2899 static int 2900 hns3_parse_speed(int speed_cmd, uint32_t *speed) 2901 { 2902 switch (speed_cmd) { 2903 case HNS3_CFG_SPEED_10M: 2904 *speed = ETH_SPEED_NUM_10M; 2905 break; 2906 case HNS3_CFG_SPEED_100M: 2907 *speed = ETH_SPEED_NUM_100M; 2908 break; 2909 case HNS3_CFG_SPEED_1G: 2910 *speed = ETH_SPEED_NUM_1G; 2911 break; 2912 case HNS3_CFG_SPEED_10G: 2913 *speed = ETH_SPEED_NUM_10G; 2914 break; 2915 case HNS3_CFG_SPEED_25G: 2916 *speed = ETH_SPEED_NUM_25G; 2917 break; 2918 case HNS3_CFG_SPEED_40G: 2919 *speed = ETH_SPEED_NUM_40G; 2920 break; 2921 case HNS3_CFG_SPEED_50G: 2922 *speed = ETH_SPEED_NUM_50G; 2923 break; 2924 case HNS3_CFG_SPEED_100G: 2925 *speed = ETH_SPEED_NUM_100G; 2926 break; 2927 case HNS3_CFG_SPEED_200G: 2928 *speed = ETH_SPEED_NUM_200G; 2929 break; 2930 default: 2931 return -EINVAL; 2932 } 2933 2934 return 0; 2935 } 2936 2937 static void 2938 hns3_set_default_dev_specifications(struct hns3_hw *hw) 2939 { 2940 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 2941 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 2942 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 2943 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 2944 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 2945 } 2946 2947 static void 2948 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 2949 { 2950 struct hns3_dev_specs_0_cmd *req0; 2951 2952 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 2953 2954 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 2955 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 2956 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 2957 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 2958 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 2959 } 2960 2961 static int 2962 hns3_query_dev_specifications(struct hns3_hw *hw) 2963 { 2964 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 2965 int ret; 2966 int i; 2967 2968 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2969 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 2970 true); 2971 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 2972 } 2973 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 2974 2975 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 2976 if (ret) 2977 return ret; 2978 2979 hns3_parse_dev_specifications(hw, desc); 2980 2981 return 0; 2982 } 2983 2984 static int 2985 hns3_get_capability(struct hns3_hw *hw) 2986 { 2987 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2988 struct rte_pci_device *pci_dev; 2989 struct hns3_pf *pf = &hns->pf; 2990 struct rte_eth_dev *eth_dev; 2991 uint16_t device_id; 2992 uint8_t revision; 2993 int ret; 2994 2995 eth_dev = &rte_eth_devices[hw->data->port_id]; 2996 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2997 device_id = pci_dev->id.device_id; 2998 2999 if (device_id == HNS3_DEV_ID_25GE_RDMA || 3000 device_id == HNS3_DEV_ID_50GE_RDMA || 3001 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 3002 device_id == HNS3_DEV_ID_200G_RDMA) 3003 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 3004 3005 ret = hns3_query_dev_fec_info(eth_dev); 3006 if (ret) { 3007 PMD_INIT_LOG(ERR, 3008 "failed to query FEC information, ret = %d", ret); 3009 return ret; 3010 } 3011 3012 /* Get PCI revision id */ 3013 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 3014 HNS3_PCI_REVISION_ID); 3015 if (ret != HNS3_PCI_REVISION_ID_LEN) { 3016 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 3017 ret); 3018 return -EIO; 3019 } 3020 hw->revision = revision; 3021 3022 if (revision < PCI_REVISION_ID_HIP09_A) { 3023 hns3_set_default_dev_specifications(hw); 3024 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 3025 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 3026 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 3027 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; 3028 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 3029 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; 3030 hw->rss_info.ipv6_sctp_offload_supported = false; 3031 return 0; 3032 } 3033 3034 ret = hns3_query_dev_specifications(hw); 3035 if (ret) { 3036 PMD_INIT_LOG(ERR, 3037 "failed to query dev specifications, ret = %d", 3038 ret); 3039 return ret; 3040 } 3041 3042 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 3043 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 3044 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 3045 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; 3046 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 3047 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; 3048 hw->rss_info.ipv6_sctp_offload_supported = true; 3049 3050 return 0; 3051 } 3052 3053 static int 3054 hns3_get_board_configuration(struct hns3_hw *hw) 3055 { 3056 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3057 struct hns3_pf *pf = &hns->pf; 3058 struct hns3_cfg cfg; 3059 int ret; 3060 3061 ret = hns3_get_board_cfg(hw, &cfg); 3062 if (ret) { 3063 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 3064 return ret; 3065 } 3066 3067 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER && 3068 !hns3_dev_copper_supported(hw)) { 3069 PMD_INIT_LOG(ERR, "media type is copper, not supported."); 3070 return -EOPNOTSUPP; 3071 } 3072 3073 hw->mac.media_type = cfg.media_type; 3074 hw->rss_size_max = cfg.rss_size_max; 3075 hw->rss_dis_flag = false; 3076 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 3077 hw->mac.phy_addr = cfg.phy_addr; 3078 hw->mac.default_addr_setted = false; 3079 hw->num_tx_desc = cfg.tqp_desc_num; 3080 hw->num_rx_desc = cfg.tqp_desc_num; 3081 hw->dcb_info.num_pg = 1; 3082 hw->dcb_info.hw_pfc_map = 0; 3083 3084 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 3085 if (ret) { 3086 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d", 3087 cfg.default_speed, ret); 3088 return ret; 3089 } 3090 3091 pf->tc_max = cfg.tc_num; 3092 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 3093 PMD_INIT_LOG(WARNING, 3094 "Get TC num(%u) from flash, set TC num to 1", 3095 pf->tc_max); 3096 pf->tc_max = 1; 3097 } 3098 3099 /* Dev does not support DCB */ 3100 if (!hns3_dev_dcb_supported(hw)) { 3101 pf->tc_max = 1; 3102 pf->pfc_max = 0; 3103 } else 3104 pf->pfc_max = pf->tc_max; 3105 3106 hw->dcb_info.num_tc = 1; 3107 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 3108 hw->tqps_num / hw->dcb_info.num_tc); 3109 hns3_set_bit(hw->hw_tc_map, 0, 1); 3110 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 3111 3112 pf->wanted_umv_size = cfg.umv_space; 3113 3114 return ret; 3115 } 3116 3117 static int 3118 hns3_get_configuration(struct hns3_hw *hw) 3119 { 3120 int ret; 3121 3122 ret = hns3_query_function_status(hw); 3123 if (ret) { 3124 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 3125 return ret; 3126 } 3127 3128 /* Get device capability */ 3129 ret = hns3_get_capability(hw); 3130 if (ret) { 3131 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 3132 return ret; 3133 } 3134 3135 /* Get pf resource */ 3136 ret = hns3_query_pf_resource(hw); 3137 if (ret) { 3138 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 3139 return ret; 3140 } 3141 3142 ret = hns3_get_board_configuration(hw); 3143 if (ret) 3144 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret); 3145 3146 return ret; 3147 } 3148 3149 static int 3150 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 3151 uint16_t tqp_vid, bool is_pf) 3152 { 3153 struct hns3_tqp_map_cmd *req; 3154 struct hns3_cmd_desc desc; 3155 int ret; 3156 3157 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 3158 3159 req = (struct hns3_tqp_map_cmd *)desc.data; 3160 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 3161 req->tqp_vf = func_id; 3162 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 3163 if (!is_pf) 3164 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 3165 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 3166 3167 ret = hns3_cmd_send(hw, &desc, 1); 3168 if (ret) 3169 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 3170 3171 return ret; 3172 } 3173 3174 static int 3175 hns3_map_tqp(struct hns3_hw *hw) 3176 { 3177 int ret; 3178 int i; 3179 3180 /* 3181 * In current version, VF is not supported when PF is driven by DPDK 3182 * driver, so we assign total tqps_num tqps allocated to this port 3183 * to PF. 3184 */ 3185 for (i = 0; i < hw->total_tqps_num; i++) { 3186 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true); 3187 if (ret) 3188 return ret; 3189 } 3190 3191 return 0; 3192 } 3193 3194 static int 3195 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 3196 { 3197 struct hns3_config_mac_speed_dup_cmd *req; 3198 struct hns3_cmd_desc desc; 3199 int ret; 3200 3201 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 3202 3203 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 3204 3205 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 3206 3207 switch (speed) { 3208 case ETH_SPEED_NUM_10M: 3209 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3210 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 3211 break; 3212 case ETH_SPEED_NUM_100M: 3213 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3214 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 3215 break; 3216 case ETH_SPEED_NUM_1G: 3217 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3218 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 3219 break; 3220 case ETH_SPEED_NUM_10G: 3221 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3222 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 3223 break; 3224 case ETH_SPEED_NUM_25G: 3225 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3226 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 3227 break; 3228 case ETH_SPEED_NUM_40G: 3229 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3230 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 3231 break; 3232 case ETH_SPEED_NUM_50G: 3233 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3234 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 3235 break; 3236 case ETH_SPEED_NUM_100G: 3237 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3238 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 3239 break; 3240 case ETH_SPEED_NUM_200G: 3241 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3242 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 3243 break; 3244 default: 3245 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 3246 return -EINVAL; 3247 } 3248 3249 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3250 3251 ret = hns3_cmd_send(hw, &desc, 1); 3252 if (ret) 3253 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3254 3255 return ret; 3256 } 3257 3258 static int 3259 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3260 { 3261 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3262 struct hns3_pf *pf = &hns->pf; 3263 struct hns3_priv_buf *priv; 3264 uint32_t i, total_size; 3265 3266 total_size = pf->pkt_buf_size; 3267 3268 /* alloc tx buffer for all enabled tc */ 3269 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3270 priv = &buf_alloc->priv_buf[i]; 3271 3272 if (hw->hw_tc_map & BIT(i)) { 3273 if (total_size < pf->tx_buf_size) 3274 return -ENOMEM; 3275 3276 priv->tx_buf_size = pf->tx_buf_size; 3277 } else 3278 priv->tx_buf_size = 0; 3279 3280 total_size -= priv->tx_buf_size; 3281 } 3282 3283 return 0; 3284 } 3285 3286 static int 3287 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3288 { 3289 /* TX buffer size is unit by 128 byte */ 3290 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3291 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3292 struct hns3_tx_buff_alloc_cmd *req; 3293 struct hns3_cmd_desc desc; 3294 uint32_t buf_size; 3295 uint32_t i; 3296 int ret; 3297 3298 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3299 3300 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3301 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3302 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3303 3304 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3305 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3306 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3307 } 3308 3309 ret = hns3_cmd_send(hw, &desc, 1); 3310 if (ret) 3311 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3312 3313 return ret; 3314 } 3315 3316 static int 3317 hns3_get_tc_num(struct hns3_hw *hw) 3318 { 3319 int cnt = 0; 3320 uint8_t i; 3321 3322 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3323 if (hw->hw_tc_map & BIT(i)) 3324 cnt++; 3325 return cnt; 3326 } 3327 3328 static uint32_t 3329 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3330 { 3331 struct hns3_priv_buf *priv; 3332 uint32_t rx_priv = 0; 3333 int i; 3334 3335 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3336 priv = &buf_alloc->priv_buf[i]; 3337 if (priv->enable) 3338 rx_priv += priv->buf_size; 3339 } 3340 return rx_priv; 3341 } 3342 3343 static uint32_t 3344 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3345 { 3346 uint32_t total_tx_size = 0; 3347 uint32_t i; 3348 3349 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3350 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3351 3352 return total_tx_size; 3353 } 3354 3355 /* Get the number of pfc enabled TCs, which have private buffer */ 3356 static int 3357 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3358 { 3359 struct hns3_priv_buf *priv; 3360 int cnt = 0; 3361 uint8_t i; 3362 3363 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3364 priv = &buf_alloc->priv_buf[i]; 3365 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3366 cnt++; 3367 } 3368 3369 return cnt; 3370 } 3371 3372 /* Get the number of pfc disabled TCs, which have private buffer */ 3373 static int 3374 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3375 struct hns3_pkt_buf_alloc *buf_alloc) 3376 { 3377 struct hns3_priv_buf *priv; 3378 int cnt = 0; 3379 uint8_t i; 3380 3381 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3382 priv = &buf_alloc->priv_buf[i]; 3383 if (hw->hw_tc_map & BIT(i) && 3384 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3385 cnt++; 3386 } 3387 3388 return cnt; 3389 } 3390 3391 static bool 3392 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3393 uint32_t rx_all) 3394 { 3395 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3396 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3397 struct hns3_pf *pf = &hns->pf; 3398 uint32_t shared_buf, aligned_mps; 3399 uint32_t rx_priv; 3400 uint8_t tc_num; 3401 uint8_t i; 3402 3403 tc_num = hns3_get_tc_num(hw); 3404 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3405 3406 if (hns3_dev_dcb_supported(hw)) 3407 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3408 pf->dv_buf_size; 3409 else 3410 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3411 + pf->dv_buf_size; 3412 3413 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3414 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3415 HNS3_BUF_SIZE_UNIT); 3416 3417 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3418 if (rx_all < rx_priv + shared_std) 3419 return false; 3420 3421 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3422 buf_alloc->s_buf.buf_size = shared_buf; 3423 if (hns3_dev_dcb_supported(hw)) { 3424 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3425 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3426 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3427 HNS3_BUF_SIZE_UNIT); 3428 } else { 3429 buf_alloc->s_buf.self.high = 3430 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3431 buf_alloc->s_buf.self.low = aligned_mps; 3432 } 3433 3434 if (hns3_dev_dcb_supported(hw)) { 3435 hi_thrd = shared_buf - pf->dv_buf_size; 3436 3437 if (tc_num <= NEED_RESERVE_TC_NUM) 3438 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT / 3439 BUF_MAX_PERCENT; 3440 3441 if (tc_num) 3442 hi_thrd = hi_thrd / tc_num; 3443 3444 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3445 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3446 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3447 } else { 3448 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3449 lo_thrd = aligned_mps; 3450 } 3451 3452 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3453 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3454 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3455 } 3456 3457 return true; 3458 } 3459 3460 static bool 3461 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3462 struct hns3_pkt_buf_alloc *buf_alloc) 3463 { 3464 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3465 struct hns3_pf *pf = &hns->pf; 3466 struct hns3_priv_buf *priv; 3467 uint32_t aligned_mps; 3468 uint32_t rx_all; 3469 uint8_t i; 3470 3471 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3472 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3473 3474 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3475 priv = &buf_alloc->priv_buf[i]; 3476 3477 priv->enable = 0; 3478 priv->wl.low = 0; 3479 priv->wl.high = 0; 3480 priv->buf_size = 0; 3481 3482 if (!(hw->hw_tc_map & BIT(i))) 3483 continue; 3484 3485 priv->enable = 1; 3486 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3487 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3488 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3489 HNS3_BUF_SIZE_UNIT); 3490 } else { 3491 priv->wl.low = 0; 3492 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3493 aligned_mps; 3494 } 3495 3496 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3497 } 3498 3499 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3500 } 3501 3502 static bool 3503 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3504 struct hns3_pkt_buf_alloc *buf_alloc) 3505 { 3506 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3507 struct hns3_pf *pf = &hns->pf; 3508 struct hns3_priv_buf *priv; 3509 int no_pfc_priv_num; 3510 uint32_t rx_all; 3511 uint8_t mask; 3512 int i; 3513 3514 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3515 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3516 3517 /* let the last to be cleared first */ 3518 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3519 priv = &buf_alloc->priv_buf[i]; 3520 mask = BIT((uint8_t)i); 3521 3522 if (hw->hw_tc_map & mask && 3523 !(hw->dcb_info.hw_pfc_map & mask)) { 3524 /* Clear the no pfc TC private buffer */ 3525 priv->wl.low = 0; 3526 priv->wl.high = 0; 3527 priv->buf_size = 0; 3528 priv->enable = 0; 3529 no_pfc_priv_num--; 3530 } 3531 3532 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3533 no_pfc_priv_num == 0) 3534 break; 3535 } 3536 3537 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3538 } 3539 3540 static bool 3541 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3542 struct hns3_pkt_buf_alloc *buf_alloc) 3543 { 3544 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3545 struct hns3_pf *pf = &hns->pf; 3546 struct hns3_priv_buf *priv; 3547 uint32_t rx_all; 3548 int pfc_priv_num; 3549 uint8_t mask; 3550 int i; 3551 3552 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3553 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3554 3555 /* let the last to be cleared first */ 3556 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3557 priv = &buf_alloc->priv_buf[i]; 3558 mask = BIT((uint8_t)i); 3559 3560 if (hw->hw_tc_map & mask && 3561 hw->dcb_info.hw_pfc_map & mask) { 3562 /* Reduce the number of pfc TC with private buffer */ 3563 priv->wl.low = 0; 3564 priv->enable = 0; 3565 priv->wl.high = 0; 3566 priv->buf_size = 0; 3567 pfc_priv_num--; 3568 } 3569 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3570 pfc_priv_num == 0) 3571 break; 3572 } 3573 3574 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3575 } 3576 3577 static bool 3578 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3579 struct hns3_pkt_buf_alloc *buf_alloc) 3580 { 3581 #define COMPENSATE_BUFFER 0x3C00 3582 #define COMPENSATE_HALF_MPS_NUM 5 3583 #define PRIV_WL_GAP 0x1800 3584 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3585 struct hns3_pf *pf = &hns->pf; 3586 uint32_t tc_num = hns3_get_tc_num(hw); 3587 uint32_t half_mps = pf->mps >> 1; 3588 struct hns3_priv_buf *priv; 3589 uint32_t min_rx_priv; 3590 uint32_t rx_priv; 3591 uint8_t i; 3592 3593 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3594 if (tc_num) 3595 rx_priv = rx_priv / tc_num; 3596 3597 if (tc_num <= NEED_RESERVE_TC_NUM) 3598 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3599 3600 /* 3601 * Minimum value of private buffer in rx direction (min_rx_priv) is 3602 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3603 * buffer if rx_priv is greater than min_rx_priv. 3604 */ 3605 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3606 COMPENSATE_HALF_MPS_NUM * half_mps; 3607 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3608 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3609 3610 if (rx_priv < min_rx_priv) 3611 return false; 3612 3613 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3614 priv = &buf_alloc->priv_buf[i]; 3615 3616 priv->enable = 0; 3617 priv->wl.low = 0; 3618 priv->wl.high = 0; 3619 priv->buf_size = 0; 3620 3621 if (!(hw->hw_tc_map & BIT(i))) 3622 continue; 3623 3624 priv->enable = 1; 3625 priv->buf_size = rx_priv; 3626 priv->wl.high = rx_priv - pf->dv_buf_size; 3627 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3628 } 3629 3630 buf_alloc->s_buf.buf_size = 0; 3631 3632 return true; 3633 } 3634 3635 /* 3636 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3637 * @hw: pointer to struct hns3_hw 3638 * @buf_alloc: pointer to buffer calculation data 3639 * @return: 0: calculate sucessful, negative: fail 3640 */ 3641 static int 3642 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3643 { 3644 /* When DCB is not supported, rx private buffer is not allocated. */ 3645 if (!hns3_dev_dcb_supported(hw)) { 3646 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3647 struct hns3_pf *pf = &hns->pf; 3648 uint32_t rx_all = pf->pkt_buf_size; 3649 3650 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3651 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3652 return -ENOMEM; 3653 3654 return 0; 3655 } 3656 3657 /* 3658 * Try to allocate privated packet buffer for all TCs without share 3659 * buffer. 3660 */ 3661 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3662 return 0; 3663 3664 /* 3665 * Try to allocate privated packet buffer for all TCs with share 3666 * buffer. 3667 */ 3668 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3669 return 0; 3670 3671 /* 3672 * For different application scenes, the enabled port number, TC number 3673 * and no_drop TC number are different. In order to obtain the better 3674 * performance, software could allocate the buffer size and configure 3675 * the waterline by tring to decrease the private buffer size according 3676 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc 3677 * enabled tc. 3678 */ 3679 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 3680 return 0; 3681 3682 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 3683 return 0; 3684 3685 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 3686 return 0; 3687 3688 return -ENOMEM; 3689 } 3690 3691 static int 3692 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3693 { 3694 struct hns3_rx_priv_buff_cmd *req; 3695 struct hns3_cmd_desc desc; 3696 uint32_t buf_size; 3697 int ret; 3698 int i; 3699 3700 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 3701 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 3702 3703 /* Alloc private buffer TCs */ 3704 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3705 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 3706 3707 req->buf_num[i] = 3708 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 3709 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 3710 } 3711 3712 buf_size = buf_alloc->s_buf.buf_size; 3713 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 3714 (1 << HNS3_TC0_PRI_BUF_EN_B)); 3715 3716 ret = hns3_cmd_send(hw, &desc, 1); 3717 if (ret) 3718 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 3719 3720 return ret; 3721 } 3722 3723 static int 3724 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3725 { 3726 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 3727 struct hns3_rx_priv_wl_buf *req; 3728 struct hns3_priv_buf *priv; 3729 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 3730 int i, j; 3731 int ret; 3732 3733 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 3734 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 3735 false); 3736 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 3737 3738 /* The first descriptor set the NEXT bit to 1 */ 3739 if (i == 0) 3740 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3741 else 3742 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3743 3744 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3745 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 3746 3747 priv = &buf_alloc->priv_buf[idx]; 3748 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 3749 HNS3_BUF_UNIT_S); 3750 req->tc_wl[j].high |= 3751 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3752 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 3753 HNS3_BUF_UNIT_S); 3754 req->tc_wl[j].low |= 3755 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3756 } 3757 } 3758 3759 /* Send 2 descriptor at one time */ 3760 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 3761 if (ret) 3762 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 3763 ret); 3764 return ret; 3765 } 3766 3767 static int 3768 hns3_common_thrd_config(struct hns3_hw *hw, 3769 struct hns3_pkt_buf_alloc *buf_alloc) 3770 { 3771 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 3772 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 3773 struct hns3_rx_com_thrd *req; 3774 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 3775 struct hns3_tc_thrd *tc; 3776 int tc_idx; 3777 int i, j; 3778 int ret; 3779 3780 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 3781 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 3782 false); 3783 req = (struct hns3_rx_com_thrd *)&desc[i].data; 3784 3785 /* The first descriptor set the NEXT bit to 1 */ 3786 if (i == 0) 3787 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3788 else 3789 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3790 3791 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3792 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 3793 tc = &s_buf->tc_thrd[tc_idx]; 3794 3795 req->com_thrd[j].high = 3796 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 3797 req->com_thrd[j].high |= 3798 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3799 req->com_thrd[j].low = 3800 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 3801 req->com_thrd[j].low |= 3802 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3803 } 3804 } 3805 3806 /* Send 2 descriptors at one time */ 3807 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 3808 if (ret) 3809 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 3810 3811 return ret; 3812 } 3813 3814 static int 3815 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3816 { 3817 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 3818 struct hns3_rx_com_wl *req; 3819 struct hns3_cmd_desc desc; 3820 int ret; 3821 3822 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 3823 3824 req = (struct hns3_rx_com_wl *)desc.data; 3825 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 3826 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3827 3828 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 3829 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3830 3831 ret = hns3_cmd_send(hw, &desc, 1); 3832 if (ret) 3833 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 3834 3835 return ret; 3836 } 3837 3838 int 3839 hns3_buffer_alloc(struct hns3_hw *hw) 3840 { 3841 struct hns3_pkt_buf_alloc pkt_buf; 3842 int ret; 3843 3844 memset(&pkt_buf, 0, sizeof(pkt_buf)); 3845 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 3846 if (ret) { 3847 PMD_INIT_LOG(ERR, 3848 "could not calc tx buffer size for all TCs %d", 3849 ret); 3850 return ret; 3851 } 3852 3853 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 3854 if (ret) { 3855 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 3856 return ret; 3857 } 3858 3859 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 3860 if (ret) { 3861 PMD_INIT_LOG(ERR, 3862 "could not calc rx priv buffer size for all TCs %d", 3863 ret); 3864 return ret; 3865 } 3866 3867 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 3868 if (ret) { 3869 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 3870 return ret; 3871 } 3872 3873 if (hns3_dev_dcb_supported(hw)) { 3874 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 3875 if (ret) { 3876 PMD_INIT_LOG(ERR, 3877 "could not configure rx private waterline %d", 3878 ret); 3879 return ret; 3880 } 3881 3882 ret = hns3_common_thrd_config(hw, &pkt_buf); 3883 if (ret) { 3884 PMD_INIT_LOG(ERR, 3885 "could not configure common threshold %d", 3886 ret); 3887 return ret; 3888 } 3889 } 3890 3891 ret = hns3_common_wl_config(hw, &pkt_buf); 3892 if (ret) 3893 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 3894 ret); 3895 3896 return ret; 3897 } 3898 3899 static int 3900 hns3_mac_init(struct hns3_hw *hw) 3901 { 3902 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3903 struct hns3_mac *mac = &hw->mac; 3904 struct hns3_pf *pf = &hns->pf; 3905 int ret; 3906 3907 pf->support_sfp_query = true; 3908 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 3909 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 3910 if (ret) { 3911 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 3912 return ret; 3913 } 3914 3915 mac->link_status = ETH_LINK_DOWN; 3916 3917 return hns3_config_mtu(hw, pf->mps); 3918 } 3919 3920 static int 3921 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 3922 { 3923 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 3924 #define HNS3_ETHERTYPE_ALREADY_ADD 1 3925 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 3926 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 3927 int return_status; 3928 3929 if (cmdq_resp) { 3930 PMD_INIT_LOG(ERR, 3931 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 3932 cmdq_resp); 3933 return -EIO; 3934 } 3935 3936 switch (resp_code) { 3937 case HNS3_ETHERTYPE_SUCCESS_ADD: 3938 case HNS3_ETHERTYPE_ALREADY_ADD: 3939 return_status = 0; 3940 break; 3941 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 3942 PMD_INIT_LOG(ERR, 3943 "add mac ethertype failed for manager table overflow."); 3944 return_status = -EIO; 3945 break; 3946 case HNS3_ETHERTYPE_KEY_CONFLICT: 3947 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 3948 return_status = -EIO; 3949 break; 3950 default: 3951 PMD_INIT_LOG(ERR, 3952 "add mac ethertype failed for undefined, code=%d.", 3953 resp_code); 3954 return_status = -EIO; 3955 break; 3956 } 3957 3958 return return_status; 3959 } 3960 3961 static int 3962 hns3_add_mgr_tbl(struct hns3_hw *hw, 3963 const struct hns3_mac_mgr_tbl_entry_cmd *req) 3964 { 3965 struct hns3_cmd_desc desc; 3966 uint8_t resp_code; 3967 uint16_t retval; 3968 int ret; 3969 3970 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 3971 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 3972 3973 ret = hns3_cmd_send(hw, &desc, 1); 3974 if (ret) { 3975 PMD_INIT_LOG(ERR, 3976 "add mac ethertype failed for cmd_send, ret =%d.", 3977 ret); 3978 return ret; 3979 } 3980 3981 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 3982 retval = rte_le_to_cpu_16(desc.retval); 3983 3984 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 3985 } 3986 3987 static void 3988 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 3989 int *table_item_num) 3990 { 3991 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 3992 3993 /* 3994 * In current version, we add one item in management table as below: 3995 * 0x0180C200000E -- LLDP MC address 3996 */ 3997 tbl = mgr_table; 3998 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 3999 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 4000 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 4001 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 4002 tbl->i_port_bitmap = 0x1; 4003 *table_item_num = 1; 4004 } 4005 4006 static int 4007 hns3_init_mgr_tbl(struct hns3_hw *hw) 4008 { 4009 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 4010 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 4011 int table_item_num; 4012 int ret; 4013 int i; 4014 4015 memset(mgr_table, 0, sizeof(mgr_table)); 4016 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 4017 for (i = 0; i < table_item_num; i++) { 4018 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 4019 if (ret) { 4020 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 4021 ret); 4022 return ret; 4023 } 4024 } 4025 4026 return 0; 4027 } 4028 4029 static void 4030 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 4031 bool en_mc, bool en_bc, int vport_id) 4032 { 4033 if (!param) 4034 return; 4035 4036 memset(param, 0, sizeof(struct hns3_promisc_param)); 4037 if (en_uc) 4038 param->enable = HNS3_PROMISC_EN_UC; 4039 if (en_mc) 4040 param->enable |= HNS3_PROMISC_EN_MC; 4041 if (en_bc) 4042 param->enable |= HNS3_PROMISC_EN_BC; 4043 param->vf_id = vport_id; 4044 } 4045 4046 static int 4047 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 4048 { 4049 struct hns3_promisc_cfg_cmd *req; 4050 struct hns3_cmd_desc desc; 4051 int ret; 4052 4053 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 4054 4055 req = (struct hns3_promisc_cfg_cmd *)desc.data; 4056 req->vf_id = param->vf_id; 4057 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 4058 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 4059 4060 ret = hns3_cmd_send(hw, &desc, 1); 4061 if (ret) 4062 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 4063 4064 return ret; 4065 } 4066 4067 static int 4068 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 4069 { 4070 struct hns3_promisc_param param; 4071 bool en_bc_pmc = true; 4072 uint8_t vf_id; 4073 4074 /* 4075 * In current version VF is not supported when PF is driven by DPDK 4076 * driver, just need to configure parameters for PF vport. 4077 */ 4078 vf_id = HNS3_PF_FUNC_ID; 4079 4080 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 4081 return hns3_cmd_set_promisc_mode(hw, ¶m); 4082 } 4083 4084 static int 4085 hns3_promisc_init(struct hns3_hw *hw) 4086 { 4087 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4088 struct hns3_pf *pf = &hns->pf; 4089 struct hns3_promisc_param param; 4090 uint16_t func_id; 4091 int ret; 4092 4093 ret = hns3_set_promisc_mode(hw, false, false); 4094 if (ret) { 4095 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 4096 return ret; 4097 } 4098 4099 /* 4100 * In current version VFs are not supported when PF is driven by DPDK 4101 * driver. After PF has been taken over by DPDK, the original VF will 4102 * be invalid. So, there is a possibility of entry residues. It should 4103 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 4104 * during init. 4105 */ 4106 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 4107 hns3_promisc_param_init(¶m, false, false, false, func_id); 4108 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4109 if (ret) { 4110 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode," 4111 " ret = %d", func_id, ret); 4112 return ret; 4113 } 4114 } 4115 4116 return 0; 4117 } 4118 4119 static void 4120 hns3_promisc_uninit(struct hns3_hw *hw) 4121 { 4122 struct hns3_promisc_param param; 4123 uint16_t func_id; 4124 int ret; 4125 4126 func_id = HNS3_PF_FUNC_ID; 4127 4128 /* 4129 * In current version VFs are not supported when PF is driven by 4130 * DPDK driver, and VFs' promisc mode status has been cleared during 4131 * init and their status will not change. So just clear PF's promisc 4132 * mode status during uninit. 4133 */ 4134 hns3_promisc_param_init(¶m, false, false, false, func_id); 4135 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4136 if (ret) 4137 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 4138 " uninit, ret = %d", ret); 4139 } 4140 4141 static int 4142 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 4143 { 4144 bool allmulti = dev->data->all_multicast ? true : false; 4145 struct hns3_adapter *hns = dev->data->dev_private; 4146 struct hns3_hw *hw = &hns->hw; 4147 uint64_t offloads; 4148 int err; 4149 int ret; 4150 4151 rte_spinlock_lock(&hw->lock); 4152 ret = hns3_set_promisc_mode(hw, true, true); 4153 if (ret) { 4154 rte_spinlock_unlock(&hw->lock); 4155 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 4156 ret); 4157 return ret; 4158 } 4159 4160 /* 4161 * When promiscuous mode was enabled, disable the vlan filter to let 4162 * all packets coming in in the receiving direction. 4163 */ 4164 offloads = dev->data->dev_conf.rxmode.offloads; 4165 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4166 ret = hns3_enable_vlan_filter(hns, false); 4167 if (ret) { 4168 hns3_err(hw, "failed to enable promiscuous mode due to " 4169 "failure to disable vlan filter, ret = %d", 4170 ret); 4171 err = hns3_set_promisc_mode(hw, false, allmulti); 4172 if (err) 4173 hns3_err(hw, "failed to restore promiscuous " 4174 "status after disable vlan filter " 4175 "failed during enabling promiscuous " 4176 "mode, ret = %d", ret); 4177 } 4178 } 4179 4180 rte_spinlock_unlock(&hw->lock); 4181 4182 return ret; 4183 } 4184 4185 static int 4186 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 4187 { 4188 bool allmulti = dev->data->all_multicast ? true : false; 4189 struct hns3_adapter *hns = dev->data->dev_private; 4190 struct hns3_hw *hw = &hns->hw; 4191 uint64_t offloads; 4192 int err; 4193 int ret; 4194 4195 /* If now in all_multicast mode, must remain in all_multicast mode. */ 4196 rte_spinlock_lock(&hw->lock); 4197 ret = hns3_set_promisc_mode(hw, false, allmulti); 4198 if (ret) { 4199 rte_spinlock_unlock(&hw->lock); 4200 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 4201 ret); 4202 return ret; 4203 } 4204 /* when promiscuous mode was disabled, restore the vlan filter status */ 4205 offloads = dev->data->dev_conf.rxmode.offloads; 4206 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4207 ret = hns3_enable_vlan_filter(hns, true); 4208 if (ret) { 4209 hns3_err(hw, "failed to disable promiscuous mode due to" 4210 " failure to restore vlan filter, ret = %d", 4211 ret); 4212 err = hns3_set_promisc_mode(hw, true, true); 4213 if (err) 4214 hns3_err(hw, "failed to restore promiscuous " 4215 "status after enabling vlan filter " 4216 "failed during disabling promiscuous " 4217 "mode, ret = %d", ret); 4218 } 4219 } 4220 rte_spinlock_unlock(&hw->lock); 4221 4222 return ret; 4223 } 4224 4225 static int 4226 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 4227 { 4228 struct hns3_adapter *hns = dev->data->dev_private; 4229 struct hns3_hw *hw = &hns->hw; 4230 int ret; 4231 4232 if (dev->data->promiscuous) 4233 return 0; 4234 4235 rte_spinlock_lock(&hw->lock); 4236 ret = hns3_set_promisc_mode(hw, false, true); 4237 rte_spinlock_unlock(&hw->lock); 4238 if (ret) 4239 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 4240 ret); 4241 4242 return ret; 4243 } 4244 4245 static int 4246 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 4247 { 4248 struct hns3_adapter *hns = dev->data->dev_private; 4249 struct hns3_hw *hw = &hns->hw; 4250 int ret; 4251 4252 /* If now in promiscuous mode, must remain in all_multicast mode. */ 4253 if (dev->data->promiscuous) 4254 return 0; 4255 4256 rte_spinlock_lock(&hw->lock); 4257 ret = hns3_set_promisc_mode(hw, false, false); 4258 rte_spinlock_unlock(&hw->lock); 4259 if (ret) 4260 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4261 ret); 4262 4263 return ret; 4264 } 4265 4266 static int 4267 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4268 { 4269 struct hns3_hw *hw = &hns->hw; 4270 bool allmulti = hw->data->all_multicast ? true : false; 4271 int ret; 4272 4273 if (hw->data->promiscuous) { 4274 ret = hns3_set_promisc_mode(hw, true, true); 4275 if (ret) 4276 hns3_err(hw, "failed to restore promiscuous mode, " 4277 "ret = %d", ret); 4278 return ret; 4279 } 4280 4281 ret = hns3_set_promisc_mode(hw, false, allmulti); 4282 if (ret) 4283 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4284 ret); 4285 return ret; 4286 } 4287 4288 static int 4289 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed) 4290 { 4291 struct hns3_sfp_speed_cmd *resp; 4292 struct hns3_cmd_desc desc; 4293 int ret; 4294 4295 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true); 4296 resp = (struct hns3_sfp_speed_cmd *)desc.data; 4297 ret = hns3_cmd_send(hw, &desc, 1); 4298 if (ret == -EOPNOTSUPP) { 4299 hns3_err(hw, "IMP do not support get SFP speed %d", ret); 4300 return ret; 4301 } else if (ret) { 4302 hns3_err(hw, "get sfp speed failed %d", ret); 4303 return ret; 4304 } 4305 4306 *speed = resp->sfp_speed; 4307 4308 return 0; 4309 } 4310 4311 static uint8_t 4312 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4313 { 4314 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 4315 duplex = ETH_LINK_FULL_DUPLEX; 4316 4317 return duplex; 4318 } 4319 4320 static int 4321 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4322 { 4323 struct hns3_mac *mac = &hw->mac; 4324 uint32_t cur_speed = mac->link_speed; 4325 int ret; 4326 4327 duplex = hns3_check_speed_dup(duplex, speed); 4328 if (mac->link_speed == speed && mac->link_duplex == duplex) 4329 return 0; 4330 4331 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4332 if (ret) 4333 return ret; 4334 4335 mac->link_speed = speed; 4336 ret = hns3_dcb_port_shaper_cfg(hw); 4337 if (ret) { 4338 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret); 4339 mac->link_speed = cur_speed; 4340 return ret; 4341 } 4342 4343 mac->link_duplex = duplex; 4344 4345 return 0; 4346 } 4347 4348 static int 4349 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev) 4350 { 4351 struct hns3_adapter *hns = eth_dev->data->dev_private; 4352 struct hns3_hw *hw = &hns->hw; 4353 struct hns3_pf *pf = &hns->pf; 4354 uint32_t speed; 4355 int ret; 4356 4357 /* If IMP do not support get SFP/qSFP speed, return directly */ 4358 if (!pf->support_sfp_query) 4359 return 0; 4360 4361 ret = hns3_get_sfp_speed(hw, &speed); 4362 if (ret == -EOPNOTSUPP) { 4363 pf->support_sfp_query = false; 4364 return ret; 4365 } else if (ret) 4366 return ret; 4367 4368 if (speed == ETH_SPEED_NUM_NONE) 4369 return 0; /* do nothing if no SFP */ 4370 4371 /* Config full duplex for SFP */ 4372 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX); 4373 } 4374 4375 static int 4376 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4377 { 4378 struct hns3_config_mac_mode_cmd *req; 4379 struct hns3_cmd_desc desc; 4380 uint32_t loop_en = 0; 4381 uint8_t val = 0; 4382 int ret; 4383 4384 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4385 4386 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4387 if (enable) 4388 val = 1; 4389 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4390 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4391 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4392 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4393 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4394 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4395 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4396 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4397 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4398 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4399 4400 /* 4401 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4402 * when receiving frames. Otherwise, CRC will be stripped. 4403 */ 4404 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 4405 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4406 else 4407 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4408 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4409 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4410 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4411 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4412 4413 ret = hns3_cmd_send(hw, &desc, 1); 4414 if (ret) 4415 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4416 4417 return ret; 4418 } 4419 4420 static int 4421 hns3_get_mac_link_status(struct hns3_hw *hw) 4422 { 4423 struct hns3_link_status_cmd *req; 4424 struct hns3_cmd_desc desc; 4425 int link_status; 4426 int ret; 4427 4428 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4429 ret = hns3_cmd_send(hw, &desc, 1); 4430 if (ret) { 4431 hns3_err(hw, "get link status cmd failed %d", ret); 4432 return ETH_LINK_DOWN; 4433 } 4434 4435 req = (struct hns3_link_status_cmd *)desc.data; 4436 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4437 4438 return !!link_status; 4439 } 4440 4441 void 4442 hns3_update_link_status(struct hns3_hw *hw) 4443 { 4444 int state; 4445 4446 state = hns3_get_mac_link_status(hw); 4447 if (state != hw->mac.link_status) { 4448 hw->mac.link_status = state; 4449 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4450 } 4451 } 4452 4453 static void 4454 hns3_service_handler(void *param) 4455 { 4456 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4457 struct hns3_adapter *hns = eth_dev->data->dev_private; 4458 struct hns3_hw *hw = &hns->hw; 4459 4460 if (!hns3_is_reset_pending(hns)) { 4461 hns3_update_speed_duplex(eth_dev); 4462 hns3_update_link_status(hw); 4463 } else 4464 hns3_warn(hw, "Cancel the query when reset is pending"); 4465 4466 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4467 } 4468 4469 static int 4470 hns3_init_hardware(struct hns3_adapter *hns) 4471 { 4472 struct hns3_hw *hw = &hns->hw; 4473 int ret; 4474 4475 ret = hns3_map_tqp(hw); 4476 if (ret) { 4477 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4478 return ret; 4479 } 4480 4481 ret = hns3_init_umv_space(hw); 4482 if (ret) { 4483 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4484 return ret; 4485 } 4486 4487 ret = hns3_mac_init(hw); 4488 if (ret) { 4489 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4490 goto err_mac_init; 4491 } 4492 4493 ret = hns3_init_mgr_tbl(hw); 4494 if (ret) { 4495 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4496 goto err_mac_init; 4497 } 4498 4499 ret = hns3_promisc_init(hw); 4500 if (ret) { 4501 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4502 ret); 4503 goto err_mac_init; 4504 } 4505 4506 ret = hns3_init_vlan_config(hns); 4507 if (ret) { 4508 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4509 goto err_mac_init; 4510 } 4511 4512 ret = hns3_dcb_init(hw); 4513 if (ret) { 4514 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4515 goto err_mac_init; 4516 } 4517 4518 ret = hns3_init_fd_config(hns); 4519 if (ret) { 4520 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 4521 goto err_mac_init; 4522 } 4523 4524 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 4525 if (ret) { 4526 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 4527 goto err_mac_init; 4528 } 4529 4530 ret = hns3_config_gro(hw, false); 4531 if (ret) { 4532 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 4533 goto err_mac_init; 4534 } 4535 4536 /* 4537 * In the initialization clearing the all hardware mapping relationship 4538 * configurations between queues and interrupt vectors is needed, so 4539 * some error caused by the residual configurations, such as the 4540 * unexpected interrupt, can be avoid. 4541 */ 4542 ret = hns3_init_ring_with_vector(hw); 4543 if (ret) { 4544 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 4545 goto err_mac_init; 4546 } 4547 4548 return 0; 4549 4550 err_mac_init: 4551 hns3_uninit_umv_space(hw); 4552 return ret; 4553 } 4554 4555 static int 4556 hns3_clear_hw(struct hns3_hw *hw) 4557 { 4558 struct hns3_cmd_desc desc; 4559 int ret; 4560 4561 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 4562 4563 ret = hns3_cmd_send(hw, &desc, 1); 4564 if (ret && ret != -EOPNOTSUPP) 4565 return ret; 4566 4567 return 0; 4568 } 4569 4570 static void 4571 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 4572 { 4573 uint32_t val; 4574 4575 /* 4576 * The new firmware support report more hardware error types by 4577 * msix mode. These errors are defined as RAS errors in hardware 4578 * and belong to a different type from the MSI-x errors processed 4579 * by the network driver. 4580 * 4581 * Network driver should open the new error report on initialition 4582 */ 4583 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 4584 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 4585 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 4586 } 4587 4588 static int 4589 hns3_init_pf(struct rte_eth_dev *eth_dev) 4590 { 4591 struct rte_device *dev = eth_dev->device; 4592 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4593 struct hns3_adapter *hns = eth_dev->data->dev_private; 4594 struct hns3_hw *hw = &hns->hw; 4595 int ret; 4596 4597 PMD_INIT_FUNC_TRACE(); 4598 4599 /* Get hardware io base address from pcie BAR2 IO space */ 4600 hw->io_base = pci_dev->mem_resource[2].addr; 4601 4602 /* Firmware command queue initialize */ 4603 ret = hns3_cmd_init_queue(hw); 4604 if (ret) { 4605 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 4606 goto err_cmd_init_queue; 4607 } 4608 4609 hns3_clear_all_event_cause(hw); 4610 4611 /* Firmware command initialize */ 4612 ret = hns3_cmd_init(hw); 4613 if (ret) { 4614 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 4615 goto err_cmd_init; 4616 } 4617 4618 /* 4619 * To ensure that the hardware environment is clean during 4620 * initialization, the driver actively clear the hardware environment 4621 * during initialization, including PF and corresponding VFs' vlan, mac, 4622 * flow table configurations, etc. 4623 */ 4624 ret = hns3_clear_hw(hw); 4625 if (ret) { 4626 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 4627 goto err_cmd_init; 4628 } 4629 4630 hns3_config_all_msix_error(hw, true); 4631 4632 ret = rte_intr_callback_register(&pci_dev->intr_handle, 4633 hns3_interrupt_handler, 4634 eth_dev); 4635 if (ret) { 4636 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 4637 goto err_intr_callback_register; 4638 } 4639 4640 /* Enable interrupt */ 4641 rte_intr_enable(&pci_dev->intr_handle); 4642 hns3_pf_enable_irq0(hw); 4643 4644 /* Get configuration */ 4645 ret = hns3_get_configuration(hw); 4646 if (ret) { 4647 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 4648 goto err_get_config; 4649 } 4650 4651 ret = hns3_tqp_stats_init(hw); 4652 if (ret) 4653 goto err_get_config; 4654 4655 ret = hns3_init_hardware(hns); 4656 if (ret) { 4657 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 4658 goto err_init_hw; 4659 } 4660 4661 /* Initialize flow director filter list & hash */ 4662 ret = hns3_fdir_filter_init(hns); 4663 if (ret) { 4664 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 4665 goto err_fdir; 4666 } 4667 4668 hns3_set_default_rss_args(hw); 4669 4670 ret = hns3_enable_hw_error_intr(hns, true); 4671 if (ret) { 4672 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 4673 ret); 4674 goto err_enable_intr; 4675 } 4676 4677 return 0; 4678 4679 err_enable_intr: 4680 hns3_fdir_filter_uninit(hns); 4681 err_fdir: 4682 hns3_uninit_umv_space(hw); 4683 err_init_hw: 4684 hns3_tqp_stats_uninit(hw); 4685 err_get_config: 4686 hns3_pf_disable_irq0(hw); 4687 rte_intr_disable(&pci_dev->intr_handle); 4688 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 4689 eth_dev); 4690 err_intr_callback_register: 4691 err_cmd_init: 4692 hns3_cmd_uninit(hw); 4693 hns3_cmd_destroy_queue(hw); 4694 err_cmd_init_queue: 4695 hw->io_base = NULL; 4696 4697 return ret; 4698 } 4699 4700 static void 4701 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 4702 { 4703 struct hns3_adapter *hns = eth_dev->data->dev_private; 4704 struct rte_device *dev = eth_dev->device; 4705 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4706 struct hns3_hw *hw = &hns->hw; 4707 4708 PMD_INIT_FUNC_TRACE(); 4709 4710 hns3_enable_hw_error_intr(hns, false); 4711 hns3_rss_uninit(hns); 4712 (void)hns3_config_gro(hw, false); 4713 hns3_promisc_uninit(hw); 4714 hns3_fdir_filter_uninit(hns); 4715 hns3_uninit_umv_space(hw); 4716 hns3_tqp_stats_uninit(hw); 4717 hns3_pf_disable_irq0(hw); 4718 rte_intr_disable(&pci_dev->intr_handle); 4719 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 4720 eth_dev); 4721 hns3_config_all_msix_error(hw, false); 4722 hns3_cmd_uninit(hw); 4723 hns3_cmd_destroy_queue(hw); 4724 hw->io_base = NULL; 4725 } 4726 4727 static int 4728 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 4729 { 4730 struct hns3_hw *hw = &hns->hw; 4731 int ret; 4732 4733 ret = hns3_dcb_cfg_update(hns); 4734 if (ret) 4735 return ret; 4736 4737 ret = hns3_init_queues(hns, reset_queue); 4738 if (ret) { 4739 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret); 4740 return ret; 4741 } 4742 4743 ret = hns3_cfg_mac_mode(hw, true); 4744 if (ret) { 4745 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret); 4746 goto err_config_mac_mode; 4747 } 4748 return 0; 4749 4750 err_config_mac_mode: 4751 hns3_dev_release_mbufs(hns); 4752 /* 4753 * Here is exception handling, hns3_reset_all_tqps will have the 4754 * corresponding error message if it is handled incorrectly, so it is 4755 * not necessary to check hns3_reset_all_tqps return value, here keep 4756 * ret as the error code causing the exception. 4757 */ 4758 (void)hns3_reset_all_tqps(hns); 4759 return ret; 4760 } 4761 4762 static int 4763 hns3_map_rx_interrupt(struct rte_eth_dev *dev) 4764 { 4765 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4766 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4767 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4768 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 4769 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 4770 uint32_t intr_vector; 4771 uint16_t q_id; 4772 int ret; 4773 4774 if (dev->data->dev_conf.intr_conf.rxq == 0) 4775 return 0; 4776 4777 /* disable uio/vfio intr/eventfd mapping */ 4778 rte_intr_disable(intr_handle); 4779 4780 /* check and configure queue intr-vector mapping */ 4781 if (rte_intr_cap_multiple(intr_handle) || 4782 !RTE_ETH_DEV_SRIOV(dev).active) { 4783 intr_vector = hw->used_rx_queues; 4784 /* creates event fd for each intr vector when MSIX is used */ 4785 if (rte_intr_efd_enable(intr_handle, intr_vector)) 4786 return -EINVAL; 4787 } 4788 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 4789 intr_handle->intr_vec = 4790 rte_zmalloc("intr_vec", 4791 hw->used_rx_queues * sizeof(int), 0); 4792 if (intr_handle->intr_vec == NULL) { 4793 hns3_err(hw, "Failed to allocate %d rx_queues" 4794 " intr_vec", hw->used_rx_queues); 4795 ret = -ENOMEM; 4796 goto alloc_intr_vec_error; 4797 } 4798 } 4799 4800 if (rte_intr_allow_others(intr_handle)) { 4801 vec = RTE_INTR_VEC_RXTX_OFFSET; 4802 base = RTE_INTR_VEC_RXTX_OFFSET; 4803 } 4804 if (rte_intr_dp_is_en(intr_handle)) { 4805 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4806 ret = hns3_bind_ring_with_vector(hw, vec, true, 4807 HNS3_RING_TYPE_RX, 4808 q_id); 4809 if (ret) 4810 goto bind_vector_error; 4811 intr_handle->intr_vec[q_id] = vec; 4812 if (vec < base + intr_handle->nb_efd - 1) 4813 vec++; 4814 } 4815 } 4816 rte_intr_enable(intr_handle); 4817 return 0; 4818 4819 bind_vector_error: 4820 rte_intr_efd_disable(intr_handle); 4821 if (intr_handle->intr_vec) { 4822 free(intr_handle->intr_vec); 4823 intr_handle->intr_vec = NULL; 4824 } 4825 return ret; 4826 alloc_intr_vec_error: 4827 rte_intr_efd_disable(intr_handle); 4828 return ret; 4829 } 4830 4831 static int 4832 hns3_restore_rx_interrupt(struct hns3_hw *hw) 4833 { 4834 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4835 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4836 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4837 uint16_t q_id; 4838 int ret; 4839 4840 if (dev->data->dev_conf.intr_conf.rxq == 0) 4841 return 0; 4842 4843 if (rte_intr_dp_is_en(intr_handle)) { 4844 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4845 ret = hns3_bind_ring_with_vector(hw, 4846 intr_handle->intr_vec[q_id], true, 4847 HNS3_RING_TYPE_RX, q_id); 4848 if (ret) 4849 return ret; 4850 } 4851 } 4852 4853 return 0; 4854 } 4855 4856 static void 4857 hns3_restore_filter(struct rte_eth_dev *dev) 4858 { 4859 hns3_restore_rss_filter(dev); 4860 } 4861 4862 static int 4863 hns3_dev_start(struct rte_eth_dev *dev) 4864 { 4865 struct hns3_adapter *hns = dev->data->dev_private; 4866 struct hns3_hw *hw = &hns->hw; 4867 int ret; 4868 4869 PMD_INIT_FUNC_TRACE(); 4870 if (rte_atomic16_read(&hw->reset.resetting)) 4871 return -EBUSY; 4872 4873 rte_spinlock_lock(&hw->lock); 4874 hw->adapter_state = HNS3_NIC_STARTING; 4875 4876 ret = hns3_do_start(hns, true); 4877 if (ret) { 4878 hw->adapter_state = HNS3_NIC_CONFIGURED; 4879 rte_spinlock_unlock(&hw->lock); 4880 return ret; 4881 } 4882 ret = hns3_map_rx_interrupt(dev); 4883 if (ret) { 4884 hw->adapter_state = HNS3_NIC_CONFIGURED; 4885 rte_spinlock_unlock(&hw->lock); 4886 return ret; 4887 } 4888 4889 /* 4890 * There are three register used to control the status of a TQP 4891 * (contains a pair of Tx queue and Rx queue) in the new version network 4892 * engine. One is used to control the enabling of Tx queue, the other is 4893 * used to control the enabling of Rx queue, and the last is the master 4894 * switch used to control the enabling of the tqp. The Tx register and 4895 * TQP register must be enabled at the same time to enable a Tx queue. 4896 * The same applies to the Rx queue. For the older network engine, this 4897 * function only refresh the enabled flag, and it is used to update the 4898 * status of queue in the dpdk framework. 4899 */ 4900 ret = hns3_start_all_txqs(dev); 4901 if (ret) { 4902 hw->adapter_state = HNS3_NIC_CONFIGURED; 4903 rte_spinlock_unlock(&hw->lock); 4904 return ret; 4905 } 4906 4907 ret = hns3_start_all_rxqs(dev); 4908 if (ret) { 4909 hns3_stop_all_txqs(dev); 4910 hw->adapter_state = HNS3_NIC_CONFIGURED; 4911 rte_spinlock_unlock(&hw->lock); 4912 return ret; 4913 } 4914 4915 hw->adapter_state = HNS3_NIC_STARTED; 4916 rte_spinlock_unlock(&hw->lock); 4917 4918 hns3_rx_scattered_calc(dev); 4919 hns3_set_rxtx_function(dev); 4920 hns3_mp_req_start_rxtx(dev); 4921 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 4922 4923 hns3_restore_filter(dev); 4924 4925 /* Enable interrupt of all rx queues before enabling queues */ 4926 hns3_dev_all_rx_queue_intr_enable(hw, true); 4927 4928 /* 4929 * After finished the initialization, enable tqps to receive/transmit 4930 * packets and refresh all queue status. 4931 */ 4932 hns3_start_tqps(hw); 4933 4934 hns3_info(hw, "hns3 dev start successful!"); 4935 return 0; 4936 } 4937 4938 static int 4939 hns3_do_stop(struct hns3_adapter *hns) 4940 { 4941 struct hns3_hw *hw = &hns->hw; 4942 int ret; 4943 4944 ret = hns3_cfg_mac_mode(hw, false); 4945 if (ret) 4946 return ret; 4947 hw->mac.link_status = ETH_LINK_DOWN; 4948 4949 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) { 4950 hns3_configure_all_mac_addr(hns, true); 4951 ret = hns3_reset_all_tqps(hns); 4952 if (ret) { 4953 hns3_err(hw, "failed to reset all queues ret = %d.", 4954 ret); 4955 return ret; 4956 } 4957 } 4958 hw->mac.default_addr_setted = false; 4959 return 0; 4960 } 4961 4962 static void 4963 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) 4964 { 4965 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4966 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4967 struct hns3_adapter *hns = dev->data->dev_private; 4968 struct hns3_hw *hw = &hns->hw; 4969 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 4970 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 4971 uint16_t q_id; 4972 4973 if (dev->data->dev_conf.intr_conf.rxq == 0) 4974 return; 4975 4976 /* unmap the ring with vector */ 4977 if (rte_intr_allow_others(intr_handle)) { 4978 vec = RTE_INTR_VEC_RXTX_OFFSET; 4979 base = RTE_INTR_VEC_RXTX_OFFSET; 4980 } 4981 if (rte_intr_dp_is_en(intr_handle)) { 4982 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4983 (void)hns3_bind_ring_with_vector(hw, vec, false, 4984 HNS3_RING_TYPE_RX, 4985 q_id); 4986 if (vec < base + intr_handle->nb_efd - 1) 4987 vec++; 4988 } 4989 } 4990 /* Clean datapath event and queue/vec mapping */ 4991 rte_intr_efd_disable(intr_handle); 4992 if (intr_handle->intr_vec) { 4993 rte_free(intr_handle->intr_vec); 4994 intr_handle->intr_vec = NULL; 4995 } 4996 } 4997 4998 static int 4999 hns3_dev_stop(struct rte_eth_dev *dev) 5000 { 5001 struct hns3_adapter *hns = dev->data->dev_private; 5002 struct hns3_hw *hw = &hns->hw; 5003 5004 PMD_INIT_FUNC_TRACE(); 5005 dev->data->dev_started = 0; 5006 5007 hw->adapter_state = HNS3_NIC_STOPPING; 5008 hns3_set_rxtx_function(dev); 5009 rte_wmb(); 5010 /* Disable datapath on secondary process. */ 5011 hns3_mp_req_stop_rxtx(dev); 5012 /* Prevent crashes when queues are still in use. */ 5013 rte_delay_ms(hw->tqps_num); 5014 5015 rte_spinlock_lock(&hw->lock); 5016 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 5017 hns3_stop_tqps(hw); 5018 hns3_do_stop(hns); 5019 hns3_unmap_rx_interrupt(dev); 5020 hns3_dev_release_mbufs(hns); 5021 hw->adapter_state = HNS3_NIC_CONFIGURED; 5022 } 5023 hns3_rx_scattered_reset(dev); 5024 rte_eal_alarm_cancel(hns3_service_handler, dev); 5025 rte_spinlock_unlock(&hw->lock); 5026 5027 return 0; 5028 } 5029 5030 static int 5031 hns3_dev_close(struct rte_eth_dev *eth_dev) 5032 { 5033 struct hns3_adapter *hns = eth_dev->data->dev_private; 5034 struct hns3_hw *hw = &hns->hw; 5035 int ret = 0; 5036 5037 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5038 rte_free(eth_dev->process_private); 5039 eth_dev->process_private = NULL; 5040 return 0; 5041 } 5042 5043 if (hw->adapter_state == HNS3_NIC_STARTED) 5044 ret = hns3_dev_stop(eth_dev); 5045 5046 hw->adapter_state = HNS3_NIC_CLOSING; 5047 hns3_reset_abort(hns); 5048 hw->adapter_state = HNS3_NIC_CLOSED; 5049 5050 hns3_configure_all_mc_mac_addr(hns, true); 5051 hns3_remove_all_vlan_table(hns); 5052 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 5053 hns3_uninit_pf(eth_dev); 5054 hns3_free_all_queues(eth_dev); 5055 rte_free(hw->reset.wait_data); 5056 rte_free(eth_dev->process_private); 5057 eth_dev->process_private = NULL; 5058 hns3_mp_uninit_primary(); 5059 hns3_warn(hw, "Close port %d finished", hw->data->port_id); 5060 5061 return ret; 5062 } 5063 5064 static int 5065 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 5066 { 5067 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5068 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5069 5070 fc_conf->pause_time = pf->pause_time; 5071 5072 /* return fc current mode */ 5073 switch (hw->current_mode) { 5074 case HNS3_FC_FULL: 5075 fc_conf->mode = RTE_FC_FULL; 5076 break; 5077 case HNS3_FC_TX_PAUSE: 5078 fc_conf->mode = RTE_FC_TX_PAUSE; 5079 break; 5080 case HNS3_FC_RX_PAUSE: 5081 fc_conf->mode = RTE_FC_RX_PAUSE; 5082 break; 5083 case HNS3_FC_NONE: 5084 default: 5085 fc_conf->mode = RTE_FC_NONE; 5086 break; 5087 } 5088 5089 return 0; 5090 } 5091 5092 static void 5093 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode) 5094 { 5095 switch (mode) { 5096 case RTE_FC_NONE: 5097 hw->requested_mode = HNS3_FC_NONE; 5098 break; 5099 case RTE_FC_RX_PAUSE: 5100 hw->requested_mode = HNS3_FC_RX_PAUSE; 5101 break; 5102 case RTE_FC_TX_PAUSE: 5103 hw->requested_mode = HNS3_FC_TX_PAUSE; 5104 break; 5105 case RTE_FC_FULL: 5106 hw->requested_mode = HNS3_FC_FULL; 5107 break; 5108 default: 5109 hw->requested_mode = HNS3_FC_NONE; 5110 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is " 5111 "configured to RTE_FC_NONE", mode); 5112 break; 5113 } 5114 } 5115 5116 static int 5117 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 5118 { 5119 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5120 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5121 int ret; 5122 5123 if (fc_conf->high_water || fc_conf->low_water || 5124 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 5125 hns3_err(hw, "Unsupported flow control settings specified, " 5126 "high_water(%u), low_water(%u), send_xon(%u) and " 5127 "mac_ctrl_frame_fwd(%u) must be set to '0'", 5128 fc_conf->high_water, fc_conf->low_water, 5129 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 5130 return -EINVAL; 5131 } 5132 if (fc_conf->autoneg) { 5133 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 5134 return -EINVAL; 5135 } 5136 if (!fc_conf->pause_time) { 5137 hns3_err(hw, "Invalid pause time %d setting.", 5138 fc_conf->pause_time); 5139 return -EINVAL; 5140 } 5141 5142 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 5143 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 5144 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 5145 "current_fc_status = %d", hw->current_fc_status); 5146 return -EOPNOTSUPP; 5147 } 5148 5149 hns3_get_fc_mode(hw, fc_conf->mode); 5150 if (hw->requested_mode == hw->current_mode && 5151 pf->pause_time == fc_conf->pause_time) 5152 return 0; 5153 5154 rte_spinlock_lock(&hw->lock); 5155 ret = hns3_fc_enable(dev, fc_conf); 5156 rte_spinlock_unlock(&hw->lock); 5157 5158 return ret; 5159 } 5160 5161 static int 5162 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 5163 struct rte_eth_pfc_conf *pfc_conf) 5164 { 5165 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5166 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5167 uint8_t priority; 5168 int ret; 5169 5170 if (!hns3_dev_dcb_supported(hw)) { 5171 hns3_err(hw, "This port does not support dcb configurations."); 5172 return -EOPNOTSUPP; 5173 } 5174 5175 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 5176 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 5177 hns3_err(hw, "Unsupported flow control settings specified, " 5178 "high_water(%u), low_water(%u), send_xon(%u) and " 5179 "mac_ctrl_frame_fwd(%u) must be set to '0'", 5180 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 5181 pfc_conf->fc.send_xon, 5182 pfc_conf->fc.mac_ctrl_frame_fwd); 5183 return -EINVAL; 5184 } 5185 if (pfc_conf->fc.autoneg) { 5186 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 5187 return -EINVAL; 5188 } 5189 if (pfc_conf->fc.pause_time == 0) { 5190 hns3_err(hw, "Invalid pause time %d setting.", 5191 pfc_conf->fc.pause_time); 5192 return -EINVAL; 5193 } 5194 5195 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 5196 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 5197 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 5198 "current_fc_status = %d", hw->current_fc_status); 5199 return -EOPNOTSUPP; 5200 } 5201 5202 priority = pfc_conf->priority; 5203 hns3_get_fc_mode(hw, pfc_conf->fc.mode); 5204 if (hw->dcb_info.pfc_en & BIT(priority) && 5205 hw->requested_mode == hw->current_mode && 5206 pfc_conf->fc.pause_time == pf->pause_time) 5207 return 0; 5208 5209 rte_spinlock_lock(&hw->lock); 5210 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 5211 rte_spinlock_unlock(&hw->lock); 5212 5213 return ret; 5214 } 5215 5216 static int 5217 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 5218 { 5219 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5220 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5221 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 5222 int i; 5223 5224 rte_spinlock_lock(&hw->lock); 5225 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 5226 dcb_info->nb_tcs = pf->local_max_tc; 5227 else 5228 dcb_info->nb_tcs = 1; 5229 5230 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 5231 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 5232 for (i = 0; i < dcb_info->nb_tcs; i++) 5233 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 5234 5235 for (i = 0; i < hw->num_tc; i++) { 5236 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 5237 dcb_info->tc_queue.tc_txq[0][i].base = 5238 hw->tc_queue[i].tqp_offset; 5239 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 5240 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 5241 hw->tc_queue[i].tqp_count; 5242 } 5243 rte_spinlock_unlock(&hw->lock); 5244 5245 return 0; 5246 } 5247 5248 static int 5249 hns3_reinit_dev(struct hns3_adapter *hns) 5250 { 5251 struct hns3_hw *hw = &hns->hw; 5252 int ret; 5253 5254 ret = hns3_cmd_init(hw); 5255 if (ret) { 5256 hns3_err(hw, "Failed to init cmd: %d", ret); 5257 return ret; 5258 } 5259 5260 ret = hns3_reset_all_tqps(hns); 5261 if (ret) { 5262 hns3_err(hw, "Failed to reset all queues: %d", ret); 5263 return ret; 5264 } 5265 5266 ret = hns3_init_hardware(hns); 5267 if (ret) { 5268 hns3_err(hw, "Failed to init hardware: %d", ret); 5269 return ret; 5270 } 5271 5272 ret = hns3_enable_hw_error_intr(hns, true); 5273 if (ret) { 5274 hns3_err(hw, "fail to enable hw error interrupts: %d", 5275 ret); 5276 return ret; 5277 } 5278 hns3_info(hw, "Reset done, driver initialization finished."); 5279 5280 return 0; 5281 } 5282 5283 static bool 5284 is_pf_reset_done(struct hns3_hw *hw) 5285 { 5286 uint32_t val, reg, reg_bit; 5287 5288 switch (hw->reset.level) { 5289 case HNS3_IMP_RESET: 5290 reg = HNS3_GLOBAL_RESET_REG; 5291 reg_bit = HNS3_IMP_RESET_BIT; 5292 break; 5293 case HNS3_GLOBAL_RESET: 5294 reg = HNS3_GLOBAL_RESET_REG; 5295 reg_bit = HNS3_GLOBAL_RESET_BIT; 5296 break; 5297 case HNS3_FUNC_RESET: 5298 reg = HNS3_FUN_RST_ING; 5299 reg_bit = HNS3_FUN_RST_ING_B; 5300 break; 5301 case HNS3_FLR_RESET: 5302 default: 5303 hns3_err(hw, "Wait for unsupported reset level: %d", 5304 hw->reset.level); 5305 return true; 5306 } 5307 val = hns3_read_dev(hw, reg); 5308 if (hns3_get_bit(val, reg_bit)) 5309 return false; 5310 else 5311 return true; 5312 } 5313 5314 bool 5315 hns3_is_reset_pending(struct hns3_adapter *hns) 5316 { 5317 struct hns3_hw *hw = &hns->hw; 5318 enum hns3_reset_level reset; 5319 5320 hns3_check_event_cause(hns, NULL); 5321 reset = hns3_get_reset_level(hns, &hw->reset.pending); 5322 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 5323 hns3_warn(hw, "High level reset %d is pending", reset); 5324 return true; 5325 } 5326 reset = hns3_get_reset_level(hns, &hw->reset.request); 5327 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 5328 hns3_warn(hw, "High level reset %d is request", reset); 5329 return true; 5330 } 5331 return false; 5332 } 5333 5334 static int 5335 hns3_wait_hardware_ready(struct hns3_adapter *hns) 5336 { 5337 struct hns3_hw *hw = &hns->hw; 5338 struct hns3_wait_data *wait_data = hw->reset.wait_data; 5339 struct timeval tv; 5340 5341 if (wait_data->result == HNS3_WAIT_SUCCESS) 5342 return 0; 5343 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 5344 gettimeofday(&tv, NULL); 5345 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 5346 tv.tv_sec, tv.tv_usec); 5347 return -ETIME; 5348 } else if (wait_data->result == HNS3_WAIT_REQUEST) 5349 return -EAGAIN; 5350 5351 wait_data->hns = hns; 5352 wait_data->check_completion = is_pf_reset_done; 5353 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 5354 HNS3_RESET_WAIT_MS + get_timeofday_ms(); 5355 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 5356 wait_data->count = HNS3_RESET_WAIT_CNT; 5357 wait_data->result = HNS3_WAIT_REQUEST; 5358 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 5359 return -EAGAIN; 5360 } 5361 5362 static int 5363 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 5364 { 5365 struct hns3_cmd_desc desc; 5366 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 5367 5368 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 5369 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 5370 req->fun_reset_vfid = func_id; 5371 5372 return hns3_cmd_send(hw, &desc, 1); 5373 } 5374 5375 static int 5376 hns3_imp_reset_cmd(struct hns3_hw *hw) 5377 { 5378 struct hns3_cmd_desc desc; 5379 5380 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 5381 desc.data[0] = 0xeedd; 5382 5383 return hns3_cmd_send(hw, &desc, 1); 5384 } 5385 5386 static void 5387 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 5388 { 5389 struct hns3_hw *hw = &hns->hw; 5390 struct timeval tv; 5391 uint32_t val; 5392 5393 gettimeofday(&tv, NULL); 5394 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 5395 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 5396 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 5397 tv.tv_sec, tv.tv_usec); 5398 return; 5399 } 5400 5401 switch (reset_level) { 5402 case HNS3_IMP_RESET: 5403 hns3_imp_reset_cmd(hw); 5404 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 5405 tv.tv_sec, tv.tv_usec); 5406 break; 5407 case HNS3_GLOBAL_RESET: 5408 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 5409 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 5410 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 5411 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 5412 tv.tv_sec, tv.tv_usec); 5413 break; 5414 case HNS3_FUNC_RESET: 5415 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 5416 tv.tv_sec, tv.tv_usec); 5417 /* schedule again to check later */ 5418 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 5419 hns3_schedule_reset(hns); 5420 break; 5421 default: 5422 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 5423 return; 5424 } 5425 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 5426 } 5427 5428 static enum hns3_reset_level 5429 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 5430 { 5431 struct hns3_hw *hw = &hns->hw; 5432 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 5433 5434 /* Return the highest priority reset level amongst all */ 5435 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 5436 reset_level = HNS3_IMP_RESET; 5437 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 5438 reset_level = HNS3_GLOBAL_RESET; 5439 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 5440 reset_level = HNS3_FUNC_RESET; 5441 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 5442 reset_level = HNS3_FLR_RESET; 5443 5444 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 5445 return HNS3_NONE_RESET; 5446 5447 return reset_level; 5448 } 5449 5450 static void 5451 hns3_record_imp_error(struct hns3_adapter *hns) 5452 { 5453 struct hns3_hw *hw = &hns->hw; 5454 uint32_t reg_val; 5455 5456 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5457 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 5458 hns3_warn(hw, "Detected IMP RD poison!"); 5459 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); 5460 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 5461 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5462 } 5463 5464 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 5465 hns3_warn(hw, "Detected IMP CMDQ error!"); 5466 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); 5467 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 5468 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5469 } 5470 } 5471 5472 static int 5473 hns3_prepare_reset(struct hns3_adapter *hns) 5474 { 5475 struct hns3_hw *hw = &hns->hw; 5476 uint32_t reg_val; 5477 int ret; 5478 5479 switch (hw->reset.level) { 5480 case HNS3_FUNC_RESET: 5481 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 5482 if (ret) 5483 return ret; 5484 5485 /* 5486 * After performaning pf reset, it is not necessary to do the 5487 * mailbox handling or send any command to firmware, because 5488 * any mailbox handling or command to firmware is only valid 5489 * after hns3_cmd_init is called. 5490 */ 5491 rte_atomic16_set(&hw->reset.disable_cmd, 1); 5492 hw->reset.stats.request_cnt++; 5493 break; 5494 case HNS3_IMP_RESET: 5495 hns3_record_imp_error(hns); 5496 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5497 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 5498 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 5499 break; 5500 default: 5501 break; 5502 } 5503 return 0; 5504 } 5505 5506 static int 5507 hns3_set_rst_done(struct hns3_hw *hw) 5508 { 5509 struct hns3_pf_rst_done_cmd *req; 5510 struct hns3_cmd_desc desc; 5511 5512 req = (struct hns3_pf_rst_done_cmd *)desc.data; 5513 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 5514 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 5515 return hns3_cmd_send(hw, &desc, 1); 5516 } 5517 5518 static int 5519 hns3_stop_service(struct hns3_adapter *hns) 5520 { 5521 struct hns3_hw *hw = &hns->hw; 5522 struct rte_eth_dev *eth_dev; 5523 5524 eth_dev = &rte_eth_devices[hw->data->port_id]; 5525 if (hw->adapter_state == HNS3_NIC_STARTED) 5526 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 5527 hw->mac.link_status = ETH_LINK_DOWN; 5528 5529 hns3_set_rxtx_function(eth_dev); 5530 rte_wmb(); 5531 /* Disable datapath on secondary process. */ 5532 hns3_mp_req_stop_rxtx(eth_dev); 5533 rte_delay_ms(hw->tqps_num); 5534 5535 rte_spinlock_lock(&hw->lock); 5536 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 5537 hw->adapter_state == HNS3_NIC_STOPPING) { 5538 hns3_enable_all_queues(hw, false); 5539 hns3_do_stop(hns); 5540 hw->reset.mbuf_deferred_free = true; 5541 } else 5542 hw->reset.mbuf_deferred_free = false; 5543 5544 /* 5545 * It is cumbersome for hardware to pick-and-choose entries for deletion 5546 * from table space. Hence, for function reset software intervention is 5547 * required to delete the entries 5548 */ 5549 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) 5550 hns3_configure_all_mc_mac_addr(hns, true); 5551 rte_spinlock_unlock(&hw->lock); 5552 5553 return 0; 5554 } 5555 5556 static int 5557 hns3_start_service(struct hns3_adapter *hns) 5558 { 5559 struct hns3_hw *hw = &hns->hw; 5560 struct rte_eth_dev *eth_dev; 5561 5562 if (hw->reset.level == HNS3_IMP_RESET || 5563 hw->reset.level == HNS3_GLOBAL_RESET) 5564 hns3_set_rst_done(hw); 5565 eth_dev = &rte_eth_devices[hw->data->port_id]; 5566 hns3_set_rxtx_function(eth_dev); 5567 hns3_mp_req_start_rxtx(eth_dev); 5568 if (hw->adapter_state == HNS3_NIC_STARTED) { 5569 hns3_service_handler(eth_dev); 5570 5571 /* Enable interrupt of all rx queues before enabling queues */ 5572 hns3_dev_all_rx_queue_intr_enable(hw, true); 5573 /* 5574 * When finished the initialization, enable queues to receive 5575 * and transmit packets. 5576 */ 5577 hns3_enable_all_queues(hw, true); 5578 } 5579 5580 return 0; 5581 } 5582 5583 static int 5584 hns3_restore_conf(struct hns3_adapter *hns) 5585 { 5586 struct hns3_hw *hw = &hns->hw; 5587 int ret; 5588 5589 ret = hns3_configure_all_mac_addr(hns, false); 5590 if (ret) 5591 return ret; 5592 5593 ret = hns3_configure_all_mc_mac_addr(hns, false); 5594 if (ret) 5595 goto err_mc_mac; 5596 5597 ret = hns3_dev_promisc_restore(hns); 5598 if (ret) 5599 goto err_promisc; 5600 5601 ret = hns3_restore_vlan_table(hns); 5602 if (ret) 5603 goto err_promisc; 5604 5605 ret = hns3_restore_vlan_conf(hns); 5606 if (ret) 5607 goto err_promisc; 5608 5609 ret = hns3_restore_all_fdir_filter(hns); 5610 if (ret) 5611 goto err_promisc; 5612 5613 ret = hns3_restore_rx_interrupt(hw); 5614 if (ret) 5615 goto err_promisc; 5616 5617 ret = hns3_restore_gro_conf(hw); 5618 if (ret) 5619 goto err_promisc; 5620 5621 ret = hns3_restore_fec(hw); 5622 if (ret) 5623 goto err_promisc; 5624 5625 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 5626 ret = hns3_do_start(hns, false); 5627 if (ret) 5628 goto err_promisc; 5629 hns3_info(hw, "hns3 dev restart successful!"); 5630 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 5631 hw->adapter_state = HNS3_NIC_CONFIGURED; 5632 return 0; 5633 5634 err_promisc: 5635 hns3_configure_all_mc_mac_addr(hns, true); 5636 err_mc_mac: 5637 hns3_configure_all_mac_addr(hns, true); 5638 return ret; 5639 } 5640 5641 static void 5642 hns3_reset_service(void *param) 5643 { 5644 struct hns3_adapter *hns = (struct hns3_adapter *)param; 5645 struct hns3_hw *hw = &hns->hw; 5646 enum hns3_reset_level reset_level; 5647 struct timeval tv_delta; 5648 struct timeval tv_start; 5649 struct timeval tv; 5650 uint64_t msec; 5651 int ret; 5652 5653 /* 5654 * The interrupt is not triggered within the delay time. 5655 * The interrupt may have been lost. It is necessary to handle 5656 * the interrupt to recover from the error. 5657 */ 5658 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) { 5659 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); 5660 hns3_err(hw, "Handling interrupts in delayed tasks"); 5661 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 5662 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5663 if (reset_level == HNS3_NONE_RESET) { 5664 hns3_err(hw, "No reset level is set, try IMP reset"); 5665 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 5666 } 5667 } 5668 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); 5669 5670 /* 5671 * Check if there is any ongoing reset in the hardware. This status can 5672 * be checked from reset_pending. If there is then, we need to wait for 5673 * hardware to complete reset. 5674 * a. If we are able to figure out in reasonable time that hardware 5675 * has fully resetted then, we can proceed with driver, client 5676 * reset. 5677 * b. else, we can come back later to check this status so re-sched 5678 * now. 5679 */ 5680 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5681 if (reset_level != HNS3_NONE_RESET) { 5682 gettimeofday(&tv_start, NULL); 5683 ret = hns3_reset_process(hns, reset_level); 5684 gettimeofday(&tv, NULL); 5685 timersub(&tv, &tv_start, &tv_delta); 5686 msec = tv_delta.tv_sec * MSEC_PER_SEC + 5687 tv_delta.tv_usec / USEC_PER_MSEC; 5688 if (msec > HNS3_RESET_PROCESS_MS) 5689 hns3_err(hw, "%d handle long time delta %" PRIx64 5690 " ms time=%ld.%.6ld", 5691 hw->reset.level, msec, 5692 tv.tv_sec, tv.tv_usec); 5693 if (ret == -EAGAIN) 5694 return; 5695 } 5696 5697 /* Check if we got any *new* reset requests to be honored */ 5698 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 5699 if (reset_level != HNS3_NONE_RESET) 5700 hns3_msix_process(hns, reset_level); 5701 } 5702 5703 static unsigned int 5704 hns3_get_speed_capa_num(uint16_t device_id) 5705 { 5706 unsigned int num; 5707 5708 switch (device_id) { 5709 case HNS3_DEV_ID_25GE: 5710 case HNS3_DEV_ID_25GE_RDMA: 5711 num = 2; 5712 break; 5713 case HNS3_DEV_ID_100G_RDMA_MACSEC: 5714 case HNS3_DEV_ID_200G_RDMA: 5715 num = 1; 5716 break; 5717 default: 5718 num = 0; 5719 break; 5720 } 5721 5722 return num; 5723 } 5724 5725 static int 5726 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, 5727 uint16_t device_id) 5728 { 5729 switch (device_id) { 5730 case HNS3_DEV_ID_25GE: 5731 /* fallthrough */ 5732 case HNS3_DEV_ID_25GE_RDMA: 5733 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed; 5734 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa; 5735 5736 /* In HNS3 device, the 25G NIC is compatible with 10G rate */ 5737 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed; 5738 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa; 5739 break; 5740 case HNS3_DEV_ID_100G_RDMA_MACSEC: 5741 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed; 5742 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa; 5743 break; 5744 case HNS3_DEV_ID_200G_RDMA: 5745 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed; 5746 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa; 5747 break; 5748 default: 5749 return -ENOTSUP; 5750 } 5751 5752 return 0; 5753 } 5754 5755 static int 5756 hns3_fec_get_capability(struct rte_eth_dev *dev, 5757 struct rte_eth_fec_capa *speed_fec_capa, 5758 unsigned int num) 5759 { 5760 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5761 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5762 uint16_t device_id = pci_dev->id.device_id; 5763 unsigned int capa_num; 5764 int ret; 5765 5766 capa_num = hns3_get_speed_capa_num(device_id); 5767 if (capa_num == 0) { 5768 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD", 5769 device_id); 5770 return -ENOTSUP; 5771 } 5772 5773 if (speed_fec_capa == NULL || num < capa_num) 5774 return capa_num; 5775 5776 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id); 5777 if (ret) 5778 return -ENOTSUP; 5779 5780 return capa_num; 5781 } 5782 5783 static int 5784 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state) 5785 { 5786 struct hns3_config_fec_cmd *req; 5787 struct hns3_cmd_desc desc; 5788 int ret; 5789 5790 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true); 5791 req = (struct hns3_config_fec_cmd *)desc.data; 5792 ret = hns3_cmd_send(hw, &desc, 1); 5793 if (ret) { 5794 hns3_err(hw, "get current fec auto state failed, ret = %d", 5795 ret); 5796 return ret; 5797 } 5798 5799 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B); 5800 return 0; 5801 } 5802 5803 static int 5804 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 5805 { 5806 #define QUERY_ACTIVE_SPEED 1 5807 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5808 struct hns3_sfp_speed_cmd *resp; 5809 uint32_t tmp_fec_capa; 5810 uint8_t auto_state; 5811 struct hns3_cmd_desc desc; 5812 int ret; 5813 5814 /* 5815 * If link is down and AUTO is enabled, AUTO is returned, otherwise, 5816 * configured FEC mode is returned. 5817 * If link is up, current FEC mode is returned. 5818 */ 5819 if (hw->mac.link_status == ETH_LINK_DOWN) { 5820 ret = get_current_fec_auto_state(hw, &auto_state); 5821 if (ret) 5822 return ret; 5823 5824 if (auto_state == 0x1) { 5825 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 5826 return 0; 5827 } 5828 } 5829 5830 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true); 5831 resp = (struct hns3_sfp_speed_cmd *)desc.data; 5832 resp->query_type = QUERY_ACTIVE_SPEED; 5833 5834 ret = hns3_cmd_send(hw, &desc, 1); 5835 if (ret == -EOPNOTSUPP) { 5836 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret); 5837 return ret; 5838 } else if (ret) { 5839 hns3_err(hw, "get FEC failed, ret = %d", ret); 5840 return ret; 5841 } 5842 5843 /* 5844 * FEC mode order defined in hns3 hardware is inconsistend with 5845 * that defined in the ethdev library. So the sequence needs 5846 * to be converted. 5847 */ 5848 switch (resp->active_fec) { 5849 case HNS3_HW_FEC_MODE_NOFEC: 5850 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 5851 break; 5852 case HNS3_HW_FEC_MODE_BASER: 5853 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 5854 break; 5855 case HNS3_HW_FEC_MODE_RS: 5856 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 5857 break; 5858 default: 5859 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 5860 break; 5861 } 5862 5863 *fec_capa = tmp_fec_capa; 5864 return 0; 5865 } 5866 5867 static int 5868 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode) 5869 { 5870 struct hns3_config_fec_cmd *req; 5871 struct hns3_cmd_desc desc; 5872 int ret; 5873 5874 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false); 5875 5876 req = (struct hns3_config_fec_cmd *)desc.data; 5877 switch (mode) { 5878 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC): 5879 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 5880 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF); 5881 break; 5882 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER): 5883 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 5884 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER); 5885 break; 5886 case RTE_ETH_FEC_MODE_CAPA_MASK(RS): 5887 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 5888 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS); 5889 break; 5890 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO): 5891 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1); 5892 break; 5893 default: 5894 return 0; 5895 } 5896 ret = hns3_cmd_send(hw, &desc, 1); 5897 if (ret) 5898 hns3_err(hw, "set fec mode failed, ret = %d", ret); 5899 5900 return ret; 5901 } 5902 5903 static uint32_t 5904 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa) 5905 { 5906 struct hns3_mac *mac = &hw->mac; 5907 uint32_t cur_capa; 5908 5909 switch (mac->link_speed) { 5910 case ETH_SPEED_NUM_10G: 5911 cur_capa = fec_capa[1].capa; 5912 break; 5913 case ETH_SPEED_NUM_25G: 5914 case ETH_SPEED_NUM_100G: 5915 case ETH_SPEED_NUM_200G: 5916 cur_capa = fec_capa[0].capa; 5917 break; 5918 default: 5919 cur_capa = 0; 5920 break; 5921 } 5922 5923 return cur_capa; 5924 } 5925 5926 static bool 5927 is_fec_mode_one_bit_set(uint32_t mode) 5928 { 5929 int cnt = 0; 5930 uint8_t i; 5931 5932 for (i = 0; i < sizeof(mode); i++) 5933 if (mode >> i & 0x1) 5934 cnt++; 5935 5936 return cnt == 1 ? true : false; 5937 } 5938 5939 static int 5940 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) 5941 { 5942 #define FEC_CAPA_NUM 2 5943 struct hns3_adapter *hns = dev->data->dev_private; 5944 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 5945 struct hns3_pf *pf = &hns->pf; 5946 5947 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM]; 5948 uint32_t cur_capa; 5949 uint32_t num = FEC_CAPA_NUM; 5950 int ret; 5951 5952 ret = hns3_fec_get_capability(dev, fec_capa, num); 5953 if (ret < 0) 5954 return ret; 5955 5956 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */ 5957 if (!is_fec_mode_one_bit_set(mode)) 5958 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD," 5959 "FEC mode should be only one bit set", mode); 5960 5961 /* 5962 * Check whether the configured mode is within the FEC capability. 5963 * If not, the configured mode will not be supported. 5964 */ 5965 cur_capa = get_current_speed_fec_cap(hw, fec_capa); 5966 if (!(cur_capa & mode)) { 5967 hns3_err(hw, "unsupported FEC mode = 0x%x", mode); 5968 return -EINVAL; 5969 } 5970 5971 ret = hns3_set_fec_hw(hw, mode); 5972 if (ret) 5973 return ret; 5974 5975 pf->fec_mode = mode; 5976 return 0; 5977 } 5978 5979 static int 5980 hns3_restore_fec(struct hns3_hw *hw) 5981 { 5982 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 5983 struct hns3_pf *pf = &hns->pf; 5984 uint32_t mode = pf->fec_mode; 5985 int ret; 5986 5987 ret = hns3_set_fec_hw(hw, mode); 5988 if (ret) 5989 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d", 5990 mode, ret); 5991 5992 return ret; 5993 } 5994 5995 static int 5996 hns3_query_dev_fec_info(struct rte_eth_dev *dev) 5997 { 5998 struct hns3_adapter *hns = dev->data->dev_private; 5999 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6000 struct hns3_pf *pf = &hns->pf; 6001 int ret; 6002 6003 ret = hns3_fec_get(dev, &pf->fec_mode); 6004 if (ret) 6005 hns3_err(hw, "query device FEC info failed, ret = %d", ret); 6006 6007 return ret; 6008 } 6009 6010 static const struct eth_dev_ops hns3_eth_dev_ops = { 6011 .dev_configure = hns3_dev_configure, 6012 .dev_start = hns3_dev_start, 6013 .dev_stop = hns3_dev_stop, 6014 .dev_close = hns3_dev_close, 6015 .promiscuous_enable = hns3_dev_promiscuous_enable, 6016 .promiscuous_disable = hns3_dev_promiscuous_disable, 6017 .allmulticast_enable = hns3_dev_allmulticast_enable, 6018 .allmulticast_disable = hns3_dev_allmulticast_disable, 6019 .mtu_set = hns3_dev_mtu_set, 6020 .stats_get = hns3_stats_get, 6021 .stats_reset = hns3_stats_reset, 6022 .xstats_get = hns3_dev_xstats_get, 6023 .xstats_get_names = hns3_dev_xstats_get_names, 6024 .xstats_reset = hns3_dev_xstats_reset, 6025 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 6026 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 6027 .dev_infos_get = hns3_dev_infos_get, 6028 .fw_version_get = hns3_fw_version_get, 6029 .rx_queue_setup = hns3_rx_queue_setup, 6030 .tx_queue_setup = hns3_tx_queue_setup, 6031 .rx_queue_release = hns3_dev_rx_queue_release, 6032 .tx_queue_release = hns3_dev_tx_queue_release, 6033 .rx_queue_start = hns3_dev_rx_queue_start, 6034 .rx_queue_stop = hns3_dev_rx_queue_stop, 6035 .tx_queue_start = hns3_dev_tx_queue_start, 6036 .tx_queue_stop = hns3_dev_tx_queue_stop, 6037 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 6038 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 6039 .rxq_info_get = hns3_rxq_info_get, 6040 .txq_info_get = hns3_txq_info_get, 6041 .rx_burst_mode_get = hns3_rx_burst_mode_get, 6042 .tx_burst_mode_get = hns3_tx_burst_mode_get, 6043 .flow_ctrl_get = hns3_flow_ctrl_get, 6044 .flow_ctrl_set = hns3_flow_ctrl_set, 6045 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 6046 .mac_addr_add = hns3_add_mac_addr, 6047 .mac_addr_remove = hns3_remove_mac_addr, 6048 .mac_addr_set = hns3_set_default_mac_addr, 6049 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 6050 .link_update = hns3_dev_link_update, 6051 .rss_hash_update = hns3_dev_rss_hash_update, 6052 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 6053 .reta_update = hns3_dev_rss_reta_update, 6054 .reta_query = hns3_dev_rss_reta_query, 6055 .filter_ctrl = hns3_dev_filter_ctrl, 6056 .vlan_filter_set = hns3_vlan_filter_set, 6057 .vlan_tpid_set = hns3_vlan_tpid_set, 6058 .vlan_offload_set = hns3_vlan_offload_set, 6059 .vlan_pvid_set = hns3_vlan_pvid_set, 6060 .get_reg = hns3_get_regs, 6061 .get_dcb_info = hns3_get_dcb_info, 6062 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 6063 .fec_get_capability = hns3_fec_get_capability, 6064 .fec_get = hns3_fec_get, 6065 .fec_set = hns3_fec_set, 6066 }; 6067 6068 static const struct hns3_reset_ops hns3_reset_ops = { 6069 .reset_service = hns3_reset_service, 6070 .stop_service = hns3_stop_service, 6071 .prepare_reset = hns3_prepare_reset, 6072 .wait_hardware_ready = hns3_wait_hardware_ready, 6073 .reinit_dev = hns3_reinit_dev, 6074 .restore_conf = hns3_restore_conf, 6075 .start_service = hns3_start_service, 6076 }; 6077 6078 static int 6079 hns3_dev_init(struct rte_eth_dev *eth_dev) 6080 { 6081 struct hns3_adapter *hns = eth_dev->data->dev_private; 6082 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 6083 struct rte_ether_addr *eth_addr; 6084 struct hns3_hw *hw = &hns->hw; 6085 int ret; 6086 6087 PMD_INIT_FUNC_TRACE(); 6088 6089 eth_dev->process_private = (struct hns3_process_private *) 6090 rte_zmalloc_socket("hns3_filter_list", 6091 sizeof(struct hns3_process_private), 6092 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 6093 if (eth_dev->process_private == NULL) { 6094 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 6095 return -ENOMEM; 6096 } 6097 /* initialize flow filter lists */ 6098 hns3_filterlist_init(eth_dev); 6099 6100 hns3_set_rxtx_function(eth_dev); 6101 eth_dev->dev_ops = &hns3_eth_dev_ops; 6102 eth_dev->rx_queue_count = hns3_rx_queue_count; 6103 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 6104 ret = hns3_mp_init_secondary(); 6105 if (ret) { 6106 PMD_INIT_LOG(ERR, "Failed to init for secondary " 6107 "process, ret = %d", ret); 6108 goto err_mp_init_secondary; 6109 } 6110 6111 hw->secondary_cnt++; 6112 return 0; 6113 } 6114 6115 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 6116 6117 ret = hns3_mp_init_primary(); 6118 if (ret) { 6119 PMD_INIT_LOG(ERR, 6120 "Failed to init for primary process, ret = %d", 6121 ret); 6122 goto err_mp_init_primary; 6123 } 6124 6125 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 6126 hns->is_vf = false; 6127 hw->data = eth_dev->data; 6128 6129 /* 6130 * Set default max packet size according to the mtu 6131 * default vale in DPDK frame. 6132 */ 6133 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 6134 6135 ret = hns3_reset_init(hw); 6136 if (ret) 6137 goto err_init_reset; 6138 hw->reset.ops = &hns3_reset_ops; 6139 6140 ret = hns3_init_pf(eth_dev); 6141 if (ret) { 6142 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 6143 goto err_init_pf; 6144 } 6145 6146 /* Allocate memory for storing MAC addresses */ 6147 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 6148 sizeof(struct rte_ether_addr) * 6149 HNS3_UC_MACADDR_NUM, 0); 6150 if (eth_dev->data->mac_addrs == NULL) { 6151 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 6152 "to store MAC addresses", 6153 sizeof(struct rte_ether_addr) * 6154 HNS3_UC_MACADDR_NUM); 6155 ret = -ENOMEM; 6156 goto err_rte_zmalloc; 6157 } 6158 6159 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 6160 if (!rte_is_valid_assigned_ether_addr(eth_addr)) { 6161 rte_eth_random_addr(hw->mac.mac_addr); 6162 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 6163 (struct rte_ether_addr *)hw->mac.mac_addr); 6164 hns3_warn(hw, "default mac_addr from firmware is an invalid " 6165 "unicast address, using random MAC address %s", 6166 mac_str); 6167 } 6168 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 6169 ð_dev->data->mac_addrs[0]); 6170 6171 hw->adapter_state = HNS3_NIC_INITIALIZED; 6172 6173 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) { 6174 hns3_err(hw, "Reschedule reset service after dev_init"); 6175 hns3_schedule_reset(hns); 6176 } else { 6177 /* IMP will wait ready flag before reset */ 6178 hns3_notify_reset_ready(hw, false); 6179 } 6180 6181 hns3_info(hw, "hns3 dev initialization successful!"); 6182 return 0; 6183 6184 err_rte_zmalloc: 6185 hns3_uninit_pf(eth_dev); 6186 6187 err_init_pf: 6188 rte_free(hw->reset.wait_data); 6189 6190 err_init_reset: 6191 hns3_mp_uninit_primary(); 6192 6193 err_mp_init_primary: 6194 err_mp_init_secondary: 6195 eth_dev->dev_ops = NULL; 6196 eth_dev->rx_pkt_burst = NULL; 6197 eth_dev->tx_pkt_burst = NULL; 6198 eth_dev->tx_pkt_prepare = NULL; 6199 rte_free(eth_dev->process_private); 6200 eth_dev->process_private = NULL; 6201 return ret; 6202 } 6203 6204 static int 6205 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 6206 { 6207 struct hns3_adapter *hns = eth_dev->data->dev_private; 6208 struct hns3_hw *hw = &hns->hw; 6209 6210 PMD_INIT_FUNC_TRACE(); 6211 6212 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6213 return -EPERM; 6214 6215 if (hw->adapter_state < HNS3_NIC_CLOSING) 6216 hns3_dev_close(eth_dev); 6217 6218 hw->adapter_state = HNS3_NIC_REMOVED; 6219 return 0; 6220 } 6221 6222 static int 6223 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6224 struct rte_pci_device *pci_dev) 6225 { 6226 return rte_eth_dev_pci_generic_probe(pci_dev, 6227 sizeof(struct hns3_adapter), 6228 hns3_dev_init); 6229 } 6230 6231 static int 6232 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 6233 { 6234 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 6235 } 6236 6237 static const struct rte_pci_id pci_id_hns3_map[] = { 6238 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 6239 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 6240 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 6241 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 6242 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 6243 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 6244 { .vendor_id = 0, }, /* sentinel */ 6245 }; 6246 6247 static struct rte_pci_driver rte_hns3_pmd = { 6248 .id_table = pci_id_hns3_map, 6249 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 6250 .probe = eth_hns3_pci_probe, 6251 .remove = eth_hns3_pci_remove, 6252 }; 6253 6254 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 6255 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 6256 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 6257 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); 6258 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); 6259